Benoît Locher / mbedNet

Rewrite from scratch a TCP/IP stack for mbed. So far the following parts are usable: Drivers: - EMAC driver (from CMSIS 2.0) Protocols: - Ethernet protocol - ARP over ethernet for IPv4 - IPv4 over Ethernet - ICMPv4 over IPv4 - UDPv4 over IPv4 APIs: - Sockets for UDPv4 The structure of this stack is designed to be very modular. Each protocol can register one or more protocol to handle its payload, and in each protocol, an API can be hooked (like Sockets for example). This is an early release.

lpc17xx_emac.h@7:8e12f7357b9f, 2011-06-26 (annotated)

Committer:
Benoit
Date:
Sun Jun 26 09:56:31 2011 +0000
Revision:
7:8e12f7357b9f
Parent:
5:3cd83fcb1467 
Added IPv4 global broadcast address to processed frames inside IPv4 layer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Benoit 4:cb3dc3361be5 1 /* @cond */
Benoit 0:19f5f51584de 2 /***********************************************************************//**
Benoit 0:19f5f51584de 3 * @file lpc17xx_emac.h
Benoit 0:19f5f51584de 4 * @brief Contains all macro definitions and function prototypes
Benoit 0:19f5f51584de 5 * support for Ethernet MAC firmware library on LPC17xx
Benoit 0:19f5f51584de 6 * @version 2.0
Benoit 0:19f5f51584de 7 * @date 21. May. 2010
Benoit 0:19f5f51584de 8 * @author NXP MCU SW Application Team
Benoit 0:19f5f51584de 9 **************************************************************************
Benoit 0:19f5f51584de 10 * Software that is described herein is for illustrative purposes only
Benoit 0:19f5f51584de 11 * which provides customers with programming information regarding the
Benoit 0:19f5f51584de 12 * products. This software is supplied "AS IS" without any warranties.
Benoit 0:19f5f51584de 13 * NXP Semiconductors assumes no responsibility or liability for the
Benoit 0:19f5f51584de 14 * use of the software, conveys no license or title under any patent,
Benoit 0:19f5f51584de 15 * copyright, or mask work right to the product. NXP Semiconductors
Benoit 0:19f5f51584de 16 * reserves the right to make changes in the software without
Benoit 0:19f5f51584de 17 * notification. NXP Semiconductors also make no representation or
Benoit 0:19f5f51584de 18 * warranty that such application will be suitable for the specified
Benoit 0:19f5f51584de 19 * use without further testing or modification.
Benoit 0:19f5f51584de 20 **************************************************************************/
Benoit 0:19f5f51584de 21
Benoit 0:19f5f51584de 22 /* Peripheral group ----------------------------------------------------------- */
Benoit 0:19f5f51584de 23 /** @defgroup EMAC EMAC
Benoit 0:19f5f51584de 24 * @ingroup LPC1700CMSIS_FwLib_Drivers
Benoit 0:19f5f51584de 25 * @{
Benoit 0:19f5f51584de 26 */
Benoit 0:19f5f51584de 27
Benoit 0:19f5f51584de 28 #ifndef LPC17XX_EMAC_H_
Benoit 0:19f5f51584de 29 #define LPC17XX_EMAC_H_
Benoit 0:19f5f51584de 30
Benoit 0:19f5f51584de 31 /* Includes ------------------------------------------------------------------- */
Benoit 0:19f5f51584de 32 #include "LPC17xx.h"
Benoit 0:19f5f51584de 33 #include "lpc_types.h"
Benoit 0:19f5f51584de 34
Benoit 0:19f5f51584de 35
Benoit 0:19f5f51584de 36 #ifdef __cplusplus
Benoit 0:19f5f51584de 37 extern "C"
Benoit 0:19f5f51584de 38 {
Benoit 0:19f5f51584de 39 #endif
Benoit 0:19f5f51584de 40
Benoit 0:19f5f51584de 41 #define MCB_LPC_1768
Benoit 0:19f5f51584de 42 //#define IAR_LPC_1768
Benoit 0:19f5f51584de 43
Benoit 0:19f5f51584de 44 /* Public Macros -------------------------------------------------------------- */
Benoit 0:19f5f51584de 45 /** @defgroup EMAC_Public_Macros EMAC Public Macros
Benoit 0:19f5f51584de 46 * @{
Benoit 0:19f5f51584de 47 */
Benoit 0:19f5f51584de 48
Benoit 0:19f5f51584de 49
Benoit 0:19f5f51584de 50 /* EMAC PHY status type definitions */
Benoit 0:19f5f51584de 51 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
Benoit 0:19f5f51584de 52 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
Benoit 0:19f5f51584de 53 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
Benoit 0:19f5f51584de 54
Benoit 0:19f5f51584de 55 /* EMAC PHY device Speed definitions */
Benoit 0:19f5f51584de 56 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
Benoit 0:19f5f51584de 57 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
Benoit 0:19f5f51584de 58 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
Benoit 0:19f5f51584de 59 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
Benoit 0:19f5f51584de 60 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
Benoit 0:19f5f51584de 61
Benoit 0:19f5f51584de 62 /**
Benoit 0:19f5f51584de 63 * @}
Benoit 0:19f5f51584de 64 */
Benoit 0:19f5f51584de 65 /* Private Macros ------------------------------------------------------------- */
Benoit 0:19f5f51584de 66 /** @defgroup EMAC_Private_Macros EMAC Private Macros
Benoit 0:19f5f51584de 67 * @{
Benoit 0:19f5f51584de 68 */
Benoit 0:19f5f51584de 69
Benoit 0:19f5f51584de 70
Benoit 0:19f5f51584de 71 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
Benoit 1:f4040665bc61 72 #define EMAC_NUM_RX_FRAG 6 /**< Num.of RX Fragments 6*1536= 9kB */
Benoit 1:f4040665bc61 73 #define EMAC_NUM_TX_FRAG 4 /**< Num.of TX Fragments 4*1536= 6kB */
Benoit 0:19f5f51584de 74 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
Benoit 0:19f5f51584de 75 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
Benoit 0:19f5f51584de 76
Benoit 0:19f5f51584de 77 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Benoit 0:19f5f51584de 78 /*********************************************************************//**
Benoit 0:19f5f51584de 79 * Macro defines for MAC Configuration Register 1
Benoit 0:19f5f51584de 80 **********************************************************************/
Benoit 0:19f5f51584de 81 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
Benoit 0:19f5f51584de 82 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
Benoit 0:19f5f51584de 83 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
Benoit 0:19f5f51584de 84 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
Benoit 0:19f5f51584de 85 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
Benoit 0:19f5f51584de 86 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
Benoit 0:19f5f51584de 87 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
Benoit 0:19f5f51584de 88 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
Benoit 0:19f5f51584de 89 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
Benoit 0:19f5f51584de 90 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
Benoit 0:19f5f51584de 91 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
Benoit 0:19f5f51584de 92
Benoit 0:19f5f51584de 93 /*********************************************************************//**
Benoit 0:19f5f51584de 94 * Macro defines for MAC Configuration Register 2
Benoit 0:19f5f51584de 95 **********************************************************************/
Benoit 0:19f5f51584de 96 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
Benoit 0:19f5f51584de 97 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
Benoit 0:19f5f51584de 98 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
Benoit 0:19f5f51584de 99 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
Benoit 0:19f5f51584de 100 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
Benoit 0:19f5f51584de 101 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
Benoit 0:19f5f51584de 102 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
Benoit 0:19f5f51584de 103 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
Benoit 0:19f5f51584de 104 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
Benoit 0:19f5f51584de 105 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
Benoit 0:19f5f51584de 106 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
Benoit 0:19f5f51584de 107 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
Benoit 0:19f5f51584de 108 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
Benoit 0:19f5f51584de 109
Benoit 0:19f5f51584de 110 /*********************************************************************//**
Benoit 0:19f5f51584de 111 * Macro defines for Back-to-Back Inter-Packet-Gap Register
Benoit 0:19f5f51584de 112 **********************************************************************/
Benoit 0:19f5f51584de 113 /** Programmable field representing the nibble time offset of the minimum possible period
Benoit 0:19f5f51584de 114 * between the end of any transmitted packet to the beginning of the next */
Benoit 0:19f5f51584de 115 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
Benoit 0:19f5f51584de 116 /** Recommended value for Full Duplex of Programmable field representing the nibble time
Benoit 0:19f5f51584de 117 * offset of the minimum possible period between the end of any transmitted packet to the
Benoit 0:19f5f51584de 118 * beginning of the next */
Benoit 0:19f5f51584de 119 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
Benoit 0:19f5f51584de 120 /** Recommended value for Half Duplex of Programmable field representing the nibble time
Benoit 0:19f5f51584de 121 * offset of the minimum possible period between the end of any transmitted packet to the
Benoit 0:19f5f51584de 122 * beginning of the next */
Benoit 0:19f5f51584de 123 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
Benoit 0:19f5f51584de 124
Benoit 0:19f5f51584de 125 /*********************************************************************//**
Benoit 0:19f5f51584de 126 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
Benoit 0:19f5f51584de 127 **********************************************************************/
Benoit 0:19f5f51584de 128 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
Benoit 0:19f5f51584de 129 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
Benoit 0:19f5f51584de 130 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
Benoit 0:19f5f51584de 131 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
Benoit 0:19f5f51584de 132 /** Programmable field representing the optional carrierSense window referenced in
Benoit 0:19f5f51584de 133 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
Benoit 0:19f5f51584de 134 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
Benoit 0:19f5f51584de 135 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
Benoit 0:19f5f51584de 136 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
Benoit 0:19f5f51584de 137
Benoit 0:19f5f51584de 138 /*********************************************************************//**
Benoit 0:19f5f51584de 139 * Macro defines for Collision Window/Retry Register
Benoit 0:19f5f51584de 140 **********************************************************************/
Benoit 0:19f5f51584de 141 /** Programmable field specifying the number of retransmission attempts following a collision before
Benoit 0:19f5f51584de 142 * aborting the packet due to excessive collisions */
Benoit 0:19f5f51584de 143 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
Benoit 0:19f5f51584de 144 /** Programmable field representing the slot time or collision window during which collisions occur
Benoit 0:19f5f51584de 145 * in properly configured networks */
Benoit 0:19f5f51584de 146 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
Benoit 0:19f5f51584de 147 /** Default value for Collision Window / Retry register */
Benoit 0:19f5f51584de 148 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
Benoit 0:19f5f51584de 149
Benoit 0:19f5f51584de 150 /*********************************************************************//**
Benoit 0:19f5f51584de 151 * Macro defines for Maximum Frame Register
Benoit 0:19f5f51584de 152 **********************************************************************/
Benoit 0:19f5f51584de 153 /** Represents a maximum receive frame of 1536 octets */
Benoit 0:19f5f51584de 154 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
Benoit 0:19f5f51584de 155
Benoit 0:19f5f51584de 156 /*********************************************************************//**
Benoit 0:19f5f51584de 157 * Macro defines for PHY Support Register
Benoit 0:19f5f51584de 158 **********************************************************************/
Benoit 0:19f5f51584de 159 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
Benoit 0:19f5f51584de 160 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
Benoit 0:19f5f51584de 161
Benoit 0:19f5f51584de 162 /*********************************************************************//**
Benoit 0:19f5f51584de 163 * Macro defines for Test Register
Benoit 0:19f5f51584de 164 **********************************************************************/
Benoit 0:19f5f51584de 165 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
Benoit 0:19f5f51584de 166 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
Benoit 0:19f5f51584de 167 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
Benoit 0:19f5f51584de 168
Benoit 0:19f5f51584de 169 /*********************************************************************//**
Benoit 0:19f5f51584de 170 * Macro defines for MII Management Configuration Register
Benoit 0:19f5f51584de 171 **********************************************************************/
Benoit 0:19f5f51584de 172 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
Benoit 0:19f5f51584de 173 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
Benoit 0:19f5f51584de 174 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
Benoit 0:19f5f51584de 175 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
Benoit 0:19f5f51584de 176 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
Benoit 0:19f5f51584de 177
Benoit 0:19f5f51584de 178 /*********************************************************************//**
Benoit 0:19f5f51584de 179 * Macro defines for MII Management Command Register
Benoit 0:19f5f51584de 180 **********************************************************************/
Benoit 0:19f5f51584de 181 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
Benoit 0:19f5f51584de 182 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
Benoit 0:19f5f51584de 183
Benoit 0:19f5f51584de 184 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
Benoit 0:19f5f51584de 185 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
Benoit 0:19f5f51584de 186
Benoit 0:19f5f51584de 187 /*********************************************************************//**
Benoit 0:19f5f51584de 188 * Macro defines for MII Management Address Register
Benoit 0:19f5f51584de 189 **********************************************************************/
Benoit 0:19f5f51584de 190 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
Benoit 0:19f5f51584de 191 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
Benoit 0:19f5f51584de 192
Benoit 0:19f5f51584de 193 /*********************************************************************//**
Benoit 0:19f5f51584de 194 * Macro defines for MII Management Write Data Register
Benoit 0:19f5f51584de 195 **********************************************************************/
Benoit 0:19f5f51584de 196 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
Benoit 0:19f5f51584de 197
Benoit 0:19f5f51584de 198 /*********************************************************************//**
Benoit 0:19f5f51584de 199 * Macro defines for MII Management Read Data Register
Benoit 0:19f5f51584de 200 **********************************************************************/
Benoit 0:19f5f51584de 201 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
Benoit 0:19f5f51584de 202
Benoit 0:19f5f51584de 203 /*********************************************************************//**
Benoit 0:19f5f51584de 204 * Macro defines for MII Management Indicators Register
Benoit 0:19f5f51584de 205 **********************************************************************/
Benoit 0:19f5f51584de 206 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
Benoit 0:19f5f51584de 207 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
Benoit 0:19f5f51584de 208 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
Benoit 0:19f5f51584de 209 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
Benoit 0:19f5f51584de 210
Benoit 0:19f5f51584de 211 /* Station Address 0 Register */
Benoit 0:19f5f51584de 212 /* Station Address 1 Register */
Benoit 0:19f5f51584de 213 /* Station Address 2 Register */
Benoit 0:19f5f51584de 214
Benoit 0:19f5f51584de 215
Benoit 0:19f5f51584de 216 /* Control register definitions --------------------------------------------------------------------------- */
Benoit 0:19f5f51584de 217 /*********************************************************************//**
Benoit 0:19f5f51584de 218 * Macro defines for Command Register
Benoit 0:19f5f51584de 219 **********************************************************************/
Benoit 0:19f5f51584de 220 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
Benoit 0:19f5f51584de 221 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
Benoit 0:19f5f51584de 222 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
Benoit 0:19f5f51584de 223 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
Benoit 0:19f5f51584de 224 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
Benoit 0:19f5f51584de 225 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
Benoit 0:19f5f51584de 226 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
Benoit 0:19f5f51584de 227 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
Benoit 0:19f5f51584de 228 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
Benoit 0:19f5f51584de 229 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
Benoit 0:19f5f51584de 230
Benoit 0:19f5f51584de 231 /*********************************************************************//**
Benoit 0:19f5f51584de 232 * Macro defines for Status Register
Benoit 0:19f5f51584de 233 **********************************************************************/
Benoit 0:19f5f51584de 234 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
Benoit 0:19f5f51584de 235 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
Benoit 0:19f5f51584de 236
Benoit 0:19f5f51584de 237 /*********************************************************************//**
Benoit 0:19f5f51584de 238 * Macro defines for Transmit Status Vector 0 Register
Benoit 0:19f5f51584de 239 **********************************************************************/
Benoit 0:19f5f51584de 240 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
Benoit 0:19f5f51584de 241 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
Benoit 0:19f5f51584de 242 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
Benoit 0:19f5f51584de 243 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
Benoit 0:19f5f51584de 244 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
Benoit 0:19f5f51584de 245 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
Benoit 0:19f5f51584de 246 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
Benoit 0:19f5f51584de 247 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
Benoit 0:19f5f51584de 248 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
Benoit 0:19f5f51584de 249 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
Benoit 0:19f5f51584de 250 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
Benoit 0:19f5f51584de 251 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
Benoit 0:19f5f51584de 252 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
Benoit 0:19f5f51584de 253 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
Benoit 0:19f5f51584de 254 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
Benoit 0:19f5f51584de 255 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
Benoit 0:19f5f51584de 256 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
Benoit 0:19f5f51584de 257
Benoit 0:19f5f51584de 258 /*********************************************************************//**
Benoit 0:19f5f51584de 259 * Macro defines for Transmit Status Vector 1 Register
Benoit 0:19f5f51584de 260 **********************************************************************/
Benoit 0:19f5f51584de 261 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
Benoit 0:19f5f51584de 262 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
Benoit 0:19f5f51584de 263
Benoit 0:19f5f51584de 264 /*********************************************************************//**
Benoit 0:19f5f51584de 265 * Macro defines for Receive Status Vector Register
Benoit 0:19f5f51584de 266 **********************************************************************/
Benoit 0:19f5f51584de 267 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
Benoit 0:19f5f51584de 268 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
Benoit 0:19f5f51584de 269 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
Benoit 0:19f5f51584de 270 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
Benoit 0:19f5f51584de 271 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
Benoit 0:19f5f51584de 272 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
Benoit 0:19f5f51584de 273 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
Benoit 0:19f5f51584de 274 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
Benoit 0:19f5f51584de 275 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
Benoit 0:19f5f51584de 276 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
Benoit 0:19f5f51584de 277 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
Benoit 0:19f5f51584de 278 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
Benoit 0:19f5f51584de 279 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
Benoit 0:19f5f51584de 280 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
Benoit 0:19f5f51584de 281 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
Benoit 0:19f5f51584de 282 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
Benoit 0:19f5f51584de 283
Benoit 0:19f5f51584de 284 /*********************************************************************//**
Benoit 0:19f5f51584de 285 * Macro defines for Flow Control Counter Register
Benoit 0:19f5f51584de 286 **********************************************************************/
Benoit 0:19f5f51584de 287 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
Benoit 0:19f5f51584de 288 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
Benoit 0:19f5f51584de 289
Benoit 0:19f5f51584de 290 /*********************************************************************//**
Benoit 0:19f5f51584de 291 * Macro defines for Flow Control Status Register
Benoit 0:19f5f51584de 292 **********************************************************************/
Benoit 0:19f5f51584de 293 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
Benoit 0:19f5f51584de 294
Benoit 0:19f5f51584de 295
Benoit 0:19f5f51584de 296 /* Receive filter register definitions -------------------------------------------------------- */
Benoit 0:19f5f51584de 297 /*********************************************************************//**
Benoit 0:19f5f51584de 298 * Macro defines for Receive Filter Control Register
Benoit 0:19f5f51584de 299 **********************************************************************/
Benoit 0:19f5f51584de 300 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
Benoit 0:19f5f51584de 301 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
Benoit 0:19f5f51584de 302 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
Benoit 0:19f5f51584de 303 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
Benoit 0:19f5f51584de 304 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
Benoit 0:19f5f51584de 305 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
Benoit 0:19f5f51584de 306 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
Benoit 0:19f5f51584de 307 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
Benoit 0:19f5f51584de 308
Benoit 0:19f5f51584de 309 /*********************************************************************//**
Benoit 0:19f5f51584de 310 * Macro defines for Receive Filter WoL Status/Clear Registers
Benoit 0:19f5f51584de 311 **********************************************************************/
Benoit 0:19f5f51584de 312 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
Benoit 0:19f5f51584de 313 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
Benoit 0:19f5f51584de 314 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
Benoit 0:19f5f51584de 315 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
Benoit 0:19f5f51584de 316 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
Benoit 0:19f5f51584de 317 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
Benoit 0:19f5f51584de 318 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
Benoit 0:19f5f51584de 319 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
Benoit 0:19f5f51584de 320 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
Benoit 0:19f5f51584de 321
Benoit 0:19f5f51584de 322
Benoit 0:19f5f51584de 323 /* Module control register definitions ---------------------------------------------------- */
Benoit 0:19f5f51584de 324 /*********************************************************************//**
Benoit 0:19f5f51584de 325 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
Benoit 0:19f5f51584de 326 **********************************************************************/
Benoit 0:19f5f51584de 327 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
Benoit 0:19f5f51584de 328 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
Benoit 0:19f5f51584de 329 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
Benoit 0:19f5f51584de 330 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
Benoit 0:19f5f51584de 331 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
Benoit 0:19f5f51584de 332 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
Benoit 0:19f5f51584de 333 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
Benoit 0:19f5f51584de 334 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
Benoit 0:19f5f51584de 335 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
Benoit 0:19f5f51584de 336 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
Benoit 0:19f5f51584de 337
Benoit 0:19f5f51584de 338 /*********************************************************************//**
Benoit 0:19f5f51584de 339 * Macro defines for Power Down Register
Benoit 0:19f5f51584de 340 **********************************************************************/
Benoit 0:19f5f51584de 341 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
Benoit 0:19f5f51584de 342
Benoit 0:19f5f51584de 343 /* Descriptor and status formats ---------------------------------------------------- */
Benoit 0:19f5f51584de 344 /*********************************************************************//**
Benoit 0:19f5f51584de 345 * Macro defines for RX Descriptor Control Word
Benoit 0:19f5f51584de 346 **********************************************************************/
Benoit 0:19f5f51584de 347 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
Benoit 0:19f5f51584de 348 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
Benoit 0:19f5f51584de 349
Benoit 0:19f5f51584de 350 /*********************************************************************//**
Benoit 0:19f5f51584de 351 * Macro defines for RX Status Hash CRC Word
Benoit 0:19f5f51584de 352 **********************************************************************/
Benoit 0:19f5f51584de 353 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
Benoit 0:19f5f51584de 354 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
Benoit 0:19f5f51584de 355
Benoit 0:19f5f51584de 356 /*********************************************************************//**
Benoit 0:19f5f51584de 357 * Macro defines for RX Status Information Word
Benoit 0:19f5f51584de 358 **********************************************************************/
Benoit 0:19f5f51584de 359 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
Benoit 0:19f5f51584de 360 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
Benoit 0:19f5f51584de 361 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
Benoit 0:19f5f51584de 362 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
Benoit 0:19f5f51584de 363 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
Benoit 0:19f5f51584de 364 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
Benoit 0:19f5f51584de 365 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
Benoit 0:19f5f51584de 366 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
Benoit 0:19f5f51584de 367 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
Benoit 0:19f5f51584de 368 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
Benoit 0:19f5f51584de 369 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
Benoit 0:19f5f51584de 370 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
Benoit 0:19f5f51584de 371 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
Benoit 0:19f5f51584de 372 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
Benoit 0:19f5f51584de 373 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
Benoit 0:19f5f51584de 374 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
Benoit 0:19f5f51584de 375 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
Benoit 0:19f5f51584de 376
Benoit 0:19f5f51584de 377 /*********************************************************************//**
Benoit 0:19f5f51584de 378 * Macro defines for TX Descriptor Control Word
Benoit 0:19f5f51584de 379 **********************************************************************/
Benoit 0:19f5f51584de 380 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
Benoit 0:19f5f51584de 381 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
Benoit 0:19f5f51584de 382 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
Benoit 0:19f5f51584de 383 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
Benoit 0:19f5f51584de 384 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
Benoit 0:19f5f51584de 385 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
Benoit 0:19f5f51584de 386 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
Benoit 0:19f5f51584de 387
Benoit 0:19f5f51584de 388 /*********************************************************************//**
Benoit 0:19f5f51584de 389 * Macro defines for TX Status Information Word
Benoit 0:19f5f51584de 390 **********************************************************************/
Benoit 0:19f5f51584de 391 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
Benoit 0:19f5f51584de 392 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
Benoit 0:19f5f51584de 393 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
Benoit 0:19f5f51584de 394 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
Benoit 0:19f5f51584de 395 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
Benoit 0:19f5f51584de 396 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
Benoit 0:19f5f51584de 397 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
Benoit 0:19f5f51584de 398 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
Benoit 0:19f5f51584de 399
Benoit 0:19f5f51584de 400 #ifdef MCB_LPC_1768
Benoit 0:19f5f51584de 401 /* DP83848C PHY definition ------------------------------------------------------------ */
Benoit 0:19f5f51584de 402
Benoit 0:19f5f51584de 403 /** PHY device reset time out definition */
Benoit 0:19f5f51584de 404 #define EMAC_PHY_RESP_TOUT 0x100000UL
Benoit 0:19f5f51584de 405
Benoit 0:19f5f51584de 406 /* ENET Device Revision ID */
Benoit 0:19f5f51584de 407 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
Benoit 0:19f5f51584de 408
Benoit 0:19f5f51584de 409 /*********************************************************************//**
Benoit 0:19f5f51584de 410 * Macro defines for DP83848C PHY Registers
Benoit 0:19f5f51584de 411 **********************************************************************/
Benoit 0:19f5f51584de 412 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
Benoit 0:19f5f51584de 413 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
Benoit 0:19f5f51584de 414 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
Benoit 0:19f5f51584de 415 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
Benoit 0:19f5f51584de 416 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
Benoit 0:19f5f51584de 417 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
Benoit 0:19f5f51584de 418 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
Benoit 0:19f5f51584de 419 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
Benoit 0:19f5f51584de 420 #define EMAC_PHY_REG_LPNPA 0x08
Benoit 0:19f5f51584de 421
Benoit 0:19f5f51584de 422 /*********************************************************************//**
Benoit 0:19f5f51584de 423 * Macro defines for PHY Extended Registers
Benoit 0:19f5f51584de 424 **********************************************************************/
Benoit 0:19f5f51584de 425 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
Benoit 0:19f5f51584de 426 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
Benoit 0:19f5f51584de 427 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
Benoit 0:19f5f51584de 428 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
Benoit 0:19f5f51584de 429 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
Benoit 0:19f5f51584de 430 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
Benoit 0:19f5f51584de 431 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
Benoit 0:19f5f51584de 432 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
Benoit 0:19f5f51584de 433 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
Benoit 0:19f5f51584de 434 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
Benoit 0:19f5f51584de 435 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
Benoit 0:19f5f51584de 436 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
Benoit 0:19f5f51584de 437
Benoit 0:19f5f51584de 438 /*********************************************************************//**
Benoit 0:19f5f51584de 439 * Macro defines for PHY Basic Mode Control Register
Benoit 0:19f5f51584de 440 **********************************************************************/
Benoit 0:19f5f51584de 441 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
Benoit 0:19f5f51584de 442 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
Benoit 0:19f5f51584de 443 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
Benoit 0:19f5f51584de 444 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
Benoit 0:19f5f51584de 445 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
Benoit 0:19f5f51584de 446 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
Benoit 0:19f5f51584de 447 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
Benoit 0:19f5f51584de 448 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
Benoit 0:19f5f51584de 449
Benoit 0:19f5f51584de 450 /*********************************************************************//**
Benoit 0:19f5f51584de 451 * Macro defines for PHY Basic Mode Status Status Register
Benoit 0:19f5f51584de 452 **********************************************************************/
Benoit 0:19f5f51584de 453 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
Benoit 0:19f5f51584de 454 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
Benoit 0:19f5f51584de 455 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
Benoit 0:19f5f51584de 456 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
Benoit 0:19f5f51584de 457 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
Benoit 0:19f5f51584de 458 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
Benoit 0:19f5f51584de 459 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
Benoit 0:19f5f51584de 460 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
Benoit 0:19f5f51584de 461 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
Benoit 0:19f5f51584de 462 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
Benoit 0:19f5f51584de 463
Benoit 0:19f5f51584de 464 /*********************************************************************//**
Benoit 0:19f5f51584de 465 * Macro defines for PHY Status Register
Benoit 0:19f5f51584de 466 **********************************************************************/
Benoit 0:19f5f51584de 467 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
Benoit 0:19f5f51584de 468 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
Benoit 0:19f5f51584de 469 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
Benoit 0:19f5f51584de 470 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
Benoit 0:19f5f51584de 471 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
Benoit 0:19f5f51584de 472 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
Benoit 0:19f5f51584de 473 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
Benoit 0:19f5f51584de 474
Benoit 0:19f5f51584de 475 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
Benoit 0:19f5f51584de 476 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
Benoit 0:19f5f51584de 477 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
Benoit 0:19f5f51584de 478 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
Benoit 0:19f5f51584de 479 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
Benoit 0:19f5f51584de 480
Benoit 0:19f5f51584de 481 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
Benoit 0:19f5f51584de 482 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
Benoit 0:19f5f51584de 483
Benoit 0:19f5f51584de 484 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
Benoit 0:19f5f51584de 485 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
Benoit 0:19f5f51584de 486 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
Benoit 0:19f5f51584de 487
Benoit 0:19f5f51584de 488 #elif defined(IAR_LPC_1768)
Benoit 0:19f5f51584de 489 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
Benoit 0:19f5f51584de 490 /** PHY device reset time out definition */
Benoit 0:19f5f51584de 491 #define EMAC_PHY_RESP_TOUT 0x100000UL
Benoit 0:19f5f51584de 492
Benoit 0:19f5f51584de 493 /* ENET Device Revision ID */
Benoit 0:19f5f51584de 494 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
Benoit 0:19f5f51584de 495
Benoit 0:19f5f51584de 496 /*********************************************************************//**
Benoit 0:19f5f51584de 497 * Macro defines for KSZ8721BL PHY Registers
Benoit 0:19f5f51584de 498 **********************************************************************/
Benoit 0:19f5f51584de 499 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
Benoit 0:19f5f51584de 500 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
Benoit 0:19f5f51584de 501 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
Benoit 0:19f5f51584de 502 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
Benoit 0:19f5f51584de 503 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
Benoit 0:19f5f51584de 504 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
Benoit 0:19f5f51584de 505 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
Benoit 0:19f5f51584de 506 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
Benoit 0:19f5f51584de 507 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
Benoit 0:19f5f51584de 508 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
Benoit 0:19f5f51584de 509 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
Benoit 0:19f5f51584de 510 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
Benoit 0:19f5f51584de 511
Benoit 0:19f5f51584de 512 /*********************************************************************//**
Benoit 0:19f5f51584de 513 * Macro defines for PHY Basic Mode Control Register
Benoit 0:19f5f51584de 514 **********************************************************************/
Benoit 0:19f5f51584de 515 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
Benoit 0:19f5f51584de 516 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
Benoit 0:19f5f51584de 517 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
Benoit 0:19f5f51584de 518 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
Benoit 0:19f5f51584de 519 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
Benoit 0:19f5f51584de 520 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
Benoit 0:19f5f51584de 521 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
Benoit 0:19f5f51584de 522 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
Benoit 0:19f5f51584de 523 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
Benoit 0:19f5f51584de 524 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
Benoit 0:19f5f51584de 525
Benoit 0:19f5f51584de 526 /*********************************************************************//**
Benoit 0:19f5f51584de 527 * Macro defines for PHY Basic Mode Status Register
Benoit 0:19f5f51584de 528 **********************************************************************/
Benoit 0:19f5f51584de 529 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
Benoit 0:19f5f51584de 530 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
Benoit 0:19f5f51584de 531 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
Benoit 0:19f5f51584de 532 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
Benoit 0:19f5f51584de 533 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
Benoit 0:19f5f51584de 534 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
Benoit 0:19f5f51584de 535 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
Benoit 0:19f5f51584de 536 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
Benoit 0:19f5f51584de 537 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
Benoit 0:19f5f51584de 538 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
Benoit 0:19f5f51584de 539 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
Benoit 0:19f5f51584de 540 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
Benoit 0:19f5f51584de 541
Benoit 0:19f5f51584de 542 /*********************************************************************//**
Benoit 0:19f5f51584de 543 * Macro defines for PHY Identifier
Benoit 0:19f5f51584de 544 **********************************************************************/
Benoit 0:19f5f51584de 545 /* PHY Identifier 1 bitmap definitions */
Benoit 0:19f5f51584de 546 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
Benoit 0:19f5f51584de 547
Benoit 0:19f5f51584de 548 /* PHY Identifier 2 bitmap definitions */
Benoit 0:19f5f51584de 549 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
Benoit 0:19f5f51584de 550
Benoit 0:19f5f51584de 551 /*********************************************************************//**
Benoit 0:19f5f51584de 552 * Macro defines for Auto-Negotiation Advertisement
Benoit 0:19f5f51584de 553 **********************************************************************/
Benoit 0:19f5f51584de 554 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
Benoit 0:19f5f51584de 555 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
Benoit 0:19f5f51584de 556 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
Benoit 0:19f5f51584de 557 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
Benoit 0:19f5f51584de 558 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
Benoit 0:19f5f51584de 559 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
Benoit 0:19f5f51584de 560 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
Benoit 0:19f5f51584de 561 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
Benoit 0:19f5f51584de 562 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
Benoit 0:19f5f51584de 563
Benoit 0:19f5f51584de 564 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
Benoit 0:19f5f51584de 565 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
Benoit 0:19f5f51584de 566 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
Benoit 0:19f5f51584de 567 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
Benoit 0:19f5f51584de 568 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
Benoit 0:19f5f51584de 569
Benoit 0:19f5f51584de 570 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
Benoit 0:19f5f51584de 571 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
Benoit 0:19f5f51584de 572
Benoit 0:19f5f51584de 573 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
Benoit 0:19f5f51584de 574 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
Benoit 0:19f5f51584de 575 #endif
Benoit 0:19f5f51584de 576
Benoit 0:19f5f51584de 577 /**
Benoit 0:19f5f51584de 578 * @}
Benoit 0:19f5f51584de 579 */
Benoit 0:19f5f51584de 580
Benoit 0:19f5f51584de 581
Benoit 0:19f5f51584de 582 /* Public Types --------------------------------------------------------------- */
Benoit 0:19f5f51584de 583 /** @defgroup EMAC_Public_Types EMAC Public Types
Benoit 0:19f5f51584de 584 * @{
Benoit 0:19f5f51584de 585 */
Benoit 0:19f5f51584de 586
Benoit 0:19f5f51584de 587 /* Descriptor and status formats ---------------------------------------------- */
Benoit 0:19f5f51584de 588
Benoit 0:19f5f51584de 589 /**
Benoit 0:19f5f51584de 590 * @brief RX Descriptor structure type definition
Benoit 0:19f5f51584de 591 */
Benoit 0:19f5f51584de 592 typedef struct {
Benoit 0:19f5f51584de 593 uint32_t Packet; /**< Receive Packet Descriptor */
Benoit 0:19f5f51584de 594 uint32_t Ctrl; /**< Receive Control Descriptor */
Benoit 0:19f5f51584de 595 } RX_Desc;
Benoit 0:19f5f51584de 596
Benoit 0:19f5f51584de 597 /**
Benoit 0:19f5f51584de 598 * @brief RX Status structure type definition
Benoit 0:19f5f51584de 599 */
Benoit 0:19f5f51584de 600 typedef struct {
Benoit 0:19f5f51584de 601 uint32_t Info; /**< Receive Information Status */
Benoit 0:19f5f51584de 602 uint32_t HashCRC; /**< Receive Hash CRC Status */
Benoit 0:19f5f51584de 603 } RX_Stat;
Benoit 0:19f5f51584de 604
Benoit 0:19f5f51584de 605 /**
Benoit 0:19f5f51584de 606 * @brief TX Descriptor structure type definition
Benoit 0:19f5f51584de 607 */
Benoit 0:19f5f51584de 608 typedef struct {
Benoit 0:19f5f51584de 609 uint32_t Packet; /**< Transmit Packet Descriptor */
Benoit 0:19f5f51584de 610 uint32_t Ctrl; /**< Transmit Control Descriptor */
Benoit 0:19f5f51584de 611 } TX_Desc;
Benoit 0:19f5f51584de 612
Benoit 0:19f5f51584de 613 /**
Benoit 0:19f5f51584de 614 * @brief TX Status structure type definition
Benoit 0:19f5f51584de 615 */
Benoit 0:19f5f51584de 616 typedef struct {
Benoit 0:19f5f51584de 617 uint32_t Info; /**< Transmit Information Status */
Benoit 0:19f5f51584de 618 } TX_Stat;
Benoit 0:19f5f51584de 619
Benoit 0:19f5f51584de 620
Benoit 0:19f5f51584de 621 /**
Benoit 0:19f5f51584de 622 * @brief TX Data Buffer structure definition
Benoit 0:19f5f51584de 623 */
Benoit 0:19f5f51584de 624 typedef struct {
Benoit 0:19f5f51584de 625 uint32_t ulDataLen; /**< Data length */
Benoit 0:19f5f51584de 626 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
Benoit 0:19f5f51584de 627 } EMAC_PACKETBUF_Type;
Benoit 0:19f5f51584de 628
Benoit 0:19f5f51584de 629 /**
Benoit 0:19f5f51584de 630 * @brief EMAC configuration structure definition
Benoit 0:19f5f51584de 631 */
Benoit 0:19f5f51584de 632 typedef struct {
Benoit 0:19f5f51584de 633 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
Benoit 0:19f5f51584de 634 - EMAC_MODE_AUTO
Benoit 0:19f5f51584de 635 - EMAC_MODE_10M_FULL
Benoit 0:19f5f51584de 636 - EMAC_MODE_10M_HALF
Benoit 0:19f5f51584de 637 - EMAC_MODE_100M_FULL
Benoit 0:19f5f51584de 638 - EMAC_MODE_100M_HALF
Benoit 0:19f5f51584de 639 */
Benoit 0:19f5f51584de 640 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
Benoit 0:19f5f51584de 641 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
Benoit 0:19f5f51584de 642 */
Benoit 0:19f5f51584de 643 } EMAC_CFG_Type;
Benoit 0:19f5f51584de 644
Benoit 0:19f5f51584de 645
Benoit 0:19f5f51584de 646 /**
Benoit 0:19f5f51584de 647 * @}
Benoit 0:19f5f51584de 648 */
Benoit 0:19f5f51584de 649
Benoit 0:19f5f51584de 650
Benoit 0:19f5f51584de 651 /* Public Functions ----------------------------------------------------------- */
Benoit 0:19f5f51584de 652 /** @defgroup EMAC_Public_Functions EMAC Public Functions
Benoit 0:19f5f51584de 653 * @{
Benoit 0:19f5f51584de 654 */
Benoit 0:19f5f51584de 655 /* Init/DeInit EMAC peripheral */
Benoit 0:19f5f51584de 656 Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
Benoit 0:19f5f51584de 657 void EMAC_DeInit(void);
Benoit 0:19f5f51584de 658
Benoit 0:19f5f51584de 659 /* PHY functions --------------*/
Benoit 0:19f5f51584de 660 int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
Benoit 0:19f5f51584de 661 int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
Benoit 0:19f5f51584de 662 int32_t EMAC_UpdatePHYStatus(void);
Benoit 0:19f5f51584de 663
Benoit 0:19f5f51584de 664 /* Filter functions ----------*/
Benoit 0:19f5f51584de 665 void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
Benoit 0:19f5f51584de 666 void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
Benoit 0:19f5f51584de 667
Benoit 0:19f5f51584de 668 /* EMAC Packet Buffer functions */
Benoit 0:19f5f51584de 669 void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
Benoit 0:19f5f51584de 670 void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
Benoit 0:19f5f51584de 671
Benoit 0:19f5f51584de 672 /* EMAC Interrupt functions -------*/
Benoit 0:19f5f51584de 673 void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
Benoit 0:19f5f51584de 674 IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
Benoit 0:19f5f51584de 675
Benoit 0:19f5f51584de 676 /* EMAC Index functions -----------*/
Benoit 1:f4040665bc61 677 Bool EMAC_CheckReceiveIndex(void);
Benoit 1:f4040665bc61 678 Bool EMAC_CheckTransmitIndex(void);
Benoit 0:19f5f51584de 679 void EMAC_UpdateRxConsumeIndex(void);
Benoit 0:19f5f51584de 680 void EMAC_UpdateTxProduceIndex(void);
Benoit 0:19f5f51584de 681
Benoit 0:19f5f51584de 682 FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
Benoit 0:19f5f51584de 683 uint32_t EMAC_GetReceiveDataSize(void);
Benoit 0:19f5f51584de 684 FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
Benoit 0:19f5f51584de 685
Benoit 0:19f5f51584de 686 /**
Benoit 0:19f5f51584de 687 * @}
Benoit 0:19f5f51584de 688 */
Benoit 0:19f5f51584de 689
Benoit 0:19f5f51584de 690 #ifdef __cplusplus
Benoit 0:19f5f51584de 691 }
Benoit 0:19f5f51584de 692 #endif
Benoit 0:19f5f51584de 693
Benoit 0:19f5f51584de 694 #endif /* LPC17XX_EMAC_H_ */
Benoit 0:19f5f51584de 695
Benoit 0:19f5f51584de 696 /**
Benoit 0:19f5f51584de 697 * @}
Benoit 0:19f5f51584de 698 */
Benoit 0:19f5f51584de 699
Benoit 0:19f5f51584de 700 /* --------------------------------- End Of File ------------------------------ */
Benoit 5:3cd83fcb1467 701 /* @endcond */