Benoît Locher / mbedNet

Rewrite from scratch a TCP/IP stack for mbed. So far the following parts are usable: Drivers: - EMAC driver (from CMSIS 2.0) Protocols: - Ethernet protocol - ARP over ethernet for IPv4 - IPv4 over Ethernet - ICMPv4 over IPv4 - UDPv4 over IPv4 APIs: - Sockets for UDPv4 The structure of this stack is designed to be very modular. Each protocol can register one or more protocol to handle its payload, and in each protocol, an API can be hooked (like Sockets for example). This is an early release.

lpc17xx_clkpwr.cpp@7:8e12f7357b9f, 2011-06-26 (annotated)

Committer:
Benoit
Date:
Sun Jun 26 09:56:31 2011 +0000
Revision:
7:8e12f7357b9f
Parent:
1:f4040665bc61 
Added IPv4 global broadcast address to processed frames inside IPv4 layer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Benoit 1:f4040665bc61 1 /***********************************************************************//**
Benoit 1:f4040665bc61 2 * @file lpc17xx_clkpwr.c
Benoit 1:f4040665bc61 3 * @brief Contains all functions support for Clock and Power Control
Benoit 1:f4040665bc61 4 * firmware library on LPC17xx
Benoit 1:f4040665bc61 5 * @version 3.0
Benoit 1:f4040665bc61 6 * @date 18. June. 2010
Benoit 1:f4040665bc61 7 * @author NXP MCU SW Application Team
Benoit 1:f4040665bc61 8 **************************************************************************
Benoit 1:f4040665bc61 9 * Software that is described herein is for illustrative purposes only
Benoit 1:f4040665bc61 10 * which provides customers with programming information regarding the
Benoit 1:f4040665bc61 11 * products. This software is supplied "AS IS" without any warranties.
Benoit 1:f4040665bc61 12 * NXP Semiconductors assumes no responsibility or liability for the
Benoit 1:f4040665bc61 13 * use of the software, conveys no license or title under any patent,
Benoit 1:f4040665bc61 14 * copyright, or mask work right to the product. NXP Semiconductors
Benoit 1:f4040665bc61 15 * reserves the right to make changes in the software without
Benoit 1:f4040665bc61 16 * notification. NXP Semiconductors also make no representation or
Benoit 1:f4040665bc61 17 * warranty that such application will be suitable for the specified
Benoit 1:f4040665bc61 18 * use without further testing or modification.
Benoit 1:f4040665bc61 19 **********************************************************************/
Benoit 1:f4040665bc61 20
Benoit 1:f4040665bc61 21 /* Peripheral group ----------------------------------------------------------- */
Benoit 1:f4040665bc61 22 /** @addtogroup CLKPWR
Benoit 1:f4040665bc61 23 * @{
Benoit 1:f4040665bc61 24 */
Benoit 1:f4040665bc61 25
Benoit 1:f4040665bc61 26 /* Includes ------------------------------------------------------------------- */
Benoit 1:f4040665bc61 27 #include "lpc17xx_clkpwr.h"
Benoit 1:f4040665bc61 28
Benoit 1:f4040665bc61 29
Benoit 1:f4040665bc61 30 /* Public Functions ----------------------------------------------------------- */
Benoit 1:f4040665bc61 31 /** @addtogroup CLKPWR_Public_Functions
Benoit 1:f4040665bc61 32 * @{
Benoit 1:f4040665bc61 33 */
Benoit 1:f4040665bc61 34
Benoit 1:f4040665bc61 35 /*********************************************************************//**
Benoit 1:f4040665bc61 36 * @brief Set value of each Peripheral Clock Selection
Benoit 1:f4040665bc61 37 * @param[in] ClkType Peripheral Clock Selection of each type,
Benoit 1:f4040665bc61 38 * should be one of the following:
Benoit 1:f4040665bc61 39 * - CLKPWR_PCLKSEL_WDT : WDT
Benoit 1:f4040665bc61 40 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
Benoit 1:f4040665bc61 41 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
Benoit 1:f4040665bc61 42 - CLKPWR_PCLKSEL_UART0 : UART 0
Benoit 1:f4040665bc61 43 - CLKPWR_PCLKSEL_UART1 : UART 1
Benoit 1:f4040665bc61 44 - CLKPWR_PCLKSEL_PWM1 : PWM 1
Benoit 1:f4040665bc61 45 - CLKPWR_PCLKSEL_I2C0 : I2C 0
Benoit 1:f4040665bc61 46 - CLKPWR_PCLKSEL_SPI : SPI
Benoit 1:f4040665bc61 47 - CLKPWR_PCLKSEL_SSP1 : SSP 1
Benoit 1:f4040665bc61 48 - CLKPWR_PCLKSEL_DAC : DAC
Benoit 1:f4040665bc61 49 - CLKPWR_PCLKSEL_ADC : ADC
Benoit 1:f4040665bc61 50 - CLKPWR_PCLKSEL_CAN1 : CAN 1
Benoit 1:f4040665bc61 51 - CLKPWR_PCLKSEL_CAN2 : CAN 2
Benoit 1:f4040665bc61 52 - CLKPWR_PCLKSEL_ACF : ACF
Benoit 1:f4040665bc61 53 - CLKPWR_PCLKSEL_QEI : QEI
Benoit 1:f4040665bc61 54 - CLKPWR_PCLKSEL_PCB : PCB
Benoit 1:f4040665bc61 55 - CLKPWR_PCLKSEL_I2C1 : I2C 1
Benoit 1:f4040665bc61 56 - CLKPWR_PCLKSEL_SSP0 : SSP 0
Benoit 1:f4040665bc61 57 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
Benoit 1:f4040665bc61 58 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
Benoit 1:f4040665bc61 59 - CLKPWR_PCLKSEL_UART2 : UART 2
Benoit 1:f4040665bc61 60 - CLKPWR_PCLKSEL_UART3 : UART 3
Benoit 1:f4040665bc61 61 - CLKPWR_PCLKSEL_I2C2 : I2C 2
Benoit 1:f4040665bc61 62 - CLKPWR_PCLKSEL_I2S : I2S
Benoit 1:f4040665bc61 63 - CLKPWR_PCLKSEL_RIT : RIT
Benoit 1:f4040665bc61 64 - CLKPWR_PCLKSEL_SYSCON : SYSCON
Benoit 1:f4040665bc61 65 - CLKPWR_PCLKSEL_MC : MC
Benoit 1:f4040665bc61 66
Benoit 1:f4040665bc61 67 * @param[in] DivVal Value of divider, should be:
Benoit 1:f4040665bc61 68 * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
Benoit 1:f4040665bc61 69 * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
Benoit 1:f4040665bc61 70 * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
Benoit 1:f4040665bc61 71 *
Benoit 1:f4040665bc61 72 * @return none
Benoit 1:f4040665bc61 73 **********************************************************************/
Benoit 1:f4040665bc61 74 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
Benoit 1:f4040665bc61 75 {
Benoit 1:f4040665bc61 76 uint32_t bitpos;
Benoit 1:f4040665bc61 77
Benoit 1:f4040665bc61 78 bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
Benoit 1:f4040665bc61 79
Benoit 1:f4040665bc61 80 /* PCLKSEL0 selected */
Benoit 1:f4040665bc61 81 if (ClkType < 32)
Benoit 1:f4040665bc61 82 {
Benoit 1:f4040665bc61 83 /* Clear two bit at bit position */
Benoit 1:f4040665bc61 84 LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
Benoit 1:f4040665bc61 85
Benoit 1:f4040665bc61 86 /* Set two selected bit */
Benoit 1:f4040665bc61 87 LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
Benoit 1:f4040665bc61 88 }
Benoit 1:f4040665bc61 89 /* PCLKSEL1 selected */
Benoit 1:f4040665bc61 90 else
Benoit 1:f4040665bc61 91 {
Benoit 1:f4040665bc61 92 /* Clear two bit at bit position */
Benoit 1:f4040665bc61 93 LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
Benoit 1:f4040665bc61 94
Benoit 1:f4040665bc61 95 /* Set two selected bit */
Benoit 1:f4040665bc61 96 LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
Benoit 1:f4040665bc61 97 }
Benoit 1:f4040665bc61 98 }
Benoit 1:f4040665bc61 99
Benoit 1:f4040665bc61 100
Benoit 1:f4040665bc61 101 /*********************************************************************//**
Benoit 1:f4040665bc61 102 * @brief Get current value of each Peripheral Clock Selection
Benoit 1:f4040665bc61 103 * @param[in] ClkType Peripheral Clock Selection of each type,
Benoit 1:f4040665bc61 104 * should be one of the following:
Benoit 1:f4040665bc61 105 * - CLKPWR_PCLKSEL_WDT : WDT
Benoit 1:f4040665bc61 106 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
Benoit 1:f4040665bc61 107 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
Benoit 1:f4040665bc61 108 - CLKPWR_PCLKSEL_UART0 : UART 0
Benoit 1:f4040665bc61 109 - CLKPWR_PCLKSEL_UART1 : UART 1
Benoit 1:f4040665bc61 110 - CLKPWR_PCLKSEL_PWM1 : PWM 1
Benoit 1:f4040665bc61 111 - CLKPWR_PCLKSEL_I2C0 : I2C 0
Benoit 1:f4040665bc61 112 - CLKPWR_PCLKSEL_SPI : SPI
Benoit 1:f4040665bc61 113 - CLKPWR_PCLKSEL_SSP1 : SSP 1
Benoit 1:f4040665bc61 114 - CLKPWR_PCLKSEL_DAC : DAC
Benoit 1:f4040665bc61 115 - CLKPWR_PCLKSEL_ADC : ADC
Benoit 1:f4040665bc61 116 - CLKPWR_PCLKSEL_CAN1 : CAN 1
Benoit 1:f4040665bc61 117 - CLKPWR_PCLKSEL_CAN2 : CAN 2
Benoit 1:f4040665bc61 118 - CLKPWR_PCLKSEL_ACF : ACF
Benoit 1:f4040665bc61 119 - CLKPWR_PCLKSEL_QEI : QEI
Benoit 1:f4040665bc61 120 - CLKPWR_PCLKSEL_PCB : PCB
Benoit 1:f4040665bc61 121 - CLKPWR_PCLKSEL_I2C1 : I2C 1
Benoit 1:f4040665bc61 122 - CLKPWR_PCLKSEL_SSP0 : SSP 0
Benoit 1:f4040665bc61 123 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
Benoit 1:f4040665bc61 124 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
Benoit 1:f4040665bc61 125 - CLKPWR_PCLKSEL_UART2 : UART 2
Benoit 1:f4040665bc61 126 - CLKPWR_PCLKSEL_UART3 : UART 3
Benoit 1:f4040665bc61 127 - CLKPWR_PCLKSEL_I2C2 : I2C 2
Benoit 1:f4040665bc61 128 - CLKPWR_PCLKSEL_I2S : I2S
Benoit 1:f4040665bc61 129 - CLKPWR_PCLKSEL_RIT : RIT
Benoit 1:f4040665bc61 130 - CLKPWR_PCLKSEL_SYSCON : SYSCON
Benoit 1:f4040665bc61 131 - CLKPWR_PCLKSEL_MC : MC
Benoit 1:f4040665bc61 132
Benoit 1:f4040665bc61 133 * @return Value of Selected Peripheral Clock Selection
Benoit 1:f4040665bc61 134 **********************************************************************/
Benoit 1:f4040665bc61 135 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
Benoit 1:f4040665bc61 136 {
Benoit 1:f4040665bc61 137 uint32_t bitpos, retval;
Benoit 1:f4040665bc61 138
Benoit 1:f4040665bc61 139 if (ClkType < 32)
Benoit 1:f4040665bc61 140 {
Benoit 1:f4040665bc61 141 bitpos = ClkType;
Benoit 1:f4040665bc61 142 retval = LPC_SC->PCLKSEL0;
Benoit 1:f4040665bc61 143 }
Benoit 1:f4040665bc61 144 else
Benoit 1:f4040665bc61 145 {
Benoit 1:f4040665bc61 146 bitpos = ClkType - 32;
Benoit 1:f4040665bc61 147 retval = LPC_SC->PCLKSEL1;
Benoit 1:f4040665bc61 148 }
Benoit 1:f4040665bc61 149
Benoit 1:f4040665bc61 150 retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
Benoit 1:f4040665bc61 151 return retval;
Benoit 1:f4040665bc61 152 }
Benoit 1:f4040665bc61 153
Benoit 1:f4040665bc61 154
Benoit 1:f4040665bc61 155
Benoit 1:f4040665bc61 156 /*********************************************************************//**
Benoit 1:f4040665bc61 157 * @brief Get current value of each Peripheral Clock
Benoit 1:f4040665bc61 158 * @param[in] ClkType Peripheral Clock Selection of each type,
Benoit 1:f4040665bc61 159 * should be one of the following:
Benoit 1:f4040665bc61 160 * - CLKPWR_PCLKSEL_WDT : WDT
Benoit 1:f4040665bc61 161 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
Benoit 1:f4040665bc61 162 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
Benoit 1:f4040665bc61 163 - CLKPWR_PCLKSEL_UART0 : UART 0
Benoit 1:f4040665bc61 164 - CLKPWR_PCLKSEL_UART1 : UART 1
Benoit 1:f4040665bc61 165 - CLKPWR_PCLKSEL_PWM1 : PWM 1
Benoit 1:f4040665bc61 166 - CLKPWR_PCLKSEL_I2C0 : I2C 0
Benoit 1:f4040665bc61 167 - CLKPWR_PCLKSEL_SPI : SPI
Benoit 1:f4040665bc61 168 - CLKPWR_PCLKSEL_SSP1 : SSP 1
Benoit 1:f4040665bc61 169 - CLKPWR_PCLKSEL_DAC : DAC
Benoit 1:f4040665bc61 170 - CLKPWR_PCLKSEL_ADC : ADC
Benoit 1:f4040665bc61 171 - CLKPWR_PCLKSEL_CAN1 : CAN 1
Benoit 1:f4040665bc61 172 - CLKPWR_PCLKSEL_CAN2 : CAN 2
Benoit 1:f4040665bc61 173 - CLKPWR_PCLKSEL_ACF : ACF
Benoit 1:f4040665bc61 174 - CLKPWR_PCLKSEL_QEI : QEI
Benoit 1:f4040665bc61 175 - CLKPWR_PCLKSEL_PCB : PCB
Benoit 1:f4040665bc61 176 - CLKPWR_PCLKSEL_I2C1 : I2C 1
Benoit 1:f4040665bc61 177 - CLKPWR_PCLKSEL_SSP0 : SSP 0
Benoit 1:f4040665bc61 178 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
Benoit 1:f4040665bc61 179 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
Benoit 1:f4040665bc61 180 - CLKPWR_PCLKSEL_UART2 : UART 2
Benoit 1:f4040665bc61 181 - CLKPWR_PCLKSEL_UART3 : UART 3
Benoit 1:f4040665bc61 182 - CLKPWR_PCLKSEL_I2C2 : I2C 2
Benoit 1:f4040665bc61 183 - CLKPWR_PCLKSEL_I2S : I2S
Benoit 1:f4040665bc61 184 - CLKPWR_PCLKSEL_RIT : RIT
Benoit 1:f4040665bc61 185 - CLKPWR_PCLKSEL_SYSCON : SYSCON
Benoit 1:f4040665bc61 186 - CLKPWR_PCLKSEL_MC : MC
Benoit 1:f4040665bc61 187
Benoit 1:f4040665bc61 188 * @return Value of Selected Peripheral Clock
Benoit 1:f4040665bc61 189 **********************************************************************/
Benoit 1:f4040665bc61 190 uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
Benoit 1:f4040665bc61 191 {
Benoit 1:f4040665bc61 192 uint32_t retval, div;
Benoit 1:f4040665bc61 193
Benoit 1:f4040665bc61 194 retval = SystemCoreClock;
Benoit 1:f4040665bc61 195 div = CLKPWR_GetPCLKSEL(ClkType);
Benoit 1:f4040665bc61 196
Benoit 1:f4040665bc61 197 switch (div)
Benoit 1:f4040665bc61 198 {
Benoit 1:f4040665bc61 199 case 0:
Benoit 1:f4040665bc61 200 div = 4;
Benoit 1:f4040665bc61 201 break;
Benoit 1:f4040665bc61 202
Benoit 1:f4040665bc61 203 case 1:
Benoit 1:f4040665bc61 204 div = 1;
Benoit 1:f4040665bc61 205 break;
Benoit 1:f4040665bc61 206
Benoit 1:f4040665bc61 207 case 2:
Benoit 1:f4040665bc61 208 div = 2;
Benoit 1:f4040665bc61 209 break;
Benoit 1:f4040665bc61 210
Benoit 1:f4040665bc61 211 case 3:
Benoit 1:f4040665bc61 212 div = 8;
Benoit 1:f4040665bc61 213 break;
Benoit 1:f4040665bc61 214 }
Benoit 1:f4040665bc61 215 retval /= div;
Benoit 1:f4040665bc61 216
Benoit 1:f4040665bc61 217 return retval;
Benoit 1:f4040665bc61 218 }
Benoit 1:f4040665bc61 219
Benoit 1:f4040665bc61 220
Benoit 1:f4040665bc61 221
Benoit 1:f4040665bc61 222 /*********************************************************************//**
Benoit 1:f4040665bc61 223 * @brief Configure power supply for each peripheral according to NewState
Benoit 1:f4040665bc61 224 * @param[in] PPType Type of peripheral used to enable power,
Benoit 1:f4040665bc61 225 * should be one of the following:
Benoit 1:f4040665bc61 226 * - CLKPWR_PCONP_PCTIM0 : Timer 0
Benoit 1:f4040665bc61 227 - CLKPWR_PCONP_PCTIM1 : Timer 1
Benoit 1:f4040665bc61 228 - CLKPWR_PCONP_PCUART0 : UART 0
Benoit 1:f4040665bc61 229 - CLKPWR_PCONP_PCUART1 : UART 1
Benoit 1:f4040665bc61 230 - CLKPWR_PCONP_PCPWM1 : PWM 1
Benoit 1:f4040665bc61 231 - CLKPWR_PCONP_PCI2C0 : I2C 0
Benoit 1:f4040665bc61 232 - CLKPWR_PCONP_PCSPI : SPI
Benoit 1:f4040665bc61 233 - CLKPWR_PCONP_PCRTC : RTC
Benoit 1:f4040665bc61 234 - CLKPWR_PCONP_PCSSP1 : SSP 1
Benoit 1:f4040665bc61 235 - CLKPWR_PCONP_PCAD : ADC
Benoit 1:f4040665bc61 236 - CLKPWR_PCONP_PCAN1 : CAN 1
Benoit 1:f4040665bc61 237 - CLKPWR_PCONP_PCAN2 : CAN 2
Benoit 1:f4040665bc61 238 - CLKPWR_PCONP_PCGPIO : GPIO
Benoit 1:f4040665bc61 239 - CLKPWR_PCONP_PCRIT : RIT
Benoit 1:f4040665bc61 240 - CLKPWR_PCONP_PCMC : MC
Benoit 1:f4040665bc61 241 - CLKPWR_PCONP_PCQEI : QEI
Benoit 1:f4040665bc61 242 - CLKPWR_PCONP_PCI2C1 : I2C 1
Benoit 1:f4040665bc61 243 - CLKPWR_PCONP_PCSSP0 : SSP 0
Benoit 1:f4040665bc61 244 - CLKPWR_PCONP_PCTIM2 : Timer 2
Benoit 1:f4040665bc61 245 - CLKPWR_PCONP_PCTIM3 : Timer 3
Benoit 1:f4040665bc61 246 - CLKPWR_PCONP_PCUART2 : UART 2
Benoit 1:f4040665bc61 247 - CLKPWR_PCONP_PCUART3 : UART 3
Benoit 1:f4040665bc61 248 - CLKPWR_PCONP_PCI2C2 : I2C 2
Benoit 1:f4040665bc61 249 - CLKPWR_PCONP_PCI2S : I2S
Benoit 1:f4040665bc61 250 - CLKPWR_PCONP_PCGPDMA : GPDMA
Benoit 1:f4040665bc61 251 - CLKPWR_PCONP_PCENET : Ethernet
Benoit 1:f4040665bc61 252 - CLKPWR_PCONP_PCUSB : USB
Benoit 1:f4040665bc61 253 *
Benoit 1:f4040665bc61 254 * @param[in] NewState New state of Peripheral Power, should be:
Benoit 1:f4040665bc61 255 * - ENABLE : Enable power for this peripheral
Benoit 1:f4040665bc61 256 * - DISABLE : Disable power for this peripheral
Benoit 1:f4040665bc61 257 *
Benoit 1:f4040665bc61 258 * @return none
Benoit 1:f4040665bc61 259 **********************************************************************/
Benoit 1:f4040665bc61 260 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
Benoit 1:f4040665bc61 261 {
Benoit 1:f4040665bc61 262 if (NewState == ENABLE)
Benoit 1:f4040665bc61 263 {
Benoit 1:f4040665bc61 264 LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK;
Benoit 1:f4040665bc61 265 }
Benoit 1:f4040665bc61 266 else if (NewState == DISABLE)
Benoit 1:f4040665bc61 267 {
Benoit 1:f4040665bc61 268 LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
Benoit 1:f4040665bc61 269 }
Benoit 1:f4040665bc61 270 }
Benoit 1:f4040665bc61 271
Benoit 1:f4040665bc61 272
Benoit 1:f4040665bc61 273 /*********************************************************************//**
Benoit 1:f4040665bc61 274 * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
Benoit 1:f4040665bc61 275 * @param[in] None
Benoit 1:f4040665bc61 276 * @return None
Benoit 1:f4040665bc61 277 **********************************************************************/
Benoit 1:f4040665bc61 278 void CLKPWR_Sleep(void)
Benoit 1:f4040665bc61 279 {
Benoit 1:f4040665bc61 280 LPC_SC->PCON = 0x00;
Benoit 1:f4040665bc61 281 /* Sleep Mode*/
Benoit 1:f4040665bc61 282 __WFI();
Benoit 1:f4040665bc61 283 }
Benoit 1:f4040665bc61 284
Benoit 1:f4040665bc61 285
Benoit 1:f4040665bc61 286 /*********************************************************************//**
Benoit 1:f4040665bc61 287 * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
Benoit 1:f4040665bc61 288 * @param[in] None
Benoit 1:f4040665bc61 289 * @return None
Benoit 1:f4040665bc61 290 **********************************************************************/
Benoit 1:f4040665bc61 291 void CLKPWR_DeepSleep(void)
Benoit 1:f4040665bc61 292 {
Benoit 1:f4040665bc61 293 /* Deep-Sleep Mode, set SLEEPDEEP bit */
Benoit 1:f4040665bc61 294 SCB->SCR = 0x4;
Benoit 1:f4040665bc61 295 LPC_SC->PCON = 0x8;
Benoit 1:f4040665bc61 296 /* Deep Sleep Mode*/
Benoit 1:f4040665bc61 297 __WFI();
Benoit 1:f4040665bc61 298 }
Benoit 1:f4040665bc61 299
Benoit 1:f4040665bc61 300
Benoit 1:f4040665bc61 301 /*********************************************************************//**
Benoit 1:f4040665bc61 302 * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
Benoit 1:f4040665bc61 303 * @param[in] None
Benoit 1:f4040665bc61 304 * @return None
Benoit 1:f4040665bc61 305 **********************************************************************/
Benoit 1:f4040665bc61 306 void CLKPWR_PowerDown(void)
Benoit 1:f4040665bc61 307 {
Benoit 1:f4040665bc61 308 /* Deep-Sleep Mode, set SLEEPDEEP bit */
Benoit 1:f4040665bc61 309 SCB->SCR = 0x4;
Benoit 1:f4040665bc61 310 LPC_SC->PCON = 0x09;
Benoit 1:f4040665bc61 311 /* Power Down Mode*/
Benoit 1:f4040665bc61 312 __WFI();
Benoit 1:f4040665bc61 313 }
Benoit 1:f4040665bc61 314
Benoit 1:f4040665bc61 315
Benoit 1:f4040665bc61 316 /*********************************************************************//**
Benoit 1:f4040665bc61 317 * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
Benoit 1:f4040665bc61 318 * @param[in] None
Benoit 1:f4040665bc61 319 * @return None
Benoit 1:f4040665bc61 320 **********************************************************************/
Benoit 1:f4040665bc61 321 void CLKPWR_DeepPowerDown(void)
Benoit 1:f4040665bc61 322 {
Benoit 1:f4040665bc61 323 /* Deep-Sleep Mode, set SLEEPDEEP bit */
Benoit 1:f4040665bc61 324 SCB->SCR = 0x4;
Benoit 1:f4040665bc61 325 LPC_SC->PCON = 0x03;
Benoit 1:f4040665bc61 326 /* Deep Power Down Mode*/
Benoit 1:f4040665bc61 327 __WFI();
Benoit 1:f4040665bc61 328 }
Benoit 1:f4040665bc61 329
Benoit 1:f4040665bc61 330 /**
Benoit 1:f4040665bc61 331 * @}
Benoit 1:f4040665bc61 332 */
Benoit 1:f4040665bc61 333
Benoit 1:f4040665bc61 334 /**
Benoit 1:f4040665bc61 335 * @}
Benoit 1:f4040665bc61 336 */
Benoit 1:f4040665bc61 337
Benoit 1:f4040665bc61 338 /* --------------------------------- End Of File ------------------------------ */