Benoît Locher / mbedNet

Rewrite from scratch a TCP/IP stack for mbed. So far the following parts are usable: Drivers: - EMAC driver (from CMSIS 2.0) Protocols: - Ethernet protocol - ARP over ethernet for IPv4 - IPv4 over Ethernet - ICMPv4 over IPv4 - UDPv4 over IPv4 APIs: - Sockets for UDPv4 The structure of this stack is designed to be very modular. Each protocol can register one or more protocol to handle its payload, and in each protocol, an API can be hooked (like Sockets for example). This is an early release.

lpc17xx_clkpwr.h@0:19f5f51584de, 2011-06-12 (annotated)

Committer:
Benoit
Date:
Sun Jun 12 11:23:03 2011 +0000
Revision:
0:19f5f51584de
Child:
1:f4040665bc61
Initial release (alpha quality)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Benoit 0:19f5f51584de 1 /***********************************************************************//**
Benoit 0:19f5f51584de 2 * @file lpc17xx_clkpwr.h
Benoit 0:19f5f51584de 3 * @brief Contains all macro definitions and function prototypes
Benoit 0:19f5f51584de 4 * support for Clock and Power Control firmware library on LPC17xx
Benoit 0:19f5f51584de 5 * @version 2.0
Benoit 0:19f5f51584de 6 * @date 21. May. 2010
Benoit 0:19f5f51584de 7 * @author NXP MCU SW Application Team
Benoit 0:19f5f51584de 8 **************************************************************************
Benoit 0:19f5f51584de 9 * Software that is described herein is for illustrative purposes only
Benoit 0:19f5f51584de 10 * which provides customers with programming information regarding the
Benoit 0:19f5f51584de 11 * products. This software is supplied "AS IS" without any warranties.
Benoit 0:19f5f51584de 12 * NXP Semiconductors assumes no responsibility or liability for the
Benoit 0:19f5f51584de 13 * use of the software, conveys no license or title under any patent,
Benoit 0:19f5f51584de 14 * copyright, or mask work right to the product. NXP Semiconductors
Benoit 0:19f5f51584de 15 * reserves the right to make changes in the software without
Benoit 0:19f5f51584de 16 * notification. NXP Semiconductors also make no representation or
Benoit 0:19f5f51584de 17 * warranty that such application will be suitable for the specified
Benoit 0:19f5f51584de 18 * use without further testing or modification.
Benoit 0:19f5f51584de 19 **************************************************************************/
Benoit 0:19f5f51584de 20
Benoit 0:19f5f51584de 21 /* Peripheral group ----------------------------------------------------------- */
Benoit 0:19f5f51584de 22 /** @defgroup CLKPWR CLKPWR
Benoit 0:19f5f51584de 23 * @ingroup LPC1700CMSIS_FwLib_Drivers
Benoit 0:19f5f51584de 24 * @{
Benoit 0:19f5f51584de 25 */
Benoit 0:19f5f51584de 26
Benoit 0:19f5f51584de 27 #ifndef LPC17XX_CLKPWR_H_
Benoit 0:19f5f51584de 28 #define LPC17XX_CLKPWR_H_
Benoit 0:19f5f51584de 29
Benoit 0:19f5f51584de 30 /* Includes ------------------------------------------------------------------- */
Benoit 0:19f5f51584de 31 #include "lpc17xx.h"
Benoit 0:19f5f51584de 32 #include "lpc_types.h"
Benoit 0:19f5f51584de 33
Benoit 0:19f5f51584de 34 #ifdef __cplusplus
Benoit 0:19f5f51584de 35 extern "C"
Benoit 0:19f5f51584de 36 {
Benoit 0:19f5f51584de 37 #endif
Benoit 0:19f5f51584de 38
Benoit 0:19f5f51584de 39 /* Public Macros -------------------------------------------------------------- */
Benoit 0:19f5f51584de 40 /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
Benoit 0:19f5f51584de 41 * @{
Benoit 0:19f5f51584de 42 */
Benoit 0:19f5f51584de 43
Benoit 0:19f5f51584de 44 /**********************************************************************
Benoit 0:19f5f51584de 45 * Peripheral Clock Selection Definitions
Benoit 0:19f5f51584de 46 **********************************************************************/
Benoit 0:19f5f51584de 47 /** Peripheral clock divider bit position for WDT */
Benoit 0:19f5f51584de 48 #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
Benoit 0:19f5f51584de 49 /** Peripheral clock divider bit position for TIMER0 */
Benoit 0:19f5f51584de 50 #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
Benoit 0:19f5f51584de 51 /** Peripheral clock divider bit position for TIMER1 */
Benoit 0:19f5f51584de 52 #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
Benoit 0:19f5f51584de 53 /** Peripheral clock divider bit position for UART0 */
Benoit 0:19f5f51584de 54 #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
Benoit 0:19f5f51584de 55 /** Peripheral clock divider bit position for UART1 */
Benoit 0:19f5f51584de 56 #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
Benoit 0:19f5f51584de 57 /** Peripheral clock divider bit position for PWM1 */
Benoit 0:19f5f51584de 58 #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
Benoit 0:19f5f51584de 59 /** Peripheral clock divider bit position for I2C0 */
Benoit 0:19f5f51584de 60 #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
Benoit 0:19f5f51584de 61 /** Peripheral clock divider bit position for SPI */
Benoit 0:19f5f51584de 62 #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
Benoit 0:19f5f51584de 63 /** Peripheral clock divider bit position for SSP1 */
Benoit 0:19f5f51584de 64 #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
Benoit 0:19f5f51584de 65 /** Peripheral clock divider bit position for DAC */
Benoit 0:19f5f51584de 66 #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
Benoit 0:19f5f51584de 67 /** Peripheral clock divider bit position for ADC */
Benoit 0:19f5f51584de 68 #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
Benoit 0:19f5f51584de 69 /** Peripheral clock divider bit position for CAN1 */
Benoit 0:19f5f51584de 70 #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
Benoit 0:19f5f51584de 71 /** Peripheral clock divider bit position for CAN2 */
Benoit 0:19f5f51584de 72 #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
Benoit 0:19f5f51584de 73 /** Peripheral clock divider bit position for ACF */
Benoit 0:19f5f51584de 74 #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
Benoit 0:19f5f51584de 75 /** Peripheral clock divider bit position for QEI */
Benoit 0:19f5f51584de 76 #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
Benoit 0:19f5f51584de 77 /** Peripheral clock divider bit position for PCB */
Benoit 0:19f5f51584de 78 #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
Benoit 0:19f5f51584de 79 /** Peripheral clock divider bit position for I2C1 */
Benoit 0:19f5f51584de 80 #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
Benoit 0:19f5f51584de 81 /** Peripheral clock divider bit position for SSP0 */
Benoit 0:19f5f51584de 82 #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
Benoit 0:19f5f51584de 83 /** Peripheral clock divider bit position for TIMER2 */
Benoit 0:19f5f51584de 84 #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
Benoit 0:19f5f51584de 85 /** Peripheral clock divider bit position for TIMER3 */
Benoit 0:19f5f51584de 86 #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
Benoit 0:19f5f51584de 87 /** Peripheral clock divider bit position for UART2 */
Benoit 0:19f5f51584de 88 #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
Benoit 0:19f5f51584de 89 /** Peripheral clock divider bit position for UART3 */
Benoit 0:19f5f51584de 90 #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
Benoit 0:19f5f51584de 91 /** Peripheral clock divider bit position for I2C2 */
Benoit 0:19f5f51584de 92 #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
Benoit 0:19f5f51584de 93 /** Peripheral clock divider bit position for I2S */
Benoit 0:19f5f51584de 94 #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
Benoit 0:19f5f51584de 95 /** Peripheral clock divider bit position for RIT */
Benoit 0:19f5f51584de 96 #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
Benoit 0:19f5f51584de 97 /** Peripheral clock divider bit position for SYSCON */
Benoit 0:19f5f51584de 98 #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
Benoit 0:19f5f51584de 99 /** Peripheral clock divider bit position for MC */
Benoit 0:19f5f51584de 100 #define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
Benoit 0:19f5f51584de 101
Benoit 0:19f5f51584de 102 /** Macro for Peripheral Clock Selection register bit values
Benoit 0:19f5f51584de 103 * Note: When CCLK_DIV_8, Peripheral�s clock is selected to
Benoit 0:19f5f51584de 104 * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
Benoit 0:19f5f51584de 105 * when �11�selects PCLK_xyz = CCLK/6 */
Benoit 0:19f5f51584de 106 /* Peripheral clock divider is set to 4 from CCLK */
Benoit 0:19f5f51584de 107 #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
Benoit 0:19f5f51584de 108 /** Peripheral clock divider is the same with CCLK */
Benoit 0:19f5f51584de 109 #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
Benoit 0:19f5f51584de 110 /** Peripheral clock divider is set to 2 from CCLK */
Benoit 0:19f5f51584de 111 #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
Benoit 0:19f5f51584de 112
Benoit 0:19f5f51584de 113
Benoit 0:19f5f51584de 114 /********************************************************************
Benoit 0:19f5f51584de 115 * Power Control for Peripherals Definitions
Benoit 0:19f5f51584de 116 **********************************************************************/
Benoit 0:19f5f51584de 117 /** Timer/Counter 0 power/clock control bit */
Benoit 0:19f5f51584de 118 #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
Benoit 0:19f5f51584de 119 /* Timer/Counter 1 power/clock control bit */
Benoit 0:19f5f51584de 120 #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
Benoit 0:19f5f51584de 121 /** UART0 power/clock control bit */
Benoit 0:19f5f51584de 122 #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
Benoit 0:19f5f51584de 123 /** UART1 power/clock control bit */
Benoit 0:19f5f51584de 124 #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
Benoit 0:19f5f51584de 125 /** PWM1 power/clock control bit */
Benoit 0:19f5f51584de 126 #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
Benoit 0:19f5f51584de 127 /** The I2C0 interface power/clock control bit */
Benoit 0:19f5f51584de 128 #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
Benoit 0:19f5f51584de 129 /** The SPI interface power/clock control bit */
Benoit 0:19f5f51584de 130 #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
Benoit 0:19f5f51584de 131 /** The RTC power/clock control bit */
Benoit 0:19f5f51584de 132 #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
Benoit 0:19f5f51584de 133 /** The SSP1 interface power/clock control bit */
Benoit 0:19f5f51584de 134 #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
Benoit 0:19f5f51584de 135 /** A/D converter 0 (ADC0) power/clock control bit */
Benoit 0:19f5f51584de 136 #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
Benoit 0:19f5f51584de 137 /** CAN Controller 1 power/clock control bit */
Benoit 0:19f5f51584de 138 #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
Benoit 0:19f5f51584de 139 /** CAN Controller 2 power/clock control bit */
Benoit 0:19f5f51584de 140 #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
Benoit 0:19f5f51584de 141 /** GPIO power/clock control bit */
Benoit 0:19f5f51584de 142 #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
Benoit 0:19f5f51584de 143 /** Repetitive Interrupt Timer power/clock control bit */
Benoit 0:19f5f51584de 144 #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
Benoit 0:19f5f51584de 145 /** Motor Control PWM */
Benoit 0:19f5f51584de 146 #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
Benoit 0:19f5f51584de 147 /** Quadrature Encoder Interface power/clock control bit */
Benoit 0:19f5f51584de 148 #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
Benoit 0:19f5f51584de 149 /** The I2C1 interface power/clock control bit */
Benoit 0:19f5f51584de 150 #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
Benoit 0:19f5f51584de 151 /** The SSP0 interface power/clock control bit */
Benoit 0:19f5f51584de 152 #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
Benoit 0:19f5f51584de 153 /** Timer 2 power/clock control bit */
Benoit 0:19f5f51584de 154 #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
Benoit 0:19f5f51584de 155 /** Timer 3 power/clock control bit */
Benoit 0:19f5f51584de 156 #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
Benoit 0:19f5f51584de 157 /** UART 2 power/clock control bit */
Benoit 0:19f5f51584de 158 #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
Benoit 0:19f5f51584de 159 /** UART 3 power/clock control bit */
Benoit 0:19f5f51584de 160 #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
Benoit 0:19f5f51584de 161 /** I2C interface 2 power/clock control bit */
Benoit 0:19f5f51584de 162 #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
Benoit 0:19f5f51584de 163 /** I2S interface power/clock control bit*/
Benoit 0:19f5f51584de 164 #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
Benoit 0:19f5f51584de 165 /** GP DMA function power/clock control bit*/
Benoit 0:19f5f51584de 166 #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
Benoit 0:19f5f51584de 167 /** Ethernet block power/clock control bit*/
Benoit 0:19f5f51584de 168 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
Benoit 0:19f5f51584de 169 /** USB interface power/clock control bit*/
Benoit 0:19f5f51584de 170 #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
Benoit 0:19f5f51584de 171
Benoit 0:19f5f51584de 172
Benoit 0:19f5f51584de 173 /**
Benoit 0:19f5f51584de 174 * @}
Benoit 0:19f5f51584de 175 */
Benoit 0:19f5f51584de 176 /* Private Macros ------------------------------------------------------------- */
Benoit 0:19f5f51584de 177 /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
Benoit 0:19f5f51584de 178 * @{
Benoit 0:19f5f51584de 179 */
Benoit 0:19f5f51584de 180
Benoit 0:19f5f51584de 181 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Benoit 0:19f5f51584de 182 /*********************************************************************//**
Benoit 0:19f5f51584de 183 * Macro defines for Clock Source Select Register
Benoit 0:19f5f51584de 184 **********************************************************************/
Benoit 0:19f5f51584de 185 /** Internal RC oscillator */
Benoit 0:19f5f51584de 186 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
Benoit 0:19f5f51584de 187 /** Main oscillator */
Benoit 0:19f5f51584de 188 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
Benoit 0:19f5f51584de 189 /** RTC oscillator */
Benoit 0:19f5f51584de 190 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
Benoit 0:19f5f51584de 191 /** Clock source selection bit mask */
Benoit 0:19f5f51584de 192 #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
Benoit 0:19f5f51584de 193
Benoit 0:19f5f51584de 194 /*********************************************************************//**
Benoit 0:19f5f51584de 195 * Macro defines for Clock Output Configuration Register
Benoit 0:19f5f51584de 196 **********************************************************************/
Benoit 0:19f5f51584de 197 /* Clock Output Configuration register definition */
Benoit 0:19f5f51584de 198 /** Selects the CPU clock as the CLKOUT source */
Benoit 0:19f5f51584de 199 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
Benoit 0:19f5f51584de 200 /** Selects the main oscillator as the CLKOUT source */
Benoit 0:19f5f51584de 201 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
Benoit 0:19f5f51584de 202 /** Selects the Internal RC oscillator as the CLKOUT source */
Benoit 0:19f5f51584de 203 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
Benoit 0:19f5f51584de 204 /** Selects the USB clock as the CLKOUT source */
Benoit 0:19f5f51584de 205 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
Benoit 0:19f5f51584de 206 /** Selects the RTC oscillator as the CLKOUT source */
Benoit 0:19f5f51584de 207 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
Benoit 0:19f5f51584de 208 /** Integer value to divide the output clock by, minus one */
Benoit 0:19f5f51584de 209 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
Benoit 0:19f5f51584de 210 /** CLKOUT enable control */
Benoit 0:19f5f51584de 211 #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
Benoit 0:19f5f51584de 212 /** CLKOUT activity indication */
Benoit 0:19f5f51584de 213 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
Benoit 0:19f5f51584de 214 /** Clock source selection bit mask */
Benoit 0:19f5f51584de 215 #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
Benoit 0:19f5f51584de 216
Benoit 0:19f5f51584de 217 /*********************************************************************//**
Benoit 0:19f5f51584de 218 * Macro defines for PPL0 Control Register
Benoit 0:19f5f51584de 219 **********************************************************************/
Benoit 0:19f5f51584de 220 /** PLL 0 control enable */
Benoit 0:19f5f51584de 221 #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
Benoit 0:19f5f51584de 222 /** PLL 0 control connect */
Benoit 0:19f5f51584de 223 #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
Benoit 0:19f5f51584de 224 /** PLL 0 control bit mask */
Benoit 0:19f5f51584de 225 #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
Benoit 0:19f5f51584de 226
Benoit 0:19f5f51584de 227 /*********************************************************************//**
Benoit 0:19f5f51584de 228 * Macro defines for PPL0 Configuration Register
Benoit 0:19f5f51584de 229 **********************************************************************/
Benoit 0:19f5f51584de 230 /** PLL 0 Configuration MSEL field */
Benoit 0:19f5f51584de 231 #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
Benoit 0:19f5f51584de 232 /** PLL 0 Configuration NSEL field */
Benoit 0:19f5f51584de 233 #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
Benoit 0:19f5f51584de 234 /** PLL 0 Configuration bit mask */
Benoit 0:19f5f51584de 235 #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
Benoit 0:19f5f51584de 236
Benoit 0:19f5f51584de 237
Benoit 0:19f5f51584de 238 /*********************************************************************//**
Benoit 0:19f5f51584de 239 * Macro defines for PPL0 Status Register
Benoit 0:19f5f51584de 240 **********************************************************************/
Benoit 0:19f5f51584de 241 /** PLL 0 MSEL value */
Benoit 0:19f5f51584de 242 #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
Benoit 0:19f5f51584de 243 /** PLL NSEL get value */
Benoit 0:19f5f51584de 244 #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
Benoit 0:19f5f51584de 245 /** PLL status enable bit */
Benoit 0:19f5f51584de 246 #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
Benoit 0:19f5f51584de 247 /** PLL status Connect bit */
Benoit 0:19f5f51584de 248 #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
Benoit 0:19f5f51584de 249 /** PLL status lock */
Benoit 0:19f5f51584de 250 #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
Benoit 0:19f5f51584de 251
Benoit 0:19f5f51584de 252 /*********************************************************************//**
Benoit 0:19f5f51584de 253 * Macro defines for PPL0 Feed Register
Benoit 0:19f5f51584de 254 **********************************************************************/
Benoit 0:19f5f51584de 255 /** PLL0 Feed bit mask */
Benoit 0:19f5f51584de 256 #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
Benoit 0:19f5f51584de 257
Benoit 0:19f5f51584de 258 /*********************************************************************//**
Benoit 0:19f5f51584de 259 * Macro defines for PLL1 Control Register
Benoit 0:19f5f51584de 260 **********************************************************************/
Benoit 0:19f5f51584de 261 /** USB PLL control enable */
Benoit 0:19f5f51584de 262 #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
Benoit 0:19f5f51584de 263 /** USB PLL control connect */
Benoit 0:19f5f51584de 264 #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
Benoit 0:19f5f51584de 265 /** USB PLL control bit mask */
Benoit 0:19f5f51584de 266 #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
Benoit 0:19f5f51584de 267
Benoit 0:19f5f51584de 268 /*********************************************************************//**
Benoit 0:19f5f51584de 269 * Macro defines for PLL1 Configuration Register
Benoit 0:19f5f51584de 270 **********************************************************************/
Benoit 0:19f5f51584de 271 /** USB PLL MSEL set value */
Benoit 0:19f5f51584de 272 #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
Benoit 0:19f5f51584de 273 /** USB PLL PSEL set value */
Benoit 0:19f5f51584de 274 #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
Benoit 0:19f5f51584de 275 /** USB PLL configuration bit mask */
Benoit 0:19f5f51584de 276 #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
Benoit 0:19f5f51584de 277
Benoit 0:19f5f51584de 278 /*********************************************************************//**
Benoit 0:19f5f51584de 279 * Macro defines for PLL1 Status Register
Benoit 0:19f5f51584de 280 **********************************************************************/
Benoit 0:19f5f51584de 281 /** USB PLL MSEL get value */
Benoit 0:19f5f51584de 282 #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
Benoit 0:19f5f51584de 283 /** USB PLL PSEL get value */
Benoit 0:19f5f51584de 284 #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
Benoit 0:19f5f51584de 285 /** USB PLL status enable bit */
Benoit 0:19f5f51584de 286 #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
Benoit 0:19f5f51584de 287 /** USB PLL status Connect bit */
Benoit 0:19f5f51584de 288 #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
Benoit 0:19f5f51584de 289 /** USB PLL status lock */
Benoit 0:19f5f51584de 290 #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
Benoit 0:19f5f51584de 291
Benoit 0:19f5f51584de 292 /*********************************************************************//**
Benoit 0:19f5f51584de 293 * Macro defines for PLL1 Feed Register
Benoit 0:19f5f51584de 294 **********************************************************************/
Benoit 0:19f5f51584de 295 /** PLL1 Feed bit mask */
Benoit 0:19f5f51584de 296 #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
Benoit 0:19f5f51584de 297
Benoit 0:19f5f51584de 298 /*********************************************************************//**
Benoit 0:19f5f51584de 299 * Macro defines for CPU Clock Configuration Register
Benoit 0:19f5f51584de 300 **********************************************************************/
Benoit 0:19f5f51584de 301 /** CPU Clock configuration bit mask */
Benoit 0:19f5f51584de 302 #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
Benoit 0:19f5f51584de 303
Benoit 0:19f5f51584de 304 /*********************************************************************//**
Benoit 0:19f5f51584de 305 * Macro defines for USB Clock Configuration Register
Benoit 0:19f5f51584de 306 **********************************************************************/
Benoit 0:19f5f51584de 307 /** USB Clock Configuration bit mask */
Benoit 0:19f5f51584de 308 #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
Benoit 0:19f5f51584de 309
Benoit 0:19f5f51584de 310 /*********************************************************************//**
Benoit 0:19f5f51584de 311 * Macro defines for IRC Trim Register
Benoit 0:19f5f51584de 312 **********************************************************************/
Benoit 0:19f5f51584de 313 /** IRC Trim bit mask */
Benoit 0:19f5f51584de 314 #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
Benoit 0:19f5f51584de 315
Benoit 0:19f5f51584de 316 /*********************************************************************//**
Benoit 0:19f5f51584de 317 * Macro defines for Peripheral Clock Selection Register 0 and 1
Benoit 0:19f5f51584de 318 **********************************************************************/
Benoit 0:19f5f51584de 319 /** Peripheral Clock Selection 0 mask bit */
Benoit 0:19f5f51584de 320 #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
Benoit 0:19f5f51584de 321 /** Peripheral Clock Selection 1 mask bit */
Benoit 0:19f5f51584de 322 #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
Benoit 0:19f5f51584de 323 /** Macro to set peripheral clock of each type
Benoit 0:19f5f51584de 324 * p: position of two bits that hold divider of peripheral clock
Benoit 0:19f5f51584de 325 * n: value of divider of peripheral clock to be set */
Benoit 0:19f5f51584de 326 #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
Benoit 0:19f5f51584de 327 /** Macro to mask peripheral clock of each type */
Benoit 0:19f5f51584de 328 #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
Benoit 0:19f5f51584de 329 /** Macro to get peripheral clock of each type */
Benoit 0:19f5f51584de 330 #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
Benoit 0:19f5f51584de 331
Benoit 0:19f5f51584de 332 /*********************************************************************//**
Benoit 0:19f5f51584de 333 * Macro defines for Power Mode Control Register
Benoit 0:19f5f51584de 334 **********************************************************************/
Benoit 0:19f5f51584de 335 /** Power mode control bit 0 */
Benoit 0:19f5f51584de 336 #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
Benoit 0:19f5f51584de 337 /** Power mode control bit 1 */
Benoit 0:19f5f51584de 338 #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
Benoit 0:19f5f51584de 339 /** Brown-Out Reduced Power Mode */
Benoit 0:19f5f51584de 340 #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
Benoit 0:19f5f51584de 341 /** Brown-Out Global Disable */
Benoit 0:19f5f51584de 342 #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
Benoit 0:19f5f51584de 343 /** Brown Out Reset Disable */
Benoit 0:19f5f51584de 344 #define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
Benoit 0:19f5f51584de 345 /** Sleep Mode entry flag */
Benoit 0:19f5f51584de 346 #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
Benoit 0:19f5f51584de 347 /** Deep Sleep entry flag */
Benoit 0:19f5f51584de 348 #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
Benoit 0:19f5f51584de 349 /** Power-down entry flag */
Benoit 0:19f5f51584de 350 #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
Benoit 0:19f5f51584de 351 /** Deep Power-down entry flag */
Benoit 0:19f5f51584de 352 #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
Benoit 0:19f5f51584de 353
Benoit 0:19f5f51584de 354 /*********************************************************************//**
Benoit 0:19f5f51584de 355 * Macro defines for Power Control for Peripheral Register
Benoit 0:19f5f51584de 356 **********************************************************************/
Benoit 0:19f5f51584de 357 /** Power Control for Peripherals bit mask */
Benoit 0:19f5f51584de 358 #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
Benoit 0:19f5f51584de 359
Benoit 0:19f5f51584de 360 /**
Benoit 0:19f5f51584de 361 * @}
Benoit 0:19f5f51584de 362 */
Benoit 0:19f5f51584de 363
Benoit 0:19f5f51584de 364
Benoit 0:19f5f51584de 365 /* Public Functions ----------------------------------------------------------- */
Benoit 0:19f5f51584de 366 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
Benoit 0:19f5f51584de 367 * @{
Benoit 0:19f5f51584de 368 */
Benoit 0:19f5f51584de 369
Benoit 0:19f5f51584de 370 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
Benoit 0:19f5f51584de 371 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
Benoit 0:19f5f51584de 372 uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
Benoit 0:19f5f51584de 373 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
Benoit 0:19f5f51584de 374 void CLKPWR_Sleep(void);
Benoit 0:19f5f51584de 375 void CLKPWR_DeepSleep(void);
Benoit 0:19f5f51584de 376 void CLKPWR_PowerDown(void);
Benoit 0:19f5f51584de 377 void CLKPWR_DeepPowerDown(void);
Benoit 0:19f5f51584de 378
Benoit 0:19f5f51584de 379 /**
Benoit 0:19f5f51584de 380 * @}
Benoit 0:19f5f51584de 381 */
Benoit 0:19f5f51584de 382
Benoit 0:19f5f51584de 383
Benoit 0:19f5f51584de 384 #ifdef __cplusplus
Benoit 0:19f5f51584de 385 }
Benoit 0:19f5f51584de 386 #endif
Benoit 0:19f5f51584de 387
Benoit 0:19f5f51584de 388 #endif /* LPC17XX_CLKPWR_H_ */
Benoit 0:19f5f51584de 389
Benoit 0:19f5f51584de 390 /**
Benoit 0:19f5f51584de 391 * @}
Benoit 0:19f5f51584de 392 */
Benoit 0:19f5f51584de 393
Benoit 0:19f5f51584de 394 /* --------------------------------- End Of File ------------------------------ */