Thomas SOETE / SimpleLib

Simple mbed library with macros

Dependents:   SimpleTimer SimpleUART SimpleTimer Stoppuhr1

timers.h@19:f4f258dc34cf, 2010-11-17 (annotated)

Committer:
Alkorin
Date:
Wed Nov 17 14:41:39 2010 +0000
Revision:
19:f4f258dc34cf
Parent:
18:aa026d9f7fc0
Child:
20:113941bced4e
Removed leading semicolon to timers\ macros

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Alkorin 15:66150de7876b 1 /*
Alkorin 15:66150de7876b 2 * Copyright or © or Copr. 2010, Thomas SOETE
Alkorin 15:66150de7876b 3 *
Alkorin 15:66150de7876b 4 * Author e-mail: thomas@soete.org
Alkorin 15:66150de7876b 5 * Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
Alkorin 15:66150de7876b 6 *
Alkorin 15:66150de7876b 7 * This software is governed by the CeCILL license under French law and
Alkorin 15:66150de7876b 8 * abiding by the rules of distribution of free software. You can use,
Alkorin 15:66150de7876b 9 * modify and/ or redistribute the software under the terms of the CeCILL
Alkorin 15:66150de7876b 10 * license as circulated by CEA, CNRS and INRIA at the following URL
Alkorin 15:66150de7876b 11 * "http://www.cecill.info".
Alkorin 15:66150de7876b 12 *
Alkorin 15:66150de7876b 13 * As a counterpart to the access to the source code and rights to copy,
Alkorin 15:66150de7876b 14 * modify and redistribute granted by the license, users are provided only
Alkorin 15:66150de7876b 15 * with a limited warranty and the software's author, the holder of the
Alkorin 15:66150de7876b 16 * economic rights, and the successive licensors have only limited
Alkorin 15:66150de7876b 17 * liability.
Alkorin 15:66150de7876b 18 *
Alkorin 15:66150de7876b 19 * In this respect, the user's attention is drawn to the risks associated
Alkorin 15:66150de7876b 20 * with loading, using, modifying and/or developing or reproducing the
Alkorin 15:66150de7876b 21 * software by the user in light of its specific status of free software,
Alkorin 15:66150de7876b 22 * that may mean that it is complicated to manipulate, and that also
Alkorin 15:66150de7876b 23 * therefore means that it is reserved for developers and experienced
Alkorin 15:66150de7876b 24 * professionals having in-depth computer knowledge. Users are therefore
Alkorin 15:66150de7876b 25 * encouraged to load and test the software's suitability as regards their
Alkorin 15:66150de7876b 26 * requirements in conditions enabling the security of their systems and/or
Alkorin 15:66150de7876b 27 * data to be ensured and, more generally, to use and operate it in the
Alkorin 15:66150de7876b 28 * same conditions as regards security.
Alkorin 15:66150de7876b 29 *
Alkorin 15:66150de7876b 30 * The fact that you are presently reading this means that you have had
Alkorin 15:66150de7876b 31 * knowledge of the CeCILL license and that you accept its terms.
Alkorin 15:66150de7876b 32 */
Alkorin 15:66150de7876b 33
Alkorin 18:aa026d9f7fc0 34 #ifndef __SIMPLELIB_TIMERS_H__
Alkorin 18:aa026d9f7fc0 35 #define __SIMPLELIB_TIMERS_H__
Alkorin 15:66150de7876b 36
Alkorin 15:66150de7876b 37 #include "mbed_globals.h"
Alkorin 15:66150de7876b 38 #include "interrupts.h"
Alkorin 15:66150de7876b 39
Alkorin 15:66150de7876b 40 /**********************************
Alkorin 15:66150de7876b 41 * Simple Timers Managment *
Alkorin 15:66150de7876b 42 **********************************
Alkorin 15:66150de7876b 43 * The interrupt handler is : *
Alkorin 15:66150de7876b 44 * TIMERn_INTERRUPT_HANDLER(void) *
Alkorin 15:66150de7876b 45 **********************************/
Alkorin 15:66150de7876b 46
Alkorin 15:66150de7876b 47 /** Registers **/
Alkorin 15:66150de7876b 48 #define TIMER0_BASE (LPC_TIM0)
Alkorin 15:66150de7876b 49 #define TIMER1_BASE (LPC_TIM1)
Alkorin 15:66150de7876b 50 #define TIMER2_BASE (LPC_TIM2)
Alkorin 15:66150de7876b 51 #define TIMER3_BASE (LPC_TIM3)
Alkorin 15:66150de7876b 52 #define TIMER_BASE(timer) TOKENPASTE2(timer,_BASE)
Alkorin 15:66150de7876b 53
Alkorin 15:66150de7876b 54 // Peripheral Clock Selection registers (See 4.7.3 p56)
Alkorin 15:66150de7876b 55 #define TIMER0_PCLK_REG (LPC_SC->PCLKSEL0)
Alkorin 15:66150de7876b 56 #define TIMER1_PCLK_REG (LPC_SC->PCLKSEL0)
Alkorin 15:66150de7876b 57 #define TIMER2_PCLK_REG (LPC_SC->PCLKSEL1)
Alkorin 15:66150de7876b 58 #define TIMER3_PCLK_REG (LPC_SC->PCLKSEL1)
Alkorin 15:66150de7876b 59 #define TIMER_PCLK_REG(timer) TOKENPASTE2(timer,_PCLK_REG)
Alkorin 15:66150de7876b 60
Alkorin 15:66150de7876b 61 #define TIMER0_PCLK_OFFSET 2
Alkorin 15:66150de7876b 62 #define TIMER1_PCLK_OFFSET 4
Alkorin 15:66150de7876b 63 #define TIMER2_PCLK_OFFSET 12
Alkorin 15:66150de7876b 64 #define TIMER3_PCLK_OFFSET 14
Alkorin 15:66150de7876b 65 #define TIMER_PCLK_OFFSET(timer) TOKENPASTE2(timer,_PCLK_OFFSET)
Alkorin 15:66150de7876b 66
Alkorin 15:66150de7876b 67 /** Interrupt handlers **/
Alkorin 15:66150de7876b 68 #define TIMER0_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER0)
Alkorin 15:66150de7876b 69 #define TIMER1_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER1)
Alkorin 15:66150de7876b 70 #define TIMER2_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER2)
Alkorin 15:66150de7876b 71 #define TIMER3_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER3)
Alkorin 15:66150de7876b 72 #define TIMER_INTERRUPT_HANDLER(timer) EXTERN_C void __IRQ TOKENPASTE2(timer,_IRQHandler)
Alkorin 15:66150de7876b 73
Alkorin 15:66150de7876b 74 /** Bits **/
Alkorin 15:66150de7876b 75 // Power Control for Peripherals (PCONP, 4.8.7.1 p63)
Alkorin 15:66150de7876b 76 #define TIMER0_PCONP_BIT 1
Alkorin 15:66150de7876b 77 #define TIMER1_PCONP_BIT 2
Alkorin 15:66150de7876b 78 #define TIMER2_PCONP_BIT 22
Alkorin 15:66150de7876b 79 #define TIMER3_PCONP_BIT 23
Alkorin 15:66150de7876b 80
Alkorin 15:66150de7876b 81 // Match Control Register (TnMCR, 21.6.8 p496)
Alkorin 15:66150de7876b 82 #define MATCH_INTERRUPT 1
Alkorin 15:66150de7876b 83 #define MATCH_RESET 2
Alkorin 15:66150de7876b 84 #define MATCH_STOP 4
Alkorin 15:66150de7876b 85 #define MR0_OFFSET 0
Alkorin 15:66150de7876b 86 #define MR1_OFFSET 3
Alkorin 15:66150de7876b 87 #define MR2_OFFSET 6
Alkorin 15:66150de7876b 88 #define MR3_OFFSET 9
Alkorin 15:66150de7876b 89
Alkorin 15:66150de7876b 90 // Interrupt Register (TnIR, 21.6.1, p493)
Alkorin 15:66150de7876b 91 #define MR0_INT (1U << 0)
Alkorin 15:66150de7876b 92 #define MR1_INT (1U << 1)
Alkorin 15:66150de7876b 93 #define MR2_INT (1U << 2)
Alkorin 15:66150de7876b 94 #define MR3_INT (1U << 3)
Alkorin 15:66150de7876b 95 #define CR0_INT (1U << 4)
Alkorin 15:66150de7876b 96 #define CR1_INT (1U << 5)
Alkorin 15:66150de7876b 97
Alkorin 15:66150de7876b 98 /** Macros **/
Alkorin 15:66150de7876b 99 // Enable TIMERn
Alkorin 19:f4f258dc34cf 100 #define TIMER0_INIT() TIMER_INIT(TIMER0)
Alkorin 19:f4f258dc34cf 101 #define TIMER1_INIT() TIMER_INIT(TIMER1)
Alkorin 19:f4f258dc34cf 102 #define TIMER2_INIT() TIMER_INIT(TIMER2)
Alkorin 19:f4f258dc34cf 103 #define TIMER3_INIT() TIMER_INIT(TIMER3)
Alkorin 19:f4f258dc34cf 104 #define TIMER_INIT(timer) do { \
Alkorin 19:f4f258dc34cf 105 SET_BIT_VALUE(LPC_SC->PCONP, TOKENPASTE2(timer,_PCONP_BIT) , 1); /* Enable Timer */ \
Alkorin 19:f4f258dc34cf 106 TIMER_BASE(timer)->TCR = 0x2; /* Reset Timer, Table 427 p493 */ \
Alkorin 19:f4f258dc34cf 107 } while(0)
Alkorin 15:66150de7876b 108
Alkorin 15:66150de7876b 109 // Set Peripheral Clock
Alkorin 19:f4f258dc34cf 110 #define TIMER0_SETPCLK(clk) TIMER_SETPCLK(TIMER0, clk)
Alkorin 19:f4f258dc34cf 111 #define TIMER1_SETPCLK(clk) TIMER_SETPCLK(TIMER1, clk)
Alkorin 19:f4f258dc34cf 112 #define TIMER2_SETPCLK(clk) TIMER_SETPCLK(TIMER2, clk)
Alkorin 19:f4f258dc34cf 113 #define TIMER3_SETPCLK(clk) TIMER_SETPCLK(TIMER3, clk)
Alkorin 15:66150de7876b 114 #define TIMER_SETPCLK(timer, clk) TIMER_PCLK_REG(timer) = (TIMER_PCLK_REG(timer) & (~(3U << TIMER_PCLK_OFFSET(timer))) | (clk << TIMER_PCLK_OFFSET(timer)))
Alkorin 15:66150de7876b 115
Alkorin 15:66150de7876b 116 // Set Prescale Register
Alkorin 19:f4f258dc34cf 117 #define TIMER0_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER0, value)
Alkorin 19:f4f258dc34cf 118 #define TIMER1_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER1, value)
Alkorin 19:f4f258dc34cf 119 #define TIMER2_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER2, value)
Alkorin 19:f4f258dc34cf 120 #define TIMER3_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER3, value)
Alkorin 19:f4f258dc34cf 121 #define TIMER_SETPRESCALE(timer, value) TIMER_BASE(timer)->PR = (value)
Alkorin 15:66150de7876b 122
Alkorin 15:66150de7876b 123 // Set Match Register (MR0-3, 21.6.7 p496)
Alkorin 19:f4f258dc34cf 124 #define TIMER0_SETMATCH(id, value) TIMER_SETMATCH(TIMER0, id, value)
Alkorin 19:f4f258dc34cf 125 #define TIMER1_SETMATCH(id, value) TIMER_SETMATCH(TIMER1, id, value)
Alkorin 19:f4f258dc34cf 126 #define TIMER2_SETMATCH(id, value) TIMER_SETMATCH(TIMER2, id, value)
Alkorin 19:f4f258dc34cf 127 #define TIMER3_SETMATCH(id, value) TIMER_SETMATCH(TIMER3, id, value)
Alkorin 19:f4f258dc34cf 128 #define TIMER_SETMATCH(timer, id, value) TIMER_BASE(timer)->TOKENPASTE2(MR,id) = (value)
Alkorin 15:66150de7876b 129
Alkorin 15:66150de7876b 130 // Set Match Control Register (TnMCR, 21.6.8 p496)
Alkorin 19:f4f258dc34cf 131 #define TIMER0_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER0, id, value)
Alkorin 19:f4f258dc34cf 132 #define TIMER1_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER1, id, value)
Alkorin 19:f4f258dc34cf 133 #define TIMER2_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER2, id, value)
Alkorin 19:f4f258dc34cf 134 #define TIMER3_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER3, id, value)
Alkorin 19:f4f258dc34cf 135 #define TIMER_SETMATCHCONTROL(timer, id, value) TIMER_BASE(timer)->MCR = (value) << (MR ## id ## _OFFSET)
Alkorin 15:66150de7876b 136
Alkorin 15:66150de7876b 137 // Enable interrupt for TIMERn
Alkorin 19:f4f258dc34cf 138 #define TIMER0_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER0)
Alkorin 19:f4f258dc34cf 139 #define TIMER1_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER1)
Alkorin 19:f4f258dc34cf 140 #define TIMER2_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER2)
Alkorin 19:f4f258dc34cf 141 #define TIMER3_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER3)
Alkorin 19:f4f258dc34cf 142 #define TIMER_ENABLE_INTERRUPT(timer) ENABLE_INTERRUPT(TOKENPASTE2(timer,_IRQn))
Alkorin 15:66150de7876b 143
Alkorin 15:66150de7876b 144 // Interrut Register (TnIR, 21.6.1, p493)
Alkorin 19:f4f258dc34cf 145 #define TIMER0_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER0, value)
Alkorin 19:f4f258dc34cf 146 #define TIMER1_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER1, value)
Alkorin 19:f4f258dc34cf 147 #define TIMER2_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER2, value)
Alkorin 19:f4f258dc34cf 148 #define TIMER3_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER3, value)
Alkorin 19:f4f258dc34cf 149 #define TIMER_CLEAR_INTERRUPT(timer, value) TIMER_BASE(timer)->IR = (value)
Alkorin 15:66150de7876b 150
Alkorin 15:66150de7876b 151 // Start Timer
Alkorin 19:f4f258dc34cf 152 #define TIMER0_START() TIMER_START(TIMER0)
Alkorin 19:f4f258dc34cf 153 #define TIMER1_START() TIMER_START(TIMER1)
Alkorin 19:f4f258dc34cf 154 #define TIMER2_START() TIMER_START(TIMER2)
Alkorin 19:f4f258dc34cf 155 #define TIMER3_START() TIMER_START(TIMER3)
Alkorin 19:f4f258dc34cf 156 #define TIMER_START(timer) TIMER_BASE(timer)->TCR = 0x1 /* Counter Enable, Table 427 p493*/
Alkorin 15:66150de7876b 157
Alkorin 15:66150de7876b 158 // Get Timer Value
Alkorin 19:f4f258dc34cf 159 #define TIMER0_VALUE() TIMER_VALUE(TIMER0)
Alkorin 19:f4f258dc34cf 160 #define TIMER1_VALUE() TIMER_VALUE(TIMER1)
Alkorin 19:f4f258dc34cf 161 #define TIMER2_VALUE() TIMER_VALUE(TIMER2)
Alkorin 19:f4f258dc34cf 162 #define TIMER3_VALUE() TIMER_VALUE(TIMER3)
Alkorin 15:66150de7876b 163 #define TIMER_VALUE(timer) (TIMER_BASE(timer)->TC)
Alkorin 15:66150de7876b 164
Alkorin 15:66150de7876b 165 #endif