Diff: kl25z_clock.cpp

Revision:

0:218e465e76b6

Child:

1:1097467b4352

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/kl25z_clock.cpp	Thu Aug 14 23:34:18 2014 +0000
@@ -0,0 +1,61 @@
+#include <stdint.h>
+#include "MKL25Z4.h"
+
+#include "kl25z_clock.h"
+
+void switchFEItoPEE( void )
+{
+    /* SIM->SCGC5: PORTA=1 */
+    SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
+    /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+    SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
+    /* PORTA->PCR18: ISF=0,MUX=0 */
+    PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+    /* PORTA->PCR19: ISF=0,MUX=0 */
+    PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+    /* Switch to FBE Mode */
+    /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
+    OSC0->CR = (uint8_t)0x89U;
+    /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+    MCG->C2 = (uint8_t)0x24U;
+    /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+    MCG->C1 = (uint8_t)0x9AU;
+    /* MCG->C4: DMX32=0,DRST_DRS=0 */
+    MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+    /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+    MCG->C5 = (uint8_t)0x01U;
+    /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+    MCG->C6 = (uint8_t)0x00U;
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+    }
+    while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+    }
+    /* Switch to PBE Mode */
+    /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
+    MCG->C6 = (uint8_t)0x40U;
+    while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+    }
+    while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
+    }
+    /* Switch to PEE Mode */
+    /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+    MCG->C1 = (uint8_t)0x1AU;
+    while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
+    }
+    
+    /* Run this to get the new system frequency */
+    SystemCoreClockUpdate();
+}
+ 
+void switchPEEtoBLPI( void )
+{
+    MCG->C1 = (uint8_t)0x90U;
+    
+    /* Run this to get the new system frequency */
+    SystemCoreClockUpdate();
+}
+ 
+void switchBLPItoPEE( void )
+{
+    
+}
\ No newline at end of file