jim hamblen
A blink LED demo with power management to reduce power.
PowerControl/EthernetPowerControl.h@0:02d7e850d7cb, 2011-01-28 (annotated)
- Committer:
- 4180_1
- Date:
- Fri Jan 28 17:31:00 2011 +0000
- Revision:
- 0:02d7e850d7cb
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| 4180_1 | 0:02d7e850d7cb | 1 | /* mbed PowerControl Library |
| 4180_1 | 0:02d7e850d7cb | 2 | * Copyright (c) 2010 Michael Wei |
| 4180_1 | 0:02d7e850d7cb | 3 | */ |
| 4180_1 | 0:02d7e850d7cb | 4 | |
| 4180_1 | 0:02d7e850d7cb | 5 | #ifndef MBED_POWERCONTROL_ETH_H |
| 4180_1 | 0:02d7e850d7cb | 6 | #define MBED_POWERCONTROL_ETH_H |
| 4180_1 | 0:02d7e850d7cb | 7 | |
| 4180_1 | 0:02d7e850d7cb | 8 | #include "mbed.h" |
| 4180_1 | 0:02d7e850d7cb | 9 | #include "PowerControl.h" |
| 4180_1 | 0:02d7e850d7cb | 10 | |
| 4180_1 | 0:02d7e850d7cb | 11 | #define PHY_REG_BMCR_POWERDOWN 0xB |
| 4180_1 | 0:02d7e850d7cb | 12 | #define PHY_REG_EDCR_ENABLE 0xF |
| 4180_1 | 0:02d7e850d7cb | 13 | |
| 4180_1 | 0:02d7e850d7cb | 14 | |
| 4180_1 | 0:02d7e850d7cb | 15 | void EMAC_Init(); |
| 4180_1 | 0:02d7e850d7cb | 16 | static unsigned short read_PHY (unsigned int PhyReg); |
| 4180_1 | 0:02d7e850d7cb | 17 | static void write_PHY (unsigned int PhyReg, unsigned short Value); |
| 4180_1 | 0:02d7e850d7cb | 18 | |
| 4180_1 | 0:02d7e850d7cb | 19 | void PHY_PowerDown(void); |
| 4180_1 | 0:02d7e850d7cb | 20 | void PHY_PowerUp(void); |
| 4180_1 | 0:02d7e850d7cb | 21 | void PHY_EnergyDetect_Enable(void); |
| 4180_1 | 0:02d7e850d7cb | 22 | void PHY_EnergyDetect_Disable(void); |
| 4180_1 | 0:02d7e850d7cb | 23 | |
| 4180_1 | 0:02d7e850d7cb | 24 | //From NXP Sample Code .... Probably from KEIL sample code |
| 4180_1 | 0:02d7e850d7cb | 25 | /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ |
| 4180_1 | 0:02d7e850d7cb | 26 | #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ |
| 4180_1 | 0:02d7e850d7cb | 27 | #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ |
| 4180_1 | 0:02d7e850d7cb | 28 | #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ |
| 4180_1 | 0:02d7e850d7cb | 29 | |
| 4180_1 | 0:02d7e850d7cb | 30 | #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ |
| 4180_1 | 0:02d7e850d7cb | 31 | |
| 4180_1 | 0:02d7e850d7cb | 32 | /* EMAC variables located in 16K Ethernet SRAM */ |
| 4180_1 | 0:02d7e850d7cb | 33 | #define RX_DESC_BASE 0x20080000 |
| 4180_1 | 0:02d7e850d7cb | 34 | #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) |
| 4180_1 | 0:02d7e850d7cb | 35 | #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) |
| 4180_1 | 0:02d7e850d7cb | 36 | #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) |
| 4180_1 | 0:02d7e850d7cb | 37 | #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) |
| 4180_1 | 0:02d7e850d7cb | 38 | #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) |
| 4180_1 | 0:02d7e850d7cb | 39 | |
| 4180_1 | 0:02d7e850d7cb | 40 | /* RX and TX descriptor and status definitions. */ |
| 4180_1 | 0:02d7e850d7cb | 41 | #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) |
| 4180_1 | 0:02d7e850d7cb | 42 | #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) |
| 4180_1 | 0:02d7e850d7cb | 43 | #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) |
| 4180_1 | 0:02d7e850d7cb | 44 | #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) |
| 4180_1 | 0:02d7e850d7cb | 45 | #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) |
| 4180_1 | 0:02d7e850d7cb | 46 | #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) |
| 4180_1 | 0:02d7e850d7cb | 47 | #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) |
| 4180_1 | 0:02d7e850d7cb | 48 | #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) |
| 4180_1 | 0:02d7e850d7cb | 49 | #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) |
| 4180_1 | 0:02d7e850d7cb | 50 | |
| 4180_1 | 0:02d7e850d7cb | 51 | /* MAC Configuration Register 1 */ |
| 4180_1 | 0:02d7e850d7cb | 52 | #define MAC1_REC_EN 0x00000001 /* Receive Enable */ |
| 4180_1 | 0:02d7e850d7cb | 53 | #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ |
| 4180_1 | 0:02d7e850d7cb | 54 | #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ |
| 4180_1 | 0:02d7e850d7cb | 55 | #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ |
| 4180_1 | 0:02d7e850d7cb | 56 | #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ |
| 4180_1 | 0:02d7e850d7cb | 57 | #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ |
| 4180_1 | 0:02d7e850d7cb | 58 | #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ |
| 4180_1 | 0:02d7e850d7cb | 59 | #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ |
| 4180_1 | 0:02d7e850d7cb | 60 | #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ |
| 4180_1 | 0:02d7e850d7cb | 61 | #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ |
| 4180_1 | 0:02d7e850d7cb | 62 | #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ |
| 4180_1 | 0:02d7e850d7cb | 63 | |
| 4180_1 | 0:02d7e850d7cb | 64 | /* MAC Configuration Register 2 */ |
| 4180_1 | 0:02d7e850d7cb | 65 | #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ |
| 4180_1 | 0:02d7e850d7cb | 66 | #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ |
| 4180_1 | 0:02d7e850d7cb | 67 | #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ |
| 4180_1 | 0:02d7e850d7cb | 68 | #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ |
| 4180_1 | 0:02d7e850d7cb | 69 | #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ |
| 4180_1 | 0:02d7e850d7cb | 70 | #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ |
| 4180_1 | 0:02d7e850d7cb | 71 | #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ |
| 4180_1 | 0:02d7e850d7cb | 72 | #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ |
| 4180_1 | 0:02d7e850d7cb | 73 | #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ |
| 4180_1 | 0:02d7e850d7cb | 74 | #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ |
| 4180_1 | 0:02d7e850d7cb | 75 | #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ |
| 4180_1 | 0:02d7e850d7cb | 76 | #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ |
| 4180_1 | 0:02d7e850d7cb | 77 | #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ |
| 4180_1 | 0:02d7e850d7cb | 78 | |
| 4180_1 | 0:02d7e850d7cb | 79 | /* Back-to-Back Inter-Packet-Gap Register */ |
| 4180_1 | 0:02d7e850d7cb | 80 | #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ |
| 4180_1 | 0:02d7e850d7cb | 81 | #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ |
| 4180_1 | 0:02d7e850d7cb | 82 | |
| 4180_1 | 0:02d7e850d7cb | 83 | /* Non Back-to-Back Inter-Packet-Gap Register */ |
| 4180_1 | 0:02d7e850d7cb | 84 | #define IPGR_DEF 0x00000012 /* Recommended value */ |
| 4180_1 | 0:02d7e850d7cb | 85 | |
| 4180_1 | 0:02d7e850d7cb | 86 | /* Collision Window/Retry Register */ |
| 4180_1 | 0:02d7e850d7cb | 87 | #define CLRT_DEF 0x0000370F /* Default value */ |
| 4180_1 | 0:02d7e850d7cb | 88 | |
| 4180_1 | 0:02d7e850d7cb | 89 | /* PHY Support Register */ |
| 4180_1 | 0:02d7e850d7cb | 90 | #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ |
| 4180_1 | 0:02d7e850d7cb | 91 | #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ |
| 4180_1 | 0:02d7e850d7cb | 92 | |
| 4180_1 | 0:02d7e850d7cb | 93 | /* Test Register */ |
| 4180_1 | 0:02d7e850d7cb | 94 | #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ |
| 4180_1 | 0:02d7e850d7cb | 95 | #define TEST_TST_PAUSE 0x00000002 /* Test Pause */ |
| 4180_1 | 0:02d7e850d7cb | 96 | #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ |
| 4180_1 | 0:02d7e850d7cb | 97 | |
| 4180_1 | 0:02d7e850d7cb | 98 | /* MII Management Configuration Register */ |
| 4180_1 | 0:02d7e850d7cb | 99 | #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ |
| 4180_1 | 0:02d7e850d7cb | 100 | #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ |
| 4180_1 | 0:02d7e850d7cb | 101 | #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ |
| 4180_1 | 0:02d7e850d7cb | 102 | #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ |
| 4180_1 | 0:02d7e850d7cb | 103 | |
| 4180_1 | 0:02d7e850d7cb | 104 | /* MII Management Command Register */ |
| 4180_1 | 0:02d7e850d7cb | 105 | #define MCMD_READ 0x00000001 /* MII Read */ |
| 4180_1 | 0:02d7e850d7cb | 106 | #define MCMD_SCAN 0x00000002 /* MII Scan continuously */ |
| 4180_1 | 0:02d7e850d7cb | 107 | |
| 4180_1 | 0:02d7e850d7cb | 108 | #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ |
| 4180_1 | 0:02d7e850d7cb | 109 | #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ |
| 4180_1 | 0:02d7e850d7cb | 110 | |
| 4180_1 | 0:02d7e850d7cb | 111 | /* MII Management Address Register */ |
| 4180_1 | 0:02d7e850d7cb | 112 | #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ |
| 4180_1 | 0:02d7e850d7cb | 113 | #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ |
| 4180_1 | 0:02d7e850d7cb | 114 | |
| 4180_1 | 0:02d7e850d7cb | 115 | /* MII Management Indicators Register */ |
| 4180_1 | 0:02d7e850d7cb | 116 | #define MIND_BUSY 0x00000001 /* MII is Busy */ |
| 4180_1 | 0:02d7e850d7cb | 117 | #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ |
| 4180_1 | 0:02d7e850d7cb | 118 | #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ |
| 4180_1 | 0:02d7e850d7cb | 119 | #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ |
| 4180_1 | 0:02d7e850d7cb | 120 | |
| 4180_1 | 0:02d7e850d7cb | 121 | /* Command Register */ |
| 4180_1 | 0:02d7e850d7cb | 122 | #define CR_RX_EN 0x00000001 /* Enable Receive */ |
| 4180_1 | 0:02d7e850d7cb | 123 | #define CR_TX_EN 0x00000002 /* Enable Transmit */ |
| 4180_1 | 0:02d7e850d7cb | 124 | #define CR_REG_RES 0x00000008 /* Reset Host Registers */ |
| 4180_1 | 0:02d7e850d7cb | 125 | #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ |
| 4180_1 | 0:02d7e850d7cb | 126 | #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ |
| 4180_1 | 0:02d7e850d7cb | 127 | #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ |
| 4180_1 | 0:02d7e850d7cb | 128 | #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ |
| 4180_1 | 0:02d7e850d7cb | 129 | #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ |
| 4180_1 | 0:02d7e850d7cb | 130 | #define CR_RMII 0x00000200 /* Reduced MII Interface */ |
| 4180_1 | 0:02d7e850d7cb | 131 | #define CR_FULL_DUP 0x00000400 /* Full Duplex */ |
| 4180_1 | 0:02d7e850d7cb | 132 | |
| 4180_1 | 0:02d7e850d7cb | 133 | /* Status Register */ |
| 4180_1 | 0:02d7e850d7cb | 134 | #define SR_RX_EN 0x00000001 /* Enable Receive */ |
| 4180_1 | 0:02d7e850d7cb | 135 | #define SR_TX_EN 0x00000002 /* Enable Transmit */ |
| 4180_1 | 0:02d7e850d7cb | 136 | |
| 4180_1 | 0:02d7e850d7cb | 137 | /* Transmit Status Vector 0 Register */ |
| 4180_1 | 0:02d7e850d7cb | 138 | #define TSV0_CRC_ERR 0x00000001 /* CRC error */ |
| 4180_1 | 0:02d7e850d7cb | 139 | #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ |
| 4180_1 | 0:02d7e850d7cb | 140 | #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ |
| 4180_1 | 0:02d7e850d7cb | 141 | #define TSV0_DONE 0x00000008 /* Tramsmission Completed */ |
| 4180_1 | 0:02d7e850d7cb | 142 | #define TSV0_MCAST 0x00000010 /* Multicast Destination */ |
| 4180_1 | 0:02d7e850d7cb | 143 | #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ |
| 4180_1 | 0:02d7e850d7cb | 144 | #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ |
| 4180_1 | 0:02d7e850d7cb | 145 | #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ |
| 4180_1 | 0:02d7e850d7cb | 146 | #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ |
| 4180_1 | 0:02d7e850d7cb | 147 | #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ |
| 4180_1 | 0:02d7e850d7cb | 148 | #define TSV0_GIANT 0x00000400 /* Giant Frame */ |
| 4180_1 | 0:02d7e850d7cb | 149 | #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ |
| 4180_1 | 0:02d7e850d7cb | 150 | #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ |
| 4180_1 | 0:02d7e850d7cb | 151 | #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ |
| 4180_1 | 0:02d7e850d7cb | 152 | #define TSV0_PAUSE 0x20000000 /* Pause Frame */ |
| 4180_1 | 0:02d7e850d7cb | 153 | #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ |
| 4180_1 | 0:02d7e850d7cb | 154 | #define TSV0_VLAN 0x80000000 /* VLAN Frame */ |
| 4180_1 | 0:02d7e850d7cb | 155 | |
| 4180_1 | 0:02d7e850d7cb | 156 | /* Transmit Status Vector 1 Register */ |
| 4180_1 | 0:02d7e850d7cb | 157 | #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ |
| 4180_1 | 0:02d7e850d7cb | 158 | #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ |
| 4180_1 | 0:02d7e850d7cb | 159 | |
| 4180_1 | 0:02d7e850d7cb | 160 | /* Receive Status Vector Register */ |
| 4180_1 | 0:02d7e850d7cb | 161 | #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ |
| 4180_1 | 0:02d7e850d7cb | 162 | #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ |
| 4180_1 | 0:02d7e850d7cb | 163 | #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ |
| 4180_1 | 0:02d7e850d7cb | 164 | #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ |
| 4180_1 | 0:02d7e850d7cb | 165 | #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ |
| 4180_1 | 0:02d7e850d7cb | 166 | #define RSV_CRC_ERR 0x00100000 /* CRC Error */ |
| 4180_1 | 0:02d7e850d7cb | 167 | #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ |
| 4180_1 | 0:02d7e850d7cb | 168 | #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ |
| 4180_1 | 0:02d7e850d7cb | 169 | #define RSV_REC_OK 0x00800000 /* Frame Received OK */ |
| 4180_1 | 0:02d7e850d7cb | 170 | #define RSV_MCAST 0x01000000 /* Multicast Frame */ |
| 4180_1 | 0:02d7e850d7cb | 171 | #define RSV_BCAST 0x02000000 /* Broadcast Frame */ |
| 4180_1 | 0:02d7e850d7cb | 172 | #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ |
| 4180_1 | 0:02d7e850d7cb | 173 | #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ |
| 4180_1 | 0:02d7e850d7cb | 174 | #define RSV_PAUSE 0x10000000 /* Pause Frame */ |
| 4180_1 | 0:02d7e850d7cb | 175 | #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ |
| 4180_1 | 0:02d7e850d7cb | 176 | #define RSV_VLAN 0x40000000 /* VLAN Frame */ |
| 4180_1 | 0:02d7e850d7cb | 177 | |
| 4180_1 | 0:02d7e850d7cb | 178 | /* Flow Control Counter Register */ |
| 4180_1 | 0:02d7e850d7cb | 179 | #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ |
| 4180_1 | 0:02d7e850d7cb | 180 | #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ |
| 4180_1 | 0:02d7e850d7cb | 181 | |
| 4180_1 | 0:02d7e850d7cb | 182 | /* Flow Control Status Register */ |
| 4180_1 | 0:02d7e850d7cb | 183 | #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ |
| 4180_1 | 0:02d7e850d7cb | 184 | |
| 4180_1 | 0:02d7e850d7cb | 185 | /* Receive Filter Control Register */ |
| 4180_1 | 0:02d7e850d7cb | 186 | #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ |
| 4180_1 | 0:02d7e850d7cb | 187 | #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ |
| 4180_1 | 0:02d7e850d7cb | 188 | #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ |
| 4180_1 | 0:02d7e850d7cb | 189 | #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ |
| 4180_1 | 0:02d7e850d7cb | 190 | #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ |
| 4180_1 | 0:02d7e850d7cb | 191 | #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ |
| 4180_1 | 0:02d7e850d7cb | 192 | #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ |
| 4180_1 | 0:02d7e850d7cb | 193 | #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ |
| 4180_1 | 0:02d7e850d7cb | 194 | |
| 4180_1 | 0:02d7e850d7cb | 195 | /* Receive Filter WoL Status/Clear Registers */ |
| 4180_1 | 0:02d7e850d7cb | 196 | #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ |
| 4180_1 | 0:02d7e850d7cb | 197 | #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ |
| 4180_1 | 0:02d7e850d7cb | 198 | #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ |
| 4180_1 | 0:02d7e850d7cb | 199 | #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ |
| 4180_1 | 0:02d7e850d7cb | 200 | #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ |
| 4180_1 | 0:02d7e850d7cb | 201 | #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ |
| 4180_1 | 0:02d7e850d7cb | 202 | #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ |
| 4180_1 | 0:02d7e850d7cb | 203 | #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ |
| 4180_1 | 0:02d7e850d7cb | 204 | |
| 4180_1 | 0:02d7e850d7cb | 205 | /* Interrupt Status/Enable/Clear/Set Registers */ |
| 4180_1 | 0:02d7e850d7cb | 206 | #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ |
| 4180_1 | 0:02d7e850d7cb | 207 | #define INT_RX_ERR 0x00000002 /* Receive Error */ |
| 4180_1 | 0:02d7e850d7cb | 208 | #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ |
| 4180_1 | 0:02d7e850d7cb | 209 | #define INT_RX_DONE 0x00000008 /* Receive Done */ |
| 4180_1 | 0:02d7e850d7cb | 210 | #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ |
| 4180_1 | 0:02d7e850d7cb | 211 | #define INT_TX_ERR 0x00000020 /* Transmit Error */ |
| 4180_1 | 0:02d7e850d7cb | 212 | #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ |
| 4180_1 | 0:02d7e850d7cb | 213 | #define INT_TX_DONE 0x00000080 /* Transmit Done */ |
| 4180_1 | 0:02d7e850d7cb | 214 | #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ |
| 4180_1 | 0:02d7e850d7cb | 215 | #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ |
| 4180_1 | 0:02d7e850d7cb | 216 | |
| 4180_1 | 0:02d7e850d7cb | 217 | /* Power Down Register */ |
| 4180_1 | 0:02d7e850d7cb | 218 | #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ |
| 4180_1 | 0:02d7e850d7cb | 219 | |
| 4180_1 | 0:02d7e850d7cb | 220 | /* RX Descriptor Control Word */ |
| 4180_1 | 0:02d7e850d7cb | 221 | #define RCTRL_SIZE 0x000007FF /* Buffer size mask */ |
| 4180_1 | 0:02d7e850d7cb | 222 | #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ |
| 4180_1 | 0:02d7e850d7cb | 223 | |
| 4180_1 | 0:02d7e850d7cb | 224 | /* RX Status Hash CRC Word */ |
| 4180_1 | 0:02d7e850d7cb | 225 | #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ |
| 4180_1 | 0:02d7e850d7cb | 226 | #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ |
| 4180_1 | 0:02d7e850d7cb | 227 | |
| 4180_1 | 0:02d7e850d7cb | 228 | /* RX Status Information Word */ |
| 4180_1 | 0:02d7e850d7cb | 229 | #define RINFO_SIZE 0x000007FF /* Data size in bytes */ |
| 4180_1 | 0:02d7e850d7cb | 230 | #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ |
| 4180_1 | 0:02d7e850d7cb | 231 | #define RINFO_VLAN 0x00080000 /* VLAN Frame */ |
| 4180_1 | 0:02d7e850d7cb | 232 | #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ |
| 4180_1 | 0:02d7e850d7cb | 233 | #define RINFO_MCAST 0x00200000 /* Multicast Frame */ |
| 4180_1 | 0:02d7e850d7cb | 234 | #define RINFO_BCAST 0x00400000 /* Broadcast Frame */ |
| 4180_1 | 0:02d7e850d7cb | 235 | #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ |
| 4180_1 | 0:02d7e850d7cb | 236 | #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ |
| 4180_1 | 0:02d7e850d7cb | 237 | #define RINFO_LEN_ERR 0x02000000 /* Length Error */ |
| 4180_1 | 0:02d7e850d7cb | 238 | #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ |
| 4180_1 | 0:02d7e850d7cb | 239 | #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ |
| 4180_1 | 0:02d7e850d7cb | 240 | #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ |
| 4180_1 | 0:02d7e850d7cb | 241 | #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ |
| 4180_1 | 0:02d7e850d7cb | 242 | #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ |
| 4180_1 | 0:02d7e850d7cb | 243 | #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
| 4180_1 | 0:02d7e850d7cb | 244 | |
| 4180_1 | 0:02d7e850d7cb | 245 | #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ |
| 4180_1 | 0:02d7e850d7cb | 246 | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) |
| 4180_1 | 0:02d7e850d7cb | 247 | |
| 4180_1 | 0:02d7e850d7cb | 248 | /* TX Descriptor Control Word */ |
| 4180_1 | 0:02d7e850d7cb | 249 | #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ |
| 4180_1 | 0:02d7e850d7cb | 250 | #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ |
| 4180_1 | 0:02d7e850d7cb | 251 | #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ |
| 4180_1 | 0:02d7e850d7cb | 252 | #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ |
| 4180_1 | 0:02d7e850d7cb | 253 | #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ |
| 4180_1 | 0:02d7e850d7cb | 254 | #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ |
| 4180_1 | 0:02d7e850d7cb | 255 | #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ |
| 4180_1 | 0:02d7e850d7cb | 256 | |
| 4180_1 | 0:02d7e850d7cb | 257 | /* TX Status Information Word */ |
| 4180_1 | 0:02d7e850d7cb | 258 | #define TINFO_COL_CNT 0x01E00000 /* Collision Count */ |
| 4180_1 | 0:02d7e850d7cb | 259 | #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ |
| 4180_1 | 0:02d7e850d7cb | 260 | #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ |
| 4180_1 | 0:02d7e850d7cb | 261 | #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ |
| 4180_1 | 0:02d7e850d7cb | 262 | #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ |
| 4180_1 | 0:02d7e850d7cb | 263 | #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ |
| 4180_1 | 0:02d7e850d7cb | 264 | #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ |
| 4180_1 | 0:02d7e850d7cb | 265 | #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
| 4180_1 | 0:02d7e850d7cb | 266 | |
| 4180_1 | 0:02d7e850d7cb | 267 | /* DP83848C PHY Registers */ |
| 4180_1 | 0:02d7e850d7cb | 268 | #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ |
| 4180_1 | 0:02d7e850d7cb | 269 | #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ |
| 4180_1 | 0:02d7e850d7cb | 270 | #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ |
| 4180_1 | 0:02d7e850d7cb | 271 | #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ |
| 4180_1 | 0:02d7e850d7cb | 272 | #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ |
| 4180_1 | 0:02d7e850d7cb | 273 | #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ |
| 4180_1 | 0:02d7e850d7cb | 274 | #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ |
| 4180_1 | 0:02d7e850d7cb | 275 | #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ |
| 4180_1 | 0:02d7e850d7cb | 276 | |
| 4180_1 | 0:02d7e850d7cb | 277 | /* PHY Extended Registers */ |
| 4180_1 | 0:02d7e850d7cb | 278 | #define PHY_REG_STS 0x10 /* Status Register */ |
| 4180_1 | 0:02d7e850d7cb | 279 | #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ |
| 4180_1 | 0:02d7e850d7cb | 280 | #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ |
| 4180_1 | 0:02d7e850d7cb | 281 | #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ |
| 4180_1 | 0:02d7e850d7cb | 282 | #define PHY_REG_RECR 0x15 /* Receive Error Counter */ |
| 4180_1 | 0:02d7e850d7cb | 283 | #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ |
| 4180_1 | 0:02d7e850d7cb | 284 | #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ |
| 4180_1 | 0:02d7e850d7cb | 285 | #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ |
| 4180_1 | 0:02d7e850d7cb | 286 | #define PHY_REG_PHYCR 0x19 /* PHY Control Register */ |
| 4180_1 | 0:02d7e850d7cb | 287 | #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ |
| 4180_1 | 0:02d7e850d7cb | 288 | #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ |
| 4180_1 | 0:02d7e850d7cb | 289 | #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ |
| 4180_1 | 0:02d7e850d7cb | 290 | |
| 4180_1 | 0:02d7e850d7cb | 291 | #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ |
| 4180_1 | 0:02d7e850d7cb | 292 | #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ |
| 4180_1 | 0:02d7e850d7cb | 293 | #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ |
| 4180_1 | 0:02d7e850d7cb | 294 | #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ |
| 4180_1 | 0:02d7e850d7cb | 295 | #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ |
| 4180_1 | 0:02d7e850d7cb | 296 | |
| 4180_1 | 0:02d7e850d7cb | 297 | #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ |
| 4180_1 | 0:02d7e850d7cb | 298 | #define DP83848C_ID 0x20005C90 /* PHY Identifier */ |
| 4180_1 | 0:02d7e850d7cb | 299 | #endif |