PowerReduceDemo - A blink LED demo with power management to reduce …

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jim hamblen / Mbed 2 deprecated PowerReduceDemo

A blink LED demo with power management to reduce power.

PowerControl/EthernetPowerControl.cpp@0:02d7e850d7cb, 2011-01-28 (annotated)

Committer:: 4180_1
Date:: Fri Jan 28 17:31:00 2011 +0000
Revision:: 0:02d7e850d7cb

Who changed what in which revision?

User	Revision	Line number	New contents of line
4180_1	0:02d7e850d7cb	1	#include "EthernetPowerControl.h"
4180_1	0:02d7e850d7cb	2
4180_1	0:02d7e850d7cb	3	static void write_PHY (unsigned int PhyReg, unsigned short Value) {
4180_1	0:02d7e850d7cb	4	/* Write a data 'Value' to PHY register 'PhyReg'. */
4180_1	0:02d7e850d7cb	5	unsigned int tout;
4180_1	0:02d7e850d7cb	6	/* Hardware MII Management for LPC176x devices. */
4180_1	0:02d7e850d7cb	7	LPC_EMAC->MADR = DP83848C_DEF_ADR \| PhyReg;
4180_1	0:02d7e850d7cb	8	LPC_EMAC->MWTD = Value;
4180_1	0:02d7e850d7cb	9
4180_1	0:02d7e850d7cb	10	/* Wait utill operation completed */
4180_1	0:02d7e850d7cb	11	for (tout = 0; tout < MII_WR_TOUT; tout++) {
4180_1	0:02d7e850d7cb	12	if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
4180_1	0:02d7e850d7cb	13	break;
4180_1	0:02d7e850d7cb	14	}
4180_1	0:02d7e850d7cb	15	}
4180_1	0:02d7e850d7cb	16	}
4180_1	0:02d7e850d7cb	17
4180_1	0:02d7e850d7cb	18	static unsigned short read_PHY (unsigned int PhyReg) {
4180_1	0:02d7e850d7cb	19	/* Read a PHY register 'PhyReg'. */
4180_1	0:02d7e850d7cb	20	unsigned int tout, val;
4180_1	0:02d7e850d7cb	21
4180_1	0:02d7e850d7cb	22	LPC_EMAC->MADR = DP83848C_DEF_ADR \| PhyReg;
4180_1	0:02d7e850d7cb	23	LPC_EMAC->MCMD = MCMD_READ;
4180_1	0:02d7e850d7cb	24
4180_1	0:02d7e850d7cb	25	/* Wait until operation completed */
4180_1	0:02d7e850d7cb	26	for (tout = 0; tout < MII_RD_TOUT; tout++) {
4180_1	0:02d7e850d7cb	27	if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
4180_1	0:02d7e850d7cb	28	break;
4180_1	0:02d7e850d7cb	29	}
4180_1	0:02d7e850d7cb	30	}
4180_1	0:02d7e850d7cb	31	LPC_EMAC->MCMD = 0;
4180_1	0:02d7e850d7cb	32	val = LPC_EMAC->MRDD;
4180_1	0:02d7e850d7cb	33
4180_1	0:02d7e850d7cb	34	return (val);
4180_1	0:02d7e850d7cb	35	}
4180_1	0:02d7e850d7cb	36
4180_1	0:02d7e850d7cb	37	void EMAC_Init()
4180_1	0:02d7e850d7cb	38	{
4180_1	0:02d7e850d7cb	39	unsigned int tout,regv;
4180_1	0:02d7e850d7cb	40	/* Power Up the EMAC controller. */
4180_1	0:02d7e850d7cb	41	Peripheral_PowerUp(LPC1768_PCONP_PCENET);
4180_1	0:02d7e850d7cb	42
4180_1	0:02d7e850d7cb	43	LPC_PINCON->PINSEL2 = 0x50150105;
4180_1	0:02d7e850d7cb	44	LPC_PINCON->PINSEL3 &= ~0x0000000F;
4180_1	0:02d7e850d7cb	45	LPC_PINCON->PINSEL3 \|= 0x00000005;
4180_1	0:02d7e850d7cb	46
4180_1	0:02d7e850d7cb	47	/* Reset all EMAC internal modules. */
4180_1	0:02d7e850d7cb	48	LPC_EMAC->MAC1 = MAC1_RES_TX \| MAC1_RES_MCS_TX \| MAC1_RES_RX \| MAC1_RES_MCS_RX \|
4180_1	0:02d7e850d7cb	49	MAC1_SIM_RES \| MAC1_SOFT_RES;
4180_1	0:02d7e850d7cb	50	LPC_EMAC->Command = CR_REG_RES \| CR_TX_RES \| CR_RX_RES;
4180_1	0:02d7e850d7cb	51
4180_1	0:02d7e850d7cb	52	/* A short delay after reset. */
4180_1	0:02d7e850d7cb	53	for (tout = 100; tout; tout--);
4180_1	0:02d7e850d7cb	54
4180_1	0:02d7e850d7cb	55	/* Initialize MAC control registers. */
4180_1	0:02d7e850d7cb	56	LPC_EMAC->MAC1 = MAC1_PASS_ALL;
4180_1	0:02d7e850d7cb	57	LPC_EMAC->MAC2 = MAC2_CRC_EN \| MAC2_PAD_EN;
4180_1	0:02d7e850d7cb	58	LPC_EMAC->MAXF = ETH_MAX_FLEN;
4180_1	0:02d7e850d7cb	59	LPC_EMAC->CLRT = CLRT_DEF;
4180_1	0:02d7e850d7cb	60	LPC_EMAC->IPGR = IPGR_DEF;
4180_1	0:02d7e850d7cb	61
4180_1	0:02d7e850d7cb	62	/* Enable Reduced MII interface. */
4180_1	0:02d7e850d7cb	63	LPC_EMAC->Command = CR_RMII \| CR_PASS_RUNT_FRM;
4180_1	0:02d7e850d7cb	64
4180_1	0:02d7e850d7cb	65	/* Reset Reduced MII Logic. */
4180_1	0:02d7e850d7cb	66	LPC_EMAC->SUPP = SUPP_RES_RMII;
4180_1	0:02d7e850d7cb	67	for (tout = 100; tout; tout--);
4180_1	0:02d7e850d7cb	68	LPC_EMAC->SUPP = 0;
4180_1	0:02d7e850d7cb	69
4180_1	0:02d7e850d7cb	70	/* Put the DP83848C in reset mode */
4180_1	0:02d7e850d7cb	71	write_PHY (PHY_REG_BMCR, 0x8000);
4180_1	0:02d7e850d7cb	72
4180_1	0:02d7e850d7cb	73	/* Wait for hardware reset to end. */
4180_1	0:02d7e850d7cb	74	for (tout = 0; tout < 0x100000; tout++) {
4180_1	0:02d7e850d7cb	75	regv = read_PHY (PHY_REG_BMCR);
4180_1	0:02d7e850d7cb	76	if (!(regv & 0x8000)) {
4180_1	0:02d7e850d7cb	77	/* Reset complete */
4180_1	0:02d7e850d7cb	78	break;
4180_1	0:02d7e850d7cb	79	}
4180_1	0:02d7e850d7cb	80	}
4180_1	0:02d7e850d7cb	81	}
4180_1	0:02d7e850d7cb	82
4180_1	0:02d7e850d7cb	83
4180_1	0:02d7e850d7cb	84	void PHY_PowerDown()
4180_1	0:02d7e850d7cb	85	{
4180_1	0:02d7e850d7cb	86	if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
4180_1	0:02d7e850d7cb	87	EMAC_Init(); //init EMAC if it is not already init'd
4180_1	0:02d7e850d7cb	88
4180_1	0:02d7e850d7cb	89	unsigned int regv;
4180_1	0:02d7e850d7cb	90	regv = read_PHY(PHY_REG_BMCR);
4180_1	0:02d7e850d7cb	91	write_PHY(PHY_REG_BMCR, regv \| (1 << PHY_REG_BMCR_POWERDOWN));
4180_1	0:02d7e850d7cb	92	regv = read_PHY(PHY_REG_BMCR);
4180_1	0:02d7e850d7cb	93
4180_1	0:02d7e850d7cb	94	//shouldn't need the EMAC now.
4180_1	0:02d7e850d7cb	95	Peripheral_PowerDown(LPC1768_PCONP_PCENET);
4180_1	0:02d7e850d7cb	96
4180_1	0:02d7e850d7cb	97	//and turn off the PHY OSC
4180_1	0:02d7e850d7cb	98	LPC_GPIO1->FIODIR \|= 0x8000000;
4180_1	0:02d7e850d7cb	99	LPC_GPIO1->FIOCLR = 0x8000000;
4180_1	0:02d7e850d7cb	100	}
4180_1	0:02d7e850d7cb	101
4180_1	0:02d7e850d7cb	102	void PHY_PowerUp()
4180_1	0:02d7e850d7cb	103	{
4180_1	0:02d7e850d7cb	104	if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
4180_1	0:02d7e850d7cb	105	EMAC_Init(); //init EMAC if it is not already init'd
4180_1	0:02d7e850d7cb	106
4180_1	0:02d7e850d7cb	107	LPC_GPIO1->FIODIR \|= 0x8000000;
4180_1	0:02d7e850d7cb	108	LPC_GPIO1->FIOSET = 0x8000000;
4180_1	0:02d7e850d7cb	109
4180_1	0:02d7e850d7cb	110	//wait for osc to be stable
4180_1	0:02d7e850d7cb	111	wait_ms(200);
4180_1	0:02d7e850d7cb	112
4180_1	0:02d7e850d7cb	113	unsigned int regv;
4180_1	0:02d7e850d7cb	114	regv = read_PHY(PHY_REG_BMCR);
4180_1	0:02d7e850d7cb	115	write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
4180_1	0:02d7e850d7cb	116	regv = read_PHY(PHY_REG_BMCR);
4180_1	0:02d7e850d7cb	117	}
4180_1	0:02d7e850d7cb	118
4180_1	0:02d7e850d7cb	119	void PHY_EnergyDetect_Enable()
4180_1	0:02d7e850d7cb	120	{
4180_1	0:02d7e850d7cb	121	if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
4180_1	0:02d7e850d7cb	122	EMAC_Init(); //init EMAC if it is not already init'd
4180_1	0:02d7e850d7cb	123
4180_1	0:02d7e850d7cb	124	unsigned int regv;
4180_1	0:02d7e850d7cb	125	regv = read_PHY(PHY_REG_EDCR);
4180_1	0:02d7e850d7cb	126	write_PHY(PHY_REG_BMCR, regv \| (1 << PHY_REG_EDCR_ENABLE));
4180_1	0:02d7e850d7cb	127	regv = read_PHY(PHY_REG_EDCR);
4180_1	0:02d7e850d7cb	128	}
4180_1	0:02d7e850d7cb	129
4180_1	0:02d7e850d7cb	130	void PHY_EnergyDetect_Disable()
4180_1	0:02d7e850d7cb	131	{
4180_1	0:02d7e850d7cb	132	if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
4180_1	0:02d7e850d7cb	133	EMAC_Init(); //init EMAC if it is not already init'd
4180_1	0:02d7e850d7cb	134	unsigned int regv;
4180_1	0:02d7e850d7cb	135	regv = read_PHY(PHY_REG_EDCR);
4180_1	0:02d7e850d7cb	136	write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
4180_1	0:02d7e850d7cb	137	regv = read_PHY(PHY_REG_EDCR);
4180_1	0:02d7e850d7cb	138	}

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	28 Jan 2011
Imports:	47
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	4

PowerControl/EthernetPowerControl.cpp@0:02d7e850d7cb, 2011-01-28 (annotated)

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