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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_fsmc.c@106:ced8cbb51063, 2014-02-26 (annotated)

Committer:
mbed_official
Date:
Wed Feb 26 09:45:12 2014 +0000
Revision:
106:ced8cbb51063
Parent:
80:66393a7b209d 
Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd



Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/



[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 76:aeb1df146756 1 /**
mbed_official 76:aeb1df146756 2 ******************************************************************************
mbed_official 76:aeb1df146756 3 * @file stm32l1xx_fsmc.c
mbed_official 76:aeb1df146756 4 * @author MCD Application Team
mbed_official 80:66393a7b209d 5 * @version V1.3.0
mbed_official 80:66393a7b209d 6 * @date 31-January-2014
mbed_official 76:aeb1df146756 7 * @brief This file provides firmware functions to manage the following
mbed_official 76:aeb1df146756 8 * functionalities of the FSMC peripheral:
mbed_official 76:aeb1df146756 9 * + Initialization
mbed_official 76:aeb1df146756 10 * + Interrupts and flags management
mbed_official 76:aeb1df146756 11 *
mbed_official 76:aeb1df146756 12 ******************************************************************************
mbed_official 76:aeb1df146756 13 * @attention
mbed_official 76:aeb1df146756 14 *
mbed_official 106:ced8cbb51063 15 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 76:aeb1df146756 16 *
mbed_official 106:ced8cbb51063 17 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 106:ced8cbb51063 18 * are permitted provided that the following conditions are met:
mbed_official 106:ced8cbb51063 19 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 106:ced8cbb51063 20 * this list of conditions and the following disclaimer.
mbed_official 106:ced8cbb51063 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 106:ced8cbb51063 22 * this list of conditions and the following disclaimer in the documentation
mbed_official 106:ced8cbb51063 23 * and/or other materials provided with the distribution.
mbed_official 106:ced8cbb51063 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 106:ced8cbb51063 25 * may be used to endorse or promote products derived from this software
mbed_official 106:ced8cbb51063 26 * without specific prior written permission.
mbed_official 76:aeb1df146756 27 *
mbed_official 106:ced8cbb51063 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 106:ced8cbb51063 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 106:ced8cbb51063 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 106:ced8cbb51063 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 106:ced8cbb51063 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 106:ced8cbb51063 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 106:ced8cbb51063 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 106:ced8cbb51063 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 106:ced8cbb51063 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 106:ced8cbb51063 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 76:aeb1df146756 38 *
mbed_official 76:aeb1df146756 39 ******************************************************************************
mbed_official 76:aeb1df146756 40 */
mbed_official 76:aeb1df146756 41
mbed_official 76:aeb1df146756 42 /* Includes ------------------------------------------------------------------*/
mbed_official 76:aeb1df146756 43 #include "stm32l1xx_fsmc.h"
mbed_official 76:aeb1df146756 44 #include "stm32l1xx_rcc.h"
mbed_official 76:aeb1df146756 45
mbed_official 76:aeb1df146756 46 /** @addtogroup STM32L1xx_StdPeriph_Driver
mbed_official 76:aeb1df146756 47 * @{
mbed_official 76:aeb1df146756 48 */
mbed_official 76:aeb1df146756 49
mbed_official 76:aeb1df146756 50 /** @defgroup FSMC
mbed_official 76:aeb1df146756 51 * @brief FSMC driver modules
mbed_official 76:aeb1df146756 52 * @{
mbed_official 76:aeb1df146756 53 */
mbed_official 76:aeb1df146756 54
mbed_official 76:aeb1df146756 55 /* Private typedef -----------------------------------------------------------*/
mbed_official 76:aeb1df146756 56 /* Private define ------------------------------------------------------------*/
mbed_official 76:aeb1df146756 57 /* Private macro -------------------------------------------------------------*/
mbed_official 76:aeb1df146756 58 /* Private variables ---------------------------------------------------------*/
mbed_official 76:aeb1df146756 59 /* Private function prototypes -----------------------------------------------*/
mbed_official 76:aeb1df146756 60 /* Private functions ---------------------------------------------------------*/
mbed_official 76:aeb1df146756 61
mbed_official 76:aeb1df146756 62 /** @defgroup FSMC_Private_Functions
mbed_official 76:aeb1df146756 63 * @{
mbed_official 76:aeb1df146756 64 */
mbed_official 76:aeb1df146756 65
mbed_official 76:aeb1df146756 66 /** @defgroup FSMC_Group1 NOR/SRAM Controller functions
mbed_official 76:aeb1df146756 67 * @brief NOR/SRAM Controller functions
mbed_official 76:aeb1df146756 68 *
mbed_official 76:aeb1df146756 69 @verbatim
mbed_official 76:aeb1df146756 70 ==============================================================================
mbed_official 76:aeb1df146756 71 ##### NOR-SRAM Controller functions #####
mbed_official 76:aeb1df146756 72 ==============================================================================
mbed_official 76:aeb1df146756 73 [..] The following sequence should be followed to configure the FSMC to
mbed_official 76:aeb1df146756 74 interface with SRAM, PSRAM, NOR or OneNAND memory connected to the
mbed_official 76:aeb1df146756 75 NOR/SRAM Bank:
mbed_official 76:aeb1df146756 76 (#) Enable the clock for the FSMC and associated GPIOs using the following
mbed_official 76:aeb1df146756 77 functions:
mbed_official 76:aeb1df146756 78 (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
mbed_official 76:aeb1df146756 79 (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
mbed_official 76:aeb1df146756 80 (#) FSMC pins configuration
mbed_official 76:aeb1df146756 81 (++) Connect the involved FSMC pins to AF12 using the following function
mbed_official 76:aeb1df146756 82 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
mbed_official 76:aeb1df146756 83 (++) Configure these FSMC pins in alternate function mode by calling the
mbed_official 76:aeb1df146756 84 function GPIO_Init();
mbed_official 76:aeb1df146756 85 (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
mbed_official 76:aeb1df146756 86 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the
mbed_official 76:aeb1df146756 87 FSMC_NORSRAMInitStructure variable with the allowed values of the
mbed_official 76:aeb1df146756 88 structure member.
mbed_official 76:aeb1df146756 89 (#) Initialize the NOR/SRAM Controller by calling the function
mbed_official 76:aeb1df146756 90 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
mbed_official 76:aeb1df146756 91 (#) Then enable the NOR/SRAM Bank, for example:
mbed_official 76:aeb1df146756 92 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
mbed_official 76:aeb1df146756 93 (#) At this stage you can read/write from/to the memory connected to the
mbed_official 76:aeb1df146756 94 NOR/SRAM Bank.
mbed_official 76:aeb1df146756 95
mbed_official 76:aeb1df146756 96 @endverbatim
mbed_official 76:aeb1df146756 97
mbed_official 76:aeb1df146756 98 * @{
mbed_official 76:aeb1df146756 99 */
mbed_official 76:aeb1df146756 100
mbed_official 76:aeb1df146756 101 /**
mbed_official 76:aeb1df146756 102 * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
mbed_official 76:aeb1df146756 103 * reset values.
mbed_official 76:aeb1df146756 104 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 76:aeb1df146756 105 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 106 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
mbed_official 76:aeb1df146756 107 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
mbed_official 76:aeb1df146756 108 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
mbed_official 76:aeb1df146756 109 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
mbed_official 76:aeb1df146756 110 * @retval None
mbed_official 76:aeb1df146756 111 */
mbed_official 76:aeb1df146756 112 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
mbed_official 76:aeb1df146756 113 {
mbed_official 76:aeb1df146756 114 /* Check the parameter */
mbed_official 76:aeb1df146756 115 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
mbed_official 76:aeb1df146756 116
mbed_official 76:aeb1df146756 117 /* FSMC_Bank1_NORSRAM1 */
mbed_official 76:aeb1df146756 118 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
mbed_official 76:aeb1df146756 119 {
mbed_official 76:aeb1df146756 120 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
mbed_official 76:aeb1df146756 121 }
mbed_official 76:aeb1df146756 122 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
mbed_official 76:aeb1df146756 123 else
mbed_official 76:aeb1df146756 124 {
mbed_official 76:aeb1df146756 125 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
mbed_official 76:aeb1df146756 126 }
mbed_official 76:aeb1df146756 127 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
mbed_official 76:aeb1df146756 128 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
mbed_official 76:aeb1df146756 129 }
mbed_official 76:aeb1df146756 130
mbed_official 76:aeb1df146756 131 /**
mbed_official 76:aeb1df146756 132 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
mbed_official 76:aeb1df146756 133 * parameters in the FSMC_NORSRAMInitStruct.
mbed_official 76:aeb1df146756 134 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
mbed_official 76:aeb1df146756 135 * structure that contains the configuration information for
mbed_official 76:aeb1df146756 136 * the FSMC NOR/SRAM specified Banks.
mbed_official 76:aeb1df146756 137 * @retval None
mbed_official 76:aeb1df146756 138 */
mbed_official 76:aeb1df146756 139 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
mbed_official 76:aeb1df146756 140 {
mbed_official 76:aeb1df146756 141 /* Check the parameters */
mbed_official 76:aeb1df146756 142 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
mbed_official 76:aeb1df146756 143 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
mbed_official 76:aeb1df146756 144 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
mbed_official 76:aeb1df146756 145 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
mbed_official 76:aeb1df146756 146 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
mbed_official 76:aeb1df146756 147 assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
mbed_official 76:aeb1df146756 148 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
mbed_official 76:aeb1df146756 149 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
mbed_official 76:aeb1df146756 150 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
mbed_official 76:aeb1df146756 151 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
mbed_official 76:aeb1df146756 152 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
mbed_official 76:aeb1df146756 153 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
mbed_official 76:aeb1df146756 154 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
mbed_official 76:aeb1df146756 155 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
mbed_official 76:aeb1df146756 156 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
mbed_official 76:aeb1df146756 157 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
mbed_official 76:aeb1df146756 158 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
mbed_official 76:aeb1df146756 159 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
mbed_official 76:aeb1df146756 160 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
mbed_official 76:aeb1df146756 161 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
mbed_official 76:aeb1df146756 162
mbed_official 76:aeb1df146756 163 /* Bank1 NOR/SRAM control register configuration */
mbed_official 76:aeb1df146756 164 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
mbed_official 76:aeb1df146756 165 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
mbed_official 76:aeb1df146756 166 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
mbed_official 76:aeb1df146756 167 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
mbed_official 76:aeb1df146756 168 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
mbed_official 76:aeb1df146756 169 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
mbed_official 76:aeb1df146756 170 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
mbed_official 76:aeb1df146756 171 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
mbed_official 76:aeb1df146756 172 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
mbed_official 76:aeb1df146756 173 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
mbed_official 76:aeb1df146756 174 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
mbed_official 76:aeb1df146756 175 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
mbed_official 76:aeb1df146756 176 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
mbed_official 76:aeb1df146756 177
mbed_official 76:aeb1df146756 178 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
mbed_official 76:aeb1df146756 179 {
mbed_official 76:aeb1df146756 180 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;
mbed_official 76:aeb1df146756 181 }
mbed_official 76:aeb1df146756 182
mbed_official 76:aeb1df146756 183 /* Bank1 NOR/SRAM timing register configuration */
mbed_official 76:aeb1df146756 184 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
mbed_official 76:aeb1df146756 185 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
mbed_official 76:aeb1df146756 186 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
mbed_official 76:aeb1df146756 187 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
mbed_official 76:aeb1df146756 188 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
mbed_official 76:aeb1df146756 189 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
mbed_official 76:aeb1df146756 190 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
mbed_official 76:aeb1df146756 191 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
mbed_official 76:aeb1df146756 192
mbed_official 76:aeb1df146756 193
mbed_official 76:aeb1df146756 194 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
mbed_official 76:aeb1df146756 195 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
mbed_official 76:aeb1df146756 196 {
mbed_official 76:aeb1df146756 197 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
mbed_official 76:aeb1df146756 198 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
mbed_official 76:aeb1df146756 199 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
mbed_official 76:aeb1df146756 200 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
mbed_official 76:aeb1df146756 201 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
mbed_official 76:aeb1df146756 202 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
mbed_official 76:aeb1df146756 203 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
mbed_official 76:aeb1df146756 204 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
mbed_official 76:aeb1df146756 205 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
mbed_official 76:aeb1df146756 206 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
mbed_official 76:aeb1df146756 207 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
mbed_official 76:aeb1df146756 208 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
mbed_official 76:aeb1df146756 209 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
mbed_official 76:aeb1df146756 210 }
mbed_official 76:aeb1df146756 211 else
mbed_official 76:aeb1df146756 212 {
mbed_official 76:aeb1df146756 213 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
mbed_official 76:aeb1df146756 214 }
mbed_official 76:aeb1df146756 215 }
mbed_official 76:aeb1df146756 216
mbed_official 76:aeb1df146756 217 /**
mbed_official 76:aeb1df146756 218 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
mbed_official 76:aeb1df146756 219 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
mbed_official 76:aeb1df146756 220 * structure which will be initialized.
mbed_official 76:aeb1df146756 221 * @retval None
mbed_official 76:aeb1df146756 222 */
mbed_official 76:aeb1df146756 223 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
mbed_official 76:aeb1df146756 224 {
mbed_official 76:aeb1df146756 225 /* Reset NOR/SRAM Init structure parameters values */
mbed_official 76:aeb1df146756 226 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
mbed_official 76:aeb1df146756 227 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
mbed_official 76:aeb1df146756 228 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
mbed_official 76:aeb1df146756 229 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
mbed_official 76:aeb1df146756 230 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
mbed_official 76:aeb1df146756 231 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
mbed_official 76:aeb1df146756 232 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
mbed_official 76:aeb1df146756 233 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
mbed_official 76:aeb1df146756 234 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
mbed_official 76:aeb1df146756 235 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
mbed_official 76:aeb1df146756 236 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
mbed_official 76:aeb1df146756 237 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
mbed_official 76:aeb1df146756 238 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
mbed_official 76:aeb1df146756 239 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
mbed_official 76:aeb1df146756 240 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
mbed_official 76:aeb1df146756 241 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
mbed_official 76:aeb1df146756 242 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
mbed_official 76:aeb1df146756 243 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
mbed_official 76:aeb1df146756 244 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
mbed_official 76:aeb1df146756 245 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official 76:aeb1df146756 246 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
mbed_official 76:aeb1df146756 247 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
mbed_official 76:aeb1df146756 248 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
mbed_official 76:aeb1df146756 249 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
mbed_official 76:aeb1df146756 250 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
mbed_official 76:aeb1df146756 251 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
mbed_official 76:aeb1df146756 252 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official 76:aeb1df146756 253 }
mbed_official 76:aeb1df146756 254
mbed_official 76:aeb1df146756 255 /**
mbed_official 76:aeb1df146756 256 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
mbed_official 76:aeb1df146756 257 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 76:aeb1df146756 258 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 259 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
mbed_official 76:aeb1df146756 260 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
mbed_official 76:aeb1df146756 261 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
mbed_official 76:aeb1df146756 262 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
mbed_official 76:aeb1df146756 263 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 264 * @retval None
mbed_official 76:aeb1df146756 265 */
mbed_official 76:aeb1df146756 266 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
mbed_official 76:aeb1df146756 267 {
mbed_official 76:aeb1df146756 268 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
mbed_official 76:aeb1df146756 269 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 270
mbed_official 76:aeb1df146756 271 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 272 {
mbed_official 76:aeb1df146756 273 /* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */
mbed_official 76:aeb1df146756 274 FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;
mbed_official 76:aeb1df146756 275 }
mbed_official 76:aeb1df146756 276 else
mbed_official 76:aeb1df146756 277 {
mbed_official 76:aeb1df146756 278 /* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */
mbed_official 76:aeb1df146756 279 FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);
mbed_official 76:aeb1df146756 280 }
mbed_official 76:aeb1df146756 281 }
mbed_official 76:aeb1df146756 282
mbed_official 76:aeb1df146756 283 /**
mbed_official 76:aeb1df146756 284 * @}
mbed_official 76:aeb1df146756 285 */
mbed_official 76:aeb1df146756 286
mbed_official 76:aeb1df146756 287 /**
mbed_official 76:aeb1df146756 288 * @}
mbed_official 76:aeb1df146756 289 */
mbed_official 76:aeb1df146756 290
mbed_official 76:aeb1df146756 291 /**
mbed_official 76:aeb1df146756 292 * @}
mbed_official 76:aeb1df146756 293 */
mbed_official 76:aeb1df146756 294
mbed_official 76:aeb1df146756 295 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/