mbed library sources
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targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c@87:085cde657901, 2014-02-08 (annotated)
- Committer:
- mbed_official
- Date:
- Sat Feb 08 19:45:06 2014 +0000
- Revision:
- 87:085cde657901
- Parent:
- 84:f54042cbc282
- Child:
- 91:0a39e62a0464
Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2
Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/
Add NUCLEO_F401RE, improvements
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 52:a51c77007319 | 1 | /* mbed Microcontroller Library |
mbed_official | 70:c1fbde68b492 | 2 | * Copyright (c) 2014, STMicroelectronics |
mbed_official | 70:c1fbde68b492 | 3 | * All rights reserved. |
mbed_official | 52:a51c77007319 | 4 | * |
mbed_official | 70:c1fbde68b492 | 5 | * Redistribution and use in source and binary forms, with or without |
mbed_official | 70:c1fbde68b492 | 6 | * modification, are permitted provided that the following conditions are met: |
mbed_official | 52:a51c77007319 | 7 | * |
mbed_official | 70:c1fbde68b492 | 8 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 70:c1fbde68b492 | 9 | * this list of conditions and the following disclaimer. |
mbed_official | 70:c1fbde68b492 | 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 70:c1fbde68b492 | 11 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 70:c1fbde68b492 | 12 | * and/or other materials provided with the distribution. |
mbed_official | 70:c1fbde68b492 | 13 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 70:c1fbde68b492 | 14 | * may be used to endorse or promote products derived from this software |
mbed_official | 70:c1fbde68b492 | 15 | * without specific prior written permission. |
mbed_official | 52:a51c77007319 | 16 | * |
mbed_official | 70:c1fbde68b492 | 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 70:c1fbde68b492 | 18 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 70:c1fbde68b492 | 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 70:c1fbde68b492 | 20 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 70:c1fbde68b492 | 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 70:c1fbde68b492 | 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 70:c1fbde68b492 | 23 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 70:c1fbde68b492 | 24 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 70:c1fbde68b492 | 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 70:c1fbde68b492 | 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 52:a51c77007319 | 27 | */ |
mbed_official | 52:a51c77007319 | 28 | #include <stddef.h> |
mbed_official | 52:a51c77007319 | 29 | #include "us_ticker_api.h" |
mbed_official | 52:a51c77007319 | 30 | #include "PeripheralNames.h" |
mbed_official | 52:a51c77007319 | 31 | |
mbed_official | 84:f54042cbc282 | 32 | // Timer selection: |
mbed_official | 84:f54042cbc282 | 33 | #define TIM_MST TIM1 |
mbed_official | 84:f54042cbc282 | 34 | #define TIM_MST_UP_IRQ TIM1_UP_IRQn |
mbed_official | 84:f54042cbc282 | 35 | #define TIM_MST_OC_IRQ TIM1_CC_IRQn |
mbed_official | 84:f54042cbc282 | 36 | #define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE) |
mbed_official | 76:aeb1df146756 | 37 | |
mbed_official | 84:f54042cbc282 | 38 | static int us_ticker_inited = 0; |
mbed_official | 84:f54042cbc282 | 39 | static uint32_t SlaveCounter = 0; |
mbed_official | 84:f54042cbc282 | 40 | static uint32_t us_ticker_int_counter = 0; |
mbed_official | 84:f54042cbc282 | 41 | static uint16_t us_ticker_int_remainder = 0; |
mbed_official | 84:f54042cbc282 | 42 | |
mbed_official | 84:f54042cbc282 | 43 | // Used to increment the slave counter |
mbed_official | 84:f54042cbc282 | 44 | static void tim_update_irq_handler(void) { |
mbed_official | 84:f54042cbc282 | 45 | SlaveCounter++; |
mbed_official | 84:f54042cbc282 | 46 | if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) { |
mbed_official | 84:f54042cbc282 | 47 | TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update); |
mbed_official | 84:f54042cbc282 | 48 | } |
mbed_official | 84:f54042cbc282 | 49 | } |
mbed_official | 76:aeb1df146756 | 50 | |
mbed_official | 84:f54042cbc282 | 51 | // Used by interrupt system |
mbed_official | 84:f54042cbc282 | 52 | static void tim_oc_irq_handler(void) { |
mbed_official | 84:f54042cbc282 | 53 | // Clear interrupt flag |
mbed_official | 84:f54042cbc282 | 54 | if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) { |
mbed_official | 84:f54042cbc282 | 55 | TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); |
mbed_official | 84:f54042cbc282 | 56 | } |
mbed_official | 84:f54042cbc282 | 57 | |
mbed_official | 84:f54042cbc282 | 58 | if (us_ticker_int_counter > 0) { |
mbed_official | 84:f54042cbc282 | 59 | TIM_SetCompare1(TIM_MST, 0xFFFF); |
mbed_official | 84:f54042cbc282 | 60 | us_ticker_int_counter--; |
mbed_official | 84:f54042cbc282 | 61 | } else { |
mbed_official | 84:f54042cbc282 | 62 | if (us_ticker_int_remainder > 0) { |
mbed_official | 84:f54042cbc282 | 63 | TIM_SetCompare1(TIM_MST, us_ticker_int_remainder); |
mbed_official | 84:f54042cbc282 | 64 | us_ticker_int_remainder = 0; |
mbed_official | 84:f54042cbc282 | 65 | } else { |
mbed_official | 84:f54042cbc282 | 66 | // This function is going to disable the interrupts if there are |
mbed_official | 84:f54042cbc282 | 67 | // no other events in the queue |
mbed_official | 84:f54042cbc282 | 68 | us_ticker_irq_handler(); |
mbed_official | 84:f54042cbc282 | 69 | } |
mbed_official | 84:f54042cbc282 | 70 | } |
mbed_official | 84:f54042cbc282 | 71 | } |
mbed_official | 76:aeb1df146756 | 72 | |
mbed_official | 84:f54042cbc282 | 73 | void us_ticker_init(void) { |
mbed_official | 52:a51c77007319 | 74 | TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; |
mbed_official | 84:f54042cbc282 | 75 | |
mbed_official | 52:a51c77007319 | 76 | if (us_ticker_inited) return; |
mbed_official | 52:a51c77007319 | 77 | us_ticker_inited = 1; |
mbed_official | 52:a51c77007319 | 78 | |
mbed_official | 84:f54042cbc282 | 79 | // Enable Timer clock |
mbed_official | 76:aeb1df146756 | 80 | TIM_MST_RCC; |
mbed_official | 52:a51c77007319 | 81 | |
mbed_official | 84:f54042cbc282 | 82 | // Configure time base |
mbed_official | 54:24d77221bceb | 83 | TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); |
mbed_official | 52:a51c77007319 | 84 | TIM_TimeBaseStructure.TIM_Period = 0xFFFF; |
mbed_official | 52:a51c77007319 | 85 | TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick |
mbed_official | 52:a51c77007319 | 86 | TIM_TimeBaseStructure.TIM_ClockDivision = 0; |
mbed_official | 52:a51c77007319 | 87 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; |
mbed_official | 76:aeb1df146756 | 88 | TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure); |
mbed_official | 84:f54042cbc282 | 89 | |
mbed_official | 84:f54042cbc282 | 90 | // Configure interrupts |
mbed_official | 84:f54042cbc282 | 91 | TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE); |
mbed_official | 84:f54042cbc282 | 92 | TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE); |
mbed_official | 52:a51c77007319 | 93 | |
mbed_official | 84:f54042cbc282 | 94 | // For 32-bit counter |
mbed_official | 84:f54042cbc282 | 95 | NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler); |
mbed_official | 84:f54042cbc282 | 96 | NVIC_EnableIRQ(TIM_MST_UP_IRQ); |
mbed_official | 84:f54042cbc282 | 97 | |
mbed_official | 84:f54042cbc282 | 98 | // For ouput compare |
mbed_official | 84:f54042cbc282 | 99 | NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler); |
mbed_official | 84:f54042cbc282 | 100 | NVIC_EnableIRQ(TIM_MST_OC_IRQ); |
mbed_official | 52:a51c77007319 | 101 | |
mbed_official | 84:f54042cbc282 | 102 | // Enable timer |
mbed_official | 76:aeb1df146756 | 103 | TIM_Cmd(TIM_MST, ENABLE); |
mbed_official | 52:a51c77007319 | 104 | } |
mbed_official | 52:a51c77007319 | 105 | |
mbed_official | 52:a51c77007319 | 106 | uint32_t us_ticker_read() { |
mbed_official | 54:24d77221bceb | 107 | uint32_t counter, counter2; |
mbed_official | 52:a51c77007319 | 108 | if (!us_ticker_inited) us_ticker_init(); |
mbed_official | 76:aeb1df146756 | 109 | // A situation might appear when Master overflows right after Slave is read and before the |
mbed_official | 76:aeb1df146756 | 110 | // new (overflowed) value of Master is read. Which would make the code below consider the |
mbed_official | 76:aeb1df146756 | 111 | // previous (incorrect) value of Slave and the new value of Master, which would return a |
mbed_official | 54:24d77221bceb | 112 | // value in the past. Avoid this by computing consecutive values of the timer until they |
mbed_official | 54:24d77221bceb | 113 | // are properly ordered. |
mbed_official | 84:f54042cbc282 | 114 | counter = (uint32_t)(SlaveCounter << 16); |
mbed_official | 76:aeb1df146756 | 115 | counter += (uint32_t)TIM_GetCounter(TIM_MST); |
mbed_official | 54:24d77221bceb | 116 | while (1) { |
mbed_official | 84:f54042cbc282 | 117 | counter2 = (uint32_t)(SlaveCounter << 16); |
mbed_official | 76:aeb1df146756 | 118 | counter2 += (uint32_t)TIM_GetCounter(TIM_MST); |
mbed_official | 76:aeb1df146756 | 119 | if (counter2 > counter) { |
mbed_official | 54:24d77221bceb | 120 | break; |
mbed_official | 76:aeb1df146756 | 121 | } |
mbed_official | 54:24d77221bceb | 122 | counter = counter2; |
mbed_official | 54:24d77221bceb | 123 | } |
mbed_official | 54:24d77221bceb | 124 | return counter2; |
mbed_official | 52:a51c77007319 | 125 | } |
mbed_official | 52:a51c77007319 | 126 | |
mbed_official | 52:a51c77007319 | 127 | void us_ticker_set_interrupt(unsigned int timestamp) { |
mbed_official | 84:f54042cbc282 | 128 | int delta = (int)(timestamp - us_ticker_read()); |
mbed_official | 84:f54042cbc282 | 129 | |
mbed_official | 84:f54042cbc282 | 130 | if (delta <= 0) { // This event was in the past |
mbed_official | 84:f54042cbc282 | 131 | us_ticker_irq_handler(); |
mbed_official | 84:f54042cbc282 | 132 | return; |
mbed_official | 52:a51c77007319 | 133 | } |
mbed_official | 52:a51c77007319 | 134 | else { |
mbed_official | 84:f54042cbc282 | 135 | us_ticker_int_counter = (uint32_t)(delta >> 16); |
mbed_official | 84:f54042cbc282 | 136 | us_ticker_int_remainder = (uint16_t)(delta & 0xFFFF); |
mbed_official | 84:f54042cbc282 | 137 | if (us_ticker_int_counter > 0) { // means delta > 0xFFFF |
mbed_official | 84:f54042cbc282 | 138 | TIM_SetCompare1(TIM_MST, 0xFFFF); |
mbed_official | 84:f54042cbc282 | 139 | us_ticker_int_counter--; |
mbed_official | 84:f54042cbc282 | 140 | } else { |
mbed_official | 84:f54042cbc282 | 141 | TIM_SetCompare1(TIM_MST, us_ticker_int_remainder); |
mbed_official | 84:f54042cbc282 | 142 | us_ticker_int_remainder = 0; |
mbed_official | 84:f54042cbc282 | 143 | } |
mbed_official | 87:085cde657901 | 144 | TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE); |
mbed_official | 52:a51c77007319 | 145 | } |
mbed_official | 52:a51c77007319 | 146 | } |
mbed_official | 52:a51c77007319 | 147 | |
mbed_official | 52:a51c77007319 | 148 | void us_ticker_disable_interrupt(void) { |
mbed_official | 76:aeb1df146756 | 149 | TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE); |
mbed_official | 52:a51c77007319 | 150 | } |
mbed_official | 52:a51c77007319 | 151 | |
mbed_official | 52:a51c77007319 | 152 | void us_ticker_clear_interrupt(void) { |
mbed_official | 84:f54042cbc282 | 153 | if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) { |
mbed_official | 84:f54042cbc282 | 154 | TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); |
mbed_official | 84:f54042cbc282 | 155 | } |
mbed_official | 52:a51c77007319 | 156 | } |