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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.c@87:085cde657901, 2014-02-08 (annotated)

Committer:: mbed_official
Date:: Sat Feb 08 19:45:06 2014 +0000
Revision:: 87:085cde657901
Child:: 106:ced8cbb51063

Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2

Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/

Add NUCLEO_F401RE, improvements

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_tim.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	87:085cde657901	5	* @version V1.0.0RC2
mbed_official	87:085cde657901	6	* @date 04-February-2014
mbed_official	87:085cde657901	7	* @brief TIM HAL module driver.
mbed_official	87:085cde657901	8	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	9	* functionalities of the Timer (TIM) peripheral:
mbed_official	87:085cde657901	10	* + Time Base Initialization
mbed_official	87:085cde657901	11	* + Time Base Start
mbed_official	87:085cde657901	12	* + Time Base Start Interruption
mbed_official	87:085cde657901	13	* + Time Base Start DMA
mbed_official	87:085cde657901	14	* + Time Output Compare/PWM Initialization
mbed_official	87:085cde657901	15	* + Time Output Compare/PWM Channel Configuration
mbed_official	87:085cde657901	16	* + Time Output Compare/PWM Start
mbed_official	87:085cde657901	17	* + Time Output Compare/PWM Start Interruption
mbed_official	87:085cde657901	18	* + Time Output Compare/PWM Start DMA
mbed_official	87:085cde657901	19	* + Time Input Capture Initialization
mbed_official	87:085cde657901	20	* + Time Input Capture Channel Configuration
mbed_official	87:085cde657901	21	* + Time Input Capture Start
mbed_official	87:085cde657901	22	* + Time Input Capture Start Interruption
mbed_official	87:085cde657901	23	* + Time Input Capture Start DMA
mbed_official	87:085cde657901	24	* + Time One Pulse Initialization
mbed_official	87:085cde657901	25	* + Time One Pulse Channel Configuration
mbed_official	87:085cde657901	26	* + Time One Pulse Start
mbed_official	87:085cde657901	27	* + Time Encoder Interface Initialization
mbed_official	87:085cde657901	28	* + Time Encoder Interface Start
mbed_official	87:085cde657901	29	* + Time Encoder Interface Start Interruption
mbed_official	87:085cde657901	30	* + Time Encoder Interface Start DMA
mbed_official	87:085cde657901	31	* + Commutation Event configuration with Interruption and DMA
mbed_official	87:085cde657901	32	* + Time OCRef clear configuration
mbed_official	87:085cde657901	33	* + Time External Clock configuration
mbed_official	87:085cde657901	34	@verbatim
mbed_official	87:085cde657901	35	==============================================================================
mbed_official	87:085cde657901	36	##### TIMER Generic features #####
mbed_official	87:085cde657901	37	==============================================================================
mbed_official	87:085cde657901	38	[..] The Timer features include:
mbed_official	87:085cde657901	39	(#) 16-bit up, down, up/down auto-reload counter.
mbed_official	87:085cde657901	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
mbed_official	87:085cde657901	41	counter clock frequency either by any factor between 1 and 65536.
mbed_official	87:085cde657901	42	(#) Up to 4 independent channels for:
mbed_official	87:085cde657901	43	(++) Input Capture
mbed_official	87:085cde657901	44	(++) Output Compare
mbed_official	87:085cde657901	45	(++) PWM generation (Edge and Center-aligned Mode)
mbed_official	87:085cde657901	46	(++) One-pulse mode output
mbed_official	87:085cde657901	47
mbed_official	87:085cde657901	48	##### How to use this driver #####
mbed_official	87:085cde657901	49	==============================================================================
mbed_official	87:085cde657901	50	[..]
mbed_official	87:085cde657901	51	(#) Initialize the TIM low level resources by implementing the following functions
mbed_official	87:085cde657901	52	depending from feature used :
mbed_official	87:085cde657901	53	(++) Time Base : HAL_TIM_Base_MspInit()
mbed_official	87:085cde657901	54	(++) Input Capture : HAL_TIM_IC_MspInit()
mbed_official	87:085cde657901	55	(++) Output Compare : HAL_TIM_OC_MspInit()
mbed_official	87:085cde657901	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
mbed_official	87:085cde657901	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
mbed_official	87:085cde657901	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
mbed_official	87:085cde657901	59
mbed_official	87:085cde657901	60	(#) Initialize the TIM low level resources :
mbed_official	87:085cde657901	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
mbed_official	87:085cde657901	62	(##) TIM pins configuration
mbed_official	87:085cde657901	63	(+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official	87:085cde657901	64	__GPIOx_CLK_ENABLE();
mbed_official	87:085cde657901	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official	87:085cde657901	66
mbed_official	87:085cde657901	67	(#) The external Clock can be configured, if needed (the default clock is the
mbed_official	87:085cde657901	68	internal clock from the APBx), using the following function:
mbed_official	87:085cde657901	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
mbed_official	87:085cde657901	70	any start function.
mbed_official	87:085cde657901	71
mbed_official	87:085cde657901	72	(#) Configure the TIM in the desired functioning mode using one of the
mbed_official	87:085cde657901	73	initialization function of this driver:
mbed_official	87:085cde657901	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official	87:085cde657901	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official	87:085cde657901	76	Output Compare signal.
mbed_official	87:085cde657901	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official	87:085cde657901	78	PWM signal.
mbed_official	87:085cde657901	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official	87:085cde657901	80	external signal.
mbed_official	87:085cde657901	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
mbed_official	87:085cde657901	82	in One Pulse Mode.
mbed_official	87:085cde657901	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official	87:085cde657901	84
mbed_official	87:085cde657901	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
mbed_official	87:085cde657901	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
mbed_official	87:085cde657901	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
mbed_official	87:085cde657901	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
mbed_official	87:085cde657901	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
mbed_official	87:085cde657901	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
mbed_official	87:085cde657901	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
mbed_official	87:085cde657901	92
mbed_official	87:085cde657901	93	(#) The DMA Burst is managed with the two following functions:
mbed_official	87:085cde657901	94	HAL_TIM_DMABurst_WriteStart()
mbed_official	87:085cde657901	95	HAL_TIM_DMABurst_ReadStart()
mbed_official	87:085cde657901	96
mbed_official	87:085cde657901	97	@endverbatim
mbed_official	87:085cde657901	98	******************************************************************************
mbed_official	87:085cde657901	99	* @attention
mbed_official	87:085cde657901	100	*
mbed_official	87:085cde657901	101	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	102	*
mbed_official	87:085cde657901	103	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	104	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	105	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	106	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	108	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	109	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	111	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	112	* without specific prior written permission.
mbed_official	87:085cde657901	113	*
mbed_official	87:085cde657901	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	124	*
mbed_official	87:085cde657901	125	******************************************************************************
mbed_official	87:085cde657901	126	*/
mbed_official	87:085cde657901	127
mbed_official	87:085cde657901	128	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	129	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	130
mbed_official	87:085cde657901	131	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	132	* @{
mbed_official	87:085cde657901	133	*/
mbed_official	87:085cde657901	134
mbed_official	87:085cde657901	135	/** @defgroup TIM
mbed_official	87:085cde657901	136	* @brief TIM HAL module driver
mbed_official	87:085cde657901	137	* @{
mbed_official	87:085cde657901	138	*/
mbed_official	87:085cde657901	139
mbed_official	87:085cde657901	140	#ifdef HAL_TIM_MODULE_ENABLED
mbed_official	87:085cde657901	141
mbed_official	87:085cde657901	142	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	143	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	144	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	145	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	146	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	147	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	87:085cde657901	148	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	87:085cde657901	149	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	87:085cde657901	150
mbed_official	87:085cde657901	151	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	152	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	153	uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	154	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	155	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	156	uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	157	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	158	uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	159
mbed_official	87:085cde657901	160	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official	87:085cde657901	161	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official	87:085cde657901	162
mbed_official	87:085cde657901	163	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
mbed_official	87:085cde657901	164	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	165	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	166	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	167
mbed_official	87:085cde657901	168	/** @defgroup TIM_Private_Functions
mbed_official	87:085cde657901	169	* @{
mbed_official	87:085cde657901	170	*/
mbed_official	87:085cde657901	171
mbed_official	87:085cde657901	172	/** @defgroup TIM_Group1 Time Base functions
mbed_official	87:085cde657901	173	* @brief Time Base functions
mbed_official	87:085cde657901	174	*
mbed_official	87:085cde657901	175	@verbatim
mbed_official	87:085cde657901	176	==============================================================================
mbed_official	87:085cde657901	177	##### Time Base functions #####
mbed_official	87:085cde657901	178	==============================================================================
mbed_official	87:085cde657901	179	[..]
mbed_official	87:085cde657901	180	This section provides functions allowing to:
mbed_official	87:085cde657901	181	(+) Initialize and configure the TIM base.
mbed_official	87:085cde657901	182	(+) De-initialize the TIM base.
mbed_official	87:085cde657901	183	(+) Start the Time Base.
mbed_official	87:085cde657901	184	(+) Stop the Time Base.
mbed_official	87:085cde657901	185	(+) Start the Time Base and enable interrupt.
mbed_official	87:085cde657901	186	(+) Stop the Time Base and disable interrupt.
mbed_official	87:085cde657901	187	(+) Start the Time Base and enable DMA transfer.
mbed_official	87:085cde657901	188	(+) Stop the Time Base and disable DMA transfer.
mbed_official	87:085cde657901	189
mbed_official	87:085cde657901	190	@endverbatim
mbed_official	87:085cde657901	191	* @{
mbed_official	87:085cde657901	192	*/
mbed_official	87:085cde657901	193	/**
mbed_official	87:085cde657901	194	* @brief Initializes the TIM Time base Unit according to the specified
mbed_official	87:085cde657901	195	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	87:085cde657901	196	* @param htim: TIM Base handle
mbed_official	87:085cde657901	197	* @retval HAL status
mbed_official	87:085cde657901	198	*/
mbed_official	87:085cde657901	199	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	200	{
mbed_official	87:085cde657901	201	/* Check the TIM handle allocation */
mbed_official	87:085cde657901	202	if(htim == NULL)
mbed_official	87:085cde657901	203	{
mbed_official	87:085cde657901	204	return HAL_ERROR;
mbed_official	87:085cde657901	205	}
mbed_official	87:085cde657901	206
mbed_official	87:085cde657901	207	/* Check the parameters */
mbed_official	87:085cde657901	208	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	209	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	210	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	211
mbed_official	87:085cde657901	212	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	213	{
mbed_official	87:085cde657901	214	/* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official	87:085cde657901	215	HAL_TIM_Base_MspInit(htim);
mbed_official	87:085cde657901	216	}
mbed_official	87:085cde657901	217
mbed_official	87:085cde657901	218	/* Set the TIM state */
mbed_official	87:085cde657901	219	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	220
mbed_official	87:085cde657901	221	/* Set the Time Base configuration */
mbed_official	87:085cde657901	222	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	223
mbed_official	87:085cde657901	224	/* Initialize the TIM state*/
mbed_official	87:085cde657901	225	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	226
mbed_official	87:085cde657901	227	return HAL_OK;
mbed_official	87:085cde657901	228	}
mbed_official	87:085cde657901	229
mbed_official	87:085cde657901	230	/**
mbed_official	87:085cde657901	231	* @brief DeInitializes the TIM Base peripheral
mbed_official	87:085cde657901	232	* @param htim: TIM Base handle
mbed_official	87:085cde657901	233	* @retval HAL status
mbed_official	87:085cde657901	234	*/
mbed_official	87:085cde657901	235	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	236	{
mbed_official	87:085cde657901	237	/* Check the parameters */
mbed_official	87:085cde657901	238	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	239
mbed_official	87:085cde657901	240	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	241
mbed_official	87:085cde657901	242	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	243	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	244
mbed_official	87:085cde657901	245	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	87:085cde657901	246	HAL_TIM_Base_MspDeInit(htim);
mbed_official	87:085cde657901	247
mbed_official	87:085cde657901	248	/* Change TIM state */
mbed_official	87:085cde657901	249	htim->State = HAL_TIM_STATE_RESET;
mbed_official	87:085cde657901	250
mbed_official	87:085cde657901	251	return HAL_OK;
mbed_official	87:085cde657901	252	}
mbed_official	87:085cde657901	253
mbed_official	87:085cde657901	254	/**
mbed_official	87:085cde657901	255	* @brief Initializes the TIM Base MSP.
mbed_official	87:085cde657901	256	* @param htim: TIM handle
mbed_official	87:085cde657901	257	* @retval None
mbed_official	87:085cde657901	258	*/
mbed_official	87:085cde657901	259	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	260	{
mbed_official	87:085cde657901	261	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	262	the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official	87:085cde657901	263	*/
mbed_official	87:085cde657901	264	}
mbed_official	87:085cde657901	265
mbed_official	87:085cde657901	266	/**
mbed_official	87:085cde657901	267	* @brief DeInitializes TIM Base MSP.
mbed_official	87:085cde657901	268	* @param htim: TIM handle
mbed_official	87:085cde657901	269	* @retval None
mbed_official	87:085cde657901	270	*/
mbed_official	87:085cde657901	271	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	272	{
mbed_official	87:085cde657901	273	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	274	the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	275	*/
mbed_official	87:085cde657901	276	}
mbed_official	87:085cde657901	277
mbed_official	87:085cde657901	278	/**
mbed_official	87:085cde657901	279	* @brief Starts the TIM Base generation.
mbed_official	87:085cde657901	280	* @param htim : TIM handle
mbed_official	87:085cde657901	281	* @retval HAL status
mbed_official	87:085cde657901	282	*/
mbed_official	87:085cde657901	283	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	284	{
mbed_official	87:085cde657901	285	/* Check the parameters */
mbed_official	87:085cde657901	286	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	287
mbed_official	87:085cde657901	288	/* Set the TIM state */
mbed_official	87:085cde657901	289	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	290
mbed_official	87:085cde657901	291	/* Enable the Peripheral */
mbed_official	87:085cde657901	292	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	293
mbed_official	87:085cde657901	294	/* Change the TIM state*/
mbed_official	87:085cde657901	295	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	296
mbed_official	87:085cde657901	297	/* Return function status */
mbed_official	87:085cde657901	298	return HAL_OK;
mbed_official	87:085cde657901	299	}
mbed_official	87:085cde657901	300
mbed_official	87:085cde657901	301	/**
mbed_official	87:085cde657901	302	* @brief Stops the TIM Base generation.
mbed_official	87:085cde657901	303	* @param htim : TIM handle
mbed_official	87:085cde657901	304	* @retval HAL status
mbed_official	87:085cde657901	305	*/
mbed_official	87:085cde657901	306	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	307	{
mbed_official	87:085cde657901	308	/* Check the parameters */
mbed_official	87:085cde657901	309	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	310
mbed_official	87:085cde657901	311	/* Set the TIM state */
mbed_official	87:085cde657901	312	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	313
mbed_official	87:085cde657901	314	/* Disable the Peripheral */
mbed_official	87:085cde657901	315	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	316
mbed_official	87:085cde657901	317	/* Change the TIM state*/
mbed_official	87:085cde657901	318	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	319
mbed_official	87:085cde657901	320	/* Return function status */
mbed_official	87:085cde657901	321	return HAL_OK;
mbed_official	87:085cde657901	322	}
mbed_official	87:085cde657901	323
mbed_official	87:085cde657901	324	/**
mbed_official	87:085cde657901	325	* @brief Starts the TIM Base generation in interrupt mode.
mbed_official	87:085cde657901	326	* @param htim : TIM handle
mbed_official	87:085cde657901	327	* @retval HAL status
mbed_official	87:085cde657901	328	*/
mbed_official	87:085cde657901	329	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	330	{
mbed_official	87:085cde657901	331	/* Check the parameters */
mbed_official	87:085cde657901	332	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	333
mbed_official	87:085cde657901	334	/* Enable the TIM Update interrupt */
mbed_official	87:085cde657901	335	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official	87:085cde657901	336
mbed_official	87:085cde657901	337	/* Enable the Peripheral */
mbed_official	87:085cde657901	338	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	339
mbed_official	87:085cde657901	340	/* Return function status */
mbed_official	87:085cde657901	341	return HAL_OK;
mbed_official	87:085cde657901	342	}
mbed_official	87:085cde657901	343
mbed_official	87:085cde657901	344	/**
mbed_official	87:085cde657901	345	* @brief Stops the TIM Base generation in interrupt mode.
mbed_official	87:085cde657901	346	* @param htim : TIM handle
mbed_official	87:085cde657901	347	* @retval HAL status
mbed_official	87:085cde657901	348	*/
mbed_official	87:085cde657901	349	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	350	{
mbed_official	87:085cde657901	351	/* Check the parameters */
mbed_official	87:085cde657901	352	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	353	/* Disable the TIM Update interrupt */
mbed_official	87:085cde657901	354	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official	87:085cde657901	355
mbed_official	87:085cde657901	356	/* Disable the Peripheral */
mbed_official	87:085cde657901	357	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	358
mbed_official	87:085cde657901	359	/* Return function status */
mbed_official	87:085cde657901	360	return HAL_OK;
mbed_official	87:085cde657901	361	}
mbed_official	87:085cde657901	362
mbed_official	87:085cde657901	363	/**
mbed_official	87:085cde657901	364	* @brief Starts the TIM Base generation in DMA mode.
mbed_official	87:085cde657901	365	* @param htim : TIM handle
mbed_official	87:085cde657901	366	* @param pData: The source Buffer address.
mbed_official	87:085cde657901	367	* @param Length: The length of data to be transferred from memory to peripheral.
mbed_official	87:085cde657901	368	* @retval HAL status
mbed_official	87:085cde657901	369	*/
mbed_official	87:085cde657901	370	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
mbed_official	87:085cde657901	371	{
mbed_official	87:085cde657901	372	/* Check the parameters */
mbed_official	87:085cde657901	373	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	374
mbed_official	87:085cde657901	375	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	376	{
mbed_official	87:085cde657901	377	return HAL_BUSY;
mbed_official	87:085cde657901	378	}
mbed_official	87:085cde657901	379	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	380	{
mbed_official	87:085cde657901	381	if((pData == 0 ) && (Length > 0))
mbed_official	87:085cde657901	382	{
mbed_official	87:085cde657901	383	return HAL_ERROR;
mbed_official	87:085cde657901	384	}
mbed_official	87:085cde657901	385	else
mbed_official	87:085cde657901	386	{
mbed_official	87:085cde657901	387	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	388	}
mbed_official	87:085cde657901	389	}
mbed_official	87:085cde657901	390	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	391	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	87:085cde657901	392
mbed_official	87:085cde657901	393	/* Set the DMA error callback */
mbed_official	87:085cde657901	394	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	395
mbed_official	87:085cde657901	396	/* Enable the DMA Stream */
mbed_official	87:085cde657901	397	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official	87:085cde657901	398
mbed_official	87:085cde657901	399	/* Enable the TIM Update DMA request */
mbed_official	87:085cde657901	400	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official	87:085cde657901	401
mbed_official	87:085cde657901	402	/* Enable the Peripheral */
mbed_official	87:085cde657901	403	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	404
mbed_official	87:085cde657901	405	/* Return function status */
mbed_official	87:085cde657901	406	return HAL_OK;
mbed_official	87:085cde657901	407	}
mbed_official	87:085cde657901	408
mbed_official	87:085cde657901	409	/**
mbed_official	87:085cde657901	410	* @brief Stops the TIM Base generation in DMA mode.
mbed_official	87:085cde657901	411	* @param htim : TIM handle
mbed_official	87:085cde657901	412	* @retval HAL status
mbed_official	87:085cde657901	413	*/
mbed_official	87:085cde657901	414	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	415	{
mbed_official	87:085cde657901	416	/* Check the parameters */
mbed_official	87:085cde657901	417	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	418
mbed_official	87:085cde657901	419	/* Disable the TIM Update DMA request */
mbed_official	87:085cde657901	420	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official	87:085cde657901	421
mbed_official	87:085cde657901	422	/* Disable the Peripheral */
mbed_official	87:085cde657901	423	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	424
mbed_official	87:085cde657901	425	/* Change the htim state */
mbed_official	87:085cde657901	426	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	427
mbed_official	87:085cde657901	428	/* Return function status */
mbed_official	87:085cde657901	429	return HAL_OK;
mbed_official	87:085cde657901	430	}
mbed_official	87:085cde657901	431
mbed_official	87:085cde657901	432	/**
mbed_official	87:085cde657901	433	* @}
mbed_official	87:085cde657901	434	*/
mbed_official	87:085cde657901	435
mbed_official	87:085cde657901	436	/** @defgroup TIM_Group2 Time Output Compare functions
mbed_official	87:085cde657901	437	* @brief Time Output Compare functions
mbed_official	87:085cde657901	438	*
mbed_official	87:085cde657901	439	@verbatim
mbed_official	87:085cde657901	440	==============================================================================
mbed_official	87:085cde657901	441	##### Time Output Compare functions #####
mbed_official	87:085cde657901	442	==============================================================================
mbed_official	87:085cde657901	443	[..]
mbed_official	87:085cde657901	444	This section provides functions allowing to:
mbed_official	87:085cde657901	445	(+) Initialize and configure the TIM Output Compare.
mbed_official	87:085cde657901	446	(+) De-initialize the TIM Output Compare.
mbed_official	87:085cde657901	447	(+) Start the Time Output Compare.
mbed_official	87:085cde657901	448	(+) Stop the Time Output Compare.
mbed_official	87:085cde657901	449	(+) Start the Time Output Compare and enable interrupt.
mbed_official	87:085cde657901	450	(+) Stop the Time Output Compare and disable interrupt.
mbed_official	87:085cde657901	451	(+) Start the Time Output Compare and enable DMA transfer.
mbed_official	87:085cde657901	452	(+) Stop the Time Output Compare and disable DMA transfer.
mbed_official	87:085cde657901	453
mbed_official	87:085cde657901	454	@endverbatim
mbed_official	87:085cde657901	455	* @{
mbed_official	87:085cde657901	456	*/
mbed_official	87:085cde657901	457	/**
mbed_official	87:085cde657901	458	* @brief Initializes the TIM Output Compare according to the specified
mbed_official	87:085cde657901	459	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	87:085cde657901	460	* @param htim: TIM Output Compare handle
mbed_official	87:085cde657901	461	* @retval HAL status
mbed_official	87:085cde657901	462	*/
mbed_official	87:085cde657901	463	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official	87:085cde657901	464	{
mbed_official	87:085cde657901	465	/* Check the TIM handle allocation */
mbed_official	87:085cde657901	466	if(htim == NULL)
mbed_official	87:085cde657901	467	{
mbed_official	87:085cde657901	468	return HAL_ERROR;
mbed_official	87:085cde657901	469	}
mbed_official	87:085cde657901	470
mbed_official	87:085cde657901	471	/* Check the parameters */
mbed_official	87:085cde657901	472	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	473	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	474	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	475
mbed_official	87:085cde657901	476	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	477	{
mbed_official	87:085cde657901	478	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	479	HAL_TIM_OC_MspInit(htim);
mbed_official	87:085cde657901	480	}
mbed_official	87:085cde657901	481
mbed_official	87:085cde657901	482	/* Set the TIM state */
mbed_official	87:085cde657901	483	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	484
mbed_official	87:085cde657901	485	/* Init the base time for the Output Compare */
mbed_official	87:085cde657901	486	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	487
mbed_official	87:085cde657901	488	/* Initialize the TIM state*/
mbed_official	87:085cde657901	489	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	490
mbed_official	87:085cde657901	491	return HAL_OK;
mbed_official	87:085cde657901	492	}
mbed_official	87:085cde657901	493
mbed_official	87:085cde657901	494	/**
mbed_official	87:085cde657901	495	* @brief DeInitializes the TIM peripheral
mbed_official	87:085cde657901	496	* @param htim: TIM Output Compare handle
mbed_official	87:085cde657901	497	* @retval HAL status
mbed_official	87:085cde657901	498	*/
mbed_official	87:085cde657901	499	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	500	{
mbed_official	87:085cde657901	501	/* Check the parameters */
mbed_official	87:085cde657901	502	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	503
mbed_official	87:085cde657901	504	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	505
mbed_official	87:085cde657901	506	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	507	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	508
mbed_official	87:085cde657901	509	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	510	HAL_TIM_OC_MspDeInit(htim);
mbed_official	87:085cde657901	511
mbed_official	87:085cde657901	512	/* Change TIM state */
mbed_official	87:085cde657901	513	htim->State = HAL_TIM_STATE_RESET;
mbed_official	87:085cde657901	514
mbed_official	87:085cde657901	515	return HAL_OK;
mbed_official	87:085cde657901	516	}
mbed_official	87:085cde657901	517
mbed_official	87:085cde657901	518	/**
mbed_official	87:085cde657901	519	* @brief Initializes the TIM Output Compare MSP.
mbed_official	87:085cde657901	520	* @param htim: TIM handle
mbed_official	87:085cde657901	521	* @retval None
mbed_official	87:085cde657901	522	*/
mbed_official	87:085cde657901	523	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	524	{
mbed_official	87:085cde657901	525	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	526	the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official	87:085cde657901	527	*/
mbed_official	87:085cde657901	528	}
mbed_official	87:085cde657901	529
mbed_official	87:085cde657901	530	/**
mbed_official	87:085cde657901	531	* @brief DeInitializes TIM Output Compare MSP.
mbed_official	87:085cde657901	532	* @param htim: TIM handle
mbed_official	87:085cde657901	533	* @retval None
mbed_official	87:085cde657901	534	*/
mbed_official	87:085cde657901	535	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	536	{
mbed_official	87:085cde657901	537	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	538	the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	539	*/
mbed_official	87:085cde657901	540	}
mbed_official	87:085cde657901	541
mbed_official	87:085cde657901	542	/**
mbed_official	87:085cde657901	543	* @brief Starts the TIM Output Compare signal generation.
mbed_official	87:085cde657901	544	* @param htim : TIM Output Compare handle
mbed_official	87:085cde657901	545	* @param Channel : TIM Channel to be enabled
mbed_official	87:085cde657901	546	* This parameter can be one of the following values:
mbed_official	87:085cde657901	547	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	548	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	549	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	550	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	551	* @retval HAL status
mbed_official	87:085cde657901	552	*/
mbed_official	87:085cde657901	553	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	554	{
mbed_official	87:085cde657901	555	/* Check the parameters */
mbed_official	87:085cde657901	556	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	557
mbed_official	87:085cde657901	558	/* Enable the Output compare channel */
mbed_official	87:085cde657901	559	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	560
mbed_official	87:085cde657901	561	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	562	{
mbed_official	87:085cde657901	563	/* Enable the main output */
mbed_official	87:085cde657901	564	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	565	}
mbed_official	87:085cde657901	566
mbed_official	87:085cde657901	567	/* Enable the Peripheral */
mbed_official	87:085cde657901	568	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	569
mbed_official	87:085cde657901	570	/* Return function status */
mbed_official	87:085cde657901	571	return HAL_OK;
mbed_official	87:085cde657901	572	}
mbed_official	87:085cde657901	573
mbed_official	87:085cde657901	574	/**
mbed_official	87:085cde657901	575	* @brief Stops the TIM Output Compare signal generation.
mbed_official	87:085cde657901	576	* @param htim : TIM handle
mbed_official	87:085cde657901	577	* @param Channel : TIM Channel to be disabled
mbed_official	87:085cde657901	578	* This parameter can be one of the following values:
mbed_official	87:085cde657901	579	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	580	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	581	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	582	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	583	* @retval HAL status
mbed_official	87:085cde657901	584	*/
mbed_official	87:085cde657901	585	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	586	{
mbed_official	87:085cde657901	587	/* Check the parameters */
mbed_official	87:085cde657901	588	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	589
mbed_official	87:085cde657901	590	/* Disable the Output compare channel */
mbed_official	87:085cde657901	591	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	592
mbed_official	87:085cde657901	593	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	594	{
mbed_official	87:085cde657901	595	/* Disable the Main Ouput */
mbed_official	87:085cde657901	596	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	597	}
mbed_official	87:085cde657901	598
mbed_official	87:085cde657901	599	/* Disable the Peripheral */
mbed_official	87:085cde657901	600	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	601
mbed_official	87:085cde657901	602	/* Return function status */
mbed_official	87:085cde657901	603	return HAL_OK;
mbed_official	87:085cde657901	604	}
mbed_official	87:085cde657901	605
mbed_official	87:085cde657901	606	/**
mbed_official	87:085cde657901	607	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official	87:085cde657901	608	* @param htim : TIM OC handle
mbed_official	87:085cde657901	609	* @param Channel : TIM Channel to be enabled
mbed_official	87:085cde657901	610	* This parameter can be one of the following values:
mbed_official	87:085cde657901	611	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	612	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	613	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	614	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	615	* @retval HAL status
mbed_official	87:085cde657901	616	*/
mbed_official	87:085cde657901	617	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	618	{
mbed_official	87:085cde657901	619	/* Check the parameters */
mbed_official	87:085cde657901	620	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	621
mbed_official	87:085cde657901	622	switch (Channel)
mbed_official	87:085cde657901	623	{
mbed_official	87:085cde657901	624	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	625	{
mbed_official	87:085cde657901	626	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	627	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	628	}
mbed_official	87:085cde657901	629	break;
mbed_official	87:085cde657901	630
mbed_official	87:085cde657901	631	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	632	{
mbed_official	87:085cde657901	633	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	634	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	635	}
mbed_official	87:085cde657901	636	break;
mbed_official	87:085cde657901	637
mbed_official	87:085cde657901	638	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	639	{
mbed_official	87:085cde657901	640	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	641	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	642	}
mbed_official	87:085cde657901	643	break;
mbed_official	87:085cde657901	644
mbed_official	87:085cde657901	645	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	646	{
mbed_official	87:085cde657901	647	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	648	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	649	}
mbed_official	87:085cde657901	650	break;
mbed_official	87:085cde657901	651
mbed_official	87:085cde657901	652	default:
mbed_official	87:085cde657901	653	break;
mbed_official	87:085cde657901	654	}
mbed_official	87:085cde657901	655
mbed_official	87:085cde657901	656	/* Enable the Output compare channel */
mbed_official	87:085cde657901	657	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	658
mbed_official	87:085cde657901	659	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	660	{
mbed_official	87:085cde657901	661	/* Enable the main output */
mbed_official	87:085cde657901	662	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	663	}
mbed_official	87:085cde657901	664
mbed_official	87:085cde657901	665	/* Enable the Peripheral */
mbed_official	87:085cde657901	666	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	667
mbed_official	87:085cde657901	668	/* Return function status */
mbed_official	87:085cde657901	669	return HAL_OK;
mbed_official	87:085cde657901	670	}
mbed_official	87:085cde657901	671
mbed_official	87:085cde657901	672	/**
mbed_official	87:085cde657901	673	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official	87:085cde657901	674	* @param htim : TIM Output Compare handle
mbed_official	87:085cde657901	675	* @param Channel : TIM Channel to be disabled
mbed_official	87:085cde657901	676	* This parameter can be one of the following values:
mbed_official	87:085cde657901	677	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	678	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	679	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	680	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	681	* @retval HAL status
mbed_official	87:085cde657901	682	*/
mbed_official	87:085cde657901	683	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	684	{
mbed_official	87:085cde657901	685	/* Check the parameters */
mbed_official	87:085cde657901	686	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	687
mbed_official	87:085cde657901	688	switch (Channel)
mbed_official	87:085cde657901	689	{
mbed_official	87:085cde657901	690	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	691	{
mbed_official	87:085cde657901	692	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	693	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	694	}
mbed_official	87:085cde657901	695	break;
mbed_official	87:085cde657901	696
mbed_official	87:085cde657901	697	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	698	{
mbed_official	87:085cde657901	699	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	700	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	701	}
mbed_official	87:085cde657901	702	break;
mbed_official	87:085cde657901	703
mbed_official	87:085cde657901	704	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	705	{
mbed_official	87:085cde657901	706	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	707	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	708	}
mbed_official	87:085cde657901	709	break;
mbed_official	87:085cde657901	710
mbed_official	87:085cde657901	711	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	712	{
mbed_official	87:085cde657901	713	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	714	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	715	}
mbed_official	87:085cde657901	716	break;
mbed_official	87:085cde657901	717
mbed_official	87:085cde657901	718	default:
mbed_official	87:085cde657901	719	break;
mbed_official	87:085cde657901	720	}
mbed_official	87:085cde657901	721
mbed_official	87:085cde657901	722	/* Disable the Output compare channel */
mbed_official	87:085cde657901	723	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	724
mbed_official	87:085cde657901	725	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	726	{
mbed_official	87:085cde657901	727	/* Disable the Main Ouput */
mbed_official	87:085cde657901	728	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	729	}
mbed_official	87:085cde657901	730
mbed_official	87:085cde657901	731	/* Disable the Peripheral */
mbed_official	87:085cde657901	732	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	733
mbed_official	87:085cde657901	734	/* Return function status */
mbed_official	87:085cde657901	735	return HAL_OK;
mbed_official	87:085cde657901	736	}
mbed_official	87:085cde657901	737
mbed_official	87:085cde657901	738	/**
mbed_official	87:085cde657901	739	* @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official	87:085cde657901	740	* @param htim : TIM Output Compare handle
mbed_official	87:085cde657901	741	* @param Channel : TIM Channel to be enabled
mbed_official	87:085cde657901	742	* This parameter can be one of the following values:
mbed_official	87:085cde657901	743	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	744	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	745	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	746	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	747	* @param pData: The source Buffer address.
mbed_official	87:085cde657901	748	* @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official	87:085cde657901	749	* @retval HAL status
mbed_official	87:085cde657901	750	*/
mbed_official	87:085cde657901	751	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	87:085cde657901	752	{
mbed_official	87:085cde657901	753	/* Check the parameters */
mbed_official	87:085cde657901	754	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	755
mbed_official	87:085cde657901	756	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	757	{
mbed_official	87:085cde657901	758	return HAL_BUSY;
mbed_official	87:085cde657901	759	}
mbed_official	87:085cde657901	760	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	761	{
mbed_official	87:085cde657901	762	if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official	87:085cde657901	763	{
mbed_official	87:085cde657901	764	return HAL_ERROR;
mbed_official	87:085cde657901	765	}
mbed_official	87:085cde657901	766	else
mbed_official	87:085cde657901	767	{
mbed_official	87:085cde657901	768	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	769	}
mbed_official	87:085cde657901	770	}
mbed_official	87:085cde657901	771	switch (Channel)
mbed_official	87:085cde657901	772	{
mbed_official	87:085cde657901	773	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	774	{
mbed_official	87:085cde657901	775	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	776	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	777
mbed_official	87:085cde657901	778	/* Set the DMA error callback */
mbed_official	87:085cde657901	779	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	780
mbed_official	87:085cde657901	781	/* Enable the DMA Stream */
mbed_official	87:085cde657901	782	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official	87:085cde657901	783
mbed_official	87:085cde657901	784	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	785	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	786	}
mbed_official	87:085cde657901	787	break;
mbed_official	87:085cde657901	788
mbed_official	87:085cde657901	789	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	790	{
mbed_official	87:085cde657901	791	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	792	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	793
mbed_official	87:085cde657901	794	/* Set the DMA error callback */
mbed_official	87:085cde657901	795	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	796
mbed_official	87:085cde657901	797	/* Enable the DMA Stream */
mbed_official	87:085cde657901	798	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official	87:085cde657901	799
mbed_official	87:085cde657901	800	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	801	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	802	}
mbed_official	87:085cde657901	803	break;
mbed_official	87:085cde657901	804
mbed_official	87:085cde657901	805	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	806	{
mbed_official	87:085cde657901	807	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	808	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	809
mbed_official	87:085cde657901	810	/* Set the DMA error callback */
mbed_official	87:085cde657901	811	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	812
mbed_official	87:085cde657901	813	/* Enable the DMA Stream */
mbed_official	87:085cde657901	814	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official	87:085cde657901	815
mbed_official	87:085cde657901	816	/* Enable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	817	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	818	}
mbed_official	87:085cde657901	819	break;
mbed_official	87:085cde657901	820
mbed_official	87:085cde657901	821	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	822	{
mbed_official	87:085cde657901	823	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	824	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	825
mbed_official	87:085cde657901	826	/* Set the DMA error callback */
mbed_official	87:085cde657901	827	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	828
mbed_official	87:085cde657901	829	/* Enable the DMA Stream */
mbed_official	87:085cde657901	830	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official	87:085cde657901	831
mbed_official	87:085cde657901	832	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	87:085cde657901	833	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	834	}
mbed_official	87:085cde657901	835	break;
mbed_official	87:085cde657901	836
mbed_official	87:085cde657901	837	default:
mbed_official	87:085cde657901	838	break;
mbed_official	87:085cde657901	839	}
mbed_official	87:085cde657901	840
mbed_official	87:085cde657901	841	/* Enable the Output compare channel */
mbed_official	87:085cde657901	842	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	843
mbed_official	87:085cde657901	844	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	845	{
mbed_official	87:085cde657901	846	/* Enable the main output */
mbed_official	87:085cde657901	847	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	848	}
mbed_official	87:085cde657901	849
mbed_official	87:085cde657901	850	/* Enable the Peripheral */
mbed_official	87:085cde657901	851	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	852
mbed_official	87:085cde657901	853	/* Return function status */
mbed_official	87:085cde657901	854	return HAL_OK;
mbed_official	87:085cde657901	855	}
mbed_official	87:085cde657901	856
mbed_official	87:085cde657901	857	/**
mbed_official	87:085cde657901	858	* @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official	87:085cde657901	859	* @param htim : TIM Output Compare handle
mbed_official	87:085cde657901	860	* @param Channel : TIM Channel to be disabled
mbed_official	87:085cde657901	861	* This parameter can be one of the following values:
mbed_official	87:085cde657901	862	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	863	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	864	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	865	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	866	* @retval HAL status
mbed_official	87:085cde657901	867	*/
mbed_official	87:085cde657901	868	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	869	{
mbed_official	87:085cde657901	870	/* Check the parameters */
mbed_official	87:085cde657901	871	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	872
mbed_official	87:085cde657901	873	switch (Channel)
mbed_official	87:085cde657901	874	{
mbed_official	87:085cde657901	875	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	876	{
mbed_official	87:085cde657901	877	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	878	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	879	}
mbed_official	87:085cde657901	880	break;
mbed_official	87:085cde657901	881
mbed_official	87:085cde657901	882	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	883	{
mbed_official	87:085cde657901	884	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	885	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	886	}
mbed_official	87:085cde657901	887	break;
mbed_official	87:085cde657901	888
mbed_official	87:085cde657901	889	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	890	{
mbed_official	87:085cde657901	891	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	892	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	893	}
mbed_official	87:085cde657901	894	break;
mbed_official	87:085cde657901	895
mbed_official	87:085cde657901	896	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	897	{
mbed_official	87:085cde657901	898	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	899	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	900	}
mbed_official	87:085cde657901	901	break;
mbed_official	87:085cde657901	902
mbed_official	87:085cde657901	903	default:
mbed_official	87:085cde657901	904	break;
mbed_official	87:085cde657901	905	}
mbed_official	87:085cde657901	906
mbed_official	87:085cde657901	907	/* Disable the Output compare channel */
mbed_official	87:085cde657901	908	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	909
mbed_official	87:085cde657901	910	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	911	{
mbed_official	87:085cde657901	912	/* Disable the Main Ouput */
mbed_official	87:085cde657901	913	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	914	}
mbed_official	87:085cde657901	915
mbed_official	87:085cde657901	916	/* Disable the Peripheral */
mbed_official	87:085cde657901	917	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	918
mbed_official	87:085cde657901	919	/* Change the htim state */
mbed_official	87:085cde657901	920	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	921
mbed_official	87:085cde657901	922	/* Return function status */
mbed_official	87:085cde657901	923	return HAL_OK;
mbed_official	87:085cde657901	924	}
mbed_official	87:085cde657901	925
mbed_official	87:085cde657901	926	/**
mbed_official	87:085cde657901	927	* @}
mbed_official	87:085cde657901	928	*/
mbed_official	87:085cde657901	929
mbed_official	87:085cde657901	930	/** @defgroup TIM_Group3 Time PWM functions
mbed_official	87:085cde657901	931	* @brief Time PWM functions
mbed_official	87:085cde657901	932	*
mbed_official	87:085cde657901	933	@verbatim
mbed_official	87:085cde657901	934	==============================================================================
mbed_official	87:085cde657901	935	##### Time PWM functions #####
mbed_official	87:085cde657901	936	==============================================================================
mbed_official	87:085cde657901	937	[..]
mbed_official	87:085cde657901	938	This section provides functions allowing to:
mbed_official	87:085cde657901	939	(+) Initialize and configure the TIM OPWM.
mbed_official	87:085cde657901	940	(+) De-initialize the TIM PWM.
mbed_official	87:085cde657901	941	(+) Start the Time PWM.
mbed_official	87:085cde657901	942	(+) Stop the Time PWM.
mbed_official	87:085cde657901	943	(+) Start the Time PWM and enable interrupt.
mbed_official	87:085cde657901	944	(+) Stop the Time PWM and disable interrupt.
mbed_official	87:085cde657901	945	(+) Start the Time PWM and enable DMA transfer.
mbed_official	87:085cde657901	946	(+) Stop the Time PWM and disable DMA transfer.
mbed_official	87:085cde657901	947
mbed_official	87:085cde657901	948	@endverbatim
mbed_official	87:085cde657901	949	* @{
mbed_official	87:085cde657901	950	*/
mbed_official	87:085cde657901	951	/**
mbed_official	87:085cde657901	952	* @brief Initializes the TIM PWM Time Base according to the specified
mbed_official	87:085cde657901	953	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	87:085cde657901	954	* @param htim: TIM handle
mbed_official	87:085cde657901	955	* @retval HAL status
mbed_official	87:085cde657901	956	*/
mbed_official	87:085cde657901	957	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	958	{
mbed_official	87:085cde657901	959	/* Check the TIM handle allocation */
mbed_official	87:085cde657901	960	if(htim == NULL)
mbed_official	87:085cde657901	961	{
mbed_official	87:085cde657901	962	return HAL_ERROR;
mbed_official	87:085cde657901	963	}
mbed_official	87:085cde657901	964
mbed_official	87:085cde657901	965	/* Check the parameters */
mbed_official	87:085cde657901	966	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	967	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	968	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	969
mbed_official	87:085cde657901	970	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	971	{
mbed_official	87:085cde657901	972	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	973	HAL_TIM_PWM_MspInit(htim);
mbed_official	87:085cde657901	974	}
mbed_official	87:085cde657901	975
mbed_official	87:085cde657901	976	/* Set the TIM state */
mbed_official	87:085cde657901	977	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	978
mbed_official	87:085cde657901	979	/* Init the base time for the PWM */
mbed_official	87:085cde657901	980	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	981
mbed_official	87:085cde657901	982	/* Initialize the TIM state*/
mbed_official	87:085cde657901	983	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	984
mbed_official	87:085cde657901	985	return HAL_OK;
mbed_official	87:085cde657901	986	}
mbed_official	87:085cde657901	987
mbed_official	87:085cde657901	988	/**
mbed_official	87:085cde657901	989	* @brief DeInitializes the TIM peripheral
mbed_official	87:085cde657901	990	* @param htim: TIM handle
mbed_official	87:085cde657901	991	* @retval HAL status
mbed_official	87:085cde657901	992	*/
mbed_official	87:085cde657901	993	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	994	{
mbed_official	87:085cde657901	995	/* Check the parameters */
mbed_official	87:085cde657901	996	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	997
mbed_official	87:085cde657901	998	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	999
mbed_official	87:085cde657901	1000	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	1001	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1002
mbed_official	87:085cde657901	1003	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1004	HAL_TIM_PWM_MspDeInit(htim);
mbed_official	87:085cde657901	1005
mbed_official	87:085cde657901	1006	/* Change TIM state */
mbed_official	87:085cde657901	1007	htim->State = HAL_TIM_STATE_RESET;
mbed_official	87:085cde657901	1008
mbed_official	87:085cde657901	1009	return HAL_OK;
mbed_official	87:085cde657901	1010	}
mbed_official	87:085cde657901	1011
mbed_official	87:085cde657901	1012	/**
mbed_official	87:085cde657901	1013	* @brief Initializes the TIM PWM MSP.
mbed_official	87:085cde657901	1014	* @param htim: TIM handle
mbed_official	87:085cde657901	1015	* @retval None
mbed_official	87:085cde657901	1016	*/
mbed_official	87:085cde657901	1017	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1018	{
mbed_official	87:085cde657901	1019	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1020	the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official	87:085cde657901	1021	*/
mbed_official	87:085cde657901	1022	}
mbed_official	87:085cde657901	1023
mbed_official	87:085cde657901	1024	/**
mbed_official	87:085cde657901	1025	* @brief DeInitializes TIM PWM MSP.
mbed_official	87:085cde657901	1026	* @param htim: TIM handle
mbed_official	87:085cde657901	1027	* @retval None
mbed_official	87:085cde657901	1028	*/
mbed_official	87:085cde657901	1029	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1030	{
mbed_official	87:085cde657901	1031	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1032	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	1033	*/
mbed_official	87:085cde657901	1034	}
mbed_official	87:085cde657901	1035
mbed_official	87:085cde657901	1036	/**
mbed_official	87:085cde657901	1037	* @brief Starts the PWM signal generation.
mbed_official	87:085cde657901	1038	* @param htim : TIM handle
mbed_official	87:085cde657901	1039	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	1040	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1041	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1042	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1043	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1044	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1045	* @retval HAL status
mbed_official	87:085cde657901	1046	*/
mbed_official	87:085cde657901	1047	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1048	{
mbed_official	87:085cde657901	1049	/* Check the parameters */
mbed_official	87:085cde657901	1050	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1051
mbed_official	87:085cde657901	1052	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	1053	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1054
mbed_official	87:085cde657901	1055	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1056	{
mbed_official	87:085cde657901	1057	/* Enable the main output */
mbed_official	87:085cde657901	1058	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	1059	}
mbed_official	87:085cde657901	1060
mbed_official	87:085cde657901	1061	/* Enable the Peripheral */
mbed_official	87:085cde657901	1062	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1063
mbed_official	87:085cde657901	1064	/* Return function status */
mbed_official	87:085cde657901	1065	return HAL_OK;
mbed_official	87:085cde657901	1066	}
mbed_official	87:085cde657901	1067
mbed_official	87:085cde657901	1068	/**
mbed_official	87:085cde657901	1069	* @brief Stops the PWM signal generation.
mbed_official	87:085cde657901	1070	* @param htim : TIM handle
mbed_official	87:085cde657901	1071	* @param Channel : TIM Channels to be disabled
mbed_official	87:085cde657901	1072	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1073	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1074	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1075	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1076	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1077	* @retval HAL status
mbed_official	87:085cde657901	1078	*/
mbed_official	87:085cde657901	1079	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1080	{
mbed_official	87:085cde657901	1081	/* Check the parameters */
mbed_official	87:085cde657901	1082	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1083
mbed_official	87:085cde657901	1084	/* Disable the Capture compare channel */
mbed_official	87:085cde657901	1085	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1086
mbed_official	87:085cde657901	1087	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1088	{
mbed_official	87:085cde657901	1089	/* Disable the Main Ouput */
mbed_official	87:085cde657901	1090	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	1091	}
mbed_official	87:085cde657901	1092
mbed_official	87:085cde657901	1093	/* Disable the Peripheral */
mbed_official	87:085cde657901	1094	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1095
mbed_official	87:085cde657901	1096	/* Change the htim state */
mbed_official	87:085cde657901	1097	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1098
mbed_official	87:085cde657901	1099	/* Return function status */
mbed_official	87:085cde657901	1100	return HAL_OK;
mbed_official	87:085cde657901	1101	}
mbed_official	87:085cde657901	1102
mbed_official	87:085cde657901	1103	/**
mbed_official	87:085cde657901	1104	* @brief Starts the PWM signal generation in interrupt mode.
mbed_official	87:085cde657901	1105	* @param htim : TIM handle
mbed_official	87:085cde657901	1106	* @param Channel : TIM Channel to be disabled
mbed_official	87:085cde657901	1107	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1108	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1109	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1110	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1111	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1112	* @retval HAL status
mbed_official	87:085cde657901	1113	*/
mbed_official	87:085cde657901	1114	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1115	{
mbed_official	87:085cde657901	1116	/* Check the parameters */
mbed_official	87:085cde657901	1117	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1118
mbed_official	87:085cde657901	1119	switch (Channel)
mbed_official	87:085cde657901	1120	{
mbed_official	87:085cde657901	1121	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1122	{
mbed_official	87:085cde657901	1123	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	1124	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	1125	}
mbed_official	87:085cde657901	1126	break;
mbed_official	87:085cde657901	1127
mbed_official	87:085cde657901	1128	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1129	{
mbed_official	87:085cde657901	1130	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	1131	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	1132	}
mbed_official	87:085cde657901	1133	break;
mbed_official	87:085cde657901	1134
mbed_official	87:085cde657901	1135	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1136	{
mbed_official	87:085cde657901	1137	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	1138	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	1139	}
mbed_official	87:085cde657901	1140	break;
mbed_official	87:085cde657901	1141
mbed_official	87:085cde657901	1142	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1143	{
mbed_official	87:085cde657901	1144	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1145	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	1146	}
mbed_official	87:085cde657901	1147	break;
mbed_official	87:085cde657901	1148
mbed_official	87:085cde657901	1149	default:
mbed_official	87:085cde657901	1150	break;
mbed_official	87:085cde657901	1151	}
mbed_official	87:085cde657901	1152
mbed_official	87:085cde657901	1153	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	1154	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1155
mbed_official	87:085cde657901	1156	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1157	{
mbed_official	87:085cde657901	1158	/* Enable the main output */
mbed_official	87:085cde657901	1159	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	1160	}
mbed_official	87:085cde657901	1161
mbed_official	87:085cde657901	1162	/* Enable the Peripheral */
mbed_official	87:085cde657901	1163	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1164
mbed_official	87:085cde657901	1165	/* Return function status */
mbed_official	87:085cde657901	1166	return HAL_OK;
mbed_official	87:085cde657901	1167	}
mbed_official	87:085cde657901	1168
mbed_official	87:085cde657901	1169	/**
mbed_official	87:085cde657901	1170	* @brief Stops the PWM signal generation in interrupt mode.
mbed_official	87:085cde657901	1171	* @param htim : TIM handle
mbed_official	87:085cde657901	1172	* @param Channel : TIM Channels to be disabled
mbed_official	87:085cde657901	1173	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1174	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1175	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1176	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1177	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1178	* @retval HAL status
mbed_official	87:085cde657901	1179	*/
mbed_official	87:085cde657901	1180	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1181	{
mbed_official	87:085cde657901	1182	/* Check the parameters */
mbed_official	87:085cde657901	1183	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1184
mbed_official	87:085cde657901	1185	switch (Channel)
mbed_official	87:085cde657901	1186	{
mbed_official	87:085cde657901	1187	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1188	{
mbed_official	87:085cde657901	1189	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	1190	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	1191	}
mbed_official	87:085cde657901	1192	break;
mbed_official	87:085cde657901	1193
mbed_official	87:085cde657901	1194	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1195	{
mbed_official	87:085cde657901	1196	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	1197	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	1198	}
mbed_official	87:085cde657901	1199	break;
mbed_official	87:085cde657901	1200
mbed_official	87:085cde657901	1201	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1202	{
mbed_official	87:085cde657901	1203	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	1204	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	1205	}
mbed_official	87:085cde657901	1206	break;
mbed_official	87:085cde657901	1207
mbed_official	87:085cde657901	1208	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1209	{
mbed_official	87:085cde657901	1210	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1211	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	1212	}
mbed_official	87:085cde657901	1213	break;
mbed_official	87:085cde657901	1214
mbed_official	87:085cde657901	1215	default:
mbed_official	87:085cde657901	1216	break;
mbed_official	87:085cde657901	1217	}
mbed_official	87:085cde657901	1218
mbed_official	87:085cde657901	1219	/* Disable the Capture compare channel */
mbed_official	87:085cde657901	1220	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1221
mbed_official	87:085cde657901	1222	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1223	{
mbed_official	87:085cde657901	1224	/* Disable the Main Ouput */
mbed_official	87:085cde657901	1225	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	1226	}
mbed_official	87:085cde657901	1227
mbed_official	87:085cde657901	1228	/* Disable the Peripheral */
mbed_official	87:085cde657901	1229	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1230
mbed_official	87:085cde657901	1231	/* Return function status */
mbed_official	87:085cde657901	1232	return HAL_OK;
mbed_official	87:085cde657901	1233	}
mbed_official	87:085cde657901	1234
mbed_official	87:085cde657901	1235	/**
mbed_official	87:085cde657901	1236	* @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official	87:085cde657901	1237	* @param htim : TIM handle
mbed_official	87:085cde657901	1238	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	1239	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1240	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1241	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1242	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1243	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1244	* @param pData: The source Buffer address.
mbed_official	87:085cde657901	1245	* @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official	87:085cde657901	1246	* @retval HAL status
mbed_official	87:085cde657901	1247	*/
mbed_official	87:085cde657901	1248	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	87:085cde657901	1249	{
mbed_official	87:085cde657901	1250	/* Check the parameters */
mbed_official	87:085cde657901	1251	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1252
mbed_official	87:085cde657901	1253	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	1254	{
mbed_official	87:085cde657901	1255	return HAL_BUSY;
mbed_official	87:085cde657901	1256	}
mbed_official	87:085cde657901	1257	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	1258	{
mbed_official	87:085cde657901	1259	if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official	87:085cde657901	1260	{
mbed_official	87:085cde657901	1261	return HAL_ERROR;
mbed_official	87:085cde657901	1262	}
mbed_official	87:085cde657901	1263	else
mbed_official	87:085cde657901	1264	{
mbed_official	87:085cde657901	1265	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1266	}
mbed_official	87:085cde657901	1267	}
mbed_official	87:085cde657901	1268	switch (Channel)
mbed_official	87:085cde657901	1269	{
mbed_official	87:085cde657901	1270	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1271	{
mbed_official	87:085cde657901	1272	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1273	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	1274
mbed_official	87:085cde657901	1275	/* Set the DMA error callback */
mbed_official	87:085cde657901	1276	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1277
mbed_official	87:085cde657901	1278	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1279	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official	87:085cde657901	1280
mbed_official	87:085cde657901	1281	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	1282	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	1283	}
mbed_official	87:085cde657901	1284	break;
mbed_official	87:085cde657901	1285
mbed_official	87:085cde657901	1286	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1287	{
mbed_official	87:085cde657901	1288	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1289	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	1290
mbed_official	87:085cde657901	1291	/* Set the DMA error callback */
mbed_official	87:085cde657901	1292	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1293
mbed_official	87:085cde657901	1294	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1295	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official	87:085cde657901	1296
mbed_official	87:085cde657901	1297	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	1298	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	1299	}
mbed_official	87:085cde657901	1300	break;
mbed_official	87:085cde657901	1301
mbed_official	87:085cde657901	1302	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1303	{
mbed_official	87:085cde657901	1304	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1305	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	1306
mbed_official	87:085cde657901	1307	/* Set the DMA error callback */
mbed_official	87:085cde657901	1308	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1309
mbed_official	87:085cde657901	1310	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1311	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official	87:085cde657901	1312
mbed_official	87:085cde657901	1313	/* Enable the TIM Output Capture/Compare 3 request */
mbed_official	87:085cde657901	1314	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	1315	}
mbed_official	87:085cde657901	1316	break;
mbed_official	87:085cde657901	1317
mbed_official	87:085cde657901	1318	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1319	{
mbed_official	87:085cde657901	1320	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1321	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	1322
mbed_official	87:085cde657901	1323	/* Set the DMA error callback */
mbed_official	87:085cde657901	1324	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1325
mbed_official	87:085cde657901	1326	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1327	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official	87:085cde657901	1328
mbed_official	87:085cde657901	1329	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	87:085cde657901	1330	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	1331	}
mbed_official	87:085cde657901	1332	break;
mbed_official	87:085cde657901	1333
mbed_official	87:085cde657901	1334	default:
mbed_official	87:085cde657901	1335	break;
mbed_official	87:085cde657901	1336	}
mbed_official	87:085cde657901	1337
mbed_official	87:085cde657901	1338	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	1339	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1340
mbed_official	87:085cde657901	1341	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1342	{
mbed_official	87:085cde657901	1343	/* Enable the main output */
mbed_official	87:085cde657901	1344	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	1345	}
mbed_official	87:085cde657901	1346
mbed_official	87:085cde657901	1347	/* Enable the Peripheral */
mbed_official	87:085cde657901	1348	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1349
mbed_official	87:085cde657901	1350	/* Return function status */
mbed_official	87:085cde657901	1351	return HAL_OK;
mbed_official	87:085cde657901	1352	}
mbed_official	87:085cde657901	1353
mbed_official	87:085cde657901	1354	/**
mbed_official	87:085cde657901	1355	* @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official	87:085cde657901	1356	* @param htim : TIM handle
mbed_official	87:085cde657901	1357	* @param Channel : TIM Channels to be disabled
mbed_official	87:085cde657901	1358	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1359	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1360	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1361	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1362	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1363	* @retval HAL status
mbed_official	87:085cde657901	1364	*/
mbed_official	87:085cde657901	1365	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1366	{
mbed_official	87:085cde657901	1367	/* Check the parameters */
mbed_official	87:085cde657901	1368	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1369
mbed_official	87:085cde657901	1370	switch (Channel)
mbed_official	87:085cde657901	1371	{
mbed_official	87:085cde657901	1372	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1373	{
mbed_official	87:085cde657901	1374	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	1375	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	1376	}
mbed_official	87:085cde657901	1377	break;
mbed_official	87:085cde657901	1378
mbed_official	87:085cde657901	1379	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1380	{
mbed_official	87:085cde657901	1381	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	1382	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	1383	}
mbed_official	87:085cde657901	1384	break;
mbed_official	87:085cde657901	1385
mbed_official	87:085cde657901	1386	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1387	{
mbed_official	87:085cde657901	1388	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	1389	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	1390	}
mbed_official	87:085cde657901	1391	break;
mbed_official	87:085cde657901	1392
mbed_official	87:085cde657901	1393	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1394	{
mbed_official	87:085cde657901	1395	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1396	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	1397	}
mbed_official	87:085cde657901	1398	break;
mbed_official	87:085cde657901	1399
mbed_official	87:085cde657901	1400	default:
mbed_official	87:085cde657901	1401	break;
mbed_official	87:085cde657901	1402	}
mbed_official	87:085cde657901	1403
mbed_official	87:085cde657901	1404	/* Disable the Capture compare channel */
mbed_official	87:085cde657901	1405	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1406
mbed_official	87:085cde657901	1407	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1408	{
mbed_official	87:085cde657901	1409	/* Disable the Main Ouput */
mbed_official	87:085cde657901	1410	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	1411	}
mbed_official	87:085cde657901	1412
mbed_official	87:085cde657901	1413	/* Disable the Peripheral */
mbed_official	87:085cde657901	1414	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1415
mbed_official	87:085cde657901	1416	/* Change the htim state */
mbed_official	87:085cde657901	1417	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1418
mbed_official	87:085cde657901	1419	/* Return function status */
mbed_official	87:085cde657901	1420	return HAL_OK;
mbed_official	87:085cde657901	1421	}
mbed_official	87:085cde657901	1422
mbed_official	87:085cde657901	1423	/**
mbed_official	87:085cde657901	1424	* @}
mbed_official	87:085cde657901	1425	*/
mbed_official	87:085cde657901	1426
mbed_official	87:085cde657901	1427	/** @defgroup TIM_Group4 Time Input Capture functions
mbed_official	87:085cde657901	1428	* @brief Time Input Capture functions
mbed_official	87:085cde657901	1429	*
mbed_official	87:085cde657901	1430	@verbatim
mbed_official	87:085cde657901	1431	==============================================================================
mbed_official	87:085cde657901	1432	##### Time Input Capture functions #####
mbed_official	87:085cde657901	1433	==============================================================================
mbed_official	87:085cde657901	1434	[..]
mbed_official	87:085cde657901	1435	This section provides functions allowing to:
mbed_official	87:085cde657901	1436	(+) Initialize and configure the TIM Input Capture.
mbed_official	87:085cde657901	1437	(+) De-initialize the TIM Input Capture.
mbed_official	87:085cde657901	1438	(+) Start the Time Input Capture.
mbed_official	87:085cde657901	1439	(+) Stop the Time Input Capture.
mbed_official	87:085cde657901	1440	(+) Start the Time Input Capture and enable interrupt.
mbed_official	87:085cde657901	1441	(+) Stop the Time Input Capture and disable interrupt.
mbed_official	87:085cde657901	1442	(+) Start the Time Input Capture and enable DMA transfer.
mbed_official	87:085cde657901	1443	(+) Stop the Time Input Capture and disable DMA transfer.
mbed_official	87:085cde657901	1444
mbed_official	87:085cde657901	1445	@endverbatim
mbed_official	87:085cde657901	1446	* @{
mbed_official	87:085cde657901	1447	*/
mbed_official	87:085cde657901	1448	/**
mbed_official	87:085cde657901	1449	* @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official	87:085cde657901	1450	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	87:085cde657901	1451	* @param htim: TIM Input Capture handle
mbed_official	87:085cde657901	1452	* @retval HAL status
mbed_official	87:085cde657901	1453	*/
mbed_official	87:085cde657901	1454	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1455	{
mbed_official	87:085cde657901	1456	/* Check the TIM handle allocation */
mbed_official	87:085cde657901	1457	if(htim == NULL)
mbed_official	87:085cde657901	1458	{
mbed_official	87:085cde657901	1459	return HAL_ERROR;
mbed_official	87:085cde657901	1460	}
mbed_official	87:085cde657901	1461
mbed_official	87:085cde657901	1462	/* Check the parameters */
mbed_official	87:085cde657901	1463	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1464	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	1465	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	1466
mbed_official	87:085cde657901	1467	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	1468	{
mbed_official	87:085cde657901	1469	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1470	HAL_TIM_IC_MspInit(htim);
mbed_official	87:085cde657901	1471	}
mbed_official	87:085cde657901	1472
mbed_official	87:085cde657901	1473	/* Set the TIM state */
mbed_official	87:085cde657901	1474	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1475
mbed_official	87:085cde657901	1476	/* Init the base time for the input capture */
mbed_official	87:085cde657901	1477	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	1478
mbed_official	87:085cde657901	1479	/* Initialize the TIM state*/
mbed_official	87:085cde657901	1480	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1481
mbed_official	87:085cde657901	1482	return HAL_OK;
mbed_official	87:085cde657901	1483	}
mbed_official	87:085cde657901	1484
mbed_official	87:085cde657901	1485	/**
mbed_official	87:085cde657901	1486	* @brief DeInitializes the TIM peripheral
mbed_official	87:085cde657901	1487	* @param htim: TIM Input Capture handle
mbed_official	87:085cde657901	1488	* @retval HAL status
mbed_official	87:085cde657901	1489	*/
mbed_official	87:085cde657901	1490	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1491	{
mbed_official	87:085cde657901	1492	/* Check the parameters */
mbed_official	87:085cde657901	1493	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1494
mbed_official	87:085cde657901	1495	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1496
mbed_official	87:085cde657901	1497	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	1498	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1499
mbed_official	87:085cde657901	1500	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1501	HAL_TIM_IC_MspDeInit(htim);
mbed_official	87:085cde657901	1502
mbed_official	87:085cde657901	1503	/* Change TIM state */
mbed_official	87:085cde657901	1504	htim->State = HAL_TIM_STATE_RESET;
mbed_official	87:085cde657901	1505
mbed_official	87:085cde657901	1506	return HAL_OK;
mbed_official	87:085cde657901	1507	}
mbed_official	87:085cde657901	1508
mbed_official	87:085cde657901	1509	/**
mbed_official	87:085cde657901	1510	* @brief Initializes the TIM INput Capture MSP.
mbed_official	87:085cde657901	1511	* @param htim: TIM handle
mbed_official	87:085cde657901	1512	* @retval None
mbed_official	87:085cde657901	1513	*/
mbed_official	87:085cde657901	1514	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1515	{
mbed_official	87:085cde657901	1516	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1517	the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official	87:085cde657901	1518	*/
mbed_official	87:085cde657901	1519	}
mbed_official	87:085cde657901	1520
mbed_official	87:085cde657901	1521	/**
mbed_official	87:085cde657901	1522	* @brief DeInitializes TIM Input Capture MSP.
mbed_official	87:085cde657901	1523	* @param htim: TIM handle
mbed_official	87:085cde657901	1524	* @retval None
mbed_official	87:085cde657901	1525	*/
mbed_official	87:085cde657901	1526	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1527	{
mbed_official	87:085cde657901	1528	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1529	the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	1530	*/
mbed_official	87:085cde657901	1531	}
mbed_official	87:085cde657901	1532
mbed_official	87:085cde657901	1533	/**
mbed_official	87:085cde657901	1534	* @brief Starts the TIM Input Capture measurement.
mbed_official	87:085cde657901	1535	* @param hdma : TIM Input Capture handle
mbed_official	87:085cde657901	1536	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	1537	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1538	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1539	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1540	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1541	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1542	* @retval HAL status
mbed_official	87:085cde657901	1543	*/
mbed_official	87:085cde657901	1544	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1545	{
mbed_official	87:085cde657901	1546	/* Check the parameters */
mbed_official	87:085cde657901	1547	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1548
mbed_official	87:085cde657901	1549	/* Enable the Input Capture channel */
mbed_official	87:085cde657901	1550	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1551
mbed_official	87:085cde657901	1552	/* Enable the Peripheral */
mbed_official	87:085cde657901	1553	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1554
mbed_official	87:085cde657901	1555	/* Return function status */
mbed_official	87:085cde657901	1556	return HAL_OK;
mbed_official	87:085cde657901	1557	}
mbed_official	87:085cde657901	1558
mbed_official	87:085cde657901	1559	/**
mbed_official	87:085cde657901	1560	* @brief Stops the TIM Input Capture measurement.
mbed_official	87:085cde657901	1561	* @param htim : TIM handle
mbed_official	87:085cde657901	1562	* @param Channel : TIM Channels to be disabled
mbed_official	87:085cde657901	1563	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1564	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1565	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1566	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1567	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1568	* @retval HAL status
mbed_official	87:085cde657901	1569	*/
mbed_official	87:085cde657901	1570	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1571	{
mbed_official	87:085cde657901	1572	/* Check the parameters */
mbed_official	87:085cde657901	1573	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1574
mbed_official	87:085cde657901	1575	/* Disable the Input Capture channel */
mbed_official	87:085cde657901	1576	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1577
mbed_official	87:085cde657901	1578	/* Disable the Peripheral */
mbed_official	87:085cde657901	1579	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1580
mbed_official	87:085cde657901	1581	/* Return function status */
mbed_official	87:085cde657901	1582	return HAL_OK;
mbed_official	87:085cde657901	1583	}
mbed_official	87:085cde657901	1584
mbed_official	87:085cde657901	1585	/**
mbed_official	87:085cde657901	1586	* @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official	87:085cde657901	1587	* @param hdma : TIM Input Capture handle
mbed_official	87:085cde657901	1588	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	1589	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1590	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1591	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1592	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1593	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1594	* @retval HAL status
mbed_official	87:085cde657901	1595	*/
mbed_official	87:085cde657901	1596	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1597	{
mbed_official	87:085cde657901	1598	/* Check the parameters */
mbed_official	87:085cde657901	1599	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1600
mbed_official	87:085cde657901	1601	switch (Channel)
mbed_official	87:085cde657901	1602	{
mbed_official	87:085cde657901	1603	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1604	{
mbed_official	87:085cde657901	1605	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	1606	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	1607	}
mbed_official	87:085cde657901	1608	break;
mbed_official	87:085cde657901	1609
mbed_official	87:085cde657901	1610	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1611	{
mbed_official	87:085cde657901	1612	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	1613	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	1614	}
mbed_official	87:085cde657901	1615	break;
mbed_official	87:085cde657901	1616
mbed_official	87:085cde657901	1617	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1618	{
mbed_official	87:085cde657901	1619	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	1620	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	1621	}
mbed_official	87:085cde657901	1622	break;
mbed_official	87:085cde657901	1623
mbed_official	87:085cde657901	1624	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1625	{
mbed_official	87:085cde657901	1626	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1627	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	1628	}
mbed_official	87:085cde657901	1629	break;
mbed_official	87:085cde657901	1630
mbed_official	87:085cde657901	1631	default:
mbed_official	87:085cde657901	1632	break;
mbed_official	87:085cde657901	1633	}
mbed_official	87:085cde657901	1634	/* Enable the Input Capture channel */
mbed_official	87:085cde657901	1635	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1636
mbed_official	87:085cde657901	1637	/* Enable the Peripheral */
mbed_official	87:085cde657901	1638	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1639
mbed_official	87:085cde657901	1640	/* Return function status */
mbed_official	87:085cde657901	1641	return HAL_OK;
mbed_official	87:085cde657901	1642	}
mbed_official	87:085cde657901	1643
mbed_official	87:085cde657901	1644	/**
mbed_official	87:085cde657901	1645	* @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official	87:085cde657901	1646	* @param htim : TIM handle
mbed_official	87:085cde657901	1647	* @param Channel : TIM Channels to be disabled
mbed_official	87:085cde657901	1648	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1649	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1650	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1651	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1652	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1653	* @retval HAL status
mbed_official	87:085cde657901	1654	*/
mbed_official	87:085cde657901	1655	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1656	{
mbed_official	87:085cde657901	1657	/* Check the parameters */
mbed_official	87:085cde657901	1658	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1659
mbed_official	87:085cde657901	1660	switch (Channel)
mbed_official	87:085cde657901	1661	{
mbed_official	87:085cde657901	1662	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1663	{
mbed_official	87:085cde657901	1664	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	1665	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	1666	}
mbed_official	87:085cde657901	1667	break;
mbed_official	87:085cde657901	1668
mbed_official	87:085cde657901	1669	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1670	{
mbed_official	87:085cde657901	1671	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	1672	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	1673	}
mbed_official	87:085cde657901	1674	break;
mbed_official	87:085cde657901	1675
mbed_official	87:085cde657901	1676	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1677	{
mbed_official	87:085cde657901	1678	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	1679	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	1680	}
mbed_official	87:085cde657901	1681	break;
mbed_official	87:085cde657901	1682
mbed_official	87:085cde657901	1683	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1684	{
mbed_official	87:085cde657901	1685	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1686	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	1687	}
mbed_official	87:085cde657901	1688	break;
mbed_official	87:085cde657901	1689
mbed_official	87:085cde657901	1690	default:
mbed_official	87:085cde657901	1691	break;
mbed_official	87:085cde657901	1692	}
mbed_official	87:085cde657901	1693
mbed_official	87:085cde657901	1694	/* Disable the Input Capture channel */
mbed_official	87:085cde657901	1695	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1696
mbed_official	87:085cde657901	1697	/* Disable the Peripheral */
mbed_official	87:085cde657901	1698	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1699
mbed_official	87:085cde657901	1700	/* Return function status */
mbed_official	87:085cde657901	1701	return HAL_OK;
mbed_official	87:085cde657901	1702	}
mbed_official	87:085cde657901	1703
mbed_official	87:085cde657901	1704	/**
mbed_official	87:085cde657901	1705	* @brief Starts the TIM Input Capture measurement on in DMA mode.
mbed_official	87:085cde657901	1706	* @param htim : TIM Input Capture handle
mbed_official	87:085cde657901	1707	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	1708	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1709	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1710	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1711	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1712	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1713	* @param pData: The destination Buffer address.
mbed_official	87:085cde657901	1714	* @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official	87:085cde657901	1715	* @retval HAL status
mbed_official	87:085cde657901	1716	*/
mbed_official	87:085cde657901	1717	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	87:085cde657901	1718	{
mbed_official	87:085cde657901	1719	/* Check the parameters */
mbed_official	87:085cde657901	1720	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1721	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1722
mbed_official	87:085cde657901	1723	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	1724	{
mbed_official	87:085cde657901	1725	return HAL_BUSY;
mbed_official	87:085cde657901	1726	}
mbed_official	87:085cde657901	1727	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	1728	{
mbed_official	87:085cde657901	1729	if((pData == 0 ) && (Length > 0))
mbed_official	87:085cde657901	1730	{
mbed_official	87:085cde657901	1731	return HAL_ERROR;
mbed_official	87:085cde657901	1732	}
mbed_official	87:085cde657901	1733	else
mbed_official	87:085cde657901	1734	{
mbed_official	87:085cde657901	1735	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1736	}
mbed_official	87:085cde657901	1737	}
mbed_official	87:085cde657901	1738
mbed_official	87:085cde657901	1739	switch (Channel)
mbed_official	87:085cde657901	1740	{
mbed_official	87:085cde657901	1741	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1742	{
mbed_official	87:085cde657901	1743	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1744	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	1745
mbed_official	87:085cde657901	1746	/* Set the DMA error callback */
mbed_official	87:085cde657901	1747	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1748
mbed_official	87:085cde657901	1749	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1750	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official	87:085cde657901	1751
mbed_official	87:085cde657901	1752	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	1753	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	1754	}
mbed_official	87:085cde657901	1755	break;
mbed_official	87:085cde657901	1756
mbed_official	87:085cde657901	1757	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1758	{
mbed_official	87:085cde657901	1759	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1760	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	1761
mbed_official	87:085cde657901	1762	/* Set the DMA error callback */
mbed_official	87:085cde657901	1763	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1764
mbed_official	87:085cde657901	1765	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1766	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official	87:085cde657901	1767
mbed_official	87:085cde657901	1768	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	1769	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	1770	}
mbed_official	87:085cde657901	1771	break;
mbed_official	87:085cde657901	1772
mbed_official	87:085cde657901	1773	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1774	{
mbed_official	87:085cde657901	1775	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1776	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	1777
mbed_official	87:085cde657901	1778	/* Set the DMA error callback */
mbed_official	87:085cde657901	1779	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1780
mbed_official	87:085cde657901	1781	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1782	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official	87:085cde657901	1783
mbed_official	87:085cde657901	1784	/* Enable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	1785	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	1786	}
mbed_official	87:085cde657901	1787	break;
mbed_official	87:085cde657901	1788
mbed_official	87:085cde657901	1789	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1790	{
mbed_official	87:085cde657901	1791	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1792	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	1793
mbed_official	87:085cde657901	1794	/* Set the DMA error callback */
mbed_official	87:085cde657901	1795	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1796
mbed_official	87:085cde657901	1797	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1798	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official	87:085cde657901	1799
mbed_official	87:085cde657901	1800	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	87:085cde657901	1801	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	1802	}
mbed_official	87:085cde657901	1803	break;
mbed_official	87:085cde657901	1804
mbed_official	87:085cde657901	1805	default:
mbed_official	87:085cde657901	1806	break;
mbed_official	87:085cde657901	1807	}
mbed_official	87:085cde657901	1808
mbed_official	87:085cde657901	1809	/* Enable the Input Capture channel */
mbed_official	87:085cde657901	1810	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1811
mbed_official	87:085cde657901	1812	/* Enable the Peripheral */
mbed_official	87:085cde657901	1813	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1814
mbed_official	87:085cde657901	1815	/* Return function status */
mbed_official	87:085cde657901	1816	return HAL_OK;
mbed_official	87:085cde657901	1817	}
mbed_official	87:085cde657901	1818
mbed_official	87:085cde657901	1819	/**
mbed_official	87:085cde657901	1820	* @brief Stops the TIM Input Capture measurement on in DMA mode.
mbed_official	87:085cde657901	1821	* @param htim : TIM Input Capture handle
mbed_official	87:085cde657901	1822	* @param Channel : TIM Channels to be disabled
mbed_official	87:085cde657901	1823	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1824	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1825	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1826	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1827	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1828	* @retval HAL status
mbed_official	87:085cde657901	1829	*/
mbed_official	87:085cde657901	1830	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1831	{
mbed_official	87:085cde657901	1832	/* Check the parameters */
mbed_official	87:085cde657901	1833	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1834	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1835
mbed_official	87:085cde657901	1836	switch (Channel)
mbed_official	87:085cde657901	1837	{
mbed_official	87:085cde657901	1838	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1839	{
mbed_official	87:085cde657901	1840	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	1841	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	1842	}
mbed_official	87:085cde657901	1843	break;
mbed_official	87:085cde657901	1844
mbed_official	87:085cde657901	1845	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1846	{
mbed_official	87:085cde657901	1847	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	1848	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	1849	}
mbed_official	87:085cde657901	1850	break;
mbed_official	87:085cde657901	1851
mbed_official	87:085cde657901	1852	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1853	{
mbed_official	87:085cde657901	1854	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	1855	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	1856	}
mbed_official	87:085cde657901	1857	break;
mbed_official	87:085cde657901	1858
mbed_official	87:085cde657901	1859	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1860	{
mbed_official	87:085cde657901	1861	/* Disable the TIM Capture/Compare 4 DMA request */
mbed_official	87:085cde657901	1862	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	1863	}
mbed_official	87:085cde657901	1864	break;
mbed_official	87:085cde657901	1865
mbed_official	87:085cde657901	1866	default:
mbed_official	87:085cde657901	1867	break;
mbed_official	87:085cde657901	1868	}
mbed_official	87:085cde657901	1869
mbed_official	87:085cde657901	1870	/* Disable the Input Capture channel */
mbed_official	87:085cde657901	1871	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1872
mbed_official	87:085cde657901	1873	/* Disable the Peripheral */
mbed_official	87:085cde657901	1874	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1875
mbed_official	87:085cde657901	1876	/* Change the htim state */
mbed_official	87:085cde657901	1877	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1878
mbed_official	87:085cde657901	1879	/* Return function status */
mbed_official	87:085cde657901	1880	return HAL_OK;
mbed_official	87:085cde657901	1881	}
mbed_official	87:085cde657901	1882	/**
mbed_official	87:085cde657901	1883	* @}
mbed_official	87:085cde657901	1884	*/
mbed_official	87:085cde657901	1885
mbed_official	87:085cde657901	1886	/** @defgroup TIM_Group5 Time One Pulse functions
mbed_official	87:085cde657901	1887	* @brief Time One Pulse functions
mbed_official	87:085cde657901	1888	*
mbed_official	87:085cde657901	1889	@verbatim
mbed_official	87:085cde657901	1890	==============================================================================
mbed_official	87:085cde657901	1891	##### Time One Pulse functions #####
mbed_official	87:085cde657901	1892	==============================================================================
mbed_official	87:085cde657901	1893	[..]
mbed_official	87:085cde657901	1894	This section provides functions allowing to:
mbed_official	87:085cde657901	1895	(+) Initialize and configure the TIM One Pulse.
mbed_official	87:085cde657901	1896	(+) De-initialize the TIM One Pulse.
mbed_official	87:085cde657901	1897	(+) Start the Time One Pulse.
mbed_official	87:085cde657901	1898	(+) Stop the Time One Pulse.
mbed_official	87:085cde657901	1899	(+) Start the Time One Pulse and enable interrupt.
mbed_official	87:085cde657901	1900	(+) Stop the Time One Pulse and disable interrupt.
mbed_official	87:085cde657901	1901	(+) Start the Time One Pulse and enable DMA transfer.
mbed_official	87:085cde657901	1902	(+) Stop the Time One Pulse and disable DMA transfer.
mbed_official	87:085cde657901	1903
mbed_official	87:085cde657901	1904	@endverbatim
mbed_official	87:085cde657901	1905	* @{
mbed_official	87:085cde657901	1906	*/
mbed_official	87:085cde657901	1907	/**
mbed_official	87:085cde657901	1908	* @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official	87:085cde657901	1909	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	87:085cde657901	1910	* @param htim: TIM OnePulse handle
mbed_official	87:085cde657901	1911	* @param OnePulseMode: Select the One pulse mode.
mbed_official	87:085cde657901	1912	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1913	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official	87:085cde657901	1914	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
mbed_official	87:085cde657901	1915	* @retval HAL status
mbed_official	87:085cde657901	1916	*/
mbed_official	87:085cde657901	1917	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official	87:085cde657901	1918	{
mbed_official	87:085cde657901	1919	/* Check the TIM handle allocation */
mbed_official	87:085cde657901	1920	if(htim == NULL)
mbed_official	87:085cde657901	1921	{
mbed_official	87:085cde657901	1922	return HAL_ERROR;
mbed_official	87:085cde657901	1923	}
mbed_official	87:085cde657901	1924
mbed_official	87:085cde657901	1925	/* Check the parameters */
mbed_official	87:085cde657901	1926	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1927	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	1928	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	1929	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official	87:085cde657901	1930
mbed_official	87:085cde657901	1931	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	1932	{
mbed_official	87:085cde657901	1933	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1934	HAL_TIM_OnePulse_MspInit(htim);
mbed_official	87:085cde657901	1935	}
mbed_official	87:085cde657901	1936
mbed_official	87:085cde657901	1937	/* Set the TIM state */
mbed_official	87:085cde657901	1938	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1939
mbed_official	87:085cde657901	1940	/* Configure the Time base in the One Pulse Mode */
mbed_official	87:085cde657901	1941	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	1942
mbed_official	87:085cde657901	1943	/* Reset the OPM Bit */
mbed_official	87:085cde657901	1944	htim->Instance->CR1 &= ~TIM_CR1_OPM;
mbed_official	87:085cde657901	1945
mbed_official	87:085cde657901	1946	/* Configure the OPM Mode */
mbed_official	87:085cde657901	1947	htim->Instance->CR1 \|= OnePulseMode;
mbed_official	87:085cde657901	1948
mbed_official	87:085cde657901	1949	/* Initialize the TIM state*/
mbed_official	87:085cde657901	1950	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1951
mbed_official	87:085cde657901	1952	return HAL_OK;
mbed_official	87:085cde657901	1953	}
mbed_official	87:085cde657901	1954
mbed_official	87:085cde657901	1955	/**
mbed_official	87:085cde657901	1956	* @brief DeInitializes the TIM One Pulse
mbed_official	87:085cde657901	1957	* @param htim: TIM One Pulse handle
mbed_official	87:085cde657901	1958	* @retval HAL status
mbed_official	87:085cde657901	1959	*/
mbed_official	87:085cde657901	1960	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1961	{
mbed_official	87:085cde657901	1962	/* Check the parameters */
mbed_official	87:085cde657901	1963	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1964
mbed_official	87:085cde657901	1965	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1966
mbed_official	87:085cde657901	1967	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	1968	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1969
mbed_official	87:085cde657901	1970	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	87:085cde657901	1971	HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official	87:085cde657901	1972
mbed_official	87:085cde657901	1973	/* Change TIM state */
mbed_official	87:085cde657901	1974	htim->State = HAL_TIM_STATE_RESET;
mbed_official	87:085cde657901	1975
mbed_official	87:085cde657901	1976	return HAL_OK;
mbed_official	87:085cde657901	1977	}
mbed_official	87:085cde657901	1978
mbed_official	87:085cde657901	1979	/**
mbed_official	87:085cde657901	1980	* @brief Initializes the TIM One Pulse MSP.
mbed_official	87:085cde657901	1981	* @param htim: TIM handle
mbed_official	87:085cde657901	1982	* @retval None
mbed_official	87:085cde657901	1983	*/
mbed_official	87:085cde657901	1984	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1985	{
mbed_official	87:085cde657901	1986	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1987	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official	87:085cde657901	1988	*/
mbed_official	87:085cde657901	1989	}
mbed_official	87:085cde657901	1990
mbed_official	87:085cde657901	1991	/**
mbed_official	87:085cde657901	1992	* @brief DeInitializes TIM One Pulse MSP.
mbed_official	87:085cde657901	1993	* @param htim: TIM handle
mbed_official	87:085cde657901	1994	* @retval None
mbed_official	87:085cde657901	1995	*/
mbed_official	87:085cde657901	1996	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1997	{
mbed_official	87:085cde657901	1998	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1999	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	2000	*/
mbed_official	87:085cde657901	2001	}
mbed_official	87:085cde657901	2002
mbed_official	87:085cde657901	2003	/**
mbed_official	87:085cde657901	2004	* @brief Starts the TIM One Pulse signal generation.
mbed_official	87:085cde657901	2005	* @param htim : TIM One Pulse handle
mbed_official	87:085cde657901	2006	* @param OutputChannel : TIM Channels to be enabled
mbed_official	87:085cde657901	2007	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2008	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2009	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2010	* @retval HAL status
mbed_official	87:085cde657901	2011	*/
mbed_official	87:085cde657901	2012	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	87:085cde657901	2013	{
mbed_official	87:085cde657901	2014	/* Enable the Capture compare and the Input Capture channels
mbed_official	87:085cde657901	2015	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	87:085cde657901	2016	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	87:085cde657901	2017	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	87:085cde657901	2018	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official	87:085cde657901	2019
mbed_official	87:085cde657901	2020	No need to enable the counter, it's enabled automatically by hardware
mbed_official	87:085cde657901	2021	(the counter starts in response to a stimulus and generate a pulse */
mbed_official	87:085cde657901	2022
mbed_official	87:085cde657901	2023	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2024	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2025
mbed_official	87:085cde657901	2026	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	2027	{
mbed_official	87:085cde657901	2028	/* Enable the main output */
mbed_official	87:085cde657901	2029	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	2030	}
mbed_official	87:085cde657901	2031
mbed_official	87:085cde657901	2032	/* Return function status */
mbed_official	87:085cde657901	2033	return HAL_OK;
mbed_official	87:085cde657901	2034	}
mbed_official	87:085cde657901	2035
mbed_official	87:085cde657901	2036	/**
mbed_official	87:085cde657901	2037	* @brief Stops the TIM One Pulse signal generation.
mbed_official	87:085cde657901	2038	* @param htim : TIM One Pulse handle
mbed_official	87:085cde657901	2039	* @param OutputChannel : TIM Channels to be disable
mbed_official	87:085cde657901	2040	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2041	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2042	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2043	* @retval HAL status
mbed_official	87:085cde657901	2044	*/
mbed_official	87:085cde657901	2045	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	87:085cde657901	2046	{
mbed_official	87:085cde657901	2047	/* Disable the Capture compare and the Input Capture channels
mbed_official	87:085cde657901	2048	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	87:085cde657901	2049	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	87:085cde657901	2050	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	87:085cde657901	2051	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official	87:085cde657901	2052
mbed_official	87:085cde657901	2053	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2054	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2055
mbed_official	87:085cde657901	2056	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	2057	{
mbed_official	87:085cde657901	2058	/* Disable the Main Ouput */
mbed_official	87:085cde657901	2059	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	2060	}
mbed_official	87:085cde657901	2061
mbed_official	87:085cde657901	2062	/* Disable the Peripheral */
mbed_official	87:085cde657901	2063	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2064
mbed_official	87:085cde657901	2065	/* Return function status */
mbed_official	87:085cde657901	2066	return HAL_OK;
mbed_official	87:085cde657901	2067	}
mbed_official	87:085cde657901	2068
mbed_official	87:085cde657901	2069	/**
mbed_official	87:085cde657901	2070	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official	87:085cde657901	2071	* @param htim : TIM One Pulse handle
mbed_official	87:085cde657901	2072	* @param OutputChannel : TIM Channels to be enabled
mbed_official	87:085cde657901	2073	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2074	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2075	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2076	* @retval HAL status
mbed_official	87:085cde657901	2077	*/
mbed_official	87:085cde657901	2078	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	87:085cde657901	2079	{
mbed_official	87:085cde657901	2080	/* Enable the Capture compare and the Input Capture channels
mbed_official	87:085cde657901	2081	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	87:085cde657901	2082	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	87:085cde657901	2083	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	87:085cde657901	2084	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official	87:085cde657901	2085
mbed_official	87:085cde657901	2086	No need to enable the counter, it's enabled automatically by hardware
mbed_official	87:085cde657901	2087	(the counter starts in response to a stimulus and generate a pulse */
mbed_official	87:085cde657901	2088
mbed_official	87:085cde657901	2089	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	2090	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2091
mbed_official	87:085cde657901	2092	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	2093	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2094
mbed_official	87:085cde657901	2095	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2096	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2097
mbed_official	87:085cde657901	2098	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	2099	{
mbed_official	87:085cde657901	2100	/* Enable the main output */
mbed_official	87:085cde657901	2101	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	2102	}
mbed_official	87:085cde657901	2103
mbed_official	87:085cde657901	2104	/* Return function status */
mbed_official	87:085cde657901	2105	return HAL_OK;
mbed_official	87:085cde657901	2106	}
mbed_official	87:085cde657901	2107
mbed_official	87:085cde657901	2108	/**
mbed_official	87:085cde657901	2109	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official	87:085cde657901	2110	* @param htim : TIM One Pulse handle
mbed_official	87:085cde657901	2111	* @param OutputChannel : TIM Channels to be enabled
mbed_official	87:085cde657901	2112	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2113	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2114	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2115	* @retval HAL status
mbed_official	87:085cde657901	2116	*/
mbed_official	87:085cde657901	2117	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	87:085cde657901	2118	{
mbed_official	87:085cde657901	2119	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	2120	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2121
mbed_official	87:085cde657901	2122	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	2123	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2124
mbed_official	87:085cde657901	2125	/* Disable the Capture compare and the Input Capture channels
mbed_official	87:085cde657901	2126	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	87:085cde657901	2127	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	87:085cde657901	2128	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	87:085cde657901	2129	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official	87:085cde657901	2130	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2131	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2132
mbed_official	87:085cde657901	2133	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	2134	{
mbed_official	87:085cde657901	2135	/* Disable the Main Ouput */
mbed_official	87:085cde657901	2136	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	2137	}
mbed_official	87:085cde657901	2138
mbed_official	87:085cde657901	2139	/* Disable the Peripheral */
mbed_official	87:085cde657901	2140	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2141
mbed_official	87:085cde657901	2142	/* Return function status */
mbed_official	87:085cde657901	2143	return HAL_OK;
mbed_official	87:085cde657901	2144	}
mbed_official	87:085cde657901	2145
mbed_official	87:085cde657901	2146	/**
mbed_official	87:085cde657901	2147	* @}
mbed_official	87:085cde657901	2148	*/
mbed_official	87:085cde657901	2149
mbed_official	87:085cde657901	2150	/** @defgroup TIM_Group6 Time Encoder functions
mbed_official	87:085cde657901	2151	* @brief Time Encoder functions
mbed_official	87:085cde657901	2152	*
mbed_official	87:085cde657901	2153	@verbatim
mbed_official	87:085cde657901	2154	==============================================================================
mbed_official	87:085cde657901	2155	##### Time Encoder functions #####
mbed_official	87:085cde657901	2156	==============================================================================
mbed_official	87:085cde657901	2157	[..]
mbed_official	87:085cde657901	2158	This section provides functions allowing to:
mbed_official	87:085cde657901	2159	(+) Initialize and configure the TIM Encoder.
mbed_official	87:085cde657901	2160	(+) De-initialize the TIM Encoder.
mbed_official	87:085cde657901	2161	(+) Start the Time Encoder.
mbed_official	87:085cde657901	2162	(+) Stop the Time Encoder.
mbed_official	87:085cde657901	2163	(+) Start the Time Encoder and enable interrupt.
mbed_official	87:085cde657901	2164	(+) Stop the Time Encoder and disable interrupt.
mbed_official	87:085cde657901	2165	(+) Start the Time Encoder and enable DMA transfer.
mbed_official	87:085cde657901	2166	(+) Stop the Time Encoder and disable DMA transfer.
mbed_official	87:085cde657901	2167
mbed_official	87:085cde657901	2168	@endverbatim
mbed_official	87:085cde657901	2169	* @{
mbed_official	87:085cde657901	2170	*/
mbed_official	87:085cde657901	2171	/**
mbed_official	87:085cde657901	2172	* @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official	87:085cde657901	2173	* @param htim: TIM Encoder Interface handle
mbed_official	87:085cde657901	2174	* @param sConfig: TIM Encoder Interface configuration structure
mbed_official	87:085cde657901	2175	* @retval HAL status
mbed_official	87:085cde657901	2176	*/
mbed_official	87:085cde657901	2177	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
mbed_official	87:085cde657901	2178	{
mbed_official	87:085cde657901	2179	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	2180	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	2181	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	2182
mbed_official	87:085cde657901	2183	/* Check the TIM handle allocation */
mbed_official	87:085cde657901	2184	if(htim == NULL)
mbed_official	87:085cde657901	2185	{
mbed_official	87:085cde657901	2186	return HAL_ERROR;
mbed_official	87:085cde657901	2187	}
mbed_official	87:085cde657901	2188
mbed_official	87:085cde657901	2189	/* Check the parameters */
mbed_official	87:085cde657901	2190	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2191	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official	87:085cde657901	2192	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official	87:085cde657901	2193	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official	87:085cde657901	2194	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official	87:085cde657901	2195	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official	87:085cde657901	2196	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official	87:085cde657901	2197	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official	87:085cde657901	2198	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official	87:085cde657901	2199	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official	87:085cde657901	2200
mbed_official	87:085cde657901	2201	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	2202	{
mbed_official	87:085cde657901	2203	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	2204	HAL_TIM_Encoder_MspInit(htim);
mbed_official	87:085cde657901	2205	}
mbed_official	87:085cde657901	2206
mbed_official	87:085cde657901	2207	/* Set the TIM state */
mbed_official	87:085cde657901	2208	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2209
mbed_official	87:085cde657901	2210	/* Reset the SMS bits */
mbed_official	87:085cde657901	2211	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	2212
mbed_official	87:085cde657901	2213	/* Configure the Time base in the Encoder Mode */
mbed_official	87:085cde657901	2214	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	2215
mbed_official	87:085cde657901	2216	/* Get the TIMx SMCR register value */
mbed_official	87:085cde657901	2217	tmpsmcr = htim->Instance->SMCR;
mbed_official	87:085cde657901	2218
mbed_official	87:085cde657901	2219	/* Get the TIMx CCMR1 register value */
mbed_official	87:085cde657901	2220	tmpccmr1 = htim->Instance->CCMR1;
mbed_official	87:085cde657901	2221
mbed_official	87:085cde657901	2222	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	2223	tmpccer = htim->Instance->CCER;
mbed_official	87:085cde657901	2224
mbed_official	87:085cde657901	2225	/* Set the encoder Mode */
mbed_official	87:085cde657901	2226	tmpsmcr \|= sConfig->EncoderMode;
mbed_official	87:085cde657901	2227
mbed_official	87:085cde657901	2228	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official	87:085cde657901	2229	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
mbed_official	87:085cde657901	2230	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
mbed_official	87:085cde657901	2231
mbed_official	87:085cde657901	2232	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official	87:085cde657901	2233	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
mbed_official	87:085cde657901	2234	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
mbed_official	87:085cde657901	2235	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
mbed_official	87:085cde657901	2236	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
mbed_official	87:085cde657901	2237
mbed_official	87:085cde657901	2238	/* Set the TI1 and the TI2 Polarities */
mbed_official	87:085cde657901	2239	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
mbed_official	87:085cde657901	2240	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
mbed_official	87:085cde657901	2241	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
mbed_official	87:085cde657901	2242
mbed_official	87:085cde657901	2243	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	2244	htim->Instance->SMCR = tmpsmcr;
mbed_official	87:085cde657901	2245
mbed_official	87:085cde657901	2246	/* Write to TIMx CCMR1 */
mbed_official	87:085cde657901	2247	htim->Instance->CCMR1 = tmpccmr1;
mbed_official	87:085cde657901	2248
mbed_official	87:085cde657901	2249	/* Write to TIMx CCER */
mbed_official	87:085cde657901	2250	htim->Instance->CCER = tmpccer;
mbed_official	87:085cde657901	2251
mbed_official	87:085cde657901	2252	/* Initialize the TIM state*/
mbed_official	87:085cde657901	2253	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2254
mbed_official	87:085cde657901	2255	return HAL_OK;
mbed_official	87:085cde657901	2256	}
mbed_official	87:085cde657901	2257
mbed_official	87:085cde657901	2258	/**
mbed_official	87:085cde657901	2259	* @brief DeInitializes the TIM Encoder interface
mbed_official	87:085cde657901	2260	* @param htim: TIM Encoder handle
mbed_official	87:085cde657901	2261	* @retval HAL status
mbed_official	87:085cde657901	2262	*/
mbed_official	87:085cde657901	2263	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2264	{
mbed_official	87:085cde657901	2265	/* Check the parameters */
mbed_official	87:085cde657901	2266	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2267
mbed_official	87:085cde657901	2268	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2269
mbed_official	87:085cde657901	2270	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	2271	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2272
mbed_official	87:085cde657901	2273	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	87:085cde657901	2274	HAL_TIM_Encoder_MspDeInit(htim);
mbed_official	87:085cde657901	2275
mbed_official	87:085cde657901	2276	/* Change TIM state */
mbed_official	87:085cde657901	2277	htim->State = HAL_TIM_STATE_RESET;
mbed_official	87:085cde657901	2278
mbed_official	87:085cde657901	2279	return HAL_OK;
mbed_official	87:085cde657901	2280	}
mbed_official	87:085cde657901	2281
mbed_official	87:085cde657901	2282	/**
mbed_official	87:085cde657901	2283	* @brief Initializes the TIM Encoder Interface MSP.
mbed_official	87:085cde657901	2284	* @param htim: TIM handle
mbed_official	87:085cde657901	2285	* @retval None
mbed_official	87:085cde657901	2286	*/
mbed_official	87:085cde657901	2287	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2288	{
mbed_official	87:085cde657901	2289	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	2290	the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official	87:085cde657901	2291	*/
mbed_official	87:085cde657901	2292	}
mbed_official	87:085cde657901	2293
mbed_official	87:085cde657901	2294	/**
mbed_official	87:085cde657901	2295	* @brief DeInitializes TIM Encoder Interface MSP.
mbed_official	87:085cde657901	2296	* @param htim: TIM handle
mbed_official	87:085cde657901	2297	* @retval None
mbed_official	87:085cde657901	2298	*/
mbed_official	87:085cde657901	2299	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2300	{
mbed_official	87:085cde657901	2301	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	2302	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	2303	*/
mbed_official	87:085cde657901	2304	}
mbed_official	87:085cde657901	2305
mbed_official	87:085cde657901	2306	/**
mbed_official	87:085cde657901	2307	* @brief Starts the TIM Encoder Interface.
mbed_official	87:085cde657901	2308	* @param htim : TIM Encoder Interface handle
mbed_official	87:085cde657901	2309	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	2310	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2311	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2312	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2313	* @retval HAL status
mbed_official	87:085cde657901	2314	*/
mbed_official	87:085cde657901	2315	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2316	{
mbed_official	87:085cde657901	2317	/* Check the parameters */
mbed_official	87:085cde657901	2318	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2319
mbed_official	87:085cde657901	2320	/* Enable the encoder interface channels */
mbed_official	87:085cde657901	2321	switch (Channel)
mbed_official	87:085cde657901	2322	{
mbed_official	87:085cde657901	2323	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2324	{
mbed_official	87:085cde657901	2325	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2326	break;
mbed_official	87:085cde657901	2327	}
mbed_official	87:085cde657901	2328	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2329	{
mbed_official	87:085cde657901	2330	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2331	break;
mbed_official	87:085cde657901	2332	}
mbed_official	87:085cde657901	2333	default :
mbed_official	87:085cde657901	2334	{
mbed_official	87:085cde657901	2335	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2336	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2337	break;
mbed_official	87:085cde657901	2338	}
mbed_official	87:085cde657901	2339	}
mbed_official	87:085cde657901	2340	/* Enable the Peripheral */
mbed_official	87:085cde657901	2341	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2342
mbed_official	87:085cde657901	2343	/* Return function status */
mbed_official	87:085cde657901	2344	return HAL_OK;
mbed_official	87:085cde657901	2345	}
mbed_official	87:085cde657901	2346
mbed_official	87:085cde657901	2347	/**
mbed_official	87:085cde657901	2348	* @brief Stops the TIM Encoder Interface.
mbed_official	87:085cde657901	2349	* @param htim : TIM Encoder Interface handle
mbed_official	87:085cde657901	2350	* @param Channel : TIM Channels to be disabled
mbed_official	87:085cde657901	2351	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2352	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2353	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2354	* @retval HAL status
mbed_official	87:085cde657901	2355	*/
mbed_official	87:085cde657901	2356	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2357	{
mbed_official	87:085cde657901	2358	/* Check the parameters */
mbed_official	87:085cde657901	2359	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2360
mbed_official	87:085cde657901	2361	/* Disable the Input Capture channels 1 and 2
mbed_official	87:085cde657901	2362	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	87:085cde657901	2363	switch (Channel)
mbed_official	87:085cde657901	2364	{
mbed_official	87:085cde657901	2365	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2366	{
mbed_official	87:085cde657901	2367	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2368	break;
mbed_official	87:085cde657901	2369	}
mbed_official	87:085cde657901	2370	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2371	{
mbed_official	87:085cde657901	2372	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2373	break;
mbed_official	87:085cde657901	2374	}
mbed_official	87:085cde657901	2375	default :
mbed_official	87:085cde657901	2376	{
mbed_official	87:085cde657901	2377	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2378	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2379	break;
mbed_official	87:085cde657901	2380	}
mbed_official	87:085cde657901	2381	}
mbed_official	87:085cde657901	2382	/* Disable the Peripheral */
mbed_official	87:085cde657901	2383	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2384
mbed_official	87:085cde657901	2385	/* Return function status */
mbed_official	87:085cde657901	2386	return HAL_OK;
mbed_official	87:085cde657901	2387	}
mbed_official	87:085cde657901	2388
mbed_official	87:085cde657901	2389	/**
mbed_official	87:085cde657901	2390	* @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official	87:085cde657901	2391	* @param htim : TIM Encoder Interface handle
mbed_official	87:085cde657901	2392	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	2393	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2394	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2395	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2396	* @retval HAL status
mbed_official	87:085cde657901	2397	*/
mbed_official	87:085cde657901	2398	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2399	{
mbed_official	87:085cde657901	2400	/* Check the parameters */
mbed_official	87:085cde657901	2401	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2402
mbed_official	87:085cde657901	2403	/* Enable the encoder interface channels */
mbed_official	87:085cde657901	2404	/* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official	87:085cde657901	2405	switch (Channel)
mbed_official	87:085cde657901	2406	{
mbed_official	87:085cde657901	2407	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2408	{
mbed_official	87:085cde657901	2409	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2410	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2411	break;
mbed_official	87:085cde657901	2412	}
mbed_official	87:085cde657901	2413	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2414	{
mbed_official	87:085cde657901	2415	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2416	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2417	break;
mbed_official	87:085cde657901	2418	}
mbed_official	87:085cde657901	2419	default :
mbed_official	87:085cde657901	2420	{
mbed_official	87:085cde657901	2421	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2422	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2423	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2424	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2425	break;
mbed_official	87:085cde657901	2426	}
mbed_official	87:085cde657901	2427	}
mbed_official	87:085cde657901	2428
mbed_official	87:085cde657901	2429	/* Enable the Peripheral */
mbed_official	87:085cde657901	2430	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2431
mbed_official	87:085cde657901	2432	/* Return function status */
mbed_official	87:085cde657901	2433	return HAL_OK;
mbed_official	87:085cde657901	2434	}
mbed_official	87:085cde657901	2435
mbed_official	87:085cde657901	2436	/**
mbed_official	87:085cde657901	2437	* @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official	87:085cde657901	2438	* @param htim : TIM Encoder Interface handle
mbed_official	87:085cde657901	2439	* @param Channel : TIM Channels to be disabled
mbed_official	87:085cde657901	2440	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2441	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2442	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2443	* @retval HAL status
mbed_official	87:085cde657901	2444	*/
mbed_official	87:085cde657901	2445	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2446	{
mbed_official	87:085cde657901	2447	/* Check the parameters */
mbed_official	87:085cde657901	2448	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2449
mbed_official	87:085cde657901	2450	/* Disable the Input Capture channels 1 and 2
mbed_official	87:085cde657901	2451	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	87:085cde657901	2452	if(Channel == TIM_CHANNEL_1)
mbed_official	87:085cde657901	2453	{
mbed_official	87:085cde657901	2454	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2455
mbed_official	87:085cde657901	2456	/* Disable the capture compare Interrupts 1 */
mbed_official	87:085cde657901	2457	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2458	}
mbed_official	87:085cde657901	2459	else if(Channel == TIM_CHANNEL_2)
mbed_official	87:085cde657901	2460	{
mbed_official	87:085cde657901	2461	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2462
mbed_official	87:085cde657901	2463	/* Disable the capture compare Interrupts 2 */
mbed_official	87:085cde657901	2464	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2465	}
mbed_official	87:085cde657901	2466	else
mbed_official	87:085cde657901	2467	{
mbed_official	87:085cde657901	2468	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2469	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2470
mbed_official	87:085cde657901	2471	/* Disable the capture compare Interrupts 1 and 2 */
mbed_official	87:085cde657901	2472	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2473	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2474	}
mbed_official	87:085cde657901	2475
mbed_official	87:085cde657901	2476	/* Disable the Peripheral */
mbed_official	87:085cde657901	2477	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2478
mbed_official	87:085cde657901	2479	/* Change the htim state */
mbed_official	87:085cde657901	2480	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2481
mbed_official	87:085cde657901	2482	/* Return function status */
mbed_official	87:085cde657901	2483	return HAL_OK;
mbed_official	87:085cde657901	2484	}
mbed_official	87:085cde657901	2485
mbed_official	87:085cde657901	2486	/**
mbed_official	87:085cde657901	2487	* @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official	87:085cde657901	2488	* @param htim : TIM Encoder Interface handle
mbed_official	87:085cde657901	2489	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	2490	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2491	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2492	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2493	* @param pData1: The destination Buffer address for IC1.
mbed_official	87:085cde657901	2494	* @param pData2: The destination Buffer address for IC2.
mbed_official	87:085cde657901	2495	* @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official	87:085cde657901	2496	* @retval HAL status
mbed_official	87:085cde657901	2497	*/
mbed_official	87:085cde657901	2498	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
mbed_official	87:085cde657901	2499	{
mbed_official	87:085cde657901	2500	/* Check the parameters */
mbed_official	87:085cde657901	2501	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2502
mbed_official	87:085cde657901	2503	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	2504	{
mbed_official	87:085cde657901	2505	return HAL_BUSY;
mbed_official	87:085cde657901	2506	}
mbed_official	87:085cde657901	2507	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	2508	{
mbed_official	87:085cde657901	2509	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
mbed_official	87:085cde657901	2510	{
mbed_official	87:085cde657901	2511	return HAL_ERROR;
mbed_official	87:085cde657901	2512	}
mbed_official	87:085cde657901	2513	else
mbed_official	87:085cde657901	2514	{
mbed_official	87:085cde657901	2515	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2516	}
mbed_official	87:085cde657901	2517	}
mbed_official	87:085cde657901	2518
mbed_official	87:085cde657901	2519	switch (Channel)
mbed_official	87:085cde657901	2520	{
mbed_official	87:085cde657901	2521	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2522	{
mbed_official	87:085cde657901	2523	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	2524	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	2525
mbed_official	87:085cde657901	2526	/* Set the DMA error callback */
mbed_official	87:085cde657901	2527	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	2528
mbed_official	87:085cde657901	2529	/* Enable the DMA Stream */
mbed_official	87:085cde657901	2530	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official	87:085cde657901	2531
mbed_official	87:085cde657901	2532	/* Enable the TIM Input Capture DMA request */
mbed_official	87:085cde657901	2533	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	2534
mbed_official	87:085cde657901	2535	/* Enable the Peripheral */
mbed_official	87:085cde657901	2536	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2537
mbed_official	87:085cde657901	2538	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	2539	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2540	}
mbed_official	87:085cde657901	2541	break;
mbed_official	87:085cde657901	2542
mbed_official	87:085cde657901	2543	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2544	{
mbed_official	87:085cde657901	2545	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	2546	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	2547
mbed_official	87:085cde657901	2548	/* Set the DMA error callback */
mbed_official	87:085cde657901	2549	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
mbed_official	87:085cde657901	2550	/* Enable the DMA Stream */
mbed_official	87:085cde657901	2551	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official	87:085cde657901	2552
mbed_official	87:085cde657901	2553	/* Enable the TIM Input Capture DMA request */
mbed_official	87:085cde657901	2554	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	2555
mbed_official	87:085cde657901	2556	/* Enable the Peripheral */
mbed_official	87:085cde657901	2557	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2558
mbed_official	87:085cde657901	2559	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	2560	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2561	}
mbed_official	87:085cde657901	2562	break;
mbed_official	87:085cde657901	2563
mbed_official	87:085cde657901	2564	case TIM_CHANNEL_ALL:
mbed_official	87:085cde657901	2565	{
mbed_official	87:085cde657901	2566	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	2567	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	2568
mbed_official	87:085cde657901	2569	/* Set the DMA error callback */
mbed_official	87:085cde657901	2570	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	2571
mbed_official	87:085cde657901	2572	/* Enable the DMA Stream */
mbed_official	87:085cde657901	2573	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official	87:085cde657901	2574
mbed_official	87:085cde657901	2575	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	2576	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	2577
mbed_official	87:085cde657901	2578	/* Set the DMA error callback */
mbed_official	87:085cde657901	2579	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	2580
mbed_official	87:085cde657901	2581	/* Enable the DMA Stream */
mbed_official	87:085cde657901	2582	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official	87:085cde657901	2583
mbed_official	87:085cde657901	2584	/* Enable the Peripheral */
mbed_official	87:085cde657901	2585	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2586
mbed_official	87:085cde657901	2587	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	2588	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2589	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2590
mbed_official	87:085cde657901	2591	/* Enable the TIM Input Capture DMA request */
mbed_official	87:085cde657901	2592	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	2593	/* Enable the TIM Input Capture DMA request */
mbed_official	87:085cde657901	2594	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	2595	}
mbed_official	87:085cde657901	2596	break;
mbed_official	87:085cde657901	2597
mbed_official	87:085cde657901	2598	default:
mbed_official	87:085cde657901	2599	break;
mbed_official	87:085cde657901	2600	}
mbed_official	87:085cde657901	2601	/* Return function status */
mbed_official	87:085cde657901	2602	return HAL_OK;
mbed_official	87:085cde657901	2603	}
mbed_official	87:085cde657901	2604
mbed_official	87:085cde657901	2605	/**
mbed_official	87:085cde657901	2606	* @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official	87:085cde657901	2607	* @param htim : TIM Encoder Interface handle
mbed_official	87:085cde657901	2608	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	2609	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2610	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2611	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2612	* @retval HAL status
mbed_official	87:085cde657901	2613	*/
mbed_official	87:085cde657901	2614	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2615	{
mbed_official	87:085cde657901	2616	/* Check the parameters */
mbed_official	87:085cde657901	2617	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2618
mbed_official	87:085cde657901	2619	/* Disable the Input Capture channels 1 and 2
mbed_official	87:085cde657901	2620	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	87:085cde657901	2621	if(Channel == TIM_CHANNEL_1)
mbed_official	87:085cde657901	2622	{
mbed_official	87:085cde657901	2623	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2624
mbed_official	87:085cde657901	2625	/* Disable the capture compare DMA Request 1 */
mbed_official	87:085cde657901	2626	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	2627	}
mbed_official	87:085cde657901	2628	else if(Channel == TIM_CHANNEL_2)
mbed_official	87:085cde657901	2629	{
mbed_official	87:085cde657901	2630	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2631
mbed_official	87:085cde657901	2632	/* Disable the capture compare DMA Request 2 */
mbed_official	87:085cde657901	2633	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	2634	}
mbed_official	87:085cde657901	2635	else
mbed_official	87:085cde657901	2636	{
mbed_official	87:085cde657901	2637	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2638	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2639
mbed_official	87:085cde657901	2640	/* Disable the capture compare DMA Request 1 and 2 */
mbed_official	87:085cde657901	2641	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	2642	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	2643	}
mbed_official	87:085cde657901	2644
mbed_official	87:085cde657901	2645	/* Disable the Peripheral */
mbed_official	87:085cde657901	2646	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2647
mbed_official	87:085cde657901	2648	/* Change the htim state */
mbed_official	87:085cde657901	2649	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2650
mbed_official	87:085cde657901	2651	/* Return function status */
mbed_official	87:085cde657901	2652	return HAL_OK;
mbed_official	87:085cde657901	2653	}
mbed_official	87:085cde657901	2654
mbed_official	87:085cde657901	2655	/**
mbed_official	87:085cde657901	2656	* @}
mbed_official	87:085cde657901	2657	*/
mbed_official	87:085cde657901	2658	/** @defgroup TIM_Group7 TIM IRQ handler management
mbed_official	87:085cde657901	2659	* @brief IRQ handler management
mbed_official	87:085cde657901	2660	*
mbed_official	87:085cde657901	2661	@verbatim
mbed_official	87:085cde657901	2662	==============================================================================
mbed_official	87:085cde657901	2663	##### IRQ handler management #####
mbed_official	87:085cde657901	2664	==============================================================================
mbed_official	87:085cde657901	2665	[..]
mbed_official	87:085cde657901	2666	This section provides Timer IRQ handler function.
mbed_official	87:085cde657901	2667
mbed_official	87:085cde657901	2668	@endverbatim
mbed_official	87:085cde657901	2669	* @{
mbed_official	87:085cde657901	2670	*/
mbed_official	87:085cde657901	2671	/**
mbed_official	87:085cde657901	2672	* @brief This function handles TIM interrupts requests.
mbed_official	87:085cde657901	2673	* @param htim: TIM handle
mbed_official	87:085cde657901	2674	* @retval None
mbed_official	87:085cde657901	2675	*/
mbed_official	87:085cde657901	2676	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2677	{
mbed_official	87:085cde657901	2678	/* Capture compare 1 event */
mbed_official	87:085cde657901	2679	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official	87:085cde657901	2680	{
mbed_official	87:085cde657901	2681	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
mbed_official	87:085cde657901	2682	{
mbed_official	87:085cde657901	2683	{
mbed_official	87:085cde657901	2684	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2685	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official	87:085cde657901	2686
mbed_official	87:085cde657901	2687	/* Input capture event */
mbed_official	87:085cde657901	2688	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official	87:085cde657901	2689	{
mbed_official	87:085cde657901	2690	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	2691	}
mbed_official	87:085cde657901	2692	/* Output compare event */
mbed_official	87:085cde657901	2693	else
mbed_official	87:085cde657901	2694	{
mbed_official	87:085cde657901	2695	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	87:085cde657901	2696	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	2697	}
mbed_official	87:085cde657901	2698	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	87:085cde657901	2699	}
mbed_official	87:085cde657901	2700	}
mbed_official	87:085cde657901	2701	}
mbed_official	87:085cde657901	2702	/* Capture compare 2 event */
mbed_official	87:085cde657901	2703	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official	87:085cde657901	2704	{
mbed_official	87:085cde657901	2705	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
mbed_official	87:085cde657901	2706	{
mbed_official	87:085cde657901	2707	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2708	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official	87:085cde657901	2709	/* Input capture event */
mbed_official	87:085cde657901	2710	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official	87:085cde657901	2711	{
mbed_official	87:085cde657901	2712	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	2713	}
mbed_official	87:085cde657901	2714	/* Output compare event */
mbed_official	87:085cde657901	2715	else
mbed_official	87:085cde657901	2716	{
mbed_official	87:085cde657901	2717	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	87:085cde657901	2718	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	2719	}
mbed_official	87:085cde657901	2720	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	87:085cde657901	2721	}
mbed_official	87:085cde657901	2722	}
mbed_official	87:085cde657901	2723	/* Capture compare 3 event */
mbed_official	87:085cde657901	2724	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official	87:085cde657901	2725	{
mbed_official	87:085cde657901	2726	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
mbed_official	87:085cde657901	2727	{
mbed_official	87:085cde657901	2728	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	2729	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official	87:085cde657901	2730	/* Input capture event */
mbed_official	87:085cde657901	2731	if((htim->Instance->CCMR1 & TIM_CCMR2_CC3S) != 0x00)
mbed_official	87:085cde657901	2732	{
mbed_official	87:085cde657901	2733	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	2734	}
mbed_official	87:085cde657901	2735	/* Output compare event */
mbed_official	87:085cde657901	2736	else
mbed_official	87:085cde657901	2737	{
mbed_official	87:085cde657901	2738	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	87:085cde657901	2739	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	2740	}
mbed_official	87:085cde657901	2741	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	87:085cde657901	2742	}
mbed_official	87:085cde657901	2743	}
mbed_official	87:085cde657901	2744	/* Capture compare 4 event */
mbed_official	87:085cde657901	2745	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official	87:085cde657901	2746	{
mbed_official	87:085cde657901	2747	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
mbed_official	87:085cde657901	2748	{
mbed_official	87:085cde657901	2749	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	2750	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official	87:085cde657901	2751	/* Input capture event */
mbed_official	87:085cde657901	2752	if((htim->Instance->CCMR1 & TIM_CCMR2_CC4S) != 0x00)
mbed_official	87:085cde657901	2753	{
mbed_official	87:085cde657901	2754	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	2755	}
mbed_official	87:085cde657901	2756	/* Output compare event */
mbed_official	87:085cde657901	2757	else
mbed_official	87:085cde657901	2758	{
mbed_official	87:085cde657901	2759	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	87:085cde657901	2760	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	2761	}
mbed_official	87:085cde657901	2762	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	87:085cde657901	2763	}
mbed_official	87:085cde657901	2764	}
mbed_official	87:085cde657901	2765	/* TIM Update event */
mbed_official	87:085cde657901	2766	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official	87:085cde657901	2767	{
mbed_official	87:085cde657901	2768	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
mbed_official	87:085cde657901	2769	{
mbed_official	87:085cde657901	2770	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official	87:085cde657901	2771	HAL_TIM_PeriodElapsedCallback(htim);
mbed_official	87:085cde657901	2772	}
mbed_official	87:085cde657901	2773	}
mbed_official	87:085cde657901	2774	/* TIM Break input event */
mbed_official	87:085cde657901	2775	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
mbed_official	87:085cde657901	2776	{
mbed_official	87:085cde657901	2777	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
mbed_official	87:085cde657901	2778	{
mbed_official	87:085cde657901	2779	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
mbed_official	87:085cde657901	2780	HAL_TIMEx_BreakCallback(htim);
mbed_official	87:085cde657901	2781	}
mbed_official	87:085cde657901	2782	}
mbed_official	87:085cde657901	2783	/* TIM Trigger detection event */
mbed_official	87:085cde657901	2784	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official	87:085cde657901	2785	{
mbed_official	87:085cde657901	2786	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official	87:085cde657901	2787	{
mbed_official	87:085cde657901	2788	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official	87:085cde657901	2789	HAL_TIM_TriggerCallback(htim);
mbed_official	87:085cde657901	2790	}
mbed_official	87:085cde657901	2791	}
mbed_official	87:085cde657901	2792	/* TIM commutation event */
mbed_official	87:085cde657901	2793	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
mbed_official	87:085cde657901	2794	{
mbed_official	87:085cde657901	2795	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
mbed_official	87:085cde657901	2796	{
mbed_official	87:085cde657901	2797	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
mbed_official	87:085cde657901	2798	HAL_TIMEx_CommutationCallback(htim);
mbed_official	87:085cde657901	2799	}
mbed_official	87:085cde657901	2800	}
mbed_official	87:085cde657901	2801	}
mbed_official	87:085cde657901	2802
mbed_official	87:085cde657901	2803	/**
mbed_official	87:085cde657901	2804	* @}
mbed_official	87:085cde657901	2805	*/
mbed_official	87:085cde657901	2806
mbed_official	87:085cde657901	2807	/** @defgroup TIM_Group8 Peripheral Control functions
mbed_official	87:085cde657901	2808	* @brief Peripheral Control functions
mbed_official	87:085cde657901	2809	*
mbed_official	87:085cde657901	2810	@verbatim
mbed_official	87:085cde657901	2811	==============================================================================
mbed_official	87:085cde657901	2812	##### Peripheral Control functions #####
mbed_official	87:085cde657901	2813	==============================================================================
mbed_official	87:085cde657901	2814	[..]
mbed_official	87:085cde657901	2815	This section provides functions allowing to:
mbed_official	87:085cde657901	2816	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official	87:085cde657901	2817	(+) Configure External Clock source.
mbed_official	87:085cde657901	2818	(+) Configure Complementary channels, break features and dead time.
mbed_official	87:085cde657901	2819	(+) Configure Master and the Slave synchronization.
mbed_official	87:085cde657901	2820	(+) Configure the DMA Burst Mode.
mbed_official	87:085cde657901	2821
mbed_official	87:085cde657901	2822	@endverbatim
mbed_official	87:085cde657901	2823	* @{
mbed_official	87:085cde657901	2824	*/
mbed_official	87:085cde657901	2825
mbed_official	87:085cde657901	2826	/**
mbed_official	87:085cde657901	2827	* @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official	87:085cde657901	2828	* parameters in the TIM_OC_InitTypeDef.
mbed_official	87:085cde657901	2829	* @param htim: TIM Output Compare handle
mbed_official	87:085cde657901	2830	* @param sConfig: TIM Output Compare configuration structure
mbed_official	87:085cde657901	2831	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	2832	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2833	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2834	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2835	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	2836	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	2837	* @retval HAL status
mbed_official	87:085cde657901	2838	*/
mbed_official	87:085cde657901	2839	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	87:085cde657901	2840	{
mbed_official	87:085cde657901	2841	/* Check the parameters */
mbed_official	87:085cde657901	2842	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	87:085cde657901	2843	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official	87:085cde657901	2844	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official	87:085cde657901	2845	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official	87:085cde657901	2846	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official	87:085cde657901	2847	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official	87:085cde657901	2848	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official	87:085cde657901	2849
mbed_official	87:085cde657901	2850	/* Check input state */
mbed_official	87:085cde657901	2851	__HAL_LOCK(htim);
mbed_official	87:085cde657901	2852
mbed_official	87:085cde657901	2853	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2854
mbed_official	87:085cde657901	2855	switch (Channel)
mbed_official	87:085cde657901	2856	{
mbed_official	87:085cde657901	2857	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2858	{
mbed_official	87:085cde657901	2859	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2860	/* Configure the TIM Channel 1 in Output Compare */
mbed_official	87:085cde657901	2861	TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	2862	}
mbed_official	87:085cde657901	2863	break;
mbed_official	87:085cde657901	2864
mbed_official	87:085cde657901	2865	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2866	{
mbed_official	87:085cde657901	2867	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2868	/* Configure the TIM Channel 2 in Output Compare */
mbed_official	87:085cde657901	2869	TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	2870	}
mbed_official	87:085cde657901	2871	break;
mbed_official	87:085cde657901	2872
mbed_official	87:085cde657901	2873	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	2874	{
mbed_official	87:085cde657901	2875	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2876	/* Configure the TIM Channel 3 in Output Compare */
mbed_official	87:085cde657901	2877	TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	2878	}
mbed_official	87:085cde657901	2879	break;
mbed_official	87:085cde657901	2880
mbed_official	87:085cde657901	2881	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	2882	{
mbed_official	87:085cde657901	2883	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2884	/* Configure the TIM Channel 4 in Output Compare */
mbed_official	87:085cde657901	2885	TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	2886	}
mbed_official	87:085cde657901	2887	break;
mbed_official	87:085cde657901	2888
mbed_official	87:085cde657901	2889	default:
mbed_official	87:085cde657901	2890	break;
mbed_official	87:085cde657901	2891	}
mbed_official	87:085cde657901	2892	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2893
mbed_official	87:085cde657901	2894	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	2895
mbed_official	87:085cde657901	2896	return HAL_OK;
mbed_official	87:085cde657901	2897	}
mbed_official	87:085cde657901	2898
mbed_official	87:085cde657901	2899	/**
mbed_official	87:085cde657901	2900	* @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official	87:085cde657901	2901	* parameters in the TIM_IC_InitTypeDef.
mbed_official	87:085cde657901	2902	* @param htim: TIM IC handle
mbed_official	87:085cde657901	2903	* @param sConfig: TIM Input Capture configuration structure
mbed_official	87:085cde657901	2904	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	2905	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2906	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2907	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2908	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	2909	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	2910	* @retval HAL status
mbed_official	87:085cde657901	2911	*/
mbed_official	87:085cde657901	2912	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	87:085cde657901	2913	{
mbed_official	87:085cde657901	2914	/* Check the parameters */
mbed_official	87:085cde657901	2915	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2916	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official	87:085cde657901	2917	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official	87:085cde657901	2918	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official	87:085cde657901	2919	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official	87:085cde657901	2920
mbed_official	87:085cde657901	2921	__HAL_LOCK(htim);
mbed_official	87:085cde657901	2922
mbed_official	87:085cde657901	2923	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2924
mbed_official	87:085cde657901	2925	if (Channel == TIM_CHANNEL_1)
mbed_official	87:085cde657901	2926	{
mbed_official	87:085cde657901	2927	/* TI1 Configuration */
mbed_official	87:085cde657901	2928	TIM_TI1_SetConfig(htim->Instance,
mbed_official	87:085cde657901	2929	sConfig->ICPolarity,
mbed_official	87:085cde657901	2930	sConfig->ICSelection,
mbed_official	87:085cde657901	2931	sConfig->ICFilter);
mbed_official	87:085cde657901	2932
mbed_official	87:085cde657901	2933	/* Reset the IC1PSC Bits */
mbed_official	87:085cde657901	2934	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official	87:085cde657901	2935
mbed_official	87:085cde657901	2936	/* Set the IC1PSC value */
mbed_official	87:085cde657901	2937	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
mbed_official	87:085cde657901	2938	}
mbed_official	87:085cde657901	2939	else if (Channel == TIM_CHANNEL_2)
mbed_official	87:085cde657901	2940	{
mbed_official	87:085cde657901	2941	/* TI2 Configuration */
mbed_official	87:085cde657901	2942	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2943
mbed_official	87:085cde657901	2944	TIM_TI2_SetConfig(htim->Instance,
mbed_official	87:085cde657901	2945	sConfig->ICPolarity,
mbed_official	87:085cde657901	2946	sConfig->ICSelection,
mbed_official	87:085cde657901	2947	sConfig->ICFilter);
mbed_official	87:085cde657901	2948
mbed_official	87:085cde657901	2949	/* Reset the IC2PSC Bits */
mbed_official	87:085cde657901	2950	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official	87:085cde657901	2951
mbed_official	87:085cde657901	2952	/* Set the IC2PSC value */
mbed_official	87:085cde657901	2953	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
mbed_official	87:085cde657901	2954	}
mbed_official	87:085cde657901	2955	else if (Channel == TIM_CHANNEL_3)
mbed_official	87:085cde657901	2956	{
mbed_official	87:085cde657901	2957	/* TI3 Configuration */
mbed_official	87:085cde657901	2958	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2959
mbed_official	87:085cde657901	2960	TIM_TI3_SetConfig(htim->Instance,
mbed_official	87:085cde657901	2961	sConfig->ICPolarity,
mbed_official	87:085cde657901	2962	sConfig->ICSelection,
mbed_official	87:085cde657901	2963	sConfig->ICFilter);
mbed_official	87:085cde657901	2964
mbed_official	87:085cde657901	2965	/* Reset the IC3PSC Bits */
mbed_official	87:085cde657901	2966	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
mbed_official	87:085cde657901	2967
mbed_official	87:085cde657901	2968	/* Set the IC3PSC value */
mbed_official	87:085cde657901	2969	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
mbed_official	87:085cde657901	2970	}
mbed_official	87:085cde657901	2971	else
mbed_official	87:085cde657901	2972	{
mbed_official	87:085cde657901	2973	/* TI4 Configuration */
mbed_official	87:085cde657901	2974	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2975
mbed_official	87:085cde657901	2976	TIM_TI4_SetConfig(htim->Instance,
mbed_official	87:085cde657901	2977	sConfig->ICPolarity,
mbed_official	87:085cde657901	2978	sConfig->ICSelection,
mbed_official	87:085cde657901	2979	sConfig->ICFilter);
mbed_official	87:085cde657901	2980
mbed_official	87:085cde657901	2981	/* Reset the IC4PSC Bits */
mbed_official	87:085cde657901	2982	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
mbed_official	87:085cde657901	2983
mbed_official	87:085cde657901	2984	/* Set the IC4PSC value */
mbed_official	87:085cde657901	2985	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
mbed_official	87:085cde657901	2986	}
mbed_official	87:085cde657901	2987
mbed_official	87:085cde657901	2988	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2989
mbed_official	87:085cde657901	2990	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	2991
mbed_official	87:085cde657901	2992	return HAL_OK;
mbed_official	87:085cde657901	2993	}
mbed_official	87:085cde657901	2994
mbed_official	87:085cde657901	2995	/**
mbed_official	87:085cde657901	2996	* @brief Initializes the TIM PWM channels according to the specified
mbed_official	87:085cde657901	2997	* parameters in the TIM_OC_InitTypeDef.
mbed_official	87:085cde657901	2998	* @param htim: TIM handle
mbed_official	87:085cde657901	2999	* @param sConfig: TIM PWM configuration structure
mbed_official	87:085cde657901	3000	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	3001	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3002	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	3003	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	3004	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	3005	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	3006	* @retval HAL status
mbed_official	87:085cde657901	3007	*/
mbed_official	87:085cde657901	3008	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	87:085cde657901	3009	{
mbed_official	87:085cde657901	3010	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3011
mbed_official	87:085cde657901	3012	/* Check the parameters */
mbed_official	87:085cde657901	3013	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	87:085cde657901	3014	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official	87:085cde657901	3015	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official	87:085cde657901	3016	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official	87:085cde657901	3017	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official	87:085cde657901	3018	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official	87:085cde657901	3019
mbed_official	87:085cde657901	3020	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3021
mbed_official	87:085cde657901	3022	switch (Channel)
mbed_official	87:085cde657901	3023	{
mbed_official	87:085cde657901	3024	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	3025	{
mbed_official	87:085cde657901	3026	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3027	/* Configure the Channel 1 in PWM mode */
mbed_official	87:085cde657901	3028	TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	3029
mbed_official	87:085cde657901	3030	/* Set the Preload enable bit for channel1 */
mbed_official	87:085cde657901	3031	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
mbed_official	87:085cde657901	3032
mbed_official	87:085cde657901	3033	/* Configure the Output Fast mode */
mbed_official	87:085cde657901	3034	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
mbed_official	87:085cde657901	3035	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
mbed_official	87:085cde657901	3036	}
mbed_official	87:085cde657901	3037	break;
mbed_official	87:085cde657901	3038
mbed_official	87:085cde657901	3039	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	3040	{
mbed_official	87:085cde657901	3041	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3042	/* Configure the Channel 2 in PWM mode */
mbed_official	87:085cde657901	3043	TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	3044
mbed_official	87:085cde657901	3045	/* Set the Preload enable bit for channel2 */
mbed_official	87:085cde657901	3046	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
mbed_official	87:085cde657901	3047
mbed_official	87:085cde657901	3048	/* Configure the Output Fast mode */
mbed_official	87:085cde657901	3049	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
mbed_official	87:085cde657901	3050	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
mbed_official	87:085cde657901	3051	}
mbed_official	87:085cde657901	3052	break;
mbed_official	87:085cde657901	3053
mbed_official	87:085cde657901	3054	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	3055	{
mbed_official	87:085cde657901	3056	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3057	/* Configure the Channel 3 in PWM mode */
mbed_official	87:085cde657901	3058	TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	3059
mbed_official	87:085cde657901	3060	/* Set the Preload enable bit for channel3 */
mbed_official	87:085cde657901	3061	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
mbed_official	87:085cde657901	3062
mbed_official	87:085cde657901	3063	/* Configure the Output Fast mode */
mbed_official	87:085cde657901	3064	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
mbed_official	87:085cde657901	3065	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
mbed_official	87:085cde657901	3066	}
mbed_official	87:085cde657901	3067	break;
mbed_official	87:085cde657901	3068
mbed_official	87:085cde657901	3069	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	3070	{
mbed_official	87:085cde657901	3071	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3072	/* Configure the Channel 4 in PWM mode */
mbed_official	87:085cde657901	3073	TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	3074
mbed_official	87:085cde657901	3075	/* Set the Preload enable bit for channel4 */
mbed_official	87:085cde657901	3076	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
mbed_official	87:085cde657901	3077
mbed_official	87:085cde657901	3078	/* Configure the Output Fast mode */
mbed_official	87:085cde657901	3079	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
mbed_official	87:085cde657901	3080	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
mbed_official	87:085cde657901	3081	}
mbed_official	87:085cde657901	3082	break;
mbed_official	87:085cde657901	3083
mbed_official	87:085cde657901	3084	default:
mbed_official	87:085cde657901	3085	break;
mbed_official	87:085cde657901	3086	}
mbed_official	87:085cde657901	3087
mbed_official	87:085cde657901	3088	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3089
mbed_official	87:085cde657901	3090	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3091
mbed_official	87:085cde657901	3092	return HAL_OK;
mbed_official	87:085cde657901	3093	}
mbed_official	87:085cde657901	3094
mbed_official	87:085cde657901	3095	/**
mbed_official	87:085cde657901	3096	* @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official	87:085cde657901	3097	* parameters in the TIM_OnePulse_InitTypeDef.
mbed_official	87:085cde657901	3098	* @param htim: TIM One Pulse handle
mbed_official	87:085cde657901	3099	* @param sConfig: TIM One Pulse configuration structure
mbed_official	87:085cde657901	3100	* @param OutputChannel : TIM Channels to be enabled
mbed_official	87:085cde657901	3101	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3102	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	3103	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	3104	* @param InputChannel : TIM Channels to be enabled
mbed_official	87:085cde657901	3105	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3106	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	3107	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	3108	* @retval HAL status
mbed_official	87:085cde657901	3109	*/
mbed_official	87:085cde657901	3110	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official	87:085cde657901	3111	{
mbed_official	87:085cde657901	3112	TIM_OC_InitTypeDef temp1;
mbed_official	87:085cde657901	3113
mbed_official	87:085cde657901	3114	/* Check the parameters */
mbed_official	87:085cde657901	3115	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official	87:085cde657901	3116	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official	87:085cde657901	3117
mbed_official	87:085cde657901	3118	if(OutputChannel != InputChannel)
mbed_official	87:085cde657901	3119	{
mbed_official	87:085cde657901	3120	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3121
mbed_official	87:085cde657901	3122	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3123
mbed_official	87:085cde657901	3124	/* Extract the Ouput compare configuration from sConfig structure */
mbed_official	87:085cde657901	3125	temp1.OCMode = sConfig->OCMode;
mbed_official	87:085cde657901	3126	temp1.Pulse = sConfig->Pulse;
mbed_official	87:085cde657901	3127	temp1.OCPolarity = sConfig->OCPolarity;
mbed_official	87:085cde657901	3128	temp1.OCNPolarity = sConfig->OCNPolarity;
mbed_official	87:085cde657901	3129	temp1.OCIdleState = sConfig->OCIdleState;
mbed_official	87:085cde657901	3130	temp1.OCNIdleState = sConfig->OCNIdleState;
mbed_official	87:085cde657901	3131
mbed_official	87:085cde657901	3132	switch (OutputChannel)
mbed_official	87:085cde657901	3133	{
mbed_official	87:085cde657901	3134	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	3135	{
mbed_official	87:085cde657901	3136	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3137
mbed_official	87:085cde657901	3138	TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official	87:085cde657901	3139	}
mbed_official	87:085cde657901	3140	break;
mbed_official	87:085cde657901	3141	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	3142	{
mbed_official	87:085cde657901	3143	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3144
mbed_official	87:085cde657901	3145	TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official	87:085cde657901	3146	}
mbed_official	87:085cde657901	3147	break;
mbed_official	87:085cde657901	3148	default:
mbed_official	87:085cde657901	3149	break;
mbed_official	87:085cde657901	3150	}
mbed_official	87:085cde657901	3151	switch (InputChannel)
mbed_official	87:085cde657901	3152	{
mbed_official	87:085cde657901	3153	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	3154	{
mbed_official	87:085cde657901	3155	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3156
mbed_official	87:085cde657901	3157	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official	87:085cde657901	3158	sConfig->ICSelection, sConfig->ICFilter);
mbed_official	87:085cde657901	3159
mbed_official	87:085cde657901	3160	/* Reset the IC1PSC Bits */
mbed_official	87:085cde657901	3161	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official	87:085cde657901	3162
mbed_official	87:085cde657901	3163	/* Select the Trigger source */
mbed_official	87:085cde657901	3164	htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official	87:085cde657901	3165	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
mbed_official	87:085cde657901	3166
mbed_official	87:085cde657901	3167	/* Select the Slave Mode */
mbed_official	87:085cde657901	3168	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	3169	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
mbed_official	87:085cde657901	3170	}
mbed_official	87:085cde657901	3171	break;
mbed_official	87:085cde657901	3172	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	3173	{
mbed_official	87:085cde657901	3174	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3175
mbed_official	87:085cde657901	3176	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official	87:085cde657901	3177	sConfig->ICSelection, sConfig->ICFilter);
mbed_official	87:085cde657901	3178
mbed_official	87:085cde657901	3179	/* Reset the IC2PSC Bits */
mbed_official	87:085cde657901	3180	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official	87:085cde657901	3181
mbed_official	87:085cde657901	3182	/* Select the Trigger source */
mbed_official	87:085cde657901	3183	htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official	87:085cde657901	3184	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
mbed_official	87:085cde657901	3185
mbed_official	87:085cde657901	3186	/* Select the Slave Mode */
mbed_official	87:085cde657901	3187	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	3188	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
mbed_official	87:085cde657901	3189	}
mbed_official	87:085cde657901	3190	break;
mbed_official	87:085cde657901	3191
mbed_official	87:085cde657901	3192	default:
mbed_official	87:085cde657901	3193	break;
mbed_official	87:085cde657901	3194	}
mbed_official	87:085cde657901	3195
mbed_official	87:085cde657901	3196	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3197
mbed_official	87:085cde657901	3198	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3199
mbed_official	87:085cde657901	3200	return HAL_OK;
mbed_official	87:085cde657901	3201	}
mbed_official	87:085cde657901	3202	else
mbed_official	87:085cde657901	3203	{
mbed_official	87:085cde657901	3204	return HAL_ERROR;
mbed_official	87:085cde657901	3205	}
mbed_official	87:085cde657901	3206	}
mbed_official	87:085cde657901	3207
mbed_official	87:085cde657901	3208	/**
mbed_official	87:085cde657901	3209	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official	87:085cde657901	3210	* @param htim: TIM handle
mbed_official	87:085cde657901	3211	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
mbed_official	87:085cde657901	3212	* This parameters can be on of the following values:
mbed_official	87:085cde657901	3213	* @arg TIM_DMABase_CR1
mbed_official	87:085cde657901	3214	* @arg TIM_DMABase_CR2
mbed_official	87:085cde657901	3215	* @arg TIM_DMABase_SMCR
mbed_official	87:085cde657901	3216	* @arg TIM_DMABase_DIER
mbed_official	87:085cde657901	3217	* @arg TIM_DMABase_SR
mbed_official	87:085cde657901	3218	* @arg TIM_DMABase_EGR
mbed_official	87:085cde657901	3219	* @arg TIM_DMABase_CCMR1
mbed_official	87:085cde657901	3220	* @arg TIM_DMABase_CCMR2
mbed_official	87:085cde657901	3221	* @arg TIM_DMABase_CCER
mbed_official	87:085cde657901	3222	* @arg TIM_DMABase_CNT
mbed_official	87:085cde657901	3223	* @arg TIM_DMABase_PSC
mbed_official	87:085cde657901	3224	* @arg TIM_DMABase_ARR
mbed_official	87:085cde657901	3225	* @arg TIM_DMABase_RCR
mbed_official	87:085cde657901	3226	* @arg TIM_DMABase_CCR1
mbed_official	87:085cde657901	3227	* @arg TIM_DMABase_CCR2
mbed_official	87:085cde657901	3228	* @arg TIM_DMABase_CCR3
mbed_official	87:085cde657901	3229	* @arg TIM_DMABase_CCR4
mbed_official	87:085cde657901	3230	* @arg TIM_DMABase_BDTR
mbed_official	87:085cde657901	3231	* @arg TIM_DMABase_DCR
mbed_official	87:085cde657901	3232	* @param BurstRequestSrc: TIM DMA Request sources
mbed_official	87:085cde657901	3233	* This parameters can be on of the following values:
mbed_official	87:085cde657901	3234	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official	87:085cde657901	3235	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official	87:085cde657901	3236	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official	87:085cde657901	3237	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official	87:085cde657901	3238	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official	87:085cde657901	3239	* @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official	87:085cde657901	3240	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official	87:085cde657901	3241	* @param BurstBuffer: The Buffer address.
mbed_official	87:085cde657901	3242	* @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official	87:085cde657901	3243	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official	87:085cde657901	3244	* @retval HAL status
mbed_official	87:085cde657901	3245	*/
mbed_official	87:085cde657901	3246	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official	87:085cde657901	3247	uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official	87:085cde657901	3248	{
mbed_official	87:085cde657901	3249	/* Check the parameters */
mbed_official	87:085cde657901	3250	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3251	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official	87:085cde657901	3252	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	87:085cde657901	3253	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official	87:085cde657901	3254
mbed_official	87:085cde657901	3255	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	3256	{
mbed_official	87:085cde657901	3257	return HAL_BUSY;
mbed_official	87:085cde657901	3258	}
mbed_official	87:085cde657901	3259	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	3260	{
mbed_official	87:085cde657901	3261	if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official	87:085cde657901	3262	{
mbed_official	87:085cde657901	3263	return HAL_ERROR;
mbed_official	87:085cde657901	3264	}
mbed_official	87:085cde657901	3265	else
mbed_official	87:085cde657901	3266	{
mbed_official	87:085cde657901	3267	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3268	}
mbed_official	87:085cde657901	3269	}
mbed_official	87:085cde657901	3270	switch(BurstRequestSrc)
mbed_official	87:085cde657901	3271	{
mbed_official	87:085cde657901	3272	case TIM_DMA_UPDATE:
mbed_official	87:085cde657901	3273	{
mbed_official	87:085cde657901	3274	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3275	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	87:085cde657901	3276
mbed_official	87:085cde657901	3277	/* Set the DMA error callback */
mbed_official	87:085cde657901	3278	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3279
mbed_official	87:085cde657901	3280	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3281	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3282	}
mbed_official	87:085cde657901	3283	break;
mbed_official	87:085cde657901	3284	case TIM_DMA_CC1:
mbed_official	87:085cde657901	3285	{
mbed_official	87:085cde657901	3286	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3287	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	3288
mbed_official	87:085cde657901	3289	/* Set the DMA error callback */
mbed_official	87:085cde657901	3290	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3291
mbed_official	87:085cde657901	3292	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3293	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3294	}
mbed_official	87:085cde657901	3295	break;
mbed_official	87:085cde657901	3296	case TIM_DMA_CC2:
mbed_official	87:085cde657901	3297	{
mbed_official	87:085cde657901	3298	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3299	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	3300
mbed_official	87:085cde657901	3301	/* Set the DMA error callback */
mbed_official	87:085cde657901	3302	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3303
mbed_official	87:085cde657901	3304	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3305	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3306	}
mbed_official	87:085cde657901	3307	break;
mbed_official	87:085cde657901	3308	case TIM_DMA_CC3:
mbed_official	87:085cde657901	3309	{
mbed_official	87:085cde657901	3310	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3311	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	3312
mbed_official	87:085cde657901	3313	/* Set the DMA error callback */
mbed_official	87:085cde657901	3314	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3315
mbed_official	87:085cde657901	3316	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3317	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3318	}
mbed_official	87:085cde657901	3319	break;
mbed_official	87:085cde657901	3320	case TIM_DMA_CC4:
mbed_official	87:085cde657901	3321	{
mbed_official	87:085cde657901	3322	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3323	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	3324
mbed_official	87:085cde657901	3325	/* Set the DMA error callback */
mbed_official	87:085cde657901	3326	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3327
mbed_official	87:085cde657901	3328	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3329	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3330	}
mbed_official	87:085cde657901	3331	break;
mbed_official	87:085cde657901	3332	case TIM_DMA_COM:
mbed_official	87:085cde657901	3333	{
mbed_official	87:085cde657901	3334	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3335	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official	87:085cde657901	3336
mbed_official	87:085cde657901	3337	/* Set the DMA error callback */
mbed_official	87:085cde657901	3338	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3339
mbed_official	87:085cde657901	3340	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3341	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3342	}
mbed_official	87:085cde657901	3343	break;
mbed_official	87:085cde657901	3344	case TIM_DMA_TRIGGER:
mbed_official	87:085cde657901	3345	{
mbed_official	87:085cde657901	3346	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3347	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official	87:085cde657901	3348
mbed_official	87:085cde657901	3349	/* Set the DMA error callback */
mbed_official	87:085cde657901	3350	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3351
mbed_official	87:085cde657901	3352	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3353	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3354	}
mbed_official	87:085cde657901	3355	break;
mbed_official	87:085cde657901	3356	default:
mbed_official	87:085cde657901	3357	break;
mbed_official	87:085cde657901	3358	}
mbed_official	87:085cde657901	3359	/* configure the DMA Burst Mode */
mbed_official	87:085cde657901	3360	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
mbed_official	87:085cde657901	3361
mbed_official	87:085cde657901	3362	/* Enable the TIM DMA Request */
mbed_official	87:085cde657901	3363	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official	87:085cde657901	3364
mbed_official	87:085cde657901	3365	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3366
mbed_official	87:085cde657901	3367	/* Return function status */
mbed_official	87:085cde657901	3368	return HAL_OK;
mbed_official	87:085cde657901	3369	}
mbed_official	87:085cde657901	3370
mbed_official	87:085cde657901	3371	/**
mbed_official	87:085cde657901	3372	* @brief Stops the TIM DMA Burst mode
mbed_official	87:085cde657901	3373	* @param htim: TIM handle
mbed_official	87:085cde657901	3374	* @param BurstRequestSrc: TIM DMA Request sources to disable
mbed_official	87:085cde657901	3375	* @retval HAL status
mbed_official	87:085cde657901	3376	*/
mbed_official	87:085cde657901	3377	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official	87:085cde657901	3378	{
mbed_official	87:085cde657901	3379	/* Check the parameters */
mbed_official	87:085cde657901	3380	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	87:085cde657901	3381
mbed_official	87:085cde657901	3382	/* Disable the TIM Update DMA request */
mbed_official	87:085cde657901	3383	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official	87:085cde657901	3384
mbed_official	87:085cde657901	3385	/* Return function status */
mbed_official	87:085cde657901	3386	return HAL_OK;
mbed_official	87:085cde657901	3387	}
mbed_official	87:085cde657901	3388
mbed_official	87:085cde657901	3389	/**
mbed_official	87:085cde657901	3390	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official	87:085cde657901	3391	* @param htim: TIM handle
mbed_official	87:085cde657901	3392	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
mbed_official	87:085cde657901	3393	* This parameters can be on of the following values:
mbed_official	87:085cde657901	3394	* @arg TIM_DMABase_CR1
mbed_official	87:085cde657901	3395	* @arg TIM_DMABase_CR2
mbed_official	87:085cde657901	3396	* @arg TIM_DMABase_SMCR
mbed_official	87:085cde657901	3397	* @arg TIM_DMABase_DIER
mbed_official	87:085cde657901	3398	* @arg TIM_DMABase_SR
mbed_official	87:085cde657901	3399	* @arg TIM_DMABase_EGR
mbed_official	87:085cde657901	3400	* @arg TIM_DMABase_CCMR1
mbed_official	87:085cde657901	3401	* @arg TIM_DMABase_CCMR2
mbed_official	87:085cde657901	3402	* @arg TIM_DMABase_CCER
mbed_official	87:085cde657901	3403	* @arg TIM_DMABase_CNT
mbed_official	87:085cde657901	3404	* @arg TIM_DMABase_PSC
mbed_official	87:085cde657901	3405	* @arg TIM_DMABase_ARR
mbed_official	87:085cde657901	3406	* @arg TIM_DMABase_RCR
mbed_official	87:085cde657901	3407	* @arg TIM_DMABase_CCR1
mbed_official	87:085cde657901	3408	* @arg TIM_DMABase_CCR2
mbed_official	87:085cde657901	3409	* @arg TIM_DMABase_CCR3
mbed_official	87:085cde657901	3410	* @arg TIM_DMABase_CCR4
mbed_official	87:085cde657901	3411	* @arg TIM_DMABase_BDTR
mbed_official	87:085cde657901	3412	* @arg TIM_DMABase_DCR
mbed_official	87:085cde657901	3413	* @param BurstRequestSrc: TIM DMA Request sources
mbed_official	87:085cde657901	3414	* This parameters can be on of the following values:
mbed_official	87:085cde657901	3415	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official	87:085cde657901	3416	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official	87:085cde657901	3417	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official	87:085cde657901	3418	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official	87:085cde657901	3419	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official	87:085cde657901	3420	* @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official	87:085cde657901	3421	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official	87:085cde657901	3422	* @param BurstBuffer: The Buffer address.
mbed_official	87:085cde657901	3423	* @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official	87:085cde657901	3424	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official	87:085cde657901	3425	* @retval HAL status
mbed_official	87:085cde657901	3426	*/
mbed_official	87:085cde657901	3427	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official	87:085cde657901	3428	uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official	87:085cde657901	3429	{
mbed_official	87:085cde657901	3430	/* Check the parameters */
mbed_official	87:085cde657901	3431	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3432	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official	87:085cde657901	3433	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	87:085cde657901	3434	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official	87:085cde657901	3435
mbed_official	87:085cde657901	3436	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	3437	{
mbed_official	87:085cde657901	3438	return HAL_BUSY;
mbed_official	87:085cde657901	3439	}
mbed_official	87:085cde657901	3440	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	3441	{
mbed_official	87:085cde657901	3442	if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official	87:085cde657901	3443	{
mbed_official	87:085cde657901	3444	return HAL_ERROR;
mbed_official	87:085cde657901	3445	}
mbed_official	87:085cde657901	3446	else
mbed_official	87:085cde657901	3447	{
mbed_official	87:085cde657901	3448	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3449	}
mbed_official	87:085cde657901	3450	}
mbed_official	87:085cde657901	3451	switch(BurstRequestSrc)
mbed_official	87:085cde657901	3452	{
mbed_official	87:085cde657901	3453	case TIM_DMA_UPDATE:
mbed_official	87:085cde657901	3454	{
mbed_official	87:085cde657901	3455	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3456	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	87:085cde657901	3457
mbed_official	87:085cde657901	3458	/* Set the DMA error callback */
mbed_official	87:085cde657901	3459	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3460
mbed_official	87:085cde657901	3461	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3462	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3463	}
mbed_official	87:085cde657901	3464	break;
mbed_official	87:085cde657901	3465	case TIM_DMA_CC1:
mbed_official	87:085cde657901	3466	{
mbed_official	87:085cde657901	3467	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3468	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	3469
mbed_official	87:085cde657901	3470	/* Set the DMA error callback */
mbed_official	87:085cde657901	3471	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3472
mbed_official	87:085cde657901	3473	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3474	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3475	}
mbed_official	87:085cde657901	3476	break;
mbed_official	87:085cde657901	3477	case TIM_DMA_CC2:
mbed_official	87:085cde657901	3478	{
mbed_official	87:085cde657901	3479	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3480	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	3481
mbed_official	87:085cde657901	3482	/* Set the DMA error callback */
mbed_official	87:085cde657901	3483	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3484
mbed_official	87:085cde657901	3485	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3486	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3487	}
mbed_official	87:085cde657901	3488	break;
mbed_official	87:085cde657901	3489	case TIM_DMA_CC3:
mbed_official	87:085cde657901	3490	{
mbed_official	87:085cde657901	3491	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3492	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	3493
mbed_official	87:085cde657901	3494	/* Set the DMA error callback */
mbed_official	87:085cde657901	3495	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3496
mbed_official	87:085cde657901	3497	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3498	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3499	}
mbed_official	87:085cde657901	3500	break;
mbed_official	87:085cde657901	3501	case TIM_DMA_CC4:
mbed_official	87:085cde657901	3502	{
mbed_official	87:085cde657901	3503	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3504	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	3505
mbed_official	87:085cde657901	3506	/* Set the DMA error callback */
mbed_official	87:085cde657901	3507	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3508
mbed_official	87:085cde657901	3509	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3510	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3511	}
mbed_official	87:085cde657901	3512	break;
mbed_official	87:085cde657901	3513	case TIM_DMA_COM:
mbed_official	87:085cde657901	3514	{
mbed_official	87:085cde657901	3515	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3516	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official	87:085cde657901	3517
mbed_official	87:085cde657901	3518	/* Set the DMA error callback */
mbed_official	87:085cde657901	3519	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3520
mbed_official	87:085cde657901	3521	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3522	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3523	}
mbed_official	87:085cde657901	3524	break;
mbed_official	87:085cde657901	3525	case TIM_DMA_TRIGGER:
mbed_official	87:085cde657901	3526	{
mbed_official	87:085cde657901	3527	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3528	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official	87:085cde657901	3529
mbed_official	87:085cde657901	3530	/* Set the DMA error callback */
mbed_official	87:085cde657901	3531	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3532
mbed_official	87:085cde657901	3533	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3534	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3535	}
mbed_official	87:085cde657901	3536	break;
mbed_official	87:085cde657901	3537	default:
mbed_official	87:085cde657901	3538	break;
mbed_official	87:085cde657901	3539	}
mbed_official	87:085cde657901	3540
mbed_official	87:085cde657901	3541	/* configure the DMA Burst Mode */
mbed_official	87:085cde657901	3542	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
mbed_official	87:085cde657901	3543
mbed_official	87:085cde657901	3544	/* Enable the TIM DMA Request */
mbed_official	87:085cde657901	3545	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official	87:085cde657901	3546
mbed_official	87:085cde657901	3547	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3548
mbed_official	87:085cde657901	3549	/* Return function status */
mbed_official	87:085cde657901	3550	return HAL_OK;
mbed_official	87:085cde657901	3551	}
mbed_official	87:085cde657901	3552
mbed_official	87:085cde657901	3553	/**
mbed_official	87:085cde657901	3554	* @brief Stop the DMA burst reading
mbed_official	87:085cde657901	3555	* @param htim: TIM handle
mbed_official	87:085cde657901	3556	* @param BurstRequestSrc: TIM DMA Request sources to disable.
mbed_official	87:085cde657901	3557	* @retval HAL status
mbed_official	87:085cde657901	3558	*/
mbed_official	87:085cde657901	3559	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official	87:085cde657901	3560	{
mbed_official	87:085cde657901	3561	/* Check the parameters */
mbed_official	87:085cde657901	3562	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	87:085cde657901	3563
mbed_official	87:085cde657901	3564	/* Disable the TIM Update DMA request */
mbed_official	87:085cde657901	3565	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official	87:085cde657901	3566
mbed_official	87:085cde657901	3567	/* Return function status */
mbed_official	87:085cde657901	3568	return HAL_OK;
mbed_official	87:085cde657901	3569	}
mbed_official	87:085cde657901	3570
mbed_official	87:085cde657901	3571	/**
mbed_official	87:085cde657901	3572	* @brief Generate a software event
mbed_official	87:085cde657901	3573	* @param htim: TIM handle
mbed_official	87:085cde657901	3574	* @param EventSource: specifies the event source.
mbed_official	87:085cde657901	3575	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3576	* @arg TIM_EventSource_Update: Timer update Event source
mbed_official	87:085cde657901	3577	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
mbed_official	87:085cde657901	3578	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official	87:085cde657901	3579	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official	87:085cde657901	3580	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official	87:085cde657901	3581	* @arg TIM_EventSource_COM: Timer COM event source
mbed_official	87:085cde657901	3582	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
mbed_official	87:085cde657901	3583	* @arg TIM_EventSource_Break: Timer Break event source
mbed_official	87:085cde657901	3584	* @note TIM6 and TIM7 can only generate an update event.
mbed_official	87:085cde657901	3585	* @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
mbed_official	87:085cde657901	3586	* @retval HAL status
mbed_official	87:085cde657901	3587	*/
mbed_official	87:085cde657901	3588
mbed_official	87:085cde657901	3589	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official	87:085cde657901	3590	{
mbed_official	87:085cde657901	3591	/* Check the parameters */
mbed_official	87:085cde657901	3592	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3593	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official	87:085cde657901	3594
mbed_official	87:085cde657901	3595	/* Process Locked */
mbed_official	87:085cde657901	3596	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3597
mbed_official	87:085cde657901	3598	/* Change the TIM state */
mbed_official	87:085cde657901	3599	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3600
mbed_official	87:085cde657901	3601	/* Set the event sources */
mbed_official	87:085cde657901	3602	htim->Instance->EGR = EventSource;
mbed_official	87:085cde657901	3603
mbed_official	87:085cde657901	3604	/* Change the TIM state */
mbed_official	87:085cde657901	3605	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3606
mbed_official	87:085cde657901	3607	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3608
mbed_official	87:085cde657901	3609	/* Return function status */
mbed_official	87:085cde657901	3610	return HAL_OK;
mbed_official	87:085cde657901	3611	}
mbed_official	87:085cde657901	3612
mbed_official	87:085cde657901	3613	/**
mbed_official	87:085cde657901	3614	* @brief Configures the OCRef clear feature
mbed_official	87:085cde657901	3615	* @param htim: TIM handle
mbed_official	87:085cde657901	3616	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official	87:085cde657901	3617	* contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official	87:085cde657901	3618	* @param Channel: specifies the TIM Channel
mbed_official	87:085cde657901	3619	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3620	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	87:085cde657901	3621	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	87:085cde657901	3622	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	87:085cde657901	3623	* @arg TIM_Channel_4: TIM Channel 4
mbed_official	87:085cde657901	3624	* @retval HAL status
mbed_official	87:085cde657901	3625	*/
mbed_official	87:085cde657901	3626	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
mbed_official	87:085cde657901	3627	{
mbed_official	87:085cde657901	3628	/* Check the parameters */
mbed_official	87:085cde657901	3629	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3630	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	87:085cde657901	3631	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official	87:085cde657901	3632	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official	87:085cde657901	3633	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official	87:085cde657901	3634	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official	87:085cde657901	3635
mbed_official	87:085cde657901	3636	/* Process Locked */
mbed_official	87:085cde657901	3637	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3638
mbed_official	87:085cde657901	3639	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3640
mbed_official	87:085cde657901	3641	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
mbed_official	87:085cde657901	3642	{
mbed_official	87:085cde657901	3643	TIM_ETR_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3644	sClearInputConfig->ClearInputPrescaler,
mbed_official	87:085cde657901	3645	sClearInputConfig->ClearInputPolarity,
mbed_official	87:085cde657901	3646	sClearInputConfig->ClearInputFilter);
mbed_official	87:085cde657901	3647	}
mbed_official	87:085cde657901	3648
mbed_official	87:085cde657901	3649	switch (Channel)
mbed_official	87:085cde657901	3650	{
mbed_official	87:085cde657901	3651	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	3652	{
mbed_official	87:085cde657901	3653	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	87:085cde657901	3654	{
mbed_official	87:085cde657901	3655	/* Enable the Ocref clear feature for Channel 1 */
mbed_official	87:085cde657901	3656	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
mbed_official	87:085cde657901	3657	}
mbed_official	87:085cde657901	3658	else
mbed_official	87:085cde657901	3659	{
mbed_official	87:085cde657901	3660	/* Disable the Ocref clear feature for Channel 1 */
mbed_official	87:085cde657901	3661	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
mbed_official	87:085cde657901	3662	}
mbed_official	87:085cde657901	3663	}
mbed_official	87:085cde657901	3664	break;
mbed_official	87:085cde657901	3665	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	3666	{
mbed_official	87:085cde657901	3667	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3668	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	87:085cde657901	3669	{
mbed_official	87:085cde657901	3670	/* Enable the Ocref clear feature for Channel 2 */
mbed_official	87:085cde657901	3671	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
mbed_official	87:085cde657901	3672	}
mbed_official	87:085cde657901	3673	else
mbed_official	87:085cde657901	3674	{
mbed_official	87:085cde657901	3675	/* Disable the Ocref clear feature for Channel 2 */
mbed_official	87:085cde657901	3676	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
mbed_official	87:085cde657901	3677	}
mbed_official	87:085cde657901	3678	}
mbed_official	87:085cde657901	3679	break;
mbed_official	87:085cde657901	3680	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	3681	{
mbed_official	87:085cde657901	3682	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3683	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	87:085cde657901	3684	{
mbed_official	87:085cde657901	3685	/* Enable the Ocref clear feature for Channel 3 */
mbed_official	87:085cde657901	3686	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
mbed_official	87:085cde657901	3687	}
mbed_official	87:085cde657901	3688	else
mbed_official	87:085cde657901	3689	{
mbed_official	87:085cde657901	3690	/* Disable the Ocref clear feature for Channel 3 */
mbed_official	87:085cde657901	3691	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
mbed_official	87:085cde657901	3692	}
mbed_official	87:085cde657901	3693	}
mbed_official	87:085cde657901	3694	break;
mbed_official	87:085cde657901	3695	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	3696	{
mbed_official	87:085cde657901	3697	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3698	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	87:085cde657901	3699	{
mbed_official	87:085cde657901	3700	/* Enable the Ocref clear feature for Channel 4 */
mbed_official	87:085cde657901	3701	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
mbed_official	87:085cde657901	3702	}
mbed_official	87:085cde657901	3703	else
mbed_official	87:085cde657901	3704	{
mbed_official	87:085cde657901	3705	/* Disable the Ocref clear feature for Channel 4 */
mbed_official	87:085cde657901	3706	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
mbed_official	87:085cde657901	3707	}
mbed_official	87:085cde657901	3708	}
mbed_official	87:085cde657901	3709	break;
mbed_official	87:085cde657901	3710	default:
mbed_official	87:085cde657901	3711	break;
mbed_official	87:085cde657901	3712	}
mbed_official	87:085cde657901	3713
mbed_official	87:085cde657901	3714	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3715
mbed_official	87:085cde657901	3716	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3717
mbed_official	87:085cde657901	3718	return HAL_OK;
mbed_official	87:085cde657901	3719	}
mbed_official	87:085cde657901	3720
mbed_official	87:085cde657901	3721	/**
mbed_official	87:085cde657901	3722	* @brief Configures the clock source to be used
mbed_official	87:085cde657901	3723	* @param htim: TIM handle
mbed_official	87:085cde657901	3724	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
mbed_official	87:085cde657901	3725	* contains the clock source information for the TIM peripheral.
mbed_official	87:085cde657901	3726	* @retval HAL status
mbed_official	87:085cde657901	3727	*/
mbed_official	87:085cde657901	3728	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
mbed_official	87:085cde657901	3729	{
mbed_official	87:085cde657901	3730	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	3731
mbed_official	87:085cde657901	3732	/* Process Locked */
mbed_official	87:085cde657901	3733	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3734
mbed_official	87:085cde657901	3735	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3736
mbed_official	87:085cde657901	3737	/* Check the parameters */
mbed_official	87:085cde657901	3738	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official	87:085cde657901	3739	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	87:085cde657901	3740	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	87:085cde657901	3741	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	87:085cde657901	3742
mbed_official	87:085cde657901	3743	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official	87:085cde657901	3744	tmpsmcr = htim->Instance->SMCR;
mbed_official	87:085cde657901	3745	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
mbed_official	87:085cde657901	3746	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
mbed_official	87:085cde657901	3747	htim->Instance->SMCR = tmpsmcr;
mbed_official	87:085cde657901	3748
mbed_official	87:085cde657901	3749	switch (sClockSourceConfig->ClockSource)
mbed_official	87:085cde657901	3750	{
mbed_official	87:085cde657901	3751	case TIM_CLOCKSOURCE_INTERNAL:
mbed_official	87:085cde657901	3752	{
mbed_official	87:085cde657901	3753	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3754	/* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official	87:085cde657901	3755	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	3756	}
mbed_official	87:085cde657901	3757	break;
mbed_official	87:085cde657901	3758
mbed_official	87:085cde657901	3759	case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official	87:085cde657901	3760	{
mbed_official	87:085cde657901	3761	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3762	/* Configure the ETR Clock source */
mbed_official	87:085cde657901	3763	TIM_ETR_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3764	sClockSourceConfig->ClockPrescaler,
mbed_official	87:085cde657901	3765	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3766	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3767	/* Get the TIMx SMCR register value */
mbed_official	87:085cde657901	3768	tmpsmcr = htim->Instance->SMCR;
mbed_official	87:085cde657901	3769	/* Reset the SMS and TS Bits */
mbed_official	87:085cde657901	3770	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
mbed_official	87:085cde657901	3771	/* Select the External clock mode1 and the ETRF trigger */
mbed_official	87:085cde657901	3772	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
mbed_official	87:085cde657901	3773	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	3774	htim->Instance->SMCR = tmpsmcr;
mbed_official	87:085cde657901	3775	}
mbed_official	87:085cde657901	3776	break;
mbed_official	87:085cde657901	3777
mbed_official	87:085cde657901	3778	case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official	87:085cde657901	3779	{
mbed_official	87:085cde657901	3780	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3781	/* Configure the ETR Clock source */
mbed_official	87:085cde657901	3782	TIM_ETR_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3783	sClockSourceConfig->ClockPrescaler,
mbed_official	87:085cde657901	3784	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3785	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3786	/* Enable the External clock mode2 */
mbed_official	87:085cde657901	3787	htim->Instance->SMCR \|= TIM_SMCR_ECE;
mbed_official	87:085cde657901	3788	}
mbed_official	87:085cde657901	3789	break;
mbed_official	87:085cde657901	3790
mbed_official	87:085cde657901	3791	case TIM_CLOCKSOURCE_TI1:
mbed_official	87:085cde657901	3792	{
mbed_official	87:085cde657901	3793	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3794	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	3795	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3796	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3797	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official	87:085cde657901	3798	}
mbed_official	87:085cde657901	3799	break;
mbed_official	87:085cde657901	3800	case TIM_CLOCKSOURCE_TI2:
mbed_official	87:085cde657901	3801	{
mbed_official	87:085cde657901	3802	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3803	TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	3804	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3805	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3806	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official	87:085cde657901	3807	}
mbed_official	87:085cde657901	3808	break;
mbed_official	87:085cde657901	3809	case TIM_CLOCKSOURCE_TI1ED:
mbed_official	87:085cde657901	3810	{
mbed_official	87:085cde657901	3811	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3812	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	3813	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3814	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3815	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official	87:085cde657901	3816	}
mbed_official	87:085cde657901	3817	break;
mbed_official	87:085cde657901	3818	case TIM_CLOCKSOURCE_ITR0:
mbed_official	87:085cde657901	3819	{
mbed_official	87:085cde657901	3820	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3821	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official	87:085cde657901	3822	}
mbed_official	87:085cde657901	3823	break;
mbed_official	87:085cde657901	3824	case TIM_CLOCKSOURCE_ITR1:
mbed_official	87:085cde657901	3825	{
mbed_official	87:085cde657901	3826	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3827	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official	87:085cde657901	3828	}
mbed_official	87:085cde657901	3829	break;
mbed_official	87:085cde657901	3830	case TIM_CLOCKSOURCE_ITR2:
mbed_official	87:085cde657901	3831	{
mbed_official	87:085cde657901	3832	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3833	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official	87:085cde657901	3834	}
mbed_official	87:085cde657901	3835	break;
mbed_official	87:085cde657901	3836	case TIM_CLOCKSOURCE_ITR3:
mbed_official	87:085cde657901	3837	{
mbed_official	87:085cde657901	3838	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3839	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official	87:085cde657901	3840	}
mbed_official	87:085cde657901	3841	break;
mbed_official	87:085cde657901	3842
mbed_official	87:085cde657901	3843	default:
mbed_official	87:085cde657901	3844	break;
mbed_official	87:085cde657901	3845	}
mbed_official	87:085cde657901	3846	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3847
mbed_official	87:085cde657901	3848	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3849
mbed_official	87:085cde657901	3850	return HAL_OK;
mbed_official	87:085cde657901	3851	}
mbed_official	87:085cde657901	3852
mbed_official	87:085cde657901	3853	/**
mbed_official	87:085cde657901	3854	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official	87:085cde657901	3855	* or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official	87:085cde657901	3856	* @param htim: TIM handle.
mbed_official	87:085cde657901	3857	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
mbed_official	87:085cde657901	3858	* output of a XOR gate.
mbed_official	87:085cde657901	3859	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3860	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official	87:085cde657901	3861	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official	87:085cde657901	3862	* pins are connected to the TI1 input (XOR combination)
mbed_official	87:085cde657901	3863	* @retval HAL status
mbed_official	87:085cde657901	3864	*/
mbed_official	87:085cde657901	3865	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official	87:085cde657901	3866	{
mbed_official	87:085cde657901	3867	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	3868
mbed_official	87:085cde657901	3869	/* Check the parameters */
mbed_official	87:085cde657901	3870	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3871	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official	87:085cde657901	3872
mbed_official	87:085cde657901	3873	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	3874	tmpcr2 = htim->Instance->CR2;
mbed_official	87:085cde657901	3875
mbed_official	87:085cde657901	3876	/* Reset the TI1 selection */
mbed_official	87:085cde657901	3877	tmpcr2 &= ~TIM_CR2_TI1S;
mbed_official	87:085cde657901	3878
mbed_official	87:085cde657901	3879	/* Set the the TI1 selection */
mbed_official	87:085cde657901	3880	tmpcr2 \|= TI1_Selection;
mbed_official	87:085cde657901	3881
mbed_official	87:085cde657901	3882	/* Write to TIMxCR2 */
mbed_official	87:085cde657901	3883	htim->Instance->CR2 = tmpcr2;
mbed_official	87:085cde657901	3884
mbed_official	87:085cde657901	3885	return HAL_OK;
mbed_official	87:085cde657901	3886	}
mbed_official	87:085cde657901	3887
mbed_official	87:085cde657901	3888	/**
mbed_official	87:085cde657901	3889	* @brief Configures the TIM in Slave mode
mbed_official	87:085cde657901	3890	* @param htim: TIM handle.
mbed_official	87:085cde657901	3891	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official	87:085cde657901	3892	* contains the selected trigger (internal trigger input, filtered
mbed_official	87:085cde657901	3893	* timer input or external trigger input) and the ) and the Slave
mbed_official	87:085cde657901	3894	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official	87:085cde657901	3895	* @retval HAL status
mbed_official	87:085cde657901	3896	*/
mbed_official	87:085cde657901	3897	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
mbed_official	87:085cde657901	3898	{
mbed_official	87:085cde657901	3899	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	3900	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	3901	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	3902
mbed_official	87:085cde657901	3903	/* Check the parameters */
mbed_official	87:085cde657901	3904	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3905	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official	87:085cde657901	3906	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official	87:085cde657901	3907
mbed_official	87:085cde657901	3908	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3909
mbed_official	87:085cde657901	3910	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3911
mbed_official	87:085cde657901	3912	/* Get the TIMx SMCR register value */
mbed_official	87:085cde657901	3913	tmpsmcr = htim->Instance->SMCR;
mbed_official	87:085cde657901	3914
mbed_official	87:085cde657901	3915	/* Reset the Trigger Selection Bits */
mbed_official	87:085cde657901	3916	tmpsmcr &= ~TIM_SMCR_TS;
mbed_official	87:085cde657901	3917	/* Set the Input Trigger source */
mbed_official	87:085cde657901	3918	tmpsmcr \|= sSlaveConfig->InputTrigger;
mbed_official	87:085cde657901	3919
mbed_official	87:085cde657901	3920	/* Reset the slave mode Bits */
mbed_official	87:085cde657901	3921	tmpsmcr &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	3922	/* Set the slave mode */
mbed_official	87:085cde657901	3923	tmpsmcr \|= sSlaveConfig->SlaveMode;
mbed_official	87:085cde657901	3924
mbed_official	87:085cde657901	3925	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	3926	htim->Instance->SMCR = tmpsmcr;
mbed_official	87:085cde657901	3927
mbed_official	87:085cde657901	3928	/* Configure the trigger prescaler, filter, and polarity */
mbed_official	87:085cde657901	3929	switch (sSlaveConfig->InputTrigger)
mbed_official	87:085cde657901	3930	{
mbed_official	87:085cde657901	3931	case TIM_TS_ETRF:
mbed_official	87:085cde657901	3932	{
mbed_official	87:085cde657901	3933	/* Check the parameters */
mbed_official	87:085cde657901	3934	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3935	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official	87:085cde657901	3936	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	87:085cde657901	3937	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	87:085cde657901	3938	/* Configure the ETR Trigger source */
mbed_official	87:085cde657901	3939	TIM_ETR_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3940	sSlaveConfig->TriggerPrescaler,
mbed_official	87:085cde657901	3941	sSlaveConfig->TriggerPolarity,
mbed_official	87:085cde657901	3942	sSlaveConfig->TriggerFilter);
mbed_official	87:085cde657901	3943	}
mbed_official	87:085cde657901	3944	break;
mbed_official	87:085cde657901	3945
mbed_official	87:085cde657901	3946	case TIM_TS_TI1F_ED:
mbed_official	87:085cde657901	3947	{
mbed_official	87:085cde657901	3948	/* Check the parameters */
mbed_official	87:085cde657901	3949	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3950	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	87:085cde657901	3951
mbed_official	87:085cde657901	3952	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	87:085cde657901	3953	tmpccer = htim->Instance->CCER;
mbed_official	87:085cde657901	3954	htim->Instance->CCER &= ~TIM_CCER_CC1E;
mbed_official	87:085cde657901	3955	tmpccmr1 = htim->Instance->CCMR1;
mbed_official	87:085cde657901	3956
mbed_official	87:085cde657901	3957	/* Set the filter */
mbed_official	87:085cde657901	3958	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	87:085cde657901	3959	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official	87:085cde657901	3960
mbed_official	87:085cde657901	3961	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	3962	htim->Instance->CCMR1 = tmpccmr1;
mbed_official	87:085cde657901	3963	htim->Instance->CCER = tmpccer;
mbed_official	87:085cde657901	3964
mbed_official	87:085cde657901	3965	}
mbed_official	87:085cde657901	3966	break;
mbed_official	87:085cde657901	3967
mbed_official	87:085cde657901	3968	case TIM_TS_TI1FP1:
mbed_official	87:085cde657901	3969	{
mbed_official	87:085cde657901	3970	/* Check the parameters */
mbed_official	87:085cde657901	3971	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3972	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	87:085cde657901	3973	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	87:085cde657901	3974
mbed_official	87:085cde657901	3975	/* Configure TI1 Filter and Polarity */
mbed_official	87:085cde657901	3976	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	3977	sSlaveConfig->TriggerPolarity,
mbed_official	87:085cde657901	3978	sSlaveConfig->TriggerFilter);
mbed_official	87:085cde657901	3979	}
mbed_official	87:085cde657901	3980	break;
mbed_official	87:085cde657901	3981
mbed_official	87:085cde657901	3982	case TIM_TS_TI2FP2:
mbed_official	87:085cde657901	3983	{
mbed_official	87:085cde657901	3984	/* Check the parameters */
mbed_official	87:085cde657901	3985	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3986	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	87:085cde657901	3987	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	87:085cde657901	3988
mbed_official	87:085cde657901	3989	/* Configure TI2 Filter and Polarity */
mbed_official	87:085cde657901	3990	TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	3991	sSlaveConfig->TriggerPolarity,
mbed_official	87:085cde657901	3992	sSlaveConfig->TriggerFilter);
mbed_official	87:085cde657901	3993	}
mbed_official	87:085cde657901	3994	break;
mbed_official	87:085cde657901	3995
mbed_official	87:085cde657901	3996	case TIM_TS_ITR0:
mbed_official	87:085cde657901	3997	{
mbed_official	87:085cde657901	3998	/* Check the parameter */
mbed_official	87:085cde657901	3999	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4000	}
mbed_official	87:085cde657901	4001	break;
mbed_official	87:085cde657901	4002
mbed_official	87:085cde657901	4003	case TIM_TS_ITR1:
mbed_official	87:085cde657901	4004	{
mbed_official	87:085cde657901	4005	/* Check the parameter */
mbed_official	87:085cde657901	4006	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4007	}
mbed_official	87:085cde657901	4008	break;
mbed_official	87:085cde657901	4009
mbed_official	87:085cde657901	4010	case TIM_TS_ITR2:
mbed_official	87:085cde657901	4011	{
mbed_official	87:085cde657901	4012	/* Check the parameter */
mbed_official	87:085cde657901	4013	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4014	}
mbed_official	87:085cde657901	4015	break;
mbed_official	87:085cde657901	4016
mbed_official	87:085cde657901	4017	case TIM_TS_ITR3:
mbed_official	87:085cde657901	4018	{
mbed_official	87:085cde657901	4019	/* Check the parameter */
mbed_official	87:085cde657901	4020	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4021	}
mbed_official	87:085cde657901	4022	break;
mbed_official	87:085cde657901	4023
mbed_official	87:085cde657901	4024	default:
mbed_official	87:085cde657901	4025	break;
mbed_official	87:085cde657901	4026	}
mbed_official	87:085cde657901	4027
mbed_official	87:085cde657901	4028	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4029
mbed_official	87:085cde657901	4030	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	4031
mbed_official	87:085cde657901	4032	return HAL_OK;
mbed_official	87:085cde657901	4033	}
mbed_official	87:085cde657901	4034
mbed_official	87:085cde657901	4035	/**
mbed_official	87:085cde657901	4036	* @brief Read the captured value from Capture Compare unit
mbed_official	87:085cde657901	4037	* @param htim: TIM handle.
mbed_official	87:085cde657901	4038	* @param Channel : TIM Channels to be enabled
mbed_official	87:085cde657901	4039	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4040	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	4041	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	4042	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	4043	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	4044	* @retval Captured value
mbed_official	87:085cde657901	4045	*/
mbed_official	87:085cde657901	4046	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	4047	{
mbed_official	87:085cde657901	4048	uint32_t tmpreg = 0;
mbed_official	87:085cde657901	4049
mbed_official	87:085cde657901	4050	__HAL_LOCK(htim);
mbed_official	87:085cde657901	4051
mbed_official	87:085cde657901	4052	switch (Channel)
mbed_official	87:085cde657901	4053	{
mbed_official	87:085cde657901	4054	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	4055	{
mbed_official	87:085cde657901	4056	/* Check the parameters */
mbed_official	87:085cde657901	4057	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4058
mbed_official	87:085cde657901	4059	/* Return the capture 1 value */
mbed_official	87:085cde657901	4060	tmpreg = htim->Instance->CCR1;
mbed_official	87:085cde657901	4061
mbed_official	87:085cde657901	4062	break;
mbed_official	87:085cde657901	4063	}
mbed_official	87:085cde657901	4064	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	4065	{
mbed_official	87:085cde657901	4066	/* Check the parameters */
mbed_official	87:085cde657901	4067	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4068
mbed_official	87:085cde657901	4069	/* Return the capture 2 value */
mbed_official	87:085cde657901	4070	tmpreg = htim->Instance->CCR2;
mbed_official	87:085cde657901	4071
mbed_official	87:085cde657901	4072	break;
mbed_official	87:085cde657901	4073	}
mbed_official	87:085cde657901	4074
mbed_official	87:085cde657901	4075	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	4076	{
mbed_official	87:085cde657901	4077	/* Check the parameters */
mbed_official	87:085cde657901	4078	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4079
mbed_official	87:085cde657901	4080	/* Return the capture 3 value */
mbed_official	87:085cde657901	4081	tmpreg = htim->Instance->CCR3;
mbed_official	87:085cde657901	4082
mbed_official	87:085cde657901	4083	break;
mbed_official	87:085cde657901	4084	}
mbed_official	87:085cde657901	4085
mbed_official	87:085cde657901	4086	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	4087	{
mbed_official	87:085cde657901	4088	/* Check the parameters */
mbed_official	87:085cde657901	4089	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4090
mbed_official	87:085cde657901	4091	/* Return the capture 4 value */
mbed_official	87:085cde657901	4092	tmpreg = htim->Instance->CCR4;
mbed_official	87:085cde657901	4093
mbed_official	87:085cde657901	4094	break;
mbed_official	87:085cde657901	4095	}
mbed_official	87:085cde657901	4096
mbed_official	87:085cde657901	4097	default:
mbed_official	87:085cde657901	4098	break;
mbed_official	87:085cde657901	4099	}
mbed_official	87:085cde657901	4100
mbed_official	87:085cde657901	4101	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	4102	return tmpreg;
mbed_official	87:085cde657901	4103	}
mbed_official	87:085cde657901	4104
mbed_official	87:085cde657901	4105	/**
mbed_official	87:085cde657901	4106	* @}
mbed_official	87:085cde657901	4107	*/
mbed_official	87:085cde657901	4108
mbed_official	87:085cde657901	4109	/** @defgroup TIM_Group9 TIM Callbacks functions
mbed_official	87:085cde657901	4110	* @brief TIM Callbacks functions
mbed_official	87:085cde657901	4111	*
mbed_official	87:085cde657901	4112	@verbatim
mbed_official	87:085cde657901	4113	==============================================================================
mbed_official	87:085cde657901	4114	##### TIM Callbacks functions #####
mbed_official	87:085cde657901	4115	==============================================================================
mbed_official	87:085cde657901	4116	[..]
mbed_official	87:085cde657901	4117	This section provides TIM callback functions:
mbed_official	87:085cde657901	4118	(+) Timer Period elapsed callback
mbed_official	87:085cde657901	4119	(+) Timer Output Compare callback
mbed_official	87:085cde657901	4120	(+) Timer Input capture callback
mbed_official	87:085cde657901	4121	(+) Timer Trigger callback
mbed_official	87:085cde657901	4122	(+) Timer Error callback
mbed_official	87:085cde657901	4123
mbed_official	87:085cde657901	4124	@endverbatim
mbed_official	87:085cde657901	4125	* @{
mbed_official	87:085cde657901	4126	*/
mbed_official	87:085cde657901	4127
mbed_official	87:085cde657901	4128	/**
mbed_official	87:085cde657901	4129	* @brief Period elapsed callback in non blocking mode
mbed_official	87:085cde657901	4130	* @param htim : TIM handle
mbed_official	87:085cde657901	4131	* @retval None
mbed_official	87:085cde657901	4132	*/
mbed_official	87:085cde657901	4133	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4134	{
mbed_official	87:085cde657901	4135	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4136	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official	87:085cde657901	4137	*/
mbed_official	87:085cde657901	4138
mbed_official	87:085cde657901	4139	}
mbed_official	87:085cde657901	4140	/**
mbed_official	87:085cde657901	4141	* @brief Output Compare callback in non blocking mode
mbed_official	87:085cde657901	4142	* @param htim : TIM OC handle
mbed_official	87:085cde657901	4143	* @retval None
mbed_official	87:085cde657901	4144	*/
mbed_official	87:085cde657901	4145	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4146	{
mbed_official	87:085cde657901	4147	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4148	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official	87:085cde657901	4149	*/
mbed_official	87:085cde657901	4150	}
mbed_official	87:085cde657901	4151	/**
mbed_official	87:085cde657901	4152	* @brief Input Capture callback in non blocking mode
mbed_official	87:085cde657901	4153	* @param htim : TIM IC handle
mbed_official	87:085cde657901	4154	* @retval None
mbed_official	87:085cde657901	4155	*/
mbed_official	87:085cde657901	4156	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4157	{
mbed_official	87:085cde657901	4158	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4159	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official	87:085cde657901	4160	*/
mbed_official	87:085cde657901	4161	}
mbed_official	87:085cde657901	4162
mbed_official	87:085cde657901	4163	/**
mbed_official	87:085cde657901	4164	* @brief PWM Pulse finished callback in non blocking mode
mbed_official	87:085cde657901	4165	* @param htim : TIM handle
mbed_official	87:085cde657901	4166	* @retval None
mbed_official	87:085cde657901	4167	*/
mbed_official	87:085cde657901	4168	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4169	{
mbed_official	87:085cde657901	4170	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4171	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official	87:085cde657901	4172	*/
mbed_official	87:085cde657901	4173	}
mbed_official	87:085cde657901	4174
mbed_official	87:085cde657901	4175	/**
mbed_official	87:085cde657901	4176	* @brief Hall Trigger detection callback in non blocking mode
mbed_official	87:085cde657901	4177	* @param htim : TIM handle
mbed_official	87:085cde657901	4178	* @retval None
mbed_official	87:085cde657901	4179	*/
mbed_official	87:085cde657901	4180	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4181	{
mbed_official	87:085cde657901	4182	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4183	the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official	87:085cde657901	4184	*/
mbed_official	87:085cde657901	4185	}
mbed_official	87:085cde657901	4186
mbed_official	87:085cde657901	4187	/**
mbed_official	87:085cde657901	4188	* @brief Timer error callback in non blocking mode
mbed_official	87:085cde657901	4189	* @param htim : TIM handle
mbed_official	87:085cde657901	4190	* @retval None
mbed_official	87:085cde657901	4191	*/
mbed_official	87:085cde657901	4192	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4193	{
mbed_official	87:085cde657901	4194	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4195	the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official	87:085cde657901	4196	*/
mbed_official	87:085cde657901	4197	}
mbed_official	87:085cde657901	4198
mbed_official	87:085cde657901	4199	/**
mbed_official	87:085cde657901	4200	* @}
mbed_official	87:085cde657901	4201	*/
mbed_official	87:085cde657901	4202
mbed_official	87:085cde657901	4203	/** @defgroup TIM_Group10 Peripheral State functions
mbed_official	87:085cde657901	4204	* @brief Peripheral State functions
mbed_official	87:085cde657901	4205	*
mbed_official	87:085cde657901	4206	@verbatim
mbed_official	87:085cde657901	4207	==============================================================================
mbed_official	87:085cde657901	4208	##### Peripheral State functions #####
mbed_official	87:085cde657901	4209	==============================================================================
mbed_official	87:085cde657901	4210	[..]
mbed_official	87:085cde657901	4211	This subsection permit to get in run-time the status of the peripheral
mbed_official	87:085cde657901	4212	and the data flow.
mbed_official	87:085cde657901	4213
mbed_official	87:085cde657901	4214	@endverbatim
mbed_official	87:085cde657901	4215	* @{
mbed_official	87:085cde657901	4216	*/
mbed_official	87:085cde657901	4217
mbed_official	87:085cde657901	4218	/**
mbed_official	87:085cde657901	4219	* @brief Return the TIM Base state
mbed_official	87:085cde657901	4220	* @param htim: TIM Base handle
mbed_official	87:085cde657901	4221	* @retval HAL state
mbed_official	87:085cde657901	4222	*/
mbed_official	87:085cde657901	4223	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4224	{
mbed_official	87:085cde657901	4225	return htim->State;
mbed_official	87:085cde657901	4226	}
mbed_official	87:085cde657901	4227
mbed_official	87:085cde657901	4228	/**
mbed_official	87:085cde657901	4229	* @brief Return the TIM OC state
mbed_official	87:085cde657901	4230	* @param htim: TIM Ouput Compare handle
mbed_official	87:085cde657901	4231	* @retval HAL state
mbed_official	87:085cde657901	4232	*/
mbed_official	87:085cde657901	4233	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4234	{
mbed_official	87:085cde657901	4235	return htim->State;
mbed_official	87:085cde657901	4236	}
mbed_official	87:085cde657901	4237
mbed_official	87:085cde657901	4238	/**
mbed_official	87:085cde657901	4239	* @brief Return the TIM PWM state
mbed_official	87:085cde657901	4240	* @param htim: TIM handle
mbed_official	87:085cde657901	4241	* @retval HAL state
mbed_official	87:085cde657901	4242	*/
mbed_official	87:085cde657901	4243	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4244	{
mbed_official	87:085cde657901	4245	return htim->State;
mbed_official	87:085cde657901	4246	}
mbed_official	87:085cde657901	4247
mbed_official	87:085cde657901	4248	/**
mbed_official	87:085cde657901	4249	* @brief Return the TIM Input Capture state
mbed_official	87:085cde657901	4250	* @param htim: TIM IC handle
mbed_official	87:085cde657901	4251	* @retval HAL state
mbed_official	87:085cde657901	4252	*/
mbed_official	87:085cde657901	4253	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4254	{
mbed_official	87:085cde657901	4255	return htim->State;
mbed_official	87:085cde657901	4256	}
mbed_official	87:085cde657901	4257
mbed_official	87:085cde657901	4258	/**
mbed_official	87:085cde657901	4259	* @brief Return the TIM One Pulse Mode state
mbed_official	87:085cde657901	4260	* @param htim: TIM OPM handle
mbed_official	87:085cde657901	4261	* @retval HAL state
mbed_official	87:085cde657901	4262	*/
mbed_official	87:085cde657901	4263	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4264	{
mbed_official	87:085cde657901	4265	return htim->State;
mbed_official	87:085cde657901	4266	}
mbed_official	87:085cde657901	4267
mbed_official	87:085cde657901	4268	/**
mbed_official	87:085cde657901	4269	* @brief Return the TIM Encoder Mode state
mbed_official	87:085cde657901	4270	* @param htim: TIM Encoder handle
mbed_official	87:085cde657901	4271	* @retval HAL state
mbed_official	87:085cde657901	4272	*/
mbed_official	87:085cde657901	4273	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4274	{
mbed_official	87:085cde657901	4275	return htim->State;
mbed_official	87:085cde657901	4276	}
mbed_official	87:085cde657901	4277
mbed_official	87:085cde657901	4278	/**
mbed_official	87:085cde657901	4279	* @}
mbed_official	87:085cde657901	4280	*/
mbed_official	87:085cde657901	4281
mbed_official	87:085cde657901	4282	/**
mbed_official	87:085cde657901	4283	* @brief TIM DMA error callback
mbed_official	87:085cde657901	4284	* @param hdma : pointer to DMA handle.
mbed_official	87:085cde657901	4285	* @retval None
mbed_official	87:085cde657901	4286	*/
mbed_official	87:085cde657901	4287	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4288	{
mbed_official	87:085cde657901	4289	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4290
mbed_official	87:085cde657901	4291	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4292
mbed_official	87:085cde657901	4293	HAL_TIM_ErrorCallback(htim);
mbed_official	87:085cde657901	4294	}
mbed_official	87:085cde657901	4295
mbed_official	87:085cde657901	4296	/**
mbed_official	87:085cde657901	4297	* @brief TIM DMA Delay Pulse complete callback.
mbed_official	87:085cde657901	4298	* @param hdma : pointer to DMA handle.
mbed_official	87:085cde657901	4299	* @retval None
mbed_official	87:085cde657901	4300	*/
mbed_official	87:085cde657901	4301	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4302	{
mbed_official	87:085cde657901	4303	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4304
mbed_official	87:085cde657901	4305	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4306
mbed_official	87:085cde657901	4307	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	4308	}
mbed_official	87:085cde657901	4309	/**
mbed_official	87:085cde657901	4310	* @brief TIM DMA Capture complete callback.
mbed_official	87:085cde657901	4311	* @param hdma : pointer to DMA handle.
mbed_official	87:085cde657901	4312	* @retval None
mbed_official	87:085cde657901	4313	*/
mbed_official	87:085cde657901	4314	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4315	{
mbed_official	87:085cde657901	4316	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4317
mbed_official	87:085cde657901	4318	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4319
mbed_official	87:085cde657901	4320	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	4321
mbed_official	87:085cde657901	4322	}
mbed_official	87:085cde657901	4323
mbed_official	87:085cde657901	4324	/**
mbed_official	87:085cde657901	4325	* @brief TIM DMA Period Elapse complete callback.
mbed_official	87:085cde657901	4326	* @param hdma : pointer to DMA handle.
mbed_official	87:085cde657901	4327	* @retval None
mbed_official	87:085cde657901	4328	*/
mbed_official	87:085cde657901	4329	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4330	{
mbed_official	87:085cde657901	4331	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4332
mbed_official	87:085cde657901	4333	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4334
mbed_official	87:085cde657901	4335	HAL_TIM_PeriodElapsedCallback(htim);
mbed_official	87:085cde657901	4336	}
mbed_official	87:085cde657901	4337
mbed_official	87:085cde657901	4338	/**
mbed_official	87:085cde657901	4339	* @brief TIM DMA Trigger callback.
mbed_official	87:085cde657901	4340	* @param hdma : pointer to DMA handle.
mbed_official	87:085cde657901	4341	* @retval None
mbed_official	87:085cde657901	4342	*/
mbed_official	87:085cde657901	4343	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4344	{
mbed_official	87:085cde657901	4345	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4346
mbed_official	87:085cde657901	4347	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4348
mbed_official	87:085cde657901	4349	HAL_TIM_TriggerCallback(htim);
mbed_official	87:085cde657901	4350	}
mbed_official	87:085cde657901	4351
mbed_official	87:085cde657901	4352	/**
mbed_official	87:085cde657901	4353	* @brief Time Base configuration
mbed_official	87:085cde657901	4354	* @param TIMx: TIM periheral
mbed_official	87:085cde657901	4355	* @retval None
mbed_official	87:085cde657901	4356	*/
mbed_official	87:085cde657901	4357	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
mbed_official	87:085cde657901	4358	{
mbed_official	87:085cde657901	4359	uint32_t tmpcr1 = 0;
mbed_official	87:085cde657901	4360	tmpcr1 = TIMx->CR1;
mbed_official	87:085cde657901	4361
mbed_official	87:085cde657901	4362	/* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official	87:085cde657901	4363	if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4364	{
mbed_official	87:085cde657901	4365	/* Select the Counter Mode */
mbed_official	87:085cde657901	4366	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
mbed_official	87:085cde657901	4367	tmpcr1 \|= Structure->CounterMode;
mbed_official	87:085cde657901	4368	}
mbed_official	87:085cde657901	4369
mbed_official	87:085cde657901	4370	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4371	{
mbed_official	87:085cde657901	4372	/* Set the clock division */
mbed_official	87:085cde657901	4373	tmpcr1 &= ~TIM_CR1_CKD;
mbed_official	87:085cde657901	4374	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
mbed_official	87:085cde657901	4375	}
mbed_official	87:085cde657901	4376
mbed_official	87:085cde657901	4377	TIMx->CR1 = tmpcr1;
mbed_official	87:085cde657901	4378
mbed_official	87:085cde657901	4379	/* Set the Autoreload value */
mbed_official	87:085cde657901	4380	TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official	87:085cde657901	4381
mbed_official	87:085cde657901	4382	/* Set the Prescaler value */
mbed_official	87:085cde657901	4383	TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official	87:085cde657901	4384
mbed_official	87:085cde657901	4385	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4386	{
mbed_official	87:085cde657901	4387	/* Set the Repetition Counter value */
mbed_official	87:085cde657901	4388	TIMx->RCR = Structure->RepetitionCounter;
mbed_official	87:085cde657901	4389	}
mbed_official	87:085cde657901	4390
mbed_official	87:085cde657901	4391	/* Generate an update event to reload the Prescaler
mbed_official	87:085cde657901	4392	and the repetition counter(only for TIM1 and TIM8) value immediatly */
mbed_official	87:085cde657901	4393	TIMx->EGR = TIM_EGR_UG;
mbed_official	87:085cde657901	4394	}
mbed_official	87:085cde657901	4395
mbed_official	87:085cde657901	4396	/**
mbed_official	87:085cde657901	4397	* @brief Time Ouput Compare 1 configuration
mbed_official	87:085cde657901	4398	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4399	* @param OC_Config: The ouput configuration structure
mbed_official	87:085cde657901	4400	* @retval None
mbed_official	87:085cde657901	4401	*/
mbed_official	87:085cde657901	4402	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	87:085cde657901	4403	{
mbed_official	87:085cde657901	4404	uint32_t tmpccmrx = 0;
mbed_official	87:085cde657901	4405	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4406	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	4407
mbed_official	87:085cde657901	4408	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	87:085cde657901	4409	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	87:085cde657901	4410
mbed_official	87:085cde657901	4411	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	4412	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4413	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	4414	tmpcr2 = TIMx->CR2;
mbed_official	87:085cde657901	4415
mbed_official	87:085cde657901	4416	/* Get the TIMx CCMR1 register value */
mbed_official	87:085cde657901	4417	tmpccmrx = TIMx->CCMR1;
mbed_official	87:085cde657901	4418
mbed_official	87:085cde657901	4419	/* Reset the Output Compare Mode Bits */
mbed_official	87:085cde657901	4420	tmpccmrx &= ~TIM_CCMR1_OC1M;
mbed_official	87:085cde657901	4421	tmpccmrx &= ~TIM_CCMR1_CC1S;
mbed_official	87:085cde657901	4422	/* Select the Output Compare Mode */
mbed_official	87:085cde657901	4423	tmpccmrx \|= OC_Config->OCMode;
mbed_official	87:085cde657901	4424
mbed_official	87:085cde657901	4425	/* Reset the Output Polarity level */
mbed_official	87:085cde657901	4426	tmpccer &= ~TIM_CCER_CC1P;
mbed_official	87:085cde657901	4427	/* Set the Output Compare Polarity */
mbed_official	87:085cde657901	4428	tmpccer \|= OC_Config->OCPolarity;
mbed_official	87:085cde657901	4429
mbed_official	87:085cde657901	4430
mbed_official	87:085cde657901	4431	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4432	{
mbed_official	87:085cde657901	4433	/* Reset the Output N Polarity level */
mbed_official	87:085cde657901	4434	tmpccer &= ~TIM_CCER_CC1NP;
mbed_official	87:085cde657901	4435	/* Set the Output N Polarity */
mbed_official	87:085cde657901	4436	tmpccer \|= OC_Config->OCNPolarity;
mbed_official	87:085cde657901	4437	/* Reset the Output N State */
mbed_official	87:085cde657901	4438	tmpccer &= ~TIM_CCER_CC1NE;
mbed_official	87:085cde657901	4439
mbed_official	87:085cde657901	4440	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	87:085cde657901	4441	tmpcr2 &= ~TIM_CR2_OIS1;
mbed_official	87:085cde657901	4442	tmpcr2 &= ~TIM_CR2_OIS1N;
mbed_official	87:085cde657901	4443	/* Set the Output Idle state */
mbed_official	87:085cde657901	4444	tmpcr2 \|= OC_Config->OCIdleState;
mbed_official	87:085cde657901	4445	/* Set the Output N Idle state */
mbed_official	87:085cde657901	4446	tmpcr2 \|= OC_Config->OCNIdleState;
mbed_official	87:085cde657901	4447	}
mbed_official	87:085cde657901	4448	/* Write to TIMx CR2 */
mbed_official	87:085cde657901	4449	TIMx->CR2 = tmpcr2;
mbed_official	87:085cde657901	4450
mbed_official	87:085cde657901	4451	/* Write to TIMx CCMR1 */
mbed_official	87:085cde657901	4452	TIMx->CCMR1 = tmpccmrx;
mbed_official	87:085cde657901	4453
mbed_official	87:085cde657901	4454	/* Set the Capture Compare Register value */
mbed_official	87:085cde657901	4455	TIMx->CCR1 = OC_Config->Pulse;
mbed_official	87:085cde657901	4456
mbed_official	87:085cde657901	4457	/* Write to TIMx CCER */
mbed_official	87:085cde657901	4458	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4459	}
mbed_official	87:085cde657901	4460
mbed_official	87:085cde657901	4461	/**
mbed_official	87:085cde657901	4462	* @brief Time Ouput Compare 2 configuration
mbed_official	87:085cde657901	4463	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4464	* @param OC_Config: The ouput configuration structure
mbed_official	87:085cde657901	4465	* @retval None
mbed_official	87:085cde657901	4466	*/
mbed_official	87:085cde657901	4467	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	87:085cde657901	4468	{
mbed_official	87:085cde657901	4469	uint32_t tmpccmrx = 0;
mbed_official	87:085cde657901	4470	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4471	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	4472
mbed_official	87:085cde657901	4473	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	87:085cde657901	4474	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	87:085cde657901	4475
mbed_official	87:085cde657901	4476	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	4477	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4478	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	4479	tmpcr2 = TIMx->CR2;
mbed_official	87:085cde657901	4480
mbed_official	87:085cde657901	4481	/* Get the TIMx CCMR1 register value */
mbed_official	87:085cde657901	4482	tmpccmrx = TIMx->CCMR1;
mbed_official	87:085cde657901	4483
mbed_official	87:085cde657901	4484	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	87:085cde657901	4485	tmpccmrx &= ~TIM_CCMR1_OC2M;
mbed_official	87:085cde657901	4486	tmpccmrx &= ~TIM_CCMR1_CC2S;
mbed_official	87:085cde657901	4487
mbed_official	87:085cde657901	4488	/* Select the Output Compare Mode */
mbed_official	87:085cde657901	4489	tmpccmrx \|= (OC_Config->OCMode << 8);
mbed_official	87:085cde657901	4490
mbed_official	87:085cde657901	4491	/* Reset the Output Polarity level */
mbed_official	87:085cde657901	4492	tmpccer &= ~TIM_CCER_CC2P;
mbed_official	87:085cde657901	4493	/* Set the Output Compare Polarity */
mbed_official	87:085cde657901	4494	tmpccer \|= (OC_Config->OCPolarity << 4);
mbed_official	87:085cde657901	4495
mbed_official	87:085cde657901	4496	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4497	{
mbed_official	87:085cde657901	4498	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official	87:085cde657901	4499	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	87:085cde657901	4500	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	87:085cde657901	4501
mbed_official	87:085cde657901	4502	/* Reset the Output N Polarity level */
mbed_official	87:085cde657901	4503	tmpccer &= ~TIM_CCER_CC2NP;
mbed_official	87:085cde657901	4504	/* Set the Output N Polarity */
mbed_official	87:085cde657901	4505	tmpccer \|= (OC_Config->OCNPolarity << 4);
mbed_official	87:085cde657901	4506	/* Reset the Output N State */
mbed_official	87:085cde657901	4507	tmpccer &= ~TIM_CCER_CC2NE;
mbed_official	87:085cde657901	4508
mbed_official	87:085cde657901	4509	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	87:085cde657901	4510	tmpcr2 &= ~TIM_CR2_OIS2;
mbed_official	87:085cde657901	4511	tmpcr2 &= ~TIM_CR2_OIS2N;
mbed_official	87:085cde657901	4512	/* Set the Output Idle state */
mbed_official	87:085cde657901	4513	tmpcr2 \|= (OC_Config->OCIdleState << 2);
mbed_official	87:085cde657901	4514	/* Set the Output N Idle state */
mbed_official	87:085cde657901	4515	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
mbed_official	87:085cde657901	4516	}
mbed_official	87:085cde657901	4517	/* Write to TIMx CR2 */
mbed_official	87:085cde657901	4518	TIMx->CR2 = tmpcr2;
mbed_official	87:085cde657901	4519
mbed_official	87:085cde657901	4520	/* Write to TIMx CCMR1 */
mbed_official	87:085cde657901	4521	TIMx->CCMR1 = tmpccmrx;
mbed_official	87:085cde657901	4522
mbed_official	87:085cde657901	4523	/* Set the Capture Compare Register value */
mbed_official	87:085cde657901	4524	TIMx->CCR2 = OC_Config->Pulse;
mbed_official	87:085cde657901	4525
mbed_official	87:085cde657901	4526	/* Write to TIMx CCER */
mbed_official	87:085cde657901	4527	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4528	}
mbed_official	87:085cde657901	4529
mbed_official	87:085cde657901	4530	/**
mbed_official	87:085cde657901	4531	* @brief Time Ouput Compare 3 configuration
mbed_official	87:085cde657901	4532	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4533	* @param OC_Config: The ouput configuration structure
mbed_official	87:085cde657901	4534	* @retval None
mbed_official	87:085cde657901	4535	*/
mbed_official	87:085cde657901	4536	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	87:085cde657901	4537	{
mbed_official	87:085cde657901	4538	uint32_t tmpccmrx = 0;
mbed_official	87:085cde657901	4539	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4540	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	4541
mbed_official	87:085cde657901	4542	/* Disable the Channel 3: Reset the CC2E Bit */
mbed_official	87:085cde657901	4543	TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official	87:085cde657901	4544
mbed_official	87:085cde657901	4545	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	4546	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4547	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	4548	tmpcr2 = TIMx->CR2;
mbed_official	87:085cde657901	4549
mbed_official	87:085cde657901	4550	/* Get the TIMx CCMR2 register value */
mbed_official	87:085cde657901	4551	tmpccmrx = TIMx->CCMR2;
mbed_official	87:085cde657901	4552
mbed_official	87:085cde657901	4553	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	87:085cde657901	4554	tmpccmrx &= ~TIM_CCMR2_OC3M;
mbed_official	87:085cde657901	4555	tmpccmrx &= ~TIM_CCMR2_CC3S;
mbed_official	87:085cde657901	4556	/* Select the Output Compare Mode */
mbed_official	87:085cde657901	4557	tmpccmrx \|= OC_Config->OCMode;
mbed_official	87:085cde657901	4558
mbed_official	87:085cde657901	4559	/* Reset the Output Polarity level */
mbed_official	87:085cde657901	4560	tmpccer &= ~TIM_CCER_CC3P;
mbed_official	87:085cde657901	4561	/* Set the Output Compare Polarity */
mbed_official	87:085cde657901	4562	tmpccer \|= (OC_Config->OCPolarity << 8);
mbed_official	87:085cde657901	4563
mbed_official	87:085cde657901	4564	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4565	{
mbed_official	87:085cde657901	4566	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official	87:085cde657901	4567	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	87:085cde657901	4568	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	87:085cde657901	4569
mbed_official	87:085cde657901	4570	/* Reset the Output N Polarity level */
mbed_official	87:085cde657901	4571	tmpccer &= ~TIM_CCER_CC3NP;
mbed_official	87:085cde657901	4572	/* Set the Output N Polarity */
mbed_official	87:085cde657901	4573	tmpccer \|= (OC_Config->OCNPolarity << 8);
mbed_official	87:085cde657901	4574	/* Reset the Output N State */
mbed_official	87:085cde657901	4575	tmpccer &= ~TIM_CCER_CC3NE;
mbed_official	87:085cde657901	4576
mbed_official	87:085cde657901	4577	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	87:085cde657901	4578	tmpcr2 &= ~TIM_CR2_OIS3;
mbed_official	87:085cde657901	4579	tmpcr2 &= ~TIM_CR2_OIS3N;
mbed_official	87:085cde657901	4580	/* Set the Output Idle state */
mbed_official	87:085cde657901	4581	tmpcr2 \|= (OC_Config->OCIdleState << 4);
mbed_official	87:085cde657901	4582	/* Set the Output N Idle state */
mbed_official	87:085cde657901	4583	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
mbed_official	87:085cde657901	4584	}
mbed_official	87:085cde657901	4585	/* Write to TIMx CR2 */
mbed_official	87:085cde657901	4586	TIMx->CR2 = tmpcr2;
mbed_official	87:085cde657901	4587
mbed_official	87:085cde657901	4588	/* Write to TIMx CCMR2 */
mbed_official	87:085cde657901	4589	TIMx->CCMR2 = tmpccmrx;
mbed_official	87:085cde657901	4590
mbed_official	87:085cde657901	4591	/* Set the Capture Compare Register value */
mbed_official	87:085cde657901	4592	TIMx->CCR3 = OC_Config->Pulse;
mbed_official	87:085cde657901	4593
mbed_official	87:085cde657901	4594	/* Write to TIMx CCER */
mbed_official	87:085cde657901	4595	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4596	}
mbed_official	87:085cde657901	4597
mbed_official	87:085cde657901	4598	/**
mbed_official	87:085cde657901	4599	* @brief Time Ouput Compare 4 configuration
mbed_official	87:085cde657901	4600	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4601	* @param OC_Config: The ouput configuration structure
mbed_official	87:085cde657901	4602	* @retval None
mbed_official	87:085cde657901	4603	*/
mbed_official	87:085cde657901	4604	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	87:085cde657901	4605	{
mbed_official	87:085cde657901	4606	uint32_t tmpccmrx = 0;
mbed_official	87:085cde657901	4607	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4608	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	4609
mbed_official	87:085cde657901	4610	/* Disable the Channel 4: Reset the CC4E Bit */
mbed_official	87:085cde657901	4611	TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official	87:085cde657901	4612
mbed_official	87:085cde657901	4613	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	4614	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4615	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	4616	tmpcr2 = TIMx->CR2;
mbed_official	87:085cde657901	4617
mbed_official	87:085cde657901	4618	/* Get the TIMx CCMR2 register value */
mbed_official	87:085cde657901	4619	tmpccmrx = TIMx->CCMR2;
mbed_official	87:085cde657901	4620
mbed_official	87:085cde657901	4621	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	87:085cde657901	4622	tmpccmrx &= ~TIM_CCMR2_OC4M;
mbed_official	87:085cde657901	4623	tmpccmrx &= ~TIM_CCMR2_CC4S;
mbed_official	87:085cde657901	4624
mbed_official	87:085cde657901	4625	/* Select the Output Compare Mode */
mbed_official	87:085cde657901	4626	tmpccmrx \|= (OC_Config->OCMode << 8);
mbed_official	87:085cde657901	4627
mbed_official	87:085cde657901	4628	/* Reset the Output Polarity level */
mbed_official	87:085cde657901	4629	tmpccer &= ~TIM_CCER_CC4P;
mbed_official	87:085cde657901	4630	/* Set the Output Compare Polarity */
mbed_official	87:085cde657901	4631	tmpccer \|= (OC_Config->OCPolarity << 12);
mbed_official	87:085cde657901	4632
mbed_official	87:085cde657901	4633	/if((TIMx == TIM1) \|\| (TIMx == TIM8))/
mbed_official	87:085cde657901	4634	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4635	{
mbed_official	87:085cde657901	4636	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	87:085cde657901	4637	/* Reset the Output Compare IDLE State */
mbed_official	87:085cde657901	4638	tmpcr2 &= ~TIM_CR2_OIS4;
mbed_official	87:085cde657901	4639	/* Set the Output Idle state */
mbed_official	87:085cde657901	4640	tmpcr2 \|= (OC_Config->OCIdleState << 6);
mbed_official	87:085cde657901	4641	}
mbed_official	87:085cde657901	4642	/* Write to TIMx CR2 */
mbed_official	87:085cde657901	4643	TIMx->CR2 = tmpcr2;
mbed_official	87:085cde657901	4644
mbed_official	87:085cde657901	4645	/* Write to TIMx CCMR2 */
mbed_official	87:085cde657901	4646	TIMx->CCMR2 = tmpccmrx;
mbed_official	87:085cde657901	4647
mbed_official	87:085cde657901	4648	/* Set the Capture Compare Register value */
mbed_official	87:085cde657901	4649	TIMx->CCR4 = OC_Config->Pulse;
mbed_official	87:085cde657901	4650
mbed_official	87:085cde657901	4651	/* Write to TIMx CCER */
mbed_official	87:085cde657901	4652	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4653	}
mbed_official	87:085cde657901	4654
mbed_official	87:085cde657901	4655	/**
mbed_official	87:085cde657901	4656	* @brief Configure the TI1 as Input.
mbed_official	87:085cde657901	4657	* @param TIMx to select the TIM peripheral.
mbed_official	87:085cde657901	4658	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4659	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4660	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4661	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4662	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4663	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	87:085cde657901	4664	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4665	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official	87:085cde657901	4666	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official	87:085cde657901	4667	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official	87:085cde657901	4668	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4669	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4670	* @retval None
mbed_official	87:085cde657901	4671	*/
mbed_official	87:085cde657901	4672	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	4673	uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4674	{
mbed_official	87:085cde657901	4675	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	4676	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4677
mbed_official	87:085cde657901	4678	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	87:085cde657901	4679	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	87:085cde657901	4680	tmpccmr1 = TIMx->CCMR1;
mbed_official	87:085cde657901	4681	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4682
mbed_official	87:085cde657901	4683	/* Select the Input */
mbed_official	87:085cde657901	4684	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4685	{
mbed_official	87:085cde657901	4686	tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official	87:085cde657901	4687	tmpccmr1 \|= TIM_ICSelection;
mbed_official	87:085cde657901	4688	}
mbed_official	87:085cde657901	4689	else
mbed_official	87:085cde657901	4690	{
mbed_official	87:085cde657901	4691	tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official	87:085cde657901	4692	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
mbed_official	87:085cde657901	4693	}
mbed_official	87:085cde657901	4694
mbed_official	87:085cde657901	4695	/* Set the filter */
mbed_official	87:085cde657901	4696	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	87:085cde657901	4697	tmpccmr1 \|= (TIM_ICFilter << 4);
mbed_official	87:085cde657901	4698
mbed_official	87:085cde657901	4699	/* Select the Polarity and set the CC1E Bit */
mbed_official	87:085cde657901	4700	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
mbed_official	87:085cde657901	4701	tmpccer \|= TIM_ICPolarity;
mbed_official	87:085cde657901	4702
mbed_official	87:085cde657901	4703	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4704	TIMx->CCMR1 = tmpccmr1;
mbed_official	87:085cde657901	4705	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4706	}
mbed_official	87:085cde657901	4707
mbed_official	87:085cde657901	4708	/**
mbed_official	87:085cde657901	4709	* @brief Configure the Polarity and Filter for TI1.
mbed_official	87:085cde657901	4710	* @param TIMx to select the TIM peripheral.
mbed_official	87:085cde657901	4711	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4712	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4713	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4714	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4715	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4716	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4717	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4718	* @retval None
mbed_official	87:085cde657901	4719	*/
mbed_official	87:085cde657901	4720	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4721	{
mbed_official	87:085cde657901	4722	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	4723	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4724
mbed_official	87:085cde657901	4725	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	87:085cde657901	4726	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4727	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	87:085cde657901	4728	tmpccmr1 = TIMx->CCMR1;
mbed_official	87:085cde657901	4729
mbed_official	87:085cde657901	4730	/* Set the filter */
mbed_official	87:085cde657901	4731	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	87:085cde657901	4732	tmpccmr1 \|= (TIM_ICFilter << 4);
mbed_official	87:085cde657901	4733
mbed_official	87:085cde657901	4734	/* Select the Polarity and set the CC1E Bit */
mbed_official	87:085cde657901	4735	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
mbed_official	87:085cde657901	4736	tmpccer \|= TIM_ICPolarity;
mbed_official	87:085cde657901	4737
mbed_official	87:085cde657901	4738	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4739	TIMx->CCMR1 = tmpccmr1;
mbed_official	87:085cde657901	4740	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4741	}
mbed_official	87:085cde657901	4742
mbed_official	87:085cde657901	4743	/**
mbed_official	87:085cde657901	4744	* @brief Configure the TI2 as Input.
mbed_official	87:085cde657901	4745	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4746	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4747	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4748	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4749	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4750	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4751	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	87:085cde657901	4752	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4753	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official	87:085cde657901	4754	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official	87:085cde657901	4755	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official	87:085cde657901	4756	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4757	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4758	* @retval None
mbed_official	87:085cde657901	4759	*/
mbed_official	87:085cde657901	4760	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	4761	uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4762	{
mbed_official	87:085cde657901	4763	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	4764	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4765
mbed_official	87:085cde657901	4766	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	87:085cde657901	4767	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	87:085cde657901	4768	tmpccmr1 = TIMx->CCMR1;
mbed_official	87:085cde657901	4769	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4770
mbed_official	87:085cde657901	4771	/* Select the Input */
mbed_official	87:085cde657901	4772	tmpccmr1 &= ~TIM_CCMR1_CC2S;
mbed_official	87:085cde657901	4773	tmpccmr1 \|= (TIM_ICSelection << 8);
mbed_official	87:085cde657901	4774
mbed_official	87:085cde657901	4775	/* Set the filter */
mbed_official	87:085cde657901	4776	tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official	87:085cde657901	4777	tmpccmr1 \|= (TIM_ICFilter << 12);
mbed_official	87:085cde657901	4778
mbed_official	87:085cde657901	4779	/* Select the Polarity and set the CC2E Bit */
mbed_official	87:085cde657901	4780	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
mbed_official	87:085cde657901	4781	tmpccer \|= (TIM_ICPolarity << 4);
mbed_official	87:085cde657901	4782
mbed_official	87:085cde657901	4783	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4784	TIMx->CCMR1 = tmpccmr1 ;
mbed_official	87:085cde657901	4785	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4786	}
mbed_official	87:085cde657901	4787
mbed_official	87:085cde657901	4788	/**
mbed_official	87:085cde657901	4789	* @brief Configure the Polarity and Filter for TI2.
mbed_official	87:085cde657901	4790	* @param TIMx to select the TIM peripheral.
mbed_official	87:085cde657901	4791	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4792	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4793	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4794	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4795	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4796	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4797	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4798	* @retval None
mbed_official	87:085cde657901	4799	*/
mbed_official	87:085cde657901	4800	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4801	{
mbed_official	87:085cde657901	4802	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	4803	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4804
mbed_official	87:085cde657901	4805	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	87:085cde657901	4806	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	87:085cde657901	4807	tmpccmr1 = TIMx->CCMR1;
mbed_official	87:085cde657901	4808	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4809
mbed_official	87:085cde657901	4810	/* Set the filter */
mbed_official	87:085cde657901	4811	tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official	87:085cde657901	4812	tmpccmr1 \|= (TIM_ICFilter << 12);
mbed_official	87:085cde657901	4813
mbed_official	87:085cde657901	4814	/* Select the Polarity and set the CC2E Bit */
mbed_official	87:085cde657901	4815	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
mbed_official	87:085cde657901	4816	tmpccer \|= (TIM_ICPolarity << 4);
mbed_official	87:085cde657901	4817
mbed_official	87:085cde657901	4818	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4819	TIMx->CCMR1 = tmpccmr1 ;
mbed_official	87:085cde657901	4820	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4821	}
mbed_official	87:085cde657901	4822
mbed_official	87:085cde657901	4823	/**
mbed_official	87:085cde657901	4824	* @brief Configure the TI3 as Input.
mbed_official	87:085cde657901	4825	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4826	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4827	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4828	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4829	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4830	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4831	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	87:085cde657901	4832	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4833	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official	87:085cde657901	4834	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official	87:085cde657901	4835	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official	87:085cde657901	4836	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4837	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4838	* @retval None
mbed_official	87:085cde657901	4839	*/
mbed_official	87:085cde657901	4840	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	4841	uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4842	{
mbed_official	87:085cde657901	4843	uint32_t tmpccmr2 = 0;
mbed_official	87:085cde657901	4844	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4845
mbed_official	87:085cde657901	4846	/* Disable the Channel 3: Reset the CC3E Bit */
mbed_official	87:085cde657901	4847	TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official	87:085cde657901	4848	tmpccmr2 = TIMx->CCMR2;
mbed_official	87:085cde657901	4849	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4850
mbed_official	87:085cde657901	4851	/* Select the Input */
mbed_official	87:085cde657901	4852	tmpccmr2 &= ~TIM_CCMR2_CC3S;
mbed_official	87:085cde657901	4853	tmpccmr2 \|= TIM_ICSelection;
mbed_official	87:085cde657901	4854
mbed_official	87:085cde657901	4855	/* Set the filter */
mbed_official	87:085cde657901	4856	tmpccmr2 &= ~TIM_CCMR2_IC3F;
mbed_official	87:085cde657901	4857	tmpccmr2 \|= (TIM_ICFilter << 4);
mbed_official	87:085cde657901	4858
mbed_official	87:085cde657901	4859	/* Select the Polarity and set the CC3E Bit */
mbed_official	87:085cde657901	4860	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
mbed_official	87:085cde657901	4861	tmpccer \|= (TIM_ICPolarity << 8);
mbed_official	87:085cde657901	4862
mbed_official	87:085cde657901	4863	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	87:085cde657901	4864	TIMx->CCMR2 = tmpccmr2;
mbed_official	87:085cde657901	4865	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4866	}
mbed_official	87:085cde657901	4867
mbed_official	87:085cde657901	4868	/**
mbed_official	87:085cde657901	4869	* @brief Configure the TI4 as Input.
mbed_official	87:085cde657901	4870	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4871	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4872	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4873	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4874	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4875	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4876	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	87:085cde657901	4877	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4878	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official	87:085cde657901	4879	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official	87:085cde657901	4880	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official	87:085cde657901	4881	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4882	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4883	* @retval None
mbed_official	87:085cde657901	4884	*/
mbed_official	87:085cde657901	4885	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	4886	uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4887	{
mbed_official	87:085cde657901	4888	uint32_t tmpccmr2 = 0;
mbed_official	87:085cde657901	4889	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4890
mbed_official	87:085cde657901	4891	/* Disable the Channel 4: Reset the CC4E Bit */
mbed_official	87:085cde657901	4892	TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official	87:085cde657901	4893	tmpccmr2 = TIMx->CCMR2;
mbed_official	87:085cde657901	4894	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4895
mbed_official	87:085cde657901	4896	/* Select the Input */
mbed_official	87:085cde657901	4897	tmpccmr2 &= ~TIM_CCMR2_CC4S;
mbed_official	87:085cde657901	4898	tmpccmr2 \|= (TIM_ICSelection << 8);
mbed_official	87:085cde657901	4899
mbed_official	87:085cde657901	4900	/* Set the filter */
mbed_official	87:085cde657901	4901	tmpccmr2 &= ~TIM_CCMR2_IC4F;
mbed_official	87:085cde657901	4902	tmpccmr2 \|= (TIM_ICFilter << 12);
mbed_official	87:085cde657901	4903
mbed_official	87:085cde657901	4904	/* Select the Polarity and set the CC4E Bit */
mbed_official	87:085cde657901	4905	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
mbed_official	87:085cde657901	4906	tmpccer \|= (TIM_ICPolarity << 12);
mbed_official	87:085cde657901	4907
mbed_official	87:085cde657901	4908	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	87:085cde657901	4909	TIMx->CCMR2 = tmpccmr2;
mbed_official	87:085cde657901	4910	TIMx->CCER = tmpccer ;
mbed_official	87:085cde657901	4911	}
mbed_official	87:085cde657901	4912
mbed_official	87:085cde657901	4913	/**
mbed_official	87:085cde657901	4914	* @brief Selects the Input Trigger source
mbed_official	87:085cde657901	4915	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4916	* @param InputTriggerSource: The Input Trigger source.
mbed_official	87:085cde657901	4917	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4918	* @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official	87:085cde657901	4919	* @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official	87:085cde657901	4920	* @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official	87:085cde657901	4921	* @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official	87:085cde657901	4922	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official	87:085cde657901	4923	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official	87:085cde657901	4924	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official	87:085cde657901	4925	* @arg TIM_TS_ETRF: External Trigger input
mbed_official	87:085cde657901	4926	* @retval None
mbed_official	87:085cde657901	4927	*/
mbed_official	87:085cde657901	4928	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
mbed_official	87:085cde657901	4929	{
mbed_official	87:085cde657901	4930	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	4931
mbed_official	87:085cde657901	4932	/* Get the TIMx SMCR register value */
mbed_official	87:085cde657901	4933	tmpsmcr = TIMx->SMCR;
mbed_official	87:085cde657901	4934	/* Reset the TS Bits */
mbed_official	87:085cde657901	4935	tmpsmcr &= ~TIM_SMCR_TS;
mbed_official	87:085cde657901	4936	/* Set the Input Trigger source and the slave mode*/
mbed_official	87:085cde657901	4937	tmpsmcr \|= TIM_ITRx \| TIM_SLAVEMODE_EXTERNAL1;
mbed_official	87:085cde657901	4938	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	4939	TIMx->SMCR = tmpsmcr;
mbed_official	87:085cde657901	4940	}
mbed_official	87:085cde657901	4941	/**
mbed_official	87:085cde657901	4942	* @brief Configures the TIMx External Trigger (ETR).
mbed_official	87:085cde657901	4943	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4944	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official	87:085cde657901	4945	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4946	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
mbed_official	87:085cde657901	4947	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official	87:085cde657901	4948	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official	87:085cde657901	4949	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official	87:085cde657901	4950	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official	87:085cde657901	4951	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4952	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official	87:085cde657901	4953	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official	87:085cde657901	4954	* @param ExtTRGFilter: External Trigger Filter.
mbed_official	87:085cde657901	4955	* This parameter must be a value between 0x00 and 0x0F
mbed_official	87:085cde657901	4956	* @retval None
mbed_official	87:085cde657901	4957	*/
mbed_official	87:085cde657901	4958	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official	87:085cde657901	4959	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official	87:085cde657901	4960	{
mbed_official	87:085cde657901	4961	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	4962
mbed_official	87:085cde657901	4963	tmpsmcr = TIMx->SMCR;
mbed_official	87:085cde657901	4964
mbed_official	87:085cde657901	4965	/* Reset the ETR Bits */
mbed_official	87:085cde657901	4966	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
mbed_official	87:085cde657901	4967
mbed_official	87:085cde657901	4968	/* Set the Prescaler, the Filter value and the Polarity */
mbed_official	87:085cde657901	4969	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
mbed_official	87:085cde657901	4970
mbed_official	87:085cde657901	4971	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	4972	TIMx->SMCR = tmpsmcr;
mbed_official	87:085cde657901	4973	}
mbed_official	87:085cde657901	4974
mbed_official	87:085cde657901	4975	/**
mbed_official	87:085cde657901	4976	* @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official	87:085cde657901	4977	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4978	* @param Channel: specifies the TIM Channel
mbed_official	87:085cde657901	4979	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4980	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	87:085cde657901	4981	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	87:085cde657901	4982	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	87:085cde657901	4983	* @arg TIM_Channel_4: TIM Channel 4
mbed_official	87:085cde657901	4984	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
mbed_official	87:085cde657901	4985	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official	87:085cde657901	4986	* @retval None
mbed_official	87:085cde657901	4987	*/
mbed_official	87:085cde657901	4988	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official	87:085cde657901	4989	{
mbed_official	87:085cde657901	4990	uint32_t tmp = 0;
mbed_official	87:085cde657901	4991
mbed_official	87:085cde657901	4992	/* Check the parameters */
mbed_official	87:085cde657901	4993	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
mbed_official	87:085cde657901	4994	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	87:085cde657901	4995
mbed_official	87:085cde657901	4996	tmp = TIM_CCER_CC1E << Channel;
mbed_official	87:085cde657901	4997
mbed_official	87:085cde657901	4998	/* Reset the CCxE Bit */
mbed_official	87:085cde657901	4999	TIMx->CCER &= ~tmp;
mbed_official	87:085cde657901	5000
mbed_official	87:085cde657901	5001	/* Set or reset the CCxE Bit */
mbed_official	87:085cde657901	5002	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
mbed_official	87:085cde657901	5003	}
mbed_official	87:085cde657901	5004
mbed_official	87:085cde657901	5005
mbed_official	87:085cde657901	5006	/**
mbed_official	87:085cde657901	5007	* @}
mbed_official	87:085cde657901	5008	*/
mbed_official	87:085cde657901	5009
mbed_official	87:085cde657901	5010	#endif /* HAL_TIM_MODULE_ENABLED */
mbed_official	87:085cde657901	5011	/**
mbed_official	87:085cde657901	5012	* @}
mbed_official	87:085cde657901	5013	*/
mbed_official	87:085cde657901	5014
mbed_official	87:085cde657901	5015	/**
mbed_official	87:085cde657901	5016	* @}
mbed_official	87:085cde657901	5017	*/
mbed_official	87:085cde657901	5018	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	29 Jun 2014
Imports:	3
Forks:	0
Commits:	135
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.c@87:085cde657901, 2014-02-08 (annotated)

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