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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.c@87:085cde657901, 2014-02-08 (annotated)
- Committer:
- mbed_official
- Date:
- Sat Feb 08 19:45:06 2014 +0000
- Revision:
- 87:085cde657901
- Child:
- 106:ced8cbb51063
Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2
Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/
Add NUCLEO_F401RE, improvements
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 87:085cde657901 | 1 | /** |
mbed_official | 87:085cde657901 | 2 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 3 | * @file stm32f4xx_hal_sdram.c |
mbed_official | 87:085cde657901 | 4 | * @author MCD Application Team |
mbed_official | 87:085cde657901 | 5 | * @version V1.0.0RC2 |
mbed_official | 87:085cde657901 | 6 | * @date 04-February-2014 |
mbed_official | 87:085cde657901 | 7 | * @brief SDRAM HAL module driver. |
mbed_official | 87:085cde657901 | 8 | * This file provides a generic firmware to drive SDRAM memories mounted |
mbed_official | 87:085cde657901 | 9 | * as external device. |
mbed_official | 87:085cde657901 | 10 | * |
mbed_official | 87:085cde657901 | 11 | @verbatim |
mbed_official | 87:085cde657901 | 12 | ============================================================================== |
mbed_official | 87:085cde657901 | 13 | ##### How to use this driver ##### |
mbed_official | 87:085cde657901 | 14 | ============================================================================== |
mbed_official | 87:085cde657901 | 15 | [..] |
mbed_official | 87:085cde657901 | 16 | This driver is a generic layered driver which contains a set of APIs used to |
mbed_official | 87:085cde657901 | 17 | control SDRAM memories. It uses the FMC layer functions to interface |
mbed_official | 87:085cde657901 | 18 | with SDRAM devices. |
mbed_official | 87:085cde657901 | 19 | The following sequence should be followed to configure the FMC to interface |
mbed_official | 87:085cde657901 | 20 | with SDRAM memories: |
mbed_official | 87:085cde657901 | 21 | |
mbed_official | 87:085cde657901 | 22 | (#) Declare a SDRAM_HandleTypeDef handle structure, for example: |
mbed_official | 87:085cde657901 | 23 | SDRAM_HandleTypeDef hdsram; and: |
mbed_official | 87:085cde657901 | 24 | |
mbed_official | 87:085cde657901 | 25 | (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed |
mbed_official | 87:085cde657901 | 26 | values of the structure member. |
mbed_official | 87:085cde657901 | 27 | |
mbed_official | 87:085cde657901 | 28 | (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined |
mbed_official | 87:085cde657901 | 29 | base register instance for NOR or SDRAM device |
mbed_official | 87:085cde657901 | 30 | |
mbed_official | 87:085cde657901 | 31 | (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: |
mbed_official | 87:085cde657901 | 32 | FMC_SDRAM_TimingTypeDef Timing; |
mbed_official | 87:085cde657901 | 33 | and fill its fields with the allowed values of the structure member. |
mbed_official | 87:085cde657901 | 34 | |
mbed_official | 87:085cde657901 | 35 | (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function |
mbed_official | 87:085cde657901 | 36 | performs the following sequence: |
mbed_official | 87:085cde657901 | 37 | |
mbed_official | 87:085cde657901 | 38 | (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() |
mbed_official | 87:085cde657901 | 39 | (##) Control register configuration using the FMC SDRAM interface function |
mbed_official | 87:085cde657901 | 40 | FMC_SDRAM_Init() |
mbed_official | 87:085cde657901 | 41 | (##) Timing register configuration using the FMC SDRAM interface function |
mbed_official | 87:085cde657901 | 42 | FMC_SDRAM_Timing_Init() |
mbed_official | 87:085cde657901 | 43 | (##) Program the SDRAM external device by applying its initialization sequence |
mbed_official | 87:085cde657901 | 44 | according to the device plugged in your hardware. This step is mandatory |
mbed_official | 87:085cde657901 | 45 | for accessing the SDRAM device. |
mbed_official | 87:085cde657901 | 46 | |
mbed_official | 87:085cde657901 | 47 | (#) At this stage you can perform read/write accesses from/to the memory connected |
mbed_official | 87:085cde657901 | 48 | to the SDRAM Bank. You can perform either polling or DMA transfer using the |
mbed_official | 87:085cde657901 | 49 | following APIs: |
mbed_official | 87:085cde657901 | 50 | (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access |
mbed_official | 87:085cde657901 | 51 | (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer |
mbed_official | 87:085cde657901 | 52 | |
mbed_official | 87:085cde657901 | 53 | (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ |
mbed_official | 87:085cde657901 | 54 | HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or |
mbed_official | 87:085cde657901 | 55 | the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM |
mbed_official | 87:085cde657901 | 56 | device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef |
mbed_official | 87:085cde657901 | 57 | structure. |
mbed_official | 87:085cde657901 | 58 | |
mbed_official | 87:085cde657901 | 59 | (#) You can continuously monitor the SDRAM device HAL state by calling the function |
mbed_official | 87:085cde657901 | 60 | HAL_SDRAM_GetState() |
mbed_official | 87:085cde657901 | 61 | |
mbed_official | 87:085cde657901 | 62 | @endverbatim |
mbed_official | 87:085cde657901 | 63 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 64 | * @attention |
mbed_official | 87:085cde657901 | 65 | * |
mbed_official | 87:085cde657901 | 66 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 87:085cde657901 | 67 | * |
mbed_official | 87:085cde657901 | 68 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 87:085cde657901 | 69 | * are permitted provided that the following conditions are met: |
mbed_official | 87:085cde657901 | 70 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 87:085cde657901 | 71 | * this list of conditions and the following disclaimer. |
mbed_official | 87:085cde657901 | 72 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 87:085cde657901 | 73 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 87:085cde657901 | 74 | * and/or other materials provided with the distribution. |
mbed_official | 87:085cde657901 | 75 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 87:085cde657901 | 76 | * may be used to endorse or promote products derived from this software |
mbed_official | 87:085cde657901 | 77 | * without specific prior written permission. |
mbed_official | 87:085cde657901 | 78 | * |
mbed_official | 87:085cde657901 | 79 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 87:085cde657901 | 80 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 87:085cde657901 | 81 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 87:085cde657901 | 82 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 87:085cde657901 | 83 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 87:085cde657901 | 84 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 87:085cde657901 | 85 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 87:085cde657901 | 86 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 87:085cde657901 | 87 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 87:085cde657901 | 88 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 87:085cde657901 | 89 | * |
mbed_official | 87:085cde657901 | 90 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 91 | */ |
mbed_official | 87:085cde657901 | 92 | |
mbed_official | 87:085cde657901 | 93 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 94 | #include "stm32f4xx_hal.h" |
mbed_official | 87:085cde657901 | 95 | |
mbed_official | 87:085cde657901 | 96 | /** @addtogroup STM32F4xx_HAL_Driver |
mbed_official | 87:085cde657901 | 97 | * @{ |
mbed_official | 87:085cde657901 | 98 | */ |
mbed_official | 87:085cde657901 | 99 | |
mbed_official | 87:085cde657901 | 100 | /** @defgroup SDRAM |
mbed_official | 87:085cde657901 | 101 | * @brief SDRAM driver modules |
mbed_official | 87:085cde657901 | 102 | * @{ |
mbed_official | 87:085cde657901 | 103 | */ |
mbed_official | 87:085cde657901 | 104 | #ifdef HAL_SDRAM_MODULE_ENABLED |
mbed_official | 87:085cde657901 | 105 | |
mbed_official | 87:085cde657901 | 106 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
mbed_official | 87:085cde657901 | 107 | |
mbed_official | 87:085cde657901 | 108 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 109 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 110 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 111 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 112 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 113 | |
mbed_official | 87:085cde657901 | 114 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 115 | |
mbed_official | 87:085cde657901 | 116 | /** @defgroup SDRAM_Private_Functions |
mbed_official | 87:085cde657901 | 117 | * @{ |
mbed_official | 87:085cde657901 | 118 | */ |
mbed_official | 87:085cde657901 | 119 | |
mbed_official | 87:085cde657901 | 120 | /** @defgroup SDRAM_Group1 Initialization and de-initialization functions |
mbed_official | 87:085cde657901 | 121 | * @brief Initialization and Configuration functions |
mbed_official | 87:085cde657901 | 122 | * |
mbed_official | 87:085cde657901 | 123 | @verbatim |
mbed_official | 87:085cde657901 | 124 | ============================================================================== |
mbed_official | 87:085cde657901 | 125 | ##### SDRAM Initialization and de_initialization functions ##### |
mbed_official | 87:085cde657901 | 126 | ============================================================================== |
mbed_official | 87:085cde657901 | 127 | [..] |
mbed_official | 87:085cde657901 | 128 | This section provides functions allowing to initialize/de-initialize |
mbed_official | 87:085cde657901 | 129 | the SDRAM memory |
mbed_official | 87:085cde657901 | 130 | |
mbed_official | 87:085cde657901 | 131 | @endverbatim |
mbed_official | 87:085cde657901 | 132 | * @{ |
mbed_official | 87:085cde657901 | 133 | */ |
mbed_official | 87:085cde657901 | 134 | |
mbed_official | 87:085cde657901 | 135 | /** |
mbed_official | 87:085cde657901 | 136 | * @brief Performs the SDRAM device initialization sequence. |
mbed_official | 87:085cde657901 | 137 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 138 | * @param Timing: Pointer to SDRAM control timing structure |
mbed_official | 87:085cde657901 | 139 | * @retval HAL status |
mbed_official | 87:085cde657901 | 140 | */ |
mbed_official | 87:085cde657901 | 141 | HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) |
mbed_official | 87:085cde657901 | 142 | { |
mbed_official | 87:085cde657901 | 143 | /* Check the SDRAM handle parameter */ |
mbed_official | 87:085cde657901 | 144 | if(hsdram == NULL) |
mbed_official | 87:085cde657901 | 145 | { |
mbed_official | 87:085cde657901 | 146 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 147 | } |
mbed_official | 87:085cde657901 | 148 | |
mbed_official | 87:085cde657901 | 149 | if(hsdram->State == HAL_SDRAM_STATE_RESET) |
mbed_official | 87:085cde657901 | 150 | { |
mbed_official | 87:085cde657901 | 151 | /* Initialize the low level hardware (MSP) */ |
mbed_official | 87:085cde657901 | 152 | HAL_SDRAM_MspInit(hsdram); |
mbed_official | 87:085cde657901 | 153 | } |
mbed_official | 87:085cde657901 | 154 | |
mbed_official | 87:085cde657901 | 155 | /* Initialize the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 156 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 87:085cde657901 | 157 | |
mbed_official | 87:085cde657901 | 158 | /* Initialize SDRAM control Interface */ |
mbed_official | 87:085cde657901 | 159 | FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); |
mbed_official | 87:085cde657901 | 160 | |
mbed_official | 87:085cde657901 | 161 | /* Initialize SDRAM timing Interface */ |
mbed_official | 87:085cde657901 | 162 | FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); |
mbed_official | 87:085cde657901 | 163 | |
mbed_official | 87:085cde657901 | 164 | /* Update the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 165 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 87:085cde657901 | 166 | |
mbed_official | 87:085cde657901 | 167 | return HAL_OK; |
mbed_official | 87:085cde657901 | 168 | } |
mbed_official | 87:085cde657901 | 169 | |
mbed_official | 87:085cde657901 | 170 | /** |
mbed_official | 87:085cde657901 | 171 | * @brief Perform the SDRAM device initialization sequence. |
mbed_official | 87:085cde657901 | 172 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 173 | * @retval HAL status |
mbed_official | 87:085cde657901 | 174 | */ |
mbed_official | 87:085cde657901 | 175 | HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 176 | { |
mbed_official | 87:085cde657901 | 177 | /* Initialize the low level hardware (MSP) */ |
mbed_official | 87:085cde657901 | 178 | HAL_SDRAM_MspDeInit(hsdram); |
mbed_official | 87:085cde657901 | 179 | |
mbed_official | 87:085cde657901 | 180 | /* Configure the SDRAM registers with their reset values */ |
mbed_official | 87:085cde657901 | 181 | FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); |
mbed_official | 87:085cde657901 | 182 | |
mbed_official | 87:085cde657901 | 183 | return HAL_OK; |
mbed_official | 87:085cde657901 | 184 | } |
mbed_official | 87:085cde657901 | 185 | |
mbed_official | 87:085cde657901 | 186 | /** |
mbed_official | 87:085cde657901 | 187 | * @brief SDRAM MSP Init. |
mbed_official | 87:085cde657901 | 188 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 189 | * @retval None |
mbed_official | 87:085cde657901 | 190 | */ |
mbed_official | 87:085cde657901 | 191 | __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 192 | { |
mbed_official | 87:085cde657901 | 193 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 194 | the HAL_SDRAM_MspInit could be implemented in the user file |
mbed_official | 87:085cde657901 | 195 | */ |
mbed_official | 87:085cde657901 | 196 | } |
mbed_official | 87:085cde657901 | 197 | |
mbed_official | 87:085cde657901 | 198 | /** |
mbed_official | 87:085cde657901 | 199 | * @brief SDRAM MSP DeInit. |
mbed_official | 87:085cde657901 | 200 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 201 | * @retval None |
mbed_official | 87:085cde657901 | 202 | */ |
mbed_official | 87:085cde657901 | 203 | __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 204 | { |
mbed_official | 87:085cde657901 | 205 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 206 | the HAL_SDRAM_MspDeInit could be implemented in the user file |
mbed_official | 87:085cde657901 | 207 | */ |
mbed_official | 87:085cde657901 | 208 | } |
mbed_official | 87:085cde657901 | 209 | |
mbed_official | 87:085cde657901 | 210 | /** |
mbed_official | 87:085cde657901 | 211 | * @brief This function handles SDRAM refresh error interrupt request. |
mbed_official | 87:085cde657901 | 212 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 213 | * @retval HAL status |
mbed_official | 87:085cde657901 | 214 | */ |
mbed_official | 87:085cde657901 | 215 | void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 216 | { |
mbed_official | 87:085cde657901 | 217 | /* Check SDRAM interrupt Rising edge flag */ |
mbed_official | 87:085cde657901 | 218 | if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) |
mbed_official | 87:085cde657901 | 219 | { |
mbed_official | 87:085cde657901 | 220 | /* SDRAM refresh error interrupt callback */ |
mbed_official | 87:085cde657901 | 221 | HAL_SDRAM_RefreshErrorCallback(hsdram); |
mbed_official | 87:085cde657901 | 222 | |
mbed_official | 87:085cde657901 | 223 | /* Clear SDRAM refresh error interrupt pending bit */ |
mbed_official | 87:085cde657901 | 224 | __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); |
mbed_official | 87:085cde657901 | 225 | } |
mbed_official | 87:085cde657901 | 226 | } |
mbed_official | 87:085cde657901 | 227 | |
mbed_official | 87:085cde657901 | 228 | /** |
mbed_official | 87:085cde657901 | 229 | * @brief SDRAM Refresh error callback. |
mbed_official | 87:085cde657901 | 230 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 231 | * @retval None |
mbed_official | 87:085cde657901 | 232 | */ |
mbed_official | 87:085cde657901 | 233 | __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 234 | { |
mbed_official | 87:085cde657901 | 235 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 236 | the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file |
mbed_official | 87:085cde657901 | 237 | */ |
mbed_official | 87:085cde657901 | 238 | } |
mbed_official | 87:085cde657901 | 239 | |
mbed_official | 87:085cde657901 | 240 | /** |
mbed_official | 87:085cde657901 | 241 | * @brief DMA transfer complete callback. |
mbed_official | 87:085cde657901 | 242 | * @param hdma: DMA handle |
mbed_official | 87:085cde657901 | 243 | * @retval None |
mbed_official | 87:085cde657901 | 244 | */ |
mbed_official | 87:085cde657901 | 245 | __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) |
mbed_official | 87:085cde657901 | 246 | { |
mbed_official | 87:085cde657901 | 247 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 248 | the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file |
mbed_official | 87:085cde657901 | 249 | */ |
mbed_official | 87:085cde657901 | 250 | } |
mbed_official | 87:085cde657901 | 251 | |
mbed_official | 87:085cde657901 | 252 | /** |
mbed_official | 87:085cde657901 | 253 | * @brief DMA transfer complete error callback. |
mbed_official | 87:085cde657901 | 254 | * @param hdma: DMA handle |
mbed_official | 87:085cde657901 | 255 | * @retval None |
mbed_official | 87:085cde657901 | 256 | */ |
mbed_official | 87:085cde657901 | 257 | __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) |
mbed_official | 87:085cde657901 | 258 | { |
mbed_official | 87:085cde657901 | 259 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 260 | the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file |
mbed_official | 87:085cde657901 | 261 | */ |
mbed_official | 87:085cde657901 | 262 | } |
mbed_official | 87:085cde657901 | 263 | |
mbed_official | 87:085cde657901 | 264 | /** |
mbed_official | 87:085cde657901 | 265 | * @} |
mbed_official | 87:085cde657901 | 266 | */ |
mbed_official | 87:085cde657901 | 267 | |
mbed_official | 87:085cde657901 | 268 | /** @defgroup SDRAM_Group2 Input and Output functions |
mbed_official | 87:085cde657901 | 269 | * @brief Input Output and memory control functions |
mbed_official | 87:085cde657901 | 270 | * |
mbed_official | 87:085cde657901 | 271 | @verbatim |
mbed_official | 87:085cde657901 | 272 | ============================================================================== |
mbed_official | 87:085cde657901 | 273 | ##### SDRAM Input and Output functions ##### |
mbed_official | 87:085cde657901 | 274 | ============================================================================== |
mbed_official | 87:085cde657901 | 275 | [..] |
mbed_official | 87:085cde657901 | 276 | This section provides functions allowing to use and control the SDRAM memory |
mbed_official | 87:085cde657901 | 277 | |
mbed_official | 87:085cde657901 | 278 | @endverbatim |
mbed_official | 87:085cde657901 | 279 | * @{ |
mbed_official | 87:085cde657901 | 280 | */ |
mbed_official | 87:085cde657901 | 281 | |
mbed_official | 87:085cde657901 | 282 | /** |
mbed_official | 87:085cde657901 | 283 | * @brief Reads 8-bit data buffer from the SDRAM memory. |
mbed_official | 87:085cde657901 | 284 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 285 | * @param pAddress: Pointer to read start address |
mbed_official | 87:085cde657901 | 286 | * @param pDstBuffer: Pointer to destination buffer |
mbed_official | 87:085cde657901 | 287 | * @param BufferSize: Size of the buffer to read from memory |
mbed_official | 87:085cde657901 | 288 | * @retval HAL status |
mbed_official | 87:085cde657901 | 289 | */ |
mbed_official | 87:085cde657901 | 290 | HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) |
mbed_official | 87:085cde657901 | 291 | { |
mbed_official | 87:085cde657901 | 292 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; |
mbed_official | 87:085cde657901 | 293 | |
mbed_official | 87:085cde657901 | 294 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 295 | __HAL_LOCK(hsdram); |
mbed_official | 87:085cde657901 | 296 | |
mbed_official | 87:085cde657901 | 297 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 298 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 299 | { |
mbed_official | 87:085cde657901 | 300 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 301 | } |
mbed_official | 87:085cde657901 | 302 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
mbed_official | 87:085cde657901 | 303 | { |
mbed_official | 87:085cde657901 | 304 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 305 | } |
mbed_official | 87:085cde657901 | 306 | |
mbed_official | 87:085cde657901 | 307 | /* Read data from source */ |
mbed_official | 87:085cde657901 | 308 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 87:085cde657901 | 309 | { |
mbed_official | 87:085cde657901 | 310 | *pDstBuffer = *(__IO uint8_t *)pSdramAddress; |
mbed_official | 87:085cde657901 | 311 | pDstBuffer++; |
mbed_official | 87:085cde657901 | 312 | pSdramAddress++; |
mbed_official | 87:085cde657901 | 313 | } |
mbed_official | 87:085cde657901 | 314 | |
mbed_official | 87:085cde657901 | 315 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 316 | __HAL_UNLOCK(hsdram); |
mbed_official | 87:085cde657901 | 317 | |
mbed_official | 87:085cde657901 | 318 | return HAL_OK; |
mbed_official | 87:085cde657901 | 319 | } |
mbed_official | 87:085cde657901 | 320 | |
mbed_official | 87:085cde657901 | 321 | |
mbed_official | 87:085cde657901 | 322 | /** |
mbed_official | 87:085cde657901 | 323 | * @brief Writes 8-bit data buffer to SDRAM memory. |
mbed_official | 87:085cde657901 | 324 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 325 | * @param pAddress: Pointer to write start address |
mbed_official | 87:085cde657901 | 326 | * @param pSrcBuffer: Pointer to source buffer to write |
mbed_official | 87:085cde657901 | 327 | * @param BufferSize: Size of the buffer to write to memory |
mbed_official | 87:085cde657901 | 328 | * @retval HAL status |
mbed_official | 87:085cde657901 | 329 | */ |
mbed_official | 87:085cde657901 | 330 | HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) |
mbed_official | 87:085cde657901 | 331 | { |
mbed_official | 87:085cde657901 | 332 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; |
mbed_official | 87:085cde657901 | 333 | uint32_t tmp = 0; |
mbed_official | 87:085cde657901 | 334 | |
mbed_official | 87:085cde657901 | 335 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 336 | __HAL_LOCK(hsdram); |
mbed_official | 87:085cde657901 | 337 | |
mbed_official | 87:085cde657901 | 338 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 339 | tmp = hsdram->State; |
mbed_official | 87:085cde657901 | 340 | |
mbed_official | 87:085cde657901 | 341 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 342 | { |
mbed_official | 87:085cde657901 | 343 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 344 | } |
mbed_official | 87:085cde657901 | 345 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
mbed_official | 87:085cde657901 | 346 | { |
mbed_official | 87:085cde657901 | 347 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 348 | } |
mbed_official | 87:085cde657901 | 349 | |
mbed_official | 87:085cde657901 | 350 | /* Write data to memory */ |
mbed_official | 87:085cde657901 | 351 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 87:085cde657901 | 352 | { |
mbed_official | 87:085cde657901 | 353 | *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; |
mbed_official | 87:085cde657901 | 354 | pSrcBuffer++; |
mbed_official | 87:085cde657901 | 355 | pSdramAddress++; |
mbed_official | 87:085cde657901 | 356 | } |
mbed_official | 87:085cde657901 | 357 | |
mbed_official | 87:085cde657901 | 358 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 359 | __HAL_UNLOCK(hsdram); |
mbed_official | 87:085cde657901 | 360 | |
mbed_official | 87:085cde657901 | 361 | return HAL_OK; |
mbed_official | 87:085cde657901 | 362 | } |
mbed_official | 87:085cde657901 | 363 | |
mbed_official | 87:085cde657901 | 364 | |
mbed_official | 87:085cde657901 | 365 | /** |
mbed_official | 87:085cde657901 | 366 | * @brief Reads 16-bit data buffer from the SDRAM memory. |
mbed_official | 87:085cde657901 | 367 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 368 | * @param pAddress: Pointer to read start address |
mbed_official | 87:085cde657901 | 369 | * @param pDstBuffer: Pointer to destination buffer |
mbed_official | 87:085cde657901 | 370 | * @param BufferSize: Size of the buffer to read from memory |
mbed_official | 87:085cde657901 | 371 | * @retval HAL status |
mbed_official | 87:085cde657901 | 372 | */ |
mbed_official | 87:085cde657901 | 373 | HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) |
mbed_official | 87:085cde657901 | 374 | { |
mbed_official | 87:085cde657901 | 375 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; |
mbed_official | 87:085cde657901 | 376 | |
mbed_official | 87:085cde657901 | 377 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 378 | __HAL_LOCK(hsdram); |
mbed_official | 87:085cde657901 | 379 | |
mbed_official | 87:085cde657901 | 380 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 381 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 382 | { |
mbed_official | 87:085cde657901 | 383 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 384 | } |
mbed_official | 87:085cde657901 | 385 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
mbed_official | 87:085cde657901 | 386 | { |
mbed_official | 87:085cde657901 | 387 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 388 | } |
mbed_official | 87:085cde657901 | 389 | |
mbed_official | 87:085cde657901 | 390 | /* Read data from source */ |
mbed_official | 87:085cde657901 | 391 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 87:085cde657901 | 392 | { |
mbed_official | 87:085cde657901 | 393 | *pDstBuffer = *(__IO uint16_t *)pSdramAddress; |
mbed_official | 87:085cde657901 | 394 | pDstBuffer++; |
mbed_official | 87:085cde657901 | 395 | pSdramAddress++; |
mbed_official | 87:085cde657901 | 396 | } |
mbed_official | 87:085cde657901 | 397 | |
mbed_official | 87:085cde657901 | 398 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 399 | __HAL_UNLOCK(hsdram); |
mbed_official | 87:085cde657901 | 400 | |
mbed_official | 87:085cde657901 | 401 | return HAL_OK; |
mbed_official | 87:085cde657901 | 402 | } |
mbed_official | 87:085cde657901 | 403 | |
mbed_official | 87:085cde657901 | 404 | /** |
mbed_official | 87:085cde657901 | 405 | * @brief Writes 16-bit data buffer to SDRAM memory. |
mbed_official | 87:085cde657901 | 406 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 407 | * @param pAddress: Pointer to write start address |
mbed_official | 87:085cde657901 | 408 | * @param pSrcBuffer: Pointer to source buffer to write |
mbed_official | 87:085cde657901 | 409 | * @param BufferSize: Size of the buffer to write to memory |
mbed_official | 87:085cde657901 | 410 | * @retval HAL status |
mbed_official | 87:085cde657901 | 411 | */ |
mbed_official | 87:085cde657901 | 412 | HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) |
mbed_official | 87:085cde657901 | 413 | { |
mbed_official | 87:085cde657901 | 414 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; |
mbed_official | 87:085cde657901 | 415 | uint32_t tmp = 0; |
mbed_official | 87:085cde657901 | 416 | |
mbed_official | 87:085cde657901 | 417 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 418 | __HAL_LOCK(hsdram); |
mbed_official | 87:085cde657901 | 419 | |
mbed_official | 87:085cde657901 | 420 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 421 | tmp = hsdram->State; |
mbed_official | 87:085cde657901 | 422 | |
mbed_official | 87:085cde657901 | 423 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 424 | { |
mbed_official | 87:085cde657901 | 425 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 426 | } |
mbed_official | 87:085cde657901 | 427 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
mbed_official | 87:085cde657901 | 428 | { |
mbed_official | 87:085cde657901 | 429 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 430 | } |
mbed_official | 87:085cde657901 | 431 | |
mbed_official | 87:085cde657901 | 432 | /* Write data to memory */ |
mbed_official | 87:085cde657901 | 433 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 87:085cde657901 | 434 | { |
mbed_official | 87:085cde657901 | 435 | *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; |
mbed_official | 87:085cde657901 | 436 | pSrcBuffer++; |
mbed_official | 87:085cde657901 | 437 | pSdramAddress++; |
mbed_official | 87:085cde657901 | 438 | } |
mbed_official | 87:085cde657901 | 439 | |
mbed_official | 87:085cde657901 | 440 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 441 | __HAL_UNLOCK(hsdram); |
mbed_official | 87:085cde657901 | 442 | |
mbed_official | 87:085cde657901 | 443 | return HAL_OK; |
mbed_official | 87:085cde657901 | 444 | } |
mbed_official | 87:085cde657901 | 445 | |
mbed_official | 87:085cde657901 | 446 | /** |
mbed_official | 87:085cde657901 | 447 | * @brief Reads 32-bit data buffer from the SDRAM memory. |
mbed_official | 87:085cde657901 | 448 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 449 | * @param pAddress: Pointer to read start address |
mbed_official | 87:085cde657901 | 450 | * @param pDstBuffer: Pointer to destination buffer |
mbed_official | 87:085cde657901 | 451 | * @param BufferSize: Size of the buffer to read from memory |
mbed_official | 87:085cde657901 | 452 | * @retval HAL status |
mbed_official | 87:085cde657901 | 453 | */ |
mbed_official | 87:085cde657901 | 454 | HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) |
mbed_official | 87:085cde657901 | 455 | { |
mbed_official | 87:085cde657901 | 456 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; |
mbed_official | 87:085cde657901 | 457 | |
mbed_official | 87:085cde657901 | 458 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 459 | __HAL_LOCK(hsdram); |
mbed_official | 87:085cde657901 | 460 | |
mbed_official | 87:085cde657901 | 461 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 462 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 463 | { |
mbed_official | 87:085cde657901 | 464 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 465 | } |
mbed_official | 87:085cde657901 | 466 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
mbed_official | 87:085cde657901 | 467 | { |
mbed_official | 87:085cde657901 | 468 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 469 | } |
mbed_official | 87:085cde657901 | 470 | |
mbed_official | 87:085cde657901 | 471 | /* Read data from source */ |
mbed_official | 87:085cde657901 | 472 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 87:085cde657901 | 473 | { |
mbed_official | 87:085cde657901 | 474 | *pDstBuffer = *(__IO uint32_t *)pSdramAddress; |
mbed_official | 87:085cde657901 | 475 | pDstBuffer++; |
mbed_official | 87:085cde657901 | 476 | pSdramAddress++; |
mbed_official | 87:085cde657901 | 477 | } |
mbed_official | 87:085cde657901 | 478 | |
mbed_official | 87:085cde657901 | 479 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 480 | __HAL_UNLOCK(hsdram); |
mbed_official | 87:085cde657901 | 481 | |
mbed_official | 87:085cde657901 | 482 | return HAL_OK; |
mbed_official | 87:085cde657901 | 483 | } |
mbed_official | 87:085cde657901 | 484 | |
mbed_official | 87:085cde657901 | 485 | /** |
mbed_official | 87:085cde657901 | 486 | * @brief Writes 32-bit data buffer to SDRAM memory. |
mbed_official | 87:085cde657901 | 487 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 488 | * @param pAddress: Pointer to write start address |
mbed_official | 87:085cde657901 | 489 | * @param pSrcBuffer: Pointer to source buffer to write |
mbed_official | 87:085cde657901 | 490 | * @param BufferSize: Size of the buffer to write to memory |
mbed_official | 87:085cde657901 | 491 | * @retval HAL status |
mbed_official | 87:085cde657901 | 492 | */ |
mbed_official | 87:085cde657901 | 493 | HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) |
mbed_official | 87:085cde657901 | 494 | { |
mbed_official | 87:085cde657901 | 495 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; |
mbed_official | 87:085cde657901 | 496 | uint32_t tmp = 0; |
mbed_official | 87:085cde657901 | 497 | |
mbed_official | 87:085cde657901 | 498 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 499 | __HAL_LOCK(hsdram); |
mbed_official | 87:085cde657901 | 500 | |
mbed_official | 87:085cde657901 | 501 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 502 | tmp = hsdram->State; |
mbed_official | 87:085cde657901 | 503 | |
mbed_official | 87:085cde657901 | 504 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 505 | { |
mbed_official | 87:085cde657901 | 506 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 507 | } |
mbed_official | 87:085cde657901 | 508 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
mbed_official | 87:085cde657901 | 509 | { |
mbed_official | 87:085cde657901 | 510 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 511 | } |
mbed_official | 87:085cde657901 | 512 | |
mbed_official | 87:085cde657901 | 513 | /* Write data to memory */ |
mbed_official | 87:085cde657901 | 514 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 87:085cde657901 | 515 | { |
mbed_official | 87:085cde657901 | 516 | *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; |
mbed_official | 87:085cde657901 | 517 | pSrcBuffer++; |
mbed_official | 87:085cde657901 | 518 | pSdramAddress++; |
mbed_official | 87:085cde657901 | 519 | } |
mbed_official | 87:085cde657901 | 520 | |
mbed_official | 87:085cde657901 | 521 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 522 | __HAL_UNLOCK(hsdram); |
mbed_official | 87:085cde657901 | 523 | |
mbed_official | 87:085cde657901 | 524 | return HAL_OK; |
mbed_official | 87:085cde657901 | 525 | } |
mbed_official | 87:085cde657901 | 526 | |
mbed_official | 87:085cde657901 | 527 | /** |
mbed_official | 87:085cde657901 | 528 | * @brief Reads a Words data from the SDRAM memory using DMA transfer. |
mbed_official | 87:085cde657901 | 529 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 530 | * @param pAddress: Pointer to read start address |
mbed_official | 87:085cde657901 | 531 | * @param pDstBuffer: Pointer to destination buffer |
mbed_official | 87:085cde657901 | 532 | * @param BufferSize: Size of the buffer to read from memory |
mbed_official | 87:085cde657901 | 533 | * @retval HAL status |
mbed_official | 87:085cde657901 | 534 | */ |
mbed_official | 87:085cde657901 | 535 | HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) |
mbed_official | 87:085cde657901 | 536 | { |
mbed_official | 87:085cde657901 | 537 | uint32_t tmp = 0; |
mbed_official | 87:085cde657901 | 538 | |
mbed_official | 87:085cde657901 | 539 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 540 | __HAL_LOCK(hsdram); |
mbed_official | 87:085cde657901 | 541 | |
mbed_official | 87:085cde657901 | 542 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 543 | tmp = hsdram->State; |
mbed_official | 87:085cde657901 | 544 | |
mbed_official | 87:085cde657901 | 545 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 546 | { |
mbed_official | 87:085cde657901 | 547 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 548 | } |
mbed_official | 87:085cde657901 | 549 | else if(tmp == HAL_SDRAM_STATE_PRECHARGED) |
mbed_official | 87:085cde657901 | 550 | { |
mbed_official | 87:085cde657901 | 551 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 552 | } |
mbed_official | 87:085cde657901 | 553 | |
mbed_official | 87:085cde657901 | 554 | /* Configure DMA user callbacks */ |
mbed_official | 87:085cde657901 | 555 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; |
mbed_official | 87:085cde657901 | 556 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; |
mbed_official | 87:085cde657901 | 557 | |
mbed_official | 87:085cde657901 | 558 | /* Enable the DMA Stream */ |
mbed_official | 87:085cde657901 | 559 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); |
mbed_official | 87:085cde657901 | 560 | |
mbed_official | 87:085cde657901 | 561 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 562 | __HAL_UNLOCK(hsdram); |
mbed_official | 87:085cde657901 | 563 | |
mbed_official | 87:085cde657901 | 564 | return HAL_OK; |
mbed_official | 87:085cde657901 | 565 | } |
mbed_official | 87:085cde657901 | 566 | |
mbed_official | 87:085cde657901 | 567 | /** |
mbed_official | 87:085cde657901 | 568 | * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. |
mbed_official | 87:085cde657901 | 569 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 570 | * @param pAddress: Pointer to write start address |
mbed_official | 87:085cde657901 | 571 | * @param pSrcBuffer: Pointer to source buffer to write |
mbed_official | 87:085cde657901 | 572 | * @param BufferSize: Size of the buffer to write to memory |
mbed_official | 87:085cde657901 | 573 | * @retval HAL status |
mbed_official | 87:085cde657901 | 574 | */ |
mbed_official | 87:085cde657901 | 575 | HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) |
mbed_official | 87:085cde657901 | 576 | { |
mbed_official | 87:085cde657901 | 577 | uint32_t tmp = 0; |
mbed_official | 87:085cde657901 | 578 | |
mbed_official | 87:085cde657901 | 579 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 580 | __HAL_LOCK(hsdram); |
mbed_official | 87:085cde657901 | 581 | |
mbed_official | 87:085cde657901 | 582 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 583 | tmp = hsdram->State; |
mbed_official | 87:085cde657901 | 584 | |
mbed_official | 87:085cde657901 | 585 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 586 | { |
mbed_official | 87:085cde657901 | 587 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 588 | } |
mbed_official | 87:085cde657901 | 589 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
mbed_official | 87:085cde657901 | 590 | { |
mbed_official | 87:085cde657901 | 591 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 592 | } |
mbed_official | 87:085cde657901 | 593 | |
mbed_official | 87:085cde657901 | 594 | /* Configure DMA user callbacks */ |
mbed_official | 87:085cde657901 | 595 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; |
mbed_official | 87:085cde657901 | 596 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; |
mbed_official | 87:085cde657901 | 597 | |
mbed_official | 87:085cde657901 | 598 | /* Enable the DMA Stream */ |
mbed_official | 87:085cde657901 | 599 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); |
mbed_official | 87:085cde657901 | 600 | |
mbed_official | 87:085cde657901 | 601 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 602 | __HAL_UNLOCK(hsdram); |
mbed_official | 87:085cde657901 | 603 | |
mbed_official | 87:085cde657901 | 604 | return HAL_OK; |
mbed_official | 87:085cde657901 | 605 | } |
mbed_official | 87:085cde657901 | 606 | |
mbed_official | 87:085cde657901 | 607 | /** |
mbed_official | 87:085cde657901 | 608 | * @} |
mbed_official | 87:085cde657901 | 609 | */ |
mbed_official | 87:085cde657901 | 610 | |
mbed_official | 87:085cde657901 | 611 | /** @defgroup SDRAM_Group3 Control functions |
mbed_official | 87:085cde657901 | 612 | * @brief management functions |
mbed_official | 87:085cde657901 | 613 | * |
mbed_official | 87:085cde657901 | 614 | @verbatim |
mbed_official | 87:085cde657901 | 615 | ============================================================================== |
mbed_official | 87:085cde657901 | 616 | ##### SDRAM Control functions ##### |
mbed_official | 87:085cde657901 | 617 | ============================================================================== |
mbed_official | 87:085cde657901 | 618 | [..] |
mbed_official | 87:085cde657901 | 619 | This subsection provides a set of functions allowing to control dynamically |
mbed_official | 87:085cde657901 | 620 | the SDRAM interface. |
mbed_official | 87:085cde657901 | 621 | |
mbed_official | 87:085cde657901 | 622 | @endverbatim |
mbed_official | 87:085cde657901 | 623 | * @{ |
mbed_official | 87:085cde657901 | 624 | */ |
mbed_official | 87:085cde657901 | 625 | |
mbed_official | 87:085cde657901 | 626 | /** |
mbed_official | 87:085cde657901 | 627 | * @brief Enables dynamically SDRAM write protection. |
mbed_official | 87:085cde657901 | 628 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 629 | * @retval HAL status |
mbed_official | 87:085cde657901 | 630 | */ |
mbed_official | 87:085cde657901 | 631 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 632 | { |
mbed_official | 87:085cde657901 | 633 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 634 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 635 | { |
mbed_official | 87:085cde657901 | 636 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 637 | } |
mbed_official | 87:085cde657901 | 638 | |
mbed_official | 87:085cde657901 | 639 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 640 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 87:085cde657901 | 641 | |
mbed_official | 87:085cde657901 | 642 | /* Enable write protection */ |
mbed_official | 87:085cde657901 | 643 | FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); |
mbed_official | 87:085cde657901 | 644 | |
mbed_official | 87:085cde657901 | 645 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 646 | hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; |
mbed_official | 87:085cde657901 | 647 | |
mbed_official | 87:085cde657901 | 648 | return HAL_OK; |
mbed_official | 87:085cde657901 | 649 | } |
mbed_official | 87:085cde657901 | 650 | |
mbed_official | 87:085cde657901 | 651 | /** |
mbed_official | 87:085cde657901 | 652 | * @brief Disables dynamically SDRAM write protection. |
mbed_official | 87:085cde657901 | 653 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 654 | * @retval HAL status |
mbed_official | 87:085cde657901 | 655 | */ |
mbed_official | 87:085cde657901 | 656 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 657 | { |
mbed_official | 87:085cde657901 | 658 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 659 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 660 | { |
mbed_official | 87:085cde657901 | 661 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 662 | } |
mbed_official | 87:085cde657901 | 663 | |
mbed_official | 87:085cde657901 | 664 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 665 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 87:085cde657901 | 666 | |
mbed_official | 87:085cde657901 | 667 | /* Disable write protection */ |
mbed_official | 87:085cde657901 | 668 | FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); |
mbed_official | 87:085cde657901 | 669 | |
mbed_official | 87:085cde657901 | 670 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 671 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 87:085cde657901 | 672 | |
mbed_official | 87:085cde657901 | 673 | return HAL_OK; |
mbed_official | 87:085cde657901 | 674 | } |
mbed_official | 87:085cde657901 | 675 | |
mbed_official | 87:085cde657901 | 676 | /** |
mbed_official | 87:085cde657901 | 677 | * @brief Sends Command to the SDRAM bank. |
mbed_official | 87:085cde657901 | 678 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 679 | * @param Command: SDRAM command structure |
mbed_official | 87:085cde657901 | 680 | * @param Timeout: Timeout duration |
mbed_official | 87:085cde657901 | 681 | * @retval HAL state |
mbed_official | 87:085cde657901 | 682 | */ |
mbed_official | 87:085cde657901 | 683 | HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) |
mbed_official | 87:085cde657901 | 684 | { |
mbed_official | 87:085cde657901 | 685 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 686 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 687 | { |
mbed_official | 87:085cde657901 | 688 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 689 | } |
mbed_official | 87:085cde657901 | 690 | |
mbed_official | 87:085cde657901 | 691 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 692 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 87:085cde657901 | 693 | |
mbed_official | 87:085cde657901 | 694 | /* Send SDRAM command */ |
mbed_official | 87:085cde657901 | 695 | FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); |
mbed_official | 87:085cde657901 | 696 | |
mbed_official | 87:085cde657901 | 697 | /* Update the SDRAM controller state state */ |
mbed_official | 87:085cde657901 | 698 | if(Command->CommandMode == FMC_SDRAM_CMD_PALL) |
mbed_official | 87:085cde657901 | 699 | { |
mbed_official | 87:085cde657901 | 700 | hsdram->State = HAL_SDRAM_STATE_PRECHARGED; |
mbed_official | 87:085cde657901 | 701 | } |
mbed_official | 87:085cde657901 | 702 | else |
mbed_official | 87:085cde657901 | 703 | { |
mbed_official | 87:085cde657901 | 704 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 87:085cde657901 | 705 | } |
mbed_official | 87:085cde657901 | 706 | |
mbed_official | 87:085cde657901 | 707 | return HAL_OK; |
mbed_official | 87:085cde657901 | 708 | } |
mbed_official | 87:085cde657901 | 709 | |
mbed_official | 87:085cde657901 | 710 | /** |
mbed_official | 87:085cde657901 | 711 | * @brief Programs the SDRAM Memory Refresh rate. |
mbed_official | 87:085cde657901 | 712 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 713 | * @param RefreshRate: The SDRAM refresh rate value |
mbed_official | 87:085cde657901 | 714 | * @retval HAL state |
mbed_official | 87:085cde657901 | 715 | */ |
mbed_official | 87:085cde657901 | 716 | HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) |
mbed_official | 87:085cde657901 | 717 | { |
mbed_official | 87:085cde657901 | 718 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 719 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 720 | { |
mbed_official | 87:085cde657901 | 721 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 722 | } |
mbed_official | 87:085cde657901 | 723 | |
mbed_official | 87:085cde657901 | 724 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 725 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 87:085cde657901 | 726 | |
mbed_official | 87:085cde657901 | 727 | /* Program the refresh rate */ |
mbed_official | 87:085cde657901 | 728 | FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); |
mbed_official | 87:085cde657901 | 729 | |
mbed_official | 87:085cde657901 | 730 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 731 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 87:085cde657901 | 732 | |
mbed_official | 87:085cde657901 | 733 | return HAL_OK; |
mbed_official | 87:085cde657901 | 734 | } |
mbed_official | 87:085cde657901 | 735 | |
mbed_official | 87:085cde657901 | 736 | /** |
mbed_official | 87:085cde657901 | 737 | * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. |
mbed_official | 87:085cde657901 | 738 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 739 | * @param AutoRefreshNumber: The SDRAM auto Refresh number |
mbed_official | 87:085cde657901 | 740 | * @retval None |
mbed_official | 87:085cde657901 | 741 | */ |
mbed_official | 87:085cde657901 | 742 | HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) |
mbed_official | 87:085cde657901 | 743 | { |
mbed_official | 87:085cde657901 | 744 | /* Check the SDRAM controller state */ |
mbed_official | 87:085cde657901 | 745 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 87:085cde657901 | 746 | { |
mbed_official | 87:085cde657901 | 747 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 748 | } |
mbed_official | 87:085cde657901 | 749 | |
mbed_official | 87:085cde657901 | 750 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 751 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 87:085cde657901 | 752 | |
mbed_official | 87:085cde657901 | 753 | /* Set the Auto-Refresh number */ |
mbed_official | 87:085cde657901 | 754 | FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); |
mbed_official | 87:085cde657901 | 755 | |
mbed_official | 87:085cde657901 | 756 | /* Update the SDRAM state */ |
mbed_official | 87:085cde657901 | 757 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 87:085cde657901 | 758 | |
mbed_official | 87:085cde657901 | 759 | return HAL_OK; |
mbed_official | 87:085cde657901 | 760 | } |
mbed_official | 87:085cde657901 | 761 | |
mbed_official | 87:085cde657901 | 762 | /** |
mbed_official | 87:085cde657901 | 763 | * @brief Returns the SDRAM memory current mode. |
mbed_official | 87:085cde657901 | 764 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 765 | * @retval The SDRAM memory mode. |
mbed_official | 87:085cde657901 | 766 | */ |
mbed_official | 87:085cde657901 | 767 | uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 768 | { |
mbed_official | 87:085cde657901 | 769 | /* Return the SDRAM memory current mode */ |
mbed_official | 87:085cde657901 | 770 | return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); |
mbed_official | 87:085cde657901 | 771 | } |
mbed_official | 87:085cde657901 | 772 | |
mbed_official | 87:085cde657901 | 773 | /** |
mbed_official | 87:085cde657901 | 774 | * @} |
mbed_official | 87:085cde657901 | 775 | */ |
mbed_official | 87:085cde657901 | 776 | |
mbed_official | 87:085cde657901 | 777 | /** @defgroup SDRAM_Group4 State functions |
mbed_official | 87:085cde657901 | 778 | * @brief Peripheral State functions |
mbed_official | 87:085cde657901 | 779 | * |
mbed_official | 87:085cde657901 | 780 | @verbatim |
mbed_official | 87:085cde657901 | 781 | ============================================================================== |
mbed_official | 87:085cde657901 | 782 | ##### SDRAM State functions ##### |
mbed_official | 87:085cde657901 | 783 | ============================================================================== |
mbed_official | 87:085cde657901 | 784 | [..] |
mbed_official | 87:085cde657901 | 785 | This subsection permits to get in run-time the status of the SDRAM controller |
mbed_official | 87:085cde657901 | 786 | and the data flow. |
mbed_official | 87:085cde657901 | 787 | |
mbed_official | 87:085cde657901 | 788 | @endverbatim |
mbed_official | 87:085cde657901 | 789 | * @{ |
mbed_official | 87:085cde657901 | 790 | */ |
mbed_official | 87:085cde657901 | 791 | |
mbed_official | 87:085cde657901 | 792 | /** |
mbed_official | 87:085cde657901 | 793 | * @brief Returns the SDRAM state. |
mbed_official | 87:085cde657901 | 794 | * @param hsdram: SDRAM handle |
mbed_official | 87:085cde657901 | 795 | * @retval HAL state |
mbed_official | 87:085cde657901 | 796 | */ |
mbed_official | 87:085cde657901 | 797 | HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 87:085cde657901 | 798 | { |
mbed_official | 87:085cde657901 | 799 | return hsdram->State; |
mbed_official | 87:085cde657901 | 800 | } |
mbed_official | 87:085cde657901 | 801 | |
mbed_official | 87:085cde657901 | 802 | /** |
mbed_official | 87:085cde657901 | 803 | * @} |
mbed_official | 87:085cde657901 | 804 | */ |
mbed_official | 87:085cde657901 | 805 | |
mbed_official | 87:085cde657901 | 806 | /** |
mbed_official | 87:085cde657901 | 807 | * @} |
mbed_official | 87:085cde657901 | 808 | */ |
mbed_official | 87:085cde657901 | 809 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
mbed_official | 87:085cde657901 | 810 | #endif /* HAL_SDRAM_MODULE_ENABLED */ |
mbed_official | 87:085cde657901 | 811 | /** |
mbed_official | 87:085cde657901 | 812 | * @} |
mbed_official | 87:085cde657901 | 813 | */ |
mbed_official | 87:085cde657901 | 814 | |
mbed_official | 87:085cde657901 | 815 | /** |
mbed_official | 87:085cde657901 | 816 | * @} |
mbed_official | 87:085cde657901 | 817 | */ |
mbed_official | 87:085cde657901 | 818 | |
mbed_official | 87:085cde657901 | 819 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |