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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.c@87:085cde657901, 2014-02-08 (annotated)

Committer:: mbed_official
Date:: Sat Feb 08 19:45:06 2014 +0000
Revision:: 87:085cde657901
Child:: 106:ced8cbb51063

Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2

Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/

Add NUCLEO_F401RE, improvements

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_rcc.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	87:085cde657901	5	* @version V1.0.0RC2
mbed_official	87:085cde657901	6	* @date 04-February-2014
mbed_official	87:085cde657901	7	* @brief RCC HAL module driver.
mbed_official	87:085cde657901	8	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	9	* functionalities of the Reset and Clock Control (RCC) peripheral:
mbed_official	87:085cde657901	10	* + Initialization and de-initialization functions
mbed_official	87:085cde657901	11	* + Peripheral Control functions
mbed_official	87:085cde657901	12	*
mbed_official	87:085cde657901	13	@verbatim
mbed_official	87:085cde657901	14	==============================================================================
mbed_official	87:085cde657901	15	##### RCC specific features #####
mbed_official	87:085cde657901	16	==============================================================================
mbed_official	87:085cde657901	17	[..]
mbed_official	87:085cde657901	18	After reset the device is running from Internal High Speed oscillator
mbed_official	87:085cde657901	19	(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
mbed_official	87:085cde657901	20	and I-Cache are disabled, and all peripherals are off except internal
mbed_official	87:085cde657901	21	SRAM, Flash and JTAG.
mbed_official	87:085cde657901	22	(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official	87:085cde657901	23	all peripherals mapped on these busses are running at HSI speed.
mbed_official	87:085cde657901	24	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official	87:085cde657901	25	(+) All GPIOs are in input floating state, except the JTAG pins which
mbed_official	87:085cde657901	26	are assigned to be used for debug purpose.
mbed_official	87:085cde657901	27
mbed_official	87:085cde657901	28	[..]
mbed_official	87:085cde657901	29	Once the device started from reset, the user application has to:
mbed_official	87:085cde657901	30	(+) Configure the clock source to be used to drive the System clock
mbed_official	87:085cde657901	31	(if the application needs higher frequency/performance)
mbed_official	87:085cde657901	32	(+) Configure the System clock frequency and Flash settings
mbed_official	87:085cde657901	33	(+) Configure the AHB and APB busses prescalers
mbed_official	87:085cde657901	34	(+) Enable the clock for the peripheral(s) to be used
mbed_official	87:085cde657901	35	(+) Configure the clock source(s) for peripherals which clocks are not
mbed_official	87:085cde657901	36	derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
mbed_official	87:085cde657901	37
mbed_official	87:085cde657901	38	@endverbatim
mbed_official	87:085cde657901	39	******************************************************************************
mbed_official	87:085cde657901	40	* @attention
mbed_official	87:085cde657901	41	*
mbed_official	87:085cde657901	42	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	43	*
mbed_official	87:085cde657901	44	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	45	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	46	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	47	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	48	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	49	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	50	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	51	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	52	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	53	* without specific prior written permission.
mbed_official	87:085cde657901	54	*
mbed_official	87:085cde657901	55	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	56	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	57	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	58	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	59	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	60	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	61	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	62	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	63	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	64	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	65	*
mbed_official	87:085cde657901	66	******************************************************************************
mbed_official	87:085cde657901	67	*/
mbed_official	87:085cde657901	68
mbed_official	87:085cde657901	69	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	70	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	71
mbed_official	87:085cde657901	72	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	73	* @{
mbed_official	87:085cde657901	74	*/
mbed_official	87:085cde657901	75
mbed_official	87:085cde657901	76	/** @defgroup RCC
mbed_official	87:085cde657901	77	* @brief RCC HAL module driver
mbed_official	87:085cde657901	78	* @{
mbed_official	87:085cde657901	79	*/
mbed_official	87:085cde657901	80
mbed_official	87:085cde657901	81	#ifdef HAL_RCC_MODULE_ENABLED
mbed_official	87:085cde657901	82
mbed_official	87:085cde657901	83	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	84	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	85	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	87:085cde657901	86	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	87:085cde657901	87	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	87:085cde657901	88	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	87:085cde657901	89	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	87:085cde657901	90	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	87:085cde657901	91
mbed_official	87:085cde657901	92	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	93	#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE()
mbed_official	87:085cde657901	94	#define MCO1_GPIO_PORT GPIOA
mbed_official	87:085cde657901	95	#define MCO1_PIN GPIO_PIN_8
mbed_official	87:085cde657901	96
mbed_official	87:085cde657901	97	#define __MCO2_CLK_ENABLE() __GPIOC_CLK_ENABLE()
mbed_official	87:085cde657901	98	#define MCO2_GPIO_PORT GPIOC
mbed_official	87:085cde657901	99	#define MCO2_PIN GPIO_PIN_9
mbed_official	87:085cde657901	100
mbed_official	87:085cde657901	101	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	102	const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	87:085cde657901	103
mbed_official	87:085cde657901	104	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	105	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	106
mbed_official	87:085cde657901	107	/** @defgroup RCC_Private_Functions
mbed_official	87:085cde657901	108	* @{
mbed_official	87:085cde657901	109	*/
mbed_official	87:085cde657901	110
mbed_official	87:085cde657901	111	/** @defgroup RCC_Group1 Initialization and de-initialization functions
mbed_official	87:085cde657901	112	* @brief Initialization and Configuration functions
mbed_official	87:085cde657901	113	*
mbed_official	87:085cde657901	114	@verbatim
mbed_official	87:085cde657901	115	===============================================================================
mbed_official	87:085cde657901	116	##### Initialization and de-initialization functions #####
mbed_official	87:085cde657901	117	===============================================================================
mbed_official	87:085cde657901	118	[..]
mbed_official	87:085cde657901	119	This section provide functions allowing to configure the internal/external oscillators
mbed_official	87:085cde657901	120	(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
mbed_official	87:085cde657901	121	and APB2).
mbed_official	87:085cde657901	122
mbed_official	87:085cde657901	123	[..] Internal/external clock and PLL configuration
mbed_official	87:085cde657901	124	(#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
mbed_official	87:085cde657901	125	the PLL as System clock source.
mbed_official	87:085cde657901	126
mbed_official	87:085cde657901	127	(#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
mbed_official	87:085cde657901	128	clock source.
mbed_official	87:085cde657901	129
mbed_official	87:085cde657901	130	(#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
mbed_official	87:085cde657901	131	through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official	87:085cde657901	132
mbed_official	87:085cde657901	133	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official	87:085cde657901	134
mbed_official	87:085cde657901	135	(#) PLL (clocked by HSI or HSE), featuring two different output clocks:
mbed_official	87:085cde657901	136	(++) The first output is used to generate the high speed system clock (up to 168 MHz)
mbed_official	87:085cde657901	137	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
mbed_official	87:085cde657901	138	the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
mbed_official	87:085cde657901	139
mbed_official	87:085cde657901	140	(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
mbed_official	87:085cde657901	141	and if a HSE clock failure occurs(HSE used directly or through PLL as System
mbed_official	87:085cde657901	142	clock source), the System clockis automatically switched to HSI and an interrupt
mbed_official	87:085cde657901	143	is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
mbed_official	87:085cde657901	144	(Non-Maskable Interrupt) exception vector.
mbed_official	87:085cde657901	145
mbed_official	87:085cde657901	146	(#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
mbed_official	87:085cde657901	147	clock (through a configurable prescaler) on PA8 pin.
mbed_official	87:085cde657901	148
mbed_official	87:085cde657901	149	(#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
mbed_official	87:085cde657901	150	clock (through a configurable prescaler) on PC9 pin.
mbed_official	87:085cde657901	151
mbed_official	87:085cde657901	152	[..] System, AHB and APB busses clocks configuration
mbed_official	87:085cde657901	153	(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official	87:085cde657901	154	HSE and PLL.
mbed_official	87:085cde657901	155	The AHB clock (HCLK) is derived from System clock through configurable
mbed_official	87:085cde657901	156	prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official	87:085cde657901	157	on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
mbed_official	87:085cde657901	158	from AHB clock through configurable prescalers and used to clock
mbed_official	87:085cde657901	159	the peripherals mapped on these busses. You can use
mbed_official	87:085cde657901	160	"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
mbed_official	87:085cde657901	161
mbed_official	87:085cde657901	162	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
mbed_official	87:085cde657901	163	(+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
mbed_official	87:085cde657901	164	from an external clock mapped on the I2S_CKIN pin.
mbed_official	87:085cde657901	165	You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
mbed_official	87:085cde657901	166	(+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
mbed_official	87:085cde657901	167	from an external clock mapped on the I2S_CKIN pin.
mbed_official	87:085cde657901	168	You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
mbed_official	87:085cde657901	169	(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
mbed_official	87:085cde657901	170	divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
mbed_official	87:085cde657901	171	macros to configure this clock.
mbed_official	87:085cde657901	172	(+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
mbed_official	87:085cde657901	173	to work correctly, while the SDIO require a frequency equal or lower than
mbed_official	87:085cde657901	174	to 48. This clock is derived of the main PLL through PLLQ divider.
mbed_official	87:085cde657901	175	(+@) IWDG clock which is always the LSI clock.
mbed_official	87:085cde657901	176
mbed_official	87:085cde657901	177	(#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
mbed_official	87:085cde657901	178	frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
mbed_official	87:085cde657901	179	Depending on the device voltage range, the maximum frequency should
mbed_official	87:085cde657901	180	be adapted accordingly:
mbed_official	87:085cde657901	181	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	182	\| Latency \| HCLK clock frequency (MHz) \|
mbed_official	87:085cde657901	183	\| \|---------------------------------------------------------------------\|
mbed_official	87:085cde657901	184	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
mbed_official	87:085cde657901	185	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
mbed_official	87:085cde657901	186	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	187	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
mbed_official	87:085cde657901	188	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	189	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
mbed_official	87:085cde657901	190	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	191	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
mbed_official	87:085cde657901	192	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	193	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|66 < HCLK <= 88 \|60 < HCLK <= 80 \|
mbed_official	87:085cde657901	194	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	195	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|88 < HCLK <= 110 \|80 < HCLK <= 100 \|
mbed_official	87:085cde657901	196	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	197	\|5WS(6CPU cycle)\|150< HCLK <= 168\|120< HCLK <= 144\|110 < HCLK <= 132\|100 < HCLK <= 120\|
mbed_official	87:085cde657901	198	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	199	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|132 < HCLK <= 154\|120 < HCLK <= 140\|
mbed_official	87:085cde657901	200	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	201	\|7WS(8CPU cycle)\| NA \| NA \|154 < HCLK <= 168\|140 < HCLK <= 160\|
mbed_official	87:085cde657901	202	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	203	(#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
mbed_official	87:085cde657901	204	of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
mbed_official	87:085cde657901	205	Depending on the device voltage range, the maximum frequency should
mbed_official	87:085cde657901	206	be adapted accordingly:
mbed_official	87:085cde657901	207	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	208	\| Latency \| HCLK clock frequency (MHz) \|
mbed_official	87:085cde657901	209	\| \|---------------------------------------------------------------------\|
mbed_official	87:085cde657901	210	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
mbed_official	87:085cde657901	211	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
mbed_official	87:085cde657901	212	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	213	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
mbed_official	87:085cde657901	214	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	215	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
mbed_official	87:085cde657901	216	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	217	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
mbed_official	87:085cde657901	218	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	219	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|66 < HCLK <= 88 \|60 < HCLK <= 80 \|
mbed_official	87:085cde657901	220	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	221	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|88 < HCLK <= 110 \|80 < HCLK <= 100 \|
mbed_official	87:085cde657901	222	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	223	\|5WS(6CPU cycle)\|150< HCLK <= 180\|120< HCLK <= 144\|110 < HCLK <= 132\|100 < HCLK <= 120\|
mbed_official	87:085cde657901	224	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	225	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|132 < HCLK <= 154\|120 < HCLK <= 140\|
mbed_official	87:085cde657901	226	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	227	\|7WS(8CPU cycle)\| NA \|168< HCLK <= 180\|154 < HCLK <= 176\|140 < HCLK <= 160\|
mbed_official	87:085cde657901	228	\|-------------------------------------------------------------------------------------\|
mbed_official	87:085cde657901	229	\|8WS(9CPU cycle)\| NA \| NA \|176 < HCLK <= 180\|160 < HCLK <= 180\|
mbed_official	87:085cde657901	230	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	231	(#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
mbed_official	87:085cde657901	232	PCLK2 84 MHz and PCLK1 42 MHz.
mbed_official	87:085cde657901	233	Depending on the device voltage range, the maximum frequency should
mbed_official	87:085cde657901	234	be adapted accordingly:
mbed_official	87:085cde657901	235	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	236	\| Latency \| HCLK clock frequency (MHz) \|
mbed_official	87:085cde657901	237	\| \|---------------------------------------------------------------------\|
mbed_official	87:085cde657901	238	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
mbed_official	87:085cde657901	239	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
mbed_official	87:085cde657901	240	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	241	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
mbed_official	87:085cde657901	242	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	243	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
mbed_official	87:085cde657901	244	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	245	\|2WS(3CPU cycle)\|60 < HCLK <= 84 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
mbed_official	87:085cde657901	246	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	247	\|3WS(4CPU cycle)\| NA \|72 < HCLK <= 84 \|66 < HCLK <= 84 \|60 < HCLK <= 80 \|
mbed_official	87:085cde657901	248	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	249	\|4WS(5CPU cycle)\| NA \| NA \| NA \|80 < HCLK <= 84 \|
mbed_official	87:085cde657901	250	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	251	@endverbatim
mbed_official	87:085cde657901	252	* @{
mbed_official	87:085cde657901	253	*/
mbed_official	87:085cde657901	254
mbed_official	87:085cde657901	255	/**
mbed_official	87:085cde657901	256	* @brief Resets the RCC clock configuration to the default reset state.
mbed_official	87:085cde657901	257	* @note The default reset state of the clock configuration is given below:
mbed_official	87:085cde657901	258	* - HSI ON and used as system clock source
mbed_official	87:085cde657901	259	* - HSE, PLL and PLLI2S OFF
mbed_official	87:085cde657901	260	* - AHB, APB1 and APB2 prescaler set to 1.
mbed_official	87:085cde657901	261	* - CSS, MCO1 and MCO2 OFF
mbed_official	87:085cde657901	262	* - All interrupts disabled
mbed_official	87:085cde657901	263	* @note This function doesn't modify the configuration of the
mbed_official	87:085cde657901	264	* - Peripheral clocks
mbed_official	87:085cde657901	265	* - LSI, LSE and RTC clocks
mbed_official	87:085cde657901	266	* @param None
mbed_official	87:085cde657901	267	* @retval None
mbed_official	87:085cde657901	268	*/
mbed_official	87:085cde657901	269	void HAL_RCC_DeInit(void)
mbed_official	87:085cde657901	270	{
mbed_official	87:085cde657901	271	/* Set HSION bit */
mbed_official	87:085cde657901	272	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
mbed_official	87:085cde657901	273
mbed_official	87:085cde657901	274	/* Reset CFGR register */
mbed_official	87:085cde657901	275	CLEAR_REG(RCC->CFGR);
mbed_official	87:085cde657901	276
mbed_official	87:085cde657901	277	/* Reset HSEON, CSSON, PLLON, PLLI2S */
mbed_official	87:085cde657901	278	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON \| RCC_CR_PLLON\| RCC_CR_PLLI2SON);
mbed_official	87:085cde657901	279
mbed_official	87:085cde657901	280	/* Reset PLLCFGR register */
mbed_official	87:085cde657901	281	CLEAR_REG(RCC->PLLCFGR);
mbed_official	87:085cde657901	282	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2);
mbed_official	87:085cde657901	283
mbed_official	87:085cde657901	284	/* Reset PLLI2SCFGR register */
mbed_official	87:085cde657901	285	CLEAR_REG(RCC->PLLI2SCFGR);
mbed_official	87:085cde657901	286	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1);
mbed_official	87:085cde657901	287
mbed_official	87:085cde657901	288	/* Reset HSEBYP bit */
mbed_official	87:085cde657901	289	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official	87:085cde657901	290
mbed_official	87:085cde657901	291	/* Disable all interrupts */
mbed_official	87:085cde657901	292	CLEAR_REG(RCC->CIR);
mbed_official	87:085cde657901	293	}
mbed_official	87:085cde657901	294
mbed_official	87:085cde657901	295	/**
mbed_official	87:085cde657901	296	* @brief Initializes the RCC Oscillators according to the specified parameters in the
mbed_official	87:085cde657901	297	* RCC_OscInitTypeDef.
mbed_official	87:085cde657901	298	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	87:085cde657901	299	* contains the configuration information for the RCC Oscillators.
mbed_official	87:085cde657901	300	* @note The PLL is not disabled when used as system clock.
mbed_official	87:085cde657901	301	* @retval HAL status
mbed_official	87:085cde657901	302	*/
mbed_official	87:085cde657901	303	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official	87:085cde657901	304	{
mbed_official	87:085cde657901	305
mbed_official	87:085cde657901	306	uint32_t timeout = 0;
mbed_official	87:085cde657901	307
mbed_official	87:085cde657901	308	/* Check the parameters */
mbed_official	87:085cde657901	309	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
mbed_official	87:085cde657901	310	/------------------------------- HSE Configuration ------------------------/
mbed_official	87:085cde657901	311	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
mbed_official	87:085cde657901	312	{
mbed_official	87:085cde657901	313	/* Check the parameters */
mbed_official	87:085cde657901	314	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
mbed_official	87:085cde657901	315	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
mbed_official	87:085cde657901	316	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
mbed_official	87:085cde657901	317	{
mbed_official	87:085cde657901	318	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
mbed_official	87:085cde657901	319	{
mbed_official	87:085cde657901	320	return HAL_ERROR;
mbed_official	87:085cde657901	321	}
mbed_official	87:085cde657901	322	}
mbed_official	87:085cde657901	323	else
mbed_official	87:085cde657901	324	{
mbed_official	87:085cde657901	325	/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
mbed_official	87:085cde657901	326	__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
mbed_official	87:085cde657901	327
mbed_official	87:085cde657901	328	/* Get timeout */
mbed_official	87:085cde657901	329	timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	330
mbed_official	87:085cde657901	331	/* Wait till HSE is disabled */
mbed_official	87:085cde657901	332	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official	87:085cde657901	333	{
mbed_official	87:085cde657901	334	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	335	{
mbed_official	87:085cde657901	336	return HAL_TIMEOUT;
mbed_official	87:085cde657901	337	}
mbed_official	87:085cde657901	338	}
mbed_official	87:085cde657901	339
mbed_official	87:085cde657901	340	/* Set the new HSE configuration ---------------------------------------*/
mbed_official	87:085cde657901	341	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
mbed_official	87:085cde657901	342
mbed_official	87:085cde657901	343	/* Check the HSE State */
mbed_official	87:085cde657901	344	if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
mbed_official	87:085cde657901	345	{
mbed_official	87:085cde657901	346	/* Get timeout */
mbed_official	87:085cde657901	347	timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	348
mbed_official	87:085cde657901	349	/* Wait till HSE is ready */
mbed_official	87:085cde657901	350	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	87:085cde657901	351	{
mbed_official	87:085cde657901	352	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	353	{
mbed_official	87:085cde657901	354	return HAL_TIMEOUT;
mbed_official	87:085cde657901	355	}
mbed_official	87:085cde657901	356	}
mbed_official	87:085cde657901	357	}
mbed_official	87:085cde657901	358	else
mbed_official	87:085cde657901	359	{
mbed_official	87:085cde657901	360	/* Get timeout */
mbed_official	87:085cde657901	361	timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	362
mbed_official	87:085cde657901	363	/* Wait till HSE is bypassed or disabled */
mbed_official	87:085cde657901	364	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official	87:085cde657901	365	{
mbed_official	87:085cde657901	366	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	367	{
mbed_official	87:085cde657901	368	return HAL_TIMEOUT;
mbed_official	87:085cde657901	369	}
mbed_official	87:085cde657901	370	}
mbed_official	87:085cde657901	371	}
mbed_official	87:085cde657901	372	}
mbed_official	87:085cde657901	373	}
mbed_official	87:085cde657901	374	/----------------------------- HSI Configuration --------------------------/
mbed_official	87:085cde657901	375	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
mbed_official	87:085cde657901	376	{
mbed_official	87:085cde657901	377	/* Check the parameters */
mbed_official	87:085cde657901	378	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
mbed_official	87:085cde657901	379	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
mbed_official	87:085cde657901	380
mbed_official	87:085cde657901	381	/* When the HSI is used as system clock it will not disabled */
mbed_official	87:085cde657901	382	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
mbed_official	87:085cde657901	383	{
mbed_official	87:085cde657901	384	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
mbed_official	87:085cde657901	385	{
mbed_official	87:085cde657901	386	return HAL_ERROR;
mbed_official	87:085cde657901	387	}
mbed_official	87:085cde657901	388	}
mbed_official	87:085cde657901	389	else
mbed_official	87:085cde657901	390	{
mbed_official	87:085cde657901	391	/* Check the HSI State */
mbed_official	87:085cde657901	392	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
mbed_official	87:085cde657901	393	{
mbed_official	87:085cde657901	394	/* Enable the Internal High Speed oscillator (HSI). */
mbed_official	87:085cde657901	395	__HAL_RCC_HSI_ENABLE();
mbed_official	87:085cde657901	396
mbed_official	87:085cde657901	397	/* Get timeout */
mbed_official	87:085cde657901	398	timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE;
mbed_official	87:085cde657901	399
mbed_official	87:085cde657901	400	/* Wait till HSI is ready */
mbed_official	87:085cde657901	401	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	87:085cde657901	402	{
mbed_official	87:085cde657901	403	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	404	{
mbed_official	87:085cde657901	405	return HAL_TIMEOUT;
mbed_official	87:085cde657901	406	}
mbed_official	87:085cde657901	407	}
mbed_official	87:085cde657901	408
mbed_official	87:085cde657901	409	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
mbed_official	87:085cde657901	410	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
mbed_official	87:085cde657901	411	}
mbed_official	87:085cde657901	412	else
mbed_official	87:085cde657901	413	{
mbed_official	87:085cde657901	414	/* Disable the Internal High Speed oscillator (HSI). */
mbed_official	87:085cde657901	415	__HAL_RCC_HSI_DISABLE();
mbed_official	87:085cde657901	416
mbed_official	87:085cde657901	417	/* Get timeout */
mbed_official	87:085cde657901	418	timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE;
mbed_official	87:085cde657901	419
mbed_official	87:085cde657901	420	/* Wait till HSI is ready */
mbed_official	87:085cde657901	421	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official	87:085cde657901	422	{
mbed_official	87:085cde657901	423	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	424	{
mbed_official	87:085cde657901	425	return HAL_TIMEOUT;
mbed_official	87:085cde657901	426	}
mbed_official	87:085cde657901	427	}
mbed_official	87:085cde657901	428	}
mbed_official	87:085cde657901	429	}
mbed_official	87:085cde657901	430	}
mbed_official	87:085cde657901	431	/------------------------------ LSI Configuration -------------------------/
mbed_official	87:085cde657901	432	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
mbed_official	87:085cde657901	433	{
mbed_official	87:085cde657901	434	/* Check the parameters */
mbed_official	87:085cde657901	435	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
mbed_official	87:085cde657901	436
mbed_official	87:085cde657901	437	/* Check the LSI State */
mbed_official	87:085cde657901	438	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
mbed_official	87:085cde657901	439	{
mbed_official	87:085cde657901	440	/* Enable the Internal Low Speed oscillator (LSI). */
mbed_official	87:085cde657901	441	__HAL_RCC_LSI_ENABLE();
mbed_official	87:085cde657901	442
mbed_official	87:085cde657901	443	/* Get timeout */
mbed_official	87:085cde657901	444	timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE;
mbed_official	87:085cde657901	445
mbed_official	87:085cde657901	446	/* Wait till LSI is ready */
mbed_official	87:085cde657901	447	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
mbed_official	87:085cde657901	448	{
mbed_official	87:085cde657901	449	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	450	{
mbed_official	87:085cde657901	451	return HAL_TIMEOUT;
mbed_official	87:085cde657901	452	}
mbed_official	87:085cde657901	453	}
mbed_official	87:085cde657901	454	}
mbed_official	87:085cde657901	455	else
mbed_official	87:085cde657901	456	{
mbed_official	87:085cde657901	457	/* Disable the Internal Low Speed oscillator (LSI). */
mbed_official	87:085cde657901	458	__HAL_RCC_LSI_DISABLE();
mbed_official	87:085cde657901	459
mbed_official	87:085cde657901	460	/* Get timeout */
mbed_official	87:085cde657901	461	timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE;
mbed_official	87:085cde657901	462
mbed_official	87:085cde657901	463	/* Wait till LSI is ready */
mbed_official	87:085cde657901	464	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
mbed_official	87:085cde657901	465	{
mbed_official	87:085cde657901	466	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	467	{
mbed_official	87:085cde657901	468	return HAL_TIMEOUT;
mbed_official	87:085cde657901	469	}
mbed_official	87:085cde657901	470	}
mbed_official	87:085cde657901	471	}
mbed_official	87:085cde657901	472	}
mbed_official	87:085cde657901	473	/------------------------------ LSE Configuration -------------------------/
mbed_official	87:085cde657901	474	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
mbed_official	87:085cde657901	475	{
mbed_official	87:085cde657901	476	/* Check the parameters */
mbed_official	87:085cde657901	477	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
mbed_official	87:085cde657901	478
mbed_official	87:085cde657901	479	/* Check the LSE State before enabling the access to the Bachup domain */
mbed_official	87:085cde657901	480	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
mbed_official	87:085cde657901	481	{
mbed_official	87:085cde657901	482	/* Enable Power Controller clock */
mbed_official	87:085cde657901	483	__PWR_CLK_ENABLE();
mbed_official	87:085cde657901	484
mbed_official	87:085cde657901	485	/* Enable write access to Backup domain */
mbed_official	87:085cde657901	486	PWR->CR \|= PWR_CR_DBP;
mbed_official	87:085cde657901	487	}
mbed_official	87:085cde657901	488	/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
mbed_official	87:085cde657901	489	__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
mbed_official	87:085cde657901	490
mbed_official	87:085cde657901	491	/* Get timeout */
mbed_official	87:085cde657901	492	timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	493
mbed_official	87:085cde657901	494	/* Wait till LSE is ready */
mbed_official	87:085cde657901	495	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official	87:085cde657901	496	{
mbed_official	87:085cde657901	497	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	498	{
mbed_official	87:085cde657901	499	return HAL_TIMEOUT;
mbed_official	87:085cde657901	500	}
mbed_official	87:085cde657901	501	}
mbed_official	87:085cde657901	502
mbed_official	87:085cde657901	503	/* Set the new LSE configuration -----------------------------------------*/
mbed_official	87:085cde657901	504	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
mbed_official	87:085cde657901	505	/* Check the LSE State */
mbed_official	87:085cde657901	506	if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
mbed_official	87:085cde657901	507	{
mbed_official	87:085cde657901	508	/* Get timeout */
mbed_official	87:085cde657901	509	timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	510
mbed_official	87:085cde657901	511	/* Wait till LSE is ready */
mbed_official	87:085cde657901	512	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	87:085cde657901	513	{
mbed_official	87:085cde657901	514	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	515	{
mbed_official	87:085cde657901	516	return HAL_TIMEOUT;
mbed_official	87:085cde657901	517	}
mbed_official	87:085cde657901	518	}
mbed_official	87:085cde657901	519	}
mbed_official	87:085cde657901	520	else
mbed_official	87:085cde657901	521	{
mbed_official	87:085cde657901	522	/* Get timeout */
mbed_official	87:085cde657901	523	timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	524
mbed_official	87:085cde657901	525	/* Wait till LSE is ready */
mbed_official	87:085cde657901	526	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official	87:085cde657901	527	{
mbed_official	87:085cde657901	528	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	529	{
mbed_official	87:085cde657901	530	return HAL_TIMEOUT;
mbed_official	87:085cde657901	531	}
mbed_official	87:085cde657901	532	}
mbed_official	87:085cde657901	533	}
mbed_official	87:085cde657901	534	}
mbed_official	87:085cde657901	535	/-------------------------------- PLL Configuration -----------------------/
mbed_official	87:085cde657901	536	/* Check the parameters */
mbed_official	87:085cde657901	537	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
mbed_official	87:085cde657901	538	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
mbed_official	87:085cde657901	539	{
mbed_official	87:085cde657901	540	/* Check if the PLL is used as system clock or not */
mbed_official	87:085cde657901	541	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	87:085cde657901	542	{
mbed_official	87:085cde657901	543	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
mbed_official	87:085cde657901	544	{
mbed_official	87:085cde657901	545	/* Check the parameters */
mbed_official	87:085cde657901	546	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
mbed_official	87:085cde657901	547	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
mbed_official	87:085cde657901	548	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
mbed_official	87:085cde657901	549	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
mbed_official	87:085cde657901	550	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
mbed_official	87:085cde657901	551
mbed_official	87:085cde657901	552	/* Disable the main PLL. */
mbed_official	87:085cde657901	553	__HAL_RCC_PLL_DISABLE();
mbed_official	87:085cde657901	554
mbed_official	87:085cde657901	555	/* Get timeout */
mbed_official	87:085cde657901	556	timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
mbed_official	87:085cde657901	557
mbed_official	87:085cde657901	558	/* Wait till PLL is ready */
mbed_official	87:085cde657901	559	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official	87:085cde657901	560	{
mbed_official	87:085cde657901	561	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	562	{
mbed_official	87:085cde657901	563	return HAL_TIMEOUT;
mbed_official	87:085cde657901	564	}
mbed_official	87:085cde657901	565	}
mbed_official	87:085cde657901	566
mbed_official	87:085cde657901	567	/* Configure the main PLL clock source, multiplication and division factors. */
mbed_official	87:085cde657901	568	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
mbed_official	87:085cde657901	569	RCC_OscInitStruct->PLL.PLLM,
mbed_official	87:085cde657901	570	RCC_OscInitStruct->PLL.PLLN,
mbed_official	87:085cde657901	571	RCC_OscInitStruct->PLL.PLLP,
mbed_official	87:085cde657901	572	RCC_OscInitStruct->PLL.PLLQ);
mbed_official	87:085cde657901	573	/* Enable the main PLL. */
mbed_official	87:085cde657901	574	__HAL_RCC_PLL_ENABLE();
mbed_official	87:085cde657901	575
mbed_official	87:085cde657901	576	/* Get timeout */
mbed_official	87:085cde657901	577	timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
mbed_official	87:085cde657901	578
mbed_official	87:085cde657901	579	/* Wait till PLL is ready */
mbed_official	87:085cde657901	580	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	87:085cde657901	581	{
mbed_official	87:085cde657901	582	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	583	{
mbed_official	87:085cde657901	584	return HAL_TIMEOUT;
mbed_official	87:085cde657901	585	}
mbed_official	87:085cde657901	586	}
mbed_official	87:085cde657901	587	}
mbed_official	87:085cde657901	588	else
mbed_official	87:085cde657901	589	{
mbed_official	87:085cde657901	590	/* Disable the main PLL. */
mbed_official	87:085cde657901	591	__HAL_RCC_PLL_DISABLE();
mbed_official	87:085cde657901	592	/* Get timeout */
mbed_official	87:085cde657901	593	timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
mbed_official	87:085cde657901	594
mbed_official	87:085cde657901	595	/* Wait till PLL is ready */
mbed_official	87:085cde657901	596	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official	87:085cde657901	597	{
mbed_official	87:085cde657901	598	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	599	{
mbed_official	87:085cde657901	600	return HAL_TIMEOUT;
mbed_official	87:085cde657901	601	}
mbed_official	87:085cde657901	602	}
mbed_official	87:085cde657901	603	}
mbed_official	87:085cde657901	604	}
mbed_official	87:085cde657901	605	else
mbed_official	87:085cde657901	606	{
mbed_official	87:085cde657901	607	return HAL_ERROR;
mbed_official	87:085cde657901	608	}
mbed_official	87:085cde657901	609	}
mbed_official	87:085cde657901	610	return HAL_OK;
mbed_official	87:085cde657901	611	}
mbed_official	87:085cde657901	612
mbed_official	87:085cde657901	613	/**
mbed_official	87:085cde657901	614	* @brief Initializes the CPU, AHB and APB busses clocks according to the specified
mbed_official	87:085cde657901	615	* parameters in the RCC_ClkInitStruct.
mbed_official	87:085cde657901	616	* @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	87:085cde657901	617	* contains the configuration information for the RCC peripheral.
mbed_official	87:085cde657901	618	* @param FLatency: FLASH Latency, this parameter depend on device selected
mbed_official	87:085cde657901	619	*
mbed_official	87:085cde657901	620	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official	87:085cde657901	621	* and updated by HAL_RCC_GetHCLKFreq() function called within this function
mbed_official	87:085cde657901	622	*
mbed_official	87:085cde657901	623	* @note The HSI is used (enabled by hardware) as system clock source after
mbed_official	87:085cde657901	624	* startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official	87:085cde657901	625	* of failure of the HSE used directly or indirectly as system clock
mbed_official	87:085cde657901	626	* (if the Clock Security System CSS is enabled).
mbed_official	87:085cde657901	627	*
mbed_official	87:085cde657901	628	* @note A switch from one clock source to another occurs only if the target
mbed_official	87:085cde657901	629	* clock source is ready (clock stable after startup delay or PLL locked).
mbed_official	87:085cde657901	630	* If a clock source which is not yet ready is selected, the switch will
mbed_official	87:085cde657901	631	* occur when the clock source will be ready.
mbed_official	87:085cde657901	632	*
mbed_official	87:085cde657901	633	* @note Depending on the device voltage range, the software has to set correctly
mbed_official	87:085cde657901	634	* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
mbed_official	87:085cde657901	635	* (for more details refer to section above "Initialization/de-initialization functions")
mbed_official	87:085cde657901	636	* @retval None
mbed_official	87:085cde657901	637	*/
mbed_official	87:085cde657901	638	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
mbed_official	87:085cde657901	639	{
mbed_official	87:085cde657901	640
mbed_official	87:085cde657901	641	uint32_t timeout = 0;
mbed_official	87:085cde657901	642
mbed_official	87:085cde657901	643	/* Check the parameters */
mbed_official	87:085cde657901	644	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
mbed_official	87:085cde657901	645	assert_param(IS_FLASH_LATENCY(FLatency));
mbed_official	87:085cde657901	646
mbed_official	87:085cde657901	647	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
mbed_official	87:085cde657901	648	must be correctly programmed according to the frequency of the CPU clock
mbed_official	87:085cde657901	649	(HCLK) and the supply voltage of the device. */
mbed_official	87:085cde657901	650
mbed_official	87:085cde657901	651	/* Increasing the CPU frequency */
mbed_official	87:085cde657901	652	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
mbed_official	87:085cde657901	653	{
mbed_official	87:085cde657901	654	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official	87:085cde657901	655	__HAL_FLASH_SET_LATENCY(FLatency);
mbed_official	87:085cde657901	656
mbed_official	87:085cde657901	657	/* Check that the new number of wait states is taken into account to access the Flash
mbed_official	87:085cde657901	658	memory by reading the FLASH_ACR register */
mbed_official	87:085cde657901	659	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official	87:085cde657901	660	{
mbed_official	87:085cde657901	661	return HAL_ERROR;
mbed_official	87:085cde657901	662	}
mbed_official	87:085cde657901	663
mbed_official	87:085cde657901	664	/------------------------- SYSCLK Configuration ---------------------------/
mbed_official	87:085cde657901	665	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official	87:085cde657901	666	{
mbed_official	87:085cde657901	667	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official	87:085cde657901	668
mbed_official	87:085cde657901	669	/* HSE is selected as System Clock Source */
mbed_official	87:085cde657901	670	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	87:085cde657901	671	{
mbed_official	87:085cde657901	672	/* Check the HSE ready flag */
mbed_official	87:085cde657901	673	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	87:085cde657901	674	{
mbed_official	87:085cde657901	675	return HAL_ERROR;
mbed_official	87:085cde657901	676	}
mbed_official	87:085cde657901	677	}
mbed_official	87:085cde657901	678	/* PLL is selected as System Clock Source */
mbed_official	87:085cde657901	679	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	87:085cde657901	680	{
mbed_official	87:085cde657901	681	/* Check the PLL ready flag */
mbed_official	87:085cde657901	682	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	87:085cde657901	683	{
mbed_official	87:085cde657901	684	return HAL_ERROR;
mbed_official	87:085cde657901	685	}
mbed_official	87:085cde657901	686	}
mbed_official	87:085cde657901	687	/* HSI is selected as System Clock Source */
mbed_official	87:085cde657901	688	else
mbed_official	87:085cde657901	689	{
mbed_official	87:085cde657901	690	/* Check the HSI ready flag */
mbed_official	87:085cde657901	691	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	87:085cde657901	692	{
mbed_official	87:085cde657901	693	return HAL_ERROR;
mbed_official	87:085cde657901	694	}
mbed_official	87:085cde657901	695	}
mbed_official	87:085cde657901	696	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official	87:085cde657901	697
mbed_official	87:085cde657901	698	/* Get timeout */
mbed_official	87:085cde657901	699	timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE;
mbed_official	87:085cde657901	700
mbed_official	87:085cde657901	701	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	87:085cde657901	702	{
mbed_official	87:085cde657901	703	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
mbed_official	87:085cde657901	704	{
mbed_official	87:085cde657901	705	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	706	{
mbed_official	87:085cde657901	707	return HAL_TIMEOUT;
mbed_official	87:085cde657901	708	}
mbed_official	87:085cde657901	709	}
mbed_official	87:085cde657901	710	}
mbed_official	87:085cde657901	711	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	87:085cde657901	712	{
mbed_official	87:085cde657901	713	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	87:085cde657901	714	{
mbed_official	87:085cde657901	715	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	716	{
mbed_official	87:085cde657901	717	return HAL_TIMEOUT;
mbed_official	87:085cde657901	718	}
mbed_official	87:085cde657901	719	}
mbed_official	87:085cde657901	720	}
mbed_official	87:085cde657901	721	else
mbed_official	87:085cde657901	722	{
mbed_official	87:085cde657901	723	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
mbed_official	87:085cde657901	724	{
mbed_official	87:085cde657901	725	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	726	{
mbed_official	87:085cde657901	727	return HAL_TIMEOUT;
mbed_official	87:085cde657901	728	}
mbed_official	87:085cde657901	729	}
mbed_official	87:085cde657901	730	}
mbed_official	87:085cde657901	731	}
mbed_official	87:085cde657901	732	}
mbed_official	87:085cde657901	733	/* Decreasing the CPU frequency */
mbed_official	87:085cde657901	734	else
mbed_official	87:085cde657901	735	{
mbed_official	87:085cde657901	736	/------------------------- SYSCLK Configuration ---------------------------/
mbed_official	87:085cde657901	737	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official	87:085cde657901	738	{
mbed_official	87:085cde657901	739	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official	87:085cde657901	740
mbed_official	87:085cde657901	741	/* HSE is selected as System Clock Source */
mbed_official	87:085cde657901	742	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	87:085cde657901	743	{
mbed_official	87:085cde657901	744	/* Check the HSE ready flag */
mbed_official	87:085cde657901	745	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	87:085cde657901	746	{
mbed_official	87:085cde657901	747	return HAL_ERROR;
mbed_official	87:085cde657901	748	}
mbed_official	87:085cde657901	749	}
mbed_official	87:085cde657901	750	/* PLL is selected as System Clock Source */
mbed_official	87:085cde657901	751	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	87:085cde657901	752	{
mbed_official	87:085cde657901	753	/* Check the PLL ready flag */
mbed_official	87:085cde657901	754	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	87:085cde657901	755	{
mbed_official	87:085cde657901	756	return HAL_ERROR;
mbed_official	87:085cde657901	757	}
mbed_official	87:085cde657901	758	}
mbed_official	87:085cde657901	759	/* HSI is selected as System Clock Source */
mbed_official	87:085cde657901	760	else
mbed_official	87:085cde657901	761	{
mbed_official	87:085cde657901	762	/* Check the HSI ready flag */
mbed_official	87:085cde657901	763	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	87:085cde657901	764	{
mbed_official	87:085cde657901	765	return HAL_ERROR;
mbed_official	87:085cde657901	766	}
mbed_official	87:085cde657901	767	}
mbed_official	87:085cde657901	768	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official	87:085cde657901	769
mbed_official	87:085cde657901	770	/* Get timeout */
mbed_official	87:085cde657901	771	timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE;
mbed_official	87:085cde657901	772
mbed_official	87:085cde657901	773	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	87:085cde657901	774	{
mbed_official	87:085cde657901	775	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
mbed_official	87:085cde657901	776	{
mbed_official	87:085cde657901	777	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	778	{
mbed_official	87:085cde657901	779	return HAL_TIMEOUT;
mbed_official	87:085cde657901	780	}
mbed_official	87:085cde657901	781	}
mbed_official	87:085cde657901	782	}
mbed_official	87:085cde657901	783	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	87:085cde657901	784	{
mbed_official	87:085cde657901	785	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	87:085cde657901	786	{
mbed_official	87:085cde657901	787	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	788	{
mbed_official	87:085cde657901	789	return HAL_TIMEOUT;
mbed_official	87:085cde657901	790	}
mbed_official	87:085cde657901	791	}
mbed_official	87:085cde657901	792	}
mbed_official	87:085cde657901	793	else
mbed_official	87:085cde657901	794	{
mbed_official	87:085cde657901	795	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
mbed_official	87:085cde657901	796	{
mbed_official	87:085cde657901	797	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	798	{
mbed_official	87:085cde657901	799	return HAL_TIMEOUT;
mbed_official	87:085cde657901	800	}
mbed_official	87:085cde657901	801	}
mbed_official	87:085cde657901	802	}
mbed_official	87:085cde657901	803	}
mbed_official	87:085cde657901	804
mbed_official	87:085cde657901	805	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official	87:085cde657901	806	__HAL_FLASH_SET_LATENCY(FLatency);
mbed_official	87:085cde657901	807
mbed_official	87:085cde657901	808	/* Check that the new number of wait states is taken into account to access the Flash
mbed_official	87:085cde657901	809	memory by reading the FLASH_ACR register */
mbed_official	87:085cde657901	810	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official	87:085cde657901	811	{
mbed_official	87:085cde657901	812	return HAL_ERROR;
mbed_official	87:085cde657901	813	}
mbed_official	87:085cde657901	814	}
mbed_official	87:085cde657901	815
mbed_official	87:085cde657901	816	/-------------------------- HCLK Configuration ----------------------------/
mbed_official	87:085cde657901	817	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official	87:085cde657901	818	{
mbed_official	87:085cde657901	819	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official	87:085cde657901	820	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official	87:085cde657901	821	}
mbed_official	87:085cde657901	822
mbed_official	87:085cde657901	823	/-------------------------- PCLK1 Configuration ---------------------------/
mbed_official	87:085cde657901	824	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
mbed_official	87:085cde657901	825	{
mbed_official	87:085cde657901	826	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
mbed_official	87:085cde657901	827	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
mbed_official	87:085cde657901	828	}
mbed_official	87:085cde657901	829
mbed_official	87:085cde657901	830	/-------------------------- PCLK2 Configuration ---------------------------/
mbed_official	87:085cde657901	831	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
mbed_official	87:085cde657901	832	{
mbed_official	87:085cde657901	833	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
mbed_official	87:085cde657901	834	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
mbed_official	87:085cde657901	835	}
mbed_official	87:085cde657901	836
mbed_official	87:085cde657901	837	/* Setup SysTick Timer for 1 msec interrupts.
mbed_official	87:085cde657901	838	------------------------------------------
mbed_official	87:085cde657901	839	The SysTick_Config() function is a CMSIS function which configure:
mbed_official	87:085cde657901	840	- The SysTick Reload register with value passed as function parameter.
mbed_official	87:085cde657901	841	- Configure the SysTick IRQ priority to the lowest value (0x0F).
mbed_official	87:085cde657901	842	- Reset the SysTick Counter register.
mbed_official	87:085cde657901	843	- Configure the SysTick Counter clock source to be Core Clock Source (HCLK).
mbed_official	87:085cde657901	844	- Enable the SysTick Interrupt.
mbed_official	87:085cde657901	845	- Start the SysTick Counter.*/
mbed_official	87:085cde657901	846	SysTick_Config(HAL_RCC_GetHCLKFreq() / 1000);
mbed_official	87:085cde657901	847
mbed_official	87:085cde657901	848	return HAL_OK;
mbed_official	87:085cde657901	849	}
mbed_official	87:085cde657901	850
mbed_official	87:085cde657901	851	/**
mbed_official	87:085cde657901	852	* @}
mbed_official	87:085cde657901	853	*/
mbed_official	87:085cde657901	854
mbed_official	87:085cde657901	855	/** @defgroup RCC_Group2 Peripheral Control functions
mbed_official	87:085cde657901	856	* @brief RCC clocks control functions
mbed_official	87:085cde657901	857	*
mbed_official	87:085cde657901	858	@verbatim
mbed_official	87:085cde657901	859	===============================================================================
mbed_official	87:085cde657901	860	##### Peripheral Control functions #####
mbed_official	87:085cde657901	861	===============================================================================
mbed_official	87:085cde657901	862	[..]
mbed_official	87:085cde657901	863	This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official	87:085cde657901	864	frequencies.
mbed_official	87:085cde657901	865
mbed_official	87:085cde657901	866	@endverbatim
mbed_official	87:085cde657901	867	* @{
mbed_official	87:085cde657901	868	*/
mbed_official	87:085cde657901	869
mbed_official	87:085cde657901	870	/**
mbed_official	87:085cde657901	871	* @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
mbed_official	87:085cde657901	872	* @note PA8/PC9 should be configured in alternate function mode.
mbed_official	87:085cde657901	873	* @param RCC_MCOx: specifies the output direction for the clock source.
mbed_official	87:085cde657901	874	* This parameter can be one of the following values:
mbed_official	87:085cde657901	875	* @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
mbed_official	87:085cde657901	876	* @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
mbed_official	87:085cde657901	877	* @param RCC_MCOSource: specifies the clock source to output.
mbed_official	87:085cde657901	878	* This parameter can be one of the following values:
mbed_official	87:085cde657901	879	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
mbed_official	87:085cde657901	880	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
mbed_official	87:085cde657901	881	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
mbed_official	87:085cde657901	882	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
mbed_official	87:085cde657901	883	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
mbed_official	87:085cde657901	884	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
mbed_official	87:085cde657901	885	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
mbed_official	87:085cde657901	886	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
mbed_official	87:085cde657901	887	* @param RCC_MCODiv: specifies the MCOx prescaler.
mbed_official	87:085cde657901	888	* This parameter can be one of the following values:
mbed_official	87:085cde657901	889	* @arg RCC_MCODIV_1: no division applied to MCOx clock
mbed_official	87:085cde657901	890	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
mbed_official	87:085cde657901	891	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
mbed_official	87:085cde657901	892	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
mbed_official	87:085cde657901	893	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
mbed_official	87:085cde657901	894	* @retval None
mbed_official	87:085cde657901	895	*/
mbed_official	87:085cde657901	896	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
mbed_official	87:085cde657901	897	{
mbed_official	87:085cde657901	898	GPIO_InitTypeDef GPIO_InitStruct;
mbed_official	87:085cde657901	899	/* Check the parameters */
mbed_official	87:085cde657901	900	assert_param(IS_RCC_MCO(RCC_MCOx));
mbed_official	87:085cde657901	901	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
mbed_official	87:085cde657901	902	/* RCC_MCO1 */
mbed_official	87:085cde657901	903	if(RCC_MCOx == RCC_MCO1)
mbed_official	87:085cde657901	904	{
mbed_official	87:085cde657901	905	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
mbed_official	87:085cde657901	906
mbed_official	87:085cde657901	907	/* MCO1 Clock Enable */
mbed_official	87:085cde657901	908	__MCO1_CLK_ENABLE();
mbed_official	87:085cde657901	909
mbed_official	87:085cde657901	910	/* Configue the MCO1 pin in alternate function mode */
mbed_official	87:085cde657901	911	GPIO_InitStruct.Pin = MCO1_PIN;
mbed_official	87:085cde657901	912	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
mbed_official	87:085cde657901	913	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
mbed_official	87:085cde657901	914	GPIO_InitStruct.Pull = GPIO_NOPULL;
mbed_official	87:085cde657901	915	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
mbed_official	87:085cde657901	916	HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
mbed_official	87:085cde657901	917
mbed_official	87:085cde657901	918	/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
mbed_official	87:085cde657901	919	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), (RCC_MCOSource \| RCC_MCODiv));
mbed_official	87:085cde657901	920	}
mbed_official	87:085cde657901	921	else
mbed_official	87:085cde657901	922	{
mbed_official	87:085cde657901	923	assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
mbed_official	87:085cde657901	924
mbed_official	87:085cde657901	925	/* MCO2 Clock Enable */
mbed_official	87:085cde657901	926	__MCO2_CLK_ENABLE();
mbed_official	87:085cde657901	927
mbed_official	87:085cde657901	928	/* Configue the MCO2 pin in alternate function mode */
mbed_official	87:085cde657901	929	GPIO_InitStruct.Pin = MCO2_PIN;
mbed_official	87:085cde657901	930	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
mbed_official	87:085cde657901	931	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
mbed_official	87:085cde657901	932	GPIO_InitStruct.Pull = GPIO_NOPULL;
mbed_official	87:085cde657901	933	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
mbed_official	87:085cde657901	934	HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
mbed_official	87:085cde657901	935
mbed_official	87:085cde657901	936	/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
mbed_official	87:085cde657901	937	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), (RCC_MCOSource \| (RCC_MCODiv << 3)));
mbed_official	87:085cde657901	938	}
mbed_official	87:085cde657901	939	}
mbed_official	87:085cde657901	940
mbed_official	87:085cde657901	941	/**
mbed_official	87:085cde657901	942	* @brief Enables the Clock Security System.
mbed_official	87:085cde657901	943	* @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official	87:085cde657901	944	* is automatically disabled and an interrupt is generated to inform the
mbed_official	87:085cde657901	945	* software about the failure (Clock Security System Interrupt, CSSI),
mbed_official	87:085cde657901	946	* allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official	87:085cde657901	947	* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
mbed_official	87:085cde657901	948	* @param None
mbed_official	87:085cde657901	949	* @retval None
mbed_official	87:085cde657901	950	*/
mbed_official	87:085cde657901	951	void HAL_RCC_EnableCSS(void)
mbed_official	87:085cde657901	952	{
mbed_official	87:085cde657901	953	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)ENABLE;
mbed_official	87:085cde657901	954	}
mbed_official	87:085cde657901	955
mbed_official	87:085cde657901	956	/**
mbed_official	87:085cde657901	957	* @brief Disables the Clock Security System.
mbed_official	87:085cde657901	958	* @param None
mbed_official	87:085cde657901	959	* @retval None
mbed_official	87:085cde657901	960	*/
mbed_official	87:085cde657901	961	void HAL_RCC_DisableCSS(void)
mbed_official	87:085cde657901	962	{
mbed_official	87:085cde657901	963	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)DISABLE;
mbed_official	87:085cde657901	964	}
mbed_official	87:085cde657901	965
mbed_official	87:085cde657901	966	/**
mbed_official	87:085cde657901	967	* @brief Returns the SYSCLK frequency
mbed_official	87:085cde657901	968	*
mbed_official	87:085cde657901	969	* @note The system frequency computed by this function is not the real
mbed_official	87:085cde657901	970	* frequency in the chip. It is calculated based on the predefined
mbed_official	87:085cde657901	971	* constant and the selected clock source:
mbed_official	87:085cde657901	972	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official	87:085cde657901	973	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
mbed_official	87:085cde657901	974	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
mbed_official	87:085cde657901	975	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	87:085cde657901	976	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	87:085cde657901	977	* 16 MHz) but the real value may vary depending on the variations
mbed_official	87:085cde657901	978	* in voltage and temperature.
mbed_official	87:085cde657901	979	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	87:085cde657901	980	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	87:085cde657901	981	* frequency of the crystal used. Otherwise, this function may
mbed_official	87:085cde657901	982	* have wrong result.
mbed_official	87:085cde657901	983	*
mbed_official	87:085cde657901	984	* @note The result of this function could be not correct when using fractional
mbed_official	87:085cde657901	985	* value for HSE crystal.
mbed_official	87:085cde657901	986	*
mbed_official	87:085cde657901	987	* @note This function can be used by the user application to compute the
mbed_official	87:085cde657901	988	* baudrate for the communication peripherals or configure other parameters.
mbed_official	87:085cde657901	989	*
mbed_official	87:085cde657901	990	* @note Each time SYSCLK changes, this function must be called to update the
mbed_official	87:085cde657901	991	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	87:085cde657901	992	*
mbed_official	87:085cde657901	993	*
mbed_official	87:085cde657901	994	* @param None
mbed_official	87:085cde657901	995	* @retval SYSCLK frequency
mbed_official	87:085cde657901	996	*/
mbed_official	87:085cde657901	997	uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official	87:085cde657901	998	{
mbed_official	87:085cde657901	999	uint32_t pllm = 0, pllvco = 0, pllp = 0;
mbed_official	87:085cde657901	1000	uint32_t sysclockfreq = 0;
mbed_official	87:085cde657901	1001
mbed_official	87:085cde657901	1002	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	87:085cde657901	1003	switch (RCC->CFGR & RCC_CFGR_SWS)
mbed_official	87:085cde657901	1004	{
mbed_official	87:085cde657901	1005	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
mbed_official	87:085cde657901	1006	{
mbed_official	87:085cde657901	1007	sysclockfreq = HSI_VALUE;
mbed_official	87:085cde657901	1008	break;
mbed_official	87:085cde657901	1009	}
mbed_official	87:085cde657901	1010	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
mbed_official	87:085cde657901	1011	{
mbed_official	87:085cde657901	1012	sysclockfreq = HSE_VALUE;
mbed_official	87:085cde657901	1013	break;
mbed_official	87:085cde657901	1014	}
mbed_official	87:085cde657901	1015	case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
mbed_official	87:085cde657901	1016	{
mbed_official	87:085cde657901	1017	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
mbed_official	87:085cde657901	1018	SYSCLK = PLL_VCO / PLLP */
mbed_official	87:085cde657901	1019	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official	87:085cde657901	1020	if (__RCC_PLLSRC() != 0)
mbed_official	87:085cde657901	1021	{
mbed_official	87:085cde657901	1022	/* HSE used as PLL clock source */
mbed_official	87:085cde657901	1023	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	87:085cde657901	1024	}
mbed_official	87:085cde657901	1025	else
mbed_official	87:085cde657901	1026	{
mbed_official	87:085cde657901	1027	/* HSI used as PLL clock source */
mbed_official	87:085cde657901	1028	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	87:085cde657901	1029	}
mbed_official	87:085cde657901	1030	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
mbed_official	87:085cde657901	1031
mbed_official	87:085cde657901	1032	sysclockfreq = pllvco/pllp;
mbed_official	87:085cde657901	1033	break;
mbed_official	87:085cde657901	1034	}
mbed_official	87:085cde657901	1035	default:
mbed_official	87:085cde657901	1036	{
mbed_official	87:085cde657901	1037	sysclockfreq = HSI_VALUE;
mbed_official	87:085cde657901	1038	break;
mbed_official	87:085cde657901	1039	}
mbed_official	87:085cde657901	1040	}
mbed_official	87:085cde657901	1041	return sysclockfreq;
mbed_official	87:085cde657901	1042	}
mbed_official	87:085cde657901	1043
mbed_official	87:085cde657901	1044	/**
mbed_official	87:085cde657901	1045	* @brief Returns the HCLK frequency
mbed_official	87:085cde657901	1046	* @note Each time HCLK changes, this function must be called to update the
mbed_official	87:085cde657901	1047	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	87:085cde657901	1048	*
mbed_official	87:085cde657901	1049	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official	87:085cde657901	1050	* and updated within this function
mbed_official	87:085cde657901	1051	* @param None
mbed_official	87:085cde657901	1052	* @retval HCLK frequency
mbed_official	87:085cde657901	1053	*/
mbed_official	87:085cde657901	1054	uint32_t HAL_RCC_GetHCLKFreq(void)
mbed_official	87:085cde657901	1055	{
mbed_official	87:085cde657901	1056	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
mbed_official	87:085cde657901	1057	return SystemCoreClock;
mbed_official	87:085cde657901	1058	}
mbed_official	87:085cde657901	1059
mbed_official	87:085cde657901	1060	/**
mbed_official	87:085cde657901	1061	* @brief Returns the PCLK1 frequency
mbed_official	87:085cde657901	1062	* @note Each time PCLK1 changes, this function must be called to update the
mbed_official	87:085cde657901	1063	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	87:085cde657901	1064	* @param None
mbed_official	87:085cde657901	1065	* @retval PCLK1 frequency
mbed_official	87:085cde657901	1066	*/
mbed_official	87:085cde657901	1067	uint32_t HAL_RCC_GetPCLK1Freq(void)
mbed_official	87:085cde657901	1068	{
mbed_official	87:085cde657901	1069	/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
mbed_official	87:085cde657901	1070	return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
mbed_official	87:085cde657901	1071	}
mbed_official	87:085cde657901	1072
mbed_official	87:085cde657901	1073	/**
mbed_official	87:085cde657901	1074	* @brief Returns the PCLK2 frequency
mbed_official	87:085cde657901	1075	* @note Each time PCLK2 changes, this function must be called to update the
mbed_official	87:085cde657901	1076	* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	87:085cde657901	1077	* @param None
mbed_official	87:085cde657901	1078	* @retval PCLK2 frequency
mbed_official	87:085cde657901	1079	*/
mbed_official	87:085cde657901	1080	uint32_t HAL_RCC_GetPCLK2Freq(void)
mbed_official	87:085cde657901	1081	{
mbed_official	87:085cde657901	1082	/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
mbed_official	87:085cde657901	1083	return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
mbed_official	87:085cde657901	1084	}
mbed_official	87:085cde657901	1085
mbed_official	87:085cde657901	1086	/**
mbed_official	87:085cde657901	1087	* @brief Configures the RCC_OscInitStruct according to the internal
mbed_official	87:085cde657901	1088	* RCC configuration registers.
mbed_official	87:085cde657901	1089	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	87:085cde657901	1090	* will be configured.
mbed_official	87:085cde657901	1091	* @retval None
mbed_official	87:085cde657901	1092	*/
mbed_official	87:085cde657901	1093	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official	87:085cde657901	1094	{
mbed_official	87:085cde657901	1095	/* Set all possible values for the Oscillator type parameter ---------------*/
mbed_official	87:085cde657901	1096	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
mbed_official	87:085cde657901	1097
mbed_official	87:085cde657901	1098	/* Get the HSE configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1099	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
mbed_official	87:085cde657901	1100	{
mbed_official	87:085cde657901	1101	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
mbed_official	87:085cde657901	1102	}
mbed_official	87:085cde657901	1103	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
mbed_official	87:085cde657901	1104	{
mbed_official	87:085cde657901	1105	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
mbed_official	87:085cde657901	1106	}
mbed_official	87:085cde657901	1107	else
mbed_official	87:085cde657901	1108	{
mbed_official	87:085cde657901	1109	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
mbed_official	87:085cde657901	1110	}
mbed_official	87:085cde657901	1111
mbed_official	87:085cde657901	1112	/* Get the HSI configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1113	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
mbed_official	87:085cde657901	1114	{
mbed_official	87:085cde657901	1115	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
mbed_official	87:085cde657901	1116	}
mbed_official	87:085cde657901	1117	else
mbed_official	87:085cde657901	1118	{
mbed_official	87:085cde657901	1119	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
mbed_official	87:085cde657901	1120	}
mbed_official	87:085cde657901	1121
mbed_official	87:085cde657901	1122	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
mbed_official	87:085cde657901	1123
mbed_official	87:085cde657901	1124	/* Get the LSE configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1125	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
mbed_official	87:085cde657901	1126	{
mbed_official	87:085cde657901	1127	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
mbed_official	87:085cde657901	1128	}
mbed_official	87:085cde657901	1129	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
mbed_official	87:085cde657901	1130	{
mbed_official	87:085cde657901	1131	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
mbed_official	87:085cde657901	1132	}
mbed_official	87:085cde657901	1133	else
mbed_official	87:085cde657901	1134	{
mbed_official	87:085cde657901	1135	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
mbed_official	87:085cde657901	1136	}
mbed_official	87:085cde657901	1137
mbed_official	87:085cde657901	1138	/* Get the LSI configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1139	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
mbed_official	87:085cde657901	1140	{
mbed_official	87:085cde657901	1141	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
mbed_official	87:085cde657901	1142	}
mbed_official	87:085cde657901	1143	else
mbed_official	87:085cde657901	1144	{
mbed_official	87:085cde657901	1145	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
mbed_official	87:085cde657901	1146	}
mbed_official	87:085cde657901	1147
mbed_official	87:085cde657901	1148	/* Get the PLL configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1149	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
mbed_official	87:085cde657901	1150	{
mbed_official	87:085cde657901	1151	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
mbed_official	87:085cde657901	1152	}
mbed_official	87:085cde657901	1153	else
mbed_official	87:085cde657901	1154	{
mbed_official	87:085cde657901	1155	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
mbed_official	87:085cde657901	1156	}
mbed_official	87:085cde657901	1157	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
mbed_official	87:085cde657901	1158	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
mbed_official	87:085cde657901	1159	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
mbed_official	87:085cde657901	1160	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
mbed_official	87:085cde657901	1161	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
mbed_official	87:085cde657901	1162	}
mbed_official	87:085cde657901	1163
mbed_official	87:085cde657901	1164	/**
mbed_official	87:085cde657901	1165	* @brief Configures the RCC_ClkInitStruct according to the internal
mbed_official	87:085cde657901	1166	* RCC configuration registers.
mbed_official	87:085cde657901	1167	* @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
mbed_official	87:085cde657901	1168	* will be configured.
mbed_official	87:085cde657901	1169	* @param pFLatency: Pointer on the Flash Latency.
mbed_official	87:085cde657901	1170	* @retval None
mbed_official	87:085cde657901	1171	*/
mbed_official	87:085cde657901	1172	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
mbed_official	87:085cde657901	1173	{
mbed_official	87:085cde657901	1174	/* Set all possible values for the Clock type parameter --------------------*/
mbed_official	87:085cde657901	1175	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
mbed_official	87:085cde657901	1176
mbed_official	87:085cde657901	1177	/* Get the SYSCLK configuration --------------------------------------------*/
mbed_official	87:085cde657901	1178	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
mbed_official	87:085cde657901	1179
mbed_official	87:085cde657901	1180	/* Get the HCLK configuration ----------------------------------------------*/
mbed_official	87:085cde657901	1181	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
mbed_official	87:085cde657901	1182
mbed_official	87:085cde657901	1183	/* Get the APB1 configuration ----------------------------------------------*/
mbed_official	87:085cde657901	1184	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
mbed_official	87:085cde657901	1185
mbed_official	87:085cde657901	1186	/* Get the APB2 configuration ----------------------------------------------*/
mbed_official	87:085cde657901	1187	RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
mbed_official	87:085cde657901	1188
mbed_official	87:085cde657901	1189	/* Get the Flash Wait State (Latency) configuration ------------------------*/
mbed_official	87:085cde657901	1190	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
mbed_official	87:085cde657901	1191	}
mbed_official	87:085cde657901	1192
mbed_official	87:085cde657901	1193	/**
mbed_official	87:085cde657901	1194	* @brief This function handles the RCC CSS interrupt request.
mbed_official	87:085cde657901	1195	* @note This API should be called under the NMI_Handler().
mbed_official	87:085cde657901	1196	* @param None
mbed_official	87:085cde657901	1197	* @retval None
mbed_official	87:085cde657901	1198	*/
mbed_official	87:085cde657901	1199	void HAL_RCC_NMI_IRQHandler(void)
mbed_official	87:085cde657901	1200	{
mbed_official	87:085cde657901	1201	/* Check RCC CSSF flag */
mbed_official	87:085cde657901	1202	if(__HAL_RCC_GET_IT(RCC_IT_CSS))
mbed_official	87:085cde657901	1203	{
mbed_official	87:085cde657901	1204	/* RCC Clock Security System interrupt user callback */
mbed_official	87:085cde657901	1205	HAL_RCC_CCSCallback();
mbed_official	87:085cde657901	1206
mbed_official	87:085cde657901	1207	/* Clear RCC CSS pending bit */
mbed_official	87:085cde657901	1208	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
mbed_official	87:085cde657901	1209	}
mbed_official	87:085cde657901	1210	}
mbed_official	87:085cde657901	1211
mbed_official	87:085cde657901	1212	/**
mbed_official	87:085cde657901	1213	* @brief RCC Clock Security System interrupt callback
mbed_official	87:085cde657901	1214	* @param none
mbed_official	87:085cde657901	1215	* @retval none
mbed_official	87:085cde657901	1216	*/
mbed_official	87:085cde657901	1217	__weak void HAL_RCC_CCSCallback(void)
mbed_official	87:085cde657901	1218	{
mbed_official	87:085cde657901	1219	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1220	the HAL_RCC_CCSCallback could be implemented in the user file
mbed_official	87:085cde657901	1221	*/
mbed_official	87:085cde657901	1222	}
mbed_official	87:085cde657901	1223
mbed_official	87:085cde657901	1224	/**
mbed_official	87:085cde657901	1225	* @}
mbed_official	87:085cde657901	1226	*/
mbed_official	87:085cde657901	1227
mbed_official	87:085cde657901	1228	/**
mbed_official	87:085cde657901	1229	* @}
mbed_official	87:085cde657901	1230	*/
mbed_official	87:085cde657901	1231
mbed_official	87:085cde657901	1232	#endif /* HAL_RCC_MODULE_ENABLED */
mbed_official	87:085cde657901	1233	/**
mbed_official	87:085cde657901	1234	* @}
mbed_official	87:085cde657901	1235	*/
mbed_official	87:085cde657901	1236
mbed_official	87:085cde657901	1237	/**
mbed_official	87:085cde657901	1238	* @}
mbed_official	87:085cde657901	1239	*/
mbed_official	87:085cde657901	1240
mbed_official	87:085cde657901	1241	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	29 Jun 2014
Imports:	3
Forks:	0
Commits:	135
Dependents:	1
Dependencies:	0
Followers:	3

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.c@87:085cde657901, 2014-02-08 (annotated)

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