test
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Dependents: mbed_in_china_blink_led
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mbed official
targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim.c@133:d4dda5c437f0, 2014-03-24 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Mar 24 17:45:07 2014 +0000
- Revision:
- 133:d4dda5c437f0
Synchronized with git revision 47b961246bed973fe4cb8932781ffc8025b78a61
Full URL: https://github.com/mbedmicro/mbed/commit/47b961246bed973fe4cb8932781ffc8025b78a61/
[STM32F4-Discovery (STM32F407VG)] initial port
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 133:d4dda5c437f0 | 1 | /** |
| mbed_official | 133:d4dda5c437f0 | 2 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 3 | * @file stm32f4xx_hal_tim.c |
| mbed_official | 133:d4dda5c437f0 | 4 | * @author MCD Application Team |
| mbed_official | 133:d4dda5c437f0 | 5 | * @version V1.0.0 |
| mbed_official | 133:d4dda5c437f0 | 6 | * @date 18-February-2014 |
| mbed_official | 133:d4dda5c437f0 | 7 | * @brief TIM HAL module driver. |
| mbed_official | 133:d4dda5c437f0 | 8 | * This file provides firmware functions to manage the following |
| mbed_official | 133:d4dda5c437f0 | 9 | * functionalities of the Timer (TIM) peripheral: |
| mbed_official | 133:d4dda5c437f0 | 10 | * + Time Base Initialization |
| mbed_official | 133:d4dda5c437f0 | 11 | * + Time Base Start |
| mbed_official | 133:d4dda5c437f0 | 12 | * + Time Base Start Interruption |
| mbed_official | 133:d4dda5c437f0 | 13 | * + Time Base Start DMA |
| mbed_official | 133:d4dda5c437f0 | 14 | * + Time Output Compare/PWM Initialization |
| mbed_official | 133:d4dda5c437f0 | 15 | * + Time Output Compare/PWM Channel Configuration |
| mbed_official | 133:d4dda5c437f0 | 16 | * + Time Output Compare/PWM Start |
| mbed_official | 133:d4dda5c437f0 | 17 | * + Time Output Compare/PWM Start Interruption |
| mbed_official | 133:d4dda5c437f0 | 18 | * + Time Output Compare/PWM Start DMA |
| mbed_official | 133:d4dda5c437f0 | 19 | * + Time Input Capture Initialization |
| mbed_official | 133:d4dda5c437f0 | 20 | * + Time Input Capture Channel Configuration |
| mbed_official | 133:d4dda5c437f0 | 21 | * + Time Input Capture Start |
| mbed_official | 133:d4dda5c437f0 | 22 | * + Time Input Capture Start Interruption |
| mbed_official | 133:d4dda5c437f0 | 23 | * + Time Input Capture Start DMA |
| mbed_official | 133:d4dda5c437f0 | 24 | * + Time One Pulse Initialization |
| mbed_official | 133:d4dda5c437f0 | 25 | * + Time One Pulse Channel Configuration |
| mbed_official | 133:d4dda5c437f0 | 26 | * + Time One Pulse Start |
| mbed_official | 133:d4dda5c437f0 | 27 | * + Time Encoder Interface Initialization |
| mbed_official | 133:d4dda5c437f0 | 28 | * + Time Encoder Interface Start |
| mbed_official | 133:d4dda5c437f0 | 29 | * + Time Encoder Interface Start Interruption |
| mbed_official | 133:d4dda5c437f0 | 30 | * + Time Encoder Interface Start DMA |
| mbed_official | 133:d4dda5c437f0 | 31 | * + Commutation Event configuration with Interruption and DMA |
| mbed_official | 133:d4dda5c437f0 | 32 | * + Time OCRef clear configuration |
| mbed_official | 133:d4dda5c437f0 | 33 | * + Time External Clock configuration |
| mbed_official | 133:d4dda5c437f0 | 34 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 35 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 36 | ##### TIMER Generic features ##### |
| mbed_official | 133:d4dda5c437f0 | 37 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 38 | [..] The Timer features include: |
| mbed_official | 133:d4dda5c437f0 | 39 | (#) 16-bit up, down, up/down auto-reload counter. |
| mbed_official | 133:d4dda5c437f0 | 40 | (#) 16-bit programmable prescaler allowing dividing (also on the fly) the |
| mbed_official | 133:d4dda5c437f0 | 41 | counter clock frequency either by any factor between 1 and 65536. |
| mbed_official | 133:d4dda5c437f0 | 42 | (#) Up to 4 independent channels for: |
| mbed_official | 133:d4dda5c437f0 | 43 | (++) Input Capture |
| mbed_official | 133:d4dda5c437f0 | 44 | (++) Output Compare |
| mbed_official | 133:d4dda5c437f0 | 45 | (++) PWM generation (Edge and Center-aligned Mode) |
| mbed_official | 133:d4dda5c437f0 | 46 | (++) One-pulse mode output |
| mbed_official | 133:d4dda5c437f0 | 47 | |
| mbed_official | 133:d4dda5c437f0 | 48 | ##### How to use this driver ##### |
| mbed_official | 133:d4dda5c437f0 | 49 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 50 | [..] |
| mbed_official | 133:d4dda5c437f0 | 51 | (#) Initialize the TIM low level resources by implementing the following functions |
| mbed_official | 133:d4dda5c437f0 | 52 | depending from feature used : |
| mbed_official | 133:d4dda5c437f0 | 53 | (++) Time Base : HAL_TIM_Base_MspInit() |
| mbed_official | 133:d4dda5c437f0 | 54 | (++) Input Capture : HAL_TIM_IC_MspInit() |
| mbed_official | 133:d4dda5c437f0 | 55 | (++) Output Compare : HAL_TIM_OC_MspInit() |
| mbed_official | 133:d4dda5c437f0 | 56 | (++) PWM generation : HAL_TIM_PWM_MspInit() |
| mbed_official | 133:d4dda5c437f0 | 57 | (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() |
| mbed_official | 133:d4dda5c437f0 | 58 | (++) Encoder mode output : HAL_TIM_Encoder_MspInit() |
| mbed_official | 133:d4dda5c437f0 | 59 | |
| mbed_official | 133:d4dda5c437f0 | 60 | (#) Initialize the TIM low level resources : |
| mbed_official | 133:d4dda5c437f0 | 61 | (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); |
| mbed_official | 133:d4dda5c437f0 | 62 | (##) TIM pins configuration |
| mbed_official | 133:d4dda5c437f0 | 63 | (+++) Enable the clock for the TIM GPIOs using the following function: |
| mbed_official | 133:d4dda5c437f0 | 64 | __GPIOx_CLK_ENABLE(); |
| mbed_official | 133:d4dda5c437f0 | 65 | (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); |
| mbed_official | 133:d4dda5c437f0 | 66 | |
| mbed_official | 133:d4dda5c437f0 | 67 | (#) The external Clock can be configured, if needed (the default clock is the |
| mbed_official | 133:d4dda5c437f0 | 68 | internal clock from the APBx), using the following function: |
| mbed_official | 133:d4dda5c437f0 | 69 | HAL_TIM_ConfigClockSource, the clock configuration should be done before |
| mbed_official | 133:d4dda5c437f0 | 70 | any start function. |
| mbed_official | 133:d4dda5c437f0 | 71 | |
| mbed_official | 133:d4dda5c437f0 | 72 | (#) Configure the TIM in the desired functioning mode using one of the |
| mbed_official | 133:d4dda5c437f0 | 73 | initialization function of this driver: |
| mbed_official | 133:d4dda5c437f0 | 74 | (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base |
| mbed_official | 133:d4dda5c437f0 | 75 | (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an |
| mbed_official | 133:d4dda5c437f0 | 76 | Output Compare signal. |
| mbed_official | 133:d4dda5c437f0 | 77 | (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a |
| mbed_official | 133:d4dda5c437f0 | 78 | PWM signal. |
| mbed_official | 133:d4dda5c437f0 | 79 | (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an |
| mbed_official | 133:d4dda5c437f0 | 80 | external signal. |
| mbed_official | 133:d4dda5c437f0 | 81 | (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer |
| mbed_official | 133:d4dda5c437f0 | 82 | in One Pulse Mode. |
| mbed_official | 133:d4dda5c437f0 | 83 | (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. |
| mbed_official | 133:d4dda5c437f0 | 84 | |
| mbed_official | 133:d4dda5c437f0 | 85 | (#) Activate the TIM peripheral using one of the start functions depending from the feature used: |
| mbed_official | 133:d4dda5c437f0 | 86 | (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() |
| mbed_official | 133:d4dda5c437f0 | 87 | (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() |
| mbed_official | 133:d4dda5c437f0 | 88 | (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() |
| mbed_official | 133:d4dda5c437f0 | 89 | (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() |
| mbed_official | 133:d4dda5c437f0 | 90 | (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() |
| mbed_official | 133:d4dda5c437f0 | 91 | (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). |
| mbed_official | 133:d4dda5c437f0 | 92 | |
| mbed_official | 133:d4dda5c437f0 | 93 | (#) The DMA Burst is managed with the two following functions: |
| mbed_official | 133:d4dda5c437f0 | 94 | HAL_TIM_DMABurst_WriteStart() |
| mbed_official | 133:d4dda5c437f0 | 95 | HAL_TIM_DMABurst_ReadStart() |
| mbed_official | 133:d4dda5c437f0 | 96 | |
| mbed_official | 133:d4dda5c437f0 | 97 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 98 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 99 | * @attention |
| mbed_official | 133:d4dda5c437f0 | 100 | * |
| mbed_official | 133:d4dda5c437f0 | 101 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 133:d4dda5c437f0 | 102 | * |
| mbed_official | 133:d4dda5c437f0 | 103 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 133:d4dda5c437f0 | 104 | * are permitted provided that the following conditions are met: |
| mbed_official | 133:d4dda5c437f0 | 105 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 106 | * this list of conditions and the following disclaimer. |
| mbed_official | 133:d4dda5c437f0 | 107 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 108 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 133:d4dda5c437f0 | 109 | * and/or other materials provided with the distribution. |
| mbed_official | 133:d4dda5c437f0 | 110 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 133:d4dda5c437f0 | 111 | * may be used to endorse or promote products derived from this software |
| mbed_official | 133:d4dda5c437f0 | 112 | * without specific prior written permission. |
| mbed_official | 133:d4dda5c437f0 | 113 | * |
| mbed_official | 133:d4dda5c437f0 | 114 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 133:d4dda5c437f0 | 115 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 133:d4dda5c437f0 | 116 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 133:d4dda5c437f0 | 117 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 133:d4dda5c437f0 | 118 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 133:d4dda5c437f0 | 119 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 133:d4dda5c437f0 | 120 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 133:d4dda5c437f0 | 121 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 133:d4dda5c437f0 | 122 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 133:d4dda5c437f0 | 123 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 133:d4dda5c437f0 | 124 | * |
| mbed_official | 133:d4dda5c437f0 | 125 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 126 | */ |
| mbed_official | 133:d4dda5c437f0 | 127 | |
| mbed_official | 133:d4dda5c437f0 | 128 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 129 | #include "stm32f4xx_hal.h" |
| mbed_official | 133:d4dda5c437f0 | 130 | |
| mbed_official | 133:d4dda5c437f0 | 131 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 133:d4dda5c437f0 | 132 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 133 | */ |
| mbed_official | 133:d4dda5c437f0 | 134 | |
| mbed_official | 133:d4dda5c437f0 | 135 | /** @defgroup TIM |
| mbed_official | 133:d4dda5c437f0 | 136 | * @brief TIM HAL module driver |
| mbed_official | 133:d4dda5c437f0 | 137 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 138 | */ |
| mbed_official | 133:d4dda5c437f0 | 139 | |
| mbed_official | 133:d4dda5c437f0 | 140 | #ifdef HAL_TIM_MODULE_ENABLED |
| mbed_official | 133:d4dda5c437f0 | 141 | |
| mbed_official | 133:d4dda5c437f0 | 142 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 143 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 144 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 145 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 146 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 147 | static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 133:d4dda5c437f0 | 148 | static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 133:d4dda5c437f0 | 149 | static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 133:d4dda5c437f0 | 150 | |
| mbed_official | 133:d4dda5c437f0 | 151 | static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 152 | static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 153 | uint32_t TIM_ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 154 | static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 155 | static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 156 | uint32_t TIM_ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 157 | static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 158 | uint32_t TIM_ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 159 | |
| mbed_official | 133:d4dda5c437f0 | 160 | static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, |
| mbed_official | 133:d4dda5c437f0 | 161 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
| mbed_official | 133:d4dda5c437f0 | 162 | |
| mbed_official | 133:d4dda5c437f0 | 163 | static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx); |
| mbed_official | 133:d4dda5c437f0 | 164 | static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 133:d4dda5c437f0 | 165 | static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 133:d4dda5c437f0 | 166 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 167 | |
| mbed_official | 133:d4dda5c437f0 | 168 | /** @defgroup TIM_Private_Functions |
| mbed_official | 133:d4dda5c437f0 | 169 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 170 | */ |
| mbed_official | 133:d4dda5c437f0 | 171 | |
| mbed_official | 133:d4dda5c437f0 | 172 | /** @defgroup TIM_Group1 Time Base functions |
| mbed_official | 133:d4dda5c437f0 | 173 | * @brief Time Base functions |
| mbed_official | 133:d4dda5c437f0 | 174 | * |
| mbed_official | 133:d4dda5c437f0 | 175 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 176 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 177 | ##### Time Base functions ##### |
| mbed_official | 133:d4dda5c437f0 | 178 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 179 | [..] |
| mbed_official | 133:d4dda5c437f0 | 180 | This section provides functions allowing to: |
| mbed_official | 133:d4dda5c437f0 | 181 | (+) Initialize and configure the TIM base. |
| mbed_official | 133:d4dda5c437f0 | 182 | (+) De-initialize the TIM base. |
| mbed_official | 133:d4dda5c437f0 | 183 | (+) Start the Time Base. |
| mbed_official | 133:d4dda5c437f0 | 184 | (+) Stop the Time Base. |
| mbed_official | 133:d4dda5c437f0 | 185 | (+) Start the Time Base and enable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 186 | (+) Stop the Time Base and disable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 187 | (+) Start the Time Base and enable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 188 | (+) Stop the Time Base and disable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 189 | |
| mbed_official | 133:d4dda5c437f0 | 190 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 191 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 192 | */ |
| mbed_official | 133:d4dda5c437f0 | 193 | /** |
| mbed_official | 133:d4dda5c437f0 | 194 | * @brief Initializes the TIM Time base Unit according to the specified |
| mbed_official | 133:d4dda5c437f0 | 195 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 133:d4dda5c437f0 | 196 | * @param htim: TIM Base handle |
| mbed_official | 133:d4dda5c437f0 | 197 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 198 | */ |
| mbed_official | 133:d4dda5c437f0 | 199 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 200 | { |
| mbed_official | 133:d4dda5c437f0 | 201 | /* Check the TIM handle allocation */ |
| mbed_official | 133:d4dda5c437f0 | 202 | if(htim == NULL) |
| mbed_official | 133:d4dda5c437f0 | 203 | { |
| mbed_official | 133:d4dda5c437f0 | 204 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 205 | } |
| mbed_official | 133:d4dda5c437f0 | 206 | |
| mbed_official | 133:d4dda5c437f0 | 207 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 208 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 209 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 133:d4dda5c437f0 | 210 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 133:d4dda5c437f0 | 211 | |
| mbed_official | 133:d4dda5c437f0 | 212 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 133:d4dda5c437f0 | 213 | { |
| mbed_official | 133:d4dda5c437f0 | 214 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| mbed_official | 133:d4dda5c437f0 | 215 | HAL_TIM_Base_MspInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 216 | } |
| mbed_official | 133:d4dda5c437f0 | 217 | |
| mbed_official | 133:d4dda5c437f0 | 218 | /* Set the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 219 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 220 | |
| mbed_official | 133:d4dda5c437f0 | 221 | /* Set the Time Base configuration */ |
| mbed_official | 133:d4dda5c437f0 | 222 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 133:d4dda5c437f0 | 223 | |
| mbed_official | 133:d4dda5c437f0 | 224 | /* Initialize the TIM state*/ |
| mbed_official | 133:d4dda5c437f0 | 225 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 226 | |
| mbed_official | 133:d4dda5c437f0 | 227 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 228 | } |
| mbed_official | 133:d4dda5c437f0 | 229 | |
| mbed_official | 133:d4dda5c437f0 | 230 | /** |
| mbed_official | 133:d4dda5c437f0 | 231 | * @brief DeInitializes the TIM Base peripheral |
| mbed_official | 133:d4dda5c437f0 | 232 | * @param htim: TIM Base handle |
| mbed_official | 133:d4dda5c437f0 | 233 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 234 | */ |
| mbed_official | 133:d4dda5c437f0 | 235 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 236 | { |
| mbed_official | 133:d4dda5c437f0 | 237 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 238 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 239 | |
| mbed_official | 133:d4dda5c437f0 | 240 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 241 | |
| mbed_official | 133:d4dda5c437f0 | 242 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 133:d4dda5c437f0 | 243 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 244 | |
| mbed_official | 133:d4dda5c437f0 | 245 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| mbed_official | 133:d4dda5c437f0 | 246 | HAL_TIM_Base_MspDeInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 247 | |
| mbed_official | 133:d4dda5c437f0 | 248 | /* Change TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 249 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 133:d4dda5c437f0 | 250 | |
| mbed_official | 133:d4dda5c437f0 | 251 | /* Release Lock */ |
| mbed_official | 133:d4dda5c437f0 | 252 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 253 | |
| mbed_official | 133:d4dda5c437f0 | 254 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 255 | } |
| mbed_official | 133:d4dda5c437f0 | 256 | |
| mbed_official | 133:d4dda5c437f0 | 257 | /** |
| mbed_official | 133:d4dda5c437f0 | 258 | * @brief Initializes the TIM Base MSP. |
| mbed_official | 133:d4dda5c437f0 | 259 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 260 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 261 | */ |
| mbed_official | 133:d4dda5c437f0 | 262 | __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 263 | { |
| mbed_official | 133:d4dda5c437f0 | 264 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 265 | the HAL_TIM_Base_MspInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 266 | */ |
| mbed_official | 133:d4dda5c437f0 | 267 | } |
| mbed_official | 133:d4dda5c437f0 | 268 | |
| mbed_official | 133:d4dda5c437f0 | 269 | /** |
| mbed_official | 133:d4dda5c437f0 | 270 | * @brief DeInitializes TIM Base MSP. |
| mbed_official | 133:d4dda5c437f0 | 271 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 272 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 273 | */ |
| mbed_official | 133:d4dda5c437f0 | 274 | __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 275 | { |
| mbed_official | 133:d4dda5c437f0 | 276 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 277 | the HAL_TIM_Base_MspDeInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 278 | */ |
| mbed_official | 133:d4dda5c437f0 | 279 | } |
| mbed_official | 133:d4dda5c437f0 | 280 | |
| mbed_official | 133:d4dda5c437f0 | 281 | /** |
| mbed_official | 133:d4dda5c437f0 | 282 | * @brief Starts the TIM Base generation. |
| mbed_official | 133:d4dda5c437f0 | 283 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 284 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 285 | */ |
| mbed_official | 133:d4dda5c437f0 | 286 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 287 | { |
| mbed_official | 133:d4dda5c437f0 | 288 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 289 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 290 | |
| mbed_official | 133:d4dda5c437f0 | 291 | /* Set the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 292 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 293 | |
| mbed_official | 133:d4dda5c437f0 | 294 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 295 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 296 | |
| mbed_official | 133:d4dda5c437f0 | 297 | /* Change the TIM state*/ |
| mbed_official | 133:d4dda5c437f0 | 298 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 299 | |
| mbed_official | 133:d4dda5c437f0 | 300 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 301 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 302 | } |
| mbed_official | 133:d4dda5c437f0 | 303 | |
| mbed_official | 133:d4dda5c437f0 | 304 | /** |
| mbed_official | 133:d4dda5c437f0 | 305 | * @brief Stops the TIM Base generation. |
| mbed_official | 133:d4dda5c437f0 | 306 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 307 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 308 | */ |
| mbed_official | 133:d4dda5c437f0 | 309 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 310 | { |
| mbed_official | 133:d4dda5c437f0 | 311 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 312 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 313 | |
| mbed_official | 133:d4dda5c437f0 | 314 | /* Set the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 315 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 316 | |
| mbed_official | 133:d4dda5c437f0 | 317 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 318 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 319 | |
| mbed_official | 133:d4dda5c437f0 | 320 | /* Change the TIM state*/ |
| mbed_official | 133:d4dda5c437f0 | 321 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 322 | |
| mbed_official | 133:d4dda5c437f0 | 323 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 324 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 325 | } |
| mbed_official | 133:d4dda5c437f0 | 326 | |
| mbed_official | 133:d4dda5c437f0 | 327 | /** |
| mbed_official | 133:d4dda5c437f0 | 328 | * @brief Starts the TIM Base generation in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 329 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 330 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 331 | */ |
| mbed_official | 133:d4dda5c437f0 | 332 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 333 | { |
| mbed_official | 133:d4dda5c437f0 | 334 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 335 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 336 | |
| mbed_official | 133:d4dda5c437f0 | 337 | /* Enable the TIM Update interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 338 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); |
| mbed_official | 133:d4dda5c437f0 | 339 | |
| mbed_official | 133:d4dda5c437f0 | 340 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 341 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 342 | |
| mbed_official | 133:d4dda5c437f0 | 343 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 344 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 345 | } |
| mbed_official | 133:d4dda5c437f0 | 346 | |
| mbed_official | 133:d4dda5c437f0 | 347 | /** |
| mbed_official | 133:d4dda5c437f0 | 348 | * @brief Stops the TIM Base generation in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 349 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 350 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 351 | */ |
| mbed_official | 133:d4dda5c437f0 | 352 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 353 | { |
| mbed_official | 133:d4dda5c437f0 | 354 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 355 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 356 | /* Disable the TIM Update interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 357 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); |
| mbed_official | 133:d4dda5c437f0 | 358 | |
| mbed_official | 133:d4dda5c437f0 | 359 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 360 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 361 | |
| mbed_official | 133:d4dda5c437f0 | 362 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 363 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 364 | } |
| mbed_official | 133:d4dda5c437f0 | 365 | |
| mbed_official | 133:d4dda5c437f0 | 366 | /** |
| mbed_official | 133:d4dda5c437f0 | 367 | * @brief Starts the TIM Base generation in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 368 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 369 | * @param pData: The source Buffer address. |
| mbed_official | 133:d4dda5c437f0 | 370 | * @param Length: The length of data to be transferred from memory to peripheral. |
| mbed_official | 133:d4dda5c437f0 | 371 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 372 | */ |
| mbed_official | 133:d4dda5c437f0 | 373 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) |
| mbed_official | 133:d4dda5c437f0 | 374 | { |
| mbed_official | 133:d4dda5c437f0 | 375 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 376 | assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 377 | |
| mbed_official | 133:d4dda5c437f0 | 378 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 133:d4dda5c437f0 | 379 | { |
| mbed_official | 133:d4dda5c437f0 | 380 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 381 | } |
| mbed_official | 133:d4dda5c437f0 | 382 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 133:d4dda5c437f0 | 383 | { |
| mbed_official | 133:d4dda5c437f0 | 384 | if((pData == 0 ) && (Length > 0)) |
| mbed_official | 133:d4dda5c437f0 | 385 | { |
| mbed_official | 133:d4dda5c437f0 | 386 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 387 | } |
| mbed_official | 133:d4dda5c437f0 | 388 | else |
| mbed_official | 133:d4dda5c437f0 | 389 | { |
| mbed_official | 133:d4dda5c437f0 | 390 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 391 | } |
| mbed_official | 133:d4dda5c437f0 | 392 | } |
| mbed_official | 133:d4dda5c437f0 | 393 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 394 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; |
| mbed_official | 133:d4dda5c437f0 | 395 | |
| mbed_official | 133:d4dda5c437f0 | 396 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 397 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 398 | |
| mbed_official | 133:d4dda5c437f0 | 399 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 400 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); |
| mbed_official | 133:d4dda5c437f0 | 401 | |
| mbed_official | 133:d4dda5c437f0 | 402 | /* Enable the TIM Update DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 403 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); |
| mbed_official | 133:d4dda5c437f0 | 404 | |
| mbed_official | 133:d4dda5c437f0 | 405 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 406 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 407 | |
| mbed_official | 133:d4dda5c437f0 | 408 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 409 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 410 | } |
| mbed_official | 133:d4dda5c437f0 | 411 | |
| mbed_official | 133:d4dda5c437f0 | 412 | /** |
| mbed_official | 133:d4dda5c437f0 | 413 | * @brief Stops the TIM Base generation in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 414 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 415 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 416 | */ |
| mbed_official | 133:d4dda5c437f0 | 417 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 418 | { |
| mbed_official | 133:d4dda5c437f0 | 419 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 420 | assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 421 | |
| mbed_official | 133:d4dda5c437f0 | 422 | /* Disable the TIM Update DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 423 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); |
| mbed_official | 133:d4dda5c437f0 | 424 | |
| mbed_official | 133:d4dda5c437f0 | 425 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 426 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 427 | |
| mbed_official | 133:d4dda5c437f0 | 428 | /* Change the htim state */ |
| mbed_official | 133:d4dda5c437f0 | 429 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 430 | |
| mbed_official | 133:d4dda5c437f0 | 431 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 432 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 433 | } |
| mbed_official | 133:d4dda5c437f0 | 434 | |
| mbed_official | 133:d4dda5c437f0 | 435 | /** |
| mbed_official | 133:d4dda5c437f0 | 436 | * @} |
| mbed_official | 133:d4dda5c437f0 | 437 | */ |
| mbed_official | 133:d4dda5c437f0 | 438 | |
| mbed_official | 133:d4dda5c437f0 | 439 | /** @defgroup TIM_Group2 Time Output Compare functions |
| mbed_official | 133:d4dda5c437f0 | 440 | * @brief Time Output Compare functions |
| mbed_official | 133:d4dda5c437f0 | 441 | * |
| mbed_official | 133:d4dda5c437f0 | 442 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 443 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 444 | ##### Time Output Compare functions ##### |
| mbed_official | 133:d4dda5c437f0 | 445 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 446 | [..] |
| mbed_official | 133:d4dda5c437f0 | 447 | This section provides functions allowing to: |
| mbed_official | 133:d4dda5c437f0 | 448 | (+) Initialize and configure the TIM Output Compare. |
| mbed_official | 133:d4dda5c437f0 | 449 | (+) De-initialize the TIM Output Compare. |
| mbed_official | 133:d4dda5c437f0 | 450 | (+) Start the Time Output Compare. |
| mbed_official | 133:d4dda5c437f0 | 451 | (+) Stop the Time Output Compare. |
| mbed_official | 133:d4dda5c437f0 | 452 | (+) Start the Time Output Compare and enable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 453 | (+) Stop the Time Output Compare and disable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 454 | (+) Start the Time Output Compare and enable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 455 | (+) Stop the Time Output Compare and disable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 456 | |
| mbed_official | 133:d4dda5c437f0 | 457 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 458 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 459 | */ |
| mbed_official | 133:d4dda5c437f0 | 460 | /** |
| mbed_official | 133:d4dda5c437f0 | 461 | * @brief Initializes the TIM Output Compare according to the specified |
| mbed_official | 133:d4dda5c437f0 | 462 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 133:d4dda5c437f0 | 463 | * @param htim: TIM Output Compare handle |
| mbed_official | 133:d4dda5c437f0 | 464 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 465 | */ |
| mbed_official | 133:d4dda5c437f0 | 466 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) |
| mbed_official | 133:d4dda5c437f0 | 467 | { |
| mbed_official | 133:d4dda5c437f0 | 468 | /* Check the TIM handle allocation */ |
| mbed_official | 133:d4dda5c437f0 | 469 | if(htim == NULL) |
| mbed_official | 133:d4dda5c437f0 | 470 | { |
| mbed_official | 133:d4dda5c437f0 | 471 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 472 | } |
| mbed_official | 133:d4dda5c437f0 | 473 | |
| mbed_official | 133:d4dda5c437f0 | 474 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 475 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 476 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 133:d4dda5c437f0 | 477 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 133:d4dda5c437f0 | 478 | |
| mbed_official | 133:d4dda5c437f0 | 479 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 133:d4dda5c437f0 | 480 | { |
| mbed_official | 133:d4dda5c437f0 | 481 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 133:d4dda5c437f0 | 482 | HAL_TIM_OC_MspInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 483 | } |
| mbed_official | 133:d4dda5c437f0 | 484 | |
| mbed_official | 133:d4dda5c437f0 | 485 | /* Set the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 486 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 487 | |
| mbed_official | 133:d4dda5c437f0 | 488 | /* Init the base time for the Output Compare */ |
| mbed_official | 133:d4dda5c437f0 | 489 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 133:d4dda5c437f0 | 490 | |
| mbed_official | 133:d4dda5c437f0 | 491 | /* Initialize the TIM state*/ |
| mbed_official | 133:d4dda5c437f0 | 492 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 493 | |
| mbed_official | 133:d4dda5c437f0 | 494 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 495 | } |
| mbed_official | 133:d4dda5c437f0 | 496 | |
| mbed_official | 133:d4dda5c437f0 | 497 | /** |
| mbed_official | 133:d4dda5c437f0 | 498 | * @brief DeInitializes the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 499 | * @param htim: TIM Output Compare handle |
| mbed_official | 133:d4dda5c437f0 | 500 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 501 | */ |
| mbed_official | 133:d4dda5c437f0 | 502 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 503 | { |
| mbed_official | 133:d4dda5c437f0 | 504 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 505 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 506 | |
| mbed_official | 133:d4dda5c437f0 | 507 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 508 | |
| mbed_official | 133:d4dda5c437f0 | 509 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 133:d4dda5c437f0 | 510 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 511 | |
| mbed_official | 133:d4dda5c437f0 | 512 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 133:d4dda5c437f0 | 513 | HAL_TIM_OC_MspDeInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 514 | |
| mbed_official | 133:d4dda5c437f0 | 515 | /* Change TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 516 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 133:d4dda5c437f0 | 517 | |
| mbed_official | 133:d4dda5c437f0 | 518 | /* Release Lock */ |
| mbed_official | 133:d4dda5c437f0 | 519 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 520 | |
| mbed_official | 133:d4dda5c437f0 | 521 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 522 | } |
| mbed_official | 133:d4dda5c437f0 | 523 | |
| mbed_official | 133:d4dda5c437f0 | 524 | /** |
| mbed_official | 133:d4dda5c437f0 | 525 | * @brief Initializes the TIM Output Compare MSP. |
| mbed_official | 133:d4dda5c437f0 | 526 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 527 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 528 | */ |
| mbed_official | 133:d4dda5c437f0 | 529 | __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 530 | { |
| mbed_official | 133:d4dda5c437f0 | 531 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 532 | the HAL_TIM_OC_MspInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 533 | */ |
| mbed_official | 133:d4dda5c437f0 | 534 | } |
| mbed_official | 133:d4dda5c437f0 | 535 | |
| mbed_official | 133:d4dda5c437f0 | 536 | /** |
| mbed_official | 133:d4dda5c437f0 | 537 | * @brief DeInitializes TIM Output Compare MSP. |
| mbed_official | 133:d4dda5c437f0 | 538 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 539 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 540 | */ |
| mbed_official | 133:d4dda5c437f0 | 541 | __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 542 | { |
| mbed_official | 133:d4dda5c437f0 | 543 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 544 | the HAL_TIM_OC_MspDeInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 545 | */ |
| mbed_official | 133:d4dda5c437f0 | 546 | } |
| mbed_official | 133:d4dda5c437f0 | 547 | |
| mbed_official | 133:d4dda5c437f0 | 548 | /** |
| mbed_official | 133:d4dda5c437f0 | 549 | * @brief Starts the TIM Output Compare signal generation. |
| mbed_official | 133:d4dda5c437f0 | 550 | * @param htim : TIM Output Compare handle |
| mbed_official | 133:d4dda5c437f0 | 551 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 133:d4dda5c437f0 | 552 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 553 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 554 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 555 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 556 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 557 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 558 | */ |
| mbed_official | 133:d4dda5c437f0 | 559 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 560 | { |
| mbed_official | 133:d4dda5c437f0 | 561 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 562 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 563 | |
| mbed_official | 133:d4dda5c437f0 | 564 | /* Enable the Output compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 565 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 566 | |
| mbed_official | 133:d4dda5c437f0 | 567 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 568 | { |
| mbed_official | 133:d4dda5c437f0 | 569 | /* Enable the main output */ |
| mbed_official | 133:d4dda5c437f0 | 570 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 571 | } |
| mbed_official | 133:d4dda5c437f0 | 572 | |
| mbed_official | 133:d4dda5c437f0 | 573 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 574 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 575 | |
| mbed_official | 133:d4dda5c437f0 | 576 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 577 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 578 | } |
| mbed_official | 133:d4dda5c437f0 | 579 | |
| mbed_official | 133:d4dda5c437f0 | 580 | /** |
| mbed_official | 133:d4dda5c437f0 | 581 | * @brief Stops the TIM Output Compare signal generation. |
| mbed_official | 133:d4dda5c437f0 | 582 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 583 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 133:d4dda5c437f0 | 584 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 585 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 586 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 587 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 588 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 589 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 590 | */ |
| mbed_official | 133:d4dda5c437f0 | 591 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 592 | { |
| mbed_official | 133:d4dda5c437f0 | 593 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 594 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 595 | |
| mbed_official | 133:d4dda5c437f0 | 596 | /* Disable the Output compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 597 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 598 | |
| mbed_official | 133:d4dda5c437f0 | 599 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 600 | { |
| mbed_official | 133:d4dda5c437f0 | 601 | /* Disable the Main Ouput */ |
| mbed_official | 133:d4dda5c437f0 | 602 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 603 | } |
| mbed_official | 133:d4dda5c437f0 | 604 | |
| mbed_official | 133:d4dda5c437f0 | 605 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 606 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 607 | |
| mbed_official | 133:d4dda5c437f0 | 608 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 609 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 610 | } |
| mbed_official | 133:d4dda5c437f0 | 611 | |
| mbed_official | 133:d4dda5c437f0 | 612 | /** |
| mbed_official | 133:d4dda5c437f0 | 613 | * @brief Starts the TIM Output Compare signal generation in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 614 | * @param htim : TIM OC handle |
| mbed_official | 133:d4dda5c437f0 | 615 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 133:d4dda5c437f0 | 616 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 617 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 618 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 619 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 620 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 621 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 622 | */ |
| mbed_official | 133:d4dda5c437f0 | 623 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 624 | { |
| mbed_official | 133:d4dda5c437f0 | 625 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 626 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 627 | |
| mbed_official | 133:d4dda5c437f0 | 628 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 629 | { |
| mbed_official | 133:d4dda5c437f0 | 630 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 631 | { |
| mbed_official | 133:d4dda5c437f0 | 632 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 633 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 634 | } |
| mbed_official | 133:d4dda5c437f0 | 635 | break; |
| mbed_official | 133:d4dda5c437f0 | 636 | |
| mbed_official | 133:d4dda5c437f0 | 637 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 638 | { |
| mbed_official | 133:d4dda5c437f0 | 639 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 640 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 641 | } |
| mbed_official | 133:d4dda5c437f0 | 642 | break; |
| mbed_official | 133:d4dda5c437f0 | 643 | |
| mbed_official | 133:d4dda5c437f0 | 644 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 645 | { |
| mbed_official | 133:d4dda5c437f0 | 646 | /* Enable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 647 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 133:d4dda5c437f0 | 648 | } |
| mbed_official | 133:d4dda5c437f0 | 649 | break; |
| mbed_official | 133:d4dda5c437f0 | 650 | |
| mbed_official | 133:d4dda5c437f0 | 651 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 652 | { |
| mbed_official | 133:d4dda5c437f0 | 653 | /* Enable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 654 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 133:d4dda5c437f0 | 655 | } |
| mbed_official | 133:d4dda5c437f0 | 656 | break; |
| mbed_official | 133:d4dda5c437f0 | 657 | |
| mbed_official | 133:d4dda5c437f0 | 658 | default: |
| mbed_official | 133:d4dda5c437f0 | 659 | break; |
| mbed_official | 133:d4dda5c437f0 | 660 | } |
| mbed_official | 133:d4dda5c437f0 | 661 | |
| mbed_official | 133:d4dda5c437f0 | 662 | /* Enable the Output compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 663 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 664 | |
| mbed_official | 133:d4dda5c437f0 | 665 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 666 | { |
| mbed_official | 133:d4dda5c437f0 | 667 | /* Enable the main output */ |
| mbed_official | 133:d4dda5c437f0 | 668 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 669 | } |
| mbed_official | 133:d4dda5c437f0 | 670 | |
| mbed_official | 133:d4dda5c437f0 | 671 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 672 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 673 | |
| mbed_official | 133:d4dda5c437f0 | 674 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 675 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 676 | } |
| mbed_official | 133:d4dda5c437f0 | 677 | |
| mbed_official | 133:d4dda5c437f0 | 678 | /** |
| mbed_official | 133:d4dda5c437f0 | 679 | * @brief Stops the TIM Output Compare signal generation in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 680 | * @param htim : TIM Output Compare handle |
| mbed_official | 133:d4dda5c437f0 | 681 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 133:d4dda5c437f0 | 682 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 683 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 684 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 685 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 686 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 687 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 688 | */ |
| mbed_official | 133:d4dda5c437f0 | 689 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 690 | { |
| mbed_official | 133:d4dda5c437f0 | 691 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 692 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 693 | |
| mbed_official | 133:d4dda5c437f0 | 694 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 695 | { |
| mbed_official | 133:d4dda5c437f0 | 696 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 697 | { |
| mbed_official | 133:d4dda5c437f0 | 698 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 699 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 700 | } |
| mbed_official | 133:d4dda5c437f0 | 701 | break; |
| mbed_official | 133:d4dda5c437f0 | 702 | |
| mbed_official | 133:d4dda5c437f0 | 703 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 704 | { |
| mbed_official | 133:d4dda5c437f0 | 705 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 706 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 707 | } |
| mbed_official | 133:d4dda5c437f0 | 708 | break; |
| mbed_official | 133:d4dda5c437f0 | 709 | |
| mbed_official | 133:d4dda5c437f0 | 710 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 711 | { |
| mbed_official | 133:d4dda5c437f0 | 712 | /* Disable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 713 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 133:d4dda5c437f0 | 714 | } |
| mbed_official | 133:d4dda5c437f0 | 715 | break; |
| mbed_official | 133:d4dda5c437f0 | 716 | |
| mbed_official | 133:d4dda5c437f0 | 717 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 718 | { |
| mbed_official | 133:d4dda5c437f0 | 719 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 720 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 133:d4dda5c437f0 | 721 | } |
| mbed_official | 133:d4dda5c437f0 | 722 | break; |
| mbed_official | 133:d4dda5c437f0 | 723 | |
| mbed_official | 133:d4dda5c437f0 | 724 | default: |
| mbed_official | 133:d4dda5c437f0 | 725 | break; |
| mbed_official | 133:d4dda5c437f0 | 726 | } |
| mbed_official | 133:d4dda5c437f0 | 727 | |
| mbed_official | 133:d4dda5c437f0 | 728 | /* Disable the Output compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 729 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 730 | |
| mbed_official | 133:d4dda5c437f0 | 731 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 732 | { |
| mbed_official | 133:d4dda5c437f0 | 733 | /* Disable the Main Ouput */ |
| mbed_official | 133:d4dda5c437f0 | 734 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 735 | } |
| mbed_official | 133:d4dda5c437f0 | 736 | |
| mbed_official | 133:d4dda5c437f0 | 737 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 738 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 739 | |
| mbed_official | 133:d4dda5c437f0 | 740 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 741 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 742 | } |
| mbed_official | 133:d4dda5c437f0 | 743 | |
| mbed_official | 133:d4dda5c437f0 | 744 | /** |
| mbed_official | 133:d4dda5c437f0 | 745 | * @brief Starts the TIM Output Compare signal generation in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 746 | * @param htim : TIM Output Compare handle |
| mbed_official | 133:d4dda5c437f0 | 747 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 133:d4dda5c437f0 | 748 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 749 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 750 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 751 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 752 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 753 | * @param pData: The source Buffer address. |
| mbed_official | 133:d4dda5c437f0 | 754 | * @param Length: The length of data to be transferred from memory to TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 755 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 756 | */ |
| mbed_official | 133:d4dda5c437f0 | 757 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| mbed_official | 133:d4dda5c437f0 | 758 | { |
| mbed_official | 133:d4dda5c437f0 | 759 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 760 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 761 | |
| mbed_official | 133:d4dda5c437f0 | 762 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 133:d4dda5c437f0 | 763 | { |
| mbed_official | 133:d4dda5c437f0 | 764 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 765 | } |
| mbed_official | 133:d4dda5c437f0 | 766 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 133:d4dda5c437f0 | 767 | { |
| mbed_official | 133:d4dda5c437f0 | 768 | if(((uint32_t)pData == 0 ) && (Length > 0)) |
| mbed_official | 133:d4dda5c437f0 | 769 | { |
| mbed_official | 133:d4dda5c437f0 | 770 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 771 | } |
| mbed_official | 133:d4dda5c437f0 | 772 | else |
| mbed_official | 133:d4dda5c437f0 | 773 | { |
| mbed_official | 133:d4dda5c437f0 | 774 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 775 | } |
| mbed_official | 133:d4dda5c437f0 | 776 | } |
| mbed_official | 133:d4dda5c437f0 | 777 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 778 | { |
| mbed_official | 133:d4dda5c437f0 | 779 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 780 | { |
| mbed_official | 133:d4dda5c437f0 | 781 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 782 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 783 | |
| mbed_official | 133:d4dda5c437f0 | 784 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 785 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 786 | |
| mbed_official | 133:d4dda5c437f0 | 787 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 788 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); |
| mbed_official | 133:d4dda5c437f0 | 789 | |
| mbed_official | 133:d4dda5c437f0 | 790 | /* Enable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 791 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 792 | } |
| mbed_official | 133:d4dda5c437f0 | 793 | break; |
| mbed_official | 133:d4dda5c437f0 | 794 | |
| mbed_official | 133:d4dda5c437f0 | 795 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 796 | { |
| mbed_official | 133:d4dda5c437f0 | 797 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 798 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 799 | |
| mbed_official | 133:d4dda5c437f0 | 800 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 801 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 802 | |
| mbed_official | 133:d4dda5c437f0 | 803 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 804 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); |
| mbed_official | 133:d4dda5c437f0 | 805 | |
| mbed_official | 133:d4dda5c437f0 | 806 | /* Enable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 807 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 808 | } |
| mbed_official | 133:d4dda5c437f0 | 809 | break; |
| mbed_official | 133:d4dda5c437f0 | 810 | |
| mbed_official | 133:d4dda5c437f0 | 811 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 812 | { |
| mbed_official | 133:d4dda5c437f0 | 813 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 814 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 815 | |
| mbed_official | 133:d4dda5c437f0 | 816 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 817 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 818 | |
| mbed_official | 133:d4dda5c437f0 | 819 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 820 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); |
| mbed_official | 133:d4dda5c437f0 | 821 | |
| mbed_official | 133:d4dda5c437f0 | 822 | /* Enable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 823 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 133:d4dda5c437f0 | 824 | } |
| mbed_official | 133:d4dda5c437f0 | 825 | break; |
| mbed_official | 133:d4dda5c437f0 | 826 | |
| mbed_official | 133:d4dda5c437f0 | 827 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 828 | { |
| mbed_official | 133:d4dda5c437f0 | 829 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 830 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 831 | |
| mbed_official | 133:d4dda5c437f0 | 832 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 833 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 834 | |
| mbed_official | 133:d4dda5c437f0 | 835 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 836 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); |
| mbed_official | 133:d4dda5c437f0 | 837 | |
| mbed_official | 133:d4dda5c437f0 | 838 | /* Enable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 839 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 133:d4dda5c437f0 | 840 | } |
| mbed_official | 133:d4dda5c437f0 | 841 | break; |
| mbed_official | 133:d4dda5c437f0 | 842 | |
| mbed_official | 133:d4dda5c437f0 | 843 | default: |
| mbed_official | 133:d4dda5c437f0 | 844 | break; |
| mbed_official | 133:d4dda5c437f0 | 845 | } |
| mbed_official | 133:d4dda5c437f0 | 846 | |
| mbed_official | 133:d4dda5c437f0 | 847 | /* Enable the Output compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 848 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 849 | |
| mbed_official | 133:d4dda5c437f0 | 850 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 851 | { |
| mbed_official | 133:d4dda5c437f0 | 852 | /* Enable the main output */ |
| mbed_official | 133:d4dda5c437f0 | 853 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 854 | } |
| mbed_official | 133:d4dda5c437f0 | 855 | |
| mbed_official | 133:d4dda5c437f0 | 856 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 857 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 858 | |
| mbed_official | 133:d4dda5c437f0 | 859 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 860 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 861 | } |
| mbed_official | 133:d4dda5c437f0 | 862 | |
| mbed_official | 133:d4dda5c437f0 | 863 | /** |
| mbed_official | 133:d4dda5c437f0 | 864 | * @brief Stops the TIM Output Compare signal generation in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 865 | * @param htim : TIM Output Compare handle |
| mbed_official | 133:d4dda5c437f0 | 866 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 133:d4dda5c437f0 | 867 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 868 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 869 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 870 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 871 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 872 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 873 | */ |
| mbed_official | 133:d4dda5c437f0 | 874 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 875 | { |
| mbed_official | 133:d4dda5c437f0 | 876 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 877 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 878 | |
| mbed_official | 133:d4dda5c437f0 | 879 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 880 | { |
| mbed_official | 133:d4dda5c437f0 | 881 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 882 | { |
| mbed_official | 133:d4dda5c437f0 | 883 | /* Disable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 884 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 885 | } |
| mbed_official | 133:d4dda5c437f0 | 886 | break; |
| mbed_official | 133:d4dda5c437f0 | 887 | |
| mbed_official | 133:d4dda5c437f0 | 888 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 889 | { |
| mbed_official | 133:d4dda5c437f0 | 890 | /* Disable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 891 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 892 | } |
| mbed_official | 133:d4dda5c437f0 | 893 | break; |
| mbed_official | 133:d4dda5c437f0 | 894 | |
| mbed_official | 133:d4dda5c437f0 | 895 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 896 | { |
| mbed_official | 133:d4dda5c437f0 | 897 | /* Disable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 898 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 133:d4dda5c437f0 | 899 | } |
| mbed_official | 133:d4dda5c437f0 | 900 | break; |
| mbed_official | 133:d4dda5c437f0 | 901 | |
| mbed_official | 133:d4dda5c437f0 | 902 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 903 | { |
| mbed_official | 133:d4dda5c437f0 | 904 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 905 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 133:d4dda5c437f0 | 906 | } |
| mbed_official | 133:d4dda5c437f0 | 907 | break; |
| mbed_official | 133:d4dda5c437f0 | 908 | |
| mbed_official | 133:d4dda5c437f0 | 909 | default: |
| mbed_official | 133:d4dda5c437f0 | 910 | break; |
| mbed_official | 133:d4dda5c437f0 | 911 | } |
| mbed_official | 133:d4dda5c437f0 | 912 | |
| mbed_official | 133:d4dda5c437f0 | 913 | /* Disable the Output compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 914 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 915 | |
| mbed_official | 133:d4dda5c437f0 | 916 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 917 | { |
| mbed_official | 133:d4dda5c437f0 | 918 | /* Disable the Main Ouput */ |
| mbed_official | 133:d4dda5c437f0 | 919 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 920 | } |
| mbed_official | 133:d4dda5c437f0 | 921 | |
| mbed_official | 133:d4dda5c437f0 | 922 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 923 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 924 | |
| mbed_official | 133:d4dda5c437f0 | 925 | /* Change the htim state */ |
| mbed_official | 133:d4dda5c437f0 | 926 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 927 | |
| mbed_official | 133:d4dda5c437f0 | 928 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 929 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 930 | } |
| mbed_official | 133:d4dda5c437f0 | 931 | |
| mbed_official | 133:d4dda5c437f0 | 932 | /** |
| mbed_official | 133:d4dda5c437f0 | 933 | * @} |
| mbed_official | 133:d4dda5c437f0 | 934 | */ |
| mbed_official | 133:d4dda5c437f0 | 935 | |
| mbed_official | 133:d4dda5c437f0 | 936 | /** @defgroup TIM_Group3 Time PWM functions |
| mbed_official | 133:d4dda5c437f0 | 937 | * @brief Time PWM functions |
| mbed_official | 133:d4dda5c437f0 | 938 | * |
| mbed_official | 133:d4dda5c437f0 | 939 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 940 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 941 | ##### Time PWM functions ##### |
| mbed_official | 133:d4dda5c437f0 | 942 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 943 | [..] |
| mbed_official | 133:d4dda5c437f0 | 944 | This section provides functions allowing to: |
| mbed_official | 133:d4dda5c437f0 | 945 | (+) Initialize and configure the TIM OPWM. |
| mbed_official | 133:d4dda5c437f0 | 946 | (+) De-initialize the TIM PWM. |
| mbed_official | 133:d4dda5c437f0 | 947 | (+) Start the Time PWM. |
| mbed_official | 133:d4dda5c437f0 | 948 | (+) Stop the Time PWM. |
| mbed_official | 133:d4dda5c437f0 | 949 | (+) Start the Time PWM and enable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 950 | (+) Stop the Time PWM and disable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 951 | (+) Start the Time PWM and enable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 952 | (+) Stop the Time PWM and disable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 953 | |
| mbed_official | 133:d4dda5c437f0 | 954 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 955 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 956 | */ |
| mbed_official | 133:d4dda5c437f0 | 957 | /** |
| mbed_official | 133:d4dda5c437f0 | 958 | * @brief Initializes the TIM PWM Time Base according to the specified |
| mbed_official | 133:d4dda5c437f0 | 959 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 133:d4dda5c437f0 | 960 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 961 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 962 | */ |
| mbed_official | 133:d4dda5c437f0 | 963 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 964 | { |
| mbed_official | 133:d4dda5c437f0 | 965 | /* Check the TIM handle allocation */ |
| mbed_official | 133:d4dda5c437f0 | 966 | if(htim == NULL) |
| mbed_official | 133:d4dda5c437f0 | 967 | { |
| mbed_official | 133:d4dda5c437f0 | 968 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 969 | } |
| mbed_official | 133:d4dda5c437f0 | 970 | |
| mbed_official | 133:d4dda5c437f0 | 971 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 972 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 973 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 133:d4dda5c437f0 | 974 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 133:d4dda5c437f0 | 975 | |
| mbed_official | 133:d4dda5c437f0 | 976 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 133:d4dda5c437f0 | 977 | { |
| mbed_official | 133:d4dda5c437f0 | 978 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 133:d4dda5c437f0 | 979 | HAL_TIM_PWM_MspInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 980 | } |
| mbed_official | 133:d4dda5c437f0 | 981 | |
| mbed_official | 133:d4dda5c437f0 | 982 | /* Set the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 983 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 984 | |
| mbed_official | 133:d4dda5c437f0 | 985 | /* Init the base time for the PWM */ |
| mbed_official | 133:d4dda5c437f0 | 986 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 133:d4dda5c437f0 | 987 | |
| mbed_official | 133:d4dda5c437f0 | 988 | /* Initialize the TIM state*/ |
| mbed_official | 133:d4dda5c437f0 | 989 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 990 | |
| mbed_official | 133:d4dda5c437f0 | 991 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 992 | } |
| mbed_official | 133:d4dda5c437f0 | 993 | |
| mbed_official | 133:d4dda5c437f0 | 994 | /** |
| mbed_official | 133:d4dda5c437f0 | 995 | * @brief DeInitializes the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 996 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 997 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 998 | */ |
| mbed_official | 133:d4dda5c437f0 | 999 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 1000 | { |
| mbed_official | 133:d4dda5c437f0 | 1001 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1002 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 1003 | |
| mbed_official | 133:d4dda5c437f0 | 1004 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1005 | |
| mbed_official | 133:d4dda5c437f0 | 1006 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 133:d4dda5c437f0 | 1007 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1008 | |
| mbed_official | 133:d4dda5c437f0 | 1009 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 133:d4dda5c437f0 | 1010 | HAL_TIM_PWM_MspDeInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 1011 | |
| mbed_official | 133:d4dda5c437f0 | 1012 | /* Change TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 1013 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 133:d4dda5c437f0 | 1014 | |
| mbed_official | 133:d4dda5c437f0 | 1015 | /* Release Lock */ |
| mbed_official | 133:d4dda5c437f0 | 1016 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 1017 | |
| mbed_official | 133:d4dda5c437f0 | 1018 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1019 | } |
| mbed_official | 133:d4dda5c437f0 | 1020 | |
| mbed_official | 133:d4dda5c437f0 | 1021 | /** |
| mbed_official | 133:d4dda5c437f0 | 1022 | * @brief Initializes the TIM PWM MSP. |
| mbed_official | 133:d4dda5c437f0 | 1023 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1024 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 1025 | */ |
| mbed_official | 133:d4dda5c437f0 | 1026 | __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 1027 | { |
| mbed_official | 133:d4dda5c437f0 | 1028 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 1029 | the HAL_TIM_PWM_MspInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 1030 | */ |
| mbed_official | 133:d4dda5c437f0 | 1031 | } |
| mbed_official | 133:d4dda5c437f0 | 1032 | |
| mbed_official | 133:d4dda5c437f0 | 1033 | /** |
| mbed_official | 133:d4dda5c437f0 | 1034 | * @brief DeInitializes TIM PWM MSP. |
| mbed_official | 133:d4dda5c437f0 | 1035 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1036 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 1037 | */ |
| mbed_official | 133:d4dda5c437f0 | 1038 | __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 1039 | { |
| mbed_official | 133:d4dda5c437f0 | 1040 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 1041 | the HAL_TIM_PWM_MspDeInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 1042 | */ |
| mbed_official | 133:d4dda5c437f0 | 1043 | } |
| mbed_official | 133:d4dda5c437f0 | 1044 | |
| mbed_official | 133:d4dda5c437f0 | 1045 | /** |
| mbed_official | 133:d4dda5c437f0 | 1046 | * @brief Starts the PWM signal generation. |
| mbed_official | 133:d4dda5c437f0 | 1047 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1048 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 1049 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1050 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1051 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1052 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1053 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1054 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1055 | */ |
| mbed_official | 133:d4dda5c437f0 | 1056 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1057 | { |
| mbed_official | 133:d4dda5c437f0 | 1058 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1059 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1060 | |
| mbed_official | 133:d4dda5c437f0 | 1061 | /* Enable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 1062 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 1063 | |
| mbed_official | 133:d4dda5c437f0 | 1064 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 1065 | { |
| mbed_official | 133:d4dda5c437f0 | 1066 | /* Enable the main output */ |
| mbed_official | 133:d4dda5c437f0 | 1067 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1068 | } |
| mbed_official | 133:d4dda5c437f0 | 1069 | |
| mbed_official | 133:d4dda5c437f0 | 1070 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1071 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1072 | |
| mbed_official | 133:d4dda5c437f0 | 1073 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1074 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1075 | } |
| mbed_official | 133:d4dda5c437f0 | 1076 | |
| mbed_official | 133:d4dda5c437f0 | 1077 | /** |
| mbed_official | 133:d4dda5c437f0 | 1078 | * @brief Stops the PWM signal generation. |
| mbed_official | 133:d4dda5c437f0 | 1079 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1080 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 133:d4dda5c437f0 | 1081 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1082 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1083 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1084 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1085 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1086 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1087 | */ |
| mbed_official | 133:d4dda5c437f0 | 1088 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1089 | { |
| mbed_official | 133:d4dda5c437f0 | 1090 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1091 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1092 | |
| mbed_official | 133:d4dda5c437f0 | 1093 | /* Disable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 1094 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 1095 | |
| mbed_official | 133:d4dda5c437f0 | 1096 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 1097 | { |
| mbed_official | 133:d4dda5c437f0 | 1098 | /* Disable the Main Ouput */ |
| mbed_official | 133:d4dda5c437f0 | 1099 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1100 | } |
| mbed_official | 133:d4dda5c437f0 | 1101 | |
| mbed_official | 133:d4dda5c437f0 | 1102 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1103 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1104 | |
| mbed_official | 133:d4dda5c437f0 | 1105 | /* Change the htim state */ |
| mbed_official | 133:d4dda5c437f0 | 1106 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 1107 | |
| mbed_official | 133:d4dda5c437f0 | 1108 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1109 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1110 | } |
| mbed_official | 133:d4dda5c437f0 | 1111 | |
| mbed_official | 133:d4dda5c437f0 | 1112 | /** |
| mbed_official | 133:d4dda5c437f0 | 1113 | * @brief Starts the PWM signal generation in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 1114 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1115 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 133:d4dda5c437f0 | 1116 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1117 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1118 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1119 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1120 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1121 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1122 | */ |
| mbed_official | 133:d4dda5c437f0 | 1123 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1124 | { |
| mbed_official | 133:d4dda5c437f0 | 1125 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1126 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1127 | |
| mbed_official | 133:d4dda5c437f0 | 1128 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 1129 | { |
| mbed_official | 133:d4dda5c437f0 | 1130 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 1131 | { |
| mbed_official | 133:d4dda5c437f0 | 1132 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1133 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 1134 | } |
| mbed_official | 133:d4dda5c437f0 | 1135 | break; |
| mbed_official | 133:d4dda5c437f0 | 1136 | |
| mbed_official | 133:d4dda5c437f0 | 1137 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 1138 | { |
| mbed_official | 133:d4dda5c437f0 | 1139 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1140 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 1141 | } |
| mbed_official | 133:d4dda5c437f0 | 1142 | break; |
| mbed_official | 133:d4dda5c437f0 | 1143 | |
| mbed_official | 133:d4dda5c437f0 | 1144 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 1145 | { |
| mbed_official | 133:d4dda5c437f0 | 1146 | /* Enable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1147 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 133:d4dda5c437f0 | 1148 | } |
| mbed_official | 133:d4dda5c437f0 | 1149 | break; |
| mbed_official | 133:d4dda5c437f0 | 1150 | |
| mbed_official | 133:d4dda5c437f0 | 1151 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 1152 | { |
| mbed_official | 133:d4dda5c437f0 | 1153 | /* Enable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1154 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 133:d4dda5c437f0 | 1155 | } |
| mbed_official | 133:d4dda5c437f0 | 1156 | break; |
| mbed_official | 133:d4dda5c437f0 | 1157 | |
| mbed_official | 133:d4dda5c437f0 | 1158 | default: |
| mbed_official | 133:d4dda5c437f0 | 1159 | break; |
| mbed_official | 133:d4dda5c437f0 | 1160 | } |
| mbed_official | 133:d4dda5c437f0 | 1161 | |
| mbed_official | 133:d4dda5c437f0 | 1162 | /* Enable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 1163 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 1164 | |
| mbed_official | 133:d4dda5c437f0 | 1165 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 1166 | { |
| mbed_official | 133:d4dda5c437f0 | 1167 | /* Enable the main output */ |
| mbed_official | 133:d4dda5c437f0 | 1168 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1169 | } |
| mbed_official | 133:d4dda5c437f0 | 1170 | |
| mbed_official | 133:d4dda5c437f0 | 1171 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1172 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1173 | |
| mbed_official | 133:d4dda5c437f0 | 1174 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1175 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1176 | } |
| mbed_official | 133:d4dda5c437f0 | 1177 | |
| mbed_official | 133:d4dda5c437f0 | 1178 | /** |
| mbed_official | 133:d4dda5c437f0 | 1179 | * @brief Stops the PWM signal generation in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 1180 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1181 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 133:d4dda5c437f0 | 1182 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1183 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1184 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1185 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1186 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1187 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1188 | */ |
| mbed_official | 133:d4dda5c437f0 | 1189 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1190 | { |
| mbed_official | 133:d4dda5c437f0 | 1191 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1192 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1193 | |
| mbed_official | 133:d4dda5c437f0 | 1194 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 1195 | { |
| mbed_official | 133:d4dda5c437f0 | 1196 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 1197 | { |
| mbed_official | 133:d4dda5c437f0 | 1198 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1199 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 1200 | } |
| mbed_official | 133:d4dda5c437f0 | 1201 | break; |
| mbed_official | 133:d4dda5c437f0 | 1202 | |
| mbed_official | 133:d4dda5c437f0 | 1203 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 1204 | { |
| mbed_official | 133:d4dda5c437f0 | 1205 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1206 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 1207 | } |
| mbed_official | 133:d4dda5c437f0 | 1208 | break; |
| mbed_official | 133:d4dda5c437f0 | 1209 | |
| mbed_official | 133:d4dda5c437f0 | 1210 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 1211 | { |
| mbed_official | 133:d4dda5c437f0 | 1212 | /* Disable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1213 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 133:d4dda5c437f0 | 1214 | } |
| mbed_official | 133:d4dda5c437f0 | 1215 | break; |
| mbed_official | 133:d4dda5c437f0 | 1216 | |
| mbed_official | 133:d4dda5c437f0 | 1217 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 1218 | { |
| mbed_official | 133:d4dda5c437f0 | 1219 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1220 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 133:d4dda5c437f0 | 1221 | } |
| mbed_official | 133:d4dda5c437f0 | 1222 | break; |
| mbed_official | 133:d4dda5c437f0 | 1223 | |
| mbed_official | 133:d4dda5c437f0 | 1224 | default: |
| mbed_official | 133:d4dda5c437f0 | 1225 | break; |
| mbed_official | 133:d4dda5c437f0 | 1226 | } |
| mbed_official | 133:d4dda5c437f0 | 1227 | |
| mbed_official | 133:d4dda5c437f0 | 1228 | /* Disable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 1229 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 1230 | |
| mbed_official | 133:d4dda5c437f0 | 1231 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 1232 | { |
| mbed_official | 133:d4dda5c437f0 | 1233 | /* Disable the Main Ouput */ |
| mbed_official | 133:d4dda5c437f0 | 1234 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1235 | } |
| mbed_official | 133:d4dda5c437f0 | 1236 | |
| mbed_official | 133:d4dda5c437f0 | 1237 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1238 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1239 | |
| mbed_official | 133:d4dda5c437f0 | 1240 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1241 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1242 | } |
| mbed_official | 133:d4dda5c437f0 | 1243 | |
| mbed_official | 133:d4dda5c437f0 | 1244 | /** |
| mbed_official | 133:d4dda5c437f0 | 1245 | * @brief Starts the TIM PWM signal generation in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 1246 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1247 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 1248 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1249 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1250 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1251 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1252 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1253 | * @param pData: The source Buffer address. |
| mbed_official | 133:d4dda5c437f0 | 1254 | * @param Length: The length of data to be transferred from memory to TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 1255 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1256 | */ |
| mbed_official | 133:d4dda5c437f0 | 1257 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| mbed_official | 133:d4dda5c437f0 | 1258 | { |
| mbed_official | 133:d4dda5c437f0 | 1259 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1260 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1261 | |
| mbed_official | 133:d4dda5c437f0 | 1262 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 133:d4dda5c437f0 | 1263 | { |
| mbed_official | 133:d4dda5c437f0 | 1264 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1265 | } |
| mbed_official | 133:d4dda5c437f0 | 1266 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 133:d4dda5c437f0 | 1267 | { |
| mbed_official | 133:d4dda5c437f0 | 1268 | if(((uint32_t)pData == 0 ) && (Length > 0)) |
| mbed_official | 133:d4dda5c437f0 | 1269 | { |
| mbed_official | 133:d4dda5c437f0 | 1270 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 1271 | } |
| mbed_official | 133:d4dda5c437f0 | 1272 | else |
| mbed_official | 133:d4dda5c437f0 | 1273 | { |
| mbed_official | 133:d4dda5c437f0 | 1274 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1275 | } |
| mbed_official | 133:d4dda5c437f0 | 1276 | } |
| mbed_official | 133:d4dda5c437f0 | 1277 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 1278 | { |
| mbed_official | 133:d4dda5c437f0 | 1279 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 1280 | { |
| mbed_official | 133:d4dda5c437f0 | 1281 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 1282 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 1283 | |
| mbed_official | 133:d4dda5c437f0 | 1284 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 1285 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 1286 | |
| mbed_official | 133:d4dda5c437f0 | 1287 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 1288 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); |
| mbed_official | 133:d4dda5c437f0 | 1289 | |
| mbed_official | 133:d4dda5c437f0 | 1290 | /* Enable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1291 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 1292 | } |
| mbed_official | 133:d4dda5c437f0 | 1293 | break; |
| mbed_official | 133:d4dda5c437f0 | 1294 | |
| mbed_official | 133:d4dda5c437f0 | 1295 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 1296 | { |
| mbed_official | 133:d4dda5c437f0 | 1297 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 1298 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 1299 | |
| mbed_official | 133:d4dda5c437f0 | 1300 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 1301 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 1302 | |
| mbed_official | 133:d4dda5c437f0 | 1303 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 1304 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); |
| mbed_official | 133:d4dda5c437f0 | 1305 | |
| mbed_official | 133:d4dda5c437f0 | 1306 | /* Enable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1307 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 1308 | } |
| mbed_official | 133:d4dda5c437f0 | 1309 | break; |
| mbed_official | 133:d4dda5c437f0 | 1310 | |
| mbed_official | 133:d4dda5c437f0 | 1311 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 1312 | { |
| mbed_official | 133:d4dda5c437f0 | 1313 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 1314 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 1315 | |
| mbed_official | 133:d4dda5c437f0 | 1316 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 1317 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 1318 | |
| mbed_official | 133:d4dda5c437f0 | 1319 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 1320 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); |
| mbed_official | 133:d4dda5c437f0 | 1321 | |
| mbed_official | 133:d4dda5c437f0 | 1322 | /* Enable the TIM Output Capture/Compare 3 request */ |
| mbed_official | 133:d4dda5c437f0 | 1323 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 133:d4dda5c437f0 | 1324 | } |
| mbed_official | 133:d4dda5c437f0 | 1325 | break; |
| mbed_official | 133:d4dda5c437f0 | 1326 | |
| mbed_official | 133:d4dda5c437f0 | 1327 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 1328 | { |
| mbed_official | 133:d4dda5c437f0 | 1329 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 1330 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 1331 | |
| mbed_official | 133:d4dda5c437f0 | 1332 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 1333 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 1334 | |
| mbed_official | 133:d4dda5c437f0 | 1335 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 1336 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); |
| mbed_official | 133:d4dda5c437f0 | 1337 | |
| mbed_official | 133:d4dda5c437f0 | 1338 | /* Enable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1339 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 133:d4dda5c437f0 | 1340 | } |
| mbed_official | 133:d4dda5c437f0 | 1341 | break; |
| mbed_official | 133:d4dda5c437f0 | 1342 | |
| mbed_official | 133:d4dda5c437f0 | 1343 | default: |
| mbed_official | 133:d4dda5c437f0 | 1344 | break; |
| mbed_official | 133:d4dda5c437f0 | 1345 | } |
| mbed_official | 133:d4dda5c437f0 | 1346 | |
| mbed_official | 133:d4dda5c437f0 | 1347 | /* Enable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 1348 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 1349 | |
| mbed_official | 133:d4dda5c437f0 | 1350 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 1351 | { |
| mbed_official | 133:d4dda5c437f0 | 1352 | /* Enable the main output */ |
| mbed_official | 133:d4dda5c437f0 | 1353 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1354 | } |
| mbed_official | 133:d4dda5c437f0 | 1355 | |
| mbed_official | 133:d4dda5c437f0 | 1356 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1357 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1358 | |
| mbed_official | 133:d4dda5c437f0 | 1359 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1360 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1361 | } |
| mbed_official | 133:d4dda5c437f0 | 1362 | |
| mbed_official | 133:d4dda5c437f0 | 1363 | /** |
| mbed_official | 133:d4dda5c437f0 | 1364 | * @brief Stops the TIM PWM signal generation in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 1365 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1366 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 133:d4dda5c437f0 | 1367 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1368 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1369 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1370 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1371 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1372 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1373 | */ |
| mbed_official | 133:d4dda5c437f0 | 1374 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1375 | { |
| mbed_official | 133:d4dda5c437f0 | 1376 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1377 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1378 | |
| mbed_official | 133:d4dda5c437f0 | 1379 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 1380 | { |
| mbed_official | 133:d4dda5c437f0 | 1381 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 1382 | { |
| mbed_official | 133:d4dda5c437f0 | 1383 | /* Disable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1384 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 1385 | } |
| mbed_official | 133:d4dda5c437f0 | 1386 | break; |
| mbed_official | 133:d4dda5c437f0 | 1387 | |
| mbed_official | 133:d4dda5c437f0 | 1388 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 1389 | { |
| mbed_official | 133:d4dda5c437f0 | 1390 | /* Disable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1391 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 1392 | } |
| mbed_official | 133:d4dda5c437f0 | 1393 | break; |
| mbed_official | 133:d4dda5c437f0 | 1394 | |
| mbed_official | 133:d4dda5c437f0 | 1395 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 1396 | { |
| mbed_official | 133:d4dda5c437f0 | 1397 | /* Disable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1398 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 133:d4dda5c437f0 | 1399 | } |
| mbed_official | 133:d4dda5c437f0 | 1400 | break; |
| mbed_official | 133:d4dda5c437f0 | 1401 | |
| mbed_official | 133:d4dda5c437f0 | 1402 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 1403 | { |
| mbed_official | 133:d4dda5c437f0 | 1404 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1405 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 133:d4dda5c437f0 | 1406 | } |
| mbed_official | 133:d4dda5c437f0 | 1407 | break; |
| mbed_official | 133:d4dda5c437f0 | 1408 | |
| mbed_official | 133:d4dda5c437f0 | 1409 | default: |
| mbed_official | 133:d4dda5c437f0 | 1410 | break; |
| mbed_official | 133:d4dda5c437f0 | 1411 | } |
| mbed_official | 133:d4dda5c437f0 | 1412 | |
| mbed_official | 133:d4dda5c437f0 | 1413 | /* Disable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 1414 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 1415 | |
| mbed_official | 133:d4dda5c437f0 | 1416 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 1417 | { |
| mbed_official | 133:d4dda5c437f0 | 1418 | /* Disable the Main Ouput */ |
| mbed_official | 133:d4dda5c437f0 | 1419 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1420 | } |
| mbed_official | 133:d4dda5c437f0 | 1421 | |
| mbed_official | 133:d4dda5c437f0 | 1422 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1423 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1424 | |
| mbed_official | 133:d4dda5c437f0 | 1425 | /* Change the htim state */ |
| mbed_official | 133:d4dda5c437f0 | 1426 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 1427 | |
| mbed_official | 133:d4dda5c437f0 | 1428 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1429 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1430 | } |
| mbed_official | 133:d4dda5c437f0 | 1431 | |
| mbed_official | 133:d4dda5c437f0 | 1432 | /** |
| mbed_official | 133:d4dda5c437f0 | 1433 | * @} |
| mbed_official | 133:d4dda5c437f0 | 1434 | */ |
| mbed_official | 133:d4dda5c437f0 | 1435 | |
| mbed_official | 133:d4dda5c437f0 | 1436 | /** @defgroup TIM_Group4 Time Input Capture functions |
| mbed_official | 133:d4dda5c437f0 | 1437 | * @brief Time Input Capture functions |
| mbed_official | 133:d4dda5c437f0 | 1438 | * |
| mbed_official | 133:d4dda5c437f0 | 1439 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 1440 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 1441 | ##### Time Input Capture functions ##### |
| mbed_official | 133:d4dda5c437f0 | 1442 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 1443 | [..] |
| mbed_official | 133:d4dda5c437f0 | 1444 | This section provides functions allowing to: |
| mbed_official | 133:d4dda5c437f0 | 1445 | (+) Initialize and configure the TIM Input Capture. |
| mbed_official | 133:d4dda5c437f0 | 1446 | (+) De-initialize the TIM Input Capture. |
| mbed_official | 133:d4dda5c437f0 | 1447 | (+) Start the Time Input Capture. |
| mbed_official | 133:d4dda5c437f0 | 1448 | (+) Stop the Time Input Capture. |
| mbed_official | 133:d4dda5c437f0 | 1449 | (+) Start the Time Input Capture and enable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 1450 | (+) Stop the Time Input Capture and disable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 1451 | (+) Start the Time Input Capture and enable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 1452 | (+) Stop the Time Input Capture and disable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 1453 | |
| mbed_official | 133:d4dda5c437f0 | 1454 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 1455 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 1456 | */ |
| mbed_official | 133:d4dda5c437f0 | 1457 | /** |
| mbed_official | 133:d4dda5c437f0 | 1458 | * @brief Initializes the TIM Input Capture Time base according to the specified |
| mbed_official | 133:d4dda5c437f0 | 1459 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 133:d4dda5c437f0 | 1460 | * @param htim: TIM Input Capture handle |
| mbed_official | 133:d4dda5c437f0 | 1461 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1462 | */ |
| mbed_official | 133:d4dda5c437f0 | 1463 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 1464 | { |
| mbed_official | 133:d4dda5c437f0 | 1465 | /* Check the TIM handle allocation */ |
| mbed_official | 133:d4dda5c437f0 | 1466 | if(htim == NULL) |
| mbed_official | 133:d4dda5c437f0 | 1467 | { |
| mbed_official | 133:d4dda5c437f0 | 1468 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 1469 | } |
| mbed_official | 133:d4dda5c437f0 | 1470 | |
| mbed_official | 133:d4dda5c437f0 | 1471 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1472 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 1473 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 133:d4dda5c437f0 | 1474 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 133:d4dda5c437f0 | 1475 | |
| mbed_official | 133:d4dda5c437f0 | 1476 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 133:d4dda5c437f0 | 1477 | { |
| mbed_official | 133:d4dda5c437f0 | 1478 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 133:d4dda5c437f0 | 1479 | HAL_TIM_IC_MspInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 1480 | } |
| mbed_official | 133:d4dda5c437f0 | 1481 | |
| mbed_official | 133:d4dda5c437f0 | 1482 | /* Set the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 1483 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1484 | |
| mbed_official | 133:d4dda5c437f0 | 1485 | /* Init the base time for the input capture */ |
| mbed_official | 133:d4dda5c437f0 | 1486 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 133:d4dda5c437f0 | 1487 | |
| mbed_official | 133:d4dda5c437f0 | 1488 | /* Initialize the TIM state*/ |
| mbed_official | 133:d4dda5c437f0 | 1489 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 1490 | |
| mbed_official | 133:d4dda5c437f0 | 1491 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1492 | } |
| mbed_official | 133:d4dda5c437f0 | 1493 | |
| mbed_official | 133:d4dda5c437f0 | 1494 | /** |
| mbed_official | 133:d4dda5c437f0 | 1495 | * @brief DeInitializes the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 1496 | * @param htim: TIM Input Capture handle |
| mbed_official | 133:d4dda5c437f0 | 1497 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1498 | */ |
| mbed_official | 133:d4dda5c437f0 | 1499 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 1500 | { |
| mbed_official | 133:d4dda5c437f0 | 1501 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1502 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 1503 | |
| mbed_official | 133:d4dda5c437f0 | 1504 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1505 | |
| mbed_official | 133:d4dda5c437f0 | 1506 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 133:d4dda5c437f0 | 1507 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1508 | |
| mbed_official | 133:d4dda5c437f0 | 1509 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 133:d4dda5c437f0 | 1510 | HAL_TIM_IC_MspDeInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 1511 | |
| mbed_official | 133:d4dda5c437f0 | 1512 | /* Change TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 1513 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 133:d4dda5c437f0 | 1514 | |
| mbed_official | 133:d4dda5c437f0 | 1515 | /* Release Lock */ |
| mbed_official | 133:d4dda5c437f0 | 1516 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 1517 | |
| mbed_official | 133:d4dda5c437f0 | 1518 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1519 | } |
| mbed_official | 133:d4dda5c437f0 | 1520 | |
| mbed_official | 133:d4dda5c437f0 | 1521 | /** |
| mbed_official | 133:d4dda5c437f0 | 1522 | * @brief Initializes the TIM INput Capture MSP. |
| mbed_official | 133:d4dda5c437f0 | 1523 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1524 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 1525 | */ |
| mbed_official | 133:d4dda5c437f0 | 1526 | __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 1527 | { |
| mbed_official | 133:d4dda5c437f0 | 1528 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 1529 | the HAL_TIM_IC_MspInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 1530 | */ |
| mbed_official | 133:d4dda5c437f0 | 1531 | } |
| mbed_official | 133:d4dda5c437f0 | 1532 | |
| mbed_official | 133:d4dda5c437f0 | 1533 | /** |
| mbed_official | 133:d4dda5c437f0 | 1534 | * @brief DeInitializes TIM Input Capture MSP. |
| mbed_official | 133:d4dda5c437f0 | 1535 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1536 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 1537 | */ |
| mbed_official | 133:d4dda5c437f0 | 1538 | __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 1539 | { |
| mbed_official | 133:d4dda5c437f0 | 1540 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 1541 | the HAL_TIM_IC_MspDeInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 1542 | */ |
| mbed_official | 133:d4dda5c437f0 | 1543 | } |
| mbed_official | 133:d4dda5c437f0 | 1544 | |
| mbed_official | 133:d4dda5c437f0 | 1545 | /** |
| mbed_official | 133:d4dda5c437f0 | 1546 | * @brief Starts the TIM Input Capture measurement. |
| mbed_official | 133:d4dda5c437f0 | 1547 | * @param hdma : TIM Input Capture handle |
| mbed_official | 133:d4dda5c437f0 | 1548 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 1549 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1550 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1551 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1552 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1553 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1554 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1555 | */ |
| mbed_official | 133:d4dda5c437f0 | 1556 | HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1557 | { |
| mbed_official | 133:d4dda5c437f0 | 1558 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1559 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1560 | |
| mbed_official | 133:d4dda5c437f0 | 1561 | /* Enable the Input Capture channel */ |
| mbed_official | 133:d4dda5c437f0 | 1562 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 1563 | |
| mbed_official | 133:d4dda5c437f0 | 1564 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1565 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1566 | |
| mbed_official | 133:d4dda5c437f0 | 1567 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1568 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1569 | } |
| mbed_official | 133:d4dda5c437f0 | 1570 | |
| mbed_official | 133:d4dda5c437f0 | 1571 | /** |
| mbed_official | 133:d4dda5c437f0 | 1572 | * @brief Stops the TIM Input Capture measurement. |
| mbed_official | 133:d4dda5c437f0 | 1573 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1574 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 133:d4dda5c437f0 | 1575 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1576 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1577 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1578 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1579 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1580 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1581 | */ |
| mbed_official | 133:d4dda5c437f0 | 1582 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1583 | { |
| mbed_official | 133:d4dda5c437f0 | 1584 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1585 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1586 | |
| mbed_official | 133:d4dda5c437f0 | 1587 | /* Disable the Input Capture channel */ |
| mbed_official | 133:d4dda5c437f0 | 1588 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 1589 | |
| mbed_official | 133:d4dda5c437f0 | 1590 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1591 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1592 | |
| mbed_official | 133:d4dda5c437f0 | 1593 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1594 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1595 | } |
| mbed_official | 133:d4dda5c437f0 | 1596 | |
| mbed_official | 133:d4dda5c437f0 | 1597 | /** |
| mbed_official | 133:d4dda5c437f0 | 1598 | * @brief Starts the TIM Input Capture measurement in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 1599 | * @param hdma : TIM Input Capture handle |
| mbed_official | 133:d4dda5c437f0 | 1600 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 1601 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1602 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1603 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1604 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1605 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1606 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1607 | */ |
| mbed_official | 133:d4dda5c437f0 | 1608 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1609 | { |
| mbed_official | 133:d4dda5c437f0 | 1610 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1611 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1612 | |
| mbed_official | 133:d4dda5c437f0 | 1613 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 1614 | { |
| mbed_official | 133:d4dda5c437f0 | 1615 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 1616 | { |
| mbed_official | 133:d4dda5c437f0 | 1617 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1618 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 1619 | } |
| mbed_official | 133:d4dda5c437f0 | 1620 | break; |
| mbed_official | 133:d4dda5c437f0 | 1621 | |
| mbed_official | 133:d4dda5c437f0 | 1622 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 1623 | { |
| mbed_official | 133:d4dda5c437f0 | 1624 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1625 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 1626 | } |
| mbed_official | 133:d4dda5c437f0 | 1627 | break; |
| mbed_official | 133:d4dda5c437f0 | 1628 | |
| mbed_official | 133:d4dda5c437f0 | 1629 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 1630 | { |
| mbed_official | 133:d4dda5c437f0 | 1631 | /* Enable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1632 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 133:d4dda5c437f0 | 1633 | } |
| mbed_official | 133:d4dda5c437f0 | 1634 | break; |
| mbed_official | 133:d4dda5c437f0 | 1635 | |
| mbed_official | 133:d4dda5c437f0 | 1636 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 1637 | { |
| mbed_official | 133:d4dda5c437f0 | 1638 | /* Enable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1639 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 133:d4dda5c437f0 | 1640 | } |
| mbed_official | 133:d4dda5c437f0 | 1641 | break; |
| mbed_official | 133:d4dda5c437f0 | 1642 | |
| mbed_official | 133:d4dda5c437f0 | 1643 | default: |
| mbed_official | 133:d4dda5c437f0 | 1644 | break; |
| mbed_official | 133:d4dda5c437f0 | 1645 | } |
| mbed_official | 133:d4dda5c437f0 | 1646 | /* Enable the Input Capture channel */ |
| mbed_official | 133:d4dda5c437f0 | 1647 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 1648 | |
| mbed_official | 133:d4dda5c437f0 | 1649 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1650 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1651 | |
| mbed_official | 133:d4dda5c437f0 | 1652 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1653 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1654 | } |
| mbed_official | 133:d4dda5c437f0 | 1655 | |
| mbed_official | 133:d4dda5c437f0 | 1656 | /** |
| mbed_official | 133:d4dda5c437f0 | 1657 | * @brief Stops the TIM Input Capture measurement in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 1658 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1659 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 133:d4dda5c437f0 | 1660 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1661 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1662 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1663 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1664 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1665 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1666 | */ |
| mbed_official | 133:d4dda5c437f0 | 1667 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1668 | { |
| mbed_official | 133:d4dda5c437f0 | 1669 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1670 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1671 | |
| mbed_official | 133:d4dda5c437f0 | 1672 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 1673 | { |
| mbed_official | 133:d4dda5c437f0 | 1674 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 1675 | { |
| mbed_official | 133:d4dda5c437f0 | 1676 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1677 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 1678 | } |
| mbed_official | 133:d4dda5c437f0 | 1679 | break; |
| mbed_official | 133:d4dda5c437f0 | 1680 | |
| mbed_official | 133:d4dda5c437f0 | 1681 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 1682 | { |
| mbed_official | 133:d4dda5c437f0 | 1683 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1684 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 1685 | } |
| mbed_official | 133:d4dda5c437f0 | 1686 | break; |
| mbed_official | 133:d4dda5c437f0 | 1687 | |
| mbed_official | 133:d4dda5c437f0 | 1688 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 1689 | { |
| mbed_official | 133:d4dda5c437f0 | 1690 | /* Disable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1691 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 133:d4dda5c437f0 | 1692 | } |
| mbed_official | 133:d4dda5c437f0 | 1693 | break; |
| mbed_official | 133:d4dda5c437f0 | 1694 | |
| mbed_official | 133:d4dda5c437f0 | 1695 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 1696 | { |
| mbed_official | 133:d4dda5c437f0 | 1697 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 1698 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 133:d4dda5c437f0 | 1699 | } |
| mbed_official | 133:d4dda5c437f0 | 1700 | break; |
| mbed_official | 133:d4dda5c437f0 | 1701 | |
| mbed_official | 133:d4dda5c437f0 | 1702 | default: |
| mbed_official | 133:d4dda5c437f0 | 1703 | break; |
| mbed_official | 133:d4dda5c437f0 | 1704 | } |
| mbed_official | 133:d4dda5c437f0 | 1705 | |
| mbed_official | 133:d4dda5c437f0 | 1706 | /* Disable the Input Capture channel */ |
| mbed_official | 133:d4dda5c437f0 | 1707 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 1708 | |
| mbed_official | 133:d4dda5c437f0 | 1709 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1710 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1711 | |
| mbed_official | 133:d4dda5c437f0 | 1712 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1713 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1714 | } |
| mbed_official | 133:d4dda5c437f0 | 1715 | |
| mbed_official | 133:d4dda5c437f0 | 1716 | /** |
| mbed_official | 133:d4dda5c437f0 | 1717 | * @brief Starts the TIM Input Capture measurement on in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 1718 | * @param htim : TIM Input Capture handle |
| mbed_official | 133:d4dda5c437f0 | 1719 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 1720 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1721 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1722 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1723 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1724 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1725 | * @param pData: The destination Buffer address. |
| mbed_official | 133:d4dda5c437f0 | 1726 | * @param Length: The length of data to be transferred from TIM peripheral to memory. |
| mbed_official | 133:d4dda5c437f0 | 1727 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1728 | */ |
| mbed_official | 133:d4dda5c437f0 | 1729 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| mbed_official | 133:d4dda5c437f0 | 1730 | { |
| mbed_official | 133:d4dda5c437f0 | 1731 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1732 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1733 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 1734 | |
| mbed_official | 133:d4dda5c437f0 | 1735 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 133:d4dda5c437f0 | 1736 | { |
| mbed_official | 133:d4dda5c437f0 | 1737 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1738 | } |
| mbed_official | 133:d4dda5c437f0 | 1739 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 133:d4dda5c437f0 | 1740 | { |
| mbed_official | 133:d4dda5c437f0 | 1741 | if((pData == 0 ) && (Length > 0)) |
| mbed_official | 133:d4dda5c437f0 | 1742 | { |
| mbed_official | 133:d4dda5c437f0 | 1743 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 1744 | } |
| mbed_official | 133:d4dda5c437f0 | 1745 | else |
| mbed_official | 133:d4dda5c437f0 | 1746 | { |
| mbed_official | 133:d4dda5c437f0 | 1747 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1748 | } |
| mbed_official | 133:d4dda5c437f0 | 1749 | } |
| mbed_official | 133:d4dda5c437f0 | 1750 | |
| mbed_official | 133:d4dda5c437f0 | 1751 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 1752 | { |
| mbed_official | 133:d4dda5c437f0 | 1753 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 1754 | { |
| mbed_official | 133:d4dda5c437f0 | 1755 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 1756 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 1757 | |
| mbed_official | 133:d4dda5c437f0 | 1758 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 1759 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 1760 | |
| mbed_official | 133:d4dda5c437f0 | 1761 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 1762 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); |
| mbed_official | 133:d4dda5c437f0 | 1763 | |
| mbed_official | 133:d4dda5c437f0 | 1764 | /* Enable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1765 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 1766 | } |
| mbed_official | 133:d4dda5c437f0 | 1767 | break; |
| mbed_official | 133:d4dda5c437f0 | 1768 | |
| mbed_official | 133:d4dda5c437f0 | 1769 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 1770 | { |
| mbed_official | 133:d4dda5c437f0 | 1771 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 1772 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 1773 | |
| mbed_official | 133:d4dda5c437f0 | 1774 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 1775 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 1776 | |
| mbed_official | 133:d4dda5c437f0 | 1777 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 1778 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); |
| mbed_official | 133:d4dda5c437f0 | 1779 | |
| mbed_official | 133:d4dda5c437f0 | 1780 | /* Enable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1781 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 1782 | } |
| mbed_official | 133:d4dda5c437f0 | 1783 | break; |
| mbed_official | 133:d4dda5c437f0 | 1784 | |
| mbed_official | 133:d4dda5c437f0 | 1785 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 1786 | { |
| mbed_official | 133:d4dda5c437f0 | 1787 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 1788 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 1789 | |
| mbed_official | 133:d4dda5c437f0 | 1790 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 1791 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 1792 | |
| mbed_official | 133:d4dda5c437f0 | 1793 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 1794 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); |
| mbed_official | 133:d4dda5c437f0 | 1795 | |
| mbed_official | 133:d4dda5c437f0 | 1796 | /* Enable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1797 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 133:d4dda5c437f0 | 1798 | } |
| mbed_official | 133:d4dda5c437f0 | 1799 | break; |
| mbed_official | 133:d4dda5c437f0 | 1800 | |
| mbed_official | 133:d4dda5c437f0 | 1801 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 1802 | { |
| mbed_official | 133:d4dda5c437f0 | 1803 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 1804 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 1805 | |
| mbed_official | 133:d4dda5c437f0 | 1806 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 1807 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 1808 | |
| mbed_official | 133:d4dda5c437f0 | 1809 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 1810 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); |
| mbed_official | 133:d4dda5c437f0 | 1811 | |
| mbed_official | 133:d4dda5c437f0 | 1812 | /* Enable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1813 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 133:d4dda5c437f0 | 1814 | } |
| mbed_official | 133:d4dda5c437f0 | 1815 | break; |
| mbed_official | 133:d4dda5c437f0 | 1816 | |
| mbed_official | 133:d4dda5c437f0 | 1817 | default: |
| mbed_official | 133:d4dda5c437f0 | 1818 | break; |
| mbed_official | 133:d4dda5c437f0 | 1819 | } |
| mbed_official | 133:d4dda5c437f0 | 1820 | |
| mbed_official | 133:d4dda5c437f0 | 1821 | /* Enable the Input Capture channel */ |
| mbed_official | 133:d4dda5c437f0 | 1822 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 1823 | |
| mbed_official | 133:d4dda5c437f0 | 1824 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1825 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1826 | |
| mbed_official | 133:d4dda5c437f0 | 1827 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1828 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1829 | } |
| mbed_official | 133:d4dda5c437f0 | 1830 | |
| mbed_official | 133:d4dda5c437f0 | 1831 | /** |
| mbed_official | 133:d4dda5c437f0 | 1832 | * @brief Stops the TIM Input Capture measurement on in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 1833 | * @param htim : TIM Input Capture handle |
| mbed_official | 133:d4dda5c437f0 | 1834 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 133:d4dda5c437f0 | 1835 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1836 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 1837 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 1838 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 1839 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 1840 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1841 | */ |
| mbed_official | 133:d4dda5c437f0 | 1842 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 1843 | { |
| mbed_official | 133:d4dda5c437f0 | 1844 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1845 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 133:d4dda5c437f0 | 1846 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 1847 | |
| mbed_official | 133:d4dda5c437f0 | 1848 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 1849 | { |
| mbed_official | 133:d4dda5c437f0 | 1850 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 1851 | { |
| mbed_official | 133:d4dda5c437f0 | 1852 | /* Disable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1853 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 1854 | } |
| mbed_official | 133:d4dda5c437f0 | 1855 | break; |
| mbed_official | 133:d4dda5c437f0 | 1856 | |
| mbed_official | 133:d4dda5c437f0 | 1857 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 1858 | { |
| mbed_official | 133:d4dda5c437f0 | 1859 | /* Disable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1860 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 1861 | } |
| mbed_official | 133:d4dda5c437f0 | 1862 | break; |
| mbed_official | 133:d4dda5c437f0 | 1863 | |
| mbed_official | 133:d4dda5c437f0 | 1864 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 1865 | { |
| mbed_official | 133:d4dda5c437f0 | 1866 | /* Disable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1867 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 133:d4dda5c437f0 | 1868 | } |
| mbed_official | 133:d4dda5c437f0 | 1869 | break; |
| mbed_official | 133:d4dda5c437f0 | 1870 | |
| mbed_official | 133:d4dda5c437f0 | 1871 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 1872 | { |
| mbed_official | 133:d4dda5c437f0 | 1873 | /* Disable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 1874 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 133:d4dda5c437f0 | 1875 | } |
| mbed_official | 133:d4dda5c437f0 | 1876 | break; |
| mbed_official | 133:d4dda5c437f0 | 1877 | |
| mbed_official | 133:d4dda5c437f0 | 1878 | default: |
| mbed_official | 133:d4dda5c437f0 | 1879 | break; |
| mbed_official | 133:d4dda5c437f0 | 1880 | } |
| mbed_official | 133:d4dda5c437f0 | 1881 | |
| mbed_official | 133:d4dda5c437f0 | 1882 | /* Disable the Input Capture channel */ |
| mbed_official | 133:d4dda5c437f0 | 1883 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 1884 | |
| mbed_official | 133:d4dda5c437f0 | 1885 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 1886 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1887 | |
| mbed_official | 133:d4dda5c437f0 | 1888 | /* Change the htim state */ |
| mbed_official | 133:d4dda5c437f0 | 1889 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 1890 | |
| mbed_official | 133:d4dda5c437f0 | 1891 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 1892 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1893 | } |
| mbed_official | 133:d4dda5c437f0 | 1894 | /** |
| mbed_official | 133:d4dda5c437f0 | 1895 | * @} |
| mbed_official | 133:d4dda5c437f0 | 1896 | */ |
| mbed_official | 133:d4dda5c437f0 | 1897 | |
| mbed_official | 133:d4dda5c437f0 | 1898 | /** @defgroup TIM_Group5 Time One Pulse functions |
| mbed_official | 133:d4dda5c437f0 | 1899 | * @brief Time One Pulse functions |
| mbed_official | 133:d4dda5c437f0 | 1900 | * |
| mbed_official | 133:d4dda5c437f0 | 1901 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 1902 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 1903 | ##### Time One Pulse functions ##### |
| mbed_official | 133:d4dda5c437f0 | 1904 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 1905 | [..] |
| mbed_official | 133:d4dda5c437f0 | 1906 | This section provides functions allowing to: |
| mbed_official | 133:d4dda5c437f0 | 1907 | (+) Initialize and configure the TIM One Pulse. |
| mbed_official | 133:d4dda5c437f0 | 1908 | (+) De-initialize the TIM One Pulse. |
| mbed_official | 133:d4dda5c437f0 | 1909 | (+) Start the Time One Pulse. |
| mbed_official | 133:d4dda5c437f0 | 1910 | (+) Stop the Time One Pulse. |
| mbed_official | 133:d4dda5c437f0 | 1911 | (+) Start the Time One Pulse and enable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 1912 | (+) Stop the Time One Pulse and disable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 1913 | (+) Start the Time One Pulse and enable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 1914 | (+) Stop the Time One Pulse and disable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 1915 | |
| mbed_official | 133:d4dda5c437f0 | 1916 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 1917 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 1918 | */ |
| mbed_official | 133:d4dda5c437f0 | 1919 | /** |
| mbed_official | 133:d4dda5c437f0 | 1920 | * @brief Initializes the TIM One Pulse Time Base according to the specified |
| mbed_official | 133:d4dda5c437f0 | 1921 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 133:d4dda5c437f0 | 1922 | * @param htim: TIM OnePulse handle |
| mbed_official | 133:d4dda5c437f0 | 1923 | * @param OnePulseMode: Select the One pulse mode. |
| mbed_official | 133:d4dda5c437f0 | 1924 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 1925 | * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. |
| mbed_official | 133:d4dda5c437f0 | 1926 | * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. |
| mbed_official | 133:d4dda5c437f0 | 1927 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1928 | */ |
| mbed_official | 133:d4dda5c437f0 | 1929 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) |
| mbed_official | 133:d4dda5c437f0 | 1930 | { |
| mbed_official | 133:d4dda5c437f0 | 1931 | /* Check the TIM handle allocation */ |
| mbed_official | 133:d4dda5c437f0 | 1932 | if(htim == NULL) |
| mbed_official | 133:d4dda5c437f0 | 1933 | { |
| mbed_official | 133:d4dda5c437f0 | 1934 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 1935 | } |
| mbed_official | 133:d4dda5c437f0 | 1936 | |
| mbed_official | 133:d4dda5c437f0 | 1937 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1938 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 1939 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 133:d4dda5c437f0 | 1940 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 133:d4dda5c437f0 | 1941 | assert_param(IS_TIM_OPM_MODE(OnePulseMode)); |
| mbed_official | 133:d4dda5c437f0 | 1942 | |
| mbed_official | 133:d4dda5c437f0 | 1943 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 133:d4dda5c437f0 | 1944 | { |
| mbed_official | 133:d4dda5c437f0 | 1945 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 133:d4dda5c437f0 | 1946 | HAL_TIM_OnePulse_MspInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 1947 | } |
| mbed_official | 133:d4dda5c437f0 | 1948 | |
| mbed_official | 133:d4dda5c437f0 | 1949 | /* Set the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 1950 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1951 | |
| mbed_official | 133:d4dda5c437f0 | 1952 | /* Configure the Time base in the One Pulse Mode */ |
| mbed_official | 133:d4dda5c437f0 | 1953 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 133:d4dda5c437f0 | 1954 | |
| mbed_official | 133:d4dda5c437f0 | 1955 | /* Reset the OPM Bit */ |
| mbed_official | 133:d4dda5c437f0 | 1956 | htim->Instance->CR1 &= ~TIM_CR1_OPM; |
| mbed_official | 133:d4dda5c437f0 | 1957 | |
| mbed_official | 133:d4dda5c437f0 | 1958 | /* Configure the OPM Mode */ |
| mbed_official | 133:d4dda5c437f0 | 1959 | htim->Instance->CR1 |= OnePulseMode; |
| mbed_official | 133:d4dda5c437f0 | 1960 | |
| mbed_official | 133:d4dda5c437f0 | 1961 | /* Initialize the TIM state*/ |
| mbed_official | 133:d4dda5c437f0 | 1962 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 1963 | |
| mbed_official | 133:d4dda5c437f0 | 1964 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1965 | } |
| mbed_official | 133:d4dda5c437f0 | 1966 | |
| mbed_official | 133:d4dda5c437f0 | 1967 | /** |
| mbed_official | 133:d4dda5c437f0 | 1968 | * @brief DeInitializes the TIM One Pulse |
| mbed_official | 133:d4dda5c437f0 | 1969 | * @param htim: TIM One Pulse handle |
| mbed_official | 133:d4dda5c437f0 | 1970 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 1971 | */ |
| mbed_official | 133:d4dda5c437f0 | 1972 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 1973 | { |
| mbed_official | 133:d4dda5c437f0 | 1974 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 1975 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 1976 | |
| mbed_official | 133:d4dda5c437f0 | 1977 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 1978 | |
| mbed_official | 133:d4dda5c437f0 | 1979 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 133:d4dda5c437f0 | 1980 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 1981 | |
| mbed_official | 133:d4dda5c437f0 | 1982 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| mbed_official | 133:d4dda5c437f0 | 1983 | HAL_TIM_OnePulse_MspDeInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 1984 | |
| mbed_official | 133:d4dda5c437f0 | 1985 | /* Change TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 1986 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 133:d4dda5c437f0 | 1987 | |
| mbed_official | 133:d4dda5c437f0 | 1988 | /* Release Lock */ |
| mbed_official | 133:d4dda5c437f0 | 1989 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 1990 | |
| mbed_official | 133:d4dda5c437f0 | 1991 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 1992 | } |
| mbed_official | 133:d4dda5c437f0 | 1993 | |
| mbed_official | 133:d4dda5c437f0 | 1994 | /** |
| mbed_official | 133:d4dda5c437f0 | 1995 | * @brief Initializes the TIM One Pulse MSP. |
| mbed_official | 133:d4dda5c437f0 | 1996 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 1997 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 1998 | */ |
| mbed_official | 133:d4dda5c437f0 | 1999 | __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 2000 | { |
| mbed_official | 133:d4dda5c437f0 | 2001 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 2002 | the HAL_TIM_OnePulse_MspInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 2003 | */ |
| mbed_official | 133:d4dda5c437f0 | 2004 | } |
| mbed_official | 133:d4dda5c437f0 | 2005 | |
| mbed_official | 133:d4dda5c437f0 | 2006 | /** |
| mbed_official | 133:d4dda5c437f0 | 2007 | * @brief DeInitializes TIM One Pulse MSP. |
| mbed_official | 133:d4dda5c437f0 | 2008 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 2009 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 2010 | */ |
| mbed_official | 133:d4dda5c437f0 | 2011 | __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 2012 | { |
| mbed_official | 133:d4dda5c437f0 | 2013 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 2014 | the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 2015 | */ |
| mbed_official | 133:d4dda5c437f0 | 2016 | } |
| mbed_official | 133:d4dda5c437f0 | 2017 | |
| mbed_official | 133:d4dda5c437f0 | 2018 | /** |
| mbed_official | 133:d4dda5c437f0 | 2019 | * @brief Starts the TIM One Pulse signal generation. |
| mbed_official | 133:d4dda5c437f0 | 2020 | * @param htim : TIM One Pulse handle |
| mbed_official | 133:d4dda5c437f0 | 2021 | * @param OutputChannel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2022 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2023 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2024 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2025 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2026 | */ |
| mbed_official | 133:d4dda5c437f0 | 2027 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 133:d4dda5c437f0 | 2028 | { |
| mbed_official | 133:d4dda5c437f0 | 2029 | /* Enable the Capture compare and the Input Capture channels |
| mbed_official | 133:d4dda5c437f0 | 2030 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| mbed_official | 133:d4dda5c437f0 | 2031 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| mbed_official | 133:d4dda5c437f0 | 2032 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| mbed_official | 133:d4dda5c437f0 | 2033 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together |
| mbed_official | 133:d4dda5c437f0 | 2034 | |
| mbed_official | 133:d4dda5c437f0 | 2035 | No need to enable the counter, it's enabled automatically by hardware |
| mbed_official | 133:d4dda5c437f0 | 2036 | (the counter starts in response to a stimulus and generate a pulse */ |
| mbed_official | 133:d4dda5c437f0 | 2037 | |
| mbed_official | 133:d4dda5c437f0 | 2038 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2039 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2040 | |
| mbed_official | 133:d4dda5c437f0 | 2041 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2042 | { |
| mbed_official | 133:d4dda5c437f0 | 2043 | /* Enable the main output */ |
| mbed_official | 133:d4dda5c437f0 | 2044 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2045 | } |
| mbed_official | 133:d4dda5c437f0 | 2046 | |
| mbed_official | 133:d4dda5c437f0 | 2047 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2048 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2049 | } |
| mbed_official | 133:d4dda5c437f0 | 2050 | |
| mbed_official | 133:d4dda5c437f0 | 2051 | /** |
| mbed_official | 133:d4dda5c437f0 | 2052 | * @brief Stops the TIM One Pulse signal generation. |
| mbed_official | 133:d4dda5c437f0 | 2053 | * @param htim : TIM One Pulse handle |
| mbed_official | 133:d4dda5c437f0 | 2054 | * @param OutputChannel : TIM Channels to be disable |
| mbed_official | 133:d4dda5c437f0 | 2055 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2056 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2057 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2058 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2059 | */ |
| mbed_official | 133:d4dda5c437f0 | 2060 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 133:d4dda5c437f0 | 2061 | { |
| mbed_official | 133:d4dda5c437f0 | 2062 | /* Disable the Capture compare and the Input Capture channels |
| mbed_official | 133:d4dda5c437f0 | 2063 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| mbed_official | 133:d4dda5c437f0 | 2064 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| mbed_official | 133:d4dda5c437f0 | 2065 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| mbed_official | 133:d4dda5c437f0 | 2066 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ |
| mbed_official | 133:d4dda5c437f0 | 2067 | |
| mbed_official | 133:d4dda5c437f0 | 2068 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2069 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2070 | |
| mbed_official | 133:d4dda5c437f0 | 2071 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2072 | { |
| mbed_official | 133:d4dda5c437f0 | 2073 | /* Disable the Main Ouput */ |
| mbed_official | 133:d4dda5c437f0 | 2074 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2075 | } |
| mbed_official | 133:d4dda5c437f0 | 2076 | |
| mbed_official | 133:d4dda5c437f0 | 2077 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2078 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2079 | |
| mbed_official | 133:d4dda5c437f0 | 2080 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2081 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2082 | } |
| mbed_official | 133:d4dda5c437f0 | 2083 | |
| mbed_official | 133:d4dda5c437f0 | 2084 | /** |
| mbed_official | 133:d4dda5c437f0 | 2085 | * @brief Starts the TIM One Pulse signal generation in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 2086 | * @param htim : TIM One Pulse handle |
| mbed_official | 133:d4dda5c437f0 | 2087 | * @param OutputChannel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2088 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2089 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2090 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2091 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2092 | */ |
| mbed_official | 133:d4dda5c437f0 | 2093 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 133:d4dda5c437f0 | 2094 | { |
| mbed_official | 133:d4dda5c437f0 | 2095 | /* Enable the Capture compare and the Input Capture channels |
| mbed_official | 133:d4dda5c437f0 | 2096 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| mbed_official | 133:d4dda5c437f0 | 2097 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| mbed_official | 133:d4dda5c437f0 | 2098 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| mbed_official | 133:d4dda5c437f0 | 2099 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together |
| mbed_official | 133:d4dda5c437f0 | 2100 | |
| mbed_official | 133:d4dda5c437f0 | 2101 | No need to enable the counter, it's enabled automatically by hardware |
| mbed_official | 133:d4dda5c437f0 | 2102 | (the counter starts in response to a stimulus and generate a pulse */ |
| mbed_official | 133:d4dda5c437f0 | 2103 | |
| mbed_official | 133:d4dda5c437f0 | 2104 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 2105 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2106 | |
| mbed_official | 133:d4dda5c437f0 | 2107 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 2108 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2109 | |
| mbed_official | 133:d4dda5c437f0 | 2110 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2111 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2112 | |
| mbed_official | 133:d4dda5c437f0 | 2113 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2114 | { |
| mbed_official | 133:d4dda5c437f0 | 2115 | /* Enable the main output */ |
| mbed_official | 133:d4dda5c437f0 | 2116 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2117 | } |
| mbed_official | 133:d4dda5c437f0 | 2118 | |
| mbed_official | 133:d4dda5c437f0 | 2119 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2120 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2121 | } |
| mbed_official | 133:d4dda5c437f0 | 2122 | |
| mbed_official | 133:d4dda5c437f0 | 2123 | /** |
| mbed_official | 133:d4dda5c437f0 | 2124 | * @brief Stops the TIM One Pulse signal generation in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 2125 | * @param htim : TIM One Pulse handle |
| mbed_official | 133:d4dda5c437f0 | 2126 | * @param OutputChannel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2127 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2128 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2129 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2130 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2131 | */ |
| mbed_official | 133:d4dda5c437f0 | 2132 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 133:d4dda5c437f0 | 2133 | { |
| mbed_official | 133:d4dda5c437f0 | 2134 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 2135 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2136 | |
| mbed_official | 133:d4dda5c437f0 | 2137 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 2138 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2139 | |
| mbed_official | 133:d4dda5c437f0 | 2140 | /* Disable the Capture compare and the Input Capture channels |
| mbed_official | 133:d4dda5c437f0 | 2141 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| mbed_official | 133:d4dda5c437f0 | 2142 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| mbed_official | 133:d4dda5c437f0 | 2143 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| mbed_official | 133:d4dda5c437f0 | 2144 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ |
| mbed_official | 133:d4dda5c437f0 | 2145 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2146 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2147 | |
| mbed_official | 133:d4dda5c437f0 | 2148 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2149 | { |
| mbed_official | 133:d4dda5c437f0 | 2150 | /* Disable the Main Ouput */ |
| mbed_official | 133:d4dda5c437f0 | 2151 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2152 | } |
| mbed_official | 133:d4dda5c437f0 | 2153 | |
| mbed_official | 133:d4dda5c437f0 | 2154 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2155 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2156 | |
| mbed_official | 133:d4dda5c437f0 | 2157 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2158 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2159 | } |
| mbed_official | 133:d4dda5c437f0 | 2160 | |
| mbed_official | 133:d4dda5c437f0 | 2161 | /** |
| mbed_official | 133:d4dda5c437f0 | 2162 | * @} |
| mbed_official | 133:d4dda5c437f0 | 2163 | */ |
| mbed_official | 133:d4dda5c437f0 | 2164 | |
| mbed_official | 133:d4dda5c437f0 | 2165 | /** @defgroup TIM_Group6 Time Encoder functions |
| mbed_official | 133:d4dda5c437f0 | 2166 | * @brief Time Encoder functions |
| mbed_official | 133:d4dda5c437f0 | 2167 | * |
| mbed_official | 133:d4dda5c437f0 | 2168 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 2169 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 2170 | ##### Time Encoder functions ##### |
| mbed_official | 133:d4dda5c437f0 | 2171 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 2172 | [..] |
| mbed_official | 133:d4dda5c437f0 | 2173 | This section provides functions allowing to: |
| mbed_official | 133:d4dda5c437f0 | 2174 | (+) Initialize and configure the TIM Encoder. |
| mbed_official | 133:d4dda5c437f0 | 2175 | (+) De-initialize the TIM Encoder. |
| mbed_official | 133:d4dda5c437f0 | 2176 | (+) Start the Time Encoder. |
| mbed_official | 133:d4dda5c437f0 | 2177 | (+) Stop the Time Encoder. |
| mbed_official | 133:d4dda5c437f0 | 2178 | (+) Start the Time Encoder and enable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 2179 | (+) Stop the Time Encoder and disable interrupt. |
| mbed_official | 133:d4dda5c437f0 | 2180 | (+) Start the Time Encoder and enable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 2181 | (+) Stop the Time Encoder and disable DMA transfer. |
| mbed_official | 133:d4dda5c437f0 | 2182 | |
| mbed_official | 133:d4dda5c437f0 | 2183 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 2184 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 2185 | */ |
| mbed_official | 133:d4dda5c437f0 | 2186 | /** |
| mbed_official | 133:d4dda5c437f0 | 2187 | * @brief Initializes the TIM Encoder Interface and create the associated handle. |
| mbed_official | 133:d4dda5c437f0 | 2188 | * @param htim: TIM Encoder Interface handle |
| mbed_official | 133:d4dda5c437f0 | 2189 | * @param sConfig: TIM Encoder Interface configuration structure |
| mbed_official | 133:d4dda5c437f0 | 2190 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2191 | */ |
| mbed_official | 133:d4dda5c437f0 | 2192 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) |
| mbed_official | 133:d4dda5c437f0 | 2193 | { |
| mbed_official | 133:d4dda5c437f0 | 2194 | uint32_t tmpsmcr = 0; |
| mbed_official | 133:d4dda5c437f0 | 2195 | uint32_t tmpccmr1 = 0; |
| mbed_official | 133:d4dda5c437f0 | 2196 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 2197 | |
| mbed_official | 133:d4dda5c437f0 | 2198 | /* Check the TIM handle allocation */ |
| mbed_official | 133:d4dda5c437f0 | 2199 | if(htim == NULL) |
| mbed_official | 133:d4dda5c437f0 | 2200 | { |
| mbed_official | 133:d4dda5c437f0 | 2201 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 2202 | } |
| mbed_official | 133:d4dda5c437f0 | 2203 | |
| mbed_official | 133:d4dda5c437f0 | 2204 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2205 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2206 | assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); |
| mbed_official | 133:d4dda5c437f0 | 2207 | assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); |
| mbed_official | 133:d4dda5c437f0 | 2208 | assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); |
| mbed_official | 133:d4dda5c437f0 | 2209 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); |
| mbed_official | 133:d4dda5c437f0 | 2210 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); |
| mbed_official | 133:d4dda5c437f0 | 2211 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); |
| mbed_official | 133:d4dda5c437f0 | 2212 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); |
| mbed_official | 133:d4dda5c437f0 | 2213 | assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); |
| mbed_official | 133:d4dda5c437f0 | 2214 | assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); |
| mbed_official | 133:d4dda5c437f0 | 2215 | |
| mbed_official | 133:d4dda5c437f0 | 2216 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 133:d4dda5c437f0 | 2217 | { |
| mbed_official | 133:d4dda5c437f0 | 2218 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 133:d4dda5c437f0 | 2219 | HAL_TIM_Encoder_MspInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 2220 | } |
| mbed_official | 133:d4dda5c437f0 | 2221 | |
| mbed_official | 133:d4dda5c437f0 | 2222 | /* Set the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 2223 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 2224 | |
| mbed_official | 133:d4dda5c437f0 | 2225 | /* Reset the SMS bits */ |
| mbed_official | 133:d4dda5c437f0 | 2226 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 133:d4dda5c437f0 | 2227 | |
| mbed_official | 133:d4dda5c437f0 | 2228 | /* Configure the Time base in the Encoder Mode */ |
| mbed_official | 133:d4dda5c437f0 | 2229 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 133:d4dda5c437f0 | 2230 | |
| mbed_official | 133:d4dda5c437f0 | 2231 | /* Get the TIMx SMCR register value */ |
| mbed_official | 133:d4dda5c437f0 | 2232 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 133:d4dda5c437f0 | 2233 | |
| mbed_official | 133:d4dda5c437f0 | 2234 | /* Get the TIMx CCMR1 register value */ |
| mbed_official | 133:d4dda5c437f0 | 2235 | tmpccmr1 = htim->Instance->CCMR1; |
| mbed_official | 133:d4dda5c437f0 | 2236 | |
| mbed_official | 133:d4dda5c437f0 | 2237 | /* Get the TIMx CCER register value */ |
| mbed_official | 133:d4dda5c437f0 | 2238 | tmpccer = htim->Instance->CCER; |
| mbed_official | 133:d4dda5c437f0 | 2239 | |
| mbed_official | 133:d4dda5c437f0 | 2240 | /* Set the encoder Mode */ |
| mbed_official | 133:d4dda5c437f0 | 2241 | tmpsmcr |= sConfig->EncoderMode; |
| mbed_official | 133:d4dda5c437f0 | 2242 | |
| mbed_official | 133:d4dda5c437f0 | 2243 | /* Select the Capture Compare 1 and the Capture Compare 2 as input */ |
| mbed_official | 133:d4dda5c437f0 | 2244 | tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); |
| mbed_official | 133:d4dda5c437f0 | 2245 | tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); |
| mbed_official | 133:d4dda5c437f0 | 2246 | |
| mbed_official | 133:d4dda5c437f0 | 2247 | /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ |
| mbed_official | 133:d4dda5c437f0 | 2248 | tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); |
| mbed_official | 133:d4dda5c437f0 | 2249 | tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); |
| mbed_official | 133:d4dda5c437f0 | 2250 | tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); |
| mbed_official | 133:d4dda5c437f0 | 2251 | tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); |
| mbed_official | 133:d4dda5c437f0 | 2252 | |
| mbed_official | 133:d4dda5c437f0 | 2253 | /* Set the TI1 and the TI2 Polarities */ |
| mbed_official | 133:d4dda5c437f0 | 2254 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); |
| mbed_official | 133:d4dda5c437f0 | 2255 | tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); |
| mbed_official | 133:d4dda5c437f0 | 2256 | tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); |
| mbed_official | 133:d4dda5c437f0 | 2257 | |
| mbed_official | 133:d4dda5c437f0 | 2258 | /* Write to TIMx SMCR */ |
| mbed_official | 133:d4dda5c437f0 | 2259 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 133:d4dda5c437f0 | 2260 | |
| mbed_official | 133:d4dda5c437f0 | 2261 | /* Write to TIMx CCMR1 */ |
| mbed_official | 133:d4dda5c437f0 | 2262 | htim->Instance->CCMR1 = tmpccmr1; |
| mbed_official | 133:d4dda5c437f0 | 2263 | |
| mbed_official | 133:d4dda5c437f0 | 2264 | /* Write to TIMx CCER */ |
| mbed_official | 133:d4dda5c437f0 | 2265 | htim->Instance->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 2266 | |
| mbed_official | 133:d4dda5c437f0 | 2267 | /* Initialize the TIM state*/ |
| mbed_official | 133:d4dda5c437f0 | 2268 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 2269 | |
| mbed_official | 133:d4dda5c437f0 | 2270 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2271 | } |
| mbed_official | 133:d4dda5c437f0 | 2272 | |
| mbed_official | 133:d4dda5c437f0 | 2273 | /** |
| mbed_official | 133:d4dda5c437f0 | 2274 | * @brief DeInitializes the TIM Encoder interface |
| mbed_official | 133:d4dda5c437f0 | 2275 | * @param htim: TIM Encoder handle |
| mbed_official | 133:d4dda5c437f0 | 2276 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2277 | */ |
| mbed_official | 133:d4dda5c437f0 | 2278 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 2279 | { |
| mbed_official | 133:d4dda5c437f0 | 2280 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2281 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2282 | |
| mbed_official | 133:d4dda5c437f0 | 2283 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 2284 | |
| mbed_official | 133:d4dda5c437f0 | 2285 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 133:d4dda5c437f0 | 2286 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2287 | |
| mbed_official | 133:d4dda5c437f0 | 2288 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| mbed_official | 133:d4dda5c437f0 | 2289 | HAL_TIM_Encoder_MspDeInit(htim); |
| mbed_official | 133:d4dda5c437f0 | 2290 | |
| mbed_official | 133:d4dda5c437f0 | 2291 | /* Change TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 2292 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 133:d4dda5c437f0 | 2293 | |
| mbed_official | 133:d4dda5c437f0 | 2294 | /* Release Lock */ |
| mbed_official | 133:d4dda5c437f0 | 2295 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 2296 | |
| mbed_official | 133:d4dda5c437f0 | 2297 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2298 | } |
| mbed_official | 133:d4dda5c437f0 | 2299 | |
| mbed_official | 133:d4dda5c437f0 | 2300 | /** |
| mbed_official | 133:d4dda5c437f0 | 2301 | * @brief Initializes the TIM Encoder Interface MSP. |
| mbed_official | 133:d4dda5c437f0 | 2302 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 2303 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 2304 | */ |
| mbed_official | 133:d4dda5c437f0 | 2305 | __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 2306 | { |
| mbed_official | 133:d4dda5c437f0 | 2307 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 2308 | the HAL_TIM_Encoder_MspInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 2309 | */ |
| mbed_official | 133:d4dda5c437f0 | 2310 | } |
| mbed_official | 133:d4dda5c437f0 | 2311 | |
| mbed_official | 133:d4dda5c437f0 | 2312 | /** |
| mbed_official | 133:d4dda5c437f0 | 2313 | * @brief DeInitializes TIM Encoder Interface MSP. |
| mbed_official | 133:d4dda5c437f0 | 2314 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 2315 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 2316 | */ |
| mbed_official | 133:d4dda5c437f0 | 2317 | __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 2318 | { |
| mbed_official | 133:d4dda5c437f0 | 2319 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 2320 | the HAL_TIM_Encoder_MspDeInit could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 2321 | */ |
| mbed_official | 133:d4dda5c437f0 | 2322 | } |
| mbed_official | 133:d4dda5c437f0 | 2323 | |
| mbed_official | 133:d4dda5c437f0 | 2324 | /** |
| mbed_official | 133:d4dda5c437f0 | 2325 | * @brief Starts the TIM Encoder Interface. |
| mbed_official | 133:d4dda5c437f0 | 2326 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 133:d4dda5c437f0 | 2327 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2328 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2329 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2330 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2331 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2332 | */ |
| mbed_official | 133:d4dda5c437f0 | 2333 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 2334 | { |
| mbed_official | 133:d4dda5c437f0 | 2335 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2336 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2337 | |
| mbed_official | 133:d4dda5c437f0 | 2338 | /* Enable the encoder interface channels */ |
| mbed_official | 133:d4dda5c437f0 | 2339 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 2340 | { |
| mbed_official | 133:d4dda5c437f0 | 2341 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 2342 | { |
| mbed_official | 133:d4dda5c437f0 | 2343 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2344 | break; |
| mbed_official | 133:d4dda5c437f0 | 2345 | } |
| mbed_official | 133:d4dda5c437f0 | 2346 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 2347 | { |
| mbed_official | 133:d4dda5c437f0 | 2348 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2349 | break; |
| mbed_official | 133:d4dda5c437f0 | 2350 | } |
| mbed_official | 133:d4dda5c437f0 | 2351 | default : |
| mbed_official | 133:d4dda5c437f0 | 2352 | { |
| mbed_official | 133:d4dda5c437f0 | 2353 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2354 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2355 | break; |
| mbed_official | 133:d4dda5c437f0 | 2356 | } |
| mbed_official | 133:d4dda5c437f0 | 2357 | } |
| mbed_official | 133:d4dda5c437f0 | 2358 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2359 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2360 | |
| mbed_official | 133:d4dda5c437f0 | 2361 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2362 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2363 | } |
| mbed_official | 133:d4dda5c437f0 | 2364 | |
| mbed_official | 133:d4dda5c437f0 | 2365 | /** |
| mbed_official | 133:d4dda5c437f0 | 2366 | * @brief Stops the TIM Encoder Interface. |
| mbed_official | 133:d4dda5c437f0 | 2367 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 133:d4dda5c437f0 | 2368 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 133:d4dda5c437f0 | 2369 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2370 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2371 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2372 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2373 | */ |
| mbed_official | 133:d4dda5c437f0 | 2374 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 2375 | { |
| mbed_official | 133:d4dda5c437f0 | 2376 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2377 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2378 | |
| mbed_official | 133:d4dda5c437f0 | 2379 | /* Disable the Input Capture channels 1 and 2 |
| mbed_official | 133:d4dda5c437f0 | 2380 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ |
| mbed_official | 133:d4dda5c437f0 | 2381 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 2382 | { |
| mbed_official | 133:d4dda5c437f0 | 2383 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 2384 | { |
| mbed_official | 133:d4dda5c437f0 | 2385 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2386 | break; |
| mbed_official | 133:d4dda5c437f0 | 2387 | } |
| mbed_official | 133:d4dda5c437f0 | 2388 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 2389 | { |
| mbed_official | 133:d4dda5c437f0 | 2390 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2391 | break; |
| mbed_official | 133:d4dda5c437f0 | 2392 | } |
| mbed_official | 133:d4dda5c437f0 | 2393 | default : |
| mbed_official | 133:d4dda5c437f0 | 2394 | { |
| mbed_official | 133:d4dda5c437f0 | 2395 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2396 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2397 | break; |
| mbed_official | 133:d4dda5c437f0 | 2398 | } |
| mbed_official | 133:d4dda5c437f0 | 2399 | } |
| mbed_official | 133:d4dda5c437f0 | 2400 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2401 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2402 | |
| mbed_official | 133:d4dda5c437f0 | 2403 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2404 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2405 | } |
| mbed_official | 133:d4dda5c437f0 | 2406 | |
| mbed_official | 133:d4dda5c437f0 | 2407 | /** |
| mbed_official | 133:d4dda5c437f0 | 2408 | * @brief Starts the TIM Encoder Interface in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 2409 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 133:d4dda5c437f0 | 2410 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2411 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2412 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2413 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2414 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2415 | */ |
| mbed_official | 133:d4dda5c437f0 | 2416 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 2417 | { |
| mbed_official | 133:d4dda5c437f0 | 2418 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2419 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2420 | |
| mbed_official | 133:d4dda5c437f0 | 2421 | /* Enable the encoder interface channels */ |
| mbed_official | 133:d4dda5c437f0 | 2422 | /* Enable the capture compare Interrupts 1 and/or 2 */ |
| mbed_official | 133:d4dda5c437f0 | 2423 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 2424 | { |
| mbed_official | 133:d4dda5c437f0 | 2425 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 2426 | { |
| mbed_official | 133:d4dda5c437f0 | 2427 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2428 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2429 | break; |
| mbed_official | 133:d4dda5c437f0 | 2430 | } |
| mbed_official | 133:d4dda5c437f0 | 2431 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 2432 | { |
| mbed_official | 133:d4dda5c437f0 | 2433 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2434 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2435 | break; |
| mbed_official | 133:d4dda5c437f0 | 2436 | } |
| mbed_official | 133:d4dda5c437f0 | 2437 | default : |
| mbed_official | 133:d4dda5c437f0 | 2438 | { |
| mbed_official | 133:d4dda5c437f0 | 2439 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2440 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2441 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2442 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2443 | break; |
| mbed_official | 133:d4dda5c437f0 | 2444 | } |
| mbed_official | 133:d4dda5c437f0 | 2445 | } |
| mbed_official | 133:d4dda5c437f0 | 2446 | |
| mbed_official | 133:d4dda5c437f0 | 2447 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2448 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2449 | |
| mbed_official | 133:d4dda5c437f0 | 2450 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2451 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2452 | } |
| mbed_official | 133:d4dda5c437f0 | 2453 | |
| mbed_official | 133:d4dda5c437f0 | 2454 | /** |
| mbed_official | 133:d4dda5c437f0 | 2455 | * @brief Stops the TIM Encoder Interface in interrupt mode. |
| mbed_official | 133:d4dda5c437f0 | 2456 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 133:d4dda5c437f0 | 2457 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 133:d4dda5c437f0 | 2458 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2459 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2460 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2461 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2462 | */ |
| mbed_official | 133:d4dda5c437f0 | 2463 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 2464 | { |
| mbed_official | 133:d4dda5c437f0 | 2465 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2466 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2467 | |
| mbed_official | 133:d4dda5c437f0 | 2468 | /* Disable the Input Capture channels 1 and 2 |
| mbed_official | 133:d4dda5c437f0 | 2469 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ |
| mbed_official | 133:d4dda5c437f0 | 2470 | if(Channel == TIM_CHANNEL_1) |
| mbed_official | 133:d4dda5c437f0 | 2471 | { |
| mbed_official | 133:d4dda5c437f0 | 2472 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2473 | |
| mbed_official | 133:d4dda5c437f0 | 2474 | /* Disable the capture compare Interrupts 1 */ |
| mbed_official | 133:d4dda5c437f0 | 2475 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2476 | } |
| mbed_official | 133:d4dda5c437f0 | 2477 | else if(Channel == TIM_CHANNEL_2) |
| mbed_official | 133:d4dda5c437f0 | 2478 | { |
| mbed_official | 133:d4dda5c437f0 | 2479 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2480 | |
| mbed_official | 133:d4dda5c437f0 | 2481 | /* Disable the capture compare Interrupts 2 */ |
| mbed_official | 133:d4dda5c437f0 | 2482 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2483 | } |
| mbed_official | 133:d4dda5c437f0 | 2484 | else |
| mbed_official | 133:d4dda5c437f0 | 2485 | { |
| mbed_official | 133:d4dda5c437f0 | 2486 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2487 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2488 | |
| mbed_official | 133:d4dda5c437f0 | 2489 | /* Disable the capture compare Interrupts 1 and 2 */ |
| mbed_official | 133:d4dda5c437f0 | 2490 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2491 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2492 | } |
| mbed_official | 133:d4dda5c437f0 | 2493 | |
| mbed_official | 133:d4dda5c437f0 | 2494 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2495 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2496 | |
| mbed_official | 133:d4dda5c437f0 | 2497 | /* Change the htim state */ |
| mbed_official | 133:d4dda5c437f0 | 2498 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 2499 | |
| mbed_official | 133:d4dda5c437f0 | 2500 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2501 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2502 | } |
| mbed_official | 133:d4dda5c437f0 | 2503 | |
| mbed_official | 133:d4dda5c437f0 | 2504 | /** |
| mbed_official | 133:d4dda5c437f0 | 2505 | * @brief Starts the TIM Encoder Interface in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 2506 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 133:d4dda5c437f0 | 2507 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2508 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2509 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2510 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2511 | * @param pData1: The destination Buffer address for IC1. |
| mbed_official | 133:d4dda5c437f0 | 2512 | * @param pData2: The destination Buffer address for IC2. |
| mbed_official | 133:d4dda5c437f0 | 2513 | * @param Length: The length of data to be transferred from TIM peripheral to memory. |
| mbed_official | 133:d4dda5c437f0 | 2514 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2515 | */ |
| mbed_official | 133:d4dda5c437f0 | 2516 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) |
| mbed_official | 133:d4dda5c437f0 | 2517 | { |
| mbed_official | 133:d4dda5c437f0 | 2518 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2519 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2520 | |
| mbed_official | 133:d4dda5c437f0 | 2521 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 133:d4dda5c437f0 | 2522 | { |
| mbed_official | 133:d4dda5c437f0 | 2523 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 2524 | } |
| mbed_official | 133:d4dda5c437f0 | 2525 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 133:d4dda5c437f0 | 2526 | { |
| mbed_official | 133:d4dda5c437f0 | 2527 | if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) |
| mbed_official | 133:d4dda5c437f0 | 2528 | { |
| mbed_official | 133:d4dda5c437f0 | 2529 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 2530 | } |
| mbed_official | 133:d4dda5c437f0 | 2531 | else |
| mbed_official | 133:d4dda5c437f0 | 2532 | { |
| mbed_official | 133:d4dda5c437f0 | 2533 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 2534 | } |
| mbed_official | 133:d4dda5c437f0 | 2535 | } |
| mbed_official | 133:d4dda5c437f0 | 2536 | |
| mbed_official | 133:d4dda5c437f0 | 2537 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 2538 | { |
| mbed_official | 133:d4dda5c437f0 | 2539 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 2540 | { |
| mbed_official | 133:d4dda5c437f0 | 2541 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 2542 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 2543 | |
| mbed_official | 133:d4dda5c437f0 | 2544 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 2545 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 2546 | |
| mbed_official | 133:d4dda5c437f0 | 2547 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 2548 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); |
| mbed_official | 133:d4dda5c437f0 | 2549 | |
| mbed_official | 133:d4dda5c437f0 | 2550 | /* Enable the TIM Input Capture DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 2551 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2552 | |
| mbed_official | 133:d4dda5c437f0 | 2553 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2554 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2555 | |
| mbed_official | 133:d4dda5c437f0 | 2556 | /* Enable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 2557 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2558 | } |
| mbed_official | 133:d4dda5c437f0 | 2559 | break; |
| mbed_official | 133:d4dda5c437f0 | 2560 | |
| mbed_official | 133:d4dda5c437f0 | 2561 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 2562 | { |
| mbed_official | 133:d4dda5c437f0 | 2563 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 2564 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 2565 | |
| mbed_official | 133:d4dda5c437f0 | 2566 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 2567 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError; |
| mbed_official | 133:d4dda5c437f0 | 2568 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 2569 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); |
| mbed_official | 133:d4dda5c437f0 | 2570 | |
| mbed_official | 133:d4dda5c437f0 | 2571 | /* Enable the TIM Input Capture DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 2572 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2573 | |
| mbed_official | 133:d4dda5c437f0 | 2574 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2575 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2576 | |
| mbed_official | 133:d4dda5c437f0 | 2577 | /* Enable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 2578 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2579 | } |
| mbed_official | 133:d4dda5c437f0 | 2580 | break; |
| mbed_official | 133:d4dda5c437f0 | 2581 | |
| mbed_official | 133:d4dda5c437f0 | 2582 | case TIM_CHANNEL_ALL: |
| mbed_official | 133:d4dda5c437f0 | 2583 | { |
| mbed_official | 133:d4dda5c437f0 | 2584 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 2585 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 2586 | |
| mbed_official | 133:d4dda5c437f0 | 2587 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 2588 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 2589 | |
| mbed_official | 133:d4dda5c437f0 | 2590 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 2591 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); |
| mbed_official | 133:d4dda5c437f0 | 2592 | |
| mbed_official | 133:d4dda5c437f0 | 2593 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 2594 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 2595 | |
| mbed_official | 133:d4dda5c437f0 | 2596 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 2597 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 2598 | |
| mbed_official | 133:d4dda5c437f0 | 2599 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 2600 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); |
| mbed_official | 133:d4dda5c437f0 | 2601 | |
| mbed_official | 133:d4dda5c437f0 | 2602 | /* Enable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2603 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2604 | |
| mbed_official | 133:d4dda5c437f0 | 2605 | /* Enable the Capture compare channel */ |
| mbed_official | 133:d4dda5c437f0 | 2606 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2607 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 133:d4dda5c437f0 | 2608 | |
| mbed_official | 133:d4dda5c437f0 | 2609 | /* Enable the TIM Input Capture DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 2610 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2611 | /* Enable the TIM Input Capture DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 2612 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2613 | } |
| mbed_official | 133:d4dda5c437f0 | 2614 | break; |
| mbed_official | 133:d4dda5c437f0 | 2615 | |
| mbed_official | 133:d4dda5c437f0 | 2616 | default: |
| mbed_official | 133:d4dda5c437f0 | 2617 | break; |
| mbed_official | 133:d4dda5c437f0 | 2618 | } |
| mbed_official | 133:d4dda5c437f0 | 2619 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2620 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2621 | } |
| mbed_official | 133:d4dda5c437f0 | 2622 | |
| mbed_official | 133:d4dda5c437f0 | 2623 | /** |
| mbed_official | 133:d4dda5c437f0 | 2624 | * @brief Stops the TIM Encoder Interface in DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 2625 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 133:d4dda5c437f0 | 2626 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2627 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2628 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2629 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2630 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2631 | */ |
| mbed_official | 133:d4dda5c437f0 | 2632 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 2633 | { |
| mbed_official | 133:d4dda5c437f0 | 2634 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2635 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2636 | |
| mbed_official | 133:d4dda5c437f0 | 2637 | /* Disable the Input Capture channels 1 and 2 |
| mbed_official | 133:d4dda5c437f0 | 2638 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ |
| mbed_official | 133:d4dda5c437f0 | 2639 | if(Channel == TIM_CHANNEL_1) |
| mbed_official | 133:d4dda5c437f0 | 2640 | { |
| mbed_official | 133:d4dda5c437f0 | 2641 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2642 | |
| mbed_official | 133:d4dda5c437f0 | 2643 | /* Disable the capture compare DMA Request 1 */ |
| mbed_official | 133:d4dda5c437f0 | 2644 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2645 | } |
| mbed_official | 133:d4dda5c437f0 | 2646 | else if(Channel == TIM_CHANNEL_2) |
| mbed_official | 133:d4dda5c437f0 | 2647 | { |
| mbed_official | 133:d4dda5c437f0 | 2648 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2649 | |
| mbed_official | 133:d4dda5c437f0 | 2650 | /* Disable the capture compare DMA Request 2 */ |
| mbed_official | 133:d4dda5c437f0 | 2651 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2652 | } |
| mbed_official | 133:d4dda5c437f0 | 2653 | else |
| mbed_official | 133:d4dda5c437f0 | 2654 | { |
| mbed_official | 133:d4dda5c437f0 | 2655 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2656 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 133:d4dda5c437f0 | 2657 | |
| mbed_official | 133:d4dda5c437f0 | 2658 | /* Disable the capture compare DMA Request 1 and 2 */ |
| mbed_official | 133:d4dda5c437f0 | 2659 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2660 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2661 | } |
| mbed_official | 133:d4dda5c437f0 | 2662 | |
| mbed_official | 133:d4dda5c437f0 | 2663 | /* Disable the Peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 2664 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 133:d4dda5c437f0 | 2665 | |
| mbed_official | 133:d4dda5c437f0 | 2666 | /* Change the htim state */ |
| mbed_official | 133:d4dda5c437f0 | 2667 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 2668 | |
| mbed_official | 133:d4dda5c437f0 | 2669 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 2670 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2671 | } |
| mbed_official | 133:d4dda5c437f0 | 2672 | |
| mbed_official | 133:d4dda5c437f0 | 2673 | /** |
| mbed_official | 133:d4dda5c437f0 | 2674 | * @} |
| mbed_official | 133:d4dda5c437f0 | 2675 | */ |
| mbed_official | 133:d4dda5c437f0 | 2676 | /** @defgroup TIM_Group7 TIM IRQ handler management |
| mbed_official | 133:d4dda5c437f0 | 2677 | * @brief IRQ handler management |
| mbed_official | 133:d4dda5c437f0 | 2678 | * |
| mbed_official | 133:d4dda5c437f0 | 2679 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 2680 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 2681 | ##### IRQ handler management ##### |
| mbed_official | 133:d4dda5c437f0 | 2682 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 2683 | [..] |
| mbed_official | 133:d4dda5c437f0 | 2684 | This section provides Timer IRQ handler function. |
| mbed_official | 133:d4dda5c437f0 | 2685 | |
| mbed_official | 133:d4dda5c437f0 | 2686 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 2687 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 2688 | */ |
| mbed_official | 133:d4dda5c437f0 | 2689 | /** |
| mbed_official | 133:d4dda5c437f0 | 2690 | * @brief This function handles TIM interrupts requests. |
| mbed_official | 133:d4dda5c437f0 | 2691 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 2692 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 2693 | */ |
| mbed_official | 133:d4dda5c437f0 | 2694 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 2695 | { |
| mbed_official | 133:d4dda5c437f0 | 2696 | /* Capture compare 1 event */ |
| mbed_official | 133:d4dda5c437f0 | 2697 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2698 | { |
| mbed_official | 133:d4dda5c437f0 | 2699 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET) |
| mbed_official | 133:d4dda5c437f0 | 2700 | { |
| mbed_official | 133:d4dda5c437f0 | 2701 | { |
| mbed_official | 133:d4dda5c437f0 | 2702 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); |
| mbed_official | 133:d4dda5c437f0 | 2703 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; |
| mbed_official | 133:d4dda5c437f0 | 2704 | |
| mbed_official | 133:d4dda5c437f0 | 2705 | /* Input capture event */ |
| mbed_official | 133:d4dda5c437f0 | 2706 | if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) |
| mbed_official | 133:d4dda5c437f0 | 2707 | { |
| mbed_official | 133:d4dda5c437f0 | 2708 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2709 | } |
| mbed_official | 133:d4dda5c437f0 | 2710 | /* Output compare event */ |
| mbed_official | 133:d4dda5c437f0 | 2711 | else |
| mbed_official | 133:d4dda5c437f0 | 2712 | { |
| mbed_official | 133:d4dda5c437f0 | 2713 | HAL_TIM_OC_DelayElapsedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2714 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2715 | } |
| mbed_official | 133:d4dda5c437f0 | 2716 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 133:d4dda5c437f0 | 2717 | } |
| mbed_official | 133:d4dda5c437f0 | 2718 | } |
| mbed_official | 133:d4dda5c437f0 | 2719 | } |
| mbed_official | 133:d4dda5c437f0 | 2720 | /* Capture compare 2 event */ |
| mbed_official | 133:d4dda5c437f0 | 2721 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2722 | { |
| mbed_official | 133:d4dda5c437f0 | 2723 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET) |
| mbed_official | 133:d4dda5c437f0 | 2724 | { |
| mbed_official | 133:d4dda5c437f0 | 2725 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); |
| mbed_official | 133:d4dda5c437f0 | 2726 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; |
| mbed_official | 133:d4dda5c437f0 | 2727 | /* Input capture event */ |
| mbed_official | 133:d4dda5c437f0 | 2728 | if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) |
| mbed_official | 133:d4dda5c437f0 | 2729 | { |
| mbed_official | 133:d4dda5c437f0 | 2730 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2731 | } |
| mbed_official | 133:d4dda5c437f0 | 2732 | /* Output compare event */ |
| mbed_official | 133:d4dda5c437f0 | 2733 | else |
| mbed_official | 133:d4dda5c437f0 | 2734 | { |
| mbed_official | 133:d4dda5c437f0 | 2735 | HAL_TIM_OC_DelayElapsedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2736 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2737 | } |
| mbed_official | 133:d4dda5c437f0 | 2738 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 133:d4dda5c437f0 | 2739 | } |
| mbed_official | 133:d4dda5c437f0 | 2740 | } |
| mbed_official | 133:d4dda5c437f0 | 2741 | /* Capture compare 3 event */ |
| mbed_official | 133:d4dda5c437f0 | 2742 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2743 | { |
| mbed_official | 133:d4dda5c437f0 | 2744 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET) |
| mbed_official | 133:d4dda5c437f0 | 2745 | { |
| mbed_official | 133:d4dda5c437f0 | 2746 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); |
| mbed_official | 133:d4dda5c437f0 | 2747 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; |
| mbed_official | 133:d4dda5c437f0 | 2748 | /* Input capture event */ |
| mbed_official | 133:d4dda5c437f0 | 2749 | if((htim->Instance->CCMR1 & TIM_CCMR2_CC3S) != 0x00) |
| mbed_official | 133:d4dda5c437f0 | 2750 | { |
| mbed_official | 133:d4dda5c437f0 | 2751 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2752 | } |
| mbed_official | 133:d4dda5c437f0 | 2753 | /* Output compare event */ |
| mbed_official | 133:d4dda5c437f0 | 2754 | else |
| mbed_official | 133:d4dda5c437f0 | 2755 | { |
| mbed_official | 133:d4dda5c437f0 | 2756 | HAL_TIM_OC_DelayElapsedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2757 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2758 | } |
| mbed_official | 133:d4dda5c437f0 | 2759 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 133:d4dda5c437f0 | 2760 | } |
| mbed_official | 133:d4dda5c437f0 | 2761 | } |
| mbed_official | 133:d4dda5c437f0 | 2762 | /* Capture compare 4 event */ |
| mbed_official | 133:d4dda5c437f0 | 2763 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2764 | { |
| mbed_official | 133:d4dda5c437f0 | 2765 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET) |
| mbed_official | 133:d4dda5c437f0 | 2766 | { |
| mbed_official | 133:d4dda5c437f0 | 2767 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); |
| mbed_official | 133:d4dda5c437f0 | 2768 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; |
| mbed_official | 133:d4dda5c437f0 | 2769 | /* Input capture event */ |
| mbed_official | 133:d4dda5c437f0 | 2770 | if((htim->Instance->CCMR1 & TIM_CCMR2_CC4S) != 0x00) |
| mbed_official | 133:d4dda5c437f0 | 2771 | { |
| mbed_official | 133:d4dda5c437f0 | 2772 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2773 | } |
| mbed_official | 133:d4dda5c437f0 | 2774 | /* Output compare event */ |
| mbed_official | 133:d4dda5c437f0 | 2775 | else |
| mbed_official | 133:d4dda5c437f0 | 2776 | { |
| mbed_official | 133:d4dda5c437f0 | 2777 | HAL_TIM_OC_DelayElapsedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2778 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2779 | } |
| mbed_official | 133:d4dda5c437f0 | 2780 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 133:d4dda5c437f0 | 2781 | } |
| mbed_official | 133:d4dda5c437f0 | 2782 | } |
| mbed_official | 133:d4dda5c437f0 | 2783 | /* TIM Update event */ |
| mbed_official | 133:d4dda5c437f0 | 2784 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2785 | { |
| mbed_official | 133:d4dda5c437f0 | 2786 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET) |
| mbed_official | 133:d4dda5c437f0 | 2787 | { |
| mbed_official | 133:d4dda5c437f0 | 2788 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); |
| mbed_official | 133:d4dda5c437f0 | 2789 | HAL_TIM_PeriodElapsedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2790 | } |
| mbed_official | 133:d4dda5c437f0 | 2791 | } |
| mbed_official | 133:d4dda5c437f0 | 2792 | /* TIM Break input event */ |
| mbed_official | 133:d4dda5c437f0 | 2793 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2794 | { |
| mbed_official | 133:d4dda5c437f0 | 2795 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET) |
| mbed_official | 133:d4dda5c437f0 | 2796 | { |
| mbed_official | 133:d4dda5c437f0 | 2797 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); |
| mbed_official | 133:d4dda5c437f0 | 2798 | HAL_TIMEx_BreakCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2799 | } |
| mbed_official | 133:d4dda5c437f0 | 2800 | } |
| mbed_official | 133:d4dda5c437f0 | 2801 | /* TIM Trigger detection event */ |
| mbed_official | 133:d4dda5c437f0 | 2802 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2803 | { |
| mbed_official | 133:d4dda5c437f0 | 2804 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET) |
| mbed_official | 133:d4dda5c437f0 | 2805 | { |
| mbed_official | 133:d4dda5c437f0 | 2806 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); |
| mbed_official | 133:d4dda5c437f0 | 2807 | HAL_TIM_TriggerCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2808 | } |
| mbed_official | 133:d4dda5c437f0 | 2809 | } |
| mbed_official | 133:d4dda5c437f0 | 2810 | /* TIM commutation event */ |
| mbed_official | 133:d4dda5c437f0 | 2811 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 2812 | { |
| mbed_official | 133:d4dda5c437f0 | 2813 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET) |
| mbed_official | 133:d4dda5c437f0 | 2814 | { |
| mbed_official | 133:d4dda5c437f0 | 2815 | __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); |
| mbed_official | 133:d4dda5c437f0 | 2816 | HAL_TIMEx_CommutationCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 2817 | } |
| mbed_official | 133:d4dda5c437f0 | 2818 | } |
| mbed_official | 133:d4dda5c437f0 | 2819 | } |
| mbed_official | 133:d4dda5c437f0 | 2820 | |
| mbed_official | 133:d4dda5c437f0 | 2821 | /** |
| mbed_official | 133:d4dda5c437f0 | 2822 | * @} |
| mbed_official | 133:d4dda5c437f0 | 2823 | */ |
| mbed_official | 133:d4dda5c437f0 | 2824 | |
| mbed_official | 133:d4dda5c437f0 | 2825 | /** @defgroup TIM_Group8 Peripheral Control functions |
| mbed_official | 133:d4dda5c437f0 | 2826 | * @brief Peripheral Control functions |
| mbed_official | 133:d4dda5c437f0 | 2827 | * |
| mbed_official | 133:d4dda5c437f0 | 2828 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 2829 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 2830 | ##### Peripheral Control functions ##### |
| mbed_official | 133:d4dda5c437f0 | 2831 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 2832 | [..] |
| mbed_official | 133:d4dda5c437f0 | 2833 | This section provides functions allowing to: |
| mbed_official | 133:d4dda5c437f0 | 2834 | (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. |
| mbed_official | 133:d4dda5c437f0 | 2835 | (+) Configure External Clock source. |
| mbed_official | 133:d4dda5c437f0 | 2836 | (+) Configure Complementary channels, break features and dead time. |
| mbed_official | 133:d4dda5c437f0 | 2837 | (+) Configure Master and the Slave synchronization. |
| mbed_official | 133:d4dda5c437f0 | 2838 | (+) Configure the DMA Burst Mode. |
| mbed_official | 133:d4dda5c437f0 | 2839 | |
| mbed_official | 133:d4dda5c437f0 | 2840 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 2841 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 2842 | */ |
| mbed_official | 133:d4dda5c437f0 | 2843 | |
| mbed_official | 133:d4dda5c437f0 | 2844 | /** |
| mbed_official | 133:d4dda5c437f0 | 2845 | * @brief Initializes the TIM Output Compare Channels according to the specified |
| mbed_official | 133:d4dda5c437f0 | 2846 | * parameters in the TIM_OC_InitTypeDef. |
| mbed_official | 133:d4dda5c437f0 | 2847 | * @param htim: TIM Output Compare handle |
| mbed_official | 133:d4dda5c437f0 | 2848 | * @param sConfig: TIM Output Compare configuration structure |
| mbed_official | 133:d4dda5c437f0 | 2849 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2850 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2851 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2852 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2853 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 2854 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 2855 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2856 | */ |
| mbed_official | 133:d4dda5c437f0 | 2857 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 2858 | { |
| mbed_official | 133:d4dda5c437f0 | 2859 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2860 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 133:d4dda5c437f0 | 2861 | assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); |
| mbed_official | 133:d4dda5c437f0 | 2862 | assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 2863 | assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 2864 | assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); |
| mbed_official | 133:d4dda5c437f0 | 2865 | assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 2866 | assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 2867 | |
| mbed_official | 133:d4dda5c437f0 | 2868 | /* Check input state */ |
| mbed_official | 133:d4dda5c437f0 | 2869 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 2870 | |
| mbed_official | 133:d4dda5c437f0 | 2871 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 2872 | |
| mbed_official | 133:d4dda5c437f0 | 2873 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 2874 | { |
| mbed_official | 133:d4dda5c437f0 | 2875 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 2876 | { |
| mbed_official | 133:d4dda5c437f0 | 2877 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2878 | /* Configure the TIM Channel 1 in Output Compare */ |
| mbed_official | 133:d4dda5c437f0 | 2879 | TIM_OC1_SetConfig(htim->Instance, sConfig); |
| mbed_official | 133:d4dda5c437f0 | 2880 | } |
| mbed_official | 133:d4dda5c437f0 | 2881 | break; |
| mbed_official | 133:d4dda5c437f0 | 2882 | |
| mbed_official | 133:d4dda5c437f0 | 2883 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 2884 | { |
| mbed_official | 133:d4dda5c437f0 | 2885 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2886 | /* Configure the TIM Channel 2 in Output Compare */ |
| mbed_official | 133:d4dda5c437f0 | 2887 | TIM_OC2_SetConfig(htim->Instance, sConfig); |
| mbed_official | 133:d4dda5c437f0 | 2888 | } |
| mbed_official | 133:d4dda5c437f0 | 2889 | break; |
| mbed_official | 133:d4dda5c437f0 | 2890 | |
| mbed_official | 133:d4dda5c437f0 | 2891 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 2892 | { |
| mbed_official | 133:d4dda5c437f0 | 2893 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2894 | /* Configure the TIM Channel 3 in Output Compare */ |
| mbed_official | 133:d4dda5c437f0 | 2895 | TIM_OC3_SetConfig(htim->Instance, sConfig); |
| mbed_official | 133:d4dda5c437f0 | 2896 | } |
| mbed_official | 133:d4dda5c437f0 | 2897 | break; |
| mbed_official | 133:d4dda5c437f0 | 2898 | |
| mbed_official | 133:d4dda5c437f0 | 2899 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 2900 | { |
| mbed_official | 133:d4dda5c437f0 | 2901 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2902 | /* Configure the TIM Channel 4 in Output Compare */ |
| mbed_official | 133:d4dda5c437f0 | 2903 | TIM_OC4_SetConfig(htim->Instance, sConfig); |
| mbed_official | 133:d4dda5c437f0 | 2904 | } |
| mbed_official | 133:d4dda5c437f0 | 2905 | break; |
| mbed_official | 133:d4dda5c437f0 | 2906 | |
| mbed_official | 133:d4dda5c437f0 | 2907 | default: |
| mbed_official | 133:d4dda5c437f0 | 2908 | break; |
| mbed_official | 133:d4dda5c437f0 | 2909 | } |
| mbed_official | 133:d4dda5c437f0 | 2910 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 2911 | |
| mbed_official | 133:d4dda5c437f0 | 2912 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 2913 | |
| mbed_official | 133:d4dda5c437f0 | 2914 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 2915 | } |
| mbed_official | 133:d4dda5c437f0 | 2916 | |
| mbed_official | 133:d4dda5c437f0 | 2917 | /** |
| mbed_official | 133:d4dda5c437f0 | 2918 | * @brief Initializes the TIM Input Capture Channels according to the specified |
| mbed_official | 133:d4dda5c437f0 | 2919 | * parameters in the TIM_IC_InitTypeDef. |
| mbed_official | 133:d4dda5c437f0 | 2920 | * @param htim: TIM IC handle |
| mbed_official | 133:d4dda5c437f0 | 2921 | * @param sConfig: TIM Input Capture configuration structure |
| mbed_official | 133:d4dda5c437f0 | 2922 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 2923 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 2924 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 2925 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 2926 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 2927 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 2928 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 2929 | */ |
| mbed_official | 133:d4dda5c437f0 | 2930 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 2931 | { |
| mbed_official | 133:d4dda5c437f0 | 2932 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 2933 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2934 | assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 2935 | assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); |
| mbed_official | 133:d4dda5c437f0 | 2936 | assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); |
| mbed_official | 133:d4dda5c437f0 | 2937 | assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); |
| mbed_official | 133:d4dda5c437f0 | 2938 | |
| mbed_official | 133:d4dda5c437f0 | 2939 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 2940 | |
| mbed_official | 133:d4dda5c437f0 | 2941 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 2942 | |
| mbed_official | 133:d4dda5c437f0 | 2943 | if (Channel == TIM_CHANNEL_1) |
| mbed_official | 133:d4dda5c437f0 | 2944 | { |
| mbed_official | 133:d4dda5c437f0 | 2945 | /* TI1 Configuration */ |
| mbed_official | 133:d4dda5c437f0 | 2946 | TIM_TI1_SetConfig(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 2947 | sConfig->ICPolarity, |
| mbed_official | 133:d4dda5c437f0 | 2948 | sConfig->ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 2949 | sConfig->ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 2950 | |
| mbed_official | 133:d4dda5c437f0 | 2951 | /* Reset the IC1PSC Bits */ |
| mbed_official | 133:d4dda5c437f0 | 2952 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; |
| mbed_official | 133:d4dda5c437f0 | 2953 | |
| mbed_official | 133:d4dda5c437f0 | 2954 | /* Set the IC1PSC value */ |
| mbed_official | 133:d4dda5c437f0 | 2955 | htim->Instance->CCMR1 |= sConfig->ICPrescaler; |
| mbed_official | 133:d4dda5c437f0 | 2956 | } |
| mbed_official | 133:d4dda5c437f0 | 2957 | else if (Channel == TIM_CHANNEL_2) |
| mbed_official | 133:d4dda5c437f0 | 2958 | { |
| mbed_official | 133:d4dda5c437f0 | 2959 | /* TI2 Configuration */ |
| mbed_official | 133:d4dda5c437f0 | 2960 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2961 | |
| mbed_official | 133:d4dda5c437f0 | 2962 | TIM_TI2_SetConfig(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 2963 | sConfig->ICPolarity, |
| mbed_official | 133:d4dda5c437f0 | 2964 | sConfig->ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 2965 | sConfig->ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 2966 | |
| mbed_official | 133:d4dda5c437f0 | 2967 | /* Reset the IC2PSC Bits */ |
| mbed_official | 133:d4dda5c437f0 | 2968 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; |
| mbed_official | 133:d4dda5c437f0 | 2969 | |
| mbed_official | 133:d4dda5c437f0 | 2970 | /* Set the IC2PSC value */ |
| mbed_official | 133:d4dda5c437f0 | 2971 | htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); |
| mbed_official | 133:d4dda5c437f0 | 2972 | } |
| mbed_official | 133:d4dda5c437f0 | 2973 | else if (Channel == TIM_CHANNEL_3) |
| mbed_official | 133:d4dda5c437f0 | 2974 | { |
| mbed_official | 133:d4dda5c437f0 | 2975 | /* TI3 Configuration */ |
| mbed_official | 133:d4dda5c437f0 | 2976 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2977 | |
| mbed_official | 133:d4dda5c437f0 | 2978 | TIM_TI3_SetConfig(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 2979 | sConfig->ICPolarity, |
| mbed_official | 133:d4dda5c437f0 | 2980 | sConfig->ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 2981 | sConfig->ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 2982 | |
| mbed_official | 133:d4dda5c437f0 | 2983 | /* Reset the IC3PSC Bits */ |
| mbed_official | 133:d4dda5c437f0 | 2984 | htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; |
| mbed_official | 133:d4dda5c437f0 | 2985 | |
| mbed_official | 133:d4dda5c437f0 | 2986 | /* Set the IC3PSC value */ |
| mbed_official | 133:d4dda5c437f0 | 2987 | htim->Instance->CCMR2 |= sConfig->ICPrescaler; |
| mbed_official | 133:d4dda5c437f0 | 2988 | } |
| mbed_official | 133:d4dda5c437f0 | 2989 | else |
| mbed_official | 133:d4dda5c437f0 | 2990 | { |
| mbed_official | 133:d4dda5c437f0 | 2991 | /* TI4 Configuration */ |
| mbed_official | 133:d4dda5c437f0 | 2992 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 2993 | |
| mbed_official | 133:d4dda5c437f0 | 2994 | TIM_TI4_SetConfig(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 2995 | sConfig->ICPolarity, |
| mbed_official | 133:d4dda5c437f0 | 2996 | sConfig->ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 2997 | sConfig->ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 2998 | |
| mbed_official | 133:d4dda5c437f0 | 2999 | /* Reset the IC4PSC Bits */ |
| mbed_official | 133:d4dda5c437f0 | 3000 | htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; |
| mbed_official | 133:d4dda5c437f0 | 3001 | |
| mbed_official | 133:d4dda5c437f0 | 3002 | /* Set the IC4PSC value */ |
| mbed_official | 133:d4dda5c437f0 | 3003 | htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); |
| mbed_official | 133:d4dda5c437f0 | 3004 | } |
| mbed_official | 133:d4dda5c437f0 | 3005 | |
| mbed_official | 133:d4dda5c437f0 | 3006 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 3007 | |
| mbed_official | 133:d4dda5c437f0 | 3008 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3009 | |
| mbed_official | 133:d4dda5c437f0 | 3010 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3011 | } |
| mbed_official | 133:d4dda5c437f0 | 3012 | |
| mbed_official | 133:d4dda5c437f0 | 3013 | /** |
| mbed_official | 133:d4dda5c437f0 | 3014 | * @brief Initializes the TIM PWM channels according to the specified |
| mbed_official | 133:d4dda5c437f0 | 3015 | * parameters in the TIM_OC_InitTypeDef. |
| mbed_official | 133:d4dda5c437f0 | 3016 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 3017 | * @param sConfig: TIM PWM configuration structure |
| mbed_official | 133:d4dda5c437f0 | 3018 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 3019 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3020 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 3021 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 3022 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 3023 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 3024 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3025 | */ |
| mbed_official | 133:d4dda5c437f0 | 3026 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 3027 | { |
| mbed_official | 133:d4dda5c437f0 | 3028 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3029 | |
| mbed_official | 133:d4dda5c437f0 | 3030 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3031 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 133:d4dda5c437f0 | 3032 | assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); |
| mbed_official | 133:d4dda5c437f0 | 3033 | assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 3034 | assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 3035 | assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 3036 | assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 3037 | |
| mbed_official | 133:d4dda5c437f0 | 3038 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3039 | |
| mbed_official | 133:d4dda5c437f0 | 3040 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 3041 | { |
| mbed_official | 133:d4dda5c437f0 | 3042 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 3043 | { |
| mbed_official | 133:d4dda5c437f0 | 3044 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3045 | /* Configure the Channel 1 in PWM mode */ |
| mbed_official | 133:d4dda5c437f0 | 3046 | TIM_OC1_SetConfig(htim->Instance, sConfig); |
| mbed_official | 133:d4dda5c437f0 | 3047 | |
| mbed_official | 133:d4dda5c437f0 | 3048 | /* Set the Preload enable bit for channel1 */ |
| mbed_official | 133:d4dda5c437f0 | 3049 | htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; |
| mbed_official | 133:d4dda5c437f0 | 3050 | |
| mbed_official | 133:d4dda5c437f0 | 3051 | /* Configure the Output Fast mode */ |
| mbed_official | 133:d4dda5c437f0 | 3052 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; |
| mbed_official | 133:d4dda5c437f0 | 3053 | htim->Instance->CCMR1 |= sConfig->OCFastMode; |
| mbed_official | 133:d4dda5c437f0 | 3054 | } |
| mbed_official | 133:d4dda5c437f0 | 3055 | break; |
| mbed_official | 133:d4dda5c437f0 | 3056 | |
| mbed_official | 133:d4dda5c437f0 | 3057 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 3058 | { |
| mbed_official | 133:d4dda5c437f0 | 3059 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3060 | /* Configure the Channel 2 in PWM mode */ |
| mbed_official | 133:d4dda5c437f0 | 3061 | TIM_OC2_SetConfig(htim->Instance, sConfig); |
| mbed_official | 133:d4dda5c437f0 | 3062 | |
| mbed_official | 133:d4dda5c437f0 | 3063 | /* Set the Preload enable bit for channel2 */ |
| mbed_official | 133:d4dda5c437f0 | 3064 | htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; |
| mbed_official | 133:d4dda5c437f0 | 3065 | |
| mbed_official | 133:d4dda5c437f0 | 3066 | /* Configure the Output Fast mode */ |
| mbed_official | 133:d4dda5c437f0 | 3067 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; |
| mbed_official | 133:d4dda5c437f0 | 3068 | htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; |
| mbed_official | 133:d4dda5c437f0 | 3069 | } |
| mbed_official | 133:d4dda5c437f0 | 3070 | break; |
| mbed_official | 133:d4dda5c437f0 | 3071 | |
| mbed_official | 133:d4dda5c437f0 | 3072 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 3073 | { |
| mbed_official | 133:d4dda5c437f0 | 3074 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3075 | /* Configure the Channel 3 in PWM mode */ |
| mbed_official | 133:d4dda5c437f0 | 3076 | TIM_OC3_SetConfig(htim->Instance, sConfig); |
| mbed_official | 133:d4dda5c437f0 | 3077 | |
| mbed_official | 133:d4dda5c437f0 | 3078 | /* Set the Preload enable bit for channel3 */ |
| mbed_official | 133:d4dda5c437f0 | 3079 | htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; |
| mbed_official | 133:d4dda5c437f0 | 3080 | |
| mbed_official | 133:d4dda5c437f0 | 3081 | /* Configure the Output Fast mode */ |
| mbed_official | 133:d4dda5c437f0 | 3082 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; |
| mbed_official | 133:d4dda5c437f0 | 3083 | htim->Instance->CCMR2 |= sConfig->OCFastMode; |
| mbed_official | 133:d4dda5c437f0 | 3084 | } |
| mbed_official | 133:d4dda5c437f0 | 3085 | break; |
| mbed_official | 133:d4dda5c437f0 | 3086 | |
| mbed_official | 133:d4dda5c437f0 | 3087 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 3088 | { |
| mbed_official | 133:d4dda5c437f0 | 3089 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3090 | /* Configure the Channel 4 in PWM mode */ |
| mbed_official | 133:d4dda5c437f0 | 3091 | TIM_OC4_SetConfig(htim->Instance, sConfig); |
| mbed_official | 133:d4dda5c437f0 | 3092 | |
| mbed_official | 133:d4dda5c437f0 | 3093 | /* Set the Preload enable bit for channel4 */ |
| mbed_official | 133:d4dda5c437f0 | 3094 | htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; |
| mbed_official | 133:d4dda5c437f0 | 3095 | |
| mbed_official | 133:d4dda5c437f0 | 3096 | /* Configure the Output Fast mode */ |
| mbed_official | 133:d4dda5c437f0 | 3097 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; |
| mbed_official | 133:d4dda5c437f0 | 3098 | htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; |
| mbed_official | 133:d4dda5c437f0 | 3099 | } |
| mbed_official | 133:d4dda5c437f0 | 3100 | break; |
| mbed_official | 133:d4dda5c437f0 | 3101 | |
| mbed_official | 133:d4dda5c437f0 | 3102 | default: |
| mbed_official | 133:d4dda5c437f0 | 3103 | break; |
| mbed_official | 133:d4dda5c437f0 | 3104 | } |
| mbed_official | 133:d4dda5c437f0 | 3105 | |
| mbed_official | 133:d4dda5c437f0 | 3106 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 3107 | |
| mbed_official | 133:d4dda5c437f0 | 3108 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3109 | |
| mbed_official | 133:d4dda5c437f0 | 3110 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3111 | } |
| mbed_official | 133:d4dda5c437f0 | 3112 | |
| mbed_official | 133:d4dda5c437f0 | 3113 | /** |
| mbed_official | 133:d4dda5c437f0 | 3114 | * @brief Initializes the TIM One Pulse Channels according to the specified |
| mbed_official | 133:d4dda5c437f0 | 3115 | * parameters in the TIM_OnePulse_InitTypeDef. |
| mbed_official | 133:d4dda5c437f0 | 3116 | * @param htim: TIM One Pulse handle |
| mbed_official | 133:d4dda5c437f0 | 3117 | * @param sConfig: TIM One Pulse configuration structure |
| mbed_official | 133:d4dda5c437f0 | 3118 | * @param OutputChannel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 3119 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3120 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 3121 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 3122 | * @param InputChannel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 3123 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3124 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 3125 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 3126 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3127 | */ |
| mbed_official | 133:d4dda5c437f0 | 3128 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) |
| mbed_official | 133:d4dda5c437f0 | 3129 | { |
| mbed_official | 133:d4dda5c437f0 | 3130 | TIM_OC_InitTypeDef temp1; |
| mbed_official | 133:d4dda5c437f0 | 3131 | |
| mbed_official | 133:d4dda5c437f0 | 3132 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3133 | assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); |
| mbed_official | 133:d4dda5c437f0 | 3134 | assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); |
| mbed_official | 133:d4dda5c437f0 | 3135 | |
| mbed_official | 133:d4dda5c437f0 | 3136 | if(OutputChannel != InputChannel) |
| mbed_official | 133:d4dda5c437f0 | 3137 | { |
| mbed_official | 133:d4dda5c437f0 | 3138 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3139 | |
| mbed_official | 133:d4dda5c437f0 | 3140 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3141 | |
| mbed_official | 133:d4dda5c437f0 | 3142 | /* Extract the Ouput compare configuration from sConfig structure */ |
| mbed_official | 133:d4dda5c437f0 | 3143 | temp1.OCMode = sConfig->OCMode; |
| mbed_official | 133:d4dda5c437f0 | 3144 | temp1.Pulse = sConfig->Pulse; |
| mbed_official | 133:d4dda5c437f0 | 3145 | temp1.OCPolarity = sConfig->OCPolarity; |
| mbed_official | 133:d4dda5c437f0 | 3146 | temp1.OCNPolarity = sConfig->OCNPolarity; |
| mbed_official | 133:d4dda5c437f0 | 3147 | temp1.OCIdleState = sConfig->OCIdleState; |
| mbed_official | 133:d4dda5c437f0 | 3148 | temp1.OCNIdleState = sConfig->OCNIdleState; |
| mbed_official | 133:d4dda5c437f0 | 3149 | |
| mbed_official | 133:d4dda5c437f0 | 3150 | switch (OutputChannel) |
| mbed_official | 133:d4dda5c437f0 | 3151 | { |
| mbed_official | 133:d4dda5c437f0 | 3152 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 3153 | { |
| mbed_official | 133:d4dda5c437f0 | 3154 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3155 | |
| mbed_official | 133:d4dda5c437f0 | 3156 | TIM_OC1_SetConfig(htim->Instance, &temp1); |
| mbed_official | 133:d4dda5c437f0 | 3157 | } |
| mbed_official | 133:d4dda5c437f0 | 3158 | break; |
| mbed_official | 133:d4dda5c437f0 | 3159 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 3160 | { |
| mbed_official | 133:d4dda5c437f0 | 3161 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3162 | |
| mbed_official | 133:d4dda5c437f0 | 3163 | TIM_OC2_SetConfig(htim->Instance, &temp1); |
| mbed_official | 133:d4dda5c437f0 | 3164 | } |
| mbed_official | 133:d4dda5c437f0 | 3165 | break; |
| mbed_official | 133:d4dda5c437f0 | 3166 | default: |
| mbed_official | 133:d4dda5c437f0 | 3167 | break; |
| mbed_official | 133:d4dda5c437f0 | 3168 | } |
| mbed_official | 133:d4dda5c437f0 | 3169 | switch (InputChannel) |
| mbed_official | 133:d4dda5c437f0 | 3170 | { |
| mbed_official | 133:d4dda5c437f0 | 3171 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 3172 | { |
| mbed_official | 133:d4dda5c437f0 | 3173 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3174 | |
| mbed_official | 133:d4dda5c437f0 | 3175 | TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3176 | sConfig->ICSelection, sConfig->ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 3177 | |
| mbed_official | 133:d4dda5c437f0 | 3178 | /* Reset the IC1PSC Bits */ |
| mbed_official | 133:d4dda5c437f0 | 3179 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; |
| mbed_official | 133:d4dda5c437f0 | 3180 | |
| mbed_official | 133:d4dda5c437f0 | 3181 | /* Select the Trigger source */ |
| mbed_official | 133:d4dda5c437f0 | 3182 | htim->Instance->SMCR &= ~TIM_SMCR_TS; |
| mbed_official | 133:d4dda5c437f0 | 3183 | htim->Instance->SMCR |= TIM_TS_TI1FP1; |
| mbed_official | 133:d4dda5c437f0 | 3184 | |
| mbed_official | 133:d4dda5c437f0 | 3185 | /* Select the Slave Mode */ |
| mbed_official | 133:d4dda5c437f0 | 3186 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 133:d4dda5c437f0 | 3187 | htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; |
| mbed_official | 133:d4dda5c437f0 | 3188 | } |
| mbed_official | 133:d4dda5c437f0 | 3189 | break; |
| mbed_official | 133:d4dda5c437f0 | 3190 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 3191 | { |
| mbed_official | 133:d4dda5c437f0 | 3192 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3193 | |
| mbed_official | 133:d4dda5c437f0 | 3194 | TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3195 | sConfig->ICSelection, sConfig->ICFilter); |
| mbed_official | 133:d4dda5c437f0 | 3196 | |
| mbed_official | 133:d4dda5c437f0 | 3197 | /* Reset the IC2PSC Bits */ |
| mbed_official | 133:d4dda5c437f0 | 3198 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; |
| mbed_official | 133:d4dda5c437f0 | 3199 | |
| mbed_official | 133:d4dda5c437f0 | 3200 | /* Select the Trigger source */ |
| mbed_official | 133:d4dda5c437f0 | 3201 | htim->Instance->SMCR &= ~TIM_SMCR_TS; |
| mbed_official | 133:d4dda5c437f0 | 3202 | htim->Instance->SMCR |= TIM_TS_TI2FP2; |
| mbed_official | 133:d4dda5c437f0 | 3203 | |
| mbed_official | 133:d4dda5c437f0 | 3204 | /* Select the Slave Mode */ |
| mbed_official | 133:d4dda5c437f0 | 3205 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 133:d4dda5c437f0 | 3206 | htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; |
| mbed_official | 133:d4dda5c437f0 | 3207 | } |
| mbed_official | 133:d4dda5c437f0 | 3208 | break; |
| mbed_official | 133:d4dda5c437f0 | 3209 | |
| mbed_official | 133:d4dda5c437f0 | 3210 | default: |
| mbed_official | 133:d4dda5c437f0 | 3211 | break; |
| mbed_official | 133:d4dda5c437f0 | 3212 | } |
| mbed_official | 133:d4dda5c437f0 | 3213 | |
| mbed_official | 133:d4dda5c437f0 | 3214 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 3215 | |
| mbed_official | 133:d4dda5c437f0 | 3216 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3217 | |
| mbed_official | 133:d4dda5c437f0 | 3218 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3219 | } |
| mbed_official | 133:d4dda5c437f0 | 3220 | else |
| mbed_official | 133:d4dda5c437f0 | 3221 | { |
| mbed_official | 133:d4dda5c437f0 | 3222 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 3223 | } |
| mbed_official | 133:d4dda5c437f0 | 3224 | } |
| mbed_official | 133:d4dda5c437f0 | 3225 | |
| mbed_official | 133:d4dda5c437f0 | 3226 | /** |
| mbed_official | 133:d4dda5c437f0 | 3227 | * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 3228 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 3229 | * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write |
| mbed_official | 133:d4dda5c437f0 | 3230 | * This parameters can be on of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3231 | * @arg TIM_DMABase_CR1 |
| mbed_official | 133:d4dda5c437f0 | 3232 | * @arg TIM_DMABase_CR2 |
| mbed_official | 133:d4dda5c437f0 | 3233 | * @arg TIM_DMABase_SMCR |
| mbed_official | 133:d4dda5c437f0 | 3234 | * @arg TIM_DMABase_DIER |
| mbed_official | 133:d4dda5c437f0 | 3235 | * @arg TIM_DMABase_SR |
| mbed_official | 133:d4dda5c437f0 | 3236 | * @arg TIM_DMABase_EGR |
| mbed_official | 133:d4dda5c437f0 | 3237 | * @arg TIM_DMABase_CCMR1 |
| mbed_official | 133:d4dda5c437f0 | 3238 | * @arg TIM_DMABase_CCMR2 |
| mbed_official | 133:d4dda5c437f0 | 3239 | * @arg TIM_DMABase_CCER |
| mbed_official | 133:d4dda5c437f0 | 3240 | * @arg TIM_DMABase_CNT |
| mbed_official | 133:d4dda5c437f0 | 3241 | * @arg TIM_DMABase_PSC |
| mbed_official | 133:d4dda5c437f0 | 3242 | * @arg TIM_DMABase_ARR |
| mbed_official | 133:d4dda5c437f0 | 3243 | * @arg TIM_DMABase_RCR |
| mbed_official | 133:d4dda5c437f0 | 3244 | * @arg TIM_DMABase_CCR1 |
| mbed_official | 133:d4dda5c437f0 | 3245 | * @arg TIM_DMABase_CCR2 |
| mbed_official | 133:d4dda5c437f0 | 3246 | * @arg TIM_DMABase_CCR3 |
| mbed_official | 133:d4dda5c437f0 | 3247 | * @arg TIM_DMABase_CCR4 |
| mbed_official | 133:d4dda5c437f0 | 3248 | * @arg TIM_DMABase_BDTR |
| mbed_official | 133:d4dda5c437f0 | 3249 | * @arg TIM_DMABase_DCR |
| mbed_official | 133:d4dda5c437f0 | 3250 | * @param BurstRequestSrc: TIM DMA Request sources |
| mbed_official | 133:d4dda5c437f0 | 3251 | * This parameters can be on of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3252 | * @arg TIM_DMA_UPDATE: TIM update Interrupt source |
| mbed_official | 133:d4dda5c437f0 | 3253 | * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source |
| mbed_official | 133:d4dda5c437f0 | 3254 | * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source |
| mbed_official | 133:d4dda5c437f0 | 3255 | * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source |
| mbed_official | 133:d4dda5c437f0 | 3256 | * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source |
| mbed_official | 133:d4dda5c437f0 | 3257 | * @arg TIM_DMA_COM: TIM Commutation DMA source |
| mbed_official | 133:d4dda5c437f0 | 3258 | * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source |
| mbed_official | 133:d4dda5c437f0 | 3259 | * @param BurstBuffer: The Buffer address. |
| mbed_official | 133:d4dda5c437f0 | 3260 | * @param BurstLength: DMA Burst length. This parameter can be one value |
| mbed_official | 133:d4dda5c437f0 | 3261 | * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. |
| mbed_official | 133:d4dda5c437f0 | 3262 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3263 | */ |
| mbed_official | 133:d4dda5c437f0 | 3264 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, |
| mbed_official | 133:d4dda5c437f0 | 3265 | uint32_t* BurstBuffer, uint32_t BurstLength) |
| mbed_official | 133:d4dda5c437f0 | 3266 | { |
| mbed_official | 133:d4dda5c437f0 | 3267 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3268 | assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3269 | assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); |
| mbed_official | 133:d4dda5c437f0 | 3270 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); |
| mbed_official | 133:d4dda5c437f0 | 3271 | assert_param(IS_TIM_DMA_LENGTH(BurstLength)); |
| mbed_official | 133:d4dda5c437f0 | 3272 | |
| mbed_official | 133:d4dda5c437f0 | 3273 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 133:d4dda5c437f0 | 3274 | { |
| mbed_official | 133:d4dda5c437f0 | 3275 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3276 | } |
| mbed_official | 133:d4dda5c437f0 | 3277 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 133:d4dda5c437f0 | 3278 | { |
| mbed_official | 133:d4dda5c437f0 | 3279 | if((BurstBuffer == 0 ) && (BurstLength > 0)) |
| mbed_official | 133:d4dda5c437f0 | 3280 | { |
| mbed_official | 133:d4dda5c437f0 | 3281 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 3282 | } |
| mbed_official | 133:d4dda5c437f0 | 3283 | else |
| mbed_official | 133:d4dda5c437f0 | 3284 | { |
| mbed_official | 133:d4dda5c437f0 | 3285 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3286 | } |
| mbed_official | 133:d4dda5c437f0 | 3287 | } |
| mbed_official | 133:d4dda5c437f0 | 3288 | switch(BurstRequestSrc) |
| mbed_official | 133:d4dda5c437f0 | 3289 | { |
| mbed_official | 133:d4dda5c437f0 | 3290 | case TIM_DMA_UPDATE: |
| mbed_official | 133:d4dda5c437f0 | 3291 | { |
| mbed_official | 133:d4dda5c437f0 | 3292 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3293 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; |
| mbed_official | 133:d4dda5c437f0 | 3294 | |
| mbed_official | 133:d4dda5c437f0 | 3295 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3296 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3297 | |
| mbed_official | 133:d4dda5c437f0 | 3298 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3299 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3300 | } |
| mbed_official | 133:d4dda5c437f0 | 3301 | break; |
| mbed_official | 133:d4dda5c437f0 | 3302 | case TIM_DMA_CC1: |
| mbed_official | 133:d4dda5c437f0 | 3303 | { |
| mbed_official | 133:d4dda5c437f0 | 3304 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3305 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 3306 | |
| mbed_official | 133:d4dda5c437f0 | 3307 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3308 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3309 | |
| mbed_official | 133:d4dda5c437f0 | 3310 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3311 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3312 | } |
| mbed_official | 133:d4dda5c437f0 | 3313 | break; |
| mbed_official | 133:d4dda5c437f0 | 3314 | case TIM_DMA_CC2: |
| mbed_official | 133:d4dda5c437f0 | 3315 | { |
| mbed_official | 133:d4dda5c437f0 | 3316 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3317 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 3318 | |
| mbed_official | 133:d4dda5c437f0 | 3319 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3320 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3321 | |
| mbed_official | 133:d4dda5c437f0 | 3322 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3323 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3324 | } |
| mbed_official | 133:d4dda5c437f0 | 3325 | break; |
| mbed_official | 133:d4dda5c437f0 | 3326 | case TIM_DMA_CC3: |
| mbed_official | 133:d4dda5c437f0 | 3327 | { |
| mbed_official | 133:d4dda5c437f0 | 3328 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3329 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 3330 | |
| mbed_official | 133:d4dda5c437f0 | 3331 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3332 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3333 | |
| mbed_official | 133:d4dda5c437f0 | 3334 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3335 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3336 | } |
| mbed_official | 133:d4dda5c437f0 | 3337 | break; |
| mbed_official | 133:d4dda5c437f0 | 3338 | case TIM_DMA_CC4: |
| mbed_official | 133:d4dda5c437f0 | 3339 | { |
| mbed_official | 133:d4dda5c437f0 | 3340 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3341 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 133:d4dda5c437f0 | 3342 | |
| mbed_official | 133:d4dda5c437f0 | 3343 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3344 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3345 | |
| mbed_official | 133:d4dda5c437f0 | 3346 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3347 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3348 | } |
| mbed_official | 133:d4dda5c437f0 | 3349 | break; |
| mbed_official | 133:d4dda5c437f0 | 3350 | case TIM_DMA_COM: |
| mbed_official | 133:d4dda5c437f0 | 3351 | { |
| mbed_official | 133:d4dda5c437f0 | 3352 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3353 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; |
| mbed_official | 133:d4dda5c437f0 | 3354 | |
| mbed_official | 133:d4dda5c437f0 | 3355 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3356 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3357 | |
| mbed_official | 133:d4dda5c437f0 | 3358 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3359 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3360 | } |
| mbed_official | 133:d4dda5c437f0 | 3361 | break; |
| mbed_official | 133:d4dda5c437f0 | 3362 | case TIM_DMA_TRIGGER: |
| mbed_official | 133:d4dda5c437f0 | 3363 | { |
| mbed_official | 133:d4dda5c437f0 | 3364 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3365 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; |
| mbed_official | 133:d4dda5c437f0 | 3366 | |
| mbed_official | 133:d4dda5c437f0 | 3367 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3368 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3369 | |
| mbed_official | 133:d4dda5c437f0 | 3370 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3371 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3372 | } |
| mbed_official | 133:d4dda5c437f0 | 3373 | break; |
| mbed_official | 133:d4dda5c437f0 | 3374 | default: |
| mbed_official | 133:d4dda5c437f0 | 3375 | break; |
| mbed_official | 133:d4dda5c437f0 | 3376 | } |
| mbed_official | 133:d4dda5c437f0 | 3377 | /* configure the DMA Burst Mode */ |
| mbed_official | 133:d4dda5c437f0 | 3378 | htim->Instance->DCR = BurstBaseAddress | BurstLength; |
| mbed_official | 133:d4dda5c437f0 | 3379 | |
| mbed_official | 133:d4dda5c437f0 | 3380 | /* Enable the TIM DMA Request */ |
| mbed_official | 133:d4dda5c437f0 | 3381 | __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); |
| mbed_official | 133:d4dda5c437f0 | 3382 | |
| mbed_official | 133:d4dda5c437f0 | 3383 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 3384 | |
| mbed_official | 133:d4dda5c437f0 | 3385 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 3386 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3387 | } |
| mbed_official | 133:d4dda5c437f0 | 3388 | |
| mbed_official | 133:d4dda5c437f0 | 3389 | /** |
| mbed_official | 133:d4dda5c437f0 | 3390 | * @brief Stops the TIM DMA Burst mode |
| mbed_official | 133:d4dda5c437f0 | 3391 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 3392 | * @param BurstRequestSrc: TIM DMA Request sources to disable |
| mbed_official | 133:d4dda5c437f0 | 3393 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3394 | */ |
| mbed_official | 133:d4dda5c437f0 | 3395 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) |
| mbed_official | 133:d4dda5c437f0 | 3396 | { |
| mbed_official | 133:d4dda5c437f0 | 3397 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3398 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); |
| mbed_official | 133:d4dda5c437f0 | 3399 | |
| mbed_official | 133:d4dda5c437f0 | 3400 | /* Disable the TIM Update DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 3401 | __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); |
| mbed_official | 133:d4dda5c437f0 | 3402 | |
| mbed_official | 133:d4dda5c437f0 | 3403 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 3404 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3405 | } |
| mbed_official | 133:d4dda5c437f0 | 3406 | |
| mbed_official | 133:d4dda5c437f0 | 3407 | /** |
| mbed_official | 133:d4dda5c437f0 | 3408 | * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory |
| mbed_official | 133:d4dda5c437f0 | 3409 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 3410 | * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read |
| mbed_official | 133:d4dda5c437f0 | 3411 | * This parameters can be on of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3412 | * @arg TIM_DMABase_CR1 |
| mbed_official | 133:d4dda5c437f0 | 3413 | * @arg TIM_DMABase_CR2 |
| mbed_official | 133:d4dda5c437f0 | 3414 | * @arg TIM_DMABase_SMCR |
| mbed_official | 133:d4dda5c437f0 | 3415 | * @arg TIM_DMABase_DIER |
| mbed_official | 133:d4dda5c437f0 | 3416 | * @arg TIM_DMABase_SR |
| mbed_official | 133:d4dda5c437f0 | 3417 | * @arg TIM_DMABase_EGR |
| mbed_official | 133:d4dda5c437f0 | 3418 | * @arg TIM_DMABase_CCMR1 |
| mbed_official | 133:d4dda5c437f0 | 3419 | * @arg TIM_DMABase_CCMR2 |
| mbed_official | 133:d4dda5c437f0 | 3420 | * @arg TIM_DMABase_CCER |
| mbed_official | 133:d4dda5c437f0 | 3421 | * @arg TIM_DMABase_CNT |
| mbed_official | 133:d4dda5c437f0 | 3422 | * @arg TIM_DMABase_PSC |
| mbed_official | 133:d4dda5c437f0 | 3423 | * @arg TIM_DMABase_ARR |
| mbed_official | 133:d4dda5c437f0 | 3424 | * @arg TIM_DMABase_RCR |
| mbed_official | 133:d4dda5c437f0 | 3425 | * @arg TIM_DMABase_CCR1 |
| mbed_official | 133:d4dda5c437f0 | 3426 | * @arg TIM_DMABase_CCR2 |
| mbed_official | 133:d4dda5c437f0 | 3427 | * @arg TIM_DMABase_CCR3 |
| mbed_official | 133:d4dda5c437f0 | 3428 | * @arg TIM_DMABase_CCR4 |
| mbed_official | 133:d4dda5c437f0 | 3429 | * @arg TIM_DMABase_BDTR |
| mbed_official | 133:d4dda5c437f0 | 3430 | * @arg TIM_DMABase_DCR |
| mbed_official | 133:d4dda5c437f0 | 3431 | * @param BurstRequestSrc: TIM DMA Request sources |
| mbed_official | 133:d4dda5c437f0 | 3432 | * This parameters can be on of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3433 | * @arg TIM_DMA_UPDATE: TIM update Interrupt source |
| mbed_official | 133:d4dda5c437f0 | 3434 | * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source |
| mbed_official | 133:d4dda5c437f0 | 3435 | * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source |
| mbed_official | 133:d4dda5c437f0 | 3436 | * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source |
| mbed_official | 133:d4dda5c437f0 | 3437 | * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source |
| mbed_official | 133:d4dda5c437f0 | 3438 | * @arg TIM_DMA_COM: TIM Commutation DMA source |
| mbed_official | 133:d4dda5c437f0 | 3439 | * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source |
| mbed_official | 133:d4dda5c437f0 | 3440 | * @param BurstBuffer: The Buffer address. |
| mbed_official | 133:d4dda5c437f0 | 3441 | * @param BurstLength: DMA Burst length. This parameter can be one value |
| mbed_official | 133:d4dda5c437f0 | 3442 | * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. |
| mbed_official | 133:d4dda5c437f0 | 3443 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3444 | */ |
| mbed_official | 133:d4dda5c437f0 | 3445 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, |
| mbed_official | 133:d4dda5c437f0 | 3446 | uint32_t *BurstBuffer, uint32_t BurstLength) |
| mbed_official | 133:d4dda5c437f0 | 3447 | { |
| mbed_official | 133:d4dda5c437f0 | 3448 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3449 | assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3450 | assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); |
| mbed_official | 133:d4dda5c437f0 | 3451 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); |
| mbed_official | 133:d4dda5c437f0 | 3452 | assert_param(IS_TIM_DMA_LENGTH(BurstLength)); |
| mbed_official | 133:d4dda5c437f0 | 3453 | |
| mbed_official | 133:d4dda5c437f0 | 3454 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 133:d4dda5c437f0 | 3455 | { |
| mbed_official | 133:d4dda5c437f0 | 3456 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3457 | } |
| mbed_official | 133:d4dda5c437f0 | 3458 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 133:d4dda5c437f0 | 3459 | { |
| mbed_official | 133:d4dda5c437f0 | 3460 | if((BurstBuffer == 0 ) && (BurstLength > 0)) |
| mbed_official | 133:d4dda5c437f0 | 3461 | { |
| mbed_official | 133:d4dda5c437f0 | 3462 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 3463 | } |
| mbed_official | 133:d4dda5c437f0 | 3464 | else |
| mbed_official | 133:d4dda5c437f0 | 3465 | { |
| mbed_official | 133:d4dda5c437f0 | 3466 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3467 | } |
| mbed_official | 133:d4dda5c437f0 | 3468 | } |
| mbed_official | 133:d4dda5c437f0 | 3469 | switch(BurstRequestSrc) |
| mbed_official | 133:d4dda5c437f0 | 3470 | { |
| mbed_official | 133:d4dda5c437f0 | 3471 | case TIM_DMA_UPDATE: |
| mbed_official | 133:d4dda5c437f0 | 3472 | { |
| mbed_official | 133:d4dda5c437f0 | 3473 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3474 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; |
| mbed_official | 133:d4dda5c437f0 | 3475 | |
| mbed_official | 133:d4dda5c437f0 | 3476 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3477 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3478 | |
| mbed_official | 133:d4dda5c437f0 | 3479 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3480 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3481 | } |
| mbed_official | 133:d4dda5c437f0 | 3482 | break; |
| mbed_official | 133:d4dda5c437f0 | 3483 | case TIM_DMA_CC1: |
| mbed_official | 133:d4dda5c437f0 | 3484 | { |
| mbed_official | 133:d4dda5c437f0 | 3485 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3486 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 3487 | |
| mbed_official | 133:d4dda5c437f0 | 3488 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3489 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3490 | |
| mbed_official | 133:d4dda5c437f0 | 3491 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3492 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3493 | } |
| mbed_official | 133:d4dda5c437f0 | 3494 | break; |
| mbed_official | 133:d4dda5c437f0 | 3495 | case TIM_DMA_CC2: |
| mbed_official | 133:d4dda5c437f0 | 3496 | { |
| mbed_official | 133:d4dda5c437f0 | 3497 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3498 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 3499 | |
| mbed_official | 133:d4dda5c437f0 | 3500 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3501 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3502 | |
| mbed_official | 133:d4dda5c437f0 | 3503 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3504 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3505 | } |
| mbed_official | 133:d4dda5c437f0 | 3506 | break; |
| mbed_official | 133:d4dda5c437f0 | 3507 | case TIM_DMA_CC3: |
| mbed_official | 133:d4dda5c437f0 | 3508 | { |
| mbed_official | 133:d4dda5c437f0 | 3509 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3510 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 3511 | |
| mbed_official | 133:d4dda5c437f0 | 3512 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3513 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3514 | |
| mbed_official | 133:d4dda5c437f0 | 3515 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3516 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3517 | } |
| mbed_official | 133:d4dda5c437f0 | 3518 | break; |
| mbed_official | 133:d4dda5c437f0 | 3519 | case TIM_DMA_CC4: |
| mbed_official | 133:d4dda5c437f0 | 3520 | { |
| mbed_official | 133:d4dda5c437f0 | 3521 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3522 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 133:d4dda5c437f0 | 3523 | |
| mbed_official | 133:d4dda5c437f0 | 3524 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3525 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3526 | |
| mbed_official | 133:d4dda5c437f0 | 3527 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3528 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3529 | } |
| mbed_official | 133:d4dda5c437f0 | 3530 | break; |
| mbed_official | 133:d4dda5c437f0 | 3531 | case TIM_DMA_COM: |
| mbed_official | 133:d4dda5c437f0 | 3532 | { |
| mbed_official | 133:d4dda5c437f0 | 3533 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3534 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; |
| mbed_official | 133:d4dda5c437f0 | 3535 | |
| mbed_official | 133:d4dda5c437f0 | 3536 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3537 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3538 | |
| mbed_official | 133:d4dda5c437f0 | 3539 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3540 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3541 | } |
| mbed_official | 133:d4dda5c437f0 | 3542 | break; |
| mbed_official | 133:d4dda5c437f0 | 3543 | case TIM_DMA_TRIGGER: |
| mbed_official | 133:d4dda5c437f0 | 3544 | { |
| mbed_official | 133:d4dda5c437f0 | 3545 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 133:d4dda5c437f0 | 3546 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; |
| mbed_official | 133:d4dda5c437f0 | 3547 | |
| mbed_official | 133:d4dda5c437f0 | 3548 | /* Set the DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 3549 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 133:d4dda5c437f0 | 3550 | |
| mbed_official | 133:d4dda5c437f0 | 3551 | /* Enable the DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 3552 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 133:d4dda5c437f0 | 3553 | } |
| mbed_official | 133:d4dda5c437f0 | 3554 | break; |
| mbed_official | 133:d4dda5c437f0 | 3555 | default: |
| mbed_official | 133:d4dda5c437f0 | 3556 | break; |
| mbed_official | 133:d4dda5c437f0 | 3557 | } |
| mbed_official | 133:d4dda5c437f0 | 3558 | |
| mbed_official | 133:d4dda5c437f0 | 3559 | /* configure the DMA Burst Mode */ |
| mbed_official | 133:d4dda5c437f0 | 3560 | htim->Instance->DCR = BurstBaseAddress | BurstLength; |
| mbed_official | 133:d4dda5c437f0 | 3561 | |
| mbed_official | 133:d4dda5c437f0 | 3562 | /* Enable the TIM DMA Request */ |
| mbed_official | 133:d4dda5c437f0 | 3563 | __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); |
| mbed_official | 133:d4dda5c437f0 | 3564 | |
| mbed_official | 133:d4dda5c437f0 | 3565 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 3566 | |
| mbed_official | 133:d4dda5c437f0 | 3567 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 3568 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3569 | } |
| mbed_official | 133:d4dda5c437f0 | 3570 | |
| mbed_official | 133:d4dda5c437f0 | 3571 | /** |
| mbed_official | 133:d4dda5c437f0 | 3572 | * @brief Stop the DMA burst reading |
| mbed_official | 133:d4dda5c437f0 | 3573 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 3574 | * @param BurstRequestSrc: TIM DMA Request sources to disable. |
| mbed_official | 133:d4dda5c437f0 | 3575 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3576 | */ |
| mbed_official | 133:d4dda5c437f0 | 3577 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) |
| mbed_official | 133:d4dda5c437f0 | 3578 | { |
| mbed_official | 133:d4dda5c437f0 | 3579 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3580 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); |
| mbed_official | 133:d4dda5c437f0 | 3581 | |
| mbed_official | 133:d4dda5c437f0 | 3582 | /* Disable the TIM Update DMA request */ |
| mbed_official | 133:d4dda5c437f0 | 3583 | __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); |
| mbed_official | 133:d4dda5c437f0 | 3584 | |
| mbed_official | 133:d4dda5c437f0 | 3585 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 3586 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3587 | } |
| mbed_official | 133:d4dda5c437f0 | 3588 | |
| mbed_official | 133:d4dda5c437f0 | 3589 | /** |
| mbed_official | 133:d4dda5c437f0 | 3590 | * @brief Generate a software event |
| mbed_official | 133:d4dda5c437f0 | 3591 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 3592 | * @param EventSource: specifies the event source. |
| mbed_official | 133:d4dda5c437f0 | 3593 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3594 | * @arg TIM_EventSource_Update: Timer update Event source |
| mbed_official | 133:d4dda5c437f0 | 3595 | * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source |
| mbed_official | 133:d4dda5c437f0 | 3596 | * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source |
| mbed_official | 133:d4dda5c437f0 | 3597 | * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source |
| mbed_official | 133:d4dda5c437f0 | 3598 | * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source |
| mbed_official | 133:d4dda5c437f0 | 3599 | * @arg TIM_EventSource_COM: Timer COM event source |
| mbed_official | 133:d4dda5c437f0 | 3600 | * @arg TIM_EventSource_Trigger: Timer Trigger Event source |
| mbed_official | 133:d4dda5c437f0 | 3601 | * @arg TIM_EventSource_Break: Timer Break event source |
| mbed_official | 133:d4dda5c437f0 | 3602 | * @note TIM6 and TIM7 can only generate an update event. |
| mbed_official | 133:d4dda5c437f0 | 3603 | * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. |
| mbed_official | 133:d4dda5c437f0 | 3604 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3605 | */ |
| mbed_official | 133:d4dda5c437f0 | 3606 | |
| mbed_official | 133:d4dda5c437f0 | 3607 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) |
| mbed_official | 133:d4dda5c437f0 | 3608 | { |
| mbed_official | 133:d4dda5c437f0 | 3609 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3610 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3611 | assert_param(IS_TIM_EVENT_SOURCE(EventSource)); |
| mbed_official | 133:d4dda5c437f0 | 3612 | |
| mbed_official | 133:d4dda5c437f0 | 3613 | /* Process Locked */ |
| mbed_official | 133:d4dda5c437f0 | 3614 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3615 | |
| mbed_official | 133:d4dda5c437f0 | 3616 | /* Change the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 3617 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3618 | |
| mbed_official | 133:d4dda5c437f0 | 3619 | /* Set the event sources */ |
| mbed_official | 133:d4dda5c437f0 | 3620 | htim->Instance->EGR = EventSource; |
| mbed_official | 133:d4dda5c437f0 | 3621 | |
| mbed_official | 133:d4dda5c437f0 | 3622 | /* Change the TIM state */ |
| mbed_official | 133:d4dda5c437f0 | 3623 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 3624 | |
| mbed_official | 133:d4dda5c437f0 | 3625 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3626 | |
| mbed_official | 133:d4dda5c437f0 | 3627 | /* Return function status */ |
| mbed_official | 133:d4dda5c437f0 | 3628 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3629 | } |
| mbed_official | 133:d4dda5c437f0 | 3630 | |
| mbed_official | 133:d4dda5c437f0 | 3631 | /** |
| mbed_official | 133:d4dda5c437f0 | 3632 | * @brief Configures the OCRef clear feature |
| mbed_official | 133:d4dda5c437f0 | 3633 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 3634 | * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that |
| mbed_official | 133:d4dda5c437f0 | 3635 | * contains the OCREF clear feature and parameters for the TIM peripheral. |
| mbed_official | 133:d4dda5c437f0 | 3636 | * @param Channel: specifies the TIM Channel |
| mbed_official | 133:d4dda5c437f0 | 3637 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3638 | * @arg TIM_Channel_1: TIM Channel 1 |
| mbed_official | 133:d4dda5c437f0 | 3639 | * @arg TIM_Channel_2: TIM Channel 2 |
| mbed_official | 133:d4dda5c437f0 | 3640 | * @arg TIM_Channel_3: TIM Channel 3 |
| mbed_official | 133:d4dda5c437f0 | 3641 | * @arg TIM_Channel_4: TIM Channel 4 |
| mbed_official | 133:d4dda5c437f0 | 3642 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3643 | */ |
| mbed_official | 133:d4dda5c437f0 | 3644 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 3645 | { |
| mbed_official | 133:d4dda5c437f0 | 3646 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3647 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3648 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 133:d4dda5c437f0 | 3649 | assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); |
| mbed_official | 133:d4dda5c437f0 | 3650 | assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 3651 | assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); |
| mbed_official | 133:d4dda5c437f0 | 3652 | assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); |
| mbed_official | 133:d4dda5c437f0 | 3653 | |
| mbed_official | 133:d4dda5c437f0 | 3654 | /* Process Locked */ |
| mbed_official | 133:d4dda5c437f0 | 3655 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3656 | |
| mbed_official | 133:d4dda5c437f0 | 3657 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3658 | |
| mbed_official | 133:d4dda5c437f0 | 3659 | if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR) |
| mbed_official | 133:d4dda5c437f0 | 3660 | { |
| mbed_official | 133:d4dda5c437f0 | 3661 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 3662 | sClearInputConfig->ClearInputPrescaler, |
| mbed_official | 133:d4dda5c437f0 | 3663 | sClearInputConfig->ClearInputPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3664 | sClearInputConfig->ClearInputFilter); |
| mbed_official | 133:d4dda5c437f0 | 3665 | } |
| mbed_official | 133:d4dda5c437f0 | 3666 | |
| mbed_official | 133:d4dda5c437f0 | 3667 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 3668 | { |
| mbed_official | 133:d4dda5c437f0 | 3669 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 3670 | { |
| mbed_official | 133:d4dda5c437f0 | 3671 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 133:d4dda5c437f0 | 3672 | { |
| mbed_official | 133:d4dda5c437f0 | 3673 | /* Enable the Ocref clear feature for Channel 1 */ |
| mbed_official | 133:d4dda5c437f0 | 3674 | htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; |
| mbed_official | 133:d4dda5c437f0 | 3675 | } |
| mbed_official | 133:d4dda5c437f0 | 3676 | else |
| mbed_official | 133:d4dda5c437f0 | 3677 | { |
| mbed_official | 133:d4dda5c437f0 | 3678 | /* Disable the Ocref clear feature for Channel 1 */ |
| mbed_official | 133:d4dda5c437f0 | 3679 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; |
| mbed_official | 133:d4dda5c437f0 | 3680 | } |
| mbed_official | 133:d4dda5c437f0 | 3681 | } |
| mbed_official | 133:d4dda5c437f0 | 3682 | break; |
| mbed_official | 133:d4dda5c437f0 | 3683 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 3684 | { |
| mbed_official | 133:d4dda5c437f0 | 3685 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3686 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 133:d4dda5c437f0 | 3687 | { |
| mbed_official | 133:d4dda5c437f0 | 3688 | /* Enable the Ocref clear feature for Channel 2 */ |
| mbed_official | 133:d4dda5c437f0 | 3689 | htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; |
| mbed_official | 133:d4dda5c437f0 | 3690 | } |
| mbed_official | 133:d4dda5c437f0 | 3691 | else |
| mbed_official | 133:d4dda5c437f0 | 3692 | { |
| mbed_official | 133:d4dda5c437f0 | 3693 | /* Disable the Ocref clear feature for Channel 2 */ |
| mbed_official | 133:d4dda5c437f0 | 3694 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; |
| mbed_official | 133:d4dda5c437f0 | 3695 | } |
| mbed_official | 133:d4dda5c437f0 | 3696 | } |
| mbed_official | 133:d4dda5c437f0 | 3697 | break; |
| mbed_official | 133:d4dda5c437f0 | 3698 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 3699 | { |
| mbed_official | 133:d4dda5c437f0 | 3700 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3701 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 133:d4dda5c437f0 | 3702 | { |
| mbed_official | 133:d4dda5c437f0 | 3703 | /* Enable the Ocref clear feature for Channel 3 */ |
| mbed_official | 133:d4dda5c437f0 | 3704 | htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; |
| mbed_official | 133:d4dda5c437f0 | 3705 | } |
| mbed_official | 133:d4dda5c437f0 | 3706 | else |
| mbed_official | 133:d4dda5c437f0 | 3707 | { |
| mbed_official | 133:d4dda5c437f0 | 3708 | /* Disable the Ocref clear feature for Channel 3 */ |
| mbed_official | 133:d4dda5c437f0 | 3709 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; |
| mbed_official | 133:d4dda5c437f0 | 3710 | } |
| mbed_official | 133:d4dda5c437f0 | 3711 | } |
| mbed_official | 133:d4dda5c437f0 | 3712 | break; |
| mbed_official | 133:d4dda5c437f0 | 3713 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 3714 | { |
| mbed_official | 133:d4dda5c437f0 | 3715 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3716 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 133:d4dda5c437f0 | 3717 | { |
| mbed_official | 133:d4dda5c437f0 | 3718 | /* Enable the Ocref clear feature for Channel 4 */ |
| mbed_official | 133:d4dda5c437f0 | 3719 | htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; |
| mbed_official | 133:d4dda5c437f0 | 3720 | } |
| mbed_official | 133:d4dda5c437f0 | 3721 | else |
| mbed_official | 133:d4dda5c437f0 | 3722 | { |
| mbed_official | 133:d4dda5c437f0 | 3723 | /* Disable the Ocref clear feature for Channel 4 */ |
| mbed_official | 133:d4dda5c437f0 | 3724 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; |
| mbed_official | 133:d4dda5c437f0 | 3725 | } |
| mbed_official | 133:d4dda5c437f0 | 3726 | } |
| mbed_official | 133:d4dda5c437f0 | 3727 | break; |
| mbed_official | 133:d4dda5c437f0 | 3728 | default: |
| mbed_official | 133:d4dda5c437f0 | 3729 | break; |
| mbed_official | 133:d4dda5c437f0 | 3730 | } |
| mbed_official | 133:d4dda5c437f0 | 3731 | |
| mbed_official | 133:d4dda5c437f0 | 3732 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 3733 | |
| mbed_official | 133:d4dda5c437f0 | 3734 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3735 | |
| mbed_official | 133:d4dda5c437f0 | 3736 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3737 | } |
| mbed_official | 133:d4dda5c437f0 | 3738 | |
| mbed_official | 133:d4dda5c437f0 | 3739 | /** |
| mbed_official | 133:d4dda5c437f0 | 3740 | * @brief Configures the clock source to be used |
| mbed_official | 133:d4dda5c437f0 | 3741 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 3742 | * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that |
| mbed_official | 133:d4dda5c437f0 | 3743 | * contains the clock source information for the TIM peripheral. |
| mbed_official | 133:d4dda5c437f0 | 3744 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3745 | */ |
| mbed_official | 133:d4dda5c437f0 | 3746 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) |
| mbed_official | 133:d4dda5c437f0 | 3747 | { |
| mbed_official | 133:d4dda5c437f0 | 3748 | uint32_t tmpsmcr = 0; |
| mbed_official | 133:d4dda5c437f0 | 3749 | |
| mbed_official | 133:d4dda5c437f0 | 3750 | /* Process Locked */ |
| mbed_official | 133:d4dda5c437f0 | 3751 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3752 | |
| mbed_official | 133:d4dda5c437f0 | 3753 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3754 | |
| mbed_official | 133:d4dda5c437f0 | 3755 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3756 | assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); |
| mbed_official | 133:d4dda5c437f0 | 3757 | assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 3758 | assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); |
| mbed_official | 133:d4dda5c437f0 | 3759 | assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); |
| mbed_official | 133:d4dda5c437f0 | 3760 | |
| mbed_official | 133:d4dda5c437f0 | 3761 | /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ |
| mbed_official | 133:d4dda5c437f0 | 3762 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 133:d4dda5c437f0 | 3763 | tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); |
| mbed_official | 133:d4dda5c437f0 | 3764 | tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); |
| mbed_official | 133:d4dda5c437f0 | 3765 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 133:d4dda5c437f0 | 3766 | |
| mbed_official | 133:d4dda5c437f0 | 3767 | switch (sClockSourceConfig->ClockSource) |
| mbed_official | 133:d4dda5c437f0 | 3768 | { |
| mbed_official | 133:d4dda5c437f0 | 3769 | case TIM_CLOCKSOURCE_INTERNAL: |
| mbed_official | 133:d4dda5c437f0 | 3770 | { |
| mbed_official | 133:d4dda5c437f0 | 3771 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3772 | /* Disable slave mode to clock the prescaler directly with the internal clock */ |
| mbed_official | 133:d4dda5c437f0 | 3773 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 133:d4dda5c437f0 | 3774 | } |
| mbed_official | 133:d4dda5c437f0 | 3775 | break; |
| mbed_official | 133:d4dda5c437f0 | 3776 | |
| mbed_official | 133:d4dda5c437f0 | 3777 | case TIM_CLOCKSOURCE_ETRMODE1: |
| mbed_official | 133:d4dda5c437f0 | 3778 | { |
| mbed_official | 133:d4dda5c437f0 | 3779 | assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3780 | /* Configure the ETR Clock source */ |
| mbed_official | 133:d4dda5c437f0 | 3781 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 3782 | sClockSourceConfig->ClockPrescaler, |
| mbed_official | 133:d4dda5c437f0 | 3783 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3784 | sClockSourceConfig->ClockFilter); |
| mbed_official | 133:d4dda5c437f0 | 3785 | /* Get the TIMx SMCR register value */ |
| mbed_official | 133:d4dda5c437f0 | 3786 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 133:d4dda5c437f0 | 3787 | /* Reset the SMS and TS Bits */ |
| mbed_official | 133:d4dda5c437f0 | 3788 | tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); |
| mbed_official | 133:d4dda5c437f0 | 3789 | /* Select the External clock mode1 and the ETRF trigger */ |
| mbed_official | 133:d4dda5c437f0 | 3790 | tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); |
| mbed_official | 133:d4dda5c437f0 | 3791 | /* Write to TIMx SMCR */ |
| mbed_official | 133:d4dda5c437f0 | 3792 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 133:d4dda5c437f0 | 3793 | } |
| mbed_official | 133:d4dda5c437f0 | 3794 | break; |
| mbed_official | 133:d4dda5c437f0 | 3795 | |
| mbed_official | 133:d4dda5c437f0 | 3796 | case TIM_CLOCKSOURCE_ETRMODE2: |
| mbed_official | 133:d4dda5c437f0 | 3797 | { |
| mbed_official | 133:d4dda5c437f0 | 3798 | assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3799 | /* Configure the ETR Clock source */ |
| mbed_official | 133:d4dda5c437f0 | 3800 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 3801 | sClockSourceConfig->ClockPrescaler, |
| mbed_official | 133:d4dda5c437f0 | 3802 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3803 | sClockSourceConfig->ClockFilter); |
| mbed_official | 133:d4dda5c437f0 | 3804 | /* Enable the External clock mode2 */ |
| mbed_official | 133:d4dda5c437f0 | 3805 | htim->Instance->SMCR |= TIM_SMCR_ECE; |
| mbed_official | 133:d4dda5c437f0 | 3806 | } |
| mbed_official | 133:d4dda5c437f0 | 3807 | break; |
| mbed_official | 133:d4dda5c437f0 | 3808 | |
| mbed_official | 133:d4dda5c437f0 | 3809 | case TIM_CLOCKSOURCE_TI1: |
| mbed_official | 133:d4dda5c437f0 | 3810 | { |
| mbed_official | 133:d4dda5c437f0 | 3811 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3812 | TIM_TI1_ConfigInputStage(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 3813 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3814 | sClockSourceConfig->ClockFilter); |
| mbed_official | 133:d4dda5c437f0 | 3815 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); |
| mbed_official | 133:d4dda5c437f0 | 3816 | } |
| mbed_official | 133:d4dda5c437f0 | 3817 | break; |
| mbed_official | 133:d4dda5c437f0 | 3818 | case TIM_CLOCKSOURCE_TI2: |
| mbed_official | 133:d4dda5c437f0 | 3819 | { |
| mbed_official | 133:d4dda5c437f0 | 3820 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3821 | TIM_TI2_ConfigInputStage(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 3822 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3823 | sClockSourceConfig->ClockFilter); |
| mbed_official | 133:d4dda5c437f0 | 3824 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); |
| mbed_official | 133:d4dda5c437f0 | 3825 | } |
| mbed_official | 133:d4dda5c437f0 | 3826 | break; |
| mbed_official | 133:d4dda5c437f0 | 3827 | case TIM_CLOCKSOURCE_TI1ED: |
| mbed_official | 133:d4dda5c437f0 | 3828 | { |
| mbed_official | 133:d4dda5c437f0 | 3829 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3830 | TIM_TI1_ConfigInputStage(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 3831 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3832 | sClockSourceConfig->ClockFilter); |
| mbed_official | 133:d4dda5c437f0 | 3833 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); |
| mbed_official | 133:d4dda5c437f0 | 3834 | } |
| mbed_official | 133:d4dda5c437f0 | 3835 | break; |
| mbed_official | 133:d4dda5c437f0 | 3836 | case TIM_CLOCKSOURCE_ITR0: |
| mbed_official | 133:d4dda5c437f0 | 3837 | { |
| mbed_official | 133:d4dda5c437f0 | 3838 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3839 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); |
| mbed_official | 133:d4dda5c437f0 | 3840 | } |
| mbed_official | 133:d4dda5c437f0 | 3841 | break; |
| mbed_official | 133:d4dda5c437f0 | 3842 | case TIM_CLOCKSOURCE_ITR1: |
| mbed_official | 133:d4dda5c437f0 | 3843 | { |
| mbed_official | 133:d4dda5c437f0 | 3844 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3845 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); |
| mbed_official | 133:d4dda5c437f0 | 3846 | } |
| mbed_official | 133:d4dda5c437f0 | 3847 | break; |
| mbed_official | 133:d4dda5c437f0 | 3848 | case TIM_CLOCKSOURCE_ITR2: |
| mbed_official | 133:d4dda5c437f0 | 3849 | { |
| mbed_official | 133:d4dda5c437f0 | 3850 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3851 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); |
| mbed_official | 133:d4dda5c437f0 | 3852 | } |
| mbed_official | 133:d4dda5c437f0 | 3853 | break; |
| mbed_official | 133:d4dda5c437f0 | 3854 | case TIM_CLOCKSOURCE_ITR3: |
| mbed_official | 133:d4dda5c437f0 | 3855 | { |
| mbed_official | 133:d4dda5c437f0 | 3856 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3857 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); |
| mbed_official | 133:d4dda5c437f0 | 3858 | } |
| mbed_official | 133:d4dda5c437f0 | 3859 | break; |
| mbed_official | 133:d4dda5c437f0 | 3860 | |
| mbed_official | 133:d4dda5c437f0 | 3861 | default: |
| mbed_official | 133:d4dda5c437f0 | 3862 | break; |
| mbed_official | 133:d4dda5c437f0 | 3863 | } |
| mbed_official | 133:d4dda5c437f0 | 3864 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 3865 | |
| mbed_official | 133:d4dda5c437f0 | 3866 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3867 | |
| mbed_official | 133:d4dda5c437f0 | 3868 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3869 | } |
| mbed_official | 133:d4dda5c437f0 | 3870 | |
| mbed_official | 133:d4dda5c437f0 | 3871 | /** |
| mbed_official | 133:d4dda5c437f0 | 3872 | * @brief Selects the signal connected to the TI1 input: direct from CH1_input |
| mbed_official | 133:d4dda5c437f0 | 3873 | * or a XOR combination between CH1_input, CH2_input & CH3_input |
| mbed_official | 133:d4dda5c437f0 | 3874 | * @param htim: TIM handle. |
| mbed_official | 133:d4dda5c437f0 | 3875 | * @param TI1_Selection: Indicate whether or not channel 1 is connected to the |
| mbed_official | 133:d4dda5c437f0 | 3876 | * output of a XOR gate. |
| mbed_official | 133:d4dda5c437f0 | 3877 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 3878 | * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input |
| mbed_official | 133:d4dda5c437f0 | 3879 | * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 |
| mbed_official | 133:d4dda5c437f0 | 3880 | * pins are connected to the TI1 input (XOR combination) |
| mbed_official | 133:d4dda5c437f0 | 3881 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3882 | */ |
| mbed_official | 133:d4dda5c437f0 | 3883 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) |
| mbed_official | 133:d4dda5c437f0 | 3884 | { |
| mbed_official | 133:d4dda5c437f0 | 3885 | uint32_t tmpcr2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 3886 | |
| mbed_official | 133:d4dda5c437f0 | 3887 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3888 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3889 | assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); |
| mbed_official | 133:d4dda5c437f0 | 3890 | |
| mbed_official | 133:d4dda5c437f0 | 3891 | /* Get the TIMx CR2 register value */ |
| mbed_official | 133:d4dda5c437f0 | 3892 | tmpcr2 = htim->Instance->CR2; |
| mbed_official | 133:d4dda5c437f0 | 3893 | |
| mbed_official | 133:d4dda5c437f0 | 3894 | /* Reset the TI1 selection */ |
| mbed_official | 133:d4dda5c437f0 | 3895 | tmpcr2 &= ~TIM_CR2_TI1S; |
| mbed_official | 133:d4dda5c437f0 | 3896 | |
| mbed_official | 133:d4dda5c437f0 | 3897 | /* Set the the TI1 selection */ |
| mbed_official | 133:d4dda5c437f0 | 3898 | tmpcr2 |= TI1_Selection; |
| mbed_official | 133:d4dda5c437f0 | 3899 | |
| mbed_official | 133:d4dda5c437f0 | 3900 | /* Write to TIMxCR2 */ |
| mbed_official | 133:d4dda5c437f0 | 3901 | htim->Instance->CR2 = tmpcr2; |
| mbed_official | 133:d4dda5c437f0 | 3902 | |
| mbed_official | 133:d4dda5c437f0 | 3903 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 3904 | } |
| mbed_official | 133:d4dda5c437f0 | 3905 | |
| mbed_official | 133:d4dda5c437f0 | 3906 | /** |
| mbed_official | 133:d4dda5c437f0 | 3907 | * @brief Configures the TIM in Slave mode |
| mbed_official | 133:d4dda5c437f0 | 3908 | * @param htim: TIM handle. |
| mbed_official | 133:d4dda5c437f0 | 3909 | * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that |
| mbed_official | 133:d4dda5c437f0 | 3910 | * contains the selected trigger (internal trigger input, filtered |
| mbed_official | 133:d4dda5c437f0 | 3911 | * timer input or external trigger input) and the ) and the Slave |
| mbed_official | 133:d4dda5c437f0 | 3912 | * mode (Disable, Reset, Gated, Trigger, External clock mode 1). |
| mbed_official | 133:d4dda5c437f0 | 3913 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 3914 | */ |
| mbed_official | 133:d4dda5c437f0 | 3915 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) |
| mbed_official | 133:d4dda5c437f0 | 3916 | { |
| mbed_official | 133:d4dda5c437f0 | 3917 | uint32_t tmpsmcr = 0; |
| mbed_official | 133:d4dda5c437f0 | 3918 | uint32_t tmpccmr1 = 0; |
| mbed_official | 133:d4dda5c437f0 | 3919 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 3920 | |
| mbed_official | 133:d4dda5c437f0 | 3921 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3922 | assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3923 | assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); |
| mbed_official | 133:d4dda5c437f0 | 3924 | assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); |
| mbed_official | 133:d4dda5c437f0 | 3925 | |
| mbed_official | 133:d4dda5c437f0 | 3926 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 3927 | |
| mbed_official | 133:d4dda5c437f0 | 3928 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 3929 | |
| mbed_official | 133:d4dda5c437f0 | 3930 | /* Get the TIMx SMCR register value */ |
| mbed_official | 133:d4dda5c437f0 | 3931 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 133:d4dda5c437f0 | 3932 | |
| mbed_official | 133:d4dda5c437f0 | 3933 | /* Reset the Trigger Selection Bits */ |
| mbed_official | 133:d4dda5c437f0 | 3934 | tmpsmcr &= ~TIM_SMCR_TS; |
| mbed_official | 133:d4dda5c437f0 | 3935 | /* Set the Input Trigger source */ |
| mbed_official | 133:d4dda5c437f0 | 3936 | tmpsmcr |= sSlaveConfig->InputTrigger; |
| mbed_official | 133:d4dda5c437f0 | 3937 | |
| mbed_official | 133:d4dda5c437f0 | 3938 | /* Reset the slave mode Bits */ |
| mbed_official | 133:d4dda5c437f0 | 3939 | tmpsmcr &= ~TIM_SMCR_SMS; |
| mbed_official | 133:d4dda5c437f0 | 3940 | /* Set the slave mode */ |
| mbed_official | 133:d4dda5c437f0 | 3941 | tmpsmcr |= sSlaveConfig->SlaveMode; |
| mbed_official | 133:d4dda5c437f0 | 3942 | |
| mbed_official | 133:d4dda5c437f0 | 3943 | /* Write to TIMx SMCR */ |
| mbed_official | 133:d4dda5c437f0 | 3944 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 133:d4dda5c437f0 | 3945 | |
| mbed_official | 133:d4dda5c437f0 | 3946 | /* Configure the trigger prescaler, filter, and polarity */ |
| mbed_official | 133:d4dda5c437f0 | 3947 | switch (sSlaveConfig->InputTrigger) |
| mbed_official | 133:d4dda5c437f0 | 3948 | { |
| mbed_official | 133:d4dda5c437f0 | 3949 | case TIM_TS_ETRF: |
| mbed_official | 133:d4dda5c437f0 | 3950 | { |
| mbed_official | 133:d4dda5c437f0 | 3951 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3952 | assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3953 | assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); |
| mbed_official | 133:d4dda5c437f0 | 3954 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 3955 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); |
| mbed_official | 133:d4dda5c437f0 | 3956 | /* Configure the ETR Trigger source */ |
| mbed_official | 133:d4dda5c437f0 | 3957 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 3958 | sSlaveConfig->TriggerPrescaler, |
| mbed_official | 133:d4dda5c437f0 | 3959 | sSlaveConfig->TriggerPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3960 | sSlaveConfig->TriggerFilter); |
| mbed_official | 133:d4dda5c437f0 | 3961 | } |
| mbed_official | 133:d4dda5c437f0 | 3962 | break; |
| mbed_official | 133:d4dda5c437f0 | 3963 | |
| mbed_official | 133:d4dda5c437f0 | 3964 | case TIM_TS_TI1F_ED: |
| mbed_official | 133:d4dda5c437f0 | 3965 | { |
| mbed_official | 133:d4dda5c437f0 | 3966 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3967 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3968 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); |
| mbed_official | 133:d4dda5c437f0 | 3969 | |
| mbed_official | 133:d4dda5c437f0 | 3970 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 3971 | tmpccer = htim->Instance->CCER; |
| mbed_official | 133:d4dda5c437f0 | 3972 | htim->Instance->CCER &= ~TIM_CCER_CC1E; |
| mbed_official | 133:d4dda5c437f0 | 3973 | tmpccmr1 = htim->Instance->CCMR1; |
| mbed_official | 133:d4dda5c437f0 | 3974 | |
| mbed_official | 133:d4dda5c437f0 | 3975 | /* Set the filter */ |
| mbed_official | 133:d4dda5c437f0 | 3976 | tmpccmr1 &= ~TIM_CCMR1_IC1F; |
| mbed_official | 133:d4dda5c437f0 | 3977 | tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); |
| mbed_official | 133:d4dda5c437f0 | 3978 | |
| mbed_official | 133:d4dda5c437f0 | 3979 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 133:d4dda5c437f0 | 3980 | htim->Instance->CCMR1 = tmpccmr1; |
| mbed_official | 133:d4dda5c437f0 | 3981 | htim->Instance->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 3982 | |
| mbed_official | 133:d4dda5c437f0 | 3983 | } |
| mbed_official | 133:d4dda5c437f0 | 3984 | break; |
| mbed_official | 133:d4dda5c437f0 | 3985 | |
| mbed_official | 133:d4dda5c437f0 | 3986 | case TIM_TS_TI1FP1: |
| mbed_official | 133:d4dda5c437f0 | 3987 | { |
| mbed_official | 133:d4dda5c437f0 | 3988 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 3989 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 3990 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 3991 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); |
| mbed_official | 133:d4dda5c437f0 | 3992 | |
| mbed_official | 133:d4dda5c437f0 | 3993 | /* Configure TI1 Filter and Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 3994 | TIM_TI1_ConfigInputStage(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 3995 | sSlaveConfig->TriggerPolarity, |
| mbed_official | 133:d4dda5c437f0 | 3996 | sSlaveConfig->TriggerFilter); |
| mbed_official | 133:d4dda5c437f0 | 3997 | } |
| mbed_official | 133:d4dda5c437f0 | 3998 | break; |
| mbed_official | 133:d4dda5c437f0 | 3999 | |
| mbed_official | 133:d4dda5c437f0 | 4000 | case TIM_TS_TI2FP2: |
| mbed_official | 133:d4dda5c437f0 | 4001 | { |
| mbed_official | 133:d4dda5c437f0 | 4002 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 4003 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4004 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 4005 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); |
| mbed_official | 133:d4dda5c437f0 | 4006 | |
| mbed_official | 133:d4dda5c437f0 | 4007 | /* Configure TI2 Filter and Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4008 | TIM_TI2_ConfigInputStage(htim->Instance, |
| mbed_official | 133:d4dda5c437f0 | 4009 | sSlaveConfig->TriggerPolarity, |
| mbed_official | 133:d4dda5c437f0 | 4010 | sSlaveConfig->TriggerFilter); |
| mbed_official | 133:d4dda5c437f0 | 4011 | } |
| mbed_official | 133:d4dda5c437f0 | 4012 | break; |
| mbed_official | 133:d4dda5c437f0 | 4013 | |
| mbed_official | 133:d4dda5c437f0 | 4014 | case TIM_TS_ITR0: |
| mbed_official | 133:d4dda5c437f0 | 4015 | { |
| mbed_official | 133:d4dda5c437f0 | 4016 | /* Check the parameter */ |
| mbed_official | 133:d4dda5c437f0 | 4017 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4018 | } |
| mbed_official | 133:d4dda5c437f0 | 4019 | break; |
| mbed_official | 133:d4dda5c437f0 | 4020 | |
| mbed_official | 133:d4dda5c437f0 | 4021 | case TIM_TS_ITR1: |
| mbed_official | 133:d4dda5c437f0 | 4022 | { |
| mbed_official | 133:d4dda5c437f0 | 4023 | /* Check the parameter */ |
| mbed_official | 133:d4dda5c437f0 | 4024 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4025 | } |
| mbed_official | 133:d4dda5c437f0 | 4026 | break; |
| mbed_official | 133:d4dda5c437f0 | 4027 | |
| mbed_official | 133:d4dda5c437f0 | 4028 | case TIM_TS_ITR2: |
| mbed_official | 133:d4dda5c437f0 | 4029 | { |
| mbed_official | 133:d4dda5c437f0 | 4030 | /* Check the parameter */ |
| mbed_official | 133:d4dda5c437f0 | 4031 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4032 | } |
| mbed_official | 133:d4dda5c437f0 | 4033 | break; |
| mbed_official | 133:d4dda5c437f0 | 4034 | |
| mbed_official | 133:d4dda5c437f0 | 4035 | case TIM_TS_ITR3: |
| mbed_official | 133:d4dda5c437f0 | 4036 | { |
| mbed_official | 133:d4dda5c437f0 | 4037 | /* Check the parameter */ |
| mbed_official | 133:d4dda5c437f0 | 4038 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4039 | } |
| mbed_official | 133:d4dda5c437f0 | 4040 | break; |
| mbed_official | 133:d4dda5c437f0 | 4041 | |
| mbed_official | 133:d4dda5c437f0 | 4042 | default: |
| mbed_official | 133:d4dda5c437f0 | 4043 | break; |
| mbed_official | 133:d4dda5c437f0 | 4044 | } |
| mbed_official | 133:d4dda5c437f0 | 4045 | |
| mbed_official | 133:d4dda5c437f0 | 4046 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 4047 | |
| mbed_official | 133:d4dda5c437f0 | 4048 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 4049 | |
| mbed_official | 133:d4dda5c437f0 | 4050 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 4051 | } |
| mbed_official | 133:d4dda5c437f0 | 4052 | |
| mbed_official | 133:d4dda5c437f0 | 4053 | /** |
| mbed_official | 133:d4dda5c437f0 | 4054 | * @brief Read the captured value from Capture Compare unit |
| mbed_official | 133:d4dda5c437f0 | 4055 | * @param htim: TIM handle. |
| mbed_official | 133:d4dda5c437f0 | 4056 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 133:d4dda5c437f0 | 4057 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4058 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 133:d4dda5c437f0 | 4059 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 133:d4dda5c437f0 | 4060 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 133:d4dda5c437f0 | 4061 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 133:d4dda5c437f0 | 4062 | * @retval Captured value |
| mbed_official | 133:d4dda5c437f0 | 4063 | */ |
| mbed_official | 133:d4dda5c437f0 | 4064 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 133:d4dda5c437f0 | 4065 | { |
| mbed_official | 133:d4dda5c437f0 | 4066 | uint32_t tmpreg = 0; |
| mbed_official | 133:d4dda5c437f0 | 4067 | |
| mbed_official | 133:d4dda5c437f0 | 4068 | __HAL_LOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 4069 | |
| mbed_official | 133:d4dda5c437f0 | 4070 | switch (Channel) |
| mbed_official | 133:d4dda5c437f0 | 4071 | { |
| mbed_official | 133:d4dda5c437f0 | 4072 | case TIM_CHANNEL_1: |
| mbed_official | 133:d4dda5c437f0 | 4073 | { |
| mbed_official | 133:d4dda5c437f0 | 4074 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 4075 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4076 | |
| mbed_official | 133:d4dda5c437f0 | 4077 | /* Return the capture 1 value */ |
| mbed_official | 133:d4dda5c437f0 | 4078 | tmpreg = htim->Instance->CCR1; |
| mbed_official | 133:d4dda5c437f0 | 4079 | |
| mbed_official | 133:d4dda5c437f0 | 4080 | break; |
| mbed_official | 133:d4dda5c437f0 | 4081 | } |
| mbed_official | 133:d4dda5c437f0 | 4082 | case TIM_CHANNEL_2: |
| mbed_official | 133:d4dda5c437f0 | 4083 | { |
| mbed_official | 133:d4dda5c437f0 | 4084 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 4085 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4086 | |
| mbed_official | 133:d4dda5c437f0 | 4087 | /* Return the capture 2 value */ |
| mbed_official | 133:d4dda5c437f0 | 4088 | tmpreg = htim->Instance->CCR2; |
| mbed_official | 133:d4dda5c437f0 | 4089 | |
| mbed_official | 133:d4dda5c437f0 | 4090 | break; |
| mbed_official | 133:d4dda5c437f0 | 4091 | } |
| mbed_official | 133:d4dda5c437f0 | 4092 | |
| mbed_official | 133:d4dda5c437f0 | 4093 | case TIM_CHANNEL_3: |
| mbed_official | 133:d4dda5c437f0 | 4094 | { |
| mbed_official | 133:d4dda5c437f0 | 4095 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 4096 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4097 | |
| mbed_official | 133:d4dda5c437f0 | 4098 | /* Return the capture 3 value */ |
| mbed_official | 133:d4dda5c437f0 | 4099 | tmpreg = htim->Instance->CCR3; |
| mbed_official | 133:d4dda5c437f0 | 4100 | |
| mbed_official | 133:d4dda5c437f0 | 4101 | break; |
| mbed_official | 133:d4dda5c437f0 | 4102 | } |
| mbed_official | 133:d4dda5c437f0 | 4103 | |
| mbed_official | 133:d4dda5c437f0 | 4104 | case TIM_CHANNEL_4: |
| mbed_official | 133:d4dda5c437f0 | 4105 | { |
| mbed_official | 133:d4dda5c437f0 | 4106 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 4107 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 133:d4dda5c437f0 | 4108 | |
| mbed_official | 133:d4dda5c437f0 | 4109 | /* Return the capture 4 value */ |
| mbed_official | 133:d4dda5c437f0 | 4110 | tmpreg = htim->Instance->CCR4; |
| mbed_official | 133:d4dda5c437f0 | 4111 | |
| mbed_official | 133:d4dda5c437f0 | 4112 | break; |
| mbed_official | 133:d4dda5c437f0 | 4113 | } |
| mbed_official | 133:d4dda5c437f0 | 4114 | |
| mbed_official | 133:d4dda5c437f0 | 4115 | default: |
| mbed_official | 133:d4dda5c437f0 | 4116 | break; |
| mbed_official | 133:d4dda5c437f0 | 4117 | } |
| mbed_official | 133:d4dda5c437f0 | 4118 | |
| mbed_official | 133:d4dda5c437f0 | 4119 | __HAL_UNLOCK(htim); |
| mbed_official | 133:d4dda5c437f0 | 4120 | return tmpreg; |
| mbed_official | 133:d4dda5c437f0 | 4121 | } |
| mbed_official | 133:d4dda5c437f0 | 4122 | |
| mbed_official | 133:d4dda5c437f0 | 4123 | /** |
| mbed_official | 133:d4dda5c437f0 | 4124 | * @} |
| mbed_official | 133:d4dda5c437f0 | 4125 | */ |
| mbed_official | 133:d4dda5c437f0 | 4126 | |
| mbed_official | 133:d4dda5c437f0 | 4127 | /** @defgroup TIM_Group9 TIM Callbacks functions |
| mbed_official | 133:d4dda5c437f0 | 4128 | * @brief TIM Callbacks functions |
| mbed_official | 133:d4dda5c437f0 | 4129 | * |
| mbed_official | 133:d4dda5c437f0 | 4130 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 4131 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 4132 | ##### TIM Callbacks functions ##### |
| mbed_official | 133:d4dda5c437f0 | 4133 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 4134 | [..] |
| mbed_official | 133:d4dda5c437f0 | 4135 | This section provides TIM callback functions: |
| mbed_official | 133:d4dda5c437f0 | 4136 | (+) Timer Period elapsed callback |
| mbed_official | 133:d4dda5c437f0 | 4137 | (+) Timer Output Compare callback |
| mbed_official | 133:d4dda5c437f0 | 4138 | (+) Timer Input capture callback |
| mbed_official | 133:d4dda5c437f0 | 4139 | (+) Timer Trigger callback |
| mbed_official | 133:d4dda5c437f0 | 4140 | (+) Timer Error callback |
| mbed_official | 133:d4dda5c437f0 | 4141 | |
| mbed_official | 133:d4dda5c437f0 | 4142 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 4143 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 4144 | */ |
| mbed_official | 133:d4dda5c437f0 | 4145 | |
| mbed_official | 133:d4dda5c437f0 | 4146 | /** |
| mbed_official | 133:d4dda5c437f0 | 4147 | * @brief Period elapsed callback in non blocking mode |
| mbed_official | 133:d4dda5c437f0 | 4148 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 4149 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4150 | */ |
| mbed_official | 133:d4dda5c437f0 | 4151 | __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4152 | { |
| mbed_official | 133:d4dda5c437f0 | 4153 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 4154 | the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 4155 | */ |
| mbed_official | 133:d4dda5c437f0 | 4156 | |
| mbed_official | 133:d4dda5c437f0 | 4157 | } |
| mbed_official | 133:d4dda5c437f0 | 4158 | /** |
| mbed_official | 133:d4dda5c437f0 | 4159 | * @brief Output Compare callback in non blocking mode |
| mbed_official | 133:d4dda5c437f0 | 4160 | * @param htim : TIM OC handle |
| mbed_official | 133:d4dda5c437f0 | 4161 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4162 | */ |
| mbed_official | 133:d4dda5c437f0 | 4163 | __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4164 | { |
| mbed_official | 133:d4dda5c437f0 | 4165 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 4166 | the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 4167 | */ |
| mbed_official | 133:d4dda5c437f0 | 4168 | } |
| mbed_official | 133:d4dda5c437f0 | 4169 | /** |
| mbed_official | 133:d4dda5c437f0 | 4170 | * @brief Input Capture callback in non blocking mode |
| mbed_official | 133:d4dda5c437f0 | 4171 | * @param htim : TIM IC handle |
| mbed_official | 133:d4dda5c437f0 | 4172 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4173 | */ |
| mbed_official | 133:d4dda5c437f0 | 4174 | __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4175 | { |
| mbed_official | 133:d4dda5c437f0 | 4176 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 4177 | the __HAL_TIM_IC_CaptureCallback could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 4178 | */ |
| mbed_official | 133:d4dda5c437f0 | 4179 | } |
| mbed_official | 133:d4dda5c437f0 | 4180 | |
| mbed_official | 133:d4dda5c437f0 | 4181 | /** |
| mbed_official | 133:d4dda5c437f0 | 4182 | * @brief PWM Pulse finished callback in non blocking mode |
| mbed_official | 133:d4dda5c437f0 | 4183 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 4184 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4185 | */ |
| mbed_official | 133:d4dda5c437f0 | 4186 | __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4187 | { |
| mbed_official | 133:d4dda5c437f0 | 4188 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 4189 | the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 4190 | */ |
| mbed_official | 133:d4dda5c437f0 | 4191 | } |
| mbed_official | 133:d4dda5c437f0 | 4192 | |
| mbed_official | 133:d4dda5c437f0 | 4193 | /** |
| mbed_official | 133:d4dda5c437f0 | 4194 | * @brief Hall Trigger detection callback in non blocking mode |
| mbed_official | 133:d4dda5c437f0 | 4195 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 4196 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4197 | */ |
| mbed_official | 133:d4dda5c437f0 | 4198 | __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4199 | { |
| mbed_official | 133:d4dda5c437f0 | 4200 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 4201 | the HAL_TIM_TriggerCallback could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 4202 | */ |
| mbed_official | 133:d4dda5c437f0 | 4203 | } |
| mbed_official | 133:d4dda5c437f0 | 4204 | |
| mbed_official | 133:d4dda5c437f0 | 4205 | /** |
| mbed_official | 133:d4dda5c437f0 | 4206 | * @brief Timer error callback in non blocking mode |
| mbed_official | 133:d4dda5c437f0 | 4207 | * @param htim : TIM handle |
| mbed_official | 133:d4dda5c437f0 | 4208 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4209 | */ |
| mbed_official | 133:d4dda5c437f0 | 4210 | __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4211 | { |
| mbed_official | 133:d4dda5c437f0 | 4212 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 133:d4dda5c437f0 | 4213 | the HAL_TIM_ErrorCallback could be implemented in the user file |
| mbed_official | 133:d4dda5c437f0 | 4214 | */ |
| mbed_official | 133:d4dda5c437f0 | 4215 | } |
| mbed_official | 133:d4dda5c437f0 | 4216 | |
| mbed_official | 133:d4dda5c437f0 | 4217 | /** |
| mbed_official | 133:d4dda5c437f0 | 4218 | * @} |
| mbed_official | 133:d4dda5c437f0 | 4219 | */ |
| mbed_official | 133:d4dda5c437f0 | 4220 | |
| mbed_official | 133:d4dda5c437f0 | 4221 | /** @defgroup TIM_Group10 Peripheral State functions |
| mbed_official | 133:d4dda5c437f0 | 4222 | * @brief Peripheral State functions |
| mbed_official | 133:d4dda5c437f0 | 4223 | * |
| mbed_official | 133:d4dda5c437f0 | 4224 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 4225 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 4226 | ##### Peripheral State functions ##### |
| mbed_official | 133:d4dda5c437f0 | 4227 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 4228 | [..] |
| mbed_official | 133:d4dda5c437f0 | 4229 | This subsection permit to get in run-time the status of the peripheral |
| mbed_official | 133:d4dda5c437f0 | 4230 | and the data flow. |
| mbed_official | 133:d4dda5c437f0 | 4231 | |
| mbed_official | 133:d4dda5c437f0 | 4232 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 4233 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 4234 | */ |
| mbed_official | 133:d4dda5c437f0 | 4235 | |
| mbed_official | 133:d4dda5c437f0 | 4236 | /** |
| mbed_official | 133:d4dda5c437f0 | 4237 | * @brief Return the TIM Base state |
| mbed_official | 133:d4dda5c437f0 | 4238 | * @param htim: TIM Base handle |
| mbed_official | 133:d4dda5c437f0 | 4239 | * @retval HAL state |
| mbed_official | 133:d4dda5c437f0 | 4240 | */ |
| mbed_official | 133:d4dda5c437f0 | 4241 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4242 | { |
| mbed_official | 133:d4dda5c437f0 | 4243 | return htim->State; |
| mbed_official | 133:d4dda5c437f0 | 4244 | } |
| mbed_official | 133:d4dda5c437f0 | 4245 | |
| mbed_official | 133:d4dda5c437f0 | 4246 | /** |
| mbed_official | 133:d4dda5c437f0 | 4247 | * @brief Return the TIM OC state |
| mbed_official | 133:d4dda5c437f0 | 4248 | * @param htim: TIM Ouput Compare handle |
| mbed_official | 133:d4dda5c437f0 | 4249 | * @retval HAL state |
| mbed_official | 133:d4dda5c437f0 | 4250 | */ |
| mbed_official | 133:d4dda5c437f0 | 4251 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4252 | { |
| mbed_official | 133:d4dda5c437f0 | 4253 | return htim->State; |
| mbed_official | 133:d4dda5c437f0 | 4254 | } |
| mbed_official | 133:d4dda5c437f0 | 4255 | |
| mbed_official | 133:d4dda5c437f0 | 4256 | /** |
| mbed_official | 133:d4dda5c437f0 | 4257 | * @brief Return the TIM PWM state |
| mbed_official | 133:d4dda5c437f0 | 4258 | * @param htim: TIM handle |
| mbed_official | 133:d4dda5c437f0 | 4259 | * @retval HAL state |
| mbed_official | 133:d4dda5c437f0 | 4260 | */ |
| mbed_official | 133:d4dda5c437f0 | 4261 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4262 | { |
| mbed_official | 133:d4dda5c437f0 | 4263 | return htim->State; |
| mbed_official | 133:d4dda5c437f0 | 4264 | } |
| mbed_official | 133:d4dda5c437f0 | 4265 | |
| mbed_official | 133:d4dda5c437f0 | 4266 | /** |
| mbed_official | 133:d4dda5c437f0 | 4267 | * @brief Return the TIM Input Capture state |
| mbed_official | 133:d4dda5c437f0 | 4268 | * @param htim: TIM IC handle |
| mbed_official | 133:d4dda5c437f0 | 4269 | * @retval HAL state |
| mbed_official | 133:d4dda5c437f0 | 4270 | */ |
| mbed_official | 133:d4dda5c437f0 | 4271 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4272 | { |
| mbed_official | 133:d4dda5c437f0 | 4273 | return htim->State; |
| mbed_official | 133:d4dda5c437f0 | 4274 | } |
| mbed_official | 133:d4dda5c437f0 | 4275 | |
| mbed_official | 133:d4dda5c437f0 | 4276 | /** |
| mbed_official | 133:d4dda5c437f0 | 4277 | * @brief Return the TIM One Pulse Mode state |
| mbed_official | 133:d4dda5c437f0 | 4278 | * @param htim: TIM OPM handle |
| mbed_official | 133:d4dda5c437f0 | 4279 | * @retval HAL state |
| mbed_official | 133:d4dda5c437f0 | 4280 | */ |
| mbed_official | 133:d4dda5c437f0 | 4281 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4282 | { |
| mbed_official | 133:d4dda5c437f0 | 4283 | return htim->State; |
| mbed_official | 133:d4dda5c437f0 | 4284 | } |
| mbed_official | 133:d4dda5c437f0 | 4285 | |
| mbed_official | 133:d4dda5c437f0 | 4286 | /** |
| mbed_official | 133:d4dda5c437f0 | 4287 | * @brief Return the TIM Encoder Mode state |
| mbed_official | 133:d4dda5c437f0 | 4288 | * @param htim: TIM Encoder handle |
| mbed_official | 133:d4dda5c437f0 | 4289 | * @retval HAL state |
| mbed_official | 133:d4dda5c437f0 | 4290 | */ |
| mbed_official | 133:d4dda5c437f0 | 4291 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 133:d4dda5c437f0 | 4292 | { |
| mbed_official | 133:d4dda5c437f0 | 4293 | return htim->State; |
| mbed_official | 133:d4dda5c437f0 | 4294 | } |
| mbed_official | 133:d4dda5c437f0 | 4295 | |
| mbed_official | 133:d4dda5c437f0 | 4296 | /** |
| mbed_official | 133:d4dda5c437f0 | 4297 | * @} |
| mbed_official | 133:d4dda5c437f0 | 4298 | */ |
| mbed_official | 133:d4dda5c437f0 | 4299 | |
| mbed_official | 133:d4dda5c437f0 | 4300 | /** |
| mbed_official | 133:d4dda5c437f0 | 4301 | * @brief TIM DMA error callback |
| mbed_official | 133:d4dda5c437f0 | 4302 | * @param hdma : pointer to DMA handle. |
| mbed_official | 133:d4dda5c437f0 | 4303 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4304 | */ |
| mbed_official | 133:d4dda5c437f0 | 4305 | void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) |
| mbed_official | 133:d4dda5c437f0 | 4306 | { |
| mbed_official | 133:d4dda5c437f0 | 4307 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 133:d4dda5c437f0 | 4308 | |
| mbed_official | 133:d4dda5c437f0 | 4309 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 4310 | |
| mbed_official | 133:d4dda5c437f0 | 4311 | HAL_TIM_ErrorCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 4312 | } |
| mbed_official | 133:d4dda5c437f0 | 4313 | |
| mbed_official | 133:d4dda5c437f0 | 4314 | /** |
| mbed_official | 133:d4dda5c437f0 | 4315 | * @brief TIM DMA Delay Pulse complete callback. |
| mbed_official | 133:d4dda5c437f0 | 4316 | * @param hdma : pointer to DMA handle. |
| mbed_official | 133:d4dda5c437f0 | 4317 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4318 | */ |
| mbed_official | 133:d4dda5c437f0 | 4319 | void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 133:d4dda5c437f0 | 4320 | { |
| mbed_official | 133:d4dda5c437f0 | 4321 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 133:d4dda5c437f0 | 4322 | |
| mbed_official | 133:d4dda5c437f0 | 4323 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 4324 | |
| mbed_official | 133:d4dda5c437f0 | 4325 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 4326 | } |
| mbed_official | 133:d4dda5c437f0 | 4327 | /** |
| mbed_official | 133:d4dda5c437f0 | 4328 | * @brief TIM DMA Capture complete callback. |
| mbed_official | 133:d4dda5c437f0 | 4329 | * @param hdma : pointer to DMA handle. |
| mbed_official | 133:d4dda5c437f0 | 4330 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4331 | */ |
| mbed_official | 133:d4dda5c437f0 | 4332 | void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 133:d4dda5c437f0 | 4333 | { |
| mbed_official | 133:d4dda5c437f0 | 4334 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 133:d4dda5c437f0 | 4335 | |
| mbed_official | 133:d4dda5c437f0 | 4336 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 4337 | |
| mbed_official | 133:d4dda5c437f0 | 4338 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 4339 | |
| mbed_official | 133:d4dda5c437f0 | 4340 | } |
| mbed_official | 133:d4dda5c437f0 | 4341 | |
| mbed_official | 133:d4dda5c437f0 | 4342 | /** |
| mbed_official | 133:d4dda5c437f0 | 4343 | * @brief TIM DMA Period Elapse complete callback. |
| mbed_official | 133:d4dda5c437f0 | 4344 | * @param hdma : pointer to DMA handle. |
| mbed_official | 133:d4dda5c437f0 | 4345 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4346 | */ |
| mbed_official | 133:d4dda5c437f0 | 4347 | static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 133:d4dda5c437f0 | 4348 | { |
| mbed_official | 133:d4dda5c437f0 | 4349 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 133:d4dda5c437f0 | 4350 | |
| mbed_official | 133:d4dda5c437f0 | 4351 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 4352 | |
| mbed_official | 133:d4dda5c437f0 | 4353 | HAL_TIM_PeriodElapsedCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 4354 | } |
| mbed_official | 133:d4dda5c437f0 | 4355 | |
| mbed_official | 133:d4dda5c437f0 | 4356 | /** |
| mbed_official | 133:d4dda5c437f0 | 4357 | * @brief TIM DMA Trigger callback. |
| mbed_official | 133:d4dda5c437f0 | 4358 | * @param hdma : pointer to DMA handle. |
| mbed_official | 133:d4dda5c437f0 | 4359 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4360 | */ |
| mbed_official | 133:d4dda5c437f0 | 4361 | static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 133:d4dda5c437f0 | 4362 | { |
| mbed_official | 133:d4dda5c437f0 | 4363 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 133:d4dda5c437f0 | 4364 | |
| mbed_official | 133:d4dda5c437f0 | 4365 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 4366 | |
| mbed_official | 133:d4dda5c437f0 | 4367 | HAL_TIM_TriggerCallback(htim); |
| mbed_official | 133:d4dda5c437f0 | 4368 | } |
| mbed_official | 133:d4dda5c437f0 | 4369 | |
| mbed_official | 133:d4dda5c437f0 | 4370 | /** |
| mbed_official | 133:d4dda5c437f0 | 4371 | * @brief Time Base configuration |
| mbed_official | 133:d4dda5c437f0 | 4372 | * @param TIMx: TIM periheral |
| mbed_official | 133:d4dda5c437f0 | 4373 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4374 | */ |
| mbed_official | 133:d4dda5c437f0 | 4375 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) |
| mbed_official | 133:d4dda5c437f0 | 4376 | { |
| mbed_official | 133:d4dda5c437f0 | 4377 | uint32_t tmpcr1 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4378 | tmpcr1 = TIMx->CR1; |
| mbed_official | 133:d4dda5c437f0 | 4379 | |
| mbed_official | 133:d4dda5c437f0 | 4380 | /* Set TIM Time Base Unit parameters ---------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 4381 | if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 4382 | { |
| mbed_official | 133:d4dda5c437f0 | 4383 | /* Select the Counter Mode */ |
| mbed_official | 133:d4dda5c437f0 | 4384 | tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); |
| mbed_official | 133:d4dda5c437f0 | 4385 | tmpcr1 |= Structure->CounterMode; |
| mbed_official | 133:d4dda5c437f0 | 4386 | } |
| mbed_official | 133:d4dda5c437f0 | 4387 | |
| mbed_official | 133:d4dda5c437f0 | 4388 | if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 4389 | { |
| mbed_official | 133:d4dda5c437f0 | 4390 | /* Set the clock division */ |
| mbed_official | 133:d4dda5c437f0 | 4391 | tmpcr1 &= ~TIM_CR1_CKD; |
| mbed_official | 133:d4dda5c437f0 | 4392 | tmpcr1 |= (uint32_t)Structure->ClockDivision; |
| mbed_official | 133:d4dda5c437f0 | 4393 | } |
| mbed_official | 133:d4dda5c437f0 | 4394 | |
| mbed_official | 133:d4dda5c437f0 | 4395 | TIMx->CR1 = tmpcr1; |
| mbed_official | 133:d4dda5c437f0 | 4396 | |
| mbed_official | 133:d4dda5c437f0 | 4397 | /* Set the Autoreload value */ |
| mbed_official | 133:d4dda5c437f0 | 4398 | TIMx->ARR = (uint32_t)Structure->Period ; |
| mbed_official | 133:d4dda5c437f0 | 4399 | |
| mbed_official | 133:d4dda5c437f0 | 4400 | /* Set the Prescaler value */ |
| mbed_official | 133:d4dda5c437f0 | 4401 | TIMx->PSC = (uint32_t)Structure->Prescaler; |
| mbed_official | 133:d4dda5c437f0 | 4402 | |
| mbed_official | 133:d4dda5c437f0 | 4403 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 4404 | { |
| mbed_official | 133:d4dda5c437f0 | 4405 | /* Set the Repetition Counter value */ |
| mbed_official | 133:d4dda5c437f0 | 4406 | TIMx->RCR = Structure->RepetitionCounter; |
| mbed_official | 133:d4dda5c437f0 | 4407 | } |
| mbed_official | 133:d4dda5c437f0 | 4408 | |
| mbed_official | 133:d4dda5c437f0 | 4409 | /* Generate an update event to reload the Prescaler |
| mbed_official | 133:d4dda5c437f0 | 4410 | and the repetition counter(only for TIM1 and TIM8) value immediatly */ |
| mbed_official | 133:d4dda5c437f0 | 4411 | TIMx->EGR = TIM_EGR_UG; |
| mbed_official | 133:d4dda5c437f0 | 4412 | } |
| mbed_official | 133:d4dda5c437f0 | 4413 | |
| mbed_official | 133:d4dda5c437f0 | 4414 | /** |
| mbed_official | 133:d4dda5c437f0 | 4415 | * @brief Time Ouput Compare 1 configuration |
| mbed_official | 133:d4dda5c437f0 | 4416 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4417 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 133:d4dda5c437f0 | 4418 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4419 | */ |
| mbed_official | 133:d4dda5c437f0 | 4420 | static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 133:d4dda5c437f0 | 4421 | { |
| mbed_official | 133:d4dda5c437f0 | 4422 | uint32_t tmpccmrx = 0; |
| mbed_official | 133:d4dda5c437f0 | 4423 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4424 | uint32_t tmpcr2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4425 | |
| mbed_official | 133:d4dda5c437f0 | 4426 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4427 | TIMx->CCER &= ~TIM_CCER_CC1E; |
| mbed_official | 133:d4dda5c437f0 | 4428 | |
| mbed_official | 133:d4dda5c437f0 | 4429 | /* Get the TIMx CCER register value */ |
| mbed_official | 133:d4dda5c437f0 | 4430 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4431 | /* Get the TIMx CR2 register value */ |
| mbed_official | 133:d4dda5c437f0 | 4432 | tmpcr2 = TIMx->CR2; |
| mbed_official | 133:d4dda5c437f0 | 4433 | |
| mbed_official | 133:d4dda5c437f0 | 4434 | /* Get the TIMx CCMR1 register value */ |
| mbed_official | 133:d4dda5c437f0 | 4435 | tmpccmrx = TIMx->CCMR1; |
| mbed_official | 133:d4dda5c437f0 | 4436 | |
| mbed_official | 133:d4dda5c437f0 | 4437 | /* Reset the Output Compare Mode Bits */ |
| mbed_official | 133:d4dda5c437f0 | 4438 | tmpccmrx &= ~TIM_CCMR1_OC1M; |
| mbed_official | 133:d4dda5c437f0 | 4439 | tmpccmrx &= ~TIM_CCMR1_CC1S; |
| mbed_official | 133:d4dda5c437f0 | 4440 | /* Select the Output Compare Mode */ |
| mbed_official | 133:d4dda5c437f0 | 4441 | tmpccmrx |= OC_Config->OCMode; |
| mbed_official | 133:d4dda5c437f0 | 4442 | |
| mbed_official | 133:d4dda5c437f0 | 4443 | /* Reset the Output Polarity level */ |
| mbed_official | 133:d4dda5c437f0 | 4444 | tmpccer &= ~TIM_CCER_CC1P; |
| mbed_official | 133:d4dda5c437f0 | 4445 | /* Set the Output Compare Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4446 | tmpccer |= OC_Config->OCPolarity; |
| mbed_official | 133:d4dda5c437f0 | 4447 | |
| mbed_official | 133:d4dda5c437f0 | 4448 | |
| mbed_official | 133:d4dda5c437f0 | 4449 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 4450 | { |
| mbed_official | 133:d4dda5c437f0 | 4451 | /* Reset the Output N Polarity level */ |
| mbed_official | 133:d4dda5c437f0 | 4452 | tmpccer &= ~TIM_CCER_CC1NP; |
| mbed_official | 133:d4dda5c437f0 | 4453 | /* Set the Output N Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4454 | tmpccer |= OC_Config->OCNPolarity; |
| mbed_official | 133:d4dda5c437f0 | 4455 | /* Reset the Output N State */ |
| mbed_official | 133:d4dda5c437f0 | 4456 | tmpccer &= ~TIM_CCER_CC1NE; |
| mbed_official | 133:d4dda5c437f0 | 4457 | |
| mbed_official | 133:d4dda5c437f0 | 4458 | /* Reset the Output Compare and Output Compare N IDLE State */ |
| mbed_official | 133:d4dda5c437f0 | 4459 | tmpcr2 &= ~TIM_CR2_OIS1; |
| mbed_official | 133:d4dda5c437f0 | 4460 | tmpcr2 &= ~TIM_CR2_OIS1N; |
| mbed_official | 133:d4dda5c437f0 | 4461 | /* Set the Output Idle state */ |
| mbed_official | 133:d4dda5c437f0 | 4462 | tmpcr2 |= OC_Config->OCIdleState; |
| mbed_official | 133:d4dda5c437f0 | 4463 | /* Set the Output N Idle state */ |
| mbed_official | 133:d4dda5c437f0 | 4464 | tmpcr2 |= OC_Config->OCNIdleState; |
| mbed_official | 133:d4dda5c437f0 | 4465 | } |
| mbed_official | 133:d4dda5c437f0 | 4466 | /* Write to TIMx CR2 */ |
| mbed_official | 133:d4dda5c437f0 | 4467 | TIMx->CR2 = tmpcr2; |
| mbed_official | 133:d4dda5c437f0 | 4468 | |
| mbed_official | 133:d4dda5c437f0 | 4469 | /* Write to TIMx CCMR1 */ |
| mbed_official | 133:d4dda5c437f0 | 4470 | TIMx->CCMR1 = tmpccmrx; |
| mbed_official | 133:d4dda5c437f0 | 4471 | |
| mbed_official | 133:d4dda5c437f0 | 4472 | /* Set the Capture Compare Register value */ |
| mbed_official | 133:d4dda5c437f0 | 4473 | TIMx->CCR1 = OC_Config->Pulse; |
| mbed_official | 133:d4dda5c437f0 | 4474 | |
| mbed_official | 133:d4dda5c437f0 | 4475 | /* Write to TIMx CCER */ |
| mbed_official | 133:d4dda5c437f0 | 4476 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4477 | } |
| mbed_official | 133:d4dda5c437f0 | 4478 | |
| mbed_official | 133:d4dda5c437f0 | 4479 | /** |
| mbed_official | 133:d4dda5c437f0 | 4480 | * @brief Time Ouput Compare 2 configuration |
| mbed_official | 133:d4dda5c437f0 | 4481 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4482 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 133:d4dda5c437f0 | 4483 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4484 | */ |
| mbed_official | 133:d4dda5c437f0 | 4485 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 133:d4dda5c437f0 | 4486 | { |
| mbed_official | 133:d4dda5c437f0 | 4487 | uint32_t tmpccmrx = 0; |
| mbed_official | 133:d4dda5c437f0 | 4488 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4489 | uint32_t tmpcr2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4490 | |
| mbed_official | 133:d4dda5c437f0 | 4491 | /* Disable the Channel 2: Reset the CC2E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4492 | TIMx->CCER &= ~TIM_CCER_CC2E; |
| mbed_official | 133:d4dda5c437f0 | 4493 | |
| mbed_official | 133:d4dda5c437f0 | 4494 | /* Get the TIMx CCER register value */ |
| mbed_official | 133:d4dda5c437f0 | 4495 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4496 | /* Get the TIMx CR2 register value */ |
| mbed_official | 133:d4dda5c437f0 | 4497 | tmpcr2 = TIMx->CR2; |
| mbed_official | 133:d4dda5c437f0 | 4498 | |
| mbed_official | 133:d4dda5c437f0 | 4499 | /* Get the TIMx CCMR1 register value */ |
| mbed_official | 133:d4dda5c437f0 | 4500 | tmpccmrx = TIMx->CCMR1; |
| mbed_official | 133:d4dda5c437f0 | 4501 | |
| mbed_official | 133:d4dda5c437f0 | 4502 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
| mbed_official | 133:d4dda5c437f0 | 4503 | tmpccmrx &= ~TIM_CCMR1_OC2M; |
| mbed_official | 133:d4dda5c437f0 | 4504 | tmpccmrx &= ~TIM_CCMR1_CC2S; |
| mbed_official | 133:d4dda5c437f0 | 4505 | |
| mbed_official | 133:d4dda5c437f0 | 4506 | /* Select the Output Compare Mode */ |
| mbed_official | 133:d4dda5c437f0 | 4507 | tmpccmrx |= (OC_Config->OCMode << 8); |
| mbed_official | 133:d4dda5c437f0 | 4508 | |
| mbed_official | 133:d4dda5c437f0 | 4509 | /* Reset the Output Polarity level */ |
| mbed_official | 133:d4dda5c437f0 | 4510 | tmpccer &= ~TIM_CCER_CC2P; |
| mbed_official | 133:d4dda5c437f0 | 4511 | /* Set the Output Compare Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4512 | tmpccer |= (OC_Config->OCPolarity << 4); |
| mbed_official | 133:d4dda5c437f0 | 4513 | |
| mbed_official | 133:d4dda5c437f0 | 4514 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 4515 | { |
| mbed_official | 133:d4dda5c437f0 | 4516 | assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 4517 | assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 4518 | assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 4519 | |
| mbed_official | 133:d4dda5c437f0 | 4520 | /* Reset the Output N Polarity level */ |
| mbed_official | 133:d4dda5c437f0 | 4521 | tmpccer &= ~TIM_CCER_CC2NP; |
| mbed_official | 133:d4dda5c437f0 | 4522 | /* Set the Output N Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4523 | tmpccer |= (OC_Config->OCNPolarity << 4); |
| mbed_official | 133:d4dda5c437f0 | 4524 | /* Reset the Output N State */ |
| mbed_official | 133:d4dda5c437f0 | 4525 | tmpccer &= ~TIM_CCER_CC2NE; |
| mbed_official | 133:d4dda5c437f0 | 4526 | |
| mbed_official | 133:d4dda5c437f0 | 4527 | /* Reset the Output Compare and Output Compare N IDLE State */ |
| mbed_official | 133:d4dda5c437f0 | 4528 | tmpcr2 &= ~TIM_CR2_OIS2; |
| mbed_official | 133:d4dda5c437f0 | 4529 | tmpcr2 &= ~TIM_CR2_OIS2N; |
| mbed_official | 133:d4dda5c437f0 | 4530 | /* Set the Output Idle state */ |
| mbed_official | 133:d4dda5c437f0 | 4531 | tmpcr2 |= (OC_Config->OCIdleState << 2); |
| mbed_official | 133:d4dda5c437f0 | 4532 | /* Set the Output N Idle state */ |
| mbed_official | 133:d4dda5c437f0 | 4533 | tmpcr2 |= (OC_Config->OCNIdleState << 2); |
| mbed_official | 133:d4dda5c437f0 | 4534 | } |
| mbed_official | 133:d4dda5c437f0 | 4535 | /* Write to TIMx CR2 */ |
| mbed_official | 133:d4dda5c437f0 | 4536 | TIMx->CR2 = tmpcr2; |
| mbed_official | 133:d4dda5c437f0 | 4537 | |
| mbed_official | 133:d4dda5c437f0 | 4538 | /* Write to TIMx CCMR1 */ |
| mbed_official | 133:d4dda5c437f0 | 4539 | TIMx->CCMR1 = tmpccmrx; |
| mbed_official | 133:d4dda5c437f0 | 4540 | |
| mbed_official | 133:d4dda5c437f0 | 4541 | /* Set the Capture Compare Register value */ |
| mbed_official | 133:d4dda5c437f0 | 4542 | TIMx->CCR2 = OC_Config->Pulse; |
| mbed_official | 133:d4dda5c437f0 | 4543 | |
| mbed_official | 133:d4dda5c437f0 | 4544 | /* Write to TIMx CCER */ |
| mbed_official | 133:d4dda5c437f0 | 4545 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4546 | } |
| mbed_official | 133:d4dda5c437f0 | 4547 | |
| mbed_official | 133:d4dda5c437f0 | 4548 | /** |
| mbed_official | 133:d4dda5c437f0 | 4549 | * @brief Time Ouput Compare 3 configuration |
| mbed_official | 133:d4dda5c437f0 | 4550 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4551 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 133:d4dda5c437f0 | 4552 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4553 | */ |
| mbed_official | 133:d4dda5c437f0 | 4554 | static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 133:d4dda5c437f0 | 4555 | { |
| mbed_official | 133:d4dda5c437f0 | 4556 | uint32_t tmpccmrx = 0; |
| mbed_official | 133:d4dda5c437f0 | 4557 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4558 | uint32_t tmpcr2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4559 | |
| mbed_official | 133:d4dda5c437f0 | 4560 | /* Disable the Channel 3: Reset the CC2E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4561 | TIMx->CCER &= ~TIM_CCER_CC3E; |
| mbed_official | 133:d4dda5c437f0 | 4562 | |
| mbed_official | 133:d4dda5c437f0 | 4563 | /* Get the TIMx CCER register value */ |
| mbed_official | 133:d4dda5c437f0 | 4564 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4565 | /* Get the TIMx CR2 register value */ |
| mbed_official | 133:d4dda5c437f0 | 4566 | tmpcr2 = TIMx->CR2; |
| mbed_official | 133:d4dda5c437f0 | 4567 | |
| mbed_official | 133:d4dda5c437f0 | 4568 | /* Get the TIMx CCMR2 register value */ |
| mbed_official | 133:d4dda5c437f0 | 4569 | tmpccmrx = TIMx->CCMR2; |
| mbed_official | 133:d4dda5c437f0 | 4570 | |
| mbed_official | 133:d4dda5c437f0 | 4571 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
| mbed_official | 133:d4dda5c437f0 | 4572 | tmpccmrx &= ~TIM_CCMR2_OC3M; |
| mbed_official | 133:d4dda5c437f0 | 4573 | tmpccmrx &= ~TIM_CCMR2_CC3S; |
| mbed_official | 133:d4dda5c437f0 | 4574 | /* Select the Output Compare Mode */ |
| mbed_official | 133:d4dda5c437f0 | 4575 | tmpccmrx |= OC_Config->OCMode; |
| mbed_official | 133:d4dda5c437f0 | 4576 | |
| mbed_official | 133:d4dda5c437f0 | 4577 | /* Reset the Output Polarity level */ |
| mbed_official | 133:d4dda5c437f0 | 4578 | tmpccer &= ~TIM_CCER_CC3P; |
| mbed_official | 133:d4dda5c437f0 | 4579 | /* Set the Output Compare Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4580 | tmpccer |= (OC_Config->OCPolarity << 8); |
| mbed_official | 133:d4dda5c437f0 | 4581 | |
| mbed_official | 133:d4dda5c437f0 | 4582 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 4583 | { |
| mbed_official | 133:d4dda5c437f0 | 4584 | assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); |
| mbed_official | 133:d4dda5c437f0 | 4585 | assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 4586 | assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 4587 | |
| mbed_official | 133:d4dda5c437f0 | 4588 | /* Reset the Output N Polarity level */ |
| mbed_official | 133:d4dda5c437f0 | 4589 | tmpccer &= ~TIM_CCER_CC3NP; |
| mbed_official | 133:d4dda5c437f0 | 4590 | /* Set the Output N Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4591 | tmpccer |= (OC_Config->OCNPolarity << 8); |
| mbed_official | 133:d4dda5c437f0 | 4592 | /* Reset the Output N State */ |
| mbed_official | 133:d4dda5c437f0 | 4593 | tmpccer &= ~TIM_CCER_CC3NE; |
| mbed_official | 133:d4dda5c437f0 | 4594 | |
| mbed_official | 133:d4dda5c437f0 | 4595 | /* Reset the Output Compare and Output Compare N IDLE State */ |
| mbed_official | 133:d4dda5c437f0 | 4596 | tmpcr2 &= ~TIM_CR2_OIS3; |
| mbed_official | 133:d4dda5c437f0 | 4597 | tmpcr2 &= ~TIM_CR2_OIS3N; |
| mbed_official | 133:d4dda5c437f0 | 4598 | /* Set the Output Idle state */ |
| mbed_official | 133:d4dda5c437f0 | 4599 | tmpcr2 |= (OC_Config->OCIdleState << 4); |
| mbed_official | 133:d4dda5c437f0 | 4600 | /* Set the Output N Idle state */ |
| mbed_official | 133:d4dda5c437f0 | 4601 | tmpcr2 |= (OC_Config->OCNIdleState << 4); |
| mbed_official | 133:d4dda5c437f0 | 4602 | } |
| mbed_official | 133:d4dda5c437f0 | 4603 | /* Write to TIMx CR2 */ |
| mbed_official | 133:d4dda5c437f0 | 4604 | TIMx->CR2 = tmpcr2; |
| mbed_official | 133:d4dda5c437f0 | 4605 | |
| mbed_official | 133:d4dda5c437f0 | 4606 | /* Write to TIMx CCMR2 */ |
| mbed_official | 133:d4dda5c437f0 | 4607 | TIMx->CCMR2 = tmpccmrx; |
| mbed_official | 133:d4dda5c437f0 | 4608 | |
| mbed_official | 133:d4dda5c437f0 | 4609 | /* Set the Capture Compare Register value */ |
| mbed_official | 133:d4dda5c437f0 | 4610 | TIMx->CCR3 = OC_Config->Pulse; |
| mbed_official | 133:d4dda5c437f0 | 4611 | |
| mbed_official | 133:d4dda5c437f0 | 4612 | /* Write to TIMx CCER */ |
| mbed_official | 133:d4dda5c437f0 | 4613 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4614 | } |
| mbed_official | 133:d4dda5c437f0 | 4615 | |
| mbed_official | 133:d4dda5c437f0 | 4616 | /** |
| mbed_official | 133:d4dda5c437f0 | 4617 | * @brief Time Ouput Compare 4 configuration |
| mbed_official | 133:d4dda5c437f0 | 4618 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4619 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 133:d4dda5c437f0 | 4620 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4621 | */ |
| mbed_official | 133:d4dda5c437f0 | 4622 | static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 133:d4dda5c437f0 | 4623 | { |
| mbed_official | 133:d4dda5c437f0 | 4624 | uint32_t tmpccmrx = 0; |
| mbed_official | 133:d4dda5c437f0 | 4625 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4626 | uint32_t tmpcr2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4627 | |
| mbed_official | 133:d4dda5c437f0 | 4628 | /* Disable the Channel 4: Reset the CC4E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4629 | TIMx->CCER &= ~TIM_CCER_CC4E; |
| mbed_official | 133:d4dda5c437f0 | 4630 | |
| mbed_official | 133:d4dda5c437f0 | 4631 | /* Get the TIMx CCER register value */ |
| mbed_official | 133:d4dda5c437f0 | 4632 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4633 | /* Get the TIMx CR2 register value */ |
| mbed_official | 133:d4dda5c437f0 | 4634 | tmpcr2 = TIMx->CR2; |
| mbed_official | 133:d4dda5c437f0 | 4635 | |
| mbed_official | 133:d4dda5c437f0 | 4636 | /* Get the TIMx CCMR2 register value */ |
| mbed_official | 133:d4dda5c437f0 | 4637 | tmpccmrx = TIMx->CCMR2; |
| mbed_official | 133:d4dda5c437f0 | 4638 | |
| mbed_official | 133:d4dda5c437f0 | 4639 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
| mbed_official | 133:d4dda5c437f0 | 4640 | tmpccmrx &= ~TIM_CCMR2_OC4M; |
| mbed_official | 133:d4dda5c437f0 | 4641 | tmpccmrx &= ~TIM_CCMR2_CC4S; |
| mbed_official | 133:d4dda5c437f0 | 4642 | |
| mbed_official | 133:d4dda5c437f0 | 4643 | /* Select the Output Compare Mode */ |
| mbed_official | 133:d4dda5c437f0 | 4644 | tmpccmrx |= (OC_Config->OCMode << 8); |
| mbed_official | 133:d4dda5c437f0 | 4645 | |
| mbed_official | 133:d4dda5c437f0 | 4646 | /* Reset the Output Polarity level */ |
| mbed_official | 133:d4dda5c437f0 | 4647 | tmpccer &= ~TIM_CCER_CC4P; |
| mbed_official | 133:d4dda5c437f0 | 4648 | /* Set the Output Compare Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4649 | tmpccer |= (OC_Config->OCPolarity << 12); |
| mbed_official | 133:d4dda5c437f0 | 4650 | |
| mbed_official | 133:d4dda5c437f0 | 4651 | /*if((TIMx == TIM1) || (TIMx == TIM8))*/ |
| mbed_official | 133:d4dda5c437f0 | 4652 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 4653 | { |
| mbed_official | 133:d4dda5c437f0 | 4654 | assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); |
| mbed_official | 133:d4dda5c437f0 | 4655 | /* Reset the Output Compare IDLE State */ |
| mbed_official | 133:d4dda5c437f0 | 4656 | tmpcr2 &= ~TIM_CR2_OIS4; |
| mbed_official | 133:d4dda5c437f0 | 4657 | /* Set the Output Idle state */ |
| mbed_official | 133:d4dda5c437f0 | 4658 | tmpcr2 |= (OC_Config->OCIdleState << 6); |
| mbed_official | 133:d4dda5c437f0 | 4659 | } |
| mbed_official | 133:d4dda5c437f0 | 4660 | /* Write to TIMx CR2 */ |
| mbed_official | 133:d4dda5c437f0 | 4661 | TIMx->CR2 = tmpcr2; |
| mbed_official | 133:d4dda5c437f0 | 4662 | |
| mbed_official | 133:d4dda5c437f0 | 4663 | /* Write to TIMx CCMR2 */ |
| mbed_official | 133:d4dda5c437f0 | 4664 | TIMx->CCMR2 = tmpccmrx; |
| mbed_official | 133:d4dda5c437f0 | 4665 | |
| mbed_official | 133:d4dda5c437f0 | 4666 | /* Set the Capture Compare Register value */ |
| mbed_official | 133:d4dda5c437f0 | 4667 | TIMx->CCR4 = OC_Config->Pulse; |
| mbed_official | 133:d4dda5c437f0 | 4668 | |
| mbed_official | 133:d4dda5c437f0 | 4669 | /* Write to TIMx CCER */ |
| mbed_official | 133:d4dda5c437f0 | 4670 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4671 | } |
| mbed_official | 133:d4dda5c437f0 | 4672 | |
| mbed_official | 133:d4dda5c437f0 | 4673 | /** |
| mbed_official | 133:d4dda5c437f0 | 4674 | * @brief Configure the TI1 as Input. |
| mbed_official | 133:d4dda5c437f0 | 4675 | * @param TIMx to select the TIM peripheral. |
| mbed_official | 133:d4dda5c437f0 | 4676 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 133:d4dda5c437f0 | 4677 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4678 | * @arg TIM_ICPolarity_Rising |
| mbed_official | 133:d4dda5c437f0 | 4679 | * @arg TIM_ICPolarity_Falling |
| mbed_official | 133:d4dda5c437f0 | 4680 | * @arg TIM_ICPolarity_BothEdge |
| mbed_official | 133:d4dda5c437f0 | 4681 | * @param TIM_ICSelection: specifies the input to be used. |
| mbed_official | 133:d4dda5c437f0 | 4682 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4683 | * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. |
| mbed_official | 133:d4dda5c437f0 | 4684 | * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. |
| mbed_official | 133:d4dda5c437f0 | 4685 | * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. |
| mbed_official | 133:d4dda5c437f0 | 4686 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 133:d4dda5c437f0 | 4687 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 133:d4dda5c437f0 | 4688 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4689 | */ |
| mbed_official | 133:d4dda5c437f0 | 4690 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 4691 | uint32_t TIM_ICFilter) |
| mbed_official | 133:d4dda5c437f0 | 4692 | { |
| mbed_official | 133:d4dda5c437f0 | 4693 | uint32_t tmpccmr1 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4694 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4695 | |
| mbed_official | 133:d4dda5c437f0 | 4696 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4697 | TIMx->CCER &= ~TIM_CCER_CC1E; |
| mbed_official | 133:d4dda5c437f0 | 4698 | tmpccmr1 = TIMx->CCMR1; |
| mbed_official | 133:d4dda5c437f0 | 4699 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4700 | |
| mbed_official | 133:d4dda5c437f0 | 4701 | /* Select the Input */ |
| mbed_official | 133:d4dda5c437f0 | 4702 | if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 4703 | { |
| mbed_official | 133:d4dda5c437f0 | 4704 | tmpccmr1 &= ~TIM_CCMR1_CC1S; |
| mbed_official | 133:d4dda5c437f0 | 4705 | tmpccmr1 |= TIM_ICSelection; |
| mbed_official | 133:d4dda5c437f0 | 4706 | } |
| mbed_official | 133:d4dda5c437f0 | 4707 | else |
| mbed_official | 133:d4dda5c437f0 | 4708 | { |
| mbed_official | 133:d4dda5c437f0 | 4709 | tmpccmr1 &= ~TIM_CCMR1_CC1S; |
| mbed_official | 133:d4dda5c437f0 | 4710 | tmpccmr1 |= TIM_CCMR1_CC1S_0; |
| mbed_official | 133:d4dda5c437f0 | 4711 | } |
| mbed_official | 133:d4dda5c437f0 | 4712 | |
| mbed_official | 133:d4dda5c437f0 | 4713 | /* Set the filter */ |
| mbed_official | 133:d4dda5c437f0 | 4714 | tmpccmr1 &= ~TIM_CCMR1_IC1F; |
| mbed_official | 133:d4dda5c437f0 | 4715 | tmpccmr1 |= (TIM_ICFilter << 4); |
| mbed_official | 133:d4dda5c437f0 | 4716 | |
| mbed_official | 133:d4dda5c437f0 | 4717 | /* Select the Polarity and set the CC1E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4718 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); |
| mbed_official | 133:d4dda5c437f0 | 4719 | tmpccer |= TIM_ICPolarity; |
| mbed_official | 133:d4dda5c437f0 | 4720 | |
| mbed_official | 133:d4dda5c437f0 | 4721 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 133:d4dda5c437f0 | 4722 | TIMx->CCMR1 = tmpccmr1; |
| mbed_official | 133:d4dda5c437f0 | 4723 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4724 | } |
| mbed_official | 133:d4dda5c437f0 | 4725 | |
| mbed_official | 133:d4dda5c437f0 | 4726 | /** |
| mbed_official | 133:d4dda5c437f0 | 4727 | * @brief Configure the Polarity and Filter for TI1. |
| mbed_official | 133:d4dda5c437f0 | 4728 | * @param TIMx to select the TIM peripheral. |
| mbed_official | 133:d4dda5c437f0 | 4729 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 133:d4dda5c437f0 | 4730 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4731 | * @arg TIM_ICPolarity_Rising |
| mbed_official | 133:d4dda5c437f0 | 4732 | * @arg TIM_ICPolarity_Falling |
| mbed_official | 133:d4dda5c437f0 | 4733 | * @arg TIM_ICPolarity_BothEdge |
| mbed_official | 133:d4dda5c437f0 | 4734 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 133:d4dda5c437f0 | 4735 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 133:d4dda5c437f0 | 4736 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4737 | */ |
| mbed_official | 133:d4dda5c437f0 | 4738 | static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) |
| mbed_official | 133:d4dda5c437f0 | 4739 | { |
| mbed_official | 133:d4dda5c437f0 | 4740 | uint32_t tmpccmr1 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4741 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4742 | |
| mbed_official | 133:d4dda5c437f0 | 4743 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4744 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4745 | TIMx->CCER &= ~TIM_CCER_CC1E; |
| mbed_official | 133:d4dda5c437f0 | 4746 | tmpccmr1 = TIMx->CCMR1; |
| mbed_official | 133:d4dda5c437f0 | 4747 | |
| mbed_official | 133:d4dda5c437f0 | 4748 | /* Set the filter */ |
| mbed_official | 133:d4dda5c437f0 | 4749 | tmpccmr1 &= ~TIM_CCMR1_IC1F; |
| mbed_official | 133:d4dda5c437f0 | 4750 | tmpccmr1 |= (TIM_ICFilter << 4); |
| mbed_official | 133:d4dda5c437f0 | 4751 | |
| mbed_official | 133:d4dda5c437f0 | 4752 | /* Select the Polarity and set the CC1E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4753 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); |
| mbed_official | 133:d4dda5c437f0 | 4754 | tmpccer |= TIM_ICPolarity; |
| mbed_official | 133:d4dda5c437f0 | 4755 | |
| mbed_official | 133:d4dda5c437f0 | 4756 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 133:d4dda5c437f0 | 4757 | TIMx->CCMR1 = tmpccmr1; |
| mbed_official | 133:d4dda5c437f0 | 4758 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4759 | } |
| mbed_official | 133:d4dda5c437f0 | 4760 | |
| mbed_official | 133:d4dda5c437f0 | 4761 | /** |
| mbed_official | 133:d4dda5c437f0 | 4762 | * @brief Configure the TI2 as Input. |
| mbed_official | 133:d4dda5c437f0 | 4763 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4764 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 133:d4dda5c437f0 | 4765 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4766 | * @arg TIM_ICPolarity_Rising |
| mbed_official | 133:d4dda5c437f0 | 4767 | * @arg TIM_ICPolarity_Falling |
| mbed_official | 133:d4dda5c437f0 | 4768 | * @arg TIM_ICPolarity_BothEdge |
| mbed_official | 133:d4dda5c437f0 | 4769 | * @param TIM_ICSelection: specifies the input to be used. |
| mbed_official | 133:d4dda5c437f0 | 4770 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4771 | * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. |
| mbed_official | 133:d4dda5c437f0 | 4772 | * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. |
| mbed_official | 133:d4dda5c437f0 | 4773 | * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. |
| mbed_official | 133:d4dda5c437f0 | 4774 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 133:d4dda5c437f0 | 4775 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 133:d4dda5c437f0 | 4776 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4777 | */ |
| mbed_official | 133:d4dda5c437f0 | 4778 | static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 4779 | uint32_t TIM_ICFilter) |
| mbed_official | 133:d4dda5c437f0 | 4780 | { |
| mbed_official | 133:d4dda5c437f0 | 4781 | uint32_t tmpccmr1 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4782 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4783 | |
| mbed_official | 133:d4dda5c437f0 | 4784 | /* Disable the Channel 2: Reset the CC2E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4785 | TIMx->CCER &= ~TIM_CCER_CC2E; |
| mbed_official | 133:d4dda5c437f0 | 4786 | tmpccmr1 = TIMx->CCMR1; |
| mbed_official | 133:d4dda5c437f0 | 4787 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4788 | |
| mbed_official | 133:d4dda5c437f0 | 4789 | /* Select the Input */ |
| mbed_official | 133:d4dda5c437f0 | 4790 | tmpccmr1 &= ~TIM_CCMR1_CC2S; |
| mbed_official | 133:d4dda5c437f0 | 4791 | tmpccmr1 |= (TIM_ICSelection << 8); |
| mbed_official | 133:d4dda5c437f0 | 4792 | |
| mbed_official | 133:d4dda5c437f0 | 4793 | /* Set the filter */ |
| mbed_official | 133:d4dda5c437f0 | 4794 | tmpccmr1 &= ~TIM_CCMR1_IC2F; |
| mbed_official | 133:d4dda5c437f0 | 4795 | tmpccmr1 |= (TIM_ICFilter << 12); |
| mbed_official | 133:d4dda5c437f0 | 4796 | |
| mbed_official | 133:d4dda5c437f0 | 4797 | /* Select the Polarity and set the CC2E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4798 | tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); |
| mbed_official | 133:d4dda5c437f0 | 4799 | tmpccer |= (TIM_ICPolarity << 4); |
| mbed_official | 133:d4dda5c437f0 | 4800 | |
| mbed_official | 133:d4dda5c437f0 | 4801 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 133:d4dda5c437f0 | 4802 | TIMx->CCMR1 = tmpccmr1 ; |
| mbed_official | 133:d4dda5c437f0 | 4803 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4804 | } |
| mbed_official | 133:d4dda5c437f0 | 4805 | |
| mbed_official | 133:d4dda5c437f0 | 4806 | /** |
| mbed_official | 133:d4dda5c437f0 | 4807 | * @brief Configure the Polarity and Filter for TI2. |
| mbed_official | 133:d4dda5c437f0 | 4808 | * @param TIMx to select the TIM peripheral. |
| mbed_official | 133:d4dda5c437f0 | 4809 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 133:d4dda5c437f0 | 4810 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4811 | * @arg TIM_ICPolarity_Rising |
| mbed_official | 133:d4dda5c437f0 | 4812 | * @arg TIM_ICPolarity_Falling |
| mbed_official | 133:d4dda5c437f0 | 4813 | * @arg TIM_ICPolarity_BothEdge |
| mbed_official | 133:d4dda5c437f0 | 4814 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 133:d4dda5c437f0 | 4815 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 133:d4dda5c437f0 | 4816 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4817 | */ |
| mbed_official | 133:d4dda5c437f0 | 4818 | static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) |
| mbed_official | 133:d4dda5c437f0 | 4819 | { |
| mbed_official | 133:d4dda5c437f0 | 4820 | uint32_t tmpccmr1 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4821 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4822 | |
| mbed_official | 133:d4dda5c437f0 | 4823 | /* Disable the Channel 2: Reset the CC2E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4824 | TIMx->CCER &= ~TIM_CCER_CC2E; |
| mbed_official | 133:d4dda5c437f0 | 4825 | tmpccmr1 = TIMx->CCMR1; |
| mbed_official | 133:d4dda5c437f0 | 4826 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4827 | |
| mbed_official | 133:d4dda5c437f0 | 4828 | /* Set the filter */ |
| mbed_official | 133:d4dda5c437f0 | 4829 | tmpccmr1 &= ~TIM_CCMR1_IC2F; |
| mbed_official | 133:d4dda5c437f0 | 4830 | tmpccmr1 |= (TIM_ICFilter << 12); |
| mbed_official | 133:d4dda5c437f0 | 4831 | |
| mbed_official | 133:d4dda5c437f0 | 4832 | /* Select the Polarity and set the CC2E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4833 | tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); |
| mbed_official | 133:d4dda5c437f0 | 4834 | tmpccer |= (TIM_ICPolarity << 4); |
| mbed_official | 133:d4dda5c437f0 | 4835 | |
| mbed_official | 133:d4dda5c437f0 | 4836 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 133:d4dda5c437f0 | 4837 | TIMx->CCMR1 = tmpccmr1 ; |
| mbed_official | 133:d4dda5c437f0 | 4838 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4839 | } |
| mbed_official | 133:d4dda5c437f0 | 4840 | |
| mbed_official | 133:d4dda5c437f0 | 4841 | /** |
| mbed_official | 133:d4dda5c437f0 | 4842 | * @brief Configure the TI3 as Input. |
| mbed_official | 133:d4dda5c437f0 | 4843 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4844 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 133:d4dda5c437f0 | 4845 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4846 | * @arg TIM_ICPolarity_Rising |
| mbed_official | 133:d4dda5c437f0 | 4847 | * @arg TIM_ICPolarity_Falling |
| mbed_official | 133:d4dda5c437f0 | 4848 | * @arg TIM_ICPolarity_BothEdge |
| mbed_official | 133:d4dda5c437f0 | 4849 | * @param TIM_ICSelection: specifies the input to be used. |
| mbed_official | 133:d4dda5c437f0 | 4850 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4851 | * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. |
| mbed_official | 133:d4dda5c437f0 | 4852 | * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. |
| mbed_official | 133:d4dda5c437f0 | 4853 | * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. |
| mbed_official | 133:d4dda5c437f0 | 4854 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 133:d4dda5c437f0 | 4855 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 133:d4dda5c437f0 | 4856 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4857 | */ |
| mbed_official | 133:d4dda5c437f0 | 4858 | static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 4859 | uint32_t TIM_ICFilter) |
| mbed_official | 133:d4dda5c437f0 | 4860 | { |
| mbed_official | 133:d4dda5c437f0 | 4861 | uint32_t tmpccmr2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4862 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4863 | |
| mbed_official | 133:d4dda5c437f0 | 4864 | /* Disable the Channel 3: Reset the CC3E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4865 | TIMx->CCER &= ~TIM_CCER_CC3E; |
| mbed_official | 133:d4dda5c437f0 | 4866 | tmpccmr2 = TIMx->CCMR2; |
| mbed_official | 133:d4dda5c437f0 | 4867 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4868 | |
| mbed_official | 133:d4dda5c437f0 | 4869 | /* Select the Input */ |
| mbed_official | 133:d4dda5c437f0 | 4870 | tmpccmr2 &= ~TIM_CCMR2_CC3S; |
| mbed_official | 133:d4dda5c437f0 | 4871 | tmpccmr2 |= TIM_ICSelection; |
| mbed_official | 133:d4dda5c437f0 | 4872 | |
| mbed_official | 133:d4dda5c437f0 | 4873 | /* Set the filter */ |
| mbed_official | 133:d4dda5c437f0 | 4874 | tmpccmr2 &= ~TIM_CCMR2_IC3F; |
| mbed_official | 133:d4dda5c437f0 | 4875 | tmpccmr2 |= (TIM_ICFilter << 4); |
| mbed_official | 133:d4dda5c437f0 | 4876 | |
| mbed_official | 133:d4dda5c437f0 | 4877 | /* Select the Polarity and set the CC3E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4878 | tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); |
| mbed_official | 133:d4dda5c437f0 | 4879 | tmpccer |= (TIM_ICPolarity << 8); |
| mbed_official | 133:d4dda5c437f0 | 4880 | |
| mbed_official | 133:d4dda5c437f0 | 4881 | /* Write to TIMx CCMR2 and CCER registers */ |
| mbed_official | 133:d4dda5c437f0 | 4882 | TIMx->CCMR2 = tmpccmr2; |
| mbed_official | 133:d4dda5c437f0 | 4883 | TIMx->CCER = tmpccer; |
| mbed_official | 133:d4dda5c437f0 | 4884 | } |
| mbed_official | 133:d4dda5c437f0 | 4885 | |
| mbed_official | 133:d4dda5c437f0 | 4886 | /** |
| mbed_official | 133:d4dda5c437f0 | 4887 | * @brief Configure the TI4 as Input. |
| mbed_official | 133:d4dda5c437f0 | 4888 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4889 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 133:d4dda5c437f0 | 4890 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4891 | * @arg TIM_ICPolarity_Rising |
| mbed_official | 133:d4dda5c437f0 | 4892 | * @arg TIM_ICPolarity_Falling |
| mbed_official | 133:d4dda5c437f0 | 4893 | * @arg TIM_ICPolarity_BothEdge |
| mbed_official | 133:d4dda5c437f0 | 4894 | * @param TIM_ICSelection: specifies the input to be used. |
| mbed_official | 133:d4dda5c437f0 | 4895 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4896 | * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. |
| mbed_official | 133:d4dda5c437f0 | 4897 | * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. |
| mbed_official | 133:d4dda5c437f0 | 4898 | * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. |
| mbed_official | 133:d4dda5c437f0 | 4899 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 133:d4dda5c437f0 | 4900 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 133:d4dda5c437f0 | 4901 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4902 | */ |
| mbed_official | 133:d4dda5c437f0 | 4903 | static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 133:d4dda5c437f0 | 4904 | uint32_t TIM_ICFilter) |
| mbed_official | 133:d4dda5c437f0 | 4905 | { |
| mbed_official | 133:d4dda5c437f0 | 4906 | uint32_t tmpccmr2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 4907 | uint32_t tmpccer = 0; |
| mbed_official | 133:d4dda5c437f0 | 4908 | |
| mbed_official | 133:d4dda5c437f0 | 4909 | /* Disable the Channel 4: Reset the CC4E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4910 | TIMx->CCER &= ~TIM_CCER_CC4E; |
| mbed_official | 133:d4dda5c437f0 | 4911 | tmpccmr2 = TIMx->CCMR2; |
| mbed_official | 133:d4dda5c437f0 | 4912 | tmpccer = TIMx->CCER; |
| mbed_official | 133:d4dda5c437f0 | 4913 | |
| mbed_official | 133:d4dda5c437f0 | 4914 | /* Select the Input */ |
| mbed_official | 133:d4dda5c437f0 | 4915 | tmpccmr2 &= ~TIM_CCMR2_CC4S; |
| mbed_official | 133:d4dda5c437f0 | 4916 | tmpccmr2 |= (TIM_ICSelection << 8); |
| mbed_official | 133:d4dda5c437f0 | 4917 | |
| mbed_official | 133:d4dda5c437f0 | 4918 | /* Set the filter */ |
| mbed_official | 133:d4dda5c437f0 | 4919 | tmpccmr2 &= ~TIM_CCMR2_IC4F; |
| mbed_official | 133:d4dda5c437f0 | 4920 | tmpccmr2 |= (TIM_ICFilter << 12); |
| mbed_official | 133:d4dda5c437f0 | 4921 | |
| mbed_official | 133:d4dda5c437f0 | 4922 | /* Select the Polarity and set the CC4E Bit */ |
| mbed_official | 133:d4dda5c437f0 | 4923 | tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); |
| mbed_official | 133:d4dda5c437f0 | 4924 | tmpccer |= (TIM_ICPolarity << 12); |
| mbed_official | 133:d4dda5c437f0 | 4925 | |
| mbed_official | 133:d4dda5c437f0 | 4926 | /* Write to TIMx CCMR2 and CCER registers */ |
| mbed_official | 133:d4dda5c437f0 | 4927 | TIMx->CCMR2 = tmpccmr2; |
| mbed_official | 133:d4dda5c437f0 | 4928 | TIMx->CCER = tmpccer ; |
| mbed_official | 133:d4dda5c437f0 | 4929 | } |
| mbed_official | 133:d4dda5c437f0 | 4930 | |
| mbed_official | 133:d4dda5c437f0 | 4931 | /** |
| mbed_official | 133:d4dda5c437f0 | 4932 | * @brief Selects the Input Trigger source |
| mbed_official | 133:d4dda5c437f0 | 4933 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4934 | * @param InputTriggerSource: The Input Trigger source. |
| mbed_official | 133:d4dda5c437f0 | 4935 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4936 | * @arg TIM_TS_ITR0: Internal Trigger 0 |
| mbed_official | 133:d4dda5c437f0 | 4937 | * @arg TIM_TS_ITR1: Internal Trigger 1 |
| mbed_official | 133:d4dda5c437f0 | 4938 | * @arg TIM_TS_ITR2: Internal Trigger 2 |
| mbed_official | 133:d4dda5c437f0 | 4939 | * @arg TIM_TS_ITR3: Internal Trigger 3 |
| mbed_official | 133:d4dda5c437f0 | 4940 | * @arg TIM_TS_TI1F_ED: TI1 Edge Detector |
| mbed_official | 133:d4dda5c437f0 | 4941 | * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 |
| mbed_official | 133:d4dda5c437f0 | 4942 | * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 |
| mbed_official | 133:d4dda5c437f0 | 4943 | * @arg TIM_TS_ETRF: External Trigger input |
| mbed_official | 133:d4dda5c437f0 | 4944 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4945 | */ |
| mbed_official | 133:d4dda5c437f0 | 4946 | static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) |
| mbed_official | 133:d4dda5c437f0 | 4947 | { |
| mbed_official | 133:d4dda5c437f0 | 4948 | uint32_t tmpsmcr = 0; |
| mbed_official | 133:d4dda5c437f0 | 4949 | |
| mbed_official | 133:d4dda5c437f0 | 4950 | /* Get the TIMx SMCR register value */ |
| mbed_official | 133:d4dda5c437f0 | 4951 | tmpsmcr = TIMx->SMCR; |
| mbed_official | 133:d4dda5c437f0 | 4952 | /* Reset the TS Bits */ |
| mbed_official | 133:d4dda5c437f0 | 4953 | tmpsmcr &= ~TIM_SMCR_TS; |
| mbed_official | 133:d4dda5c437f0 | 4954 | /* Set the Input Trigger source and the slave mode*/ |
| mbed_official | 133:d4dda5c437f0 | 4955 | tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1; |
| mbed_official | 133:d4dda5c437f0 | 4956 | /* Write to TIMx SMCR */ |
| mbed_official | 133:d4dda5c437f0 | 4957 | TIMx->SMCR = tmpsmcr; |
| mbed_official | 133:d4dda5c437f0 | 4958 | } |
| mbed_official | 133:d4dda5c437f0 | 4959 | /** |
| mbed_official | 133:d4dda5c437f0 | 4960 | * @brief Configures the TIMx External Trigger (ETR). |
| mbed_official | 133:d4dda5c437f0 | 4961 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4962 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. |
| mbed_official | 133:d4dda5c437f0 | 4963 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4964 | * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF. |
| mbed_official | 133:d4dda5c437f0 | 4965 | * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. |
| mbed_official | 133:d4dda5c437f0 | 4966 | * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. |
| mbed_official | 133:d4dda5c437f0 | 4967 | * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. |
| mbed_official | 133:d4dda5c437f0 | 4968 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity. |
| mbed_official | 133:d4dda5c437f0 | 4969 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4970 | * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. |
| mbed_official | 133:d4dda5c437f0 | 4971 | * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. |
| mbed_official | 133:d4dda5c437f0 | 4972 | * @param ExtTRGFilter: External Trigger Filter. |
| mbed_official | 133:d4dda5c437f0 | 4973 | * This parameter must be a value between 0x00 and 0x0F |
| mbed_official | 133:d4dda5c437f0 | 4974 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 4975 | */ |
| mbed_official | 133:d4dda5c437f0 | 4976 | static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, |
| mbed_official | 133:d4dda5c437f0 | 4977 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) |
| mbed_official | 133:d4dda5c437f0 | 4978 | { |
| mbed_official | 133:d4dda5c437f0 | 4979 | uint32_t tmpsmcr = 0; |
| mbed_official | 133:d4dda5c437f0 | 4980 | |
| mbed_official | 133:d4dda5c437f0 | 4981 | tmpsmcr = TIMx->SMCR; |
| mbed_official | 133:d4dda5c437f0 | 4982 | |
| mbed_official | 133:d4dda5c437f0 | 4983 | /* Reset the ETR Bits */ |
| mbed_official | 133:d4dda5c437f0 | 4984 | tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); |
| mbed_official | 133:d4dda5c437f0 | 4985 | |
| mbed_official | 133:d4dda5c437f0 | 4986 | /* Set the Prescaler, the Filter value and the Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 4987 | tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); |
| mbed_official | 133:d4dda5c437f0 | 4988 | |
| mbed_official | 133:d4dda5c437f0 | 4989 | /* Write to TIMx SMCR */ |
| mbed_official | 133:d4dda5c437f0 | 4990 | TIMx->SMCR = tmpsmcr; |
| mbed_official | 133:d4dda5c437f0 | 4991 | } |
| mbed_official | 133:d4dda5c437f0 | 4992 | |
| mbed_official | 133:d4dda5c437f0 | 4993 | /** |
| mbed_official | 133:d4dda5c437f0 | 4994 | * @brief Enables or disables the TIM Capture Compare Channel x. |
| mbed_official | 133:d4dda5c437f0 | 4995 | * @param TIMx to select the TIM peripheral |
| mbed_official | 133:d4dda5c437f0 | 4996 | * @param Channel: specifies the TIM Channel |
| mbed_official | 133:d4dda5c437f0 | 4997 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 4998 | * @arg TIM_Channel_1: TIM Channel 1 |
| mbed_official | 133:d4dda5c437f0 | 4999 | * @arg TIM_Channel_2: TIM Channel 2 |
| mbed_official | 133:d4dda5c437f0 | 5000 | * @arg TIM_Channel_3: TIM Channel 3 |
| mbed_official | 133:d4dda5c437f0 | 5001 | * @arg TIM_Channel_4: TIM Channel 4 |
| mbed_official | 133:d4dda5c437f0 | 5002 | * @param ChannelState: specifies the TIM Channel CCxE bit new state. |
| mbed_official | 133:d4dda5c437f0 | 5003 | * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. |
| mbed_official | 133:d4dda5c437f0 | 5004 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 5005 | */ |
| mbed_official | 133:d4dda5c437f0 | 5006 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) |
| mbed_official | 133:d4dda5c437f0 | 5007 | { |
| mbed_official | 133:d4dda5c437f0 | 5008 | uint32_t tmp = 0; |
| mbed_official | 133:d4dda5c437f0 | 5009 | |
| mbed_official | 133:d4dda5c437f0 | 5010 | /* Check the parameters */ |
| mbed_official | 133:d4dda5c437f0 | 5011 | assert_param(IS_TIM_CC1_INSTANCE(TIMx)); |
| mbed_official | 133:d4dda5c437f0 | 5012 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 133:d4dda5c437f0 | 5013 | |
| mbed_official | 133:d4dda5c437f0 | 5014 | tmp = TIM_CCER_CC1E << Channel; |
| mbed_official | 133:d4dda5c437f0 | 5015 | |
| mbed_official | 133:d4dda5c437f0 | 5016 | /* Reset the CCxE Bit */ |
| mbed_official | 133:d4dda5c437f0 | 5017 | TIMx->CCER &= ~tmp; |
| mbed_official | 133:d4dda5c437f0 | 5018 | |
| mbed_official | 133:d4dda5c437f0 | 5019 | /* Set or reset the CCxE Bit */ |
| mbed_official | 133:d4dda5c437f0 | 5020 | TIMx->CCER |= (uint32_t)(ChannelState << Channel); |
| mbed_official | 133:d4dda5c437f0 | 5021 | } |
| mbed_official | 133:d4dda5c437f0 | 5022 | |
| mbed_official | 133:d4dda5c437f0 | 5023 | |
| mbed_official | 133:d4dda5c437f0 | 5024 | /** |
| mbed_official | 133:d4dda5c437f0 | 5025 | * @} |
| mbed_official | 133:d4dda5c437f0 | 5026 | */ |
| mbed_official | 133:d4dda5c437f0 | 5027 | |
| mbed_official | 133:d4dda5c437f0 | 5028 | #endif /* HAL_TIM_MODULE_ENABLED */ |
| mbed_official | 133:d4dda5c437f0 | 5029 | /** |
| mbed_official | 133:d4dda5c437f0 | 5030 | * @} |
| mbed_official | 133:d4dda5c437f0 | 5031 | */ |
| mbed_official | 133:d4dda5c437f0 | 5032 | |
| mbed_official | 133:d4dda5c437f0 | 5033 | /** |
| mbed_official | 133:d4dda5c437f0 | 5034 | * @} |
| mbed_official | 133:d4dda5c437f0 | 5035 | */ |
| mbed_official | 133:d4dda5c437f0 | 5036 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |