test / mbed_in_china

来自中国的硬件平台

Dependents:   mbed_in_china_blink_led

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s.c@133:d4dda5c437f0, 2014-03-24 (annotated)

Committer:
mbed_official
Date:
Mon Mar 24 17:45:07 2014 +0000
Revision:
133:d4dda5c437f0
Synchronized with git revision 47b961246bed973fe4cb8932781ffc8025b78a61



Full URL: https://github.com/mbedmicro/mbed/commit/47b961246bed973fe4cb8932781ffc8025b78a61/



[STM32F4-Discovery (STM32F407VG)] initial port

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_i2s.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 133:d4dda5c437f0 5 * @version V1.0.0
mbed_official 133:d4dda5c437f0 6 * @date 18-February-2014
mbed_official 133:d4dda5c437f0 7 * @brief I2S HAL module driver.
mbed_official 133:d4dda5c437f0 8 * This file provides firmware functions to manage the following
mbed_official 133:d4dda5c437f0 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
mbed_official 133:d4dda5c437f0 10 * + Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 11 * + IO operation functions
mbed_official 133:d4dda5c437f0 12 * + Peripheral State and Errors functions
mbed_official 133:d4dda5c437f0 13 @verbatim
mbed_official 133:d4dda5c437f0 14 ===============================================================================
mbed_official 133:d4dda5c437f0 15 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 16 ===============================================================================
mbed_official 133:d4dda5c437f0 17 [..]
mbed_official 133:d4dda5c437f0 18 The I2S HAL driver can be used as follow:
mbed_official 133:d4dda5c437f0 19
mbed_official 133:d4dda5c437f0 20 (#) Declare a I2S_HandleTypeDef handle structure.
mbed_official 133:d4dda5c437f0 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
mbed_official 133:d4dda5c437f0 22 (##) Enable the SPIx interface clock.
mbed_official 133:d4dda5c437f0 23 (##) I2S pins configuration:
mbed_official 133:d4dda5c437f0 24 (+++) Enable the clock for the I2S GPIOs.
mbed_official 133:d4dda5c437f0 25 (+++) Configure these I2S pins as alternate function pull-up.
mbed_official 133:d4dda5c437f0 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
mbed_official 133:d4dda5c437f0 27 and HAL_I2S_Receive_IT() APIs).
mbed_official 133:d4dda5c437f0 28 (+++) Configure the I2Sx interrupt priority.
mbed_official 133:d4dda5c437f0 29 (+++) Enable the NVIC I2S IRQ handle.
mbed_official 133:d4dda5c437f0 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
mbed_official 133:d4dda5c437f0 31 and HAL_I2S_Receive_DMA() APIs:
mbed_official 133:d4dda5c437f0 32 (+++) Declare a DMA handle structure for the Tx/Rx stream.
mbed_official 133:d4dda5c437f0 33 (+++) Enable the DMAx interface clock.
mbed_official 133:d4dda5c437f0 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
mbed_official 133:d4dda5c437f0 35 (+++) Configure the DMA Tx/Rx Stream.
mbed_official 133:d4dda5c437f0 36 (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
mbed_official 133:d4dda5c437f0 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
mbed_official 133:d4dda5c437f0 38 DMA Tx/Rx Stream.
mbed_official 133:d4dda5c437f0 39
mbed_official 133:d4dda5c437f0 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
mbed_official 133:d4dda5c437f0 41 using HAL_I2S_Init() function.
mbed_official 133:d4dda5c437f0 42
mbed_official 133:d4dda5c437f0 43 -@- The specific I2S interrupts (Transmission complete interrupt,
mbed_official 133:d4dda5c437f0 44 RXNE interrupt and Error Interrupts) will be managed using the macros
mbed_official 133:d4dda5c437f0 45 __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
mbed_official 133:d4dda5c437f0 46 -@- Make sure that either:
mbed_official 133:d4dda5c437f0 47 (+@) I2S PLL is configured or
mbed_official 133:d4dda5c437f0 48 (+@) External clock source is configured after setting correctly
mbed_official 133:d4dda5c437f0 49 the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
mbed_official 133:d4dda5c437f0 50
mbed_official 133:d4dda5c437f0 51 (#) Three mode of operations are available within this driver :
mbed_official 133:d4dda5c437f0 52
mbed_official 133:d4dda5c437f0 53 *** Polling mode IO operation ***
mbed_official 133:d4dda5c437f0 54 =================================
mbed_official 133:d4dda5c437f0 55 [..]
mbed_official 133:d4dda5c437f0 56 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
mbed_official 133:d4dda5c437f0 57 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
mbed_official 133:d4dda5c437f0 58
mbed_official 133:d4dda5c437f0 59 *** Interrupt mode IO operation ***
mbed_official 133:d4dda5c437f0 60 ===================================
mbed_official 133:d4dda5c437f0 61 [..]
mbed_official 133:d4dda5c437f0 62 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
mbed_official 133:d4dda5c437f0 63 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
mbed_official 133:d4dda5c437f0 64 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
mbed_official 133:d4dda5c437f0 65 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
mbed_official 133:d4dda5c437f0 66 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
mbed_official 133:d4dda5c437f0 67 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
mbed_official 133:d4dda5c437f0 68 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
mbed_official 133:d4dda5c437f0 69 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
mbed_official 133:d4dda5c437f0 70 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
mbed_official 133:d4dda5c437f0 71 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
mbed_official 133:d4dda5c437f0 72 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
mbed_official 133:d4dda5c437f0 73 add his own code by customization of function pointer HAL_I2S_ErrorCallback
mbed_official 133:d4dda5c437f0 74
mbed_official 133:d4dda5c437f0 75 *** DMA mode IO operation ***
mbed_official 133:d4dda5c437f0 76 ==============================
mbed_official 133:d4dda5c437f0 77 [..]
mbed_official 133:d4dda5c437f0 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
mbed_official 133:d4dda5c437f0 79 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
mbed_official 133:d4dda5c437f0 80 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
mbed_official 133:d4dda5c437f0 81 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
mbed_official 133:d4dda5c437f0 82 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
mbed_official 133:d4dda5c437f0 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
mbed_official 133:d4dda5c437f0 84 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
mbed_official 133:d4dda5c437f0 85 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
mbed_official 133:d4dda5c437f0 86 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
mbed_official 133:d4dda5c437f0 87 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
mbed_official 133:d4dda5c437f0 88 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
mbed_official 133:d4dda5c437f0 89 add his own code by customization of function pointer HAL_I2S_ErrorCallback
mbed_official 133:d4dda5c437f0 90 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
mbed_official 133:d4dda5c437f0 91 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
mbed_official 133:d4dda5c437f0 92 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
mbed_official 133:d4dda5c437f0 93
mbed_official 133:d4dda5c437f0 94 *** I2S HAL driver macros list ***
mbed_official 133:d4dda5c437f0 95 =============================================
mbed_official 133:d4dda5c437f0 96 [..]
mbed_official 133:d4dda5c437f0 97 Below the list of most used macros in USART HAL driver.
mbed_official 133:d4dda5c437f0 98
mbed_official 133:d4dda5c437f0 99 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
mbed_official 133:d4dda5c437f0 100 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
mbed_official 133:d4dda5c437f0 101 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
mbed_official 133:d4dda5c437f0 102 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
mbed_official 133:d4dda5c437f0 103 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
mbed_official 133:d4dda5c437f0 104
mbed_official 133:d4dda5c437f0 105 [..]
mbed_official 133:d4dda5c437f0 106 (@) You can refer to the I2S HAL driver header file for more useful macros
mbed_official 133:d4dda5c437f0 107
mbed_official 133:d4dda5c437f0 108 @endverbatim
mbed_official 133:d4dda5c437f0 109 ******************************************************************************
mbed_official 133:d4dda5c437f0 110 * @attention
mbed_official 133:d4dda5c437f0 111 *
mbed_official 133:d4dda5c437f0 112 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 113 *
mbed_official 133:d4dda5c437f0 114 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 115 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 116 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 117 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 118 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 119 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 120 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 121 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 122 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 123 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 124 *
mbed_official 133:d4dda5c437f0 125 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 126 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 127 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 128 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 129 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 130 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 131 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 132 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 133 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 134 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 135 *
mbed_official 133:d4dda5c437f0 136 ******************************************************************************
mbed_official 133:d4dda5c437f0 137 */
mbed_official 133:d4dda5c437f0 138
mbed_official 133:d4dda5c437f0 139 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 140 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 141
mbed_official 133:d4dda5c437f0 142 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 143 * @{
mbed_official 133:d4dda5c437f0 144 */
mbed_official 133:d4dda5c437f0 145
mbed_official 133:d4dda5c437f0 146 /** @defgroup I2S
mbed_official 133:d4dda5c437f0 147 * @brief I2S HAL module driver
mbed_official 133:d4dda5c437f0 148 * @{
mbed_official 133:d4dda5c437f0 149 */
mbed_official 133:d4dda5c437f0 150
mbed_official 133:d4dda5c437f0 151 #ifdef HAL_I2S_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 152
mbed_official 133:d4dda5c437f0 153 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 154 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 155 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 156 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 157 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 158 static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
mbed_official 133:d4dda5c437f0 159 static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
mbed_official 133:d4dda5c437f0 160 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 161
mbed_official 133:d4dda5c437f0 162 /** @defgroup I2S_Private_Functions
mbed_official 133:d4dda5c437f0 163 * @{
mbed_official 133:d4dda5c437f0 164 */
mbed_official 133:d4dda5c437f0 165
mbed_official 133:d4dda5c437f0 166 /** @defgroup I2S_Group1 Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 167 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 168 *
mbed_official 133:d4dda5c437f0 169 @verbatim
mbed_official 133:d4dda5c437f0 170 ===============================================================================
mbed_official 133:d4dda5c437f0 171 ##### Initialization and de-initialization functions #####
mbed_official 133:d4dda5c437f0 172 ===============================================================================
mbed_official 133:d4dda5c437f0 173 [..] This subsection provides a set of functions allowing to initialize and
mbed_official 133:d4dda5c437f0 174 de-initialiaze the I2Sx peripheral in simplex mode:
mbed_official 133:d4dda5c437f0 175
mbed_official 133:d4dda5c437f0 176 (+) User must Implement HAL_I2S_MspInit() function in which he configures
mbed_official 133:d4dda5c437f0 177 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official 133:d4dda5c437f0 178
mbed_official 133:d4dda5c437f0 179 (+) Call the function HAL_I2S_Init() to configure the selected device with
mbed_official 133:d4dda5c437f0 180 the selected configuration:
mbed_official 133:d4dda5c437f0 181 (++) Mode
mbed_official 133:d4dda5c437f0 182 (++) Standard
mbed_official 133:d4dda5c437f0 183 (++) Data Format
mbed_official 133:d4dda5c437f0 184 (++) MCLK Output
mbed_official 133:d4dda5c437f0 185 (++) Audio frequency
mbed_official 133:d4dda5c437f0 186 (++) Polarity
mbed_official 133:d4dda5c437f0 187 (++) Full duplex mode
mbed_official 133:d4dda5c437f0 188
mbed_official 133:d4dda5c437f0 189 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
mbed_official 133:d4dda5c437f0 190 of the selected I2Sx periperal.
mbed_official 133:d4dda5c437f0 191 @endverbatim
mbed_official 133:d4dda5c437f0 192 * @{
mbed_official 133:d4dda5c437f0 193 */
mbed_official 133:d4dda5c437f0 194
mbed_official 133:d4dda5c437f0 195 /**
mbed_official 133:d4dda5c437f0 196 * @brief Initializes the I2S according to the specified parameters
mbed_official 133:d4dda5c437f0 197 * in the I2S_InitTypeDef and create the associated handle.
mbed_official 133:d4dda5c437f0 198 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 199 * @retval HAL status
mbed_official 133:d4dda5c437f0 200 */
mbed_official 133:d4dda5c437f0 201 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 202 {
mbed_official 133:d4dda5c437f0 203 uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
mbed_official 133:d4dda5c437f0 204 uint32_t tmp = 0, i2sclk = 0;
mbed_official 133:d4dda5c437f0 205
mbed_official 133:d4dda5c437f0 206 /* Check the I2S handle allocation */
mbed_official 133:d4dda5c437f0 207 if(hi2s == NULL)
mbed_official 133:d4dda5c437f0 208 {
mbed_official 133:d4dda5c437f0 209 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 210 }
mbed_official 133:d4dda5c437f0 211
mbed_official 133:d4dda5c437f0 212 /* Check the I2S parameters */
mbed_official 133:d4dda5c437f0 213 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
mbed_official 133:d4dda5c437f0 214 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
mbed_official 133:d4dda5c437f0 215 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
mbed_official 133:d4dda5c437f0 216 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
mbed_official 133:d4dda5c437f0 217 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
mbed_official 133:d4dda5c437f0 218 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
mbed_official 133:d4dda5c437f0 219 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
mbed_official 133:d4dda5c437f0 220 assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
mbed_official 133:d4dda5c437f0 221
mbed_official 133:d4dda5c437f0 222 if(hi2s->State == HAL_I2S_STATE_RESET)
mbed_official 133:d4dda5c437f0 223 {
mbed_official 133:d4dda5c437f0 224 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
mbed_official 133:d4dda5c437f0 225 HAL_I2S_MspInit(hi2s);
mbed_official 133:d4dda5c437f0 226 }
mbed_official 133:d4dda5c437f0 227
mbed_official 133:d4dda5c437f0 228 hi2s->State = HAL_I2S_STATE_BUSY;
mbed_official 133:d4dda5c437f0 229
mbed_official 133:d4dda5c437f0 230 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
mbed_official 133:d4dda5c437f0 231 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
mbed_official 133:d4dda5c437f0 232 hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
mbed_official 133:d4dda5c437f0 233 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
mbed_official 133:d4dda5c437f0 234 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
mbed_official 133:d4dda5c437f0 235 hi2s->Instance->I2SPR = 0x0002;
mbed_official 133:d4dda5c437f0 236
mbed_official 133:d4dda5c437f0 237 /* Get the I2SCFGR register value */
mbed_official 133:d4dda5c437f0 238 tmpreg = hi2s->Instance->I2SCFGR;
mbed_official 133:d4dda5c437f0 239
mbed_official 133:d4dda5c437f0 240 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
mbed_official 133:d4dda5c437f0 241 /* If the requested audio frequency is not the default, compute the prescaler */
mbed_official 133:d4dda5c437f0 242 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
mbed_official 133:d4dda5c437f0 243 {
mbed_official 133:d4dda5c437f0 244 /* Check the frame length (For the Prescaler computing) *******************/
mbed_official 133:d4dda5c437f0 245 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
mbed_official 133:d4dda5c437f0 246 {
mbed_official 133:d4dda5c437f0 247 /* Packet length is 32 bits */
mbed_official 133:d4dda5c437f0 248 packetlength = 2;
mbed_official 133:d4dda5c437f0 249 }
mbed_official 133:d4dda5c437f0 250
mbed_official 133:d4dda5c437f0 251 /* Get I2S source Clock frequency ****************************************/
mbed_official 133:d4dda5c437f0 252 /* If an external I2S clock has to be used, the specific define should be set
mbed_official 133:d4dda5c437f0 253 in the project configuration or in the stm32f4xx_conf.h file */
mbed_official 133:d4dda5c437f0 254 if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
mbed_official 133:d4dda5c437f0 255 {
mbed_official 133:d4dda5c437f0 256 /* Set external clock as I2S clock source */
mbed_official 133:d4dda5c437f0 257 if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
mbed_official 133:d4dda5c437f0 258 {
mbed_official 133:d4dda5c437f0 259 RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
mbed_official 133:d4dda5c437f0 260 }
mbed_official 133:d4dda5c437f0 261
mbed_official 133:d4dda5c437f0 262 /* Set the I2S clock to the external clock value */
mbed_official 133:d4dda5c437f0 263 i2sclk = EXTERNAL_CLOCK_VALUE;
mbed_official 133:d4dda5c437f0 264 }
mbed_official 133:d4dda5c437f0 265 else
mbed_official 133:d4dda5c437f0 266 {
mbed_official 133:d4dda5c437f0 267 /* Check if PLLI2S is enabled or Not */
mbed_official 133:d4dda5c437f0 268 if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
mbed_official 133:d4dda5c437f0 269 {
mbed_official 133:d4dda5c437f0 270 hi2s->State= HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 271
mbed_official 133:d4dda5c437f0 272 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 273 }
mbed_official 133:d4dda5c437f0 274
mbed_official 133:d4dda5c437f0 275 /* Set PLLI2S as I2S clock source */
mbed_official 133:d4dda5c437f0 276 if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
mbed_official 133:d4dda5c437f0 277 {
mbed_official 133:d4dda5c437f0 278 RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
mbed_official 133:d4dda5c437f0 279 }
mbed_official 133:d4dda5c437f0 280
mbed_official 133:d4dda5c437f0 281 /* Get the PLLM value */
mbed_official 133:d4dda5c437f0 282 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
mbed_official 133:d4dda5c437f0 283 {
mbed_official 133:d4dda5c437f0 284 /* Get the I2S source clock value */
mbed_official 133:d4dda5c437f0 285 i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
mbed_official 133:d4dda5c437f0 286 }
mbed_official 133:d4dda5c437f0 287 else
mbed_official 133:d4dda5c437f0 288 {
mbed_official 133:d4dda5c437f0 289 /* Get the I2S source clock value */
mbed_official 133:d4dda5c437f0 290 i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
mbed_official 133:d4dda5c437f0 291 }
mbed_official 133:d4dda5c437f0 292 i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6));
mbed_official 133:d4dda5c437f0 293 i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28));
mbed_official 133:d4dda5c437f0 294 }
mbed_official 133:d4dda5c437f0 295
mbed_official 133:d4dda5c437f0 296 /* Compute the Real divider depending on the MCLK output state, with a floating point */
mbed_official 133:d4dda5c437f0 297 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
mbed_official 133:d4dda5c437f0 298 {
mbed_official 133:d4dda5c437f0 299 /* MCLK output is enabled */
mbed_official 133:d4dda5c437f0 300 tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
mbed_official 133:d4dda5c437f0 301 }
mbed_official 133:d4dda5c437f0 302 else
mbed_official 133:d4dda5c437f0 303 {
mbed_official 133:d4dda5c437f0 304 /* MCLK output is disabled */
mbed_official 133:d4dda5c437f0 305 tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
mbed_official 133:d4dda5c437f0 306 }
mbed_official 133:d4dda5c437f0 307
mbed_official 133:d4dda5c437f0 308 /* Remove the flatting point */
mbed_official 133:d4dda5c437f0 309 tmp = tmp / 10;
mbed_official 133:d4dda5c437f0 310
mbed_official 133:d4dda5c437f0 311 /* Check the parity of the divider */
mbed_official 133:d4dda5c437f0 312 i2sodd = (uint32_t)(tmp & (uint32_t)1);
mbed_official 133:d4dda5c437f0 313
mbed_official 133:d4dda5c437f0 314 /* Compute the i2sdiv prescaler */
mbed_official 133:d4dda5c437f0 315 i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
mbed_official 133:d4dda5c437f0 316
mbed_official 133:d4dda5c437f0 317 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
mbed_official 133:d4dda5c437f0 318 i2sodd = (uint32_t) (i2sodd << 8);
mbed_official 133:d4dda5c437f0 319 }
mbed_official 133:d4dda5c437f0 320
mbed_official 133:d4dda5c437f0 321 /* Test if the divider is 1 or 0 or greater than 0xFF */
mbed_official 133:d4dda5c437f0 322 if((i2sdiv < 2) || (i2sdiv > 0xFF))
mbed_official 133:d4dda5c437f0 323 {
mbed_official 133:d4dda5c437f0 324 /* Set the default values */
mbed_official 133:d4dda5c437f0 325 i2sdiv = 2;
mbed_official 133:d4dda5c437f0 326 i2sodd = 0;
mbed_official 133:d4dda5c437f0 327 }
mbed_official 133:d4dda5c437f0 328
mbed_official 133:d4dda5c437f0 329 /* Write to SPIx I2SPR register the computed value */
mbed_official 133:d4dda5c437f0 330 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
mbed_official 133:d4dda5c437f0 331
mbed_official 133:d4dda5c437f0 332 /* Configure the I2S with the I2S_InitStruct values */
mbed_official 133:d4dda5c437f0 333 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
mbed_official 133:d4dda5c437f0 334
mbed_official 133:d4dda5c437f0 335 /* Write to SPIx I2SCFGR */
mbed_official 133:d4dda5c437f0 336 hi2s->Instance->I2SCFGR = tmpreg;
mbed_official 133:d4dda5c437f0 337
mbed_official 133:d4dda5c437f0 338 /* Configure the I2S extended if the full duplex mode is enabled */
mbed_official 133:d4dda5c437f0 339 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
mbed_official 133:d4dda5c437f0 340 {
mbed_official 133:d4dda5c437f0 341 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
mbed_official 133:d4dda5c437f0 342 I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
mbed_official 133:d4dda5c437f0 343 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
mbed_official 133:d4dda5c437f0 344 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
mbed_official 133:d4dda5c437f0 345 I2SxEXT(hi2s->Instance)->I2SPR = 2;
mbed_official 133:d4dda5c437f0 346
mbed_official 133:d4dda5c437f0 347 /* Get the I2SCFGR register value */
mbed_official 133:d4dda5c437f0 348 tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
mbed_official 133:d4dda5c437f0 349
mbed_official 133:d4dda5c437f0 350 /* Get the mode to be configured for the extended I2S */
mbed_official 133:d4dda5c437f0 351 if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
mbed_official 133:d4dda5c437f0 352 {
mbed_official 133:d4dda5c437f0 353 tmp = I2S_MODE_SLAVE_RX;
mbed_official 133:d4dda5c437f0 354 }
mbed_official 133:d4dda5c437f0 355 else
mbed_official 133:d4dda5c437f0 356 {
mbed_official 133:d4dda5c437f0 357 if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
mbed_official 133:d4dda5c437f0 358 {
mbed_official 133:d4dda5c437f0 359 tmp = I2S_MODE_SLAVE_TX;
mbed_official 133:d4dda5c437f0 360 }
mbed_official 133:d4dda5c437f0 361 }
mbed_official 133:d4dda5c437f0 362
mbed_official 133:d4dda5c437f0 363 /* Configure the I2S Slave with the I2S Master parameter values */
mbed_official 133:d4dda5c437f0 364 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
mbed_official 133:d4dda5c437f0 365
mbed_official 133:d4dda5c437f0 366 /* Write to SPIx I2SCFGR */
mbed_official 133:d4dda5c437f0 367 I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
mbed_official 133:d4dda5c437f0 368 }
mbed_official 133:d4dda5c437f0 369
mbed_official 133:d4dda5c437f0 370 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 133:d4dda5c437f0 371 hi2s->State= HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 372
mbed_official 133:d4dda5c437f0 373 return HAL_OK;
mbed_official 133:d4dda5c437f0 374 }
mbed_official 133:d4dda5c437f0 375
mbed_official 133:d4dda5c437f0 376 /**
mbed_official 133:d4dda5c437f0 377 * @brief DeInitializes the I2S peripheral
mbed_official 133:d4dda5c437f0 378 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 379 * @retval HAL status
mbed_official 133:d4dda5c437f0 380 */
mbed_official 133:d4dda5c437f0 381 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 382 {
mbed_official 133:d4dda5c437f0 383 /* Check the I2S handle allocation */
mbed_official 133:d4dda5c437f0 384 if(hi2s == NULL)
mbed_official 133:d4dda5c437f0 385 {
mbed_official 133:d4dda5c437f0 386 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 387 }
mbed_official 133:d4dda5c437f0 388
mbed_official 133:d4dda5c437f0 389 hi2s->State = HAL_I2S_STATE_BUSY;
mbed_official 133:d4dda5c437f0 390
mbed_official 133:d4dda5c437f0 391 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official 133:d4dda5c437f0 392 HAL_I2S_MspDeInit(hi2s);
mbed_official 133:d4dda5c437f0 393
mbed_official 133:d4dda5c437f0 394 hi2s->State = HAL_I2S_STATE_RESET;
mbed_official 133:d4dda5c437f0 395
mbed_official 133:d4dda5c437f0 396 /* Release Lock */
mbed_official 133:d4dda5c437f0 397 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 398
mbed_official 133:d4dda5c437f0 399 return HAL_OK;
mbed_official 133:d4dda5c437f0 400 }
mbed_official 133:d4dda5c437f0 401
mbed_official 133:d4dda5c437f0 402 /**
mbed_official 133:d4dda5c437f0 403 * @brief I2S MSP Init
mbed_official 133:d4dda5c437f0 404 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 405 * @retval None
mbed_official 133:d4dda5c437f0 406 */
mbed_official 133:d4dda5c437f0 407 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 408 {
mbed_official 133:d4dda5c437f0 409 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 410 the HAL_I2S_MspInit could be implenetd in the user file
mbed_official 133:d4dda5c437f0 411 */
mbed_official 133:d4dda5c437f0 412 }
mbed_official 133:d4dda5c437f0 413
mbed_official 133:d4dda5c437f0 414 /**
mbed_official 133:d4dda5c437f0 415 * @brief I2S MSP DeInit
mbed_official 133:d4dda5c437f0 416 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 417 * @retval None
mbed_official 133:d4dda5c437f0 418 */
mbed_official 133:d4dda5c437f0 419 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 420 {
mbed_official 133:d4dda5c437f0 421 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 422 the HAL_I2S_MspDeInit could be implenetd in the user file
mbed_official 133:d4dda5c437f0 423 */
mbed_official 133:d4dda5c437f0 424 }
mbed_official 133:d4dda5c437f0 425
mbed_official 133:d4dda5c437f0 426 /**
mbed_official 133:d4dda5c437f0 427 * @}
mbed_official 133:d4dda5c437f0 428 */
mbed_official 133:d4dda5c437f0 429
mbed_official 133:d4dda5c437f0 430 /** @defgroup I2S_Group2 IO operation functions
mbed_official 133:d4dda5c437f0 431 * @brief Data transfers functions
mbed_official 133:d4dda5c437f0 432 *
mbed_official 133:d4dda5c437f0 433 @verbatim
mbed_official 133:d4dda5c437f0 434 ===============================================================================
mbed_official 133:d4dda5c437f0 435 ##### IO operation functions #####
mbed_official 133:d4dda5c437f0 436 ===============================================================================
mbed_official 133:d4dda5c437f0 437 [..]
mbed_official 133:d4dda5c437f0 438 This subsection provides a set of functions allowing to manage the I2S data
mbed_official 133:d4dda5c437f0 439 transfers.
mbed_official 133:d4dda5c437f0 440
mbed_official 133:d4dda5c437f0 441 (#) There is two mode of transfer:
mbed_official 133:d4dda5c437f0 442 (++) Blocking mode : The communication is performed in the polling mode.
mbed_official 133:d4dda5c437f0 443 The status of all data processing is returned by the same function
mbed_official 133:d4dda5c437f0 444 after finishing transfer.
mbed_official 133:d4dda5c437f0 445 (++) No-Blocking mode : The communication is performed using Interrupts
mbed_official 133:d4dda5c437f0 446 or DMA. These functions return the status of the transfer startup.
mbed_official 133:d4dda5c437f0 447 The end of the data processing will be indicated through the
mbed_official 133:d4dda5c437f0 448 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 133:d4dda5c437f0 449 using DMA mode.
mbed_official 133:d4dda5c437f0 450
mbed_official 133:d4dda5c437f0 451 (#) Blocking mode functions are :
mbed_official 133:d4dda5c437f0 452 (++) HAL_I2S_Transmit()
mbed_official 133:d4dda5c437f0 453 (++) HAL_I2S_Receive()
mbed_official 133:d4dda5c437f0 454
mbed_official 133:d4dda5c437f0 455 (#) No-Blocking mode functions with Interrupt are :
mbed_official 133:d4dda5c437f0 456 (++) HAL_I2S_Transmit_IT()
mbed_official 133:d4dda5c437f0 457 (++) HAL_I2S_Receive_IT()
mbed_official 133:d4dda5c437f0 458
mbed_official 133:d4dda5c437f0 459 (#) No-Blocking mode functions with DMA are :
mbed_official 133:d4dda5c437f0 460 (++) HAL_I2S_Transmit_DMA()
mbed_official 133:d4dda5c437f0 461 (++) HAL_I2S_Receive_DMA()
mbed_official 133:d4dda5c437f0 462
mbed_official 133:d4dda5c437f0 463 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official 133:d4dda5c437f0 464 (++) HAL_I2S_TxCpltCallback()
mbed_official 133:d4dda5c437f0 465 (++) HAL_I2S_RxCpltCallback()
mbed_official 133:d4dda5c437f0 466 (++) HAL_I2S_ErrorCallback()
mbed_official 133:d4dda5c437f0 467
mbed_official 133:d4dda5c437f0 468 @endverbatim
mbed_official 133:d4dda5c437f0 469 * @{
mbed_official 133:d4dda5c437f0 470 */
mbed_official 133:d4dda5c437f0 471
mbed_official 133:d4dda5c437f0 472 /**
mbed_official 133:d4dda5c437f0 473 * @brief Transmit an amount of data in blocking mode
mbed_official 133:d4dda5c437f0 474 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 475 * @param pData: a 16-bit pointer to data buffer.
mbed_official 133:d4dda5c437f0 476 * @param Size: number of data sample to be sent:
mbed_official 133:d4dda5c437f0 477 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 133:d4dda5c437f0 478 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 133:d4dda5c437f0 479 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 133:d4dda5c437f0 480 * the Size parameter means the number of 16-bit data length.
mbed_official 133:d4dda5c437f0 481 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 482 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 133:d4dda5c437f0 483 * between Master and Slave(example: audio streaming).
mbed_official 133:d4dda5c437f0 484 * @retval HAL status
mbed_official 133:d4dda5c437f0 485 */
mbed_official 133:d4dda5c437f0 486 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 487 {
mbed_official 133:d4dda5c437f0 488 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 133:d4dda5c437f0 489 if((pData == NULL ) || (Size == 0))
mbed_official 133:d4dda5c437f0 490 {
mbed_official 133:d4dda5c437f0 491 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 492 }
mbed_official 133:d4dda5c437f0 493
mbed_official 133:d4dda5c437f0 494 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 133:d4dda5c437f0 495 {
mbed_official 133:d4dda5c437f0 496 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 497 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 498 if((tmp1 == I2S_DATAFORMAT_24B)|| \
mbed_official 133:d4dda5c437f0 499 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 133:d4dda5c437f0 500 {
mbed_official 133:d4dda5c437f0 501 hi2s->TxXferSize = Size*2;
mbed_official 133:d4dda5c437f0 502 hi2s->TxXferCount = Size*2;
mbed_official 133:d4dda5c437f0 503 }
mbed_official 133:d4dda5c437f0 504 else
mbed_official 133:d4dda5c437f0 505 {
mbed_official 133:d4dda5c437f0 506 hi2s->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 507 hi2s->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 508 }
mbed_official 133:d4dda5c437f0 509
mbed_official 133:d4dda5c437f0 510 /* Process Locked */
mbed_official 133:d4dda5c437f0 511 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 512
mbed_official 133:d4dda5c437f0 513 hi2s->State = HAL_I2S_STATE_BUSY_TX;
mbed_official 133:d4dda5c437f0 514
mbed_official 133:d4dda5c437f0 515 /* Check if the I2S is already enabled */
mbed_official 133:d4dda5c437f0 516 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 133:d4dda5c437f0 517 {
mbed_official 133:d4dda5c437f0 518 /* Enable I2S peripheral */
mbed_official 133:d4dda5c437f0 519 __HAL_I2S_ENABLE(hi2s);
mbed_official 133:d4dda5c437f0 520 }
mbed_official 133:d4dda5c437f0 521
mbed_official 133:d4dda5c437f0 522 while(hi2s->TxXferCount > 0)
mbed_official 133:d4dda5c437f0 523 {
mbed_official 133:d4dda5c437f0 524 hi2s->Instance->DR = (*pData++);
mbed_official 133:d4dda5c437f0 525 hi2s->TxXferCount--;
mbed_official 133:d4dda5c437f0 526 /* Wait until TXE flag is set */
mbed_official 133:d4dda5c437f0 527 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 528 {
mbed_official 133:d4dda5c437f0 529 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 530 }
mbed_official 133:d4dda5c437f0 531 }
mbed_official 133:d4dda5c437f0 532 /* Wait until Busy flag is reset */
mbed_official 133:d4dda5c437f0 533 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 534 {
mbed_official 133:d4dda5c437f0 535 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 536 }
mbed_official 133:d4dda5c437f0 537
mbed_official 133:d4dda5c437f0 538 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 539
mbed_official 133:d4dda5c437f0 540 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 541 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 542
mbed_official 133:d4dda5c437f0 543 return HAL_OK;
mbed_official 133:d4dda5c437f0 544 }
mbed_official 133:d4dda5c437f0 545 else
mbed_official 133:d4dda5c437f0 546 {
mbed_official 133:d4dda5c437f0 547 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 548 }
mbed_official 133:d4dda5c437f0 549 }
mbed_official 133:d4dda5c437f0 550
mbed_official 133:d4dda5c437f0 551 /**
mbed_official 133:d4dda5c437f0 552 * @brief Receive an amount of data in blocking mode
mbed_official 133:d4dda5c437f0 553 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 554 * @param pData: a 16-bit pointer to data buffer.
mbed_official 133:d4dda5c437f0 555 * @param Size: number of data sample to be sent:
mbed_official 133:d4dda5c437f0 556 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 133:d4dda5c437f0 557 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 133:d4dda5c437f0 558 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 133:d4dda5c437f0 559 * the Size parameter means the number of 16-bit data length.
mbed_official 133:d4dda5c437f0 560 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 561 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 133:d4dda5c437f0 562 * between Master and Slave(example: audio streaming).
mbed_official 133:d4dda5c437f0 563 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
mbed_official 133:d4dda5c437f0 564 * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
mbed_official 133:d4dda5c437f0 565 * @retval HAL status
mbed_official 133:d4dda5c437f0 566 */
mbed_official 133:d4dda5c437f0 567 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 568 {
mbed_official 133:d4dda5c437f0 569 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 133:d4dda5c437f0 570 if((pData == NULL ) || (Size == 0))
mbed_official 133:d4dda5c437f0 571 {
mbed_official 133:d4dda5c437f0 572 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 573 }
mbed_official 133:d4dda5c437f0 574
mbed_official 133:d4dda5c437f0 575 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 133:d4dda5c437f0 576 {
mbed_official 133:d4dda5c437f0 577 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 578 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 579 if((tmp1 == I2S_DATAFORMAT_24B)|| \
mbed_official 133:d4dda5c437f0 580 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 133:d4dda5c437f0 581 {
mbed_official 133:d4dda5c437f0 582 hi2s->RxXferSize = Size*2;
mbed_official 133:d4dda5c437f0 583 hi2s->RxXferCount = Size*2;
mbed_official 133:d4dda5c437f0 584 }
mbed_official 133:d4dda5c437f0 585 else
mbed_official 133:d4dda5c437f0 586 {
mbed_official 133:d4dda5c437f0 587 hi2s->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 588 hi2s->RxXferCount = Size;
mbed_official 133:d4dda5c437f0 589 }
mbed_official 133:d4dda5c437f0 590 /* Process Locked */
mbed_official 133:d4dda5c437f0 591 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 592
mbed_official 133:d4dda5c437f0 593 hi2s->State = HAL_I2S_STATE_BUSY_RX;
mbed_official 133:d4dda5c437f0 594
mbed_official 133:d4dda5c437f0 595 /* Check if the I2S is already enabled */
mbed_official 133:d4dda5c437f0 596 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 133:d4dda5c437f0 597 {
mbed_official 133:d4dda5c437f0 598 /* Enable I2S peripheral */
mbed_official 133:d4dda5c437f0 599 __HAL_I2S_ENABLE(hi2s);
mbed_official 133:d4dda5c437f0 600 }
mbed_official 133:d4dda5c437f0 601
mbed_official 133:d4dda5c437f0 602 /* Check if Master Receiver mode is selected */
mbed_official 133:d4dda5c437f0 603 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 133:d4dda5c437f0 604 {
mbed_official 133:d4dda5c437f0 605 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
mbed_official 133:d4dda5c437f0 606 access to the SPI_SR register. */
mbed_official 133:d4dda5c437f0 607 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 133:d4dda5c437f0 608 }
mbed_official 133:d4dda5c437f0 609
mbed_official 133:d4dda5c437f0 610 /* Receive data */
mbed_official 133:d4dda5c437f0 611 while(hi2s->RxXferCount > 0)
mbed_official 133:d4dda5c437f0 612 {
mbed_official 133:d4dda5c437f0 613 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 614 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 615 {
mbed_official 133:d4dda5c437f0 616 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 617 }
mbed_official 133:d4dda5c437f0 618
mbed_official 133:d4dda5c437f0 619 (*pData++) = hi2s->Instance->DR;
mbed_official 133:d4dda5c437f0 620 hi2s->RxXferCount--;
mbed_official 133:d4dda5c437f0 621 }
mbed_official 133:d4dda5c437f0 622
mbed_official 133:d4dda5c437f0 623 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 624
mbed_official 133:d4dda5c437f0 625 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 626 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 627
mbed_official 133:d4dda5c437f0 628 return HAL_OK;
mbed_official 133:d4dda5c437f0 629 }
mbed_official 133:d4dda5c437f0 630 else
mbed_official 133:d4dda5c437f0 631 {
mbed_official 133:d4dda5c437f0 632 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 633 }
mbed_official 133:d4dda5c437f0 634 }
mbed_official 133:d4dda5c437f0 635
mbed_official 133:d4dda5c437f0 636 /**
mbed_official 133:d4dda5c437f0 637 * @brief Transmit an amount of data in non-blocking mode with Interrupt
mbed_official 133:d4dda5c437f0 638 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 639 * @param pData: a 16-bit pointer to data buffer.
mbed_official 133:d4dda5c437f0 640 * @param Size: number of data sample to be sent:
mbed_official 133:d4dda5c437f0 641 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 133:d4dda5c437f0 642 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 133:d4dda5c437f0 643 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 133:d4dda5c437f0 644 * the Size parameter means the number of 16-bit data length.
mbed_official 133:d4dda5c437f0 645 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 133:d4dda5c437f0 646 * between Master and Slave(example: audio streaming).
mbed_official 133:d4dda5c437f0 647 * @retval HAL status
mbed_official 133:d4dda5c437f0 648 */
mbed_official 133:d4dda5c437f0 649 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
mbed_official 133:d4dda5c437f0 650 {
mbed_official 133:d4dda5c437f0 651 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 133:d4dda5c437f0 652 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 133:d4dda5c437f0 653 {
mbed_official 133:d4dda5c437f0 654 if((pData == NULL) || (Size == 0))
mbed_official 133:d4dda5c437f0 655 {
mbed_official 133:d4dda5c437f0 656 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 657 }
mbed_official 133:d4dda5c437f0 658
mbed_official 133:d4dda5c437f0 659 hi2s->pTxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 660 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 661 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 662 if((tmp1 == I2S_DATAFORMAT_24B)|| \
mbed_official 133:d4dda5c437f0 663 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 133:d4dda5c437f0 664 {
mbed_official 133:d4dda5c437f0 665 hi2s->TxXferSize = Size*2;
mbed_official 133:d4dda5c437f0 666 hi2s->TxXferCount = Size*2;
mbed_official 133:d4dda5c437f0 667 }
mbed_official 133:d4dda5c437f0 668 else
mbed_official 133:d4dda5c437f0 669 {
mbed_official 133:d4dda5c437f0 670 hi2s->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 671 hi2s->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 672 }
mbed_official 133:d4dda5c437f0 673
mbed_official 133:d4dda5c437f0 674 /* Process Locked */
mbed_official 133:d4dda5c437f0 675 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 676
mbed_official 133:d4dda5c437f0 677 hi2s->State = HAL_I2S_STATE_BUSY_TX;
mbed_official 133:d4dda5c437f0 678 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 133:d4dda5c437f0 679
mbed_official 133:d4dda5c437f0 680 /* Enable TXE and ERR interrupt */
mbed_official 133:d4dda5c437f0 681 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
mbed_official 133:d4dda5c437f0 682
mbed_official 133:d4dda5c437f0 683 /* Check if the I2S is already enabled */
mbed_official 133:d4dda5c437f0 684 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 133:d4dda5c437f0 685 {
mbed_official 133:d4dda5c437f0 686 /* Enable I2S peripheral */
mbed_official 133:d4dda5c437f0 687 __HAL_I2S_ENABLE(hi2s);
mbed_official 133:d4dda5c437f0 688 }
mbed_official 133:d4dda5c437f0 689
mbed_official 133:d4dda5c437f0 690 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 691 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 692
mbed_official 133:d4dda5c437f0 693 return HAL_OK;
mbed_official 133:d4dda5c437f0 694 }
mbed_official 133:d4dda5c437f0 695 else
mbed_official 133:d4dda5c437f0 696 {
mbed_official 133:d4dda5c437f0 697 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 698 }
mbed_official 133:d4dda5c437f0 699 }
mbed_official 133:d4dda5c437f0 700
mbed_official 133:d4dda5c437f0 701 /**
mbed_official 133:d4dda5c437f0 702 * @brief Receive an amount of data in non-blocking mode with Interrupt
mbed_official 133:d4dda5c437f0 703 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 704 * @param pData: a 16-bit pointer to the Receive data buffer.
mbed_official 133:d4dda5c437f0 705 * @param Size: number of data sample to be sent:
mbed_official 133:d4dda5c437f0 706 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 133:d4dda5c437f0 707 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 133:d4dda5c437f0 708 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 133:d4dda5c437f0 709 * the Size parameter means the number of 16-bit data length.
mbed_official 133:d4dda5c437f0 710 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 133:d4dda5c437f0 711 * between Master and Slave(example: audio streaming).
mbed_official 133:d4dda5c437f0 712 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
mbed_official 133:d4dda5c437f0 713 * between Master and Slave otherwise the I2S interrupt should be optimized.
mbed_official 133:d4dda5c437f0 714 * @retval HAL status
mbed_official 133:d4dda5c437f0 715 */
mbed_official 133:d4dda5c437f0 716 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
mbed_official 133:d4dda5c437f0 717 {
mbed_official 133:d4dda5c437f0 718 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 133:d4dda5c437f0 719 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 133:d4dda5c437f0 720 {
mbed_official 133:d4dda5c437f0 721 if((pData == NULL) || (Size == 0))
mbed_official 133:d4dda5c437f0 722 {
mbed_official 133:d4dda5c437f0 723 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 724 }
mbed_official 133:d4dda5c437f0 725
mbed_official 133:d4dda5c437f0 726 hi2s->pRxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 727 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 728 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 729 if((tmp1 == I2S_DATAFORMAT_24B)||\
mbed_official 133:d4dda5c437f0 730 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 133:d4dda5c437f0 731 {
mbed_official 133:d4dda5c437f0 732 hi2s->RxXferSize = Size*2;
mbed_official 133:d4dda5c437f0 733 hi2s->RxXferCount = Size*2;
mbed_official 133:d4dda5c437f0 734 }
mbed_official 133:d4dda5c437f0 735 else
mbed_official 133:d4dda5c437f0 736 {
mbed_official 133:d4dda5c437f0 737 hi2s->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 738 hi2s->RxXferCount = Size;
mbed_official 133:d4dda5c437f0 739 }
mbed_official 133:d4dda5c437f0 740 /* Process Locked */
mbed_official 133:d4dda5c437f0 741 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 742
mbed_official 133:d4dda5c437f0 743 hi2s->State = HAL_I2S_STATE_BUSY_RX;
mbed_official 133:d4dda5c437f0 744 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 133:d4dda5c437f0 745
mbed_official 133:d4dda5c437f0 746 /* Enable TXE and ERR interrupt */
mbed_official 133:d4dda5c437f0 747 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
mbed_official 133:d4dda5c437f0 748
mbed_official 133:d4dda5c437f0 749 /* Check if the I2S is already enabled */
mbed_official 133:d4dda5c437f0 750 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 133:d4dda5c437f0 751 {
mbed_official 133:d4dda5c437f0 752 /* Enable I2S peripheral */
mbed_official 133:d4dda5c437f0 753 __HAL_I2S_ENABLE(hi2s);
mbed_official 133:d4dda5c437f0 754 }
mbed_official 133:d4dda5c437f0 755
mbed_official 133:d4dda5c437f0 756 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 757 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 758
mbed_official 133:d4dda5c437f0 759 return HAL_OK;
mbed_official 133:d4dda5c437f0 760 }
mbed_official 133:d4dda5c437f0 761
mbed_official 133:d4dda5c437f0 762 else
mbed_official 133:d4dda5c437f0 763 {
mbed_official 133:d4dda5c437f0 764 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 765 }
mbed_official 133:d4dda5c437f0 766 }
mbed_official 133:d4dda5c437f0 767
mbed_official 133:d4dda5c437f0 768 /**
mbed_official 133:d4dda5c437f0 769 * @brief Transmit an amount of data in non-blocking mode with DMA
mbed_official 133:d4dda5c437f0 770 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 771 * @param pData: a 16-bit pointer to the Transmit data buffer.
mbed_official 133:d4dda5c437f0 772 * @param Size: number of data sample to be sent:
mbed_official 133:d4dda5c437f0 773 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 133:d4dda5c437f0 774 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 133:d4dda5c437f0 775 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 133:d4dda5c437f0 776 * the Size parameter means the number of 16-bit data length.
mbed_official 133:d4dda5c437f0 777 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 133:d4dda5c437f0 778 * between Master and Slave(example: audio streaming).
mbed_official 133:d4dda5c437f0 779 * @retval HAL status
mbed_official 133:d4dda5c437f0 780 */
mbed_official 133:d4dda5c437f0 781 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
mbed_official 133:d4dda5c437f0 782 {
mbed_official 133:d4dda5c437f0 783 uint32_t *tmp;
mbed_official 133:d4dda5c437f0 784 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 133:d4dda5c437f0 785
mbed_official 133:d4dda5c437f0 786 if((pData == NULL) || (Size == 0))
mbed_official 133:d4dda5c437f0 787 {
mbed_official 133:d4dda5c437f0 788 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 789 }
mbed_official 133:d4dda5c437f0 790
mbed_official 133:d4dda5c437f0 791 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 133:d4dda5c437f0 792 {
mbed_official 133:d4dda5c437f0 793 hi2s->pTxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 794 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 795 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 796 if((tmp1 == I2S_DATAFORMAT_24B)|| \
mbed_official 133:d4dda5c437f0 797 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 133:d4dda5c437f0 798 {
mbed_official 133:d4dda5c437f0 799 hi2s->TxXferSize = Size*2;
mbed_official 133:d4dda5c437f0 800 hi2s->TxXferCount = Size*2;
mbed_official 133:d4dda5c437f0 801 }
mbed_official 133:d4dda5c437f0 802 else
mbed_official 133:d4dda5c437f0 803 {
mbed_official 133:d4dda5c437f0 804 hi2s->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 805 hi2s->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 806 }
mbed_official 133:d4dda5c437f0 807
mbed_official 133:d4dda5c437f0 808 /* Process Locked */
mbed_official 133:d4dda5c437f0 809 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 810
mbed_official 133:d4dda5c437f0 811 hi2s->State = HAL_I2S_STATE_BUSY_TX;
mbed_official 133:d4dda5c437f0 812 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 133:d4dda5c437f0 813
mbed_official 133:d4dda5c437f0 814 /* Set the I2S Tx DMA Half transfert complete callback */
mbed_official 133:d4dda5c437f0 815 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
mbed_official 133:d4dda5c437f0 816
mbed_official 133:d4dda5c437f0 817 /* Set the I2S Tx DMA transfert complete callback */
mbed_official 133:d4dda5c437f0 818 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
mbed_official 133:d4dda5c437f0 819
mbed_official 133:d4dda5c437f0 820 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 821 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
mbed_official 133:d4dda5c437f0 822
mbed_official 133:d4dda5c437f0 823 /* Enable the Tx DMA Stream */
mbed_official 133:d4dda5c437f0 824 tmp = (uint32_t*)&pData;
mbed_official 133:d4dda5c437f0 825 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
mbed_official 133:d4dda5c437f0 826
mbed_official 133:d4dda5c437f0 827 /* Check if the I2S is already enabled */
mbed_official 133:d4dda5c437f0 828 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 133:d4dda5c437f0 829 {
mbed_official 133:d4dda5c437f0 830 /* Enable I2S peripheral */
mbed_official 133:d4dda5c437f0 831 __HAL_I2S_ENABLE(hi2s);
mbed_official 133:d4dda5c437f0 832 }
mbed_official 133:d4dda5c437f0 833
mbed_official 133:d4dda5c437f0 834 /* Check if the I2S Tx request is already enabled */
mbed_official 133:d4dda5c437f0 835 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
mbed_official 133:d4dda5c437f0 836 {
mbed_official 133:d4dda5c437f0 837 /* Enable Tx DMA Request */
mbed_official 133:d4dda5c437f0 838 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 133:d4dda5c437f0 839 }
mbed_official 133:d4dda5c437f0 840
mbed_official 133:d4dda5c437f0 841 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 842 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 843
mbed_official 133:d4dda5c437f0 844 return HAL_OK;
mbed_official 133:d4dda5c437f0 845 }
mbed_official 133:d4dda5c437f0 846 else
mbed_official 133:d4dda5c437f0 847 {
mbed_official 133:d4dda5c437f0 848 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 849 }
mbed_official 133:d4dda5c437f0 850 }
mbed_official 133:d4dda5c437f0 851
mbed_official 133:d4dda5c437f0 852 /**
mbed_official 133:d4dda5c437f0 853 * @brief Receive an amount of data in non-blocking mode with DMA
mbed_official 133:d4dda5c437f0 854 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 855 * @param pData: a 16-bit pointer to the Receive data buffer.
mbed_official 133:d4dda5c437f0 856 * @param Size: number of data sample to be sent:
mbed_official 133:d4dda5c437f0 857 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 133:d4dda5c437f0 858 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 133:d4dda5c437f0 859 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 133:d4dda5c437f0 860 * the Size parameter means the number of 16-bit data length.
mbed_official 133:d4dda5c437f0 861 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 133:d4dda5c437f0 862 * between Master and Slave(example: audio streaming).
mbed_official 133:d4dda5c437f0 863 * @retval HAL status
mbed_official 133:d4dda5c437f0 864 */
mbed_official 133:d4dda5c437f0 865 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
mbed_official 133:d4dda5c437f0 866 {
mbed_official 133:d4dda5c437f0 867 uint32_t *tmp;
mbed_official 133:d4dda5c437f0 868 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 133:d4dda5c437f0 869
mbed_official 133:d4dda5c437f0 870 if((pData == NULL) || (Size == 0))
mbed_official 133:d4dda5c437f0 871 {
mbed_official 133:d4dda5c437f0 872 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 873 }
mbed_official 133:d4dda5c437f0 874
mbed_official 133:d4dda5c437f0 875 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 133:d4dda5c437f0 876 {
mbed_official 133:d4dda5c437f0 877 hi2s->pRxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 878 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 879 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 133:d4dda5c437f0 880 if((tmp1 == I2S_DATAFORMAT_24B)|| \
mbed_official 133:d4dda5c437f0 881 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 133:d4dda5c437f0 882 {
mbed_official 133:d4dda5c437f0 883 hi2s->RxXferSize = Size*2;
mbed_official 133:d4dda5c437f0 884 hi2s->RxXferCount = Size*2;
mbed_official 133:d4dda5c437f0 885 }
mbed_official 133:d4dda5c437f0 886 else
mbed_official 133:d4dda5c437f0 887 {
mbed_official 133:d4dda5c437f0 888 hi2s->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 889 hi2s->RxXferCount = Size;
mbed_official 133:d4dda5c437f0 890 }
mbed_official 133:d4dda5c437f0 891 /* Process Locked */
mbed_official 133:d4dda5c437f0 892 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 893
mbed_official 133:d4dda5c437f0 894 hi2s->State = HAL_I2S_STATE_BUSY_RX;
mbed_official 133:d4dda5c437f0 895 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 133:d4dda5c437f0 896
mbed_official 133:d4dda5c437f0 897 /* Set the I2S Rx DMA Half transfert complete callback */
mbed_official 133:d4dda5c437f0 898 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
mbed_official 133:d4dda5c437f0 899
mbed_official 133:d4dda5c437f0 900 /* Set the I2S Rx DMA transfert complete callback */
mbed_official 133:d4dda5c437f0 901 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
mbed_official 133:d4dda5c437f0 902
mbed_official 133:d4dda5c437f0 903 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 904 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
mbed_official 133:d4dda5c437f0 905
mbed_official 133:d4dda5c437f0 906 /* Check if Master Receiver mode is selected */
mbed_official 133:d4dda5c437f0 907 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 133:d4dda5c437f0 908 {
mbed_official 133:d4dda5c437f0 909 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
mbed_official 133:d4dda5c437f0 910 access to the SPI_SR register. */
mbed_official 133:d4dda5c437f0 911 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 133:d4dda5c437f0 912 }
mbed_official 133:d4dda5c437f0 913
mbed_official 133:d4dda5c437f0 914 /* Enable the Rx DMA Stream */
mbed_official 133:d4dda5c437f0 915 tmp = (uint32_t*)&pData;
mbed_official 133:d4dda5c437f0 916 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
mbed_official 133:d4dda5c437f0 917
mbed_official 133:d4dda5c437f0 918 /* Check if the I2S is already enabled */
mbed_official 133:d4dda5c437f0 919 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 133:d4dda5c437f0 920 {
mbed_official 133:d4dda5c437f0 921 /* Enable I2S peripheral */
mbed_official 133:d4dda5c437f0 922 __HAL_I2S_ENABLE(hi2s);
mbed_official 133:d4dda5c437f0 923 }
mbed_official 133:d4dda5c437f0 924
mbed_official 133:d4dda5c437f0 925 /* Check if the I2S Rx request is already enabled */
mbed_official 133:d4dda5c437f0 926 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
mbed_official 133:d4dda5c437f0 927 {
mbed_official 133:d4dda5c437f0 928 /* Enable Rx DMA Request */
mbed_official 133:d4dda5c437f0 929 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 133:d4dda5c437f0 930 }
mbed_official 133:d4dda5c437f0 931
mbed_official 133:d4dda5c437f0 932 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 933 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 934
mbed_official 133:d4dda5c437f0 935 return HAL_OK;
mbed_official 133:d4dda5c437f0 936 }
mbed_official 133:d4dda5c437f0 937 else
mbed_official 133:d4dda5c437f0 938 {
mbed_official 133:d4dda5c437f0 939 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 940 }
mbed_official 133:d4dda5c437f0 941 }
mbed_official 133:d4dda5c437f0 942
mbed_official 133:d4dda5c437f0 943 /**
mbed_official 133:d4dda5c437f0 944 * @brief Pauses the audio stream playing from the Media.
mbed_official 133:d4dda5c437f0 945 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 946 * @retval None
mbed_official 133:d4dda5c437f0 947 */
mbed_official 133:d4dda5c437f0 948 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 949 {
mbed_official 133:d4dda5c437f0 950 /* Process Locked */
mbed_official 133:d4dda5c437f0 951 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 952
mbed_official 133:d4dda5c437f0 953 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
mbed_official 133:d4dda5c437f0 954 {
mbed_official 133:d4dda5c437f0 955 /* Disable the I2S DMA Tx request */
mbed_official 133:d4dda5c437f0 956 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 133:d4dda5c437f0 957 }
mbed_official 133:d4dda5c437f0 958 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
mbed_official 133:d4dda5c437f0 959 {
mbed_official 133:d4dda5c437f0 960 /* Disable the I2S DMA Rx request */
mbed_official 133:d4dda5c437f0 961 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 133:d4dda5c437f0 962 }
mbed_official 133:d4dda5c437f0 963 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
mbed_official 133:d4dda5c437f0 964 {
mbed_official 133:d4dda5c437f0 965 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
mbed_official 133:d4dda5c437f0 966 {
mbed_official 133:d4dda5c437f0 967 /* Disable the I2S DMA Tx request */
mbed_official 133:d4dda5c437f0 968 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 133:d4dda5c437f0 969 /* Disable the I2SEx Rx DMA Request */
mbed_official 133:d4dda5c437f0 970 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 133:d4dda5c437f0 971 }
mbed_official 133:d4dda5c437f0 972 else
mbed_official 133:d4dda5c437f0 973 {
mbed_official 133:d4dda5c437f0 974 /* Disable the I2S DMA Rx request */
mbed_official 133:d4dda5c437f0 975 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 133:d4dda5c437f0 976 /* Disable the I2SEx Tx DMA Request */
mbed_official 133:d4dda5c437f0 977 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 133:d4dda5c437f0 978 }
mbed_official 133:d4dda5c437f0 979 }
mbed_official 133:d4dda5c437f0 980
mbed_official 133:d4dda5c437f0 981 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 982 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 983
mbed_official 133:d4dda5c437f0 984 return HAL_OK;
mbed_official 133:d4dda5c437f0 985 }
mbed_official 133:d4dda5c437f0 986
mbed_official 133:d4dda5c437f0 987 /**
mbed_official 133:d4dda5c437f0 988 * @brief Resumes the audio stream playing from the Media.
mbed_official 133:d4dda5c437f0 989 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 990 * @retval None
mbed_official 133:d4dda5c437f0 991 */
mbed_official 133:d4dda5c437f0 992 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 993 {
mbed_official 133:d4dda5c437f0 994 /* Process Locked */
mbed_official 133:d4dda5c437f0 995 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 996
mbed_official 133:d4dda5c437f0 997 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
mbed_official 133:d4dda5c437f0 998 {
mbed_official 133:d4dda5c437f0 999 /* Enable the I2S DMA Tx request */
mbed_official 133:d4dda5c437f0 1000 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 133:d4dda5c437f0 1001 }
mbed_official 133:d4dda5c437f0 1002 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
mbed_official 133:d4dda5c437f0 1003 {
mbed_official 133:d4dda5c437f0 1004 /* Enable the I2S DMA Rx request */
mbed_official 133:d4dda5c437f0 1005 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 133:d4dda5c437f0 1006 }
mbed_official 133:d4dda5c437f0 1007 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
mbed_official 133:d4dda5c437f0 1008 {
mbed_official 133:d4dda5c437f0 1009 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
mbed_official 133:d4dda5c437f0 1010 {
mbed_official 133:d4dda5c437f0 1011 /* Enable the I2S DMA Tx request */
mbed_official 133:d4dda5c437f0 1012 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 133:d4dda5c437f0 1013 /* Disable the I2SEx Rx DMA Request */
mbed_official 133:d4dda5c437f0 1014 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 133:d4dda5c437f0 1015 }
mbed_official 133:d4dda5c437f0 1016 else
mbed_official 133:d4dda5c437f0 1017 {
mbed_official 133:d4dda5c437f0 1018 /* Enable the I2S DMA Rx request */
mbed_official 133:d4dda5c437f0 1019 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 133:d4dda5c437f0 1020 /* Enable the I2SEx Tx DMA Request */
mbed_official 133:d4dda5c437f0 1021 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 133:d4dda5c437f0 1022 }
mbed_official 133:d4dda5c437f0 1023 }
mbed_official 133:d4dda5c437f0 1024
mbed_official 133:d4dda5c437f0 1025 /* If the I2S peripheral is still not enabled, enable it */
mbed_official 133:d4dda5c437f0 1026 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
mbed_official 133:d4dda5c437f0 1027 {
mbed_official 133:d4dda5c437f0 1028 /* Enable I2S peripheral */
mbed_official 133:d4dda5c437f0 1029 __HAL_I2S_ENABLE(hi2s);
mbed_official 133:d4dda5c437f0 1030 }
mbed_official 133:d4dda5c437f0 1031
mbed_official 133:d4dda5c437f0 1032 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1033 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 1034
mbed_official 133:d4dda5c437f0 1035 return HAL_OK;
mbed_official 133:d4dda5c437f0 1036 }
mbed_official 133:d4dda5c437f0 1037
mbed_official 133:d4dda5c437f0 1038 /**
mbed_official 133:d4dda5c437f0 1039 * @brief Resumes the audio stream playing from the Media.
mbed_official 133:d4dda5c437f0 1040 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1041 * @retval None
mbed_official 133:d4dda5c437f0 1042 */
mbed_official 133:d4dda5c437f0 1043 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1044 {
mbed_official 133:d4dda5c437f0 1045 /* Process Locked */
mbed_official 133:d4dda5c437f0 1046 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 1047
mbed_official 133:d4dda5c437f0 1048 /* Disable the I2S Tx/Rx DMA requests */
mbed_official 133:d4dda5c437f0 1049 hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
mbed_official 133:d4dda5c437f0 1050 hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
mbed_official 133:d4dda5c437f0 1051
mbed_official 133:d4dda5c437f0 1052 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
mbed_official 133:d4dda5c437f0 1053 {
mbed_official 133:d4dda5c437f0 1054 /* Disable the I2S extended Tx/Rx DMA requests */
mbed_official 133:d4dda5c437f0 1055 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 133:d4dda5c437f0 1056 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 133:d4dda5c437f0 1057 }
mbed_official 133:d4dda5c437f0 1058
mbed_official 133:d4dda5c437f0 1059 /* Abort the I2S DMA Stream tx */
mbed_official 133:d4dda5c437f0 1060 if(hi2s->hdmatx != NULL)
mbed_official 133:d4dda5c437f0 1061 {
mbed_official 133:d4dda5c437f0 1062 HAL_DMA_Abort(hi2s->hdmatx);
mbed_official 133:d4dda5c437f0 1063 }
mbed_official 133:d4dda5c437f0 1064 /* Abort the I2S DMA Stream rx */
mbed_official 133:d4dda5c437f0 1065 if(hi2s->hdmarx != NULL)
mbed_official 133:d4dda5c437f0 1066 {
mbed_official 133:d4dda5c437f0 1067 HAL_DMA_Abort(hi2s->hdmarx);
mbed_official 133:d4dda5c437f0 1068 }
mbed_official 133:d4dda5c437f0 1069
mbed_official 133:d4dda5c437f0 1070 /* Disable I2S peripheral */
mbed_official 133:d4dda5c437f0 1071 __HAL_I2S_DISABLE(hi2s);
mbed_official 133:d4dda5c437f0 1072
mbed_official 133:d4dda5c437f0 1073 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
mbed_official 133:d4dda5c437f0 1074 {
mbed_official 133:d4dda5c437f0 1075 /* Disable the I2Sext peripheral */
mbed_official 133:d4dda5c437f0 1076 I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
mbed_official 133:d4dda5c437f0 1077 }
mbed_official 133:d4dda5c437f0 1078
mbed_official 133:d4dda5c437f0 1079 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1080
mbed_official 133:d4dda5c437f0 1081 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1082 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 1083
mbed_official 133:d4dda5c437f0 1084 return HAL_OK;
mbed_official 133:d4dda5c437f0 1085 }
mbed_official 133:d4dda5c437f0 1086
mbed_official 133:d4dda5c437f0 1087 /**
mbed_official 133:d4dda5c437f0 1088 * @brief This function handles I2S interrupt request.
mbed_official 133:d4dda5c437f0 1089 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1090 * @retval HAL status
mbed_official 133:d4dda5c437f0 1091 */
mbed_official 133:d4dda5c437f0 1092 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1093 {
mbed_official 133:d4dda5c437f0 1094 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 133:d4dda5c437f0 1095 if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
mbed_official 133:d4dda5c437f0 1096 {
mbed_official 133:d4dda5c437f0 1097 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
mbed_official 133:d4dda5c437f0 1098 {
mbed_official 133:d4dda5c437f0 1099 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
mbed_official 133:d4dda5c437f0 1100 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
mbed_official 133:d4dda5c437f0 1101 /* I2S in mode Receiver ------------------------------------------------*/
mbed_official 133:d4dda5c437f0 1102 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1103 {
mbed_official 133:d4dda5c437f0 1104 I2S_Receive_IT(hi2s);
mbed_official 133:d4dda5c437f0 1105 }
mbed_official 133:d4dda5c437f0 1106
mbed_official 133:d4dda5c437f0 1107 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
mbed_official 133:d4dda5c437f0 1108 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
mbed_official 133:d4dda5c437f0 1109 /* I2S Overrun error interrupt occured ---------------------------------*/
mbed_official 133:d4dda5c437f0 1110 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1111 {
mbed_official 133:d4dda5c437f0 1112 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 133:d4dda5c437f0 1113 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
mbed_official 133:d4dda5c437f0 1114 }
mbed_official 133:d4dda5c437f0 1115 }
mbed_official 133:d4dda5c437f0 1116
mbed_official 133:d4dda5c437f0 1117 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
mbed_official 133:d4dda5c437f0 1118 {
mbed_official 133:d4dda5c437f0 1119 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
mbed_official 133:d4dda5c437f0 1120 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
mbed_official 133:d4dda5c437f0 1121 /* I2S in mode Tramitter -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 1122 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1123 {
mbed_official 133:d4dda5c437f0 1124 I2S_Transmit_IT(hi2s);
mbed_official 133:d4dda5c437f0 1125 }
mbed_official 133:d4dda5c437f0 1126
mbed_official 133:d4dda5c437f0 1127 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
mbed_official 133:d4dda5c437f0 1128 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
mbed_official 133:d4dda5c437f0 1129 /* I2S Underrun error interrupt occured --------------------------------*/
mbed_official 133:d4dda5c437f0 1130 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1131 {
mbed_official 133:d4dda5c437f0 1132 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
mbed_official 133:d4dda5c437f0 1133 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
mbed_official 133:d4dda5c437f0 1134 }
mbed_official 133:d4dda5c437f0 1135 }
mbed_official 133:d4dda5c437f0 1136 }
mbed_official 133:d4dda5c437f0 1137 else
mbed_official 133:d4dda5c437f0 1138 {
mbed_official 133:d4dda5c437f0 1139 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1140 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1141 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 133:d4dda5c437f0 1142 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 133:d4dda5c437f0 1143 {
mbed_official 133:d4dda5c437f0 1144 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
mbed_official 133:d4dda5c437f0 1145 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
mbed_official 133:d4dda5c437f0 1146 /* I2Sext in mode Receiver ---------------------------------------------*/
mbed_official 133:d4dda5c437f0 1147 if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
mbed_official 133:d4dda5c437f0 1148 {
mbed_official 133:d4dda5c437f0 1149 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1150 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1151 /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
mbed_official 133:d4dda5c437f0 1152 the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
mbed_official 133:d4dda5c437f0 1153 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 133:d4dda5c437f0 1154 {
mbed_official 133:d4dda5c437f0 1155 I2SEx_TransmitReceive_IT(hi2s);
mbed_official 133:d4dda5c437f0 1156 }
mbed_official 133:d4dda5c437f0 1157 }
mbed_official 133:d4dda5c437f0 1158
mbed_official 133:d4dda5c437f0 1159 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
mbed_official 133:d4dda5c437f0 1160 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
mbed_official 133:d4dda5c437f0 1161 /* I2Sext Overrun error interrupt occured ------------------------------*/
mbed_official 133:d4dda5c437f0 1162 if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
mbed_official 133:d4dda5c437f0 1163 {
mbed_official 133:d4dda5c437f0 1164 /* Clear I2Sext OVR Flag */
mbed_official 133:d4dda5c437f0 1165 I2SxEXT(hi2s->Instance)->DR;
mbed_official 133:d4dda5c437f0 1166 I2SxEXT(hi2s->Instance)->SR;
mbed_official 133:d4dda5c437f0 1167 hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
mbed_official 133:d4dda5c437f0 1168 }
mbed_official 133:d4dda5c437f0 1169
mbed_official 133:d4dda5c437f0 1170 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
mbed_official 133:d4dda5c437f0 1171 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
mbed_official 133:d4dda5c437f0 1172 /* I2S in mode Tramitter -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 1173 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1174 {
mbed_official 133:d4dda5c437f0 1175 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1176 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1177 /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
mbed_official 133:d4dda5c437f0 1178 the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
mbed_official 133:d4dda5c437f0 1179 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 133:d4dda5c437f0 1180 {
mbed_official 133:d4dda5c437f0 1181 I2SEx_TransmitReceive_IT(hi2s);
mbed_official 133:d4dda5c437f0 1182 }
mbed_official 133:d4dda5c437f0 1183 }
mbed_official 133:d4dda5c437f0 1184
mbed_official 133:d4dda5c437f0 1185 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
mbed_official 133:d4dda5c437f0 1186 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
mbed_official 133:d4dda5c437f0 1187 /* I2S Underrun error interrupt occured --------------------------------*/
mbed_official 133:d4dda5c437f0 1188 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1189 {
mbed_official 133:d4dda5c437f0 1190 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
mbed_official 133:d4dda5c437f0 1191 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
mbed_official 133:d4dda5c437f0 1192 }
mbed_official 133:d4dda5c437f0 1193 }
mbed_official 133:d4dda5c437f0 1194 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
mbed_official 133:d4dda5c437f0 1195 else
mbed_official 133:d4dda5c437f0 1196 {
mbed_official 133:d4dda5c437f0 1197 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
mbed_official 133:d4dda5c437f0 1198 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
mbed_official 133:d4dda5c437f0 1199 /* I2S in mode Receiver ------------------------------------------------*/
mbed_official 133:d4dda5c437f0 1200 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1201 {
mbed_official 133:d4dda5c437f0 1202 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1203 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1204 /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
mbed_official 133:d4dda5c437f0 1205 the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
mbed_official 133:d4dda5c437f0 1206 if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
mbed_official 133:d4dda5c437f0 1207 {
mbed_official 133:d4dda5c437f0 1208 I2SEx_TransmitReceive_IT(hi2s);
mbed_official 133:d4dda5c437f0 1209 }
mbed_official 133:d4dda5c437f0 1210 }
mbed_official 133:d4dda5c437f0 1211
mbed_official 133:d4dda5c437f0 1212 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
mbed_official 133:d4dda5c437f0 1213 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
mbed_official 133:d4dda5c437f0 1214 /* I2S Overrun error interrupt occured ---------------------------------*/
mbed_official 133:d4dda5c437f0 1215 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1216 {
mbed_official 133:d4dda5c437f0 1217 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 133:d4dda5c437f0 1218 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
mbed_official 133:d4dda5c437f0 1219 }
mbed_official 133:d4dda5c437f0 1220
mbed_official 133:d4dda5c437f0 1221 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
mbed_official 133:d4dda5c437f0 1222 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
mbed_official 133:d4dda5c437f0 1223 /* I2Sext in mode Tramitter --------------------------------------------*/
mbed_official 133:d4dda5c437f0 1224 if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
mbed_official 133:d4dda5c437f0 1225 {
mbed_official 133:d4dda5c437f0 1226 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1227 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 133:d4dda5c437f0 1228 /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
mbed_official 133:d4dda5c437f0 1229 the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
mbed_official 133:d4dda5c437f0 1230 if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
mbed_official 133:d4dda5c437f0 1231 {
mbed_official 133:d4dda5c437f0 1232 I2SEx_TransmitReceive_IT(hi2s);
mbed_official 133:d4dda5c437f0 1233 }
mbed_official 133:d4dda5c437f0 1234 }
mbed_official 133:d4dda5c437f0 1235
mbed_official 133:d4dda5c437f0 1236 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
mbed_official 133:d4dda5c437f0 1237 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
mbed_official 133:d4dda5c437f0 1238 /* I2Sext Underrun error interrupt occured -----------------------------*/
mbed_official 133:d4dda5c437f0 1239 if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
mbed_official 133:d4dda5c437f0 1240 {
mbed_official 133:d4dda5c437f0 1241 /* Clear I2Sext UDR Flag */
mbed_official 133:d4dda5c437f0 1242 I2SxEXT(hi2s->Instance)->SR;
mbed_official 133:d4dda5c437f0 1243 hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
mbed_official 133:d4dda5c437f0 1244 }
mbed_official 133:d4dda5c437f0 1245 }
mbed_official 133:d4dda5c437f0 1246 }
mbed_official 133:d4dda5c437f0 1247
mbed_official 133:d4dda5c437f0 1248 /* Call the Error call Back in case of Errors */
mbed_official 133:d4dda5c437f0 1249 if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
mbed_official 133:d4dda5c437f0 1250 {
mbed_official 133:d4dda5c437f0 1251 /* Set the I2S state ready to be able to start again the process */
mbed_official 133:d4dda5c437f0 1252 hi2s->State= HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1253 HAL_I2S_ErrorCallback(hi2s);
mbed_official 133:d4dda5c437f0 1254 }
mbed_official 133:d4dda5c437f0 1255 }
mbed_official 133:d4dda5c437f0 1256
mbed_official 133:d4dda5c437f0 1257 /**
mbed_official 133:d4dda5c437f0 1258 * @brief Tx Transfer Half completed callbacks
mbed_official 133:d4dda5c437f0 1259 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1260 * @retval None
mbed_official 133:d4dda5c437f0 1261 */
mbed_official 133:d4dda5c437f0 1262 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1263 {
mbed_official 133:d4dda5c437f0 1264 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1265 the HAL_I2S_TxHalfCpltCallback could be implenetd in the user file
mbed_official 133:d4dda5c437f0 1266 */
mbed_official 133:d4dda5c437f0 1267 }
mbed_official 133:d4dda5c437f0 1268
mbed_official 133:d4dda5c437f0 1269 /**
mbed_official 133:d4dda5c437f0 1270 * @brief Tx Transfer completed callbacks
mbed_official 133:d4dda5c437f0 1271 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1272 * @retval None
mbed_official 133:d4dda5c437f0 1273 */
mbed_official 133:d4dda5c437f0 1274 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1275 {
mbed_official 133:d4dda5c437f0 1276 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1277 the HAL_I2S_TxCpltCallback could be implenetd in the user file
mbed_official 133:d4dda5c437f0 1278 */
mbed_official 133:d4dda5c437f0 1279 }
mbed_official 133:d4dda5c437f0 1280
mbed_official 133:d4dda5c437f0 1281 /**
mbed_official 133:d4dda5c437f0 1282 * @brief Rx Transfer half completed callbacks
mbed_official 133:d4dda5c437f0 1283 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1284 * @retval None
mbed_official 133:d4dda5c437f0 1285 */
mbed_official 133:d4dda5c437f0 1286 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1287 {
mbed_official 133:d4dda5c437f0 1288 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1289 the HAL_I2S_RxCpltCallback could be implenetd in the user file
mbed_official 133:d4dda5c437f0 1290 */
mbed_official 133:d4dda5c437f0 1291 }
mbed_official 133:d4dda5c437f0 1292
mbed_official 133:d4dda5c437f0 1293 /**
mbed_official 133:d4dda5c437f0 1294 * @brief Rx Transfer completed callbacks
mbed_official 133:d4dda5c437f0 1295 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1296 * @retval None
mbed_official 133:d4dda5c437f0 1297 */
mbed_official 133:d4dda5c437f0 1298 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1299 {
mbed_official 133:d4dda5c437f0 1300 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1301 the HAL_I2S_RxCpltCallback could be implenetd in the user file
mbed_official 133:d4dda5c437f0 1302 */
mbed_official 133:d4dda5c437f0 1303 }
mbed_official 133:d4dda5c437f0 1304
mbed_official 133:d4dda5c437f0 1305 /**
mbed_official 133:d4dda5c437f0 1306 * @brief I2S error callbacks
mbed_official 133:d4dda5c437f0 1307 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1308 * @retval None
mbed_official 133:d4dda5c437f0 1309 */
mbed_official 133:d4dda5c437f0 1310 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1311 {
mbed_official 133:d4dda5c437f0 1312 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1313 the HAL_I2S_ErrorCallback could be implenetd in the user file
mbed_official 133:d4dda5c437f0 1314 */
mbed_official 133:d4dda5c437f0 1315 }
mbed_official 133:d4dda5c437f0 1316
mbed_official 133:d4dda5c437f0 1317 /**
mbed_official 133:d4dda5c437f0 1318 * @}
mbed_official 133:d4dda5c437f0 1319 */
mbed_official 133:d4dda5c437f0 1320
mbed_official 133:d4dda5c437f0 1321 /** @defgroup I2S_Group3 Peripheral State and Errors functions
mbed_official 133:d4dda5c437f0 1322 * @brief Peripheral State functions
mbed_official 133:d4dda5c437f0 1323 *
mbed_official 133:d4dda5c437f0 1324 @verbatim
mbed_official 133:d4dda5c437f0 1325 ===============================================================================
mbed_official 133:d4dda5c437f0 1326 ##### Peripheral State and Errors functions #####
mbed_official 133:d4dda5c437f0 1327 ===============================================================================
mbed_official 133:d4dda5c437f0 1328 [..]
mbed_official 133:d4dda5c437f0 1329 This subsection permit to get in run-time the status of the peripheral
mbed_official 133:d4dda5c437f0 1330 and the data flow.
mbed_official 133:d4dda5c437f0 1331
mbed_official 133:d4dda5c437f0 1332 @endverbatim
mbed_official 133:d4dda5c437f0 1333 * @{
mbed_official 133:d4dda5c437f0 1334 */
mbed_official 133:d4dda5c437f0 1335
mbed_official 133:d4dda5c437f0 1336 /**
mbed_official 133:d4dda5c437f0 1337 * @brief Return the I2S state
mbed_official 133:d4dda5c437f0 1338 * @param hi2s : I2S handle
mbed_official 133:d4dda5c437f0 1339 * @retval HAL state
mbed_official 133:d4dda5c437f0 1340 */
mbed_official 133:d4dda5c437f0 1341 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1342 {
mbed_official 133:d4dda5c437f0 1343 return hi2s->State;
mbed_official 133:d4dda5c437f0 1344 }
mbed_official 133:d4dda5c437f0 1345
mbed_official 133:d4dda5c437f0 1346 /**
mbed_official 133:d4dda5c437f0 1347 * @brief Return the I2S error code
mbed_official 133:d4dda5c437f0 1348 * @param hi2s : I2S handle
mbed_official 133:d4dda5c437f0 1349 * @retval I2S Error Code
mbed_official 133:d4dda5c437f0 1350 */
mbed_official 133:d4dda5c437f0 1351 HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1352 {
mbed_official 133:d4dda5c437f0 1353 return hi2s->ErrorCode;
mbed_official 133:d4dda5c437f0 1354 }
mbed_official 133:d4dda5c437f0 1355
mbed_official 133:d4dda5c437f0 1356 /**
mbed_official 133:d4dda5c437f0 1357 * @}
mbed_official 133:d4dda5c437f0 1358 */
mbed_official 133:d4dda5c437f0 1359
mbed_official 133:d4dda5c437f0 1360 /**
mbed_official 133:d4dda5c437f0 1361 * @brief DMA I2S transmit process complete callback
mbed_official 133:d4dda5c437f0 1362 * @param hdma : DMA handle
mbed_official 133:d4dda5c437f0 1363 * @retval None
mbed_official 133:d4dda5c437f0 1364 */
mbed_official 133:d4dda5c437f0 1365 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1366 {
mbed_official 133:d4dda5c437f0 1367 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
mbed_official 133:d4dda5c437f0 1368
mbed_official 133:d4dda5c437f0 1369 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 133:d4dda5c437f0 1370 {
mbed_official 133:d4dda5c437f0 1371 hi2s->TxXferCount = 0;
mbed_official 133:d4dda5c437f0 1372
mbed_official 133:d4dda5c437f0 1373 /* Disable Tx DMA Request */
mbed_official 133:d4dda5c437f0 1374 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 133:d4dda5c437f0 1375
mbed_official 133:d4dda5c437f0 1376 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
mbed_official 133:d4dda5c437f0 1377 {
mbed_official 133:d4dda5c437f0 1378 /* Disable Rx DMA Request for the slave*/
mbed_official 133:d4dda5c437f0 1379 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 133:d4dda5c437f0 1380 }
mbed_official 133:d4dda5c437f0 1381
mbed_official 133:d4dda5c437f0 1382 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
mbed_official 133:d4dda5c437f0 1383 {
mbed_official 133:d4dda5c437f0 1384 if(hi2s->RxXferCount == 0)
mbed_official 133:d4dda5c437f0 1385 {
mbed_official 133:d4dda5c437f0 1386 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1387 }
mbed_official 133:d4dda5c437f0 1388 }
mbed_official 133:d4dda5c437f0 1389 else
mbed_official 133:d4dda5c437f0 1390 {
mbed_official 133:d4dda5c437f0 1391 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1392 }
mbed_official 133:d4dda5c437f0 1393 }
mbed_official 133:d4dda5c437f0 1394 HAL_I2S_TxCpltCallback(hi2s);
mbed_official 133:d4dda5c437f0 1395 }
mbed_official 133:d4dda5c437f0 1396
mbed_official 133:d4dda5c437f0 1397 /**
mbed_official 133:d4dda5c437f0 1398 * @brief DMA I2S transmit process half complete callback
mbed_official 133:d4dda5c437f0 1399 * @param hdma : DMA handle
mbed_official 133:d4dda5c437f0 1400 * @retval None
mbed_official 133:d4dda5c437f0 1401 */
mbed_official 133:d4dda5c437f0 1402 void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1403 {
mbed_official 133:d4dda5c437f0 1404 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
mbed_official 133:d4dda5c437f0 1405
mbed_official 133:d4dda5c437f0 1406 HAL_I2S_TxHalfCpltCallback(hi2s);
mbed_official 133:d4dda5c437f0 1407 }
mbed_official 133:d4dda5c437f0 1408
mbed_official 133:d4dda5c437f0 1409 /**
mbed_official 133:d4dda5c437f0 1410 * @brief DMA I2S receive process complete callback
mbed_official 133:d4dda5c437f0 1411 * @param hdma : DMA handle
mbed_official 133:d4dda5c437f0 1412 * @retval None
mbed_official 133:d4dda5c437f0 1413 */
mbed_official 133:d4dda5c437f0 1414 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1415 {
mbed_official 133:d4dda5c437f0 1416 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
mbed_official 133:d4dda5c437f0 1417
mbed_official 133:d4dda5c437f0 1418 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 133:d4dda5c437f0 1419 {
mbed_official 133:d4dda5c437f0 1420 /* Disable Rx DMA Request */
mbed_official 133:d4dda5c437f0 1421 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 133:d4dda5c437f0 1422
mbed_official 133:d4dda5c437f0 1423 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
mbed_official 133:d4dda5c437f0 1424 {
mbed_official 133:d4dda5c437f0 1425 /* Disable Tx DMA Request for the slave*/
mbed_official 133:d4dda5c437f0 1426 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 133:d4dda5c437f0 1427 }
mbed_official 133:d4dda5c437f0 1428
mbed_official 133:d4dda5c437f0 1429 hi2s->RxXferCount = 0;
mbed_official 133:d4dda5c437f0 1430 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
mbed_official 133:d4dda5c437f0 1431 {
mbed_official 133:d4dda5c437f0 1432 if(hi2s->TxXferCount == 0)
mbed_official 133:d4dda5c437f0 1433 {
mbed_official 133:d4dda5c437f0 1434 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1435 }
mbed_official 133:d4dda5c437f0 1436 }
mbed_official 133:d4dda5c437f0 1437 else
mbed_official 133:d4dda5c437f0 1438 {
mbed_official 133:d4dda5c437f0 1439 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1440 }
mbed_official 133:d4dda5c437f0 1441 }
mbed_official 133:d4dda5c437f0 1442 HAL_I2S_RxCpltCallback(hi2s);
mbed_official 133:d4dda5c437f0 1443 }
mbed_official 133:d4dda5c437f0 1444
mbed_official 133:d4dda5c437f0 1445 /**
mbed_official 133:d4dda5c437f0 1446 * @brief DMA I2S receive process half complete callback
mbed_official 133:d4dda5c437f0 1447 * @param hdma : DMA handle
mbed_official 133:d4dda5c437f0 1448 * @retval None
mbed_official 133:d4dda5c437f0 1449 */
mbed_official 133:d4dda5c437f0 1450 void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1451 {
mbed_official 133:d4dda5c437f0 1452 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
mbed_official 133:d4dda5c437f0 1453
mbed_official 133:d4dda5c437f0 1454 HAL_I2S_RxHalfCpltCallback(hi2s);
mbed_official 133:d4dda5c437f0 1455 }
mbed_official 133:d4dda5c437f0 1456
mbed_official 133:d4dda5c437f0 1457 /**
mbed_official 133:d4dda5c437f0 1458 * @brief DMA I2S communication error callback
mbed_official 133:d4dda5c437f0 1459 * @param hdma : DMA handle
mbed_official 133:d4dda5c437f0 1460 * @retval None
mbed_official 133:d4dda5c437f0 1461 */
mbed_official 133:d4dda5c437f0 1462 void I2S_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1463 {
mbed_official 133:d4dda5c437f0 1464 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
mbed_official 133:d4dda5c437f0 1465
mbed_official 133:d4dda5c437f0 1466 hi2s->TxXferCount = 0;
mbed_official 133:d4dda5c437f0 1467 hi2s->RxXferCount = 0;
mbed_official 133:d4dda5c437f0 1468
mbed_official 133:d4dda5c437f0 1469 hi2s->State= HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1470
mbed_official 133:d4dda5c437f0 1471 hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
mbed_official 133:d4dda5c437f0 1472 HAL_I2S_ErrorCallback(hi2s);
mbed_official 133:d4dda5c437f0 1473 }
mbed_official 133:d4dda5c437f0 1474
mbed_official 133:d4dda5c437f0 1475 /**
mbed_official 133:d4dda5c437f0 1476 * @brief Transmit an amount of data in non-blocking mode with Interrupt
mbed_official 133:d4dda5c437f0 1477 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1478 * @retval HAL status
mbed_official 133:d4dda5c437f0 1479 */
mbed_official 133:d4dda5c437f0 1480 static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1481 {
mbed_official 133:d4dda5c437f0 1482 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
mbed_official 133:d4dda5c437f0 1483 {
mbed_official 133:d4dda5c437f0 1484 /* Process Locked */
mbed_official 133:d4dda5c437f0 1485 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 1486
mbed_official 133:d4dda5c437f0 1487 /* Transmit data */
mbed_official 133:d4dda5c437f0 1488 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
mbed_official 133:d4dda5c437f0 1489
mbed_official 133:d4dda5c437f0 1490 hi2s->TxXferCount--;
mbed_official 133:d4dda5c437f0 1491
mbed_official 133:d4dda5c437f0 1492 if(hi2s->TxXferCount == 0)
mbed_official 133:d4dda5c437f0 1493 {
mbed_official 133:d4dda5c437f0 1494 /* Disable TXE and ERR interrupt */
mbed_official 133:d4dda5c437f0 1495 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
mbed_official 133:d4dda5c437f0 1496
mbed_official 133:d4dda5c437f0 1497 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1498
mbed_official 133:d4dda5c437f0 1499 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1500 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 1501 HAL_I2S_TxCpltCallback(hi2s);
mbed_official 133:d4dda5c437f0 1502 }
mbed_official 133:d4dda5c437f0 1503 else
mbed_official 133:d4dda5c437f0 1504 {
mbed_official 133:d4dda5c437f0 1505 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1506 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 1507 }
mbed_official 133:d4dda5c437f0 1508
mbed_official 133:d4dda5c437f0 1509 return HAL_OK;
mbed_official 133:d4dda5c437f0 1510 }
mbed_official 133:d4dda5c437f0 1511
mbed_official 133:d4dda5c437f0 1512 else
mbed_official 133:d4dda5c437f0 1513 {
mbed_official 133:d4dda5c437f0 1514 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1515 }
mbed_official 133:d4dda5c437f0 1516 }
mbed_official 133:d4dda5c437f0 1517
mbed_official 133:d4dda5c437f0 1518 /**
mbed_official 133:d4dda5c437f0 1519 * @brief Receive an amount of data in non-blocking mode with Interrupt
mbed_official 133:d4dda5c437f0 1520 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1521 * @retval HAL status
mbed_official 133:d4dda5c437f0 1522 */
mbed_official 133:d4dda5c437f0 1523 static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
mbed_official 133:d4dda5c437f0 1524 {
mbed_official 133:d4dda5c437f0 1525 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
mbed_official 133:d4dda5c437f0 1526 {
mbed_official 133:d4dda5c437f0 1527 /* Process Locked */
mbed_official 133:d4dda5c437f0 1528 __HAL_LOCK(hi2s);
mbed_official 133:d4dda5c437f0 1529
mbed_official 133:d4dda5c437f0 1530 /* Receive data */
mbed_official 133:d4dda5c437f0 1531 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
mbed_official 133:d4dda5c437f0 1532
mbed_official 133:d4dda5c437f0 1533 hi2s->RxXferCount--;
mbed_official 133:d4dda5c437f0 1534
mbed_official 133:d4dda5c437f0 1535 /* Check if Master Receiver mode is selected */
mbed_official 133:d4dda5c437f0 1536 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 133:d4dda5c437f0 1537 {
mbed_official 133:d4dda5c437f0 1538 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
mbed_official 133:d4dda5c437f0 1539 access to the SPI_SR register. */
mbed_official 133:d4dda5c437f0 1540 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 133:d4dda5c437f0 1541 }
mbed_official 133:d4dda5c437f0 1542
mbed_official 133:d4dda5c437f0 1543 if(hi2s->RxXferCount == 0)
mbed_official 133:d4dda5c437f0 1544 {
mbed_official 133:d4dda5c437f0 1545 /* Disable RXNE and ERR interrupt */
mbed_official 133:d4dda5c437f0 1546 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
mbed_official 133:d4dda5c437f0 1547
mbed_official 133:d4dda5c437f0 1548 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1549
mbed_official 133:d4dda5c437f0 1550 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1551 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 1552
mbed_official 133:d4dda5c437f0 1553 HAL_I2S_RxCpltCallback(hi2s);
mbed_official 133:d4dda5c437f0 1554 }
mbed_official 133:d4dda5c437f0 1555 else
mbed_official 133:d4dda5c437f0 1556 {
mbed_official 133:d4dda5c437f0 1557 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1558 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 1559 }
mbed_official 133:d4dda5c437f0 1560
mbed_official 133:d4dda5c437f0 1561 return HAL_OK;
mbed_official 133:d4dda5c437f0 1562 }
mbed_official 133:d4dda5c437f0 1563 else
mbed_official 133:d4dda5c437f0 1564 {
mbed_official 133:d4dda5c437f0 1565 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1566 }
mbed_official 133:d4dda5c437f0 1567 }
mbed_official 133:d4dda5c437f0 1568
mbed_official 133:d4dda5c437f0 1569 /**
mbed_official 133:d4dda5c437f0 1570 * @brief This function handles I2S Communication Timeout.
mbed_official 133:d4dda5c437f0 1571 * @param hi2s: I2S handle
mbed_official 133:d4dda5c437f0 1572 * @param Flag: Flag checked
mbed_official 133:d4dda5c437f0 1573 * @param State: Value of the flag expected
mbed_official 133:d4dda5c437f0 1574 * @param Timeout: Duration of the timeout
mbed_official 133:d4dda5c437f0 1575 * @retval HAL status
mbed_official 133:d4dda5c437f0 1576 */
mbed_official 133:d4dda5c437f0 1577 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 1578 {
mbed_official 133:d4dda5c437f0 1579 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1580
mbed_official 133:d4dda5c437f0 1581 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 1582
mbed_official 133:d4dda5c437f0 1583 /* Wait until flag is set */
mbed_official 133:d4dda5c437f0 1584 if(Status == RESET)
mbed_official 133:d4dda5c437f0 1585 {
mbed_official 133:d4dda5c437f0 1586 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
mbed_official 133:d4dda5c437f0 1587 {
mbed_official 133:d4dda5c437f0 1588 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 1589 {
mbed_official 133:d4dda5c437f0 1590 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1591 {
mbed_official 133:d4dda5c437f0 1592 /* Set the I2S State ready */
mbed_official 133:d4dda5c437f0 1593 hi2s->State= HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1594
mbed_official 133:d4dda5c437f0 1595 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1596 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 1597
mbed_official 133:d4dda5c437f0 1598 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1599 }
mbed_official 133:d4dda5c437f0 1600 }
mbed_official 133:d4dda5c437f0 1601 }
mbed_official 133:d4dda5c437f0 1602 }
mbed_official 133:d4dda5c437f0 1603 else
mbed_official 133:d4dda5c437f0 1604 {
mbed_official 133:d4dda5c437f0 1605 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
mbed_official 133:d4dda5c437f0 1606 {
mbed_official 133:d4dda5c437f0 1607 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 1608 {
mbed_official 133:d4dda5c437f0 1609 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1610 {
mbed_official 133:d4dda5c437f0 1611 /* Set the I2S State ready */
mbed_official 133:d4dda5c437f0 1612 hi2s->State= HAL_I2S_STATE_READY;
mbed_official 133:d4dda5c437f0 1613
mbed_official 133:d4dda5c437f0 1614 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1615 __HAL_UNLOCK(hi2s);
mbed_official 133:d4dda5c437f0 1616
mbed_official 133:d4dda5c437f0 1617 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1618 }
mbed_official 133:d4dda5c437f0 1619 }
mbed_official 133:d4dda5c437f0 1620 }
mbed_official 133:d4dda5c437f0 1621 }
mbed_official 133:d4dda5c437f0 1622 return HAL_OK;
mbed_official 133:d4dda5c437f0 1623 }
mbed_official 133:d4dda5c437f0 1624
mbed_official 133:d4dda5c437f0 1625 /**
mbed_official 133:d4dda5c437f0 1626 * @}
mbed_official 133:d4dda5c437f0 1627 */
mbed_official 133:d4dda5c437f0 1628
mbed_official 133:d4dda5c437f0 1629 #endif /* HAL_I2S_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 1630 /**
mbed_official 133:d4dda5c437f0 1631 * @}
mbed_official 133:d4dda5c437f0 1632 */
mbed_official 133:d4dda5c437f0 1633
mbed_official 133:d4dda5c437f0 1634 /**
mbed_official 133:d4dda5c437f0 1635 * @}
mbed_official 133:d4dda5c437f0 1636 */
mbed_official 133:d4dda5c437f0 1637
mbed_official 133:d4dda5c437f0 1638 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/