Vekatech / SDHI_driver

SDHI_driver patch (mbedOS 5.11.5)

mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdhi_iodefine.h@2:7c75ab32d7c9, 2019-03-29 (annotated)

Committer:
tvendov
Date:
Fri Mar 29 19:47:34 2019 +0200
Revision:
2:7c75ab32d7c9
Fix: Folder structure changed. All SD Auto tests pass with OK!

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tvendov 2:7c75ab32d7c9 1 /*******************************************************************************
tvendov 2:7c75ab32d7c9 2 * DISCLAIMER
tvendov 2:7c75ab32d7c9 3 *******************************************************************************/
tvendov 2:7c75ab32d7c9 4 /*******************************************************************************
tvendov 2:7c75ab32d7c9 5 * File Name : sdhi_iodefine.h
tvendov 2:7c75ab32d7c9 6 * $Rev: $
tvendov 2:7c75ab32d7c9 7 * $Date:: $
tvendov 2:7c75ab32d7c9 8 * Description : Definition of I/O Register for RZ/A1
tvendov 2:7c75ab32d7c9 9 ******************************************************************************/
tvendov 2:7c75ab32d7c9 10 #ifndef SDHI_IODEFINE_H
tvendov 2:7c75ab32d7c9 11 #define SDHI_IODEFINE_H
tvendov 2:7c75ab32d7c9 12 /* ->QAC 0639 : Over 127 members (C90) */
tvendov 2:7c75ab32d7c9 13 /* ->QAC 0857 : Over 1024 #define (C90) */
tvendov 2:7c75ab32d7c9 14 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
tvendov 2:7c75ab32d7c9 15 /* ->SEC M1.10.1 : Not magic number */
tvendov 2:7c75ab32d7c9 16
tvendov 2:7c75ab32d7c9 17 #define SDHI0 (*(struct st_sdhi *)0xE804E000uL) /* SDHI0 */
tvendov 2:7c75ab32d7c9 18 #define SDHI1 (*(struct st_sdhi *)0xE804E800uL) /* SDHI1 */
tvendov 2:7c75ab32d7c9 19
tvendov 2:7c75ab32d7c9 20
tvendov 2:7c75ab32d7c9 21 /* Start of channel array defines of SDHI */
tvendov 2:7c75ab32d7c9 22
tvendov 2:7c75ab32d7c9 23 /* Channel array defines of SDHI */
tvendov 2:7c75ab32d7c9 24 /*(Sample) value = SDHI[ channel ]->SD_CMD; */
tvendov 2:7c75ab32d7c9 25 #define SDHI_COUNT (2)
tvendov 2:7c75ab32d7c9 26 #define SDHI_ADDRESS_LIST \
tvendov 2:7c75ab32d7c9 27 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
tvendov 2:7c75ab32d7c9 28 &SDHI0 \
tvendov 2:7c75ab32d7c9 29 &SDHI1 \
tvendov 2:7c75ab32d7c9 30 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
tvendov 2:7c75ab32d7c9 31
tvendov 2:7c75ab32d7c9 32 /* End of channel array defines of SDHI */
tvendov 2:7c75ab32d7c9 33
tvendov 2:7c75ab32d7c9 34
tvendov 2:7c75ab32d7c9 35 #define SD_CMD_0 (SDHI0.SD_CMD)
tvendov 2:7c75ab32d7c9 36 #define SD_ARG0_0 (SDHI0.SD_ARG0)
tvendov 2:7c75ab32d7c9 37 #define SD_ARG1_0 (SDHI0.SD_ARG1)
tvendov 2:7c75ab32d7c9 38 #define SD_STOP_0 (SDHI0.SD_STOP)
tvendov 2:7c75ab32d7c9 39 #define SD_SECCNT_0 (SDHI0.SD_SECCNT)
tvendov 2:7c75ab32d7c9 40 #define SD_RSP00_0 (SDHI0.SD_RSP00)
tvendov 2:7c75ab32d7c9 41 #define SD_RSP01_0 (SDHI0.SD_RSP01)
tvendov 2:7c75ab32d7c9 42 #define SD_RSP02_0 (SDHI0.SD_RSP02)
tvendov 2:7c75ab32d7c9 43 #define SD_RSP03_0 (SDHI0.SD_RSP03)
tvendov 2:7c75ab32d7c9 44 #define SD_RSP04_0 (SDHI0.SD_RSP04)
tvendov 2:7c75ab32d7c9 45 #define SD_RSP05_0 (SDHI0.SD_RSP05)
tvendov 2:7c75ab32d7c9 46 #define SD_RSP06_0 (SDHI0.SD_RSP06)
tvendov 2:7c75ab32d7c9 47 #define SD_RSP07_0 (SDHI0.SD_RSP07)
tvendov 2:7c75ab32d7c9 48 #define SD_INFO1_0 (SDHI0.SD_INFO1)
tvendov 2:7c75ab32d7c9 49 #define SD_INFO2_0 (SDHI0.SD_INFO2)
tvendov 2:7c75ab32d7c9 50 #define SD_INFO1_MASK_0 (SDHI0.SD_INFO1_MASK)
tvendov 2:7c75ab32d7c9 51 #define SD_INFO2_MASK_0 (SDHI0.SD_INFO2_MASK)
tvendov 2:7c75ab32d7c9 52 #define SD_CLK_CTRL_0 (SDHI0.SD_CLK_CTRL)
tvendov 2:7c75ab32d7c9 53 #define SD_SIZE_0 (SDHI0.SD_SIZE)
tvendov 2:7c75ab32d7c9 54 #define SD_OPTION_0 (SDHI0.SD_OPTION)
tvendov 2:7c75ab32d7c9 55 #define SD_ERR_STS1_0 (SDHI0.SD_ERR_STS1)
tvendov 2:7c75ab32d7c9 56 #define SD_ERR_STS2_0 (SDHI0.SD_ERR_STS2)
tvendov 2:7c75ab32d7c9 57 #define SD_BUF0_0 (SDHI0.SD_BUF0)
tvendov 2:7c75ab32d7c9 58 #define SDIO_MODE_0 (SDHI0.SDIO_MODE)
tvendov 2:7c75ab32d7c9 59 #define SDIO_INFO1_0 (SDHI0.SDIO_INFO1)
tvendov 2:7c75ab32d7c9 60 #define SDIO_INFO1_MASK_0 (SDHI0.SDIO_INFO1_MASK)
tvendov 2:7c75ab32d7c9 61 #define CC_EXT_MODE_0 (SDHI0.CC_EXT_MODE)
tvendov 2:7c75ab32d7c9 62 #define SOFT_RST_0 (SDHI0.SOFT_RST)
tvendov 2:7c75ab32d7c9 63 #define VERSION_0 (SDHI0.VERSION)
tvendov 2:7c75ab32d7c9 64 #define EXT_SWAP_0 (SDHI0.EXT_SWAP)
tvendov 2:7c75ab32d7c9 65
tvendov 2:7c75ab32d7c9 66 #define SD_CMD_1 (SDHI1.SD_CMD)
tvendov 2:7c75ab32d7c9 67 #define SD_ARG0_1 (SDHI1.SD_ARG0)
tvendov 2:7c75ab32d7c9 68 #define SD_ARG1_1 (SDHI1.SD_ARG1)
tvendov 2:7c75ab32d7c9 69 #define SD_STOP_1 (SDHI1.SD_STOP)
tvendov 2:7c75ab32d7c9 70 #define SD_SECCNT_1 (SDHI1.SD_SECCNT)
tvendov 2:7c75ab32d7c9 71 #define SD_RSP00_1 (SDHI1.SD_RSP00)
tvendov 2:7c75ab32d7c9 72 #define SD_RSP01_1 (SDHI1.SD_RSP01)
tvendov 2:7c75ab32d7c9 73 #define SD_RSP02_1 (SDHI1.SD_RSP02)
tvendov 2:7c75ab32d7c9 74 #define SD_RSP03_1 (SDHI1.SD_RSP03)
tvendov 2:7c75ab32d7c9 75 #define SD_RSP04_1 (SDHI1.SD_RSP04)
tvendov 2:7c75ab32d7c9 76 #define SD_RSP05_1 (SDHI1.SD_RSP05)
tvendov 2:7c75ab32d7c9 77 #define SD_RSP06_1 (SDHI1.SD_RSP06)
tvendov 2:7c75ab32d7c9 78 #define SD_RSP07_1 (SDHI1.SD_RSP07)
tvendov 2:7c75ab32d7c9 79 #define SD_INFO1_1 (SDHI1.SD_INFO1)
tvendov 2:7c75ab32d7c9 80 #define SD_INFO2_1 (SDHI1.SD_INFO2)
tvendov 2:7c75ab32d7c9 81 #define SD_INFO1_MASK_1 (SDHI1.SD_INFO1_MASK)
tvendov 2:7c75ab32d7c9 82 #define SD_INFO2_MASK_1 (SDHI1.SD_INFO2_MASK)
tvendov 2:7c75ab32d7c9 83 #define SD_CLK_CTRL_1 (SDHI1.SD_CLK_CTRL)
tvendov 2:7c75ab32d7c9 84 #define SD_SIZE_1 (SDHI1.SD_SIZE)
tvendov 2:7c75ab32d7c9 85 #define SD_OPTION_1 (SDHI1.SD_OPTION)
tvendov 2:7c75ab32d7c9 86 #define SD_ERR_STS1_1 (SDHI1.SD_ERR_STS1)
tvendov 2:7c75ab32d7c9 87 #define SD_ERR_STS2_1 (SDHI1.SD_ERR_STS2)
tvendov 2:7c75ab32d7c9 88 #define SD_BUF0_1 (SDHI1.SD_BUF0)
tvendov 2:7c75ab32d7c9 89 #define SDIO_MODE_1 (SDHI1.SDIO_MODE)
tvendov 2:7c75ab32d7c9 90 #define SDIO_INFO1_1 (SDHI1.SDIO_INFO1)
tvendov 2:7c75ab32d7c9 91 #define SDIO_INFO1_MASK_1 (SDHI1.SDIO_INFO1_MASK)
tvendov 2:7c75ab32d7c9 92 #define CC_EXT_MODE_1 (SDHI1.CC_EXT_MODE)
tvendov 2:7c75ab32d7c9 93 #define SOFT_RST_1 (SDHI1.SOFT_RST)
tvendov 2:7c75ab32d7c9 94 #define VERSION_1 (SDHI1.VERSION)
tvendov 2:7c75ab32d7c9 95 #define EXT_SWAP_1 (SDHI1.EXT_SWAP)
tvendov 2:7c75ab32d7c9 96
tvendov 2:7c75ab32d7c9 97 typedef struct st_sdhi
tvendov 2:7c75ab32d7c9 98 {
tvendov 2:7c75ab32d7c9 99 /* SDHI */
tvendov 2:7c75ab32d7c9 100 volatile uint16_t SD_CMD; /* SD_CMD */
tvendov 2:7c75ab32d7c9 101 volatile uint8_t dummy1[2]; /* */
tvendov 2:7c75ab32d7c9 102 volatile uint16_t SD_ARG0; /* SSLDR */
tvendov 2:7c75ab32d7c9 103 volatile uint16_t SD_ARG1; /* SSLDR */
tvendov 2:7c75ab32d7c9 104 volatile uint16_t SD_STOP; /* SPBCR */
tvendov 2:7c75ab32d7c9 105 volatile uint16_t SD_SECCNT; /* SPBCR */
tvendov 2:7c75ab32d7c9 106 volatile uint16_t SD_RSP00; /* SPBCR */
tvendov 2:7c75ab32d7c9 107 volatile uint16_t SD_RSP01; /* SPBCR */
tvendov 2:7c75ab32d7c9 108 volatile uint16_t SD_RSP02; /* SPBCR */
tvendov 2:7c75ab32d7c9 109 volatile uint16_t SD_RSP03; /* SPBCR */
tvendov 2:7c75ab32d7c9 110 volatile uint16_t SD_RSP04; /* SPBCR */
tvendov 2:7c75ab32d7c9 111 volatile uint16_t SD_RSP05; /* SPBCR */
tvendov 2:7c75ab32d7c9 112 volatile uint16_t SD_RSP06; /* SPBCR */
tvendov 2:7c75ab32d7c9 113 volatile uint16_t SD_RSP07; /* SPBCR */
tvendov 2:7c75ab32d7c9 114 volatile uint16_t SD_INFO1; /* SPBCR */
tvendov 2:7c75ab32d7c9 115 volatile uint16_t SD_INFO2; /* SPBCR */
tvendov 2:7c75ab32d7c9 116 volatile uint16_t SD_INFO1_MASK; /* SPBCR */
tvendov 2:7c75ab32d7c9 117 volatile uint16_t SD_INFO2_MASK; /* SPBCR */
tvendov 2:7c75ab32d7c9 118 volatile uint16_t SD_CLK_CTRL; /* SPBCR */
tvendov 2:7c75ab32d7c9 119 volatile uint16_t SD_SIZE; /* SPBCR */
tvendov 2:7c75ab32d7c9 120 volatile uint16_t SD_OPTION; /* SPBCR */
tvendov 2:7c75ab32d7c9 121 volatile uint8_t dummy2[2]; /* */
tvendov 2:7c75ab32d7c9 122 volatile uint16_t SD_ERR_STS1; /* SPBCR */
tvendov 2:7c75ab32d7c9 123 volatile uint16_t SD_ERR_STS2; /* SPBCR */
tvendov 2:7c75ab32d7c9 124 volatile uint32_t SD_BUF0; /* DRCR */
tvendov 2:7c75ab32d7c9 125 volatile uint16_t SDIO_MODE; /* DRCMR */
tvendov 2:7c75ab32d7c9 126 volatile uint16_t SDIO_INFO1; /* DREAR */
tvendov 2:7c75ab32d7c9 127 volatile uint16_t SDIO_INFO1_MASK; /* DROPR */
tvendov 2:7c75ab32d7c9 128 volatile uint8_t dummy3[158]; /* */
tvendov 2:7c75ab32d7c9 129 volatile uint16_t CC_EXT_MODE; /* DRENR */
tvendov 2:7c75ab32d7c9 130 volatile uint8_t dummy4[6]; /* */
tvendov 2:7c75ab32d7c9 131 volatile uint16_t SOFT_RST; /* SMCR */
tvendov 2:7c75ab32d7c9 132 volatile uint16_t VERSION; /* SMCMR */
tvendov 2:7c75ab32d7c9 133 volatile uint8_t dummy5[12]; /* */
tvendov 2:7c75ab32d7c9 134 volatile uint16_t EXT_SWAP; /* SMADR */
tvendov 2:7c75ab32d7c9 135 } r_io_sdhi_t;
tvendov 2:7c75ab32d7c9 136
tvendov 2:7c75ab32d7c9 137
tvendov 2:7c75ab32d7c9 138 /* Channel array defines of SDHI (2)*/
tvendov 2:7c75ab32d7c9 139 #ifdef DECLARE_SDHI_CHANNELS
tvendov 2:7c75ab32d7c9 140 volatile struct st_sdhi* SDHI[ SDHI_COUNT ] =
tvendov 2:7c75ab32d7c9 141 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
tvendov 2:7c75ab32d7c9 142 SDHI_ADDRESS_LIST;
tvendov 2:7c75ab32d7c9 143 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
tvendov 2:7c75ab32d7c9 144 #endif /* DECLARE_SPIBSC_CHANNELS */
tvendov 2:7c75ab32d7c9 145 /* End of channel array defines of SDHI (2)*/
tvendov 2:7c75ab32d7c9 146
tvendov 2:7c75ab32d7c9 147
tvendov 2:7c75ab32d7c9 148 /* <-SEC M1.10.1 */
tvendov 2:7c75ab32d7c9 149 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
tvendov 2:7c75ab32d7c9 150 /* <-QAC 0857 */
tvendov 2:7c75ab32d7c9 151 /* <-QAC 0639 */
tvendov 2:7c75ab32d7c9 152 #endif
tvendov 2:7c75ab32d7c9 153