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targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c@587:61103edf8a92, 2015-07-10 (annotated)

Committer:
mbed_official
Date:
Fri Jul 10 14:15:08 2015 +0100
Revision:
587:61103edf8a92
Parent:
82:0b31dbcd4769 
Synchronized with git revision 6cb7294c83b739aaf94e7f5d477479c9e332c700



Full URL: https://github.com/mbedmicro/mbed/commit/6cb7294c83b739aaf94e7f5d477479c9e332c700/



[KL25Z] add 32KHz crystal clock setup 3 + minor RTC api changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 82:0b31dbcd4769 1 /*
mbed_official 82:0b31dbcd4769 2 ** ###################################################################
mbed_official 82:0b31dbcd4769 3 ** Processor: MKL25Z128VLK4
mbed_official 82:0b31dbcd4769 4 ** Compilers: ARM Compiler
mbed_official 82:0b31dbcd4769 5 ** Freescale C/C++ for Embedded ARM
mbed_official 82:0b31dbcd4769 6 ** GNU C Compiler
mbed_official 82:0b31dbcd4769 7 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 82:0b31dbcd4769 8 **
mbed_official 82:0b31dbcd4769 9 ** Reference manual: KL25RM, Rev.1, Jun 2012
mbed_official 82:0b31dbcd4769 10 ** Version: rev. 1.1, 2012-06-21
mbed_official 82:0b31dbcd4769 11 **
mbed_official 82:0b31dbcd4769 12 ** Abstract:
mbed_official 82:0b31dbcd4769 13 ** Provides a system configuration function and a global variable that
mbed_official 82:0b31dbcd4769 14 ** contains the system frequency. It configures the device and initializes
mbed_official 82:0b31dbcd4769 15 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 82:0b31dbcd4769 16 **
mbed_official 82:0b31dbcd4769 17 ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
mbed_official 82:0b31dbcd4769 18 **
mbed_official 82:0b31dbcd4769 19 ** http: www.freescale.com
mbed_official 82:0b31dbcd4769 20 ** mail: support@freescale.com
mbed_official 82:0b31dbcd4769 21 **
mbed_official 82:0b31dbcd4769 22 ** Revisions:
mbed_official 82:0b31dbcd4769 23 ** - rev. 1.0 (2012-06-13)
mbed_official 82:0b31dbcd4769 24 ** Initial version.
mbed_official 82:0b31dbcd4769 25 ** - rev. 1.1 (2012-06-21)
mbed_official 82:0b31dbcd4769 26 ** Update according to reference manual rev. 1.
mbed_official 82:0b31dbcd4769 27 **
mbed_official 82:0b31dbcd4769 28 ** ###################################################################
mbed_official 82:0b31dbcd4769 29 */
mbed_official 82:0b31dbcd4769 30
mbed_official 82:0b31dbcd4769 31 /**
mbed_official 82:0b31dbcd4769 32 * @file MKL25Z4
mbed_official 82:0b31dbcd4769 33 * @version 1.1
mbed_official 82:0b31dbcd4769 34 * @date 2012-06-21
mbed_official 82:0b31dbcd4769 35 * @brief Device specific configuration file for MKL25Z4 (implementation file)
mbed_official 82:0b31dbcd4769 36 *
mbed_official 82:0b31dbcd4769 37 * Provides a system configuration function and a global variable that contains
mbed_official 82:0b31dbcd4769 38 * the system frequency. It configures the device and initializes the oscillator
mbed_official 82:0b31dbcd4769 39 * (PLL) that is part of the microcontroller device.
mbed_official 82:0b31dbcd4769 40 */
mbed_official 82:0b31dbcd4769 41
mbed_official 82:0b31dbcd4769 42 #include <stdint.h>
mbed_official 82:0b31dbcd4769 43 #include "MKL25Z4.h"
mbed_official 82:0b31dbcd4769 44
mbed_official 82:0b31dbcd4769 45 #define DISABLE_WDOG 1
mbed_official 82:0b31dbcd4769 46
mbed_official 82:0b31dbcd4769 47 #define CLOCK_SETUP 1
mbed_official 82:0b31dbcd4769 48 /* Predefined clock setups
mbed_official 82:0b31dbcd4769 49 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
mbed_official 82:0b31dbcd4769 50 Reference clock source for MCG module is the slow internal clock source 32.768kHz
mbed_official 82:0b31dbcd4769 51 Core clock = 41.94MHz, BusClock = 13.98MHz
mbed_official 82:0b31dbcd4769 52 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
mbed_official 82:0b31dbcd4769 53 Reference clock source for MCG module is an external crystal 8MHz
mbed_official 82:0b31dbcd4769 54 Core clock = 48MHz, BusClock = 24MHz
mbed_official 82:0b31dbcd4769 55 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
mbed_official 82:0b31dbcd4769 56 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
mbed_official 82:0b31dbcd4769 57 Core clock = 8MHz, BusClock = 8MHz
mbed_official 587:61103edf8a92 58 3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
mbed_official 587:61103edf8a92 59 Reference clock source for MCG module is an external crystal 32.768kHz
mbed_official 587:61103edf8a92 60 Core clock = 47.97MHz, BusClock = 23.98MHz
mbed_official 587:61103edf8a92 61 This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
mbed_official 587:61103edf8a92 62 RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
mbed_official 587:61103edf8a92 63 accuracy durring the reset period. RTC will reset on power down.
mbed_official 82:0b31dbcd4769 64 */
mbed_official 82:0b31dbcd4769 65
mbed_official 82:0b31dbcd4769 66 /*----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 67 Define clock source values
mbed_official 82:0b31dbcd4769 68 *----------------------------------------------------------------------------*/
mbed_official 82:0b31dbcd4769 69 #if (CLOCK_SETUP == 0)
mbed_official 82:0b31dbcd4769 70 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 71 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 72 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 73 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
mbed_official 82:0b31dbcd4769 74 #elif (CLOCK_SETUP == 1)
mbed_official 82:0b31dbcd4769 75 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 76 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 77 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 78 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
mbed_official 82:0b31dbcd4769 79 #elif (CLOCK_SETUP == 2)
mbed_official 82:0b31dbcd4769 80 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 81 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 82 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 83 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
mbed_official 587:61103edf8a92 84 #elif (CLOCK_SETUP == 3)
mbed_official 587:61103edf8a92 85 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 587:61103edf8a92 86 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 587:61103edf8a92 87 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 587:61103edf8a92 88 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
mbed_official 587:61103edf8a92 89 #endif /* (CLOCK_SETUP == 3) */
mbed_official 82:0b31dbcd4769 90
mbed_official 82:0b31dbcd4769 91 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 92 -- Core clock
mbed_official 82:0b31dbcd4769 93 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 94
mbed_official 82:0b31dbcd4769 95 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 82:0b31dbcd4769 96
mbed_official 82:0b31dbcd4769 97 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 98 -- SystemInit()
mbed_official 82:0b31dbcd4769 99 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 100
mbed_official 82:0b31dbcd4769 101 void SystemInit (void) {
mbed_official 82:0b31dbcd4769 102 #if (DISABLE_WDOG)
mbed_official 82:0b31dbcd4769 103 /* Disable the WDOG module */
mbed_official 82:0b31dbcd4769 104 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
mbed_official 82:0b31dbcd4769 105 SIM->COPC = (uint32_t)0x00u;
mbed_official 82:0b31dbcd4769 106 #endif /* (DISABLE_WDOG) */
mbed_official 82:0b31dbcd4769 107 #if (CLOCK_SETUP == 0)
mbed_official 82:0b31dbcd4769 108 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 82:0b31dbcd4769 109 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
mbed_official 82:0b31dbcd4769 110 /* Switch to FEI Mode */
mbed_official 82:0b31dbcd4769 111 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 112 MCG->C1 = (uint8_t)0x06U;
mbed_official 82:0b31dbcd4769 113 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
mbed_official 82:0b31dbcd4769 114 MCG->C2 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 115 /* MCG->C4: DMX32=0,DRST_DRS=1 */
mbed_official 82:0b31dbcd4769 116 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
mbed_official 82:0b31dbcd4769 117 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 82:0b31dbcd4769 118 OSC0->CR = (uint8_t)0x80U;
mbed_official 82:0b31dbcd4769 119 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 82:0b31dbcd4769 120 MCG->C5 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 121 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 82:0b31dbcd4769 122 MCG->C6 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 123 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
mbed_official 82:0b31dbcd4769 124 }
mbed_official 82:0b31dbcd4769 125 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 82:0b31dbcd4769 126 }
mbed_official 82:0b31dbcd4769 127 #elif (CLOCK_SETUP == 1)
mbed_official 82:0b31dbcd4769 128 /* SIM->SCGC5: PORTA=1 */
mbed_official 82:0b31dbcd4769 129 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
mbed_official 82:0b31dbcd4769 130 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 82:0b31dbcd4769 131 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
mbed_official 82:0b31dbcd4769 132 /* PORTA->PCR18: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 133 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
mbed_official 82:0b31dbcd4769 134 /* PORTA->PCR19: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 135 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
mbed_official 82:0b31dbcd4769 136 /* Switch to FBE Mode */
mbed_official 82:0b31dbcd4769 137 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
mbed_official 82:0b31dbcd4769 138 OSC0->CR = (uint8_t)0x89U;
mbed_official 82:0b31dbcd4769 139 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 82:0b31dbcd4769 140 MCG->C2 = (uint8_t)0x24U;
mbed_official 82:0b31dbcd4769 141 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 142 MCG->C1 = (uint8_t)0x9AU;
mbed_official 82:0b31dbcd4769 143 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 82:0b31dbcd4769 144 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
mbed_official 82:0b31dbcd4769 145 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
mbed_official 82:0b31dbcd4769 146 MCG->C5 = (uint8_t)0x01U;
mbed_official 82:0b31dbcd4769 147 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 82:0b31dbcd4769 148 MCG->C6 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 149 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 82:0b31dbcd4769 150 }
mbed_official 82:0b31dbcd4769 151 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 82:0b31dbcd4769 152 }
mbed_official 82:0b31dbcd4769 153 /* Switch to PBE Mode */
mbed_official 82:0b31dbcd4769 154 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
mbed_official 82:0b31dbcd4769 155 MCG->C6 = (uint8_t)0x40U;
mbed_official 82:0b31dbcd4769 156 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 82:0b31dbcd4769 157 }
mbed_official 82:0b31dbcd4769 158 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
mbed_official 82:0b31dbcd4769 159 }
mbed_official 82:0b31dbcd4769 160 /* Switch to PEE Mode */
mbed_official 82:0b31dbcd4769 161 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 162 MCG->C1 = (uint8_t)0x1AU;
mbed_official 82:0b31dbcd4769 163 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
mbed_official 82:0b31dbcd4769 164 }
mbed_official 82:0b31dbcd4769 165 #elif (CLOCK_SETUP == 2)
mbed_official 82:0b31dbcd4769 166 /* SIM->SCGC5: PORTA=1 */
mbed_official 82:0b31dbcd4769 167 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
mbed_official 82:0b31dbcd4769 168 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 82:0b31dbcd4769 169 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
mbed_official 82:0b31dbcd4769 170 /* PORTA->PCR18: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 171 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
mbed_official 82:0b31dbcd4769 172 /* PORTA->PCR19: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 173 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
mbed_official 82:0b31dbcd4769 174 /* Switch to FBE Mode */
mbed_official 82:0b31dbcd4769 175 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
mbed_official 82:0b31dbcd4769 176 OSC0->CR = (uint8_t)0x89U;
mbed_official 82:0b31dbcd4769 177 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 82:0b31dbcd4769 178 MCG->C2 = (uint8_t)0x24U;
mbed_official 82:0b31dbcd4769 179 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 180 MCG->C1 = (uint8_t)0x9AU;
mbed_official 82:0b31dbcd4769 181 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 82:0b31dbcd4769 182 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
mbed_official 82:0b31dbcd4769 183 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 82:0b31dbcd4769 184 MCG->C5 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 185 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 82:0b31dbcd4769 186 MCG->C6 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 187 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 82:0b31dbcd4769 188 }
mbed_official 82:0b31dbcd4769 189 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 82:0b31dbcd4769 190 }
mbed_official 82:0b31dbcd4769 191 /* Switch to BLPE Mode */
mbed_official 82:0b31dbcd4769 192 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
mbed_official 82:0b31dbcd4769 193 MCG->C2 = (uint8_t)0x26U;
mbed_official 82:0b31dbcd4769 194 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 82:0b31dbcd4769 195 }
mbed_official 587:61103edf8a92 196 #elif (CLOCK_SETUP == 3)
mbed_official 587:61103edf8a92 197 /* SIM->SCGC5: PORTA=1 */
mbed_official 587:61103edf8a92 198 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
mbed_official 587:61103edf8a92 199 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 587:61103edf8a92 200 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
mbed_official 587:61103edf8a92 201 /* PORTA->PCR[3]: ISF=0,MUX=0 */
mbed_official 587:61103edf8a92 202 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 587:61103edf8a92 203 /* PORTA->PCR[4]: ISF=0,MUX=0 */
mbed_official 587:61103edf8a92 204 PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 587:61103edf8a92 205 /* Switch to FEE Mode */
mbed_official 587:61103edf8a92 206 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 587:61103edf8a92 207 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
mbed_official 587:61103edf8a92 208 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 587:61103edf8a92 209 OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
mbed_official 587:61103edf8a92 210 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 587:61103edf8a92 211 MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
mbed_official 587:61103edf8a92 212 /* MCG->C4: DMX32=1,DRST_DRS=1 */
mbed_official 587:61103edf8a92 213 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
mbed_official 587:61103edf8a92 214 MCG_C4_DRST_DRS(0x02)
mbed_official 587:61103edf8a92 215 )) | (uint8_t)(
mbed_official 587:61103edf8a92 216 MCG_C4_DMX32_MASK |
mbed_official 587:61103edf8a92 217 MCG_C4_DRST_DRS(0x01)
mbed_official 587:61103edf8a92 218 ));
mbed_official 587:61103edf8a92 219 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 587:61103edf8a92 220 }
mbed_official 587:61103edf8a92 221 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 587:61103edf8a92 222 }
mbed_official 587:61103edf8a92 223 #endif /* (CLOCK_SETUP == 3) */
mbed_official 82:0b31dbcd4769 224 }
mbed_official 82:0b31dbcd4769 225
mbed_official 82:0b31dbcd4769 226 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 227 -- SystemCoreClockUpdate()
mbed_official 82:0b31dbcd4769 228 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 229
mbed_official 82:0b31dbcd4769 230 void SystemCoreClockUpdate (void) {
mbed_official 82:0b31dbcd4769 231 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 82:0b31dbcd4769 232 uint8_t Divider;
mbed_official 82:0b31dbcd4769 233
mbed_official 82:0b31dbcd4769 234 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 235 /* Output of FLL or PLL is selected */
mbed_official 82:0b31dbcd4769 236 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 237 /* FLL is selected */
mbed_official 82:0b31dbcd4769 238 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 239 /* External reference clock is selected */
mbed_official 82:0b31dbcd4769 240 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 82:0b31dbcd4769 241 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 82:0b31dbcd4769 242 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 82:0b31dbcd4769 243 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
mbed_official 82:0b31dbcd4769 244 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
mbed_official 82:0b31dbcd4769 245 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
mbed_official 82:0b31dbcd4769 246 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 247 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 82:0b31dbcd4769 248 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 249 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 82:0b31dbcd4769 250 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 82:0b31dbcd4769 251 case 0x0u:
mbed_official 82:0b31dbcd4769 252 MCGOUTClock *= 640u;
mbed_official 82:0b31dbcd4769 253 break;
mbed_official 82:0b31dbcd4769 254 case 0x20u:
mbed_official 82:0b31dbcd4769 255 MCGOUTClock *= 1280u;
mbed_official 82:0b31dbcd4769 256 break;
mbed_official 82:0b31dbcd4769 257 case 0x40u:
mbed_official 82:0b31dbcd4769 258 MCGOUTClock *= 1920u;
mbed_official 82:0b31dbcd4769 259 break;
mbed_official 82:0b31dbcd4769 260 case 0x60u:
mbed_official 82:0b31dbcd4769 261 MCGOUTClock *= 2560u;
mbed_official 82:0b31dbcd4769 262 break;
mbed_official 82:0b31dbcd4769 263 case 0x80u:
mbed_official 82:0b31dbcd4769 264 MCGOUTClock *= 732u;
mbed_official 82:0b31dbcd4769 265 break;
mbed_official 82:0b31dbcd4769 266 case 0xA0u:
mbed_official 82:0b31dbcd4769 267 MCGOUTClock *= 1464u;
mbed_official 82:0b31dbcd4769 268 break;
mbed_official 82:0b31dbcd4769 269 case 0xC0u:
mbed_official 82:0b31dbcd4769 270 MCGOUTClock *= 2197u;
mbed_official 82:0b31dbcd4769 271 break;
mbed_official 82:0b31dbcd4769 272 case 0xE0u:
mbed_official 82:0b31dbcd4769 273 MCGOUTClock *= 2929u;
mbed_official 82:0b31dbcd4769 274 break;
mbed_official 82:0b31dbcd4769 275 default:
mbed_official 82:0b31dbcd4769 276 break;
mbed_official 82:0b31dbcd4769 277 }
mbed_official 82:0b31dbcd4769 278 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 279 /* PLL is selected */
mbed_official 82:0b31dbcd4769 280 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 82:0b31dbcd4769 281 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 82:0b31dbcd4769 282 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 82:0b31dbcd4769 283 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 82:0b31dbcd4769 284 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 285 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
mbed_official 82:0b31dbcd4769 286 /* Internal reference clock is selected */
mbed_official 82:0b31dbcd4769 287 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 288 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 82:0b31dbcd4769 289 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 290 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
mbed_official 82:0b31dbcd4769 291 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 292 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
mbed_official 82:0b31dbcd4769 293 /* External reference clock is selected */
mbed_official 82:0b31dbcd4769 294 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 82:0b31dbcd4769 295 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 82:0b31dbcd4769 296 /* Reserved value */
mbed_official 82:0b31dbcd4769 297 return;
mbed_official 82:0b31dbcd4769 298 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 82:0b31dbcd4769 299 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 82:0b31dbcd4769 300 }