Revision 499:d0e9408fd176, committed 2015-03-28

Comitter:

mbed_official

Date:

Sat Mar 28 08:15:07 2015 +0000

Parent:

498:b3c41e21851c

Child:

500:222d8913df56

Commit message:

Synchronized with git revision 95bb89d4a89b0584563bfd552f148d262310ded9

Full URL: https://github.com/mbedmicro/mbed/commit/95bb89d4a89b0584563bfd552f148d262310ded9/

Hal - K20XX/K?DR Fixed deepsleep power consumption when AnalogIn is used

Changed in this revision

--- a/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c	Fri Mar 27 16:00:09 2015 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c	Sat Mar 28 08:15:07 2015 +0000
@@ -51,7 +51,6 @@
                | ADC_CFG1_ADICLK(clkdiv >> 2);    // Input Clock
 
     ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK   // ADxxb or ADxxa channels
-               | ADC_CFG2_ADACKEN_MASK  // Asynchronous Clock Output Enable
                | ADC_CFG2_ADHSC_MASK    // High-Speed Configuration
                | ADC_CFG2_ADLSTS(0);    // Long Sample Time Select
 

--- a/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c	Fri Mar 27 16:00:09 2015 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c	Sat Mar 28 08:15:07 2015 +0000
@@ -29,6 +29,15 @@
 //Very low-power stop mode
 void deepsleep(void)
 {
+    //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
+    uint8_t ADC_HSC = 0;
+    if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
+        if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
+            ADC_HSC = 1;
+            ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
+        }
+    }
+    
     //Check if PLL/FLL is enabled:
     uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
     
@@ -67,4 +76,8 @@
         while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { }    // Wait until locked             
 #endif
     }
+    
+    if (ADC_HSC) {
+        ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
+    }
 }

--- a/targets/hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c	Fri Mar 27 16:00:09 2015 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c	Sat Mar 28 08:15:07 2015 +0000
@@ -58,7 +58,6 @@
                | ADC_CFG1_ADICLK(clkdiv >> 2);  // Input Clock: (Bus Clock)/2
 
     ADC0->CFG2 = cfg2_muxsel            // ADxxb or ADxxa channels
-               | ADC_CFG2_ADACKEN_MASK  // Asynchronous Clock Output Enable
                | ADC_CFG2_ADHSC_MASK    // High-Speed Configuration
                | ADC_CFG2_ADLSTS(0);    // Long Sample Time Select
 

--- a/targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c	Fri Mar 27 16:00:09 2015 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c	Sat Mar 28 08:15:07 2015 +0000
@@ -30,6 +30,15 @@
 //Very low-power stop mode
 void deepsleep(void)
 {
+    //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
+    uint8_t ADC_HSC = 0;
+    if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
+        if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
+            ADC_HSC = 1;
+            ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
+        }
+    }
+    
 #if ! defined(TARGET_KL43Z)
     //Check if PLL/FLL is enabled:
     uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
@@ -54,4 +63,8 @@
         MCG->C1 &= ~MCG_C1_CLKS_MASK;
     }
 #endif 
+
+    if (ADC_HSC) {
+        ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
+    }
 }