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targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c@497:d54623194236, 2015-03-26 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Mar 26 13:45:12 2015 +0000
- Revision:
- 497:d54623194236
Synchronized with git revision 0251fefac99a5b59beb481e845c6fbf48736bac6
Full URL: https://github.com/mbedmicro/mbed/commit/0251fefac99a5b59beb481e845c6fbf48736bac6/
DISCO_F100RB -Support HAL driver
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 497:d54623194236 | 1 | /** |
| mbed_official | 497:d54623194236 | 2 | ****************************************************************************** |
| mbed_official | 497:d54623194236 | 3 | * @file system_stm32f1xx.c |
| mbed_official | 497:d54623194236 | 4 | * @author MCD Application Team |
| mbed_official | 497:d54623194236 | 5 | * @version V4.0.0 |
| mbed_official | 497:d54623194236 | 6 | * @date 16-December-2014 |
| mbed_official | 497:d54623194236 | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
| mbed_official | 497:d54623194236 | 8 | * |
| mbed_official | 497:d54623194236 | 9 | * 1. This file provides two functions and one global variable to be called from |
| mbed_official | 497:d54623194236 | 10 | * user application: |
| mbed_official | 497:d54623194236 | 11 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
| mbed_official | 497:d54623194236 | 12 | * factors, AHB/APBx prescalers and Flash settings). |
| mbed_official | 497:d54623194236 | 13 | * This function is called at startup just after reset and |
| mbed_official | 497:d54623194236 | 14 | * before branch to main program. This call is made inside |
| mbed_official | 497:d54623194236 | 15 | * the "startup_stm32f1xx_xx.s" file. |
| mbed_official | 497:d54623194236 | 16 | * |
| mbed_official | 497:d54623194236 | 17 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| mbed_official | 497:d54623194236 | 18 | * by the user application to setup the SysTick |
| mbed_official | 497:d54623194236 | 19 | * timer or configure other parameters. |
| mbed_official | 497:d54623194236 | 20 | * |
| mbed_official | 497:d54623194236 | 21 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| mbed_official | 497:d54623194236 | 22 | * be called whenever the core clock is changed |
| mbed_official | 497:d54623194236 | 23 | * during program execution. |
| mbed_official | 497:d54623194236 | 24 | * |
| mbed_official | 497:d54623194236 | 25 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
| mbed_official | 497:d54623194236 | 26 | * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to |
| mbed_official | 497:d54623194236 | 27 | * configure the system clock before to branch to main program. |
| mbed_official | 497:d54623194236 | 28 | * |
| mbed_official | 497:d54623194236 | 29 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on |
| mbed_official | 497:d54623194236 | 30 | * the product used), refer to "HSE_VALUE". |
| mbed_official | 497:d54623194236 | 31 | * When HSE is used as system clock source, directly or through PLL, and you |
| mbed_official | 497:d54623194236 | 32 | * are using different crystal you have to adapt the HSE value to your own |
| mbed_official | 497:d54623194236 | 33 | * configuration. |
| mbed_official | 497:d54623194236 | 34 | * |
| mbed_official | 497:d54623194236 | 35 | * This file configures the system clock as follows: |
| mbed_official | 497:d54623194236 | 36 | *----------------------------------------------------------------------------- |
| mbed_official | 497:d54623194236 | 37 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
| mbed_official | 497:d54623194236 | 38 | * | (external 8 MHz clock) | (internal 8 MHz) |
| mbed_official | 497:d54623194236 | 39 | * | 2- PLL_HSE_XTAL | |
| mbed_official | 497:d54623194236 | 40 | * | (external 8 MHz xtal) | |
| mbed_official | 497:d54623194236 | 41 | *----------------------------------------------------------------------------- |
| mbed_official | 497:d54623194236 | 42 | * SYSCLK(MHz) | 24 | 24 |
| mbed_official | 497:d54623194236 | 43 | *----------------------------------------------------------------------------- |
| mbed_official | 497:d54623194236 | 44 | * AHBCLK (MHz) | 24 | 24 |
| mbed_official | 497:d54623194236 | 45 | *----------------------------------------------------------------------------- |
| mbed_official | 497:d54623194236 | 46 | * APB1CLK (MHz) | 24 | 24 |
| mbed_official | 497:d54623194236 | 47 | *----------------------------------------------------------------------------- |
| mbed_official | 497:d54623194236 | 48 | * APB2CLK (MHz) | 24 | 24 |
| mbed_official | 497:d54623194236 | 49 | *----------------------------------------------------------------------------- |
| mbed_official | 497:d54623194236 | 50 | ****************************************************************************** |
| mbed_official | 497:d54623194236 | 51 | * @attention |
| mbed_official | 497:d54623194236 | 52 | * |
| mbed_official | 497:d54623194236 | 53 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 497:d54623194236 | 54 | * |
| mbed_official | 497:d54623194236 | 55 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 497:d54623194236 | 56 | * are permitted provided that the following conditions are met: |
| mbed_official | 497:d54623194236 | 57 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 497:d54623194236 | 58 | * this list of conditions and the following disclaimer. |
| mbed_official | 497:d54623194236 | 59 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 497:d54623194236 | 60 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 497:d54623194236 | 61 | * and/or other materials provided with the distribution. |
| mbed_official | 497:d54623194236 | 62 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 497:d54623194236 | 63 | * may be used to endorse or promote products derived from this software |
| mbed_official | 497:d54623194236 | 64 | * without specific prior written permission. |
| mbed_official | 497:d54623194236 | 65 | * |
| mbed_official | 497:d54623194236 | 66 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 497:d54623194236 | 67 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 497:d54623194236 | 68 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 497:d54623194236 | 69 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 497:d54623194236 | 70 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 497:d54623194236 | 71 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 497:d54623194236 | 72 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 497:d54623194236 | 73 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 497:d54623194236 | 74 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 497:d54623194236 | 75 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 497:d54623194236 | 76 | * |
| mbed_official | 497:d54623194236 | 77 | ****************************************************************************** |
| mbed_official | 497:d54623194236 | 78 | */ |
| mbed_official | 497:d54623194236 | 79 | |
| mbed_official | 497:d54623194236 | 80 | /** @addtogroup CMSIS |
| mbed_official | 497:d54623194236 | 81 | * @{ |
| mbed_official | 497:d54623194236 | 82 | */ |
| mbed_official | 497:d54623194236 | 83 | |
| mbed_official | 497:d54623194236 | 84 | /** @addtogroup stm32f1xx_system |
| mbed_official | 497:d54623194236 | 85 | * @{ |
| mbed_official | 497:d54623194236 | 86 | */ |
| mbed_official | 497:d54623194236 | 87 | |
| mbed_official | 497:d54623194236 | 88 | /** @addtogroup STM32F1xx_System_Private_Includes |
| mbed_official | 497:d54623194236 | 89 | * @{ |
| mbed_official | 497:d54623194236 | 90 | */ |
| mbed_official | 497:d54623194236 | 91 | |
| mbed_official | 497:d54623194236 | 92 | #include "stm32f1xx.h" |
| mbed_official | 497:d54623194236 | 93 | #include "hal_tick.h" |
| mbed_official | 497:d54623194236 | 94 | |
| mbed_official | 497:d54623194236 | 95 | /** |
| mbed_official | 497:d54623194236 | 96 | * @} |
| mbed_official | 497:d54623194236 | 97 | */ |
| mbed_official | 497:d54623194236 | 98 | |
| mbed_official | 497:d54623194236 | 99 | /** @addtogroup STM32F1xx_System_Private_TypesDefinitions |
| mbed_official | 497:d54623194236 | 100 | * @{ |
| mbed_official | 497:d54623194236 | 101 | */ |
| mbed_official | 497:d54623194236 | 102 | |
| mbed_official | 497:d54623194236 | 103 | /** |
| mbed_official | 497:d54623194236 | 104 | * @} |
| mbed_official | 497:d54623194236 | 105 | */ |
| mbed_official | 497:d54623194236 | 106 | |
| mbed_official | 497:d54623194236 | 107 | /** @addtogroup STM32F1xx_System_Private_Defines |
| mbed_official | 497:d54623194236 | 108 | * @{ |
| mbed_official | 497:d54623194236 | 109 | */ |
| mbed_official | 497:d54623194236 | 110 | |
| mbed_official | 497:d54623194236 | 111 | #if !defined (HSE_VALUE) |
| mbed_official | 497:d54623194236 | 112 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. |
| mbed_official | 497:d54623194236 | 113 | This value can be provided and adapted by the user application. */ |
| mbed_official | 497:d54623194236 | 114 | #endif /* HSE_VALUE */ |
| mbed_official | 497:d54623194236 | 115 | |
| mbed_official | 497:d54623194236 | 116 | #if !defined (HSI_VALUE) |
| mbed_official | 497:d54623194236 | 117 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. |
| mbed_official | 497:d54623194236 | 118 | This value can be provided and adapted by the user application. */ |
| mbed_official | 497:d54623194236 | 119 | #endif /* HSI_VALUE */ |
| mbed_official | 497:d54623194236 | 120 | |
| mbed_official | 497:d54623194236 | 121 | /*!< Uncomment the following line if you need to use external SRAM */ |
| mbed_official | 497:d54623194236 | 122 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| mbed_official | 497:d54623194236 | 123 | /* #define DATA_IN_ExtSRAM */ |
| mbed_official | 497:d54623194236 | 124 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
| mbed_official | 497:d54623194236 | 125 | |
| mbed_official | 497:d54623194236 | 126 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| mbed_official | 497:d54623194236 | 127 | Internal SRAM. */ |
| mbed_official | 497:d54623194236 | 128 | /* #define VECT_TAB_SRAM */ |
| mbed_official | 497:d54623194236 | 129 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
| mbed_official | 497:d54623194236 | 130 | This value must be a multiple of 0x200. */ |
| mbed_official | 497:d54623194236 | 131 | |
| mbed_official | 497:d54623194236 | 132 | |
| mbed_official | 497:d54623194236 | 133 | /** |
| mbed_official | 497:d54623194236 | 134 | * @} |
| mbed_official | 497:d54623194236 | 135 | */ |
| mbed_official | 497:d54623194236 | 136 | |
| mbed_official | 497:d54623194236 | 137 | /** @addtogroup STM32F1xx_System_Private_Macros |
| mbed_official | 497:d54623194236 | 138 | * @{ |
| mbed_official | 497:d54623194236 | 139 | */ |
| mbed_official | 497:d54623194236 | 140 | |
| mbed_official | 497:d54623194236 | 141 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| mbed_official | 497:d54623194236 | 142 | #define USE_PLL_HSE_EXTC (0) /* Use external clock */ |
| mbed_official | 497:d54623194236 | 143 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
| mbed_official | 497:d54623194236 | 144 | |
| mbed_official | 497:d54623194236 | 145 | /** |
| mbed_official | 497:d54623194236 | 146 | * @} |
| mbed_official | 497:d54623194236 | 147 | */ |
| mbed_official | 497:d54623194236 | 148 | |
| mbed_official | 497:d54623194236 | 149 | /** @addtogroup STM32F1xx_System_Private_Variables |
| mbed_official | 497:d54623194236 | 150 | * @{ |
| mbed_official | 497:d54623194236 | 151 | */ |
| mbed_official | 497:d54623194236 | 152 | |
| mbed_official | 497:d54623194236 | 153 | /******************************************************************************* |
| mbed_official | 497:d54623194236 | 154 | * Clock Definitions |
| mbed_official | 497:d54623194236 | 155 | *******************************************************************************/ |
| mbed_official | 497:d54623194236 | 156 | #if defined(STM32F100xB) ||defined(STM32F100xE) |
| mbed_official | 497:d54623194236 | 157 | uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */ |
| mbed_official | 497:d54623194236 | 158 | #else /*!< HSI Selected as System Clock source */ |
| mbed_official | 497:d54623194236 | 159 | uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ |
| mbed_official | 497:d54623194236 | 160 | #endif |
| mbed_official | 497:d54623194236 | 161 | |
| mbed_official | 497:d54623194236 | 162 | __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| mbed_official | 497:d54623194236 | 163 | /** |
| mbed_official | 497:d54623194236 | 164 | * @} |
| mbed_official | 497:d54623194236 | 165 | */ |
| mbed_official | 497:d54623194236 | 166 | |
| mbed_official | 497:d54623194236 | 167 | /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes |
| mbed_official | 497:d54623194236 | 168 | * @{ |
| mbed_official | 497:d54623194236 | 169 | */ |
| mbed_official | 497:d54623194236 | 170 | |
| mbed_official | 497:d54623194236 | 171 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| mbed_official | 497:d54623194236 | 172 | #ifdef DATA_IN_ExtSRAM |
| mbed_official | 497:d54623194236 | 173 | static void SystemInit_ExtMemCtl(void); |
| mbed_official | 497:d54623194236 | 174 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 497:d54623194236 | 175 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
| mbed_official | 497:d54623194236 | 176 | |
| mbed_official | 497:d54623194236 | 177 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 497:d54623194236 | 178 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| mbed_official | 497:d54623194236 | 179 | #endif |
| mbed_official | 497:d54623194236 | 180 | |
| mbed_official | 497:d54623194236 | 181 | uint8_t SetSysClock_PLL_HSI(void); |
| mbed_official | 497:d54623194236 | 182 | |
| mbed_official | 497:d54623194236 | 183 | /** |
| mbed_official | 497:d54623194236 | 184 | * @} |
| mbed_official | 497:d54623194236 | 185 | */ |
| mbed_official | 497:d54623194236 | 186 | |
| mbed_official | 497:d54623194236 | 187 | /** @addtogroup STM32F1xx_System_Private_Functions |
| mbed_official | 497:d54623194236 | 188 | * @{ |
| mbed_official | 497:d54623194236 | 189 | */ |
| mbed_official | 497:d54623194236 | 190 | |
| mbed_official | 497:d54623194236 | 191 | /** |
| mbed_official | 497:d54623194236 | 192 | * @brief Setup the microcontroller system |
| mbed_official | 497:d54623194236 | 193 | * Initialize the Embedded Flash Interface, the PLL and update the |
| mbed_official | 497:d54623194236 | 194 | * SystemCoreClock variable. |
| mbed_official | 497:d54623194236 | 195 | * @note This function should be used only after reset. |
| mbed_official | 497:d54623194236 | 196 | * @param None |
| mbed_official | 497:d54623194236 | 197 | * @retval None |
| mbed_official | 497:d54623194236 | 198 | */ |
| mbed_official | 497:d54623194236 | 199 | void SystemInit (void) |
| mbed_official | 497:d54623194236 | 200 | { |
| mbed_official | 497:d54623194236 | 201 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ |
| mbed_official | 497:d54623194236 | 202 | /* Set HSION bit */ |
| mbed_official | 497:d54623194236 | 203 | RCC->CR |= (uint32_t)0x00000001; |
| mbed_official | 497:d54623194236 | 204 | |
| mbed_official | 497:d54623194236 | 205 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ |
| mbed_official | 497:d54623194236 | 206 | #if !defined(STM32F105xC) && !defined(STM32F107xC) |
| mbed_official | 497:d54623194236 | 207 | RCC->CFGR &= (uint32_t)0xF8FF0000; |
| mbed_official | 497:d54623194236 | 208 | #else |
| mbed_official | 497:d54623194236 | 209 | RCC->CFGR &= (uint32_t)0xF0FF0000; |
| mbed_official | 497:d54623194236 | 210 | #endif /* STM32F105xC */ |
| mbed_official | 497:d54623194236 | 211 | |
| mbed_official | 497:d54623194236 | 212 | /* Reset HSEON, CSSON and PLLON bits */ |
| mbed_official | 497:d54623194236 | 213 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| mbed_official | 497:d54623194236 | 214 | |
| mbed_official | 497:d54623194236 | 215 | /* Reset HSEBYP bit */ |
| mbed_official | 497:d54623194236 | 216 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| mbed_official | 497:d54623194236 | 217 | |
| mbed_official | 497:d54623194236 | 218 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ |
| mbed_official | 497:d54623194236 | 219 | RCC->CFGR &= (uint32_t)0xFF80FFFF; |
| mbed_official | 497:d54623194236 | 220 | |
| mbed_official | 497:d54623194236 | 221 | #if defined(STM32F105xC) || defined(STM32F107xC) |
| mbed_official | 497:d54623194236 | 222 | /* Reset PLL2ON and PLL3ON bits */ |
| mbed_official | 497:d54623194236 | 223 | RCC->CR &= (uint32_t)0xEBFFFFFF; |
| mbed_official | 497:d54623194236 | 224 | |
| mbed_official | 497:d54623194236 | 225 | /* Disable all interrupts and clear pending bits */ |
| mbed_official | 497:d54623194236 | 226 | RCC->CIR = 0x00FF0000; |
| mbed_official | 497:d54623194236 | 227 | |
| mbed_official | 497:d54623194236 | 228 | /* Reset CFGR2 register */ |
| mbed_official | 497:d54623194236 | 229 | RCC->CFGR2 = 0x00000000; |
| mbed_official | 497:d54623194236 | 230 | #elif defined(STM32F100xB) || defined(STM32F100xE) |
| mbed_official | 497:d54623194236 | 231 | /* Disable all interrupts and clear pending bits */ |
| mbed_official | 497:d54623194236 | 232 | RCC->CIR = 0x009F0000; |
| mbed_official | 497:d54623194236 | 233 | |
| mbed_official | 497:d54623194236 | 234 | /* Reset CFGR2 register */ |
| mbed_official | 497:d54623194236 | 235 | RCC->CFGR2 = 0x00000000; |
| mbed_official | 497:d54623194236 | 236 | #else |
| mbed_official | 497:d54623194236 | 237 | /* Disable all interrupts and clear pending bits */ |
| mbed_official | 497:d54623194236 | 238 | RCC->CIR = 0x009F0000; |
| mbed_official | 497:d54623194236 | 239 | #endif /* STM32F105xC */ |
| mbed_official | 497:d54623194236 | 240 | |
| mbed_official | 497:d54623194236 | 241 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| mbed_official | 497:d54623194236 | 242 | #ifdef DATA_IN_ExtSRAM |
| mbed_official | 497:d54623194236 | 243 | SystemInit_ExtMemCtl(); |
| mbed_official | 497:d54623194236 | 244 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 497:d54623194236 | 245 | #endif |
| mbed_official | 497:d54623194236 | 246 | |
| mbed_official | 497:d54623194236 | 247 | #ifdef VECT_TAB_SRAM |
| mbed_official | 497:d54623194236 | 248 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
| mbed_official | 497:d54623194236 | 249 | #else |
| mbed_official | 497:d54623194236 | 250 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ |
| mbed_official | 497:d54623194236 | 251 | #endif |
| mbed_official | 497:d54623194236 | 252 | |
| mbed_official | 497:d54623194236 | 253 | /* Configure the Cube driver */ |
| mbed_official | 497:d54623194236 | 254 | SystemCoreClock = 8000000; // At this stage the HSI is used as system clock |
| mbed_official | 497:d54623194236 | 255 | HAL_Init(); |
| mbed_official | 497:d54623194236 | 256 | |
| mbed_official | 497:d54623194236 | 257 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 497:d54623194236 | 258 | AHB/APBx prescalers and Flash settings */ |
| mbed_official | 497:d54623194236 | 259 | SetSysClock(); |
| mbed_official | 497:d54623194236 | 260 | |
| mbed_official | 497:d54623194236 | 261 | /* Reset the timer to avoid issues after the RAM initialization */ |
| mbed_official | 497:d54623194236 | 262 | TIM_MST_RESET_ON; |
| mbed_official | 497:d54623194236 | 263 | TIM_MST_RESET_OFF; |
| mbed_official | 497:d54623194236 | 264 | } |
| mbed_official | 497:d54623194236 | 265 | |
| mbed_official | 497:d54623194236 | 266 | /** |
| mbed_official | 497:d54623194236 | 267 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| mbed_official | 497:d54623194236 | 268 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| mbed_official | 497:d54623194236 | 269 | * be used by the user application to setup the SysTick timer or configure |
| mbed_official | 497:d54623194236 | 270 | * other parameters. |
| mbed_official | 497:d54623194236 | 271 | * |
| mbed_official | 497:d54623194236 | 272 | * @note Each time the core clock (HCLK) changes, this function must be called |
| mbed_official | 497:d54623194236 | 273 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| mbed_official | 497:d54623194236 | 274 | * based on this variable will be incorrect. |
| mbed_official | 497:d54623194236 | 275 | * |
| mbed_official | 497:d54623194236 | 276 | * @note - The system frequency computed by this function is not the real |
| mbed_official | 497:d54623194236 | 277 | * frequency in the chip. It is calculated based on the predefined |
| mbed_official | 497:d54623194236 | 278 | * constant and the selected clock source: |
| mbed_official | 497:d54623194236 | 279 | * |
| mbed_official | 497:d54623194236 | 280 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| mbed_official | 497:d54623194236 | 281 | * |
| mbed_official | 497:d54623194236 | 282 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 497:d54623194236 | 283 | * |
| mbed_official | 497:d54623194236 | 284 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 497:d54623194236 | 285 | * or HSI_VALUE(*) multiplied by the PLL factors. |
| mbed_official | 497:d54623194236 | 286 | * |
| mbed_official | 497:d54623194236 | 287 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value |
| mbed_official | 497:d54623194236 | 288 | * 8 MHz) but the real value may vary depending on the variations |
| mbed_official | 497:d54623194236 | 289 | * in voltage and temperature. |
| mbed_official | 497:d54623194236 | 290 | * |
| mbed_official | 497:d54623194236 | 291 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value |
| mbed_official | 497:d54623194236 | 292 | * 8 MHz or 25 MHz, depending on the product used), user has to ensure |
| mbed_official | 497:d54623194236 | 293 | * that HSE_VALUE is same as the real frequency of the crystal used. |
| mbed_official | 497:d54623194236 | 294 | * Otherwise, this function may have wrong result. |
| mbed_official | 497:d54623194236 | 295 | * |
| mbed_official | 497:d54623194236 | 296 | * - The result of this function could be not correct when using fractional |
| mbed_official | 497:d54623194236 | 297 | * value for HSE crystal. |
| mbed_official | 497:d54623194236 | 298 | * @param None |
| mbed_official | 497:d54623194236 | 299 | * @retval None |
| mbed_official | 497:d54623194236 | 300 | */ |
| mbed_official | 497:d54623194236 | 301 | void SystemCoreClockUpdate (void) |
| mbed_official | 497:d54623194236 | 302 | { |
| mbed_official | 497:d54623194236 | 303 | uint32_t tmp = 0, pllmull = 0, pllsource = 0; |
| mbed_official | 497:d54623194236 | 304 | |
| mbed_official | 497:d54623194236 | 305 | #if defined(STM32F105xC) || defined(STM32F107xC) |
| mbed_official | 497:d54623194236 | 306 | uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; |
| mbed_official | 497:d54623194236 | 307 | #endif /* STM32F105xC */ |
| mbed_official | 497:d54623194236 | 308 | |
| mbed_official | 497:d54623194236 | 309 | #if defined(STM32F100xB) || defined(STM32F100xE) |
| mbed_official | 497:d54623194236 | 310 | uint32_t prediv1factor = 0; |
| mbed_official | 497:d54623194236 | 311 | #endif /* STM32F100xB or STM32F100xE */ |
| mbed_official | 497:d54623194236 | 312 | |
| mbed_official | 497:d54623194236 | 313 | /* Get SYSCLK source -------------------------------------------------------*/ |
| mbed_official | 497:d54623194236 | 314 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| mbed_official | 497:d54623194236 | 315 | |
| mbed_official | 497:d54623194236 | 316 | switch (tmp) |
| mbed_official | 497:d54623194236 | 317 | { |
| mbed_official | 497:d54623194236 | 318 | case 0x00: /* HSI used as system clock */ |
| mbed_official | 497:d54623194236 | 319 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 497:d54623194236 | 320 | break; |
| mbed_official | 497:d54623194236 | 321 | case 0x04: /* HSE used as system clock */ |
| mbed_official | 497:d54623194236 | 322 | SystemCoreClock = HSE_VALUE; |
| mbed_official | 497:d54623194236 | 323 | break; |
| mbed_official | 497:d54623194236 | 324 | case 0x08: /* PLL used as system clock */ |
| mbed_official | 497:d54623194236 | 325 | |
| mbed_official | 497:d54623194236 | 326 | /* Get PLL clock source and multiplication factor ----------------------*/ |
| mbed_official | 497:d54623194236 | 327 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; |
| mbed_official | 497:d54623194236 | 328 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
| mbed_official | 497:d54623194236 | 329 | |
| mbed_official | 497:d54623194236 | 330 | #if !defined(STM32F105xC) && !defined(STM32F107xC) |
| mbed_official | 497:d54623194236 | 331 | pllmull = ( pllmull >> 18) + 2; |
| mbed_official | 497:d54623194236 | 332 | |
| mbed_official | 497:d54623194236 | 333 | if (pllsource == 0x00) |
| mbed_official | 497:d54623194236 | 334 | { |
| mbed_official | 497:d54623194236 | 335 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
| mbed_official | 497:d54623194236 | 336 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
| mbed_official | 497:d54623194236 | 337 | } |
| mbed_official | 497:d54623194236 | 338 | else |
| mbed_official | 497:d54623194236 | 339 | { |
| mbed_official | 497:d54623194236 | 340 | #if defined(STM32F100xB) || defined(STM32F100xE) |
| mbed_official | 497:d54623194236 | 341 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
| mbed_official | 497:d54623194236 | 342 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
| mbed_official | 497:d54623194236 | 343 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
| mbed_official | 497:d54623194236 | 344 | #else |
| mbed_official | 497:d54623194236 | 345 | /* HSE selected as PLL clock entry */ |
| mbed_official | 497:d54623194236 | 346 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) |
| mbed_official | 497:d54623194236 | 347 | {/* HSE oscillator clock divided by 2 */ |
| mbed_official | 497:d54623194236 | 348 | SystemCoreClock = (HSE_VALUE >> 1) * pllmull; |
| mbed_official | 497:d54623194236 | 349 | } |
| mbed_official | 497:d54623194236 | 350 | else |
| mbed_official | 497:d54623194236 | 351 | { |
| mbed_official | 497:d54623194236 | 352 | SystemCoreClock = HSE_VALUE * pllmull; |
| mbed_official | 497:d54623194236 | 353 | } |
| mbed_official | 497:d54623194236 | 354 | #endif |
| mbed_official | 497:d54623194236 | 355 | } |
| mbed_official | 497:d54623194236 | 356 | #else |
| mbed_official | 497:d54623194236 | 357 | pllmull = pllmull >> 18; |
| mbed_official | 497:d54623194236 | 358 | |
| mbed_official | 497:d54623194236 | 359 | if (pllmull != 0x0D) |
| mbed_official | 497:d54623194236 | 360 | { |
| mbed_official | 497:d54623194236 | 361 | pllmull += 2; |
| mbed_official | 497:d54623194236 | 362 | } |
| mbed_official | 497:d54623194236 | 363 | else |
| mbed_official | 497:d54623194236 | 364 | { /* PLL multiplication factor = PLL input clock * 6.5 */ |
| mbed_official | 497:d54623194236 | 365 | pllmull = 13 / 2; |
| mbed_official | 497:d54623194236 | 366 | } |
| mbed_official | 497:d54623194236 | 367 | |
| mbed_official | 497:d54623194236 | 368 | if (pllsource == 0x00) |
| mbed_official | 497:d54623194236 | 369 | { |
| mbed_official | 497:d54623194236 | 370 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
| mbed_official | 497:d54623194236 | 371 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
| mbed_official | 497:d54623194236 | 372 | } |
| mbed_official | 497:d54623194236 | 373 | else |
| mbed_official | 497:d54623194236 | 374 | {/* PREDIV1 selected as PLL clock entry */ |
| mbed_official | 497:d54623194236 | 375 | |
| mbed_official | 497:d54623194236 | 376 | /* Get PREDIV1 clock source and division factor */ |
| mbed_official | 497:d54623194236 | 377 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; |
| mbed_official | 497:d54623194236 | 378 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
| mbed_official | 497:d54623194236 | 379 | |
| mbed_official | 497:d54623194236 | 380 | if (prediv1source == 0) |
| mbed_official | 497:d54623194236 | 381 | { |
| mbed_official | 497:d54623194236 | 382 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
| mbed_official | 497:d54623194236 | 383 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
| mbed_official | 497:d54623194236 | 384 | } |
| mbed_official | 497:d54623194236 | 385 | else |
| mbed_official | 497:d54623194236 | 386 | {/* PLL2 clock selected as PREDIV1 clock entry */ |
| mbed_official | 497:d54623194236 | 387 | |
| mbed_official | 497:d54623194236 | 388 | /* Get PREDIV2 division factor and PLL2 multiplication factor */ |
| mbed_official | 497:d54623194236 | 389 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; |
| mbed_official | 497:d54623194236 | 390 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; |
| mbed_official | 497:d54623194236 | 391 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; |
| mbed_official | 497:d54623194236 | 392 | } |
| mbed_official | 497:d54623194236 | 393 | } |
| mbed_official | 497:d54623194236 | 394 | #endif /* STM32F105xC */ |
| mbed_official | 497:d54623194236 | 395 | break; |
| mbed_official | 497:d54623194236 | 396 | |
| mbed_official | 497:d54623194236 | 397 | default: |
| mbed_official | 497:d54623194236 | 398 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 497:d54623194236 | 399 | break; |
| mbed_official | 497:d54623194236 | 400 | } |
| mbed_official | 497:d54623194236 | 401 | |
| mbed_official | 497:d54623194236 | 402 | /* Compute HCLK clock frequency ----------------*/ |
| mbed_official | 497:d54623194236 | 403 | /* Get HCLK prescaler */ |
| mbed_official | 497:d54623194236 | 404 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| mbed_official | 497:d54623194236 | 405 | /* HCLK clock frequency */ |
| mbed_official | 497:d54623194236 | 406 | SystemCoreClock >>= tmp; |
| mbed_official | 497:d54623194236 | 407 | } |
| mbed_official | 497:d54623194236 | 408 | |
| mbed_official | 497:d54623194236 | 409 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| mbed_official | 497:d54623194236 | 410 | /** |
| mbed_official | 497:d54623194236 | 411 | * @brief Setup the external memory controller. Called in startup_stm32f1xx.s |
| mbed_official | 497:d54623194236 | 412 | * before jump to __main |
| mbed_official | 497:d54623194236 | 413 | * @param None |
| mbed_official | 497:d54623194236 | 414 | * @retval None |
| mbed_official | 497:d54623194236 | 415 | */ |
| mbed_official | 497:d54623194236 | 416 | #ifdef DATA_IN_ExtSRAM |
| mbed_official | 497:d54623194236 | 417 | /** |
| mbed_official | 497:d54623194236 | 418 | * @brief Setup the external memory controller. |
| mbed_official | 497:d54623194236 | 419 | * Called in startup_stm32f1xx_xx.s/.c before jump to main. |
| mbed_official | 497:d54623194236 | 420 | * This function configures the external SRAM mounted on STM3210E-EVAL |
| mbed_official | 497:d54623194236 | 421 | * board (STM32 High density devices). This SRAM will be used as program |
| mbed_official | 497:d54623194236 | 422 | * data memory (including heap and stack). |
| mbed_official | 497:d54623194236 | 423 | * @param None |
| mbed_official | 497:d54623194236 | 424 | * @retval None |
| mbed_official | 497:d54623194236 | 425 | */ |
| mbed_official | 497:d54623194236 | 426 | void SystemInit_ExtMemCtl(void) |
| mbed_official | 497:d54623194236 | 427 | { |
| mbed_official | 497:d54623194236 | 428 | __IO uint32_t tmpreg; |
| mbed_official | 497:d54623194236 | 429 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is |
| mbed_official | 497:d54623194236 | 430 | required, then adjust the Register Addresses */ |
| mbed_official | 497:d54623194236 | 431 | |
| mbed_official | 497:d54623194236 | 432 | /* Enable FSMC clock */ |
| mbed_official | 497:d54623194236 | 433 | RCC->AHBENR = 0x00000114; |
| mbed_official | 497:d54623194236 | 434 | |
| mbed_official | 497:d54623194236 | 435 | /* Delay after an RCC peripheral clock enabling */ |
| mbed_official | 497:d54623194236 | 436 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); |
| mbed_official | 497:d54623194236 | 437 | |
| mbed_official | 497:d54623194236 | 438 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ |
| mbed_official | 497:d54623194236 | 439 | RCC->APB2ENR = 0x000001E0; |
| mbed_official | 497:d54623194236 | 440 | |
| mbed_official | 497:d54623194236 | 441 | /* Delay after an RCC peripheral clock enabling */ |
| mbed_official | 497:d54623194236 | 442 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); |
| mbed_official | 497:d54623194236 | 443 | |
| mbed_official | 497:d54623194236 | 444 | (void)(tmpreg); |
| mbed_official | 497:d54623194236 | 445 | |
| mbed_official | 497:d54623194236 | 446 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ |
| mbed_official | 497:d54623194236 | 447 | /*---------------- SRAM Address lines configuration -------------------------*/ |
| mbed_official | 497:d54623194236 | 448 | /*---------------- NOE and NWE configuration --------------------------------*/ |
| mbed_official | 497:d54623194236 | 449 | /*---------------- NE3 configuration ----------------------------------------*/ |
| mbed_official | 497:d54623194236 | 450 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/ |
| mbed_official | 497:d54623194236 | 451 | |
| mbed_official | 497:d54623194236 | 452 | GPIOD->CRL = 0x44BB44BB; |
| mbed_official | 497:d54623194236 | 453 | GPIOD->CRH = 0xBBBBBBBB; |
| mbed_official | 497:d54623194236 | 454 | |
| mbed_official | 497:d54623194236 | 455 | GPIOE->CRL = 0xB44444BB; |
| mbed_official | 497:d54623194236 | 456 | GPIOE->CRH = 0xBBBBBBBB; |
| mbed_official | 497:d54623194236 | 457 | |
| mbed_official | 497:d54623194236 | 458 | GPIOF->CRL = 0x44BBBBBB; |
| mbed_official | 497:d54623194236 | 459 | GPIOF->CRH = 0xBBBB4444; |
| mbed_official | 497:d54623194236 | 460 | |
| mbed_official | 497:d54623194236 | 461 | GPIOG->CRL = 0x44BBBBBB; |
| mbed_official | 497:d54623194236 | 462 | GPIOG->CRH = 0x444B4B44; |
| mbed_official | 497:d54623194236 | 463 | |
| mbed_official | 497:d54623194236 | 464 | /*---------------- FSMC Configuration ---------------------------------------*/ |
| mbed_official | 497:d54623194236 | 465 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ |
| mbed_official | 497:d54623194236 | 466 | |
| mbed_official | 497:d54623194236 | 467 | FSMC_Bank1->BTCR[4] = 0x00001091; |
| mbed_official | 497:d54623194236 | 468 | FSMC_Bank1->BTCR[5] = 0x00110212; |
| mbed_official | 497:d54623194236 | 469 | } |
| mbed_official | 497:d54623194236 | 470 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 497:d54623194236 | 471 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
| mbed_official | 497:d54623194236 | 472 | |
| mbed_official | 497:d54623194236 | 473 | /** |
| mbed_official | 497:d54623194236 | 474 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 497:d54623194236 | 475 | * AHB/APBx prescalers and Flash settings |
| mbed_official | 497:d54623194236 | 476 | * @note This function should be called only once the RCC clock configuration |
| mbed_official | 497:d54623194236 | 477 | * is reset to the default reset state (done in SystemInit() function). |
| mbed_official | 497:d54623194236 | 478 | * @param None |
| mbed_official | 497:d54623194236 | 479 | * @retval None |
| mbed_official | 497:d54623194236 | 480 | */ |
| mbed_official | 497:d54623194236 | 481 | void SetSysClock(void) |
| mbed_official | 497:d54623194236 | 482 | { |
| mbed_official | 497:d54623194236 | 483 | /* 1- Try to start with HSE and external clock */ |
| mbed_official | 497:d54623194236 | 484 | #if USE_PLL_HSE_EXTC != 0 |
| mbed_official | 497:d54623194236 | 485 | if (SetSysClock_PLL_HSE(1) == 0) |
| mbed_official | 497:d54623194236 | 486 | #endif |
| mbed_official | 497:d54623194236 | 487 | { |
| mbed_official | 497:d54623194236 | 488 | /* 2- If fail try to start with HSE and external xtal */ |
| mbed_official | 497:d54623194236 | 489 | #if USE_PLL_HSE_XTAL != 0 |
| mbed_official | 497:d54623194236 | 490 | if (SetSysClock_PLL_HSE(0) == 0) |
| mbed_official | 497:d54623194236 | 491 | #endif |
| mbed_official | 497:d54623194236 | 492 | { |
| mbed_official | 497:d54623194236 | 493 | /* 3- If fail start with HSI clock */ |
| mbed_official | 497:d54623194236 | 494 | if (SetSysClock_PLL_HSI() == 0) |
| mbed_official | 497:d54623194236 | 495 | { |
| mbed_official | 497:d54623194236 | 496 | while(1) |
| mbed_official | 497:d54623194236 | 497 | { |
| mbed_official | 497:d54623194236 | 498 | // [TODO] Put something here to tell the user that a problem occured... |
| mbed_official | 497:d54623194236 | 499 | } |
| mbed_official | 497:d54623194236 | 500 | } |
| mbed_official | 497:d54623194236 | 501 | } |
| mbed_official | 497:d54623194236 | 502 | } |
| mbed_official | 497:d54623194236 | 503 | |
| mbed_official | 497:d54623194236 | 504 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 497:d54623194236 | 505 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 24 MHz |
| mbed_official | 497:d54623194236 | 506 | } |
| mbed_official | 497:d54623194236 | 507 | |
| mbed_official | 497:d54623194236 | 508 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 497:d54623194236 | 509 | /******************************************************************************/ |
| mbed_official | 497:d54623194236 | 510 | /* PLL (clocked by HSE) used as System clock source */ |
| mbed_official | 497:d54623194236 | 511 | /******************************************************************************/ |
| mbed_official | 497:d54623194236 | 512 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| mbed_official | 497:d54623194236 | 513 | { |
| mbed_official | 497:d54623194236 | 514 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 497:d54623194236 | 515 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 497:d54623194236 | 516 | |
| mbed_official | 497:d54623194236 | 517 | /* Enable HSE oscillator and activate PLL with HSE as source */ |
| mbed_official | 497:d54623194236 | 518 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 497:d54623194236 | 519 | if (bypass == 0) |
| mbed_official | 497:d54623194236 | 520 | { |
| mbed_official | 497:d54623194236 | 521 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
| mbed_official | 497:d54623194236 | 522 | } |
| mbed_official | 497:d54623194236 | 523 | else |
| mbed_official | 497:d54623194236 | 524 | { |
| mbed_official | 497:d54623194236 | 525 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
| mbed_official | 497:d54623194236 | 526 | } |
| mbed_official | 497:d54623194236 | 527 | RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2; |
| mbed_official | 497:d54623194236 | 528 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 497:d54623194236 | 529 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| mbed_official | 497:d54623194236 | 530 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (4 MHz * 6) |
| mbed_official | 497:d54623194236 | 531 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| mbed_official | 497:d54623194236 | 532 | { |
| mbed_official | 497:d54623194236 | 533 | return 0; // FAIL |
| mbed_official | 497:d54623194236 | 534 | } |
| mbed_official | 497:d54623194236 | 535 | |
| mbed_official | 497:d54623194236 | 536 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| mbed_official | 497:d54623194236 | 537 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| mbed_official | 497:d54623194236 | 538 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz |
| mbed_official | 497:d54623194236 | 539 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz |
| mbed_official | 497:d54623194236 | 540 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz |
| mbed_official | 497:d54623194236 | 541 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz |
| mbed_official | 497:d54623194236 | 542 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) |
| mbed_official | 497:d54623194236 | 543 | { |
| mbed_official | 497:d54623194236 | 544 | return 0; // FAIL |
| mbed_official | 497:d54623194236 | 545 | } |
| mbed_official | 497:d54623194236 | 546 | |
| mbed_official | 497:d54623194236 | 547 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 497:d54623194236 | 548 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
| mbed_official | 497:d54623194236 | 549 | |
| mbed_official | 497:d54623194236 | 550 | return 1; // OK |
| mbed_official | 497:d54623194236 | 551 | } |
| mbed_official | 497:d54623194236 | 552 | #endif |
| mbed_official | 497:d54623194236 | 553 | |
| mbed_official | 497:d54623194236 | 554 | /******************************************************************************/ |
| mbed_official | 497:d54623194236 | 555 | /* PLL (clocked by HSI) used as System clock source */ |
| mbed_official | 497:d54623194236 | 556 | /******************************************************************************/ |
| mbed_official | 497:d54623194236 | 557 | uint8_t SetSysClock_PLL_HSI(void) |
| mbed_official | 497:d54623194236 | 558 | { |
| mbed_official | 497:d54623194236 | 559 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 497:d54623194236 | 560 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 497:d54623194236 | 561 | |
| mbed_official | 497:d54623194236 | 562 | /* Enable HSI oscillator and activate PLL with HSI as source */ |
| mbed_official | 497:d54623194236 | 563 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 497:d54623194236 | 564 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| mbed_official | 497:d54623194236 | 565 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
| mbed_official | 497:d54623194236 | 566 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
| mbed_official | 497:d54623194236 | 567 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 497:d54623194236 | 568 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; |
| mbed_official | 497:d54623194236 | 569 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (8 MHz/2 * 6) |
| mbed_official | 497:d54623194236 | 570 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| mbed_official | 497:d54623194236 | 571 | { |
| mbed_official | 497:d54623194236 | 572 | return 0; // FAIL |
| mbed_official | 497:d54623194236 | 573 | } |
| mbed_official | 497:d54623194236 | 574 | |
| mbed_official | 497:d54623194236 | 575 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| mbed_official | 497:d54623194236 | 576 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| mbed_official | 497:d54623194236 | 577 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz |
| mbed_official | 497:d54623194236 | 578 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz |
| mbed_official | 497:d54623194236 | 579 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz |
| mbed_official | 497:d54623194236 | 580 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz |
| mbed_official | 497:d54623194236 | 581 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) |
| mbed_official | 497:d54623194236 | 582 | { |
| mbed_official | 497:d54623194236 | 583 | return 0; // FAIL |
| mbed_official | 497:d54623194236 | 584 | } |
| mbed_official | 497:d54623194236 | 585 | |
| mbed_official | 497:d54623194236 | 586 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 497:d54623194236 | 587 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz |
| mbed_official | 497:d54623194236 | 588 | |
| mbed_official | 497:d54623194236 | 589 | return 1; // OK |
| mbed_official | 497:d54623194236 | 590 | } |
| mbed_official | 497:d54623194236 | 591 | |
| mbed_official | 497:d54623194236 | 592 | /** |
| mbed_official | 497:d54623194236 | 593 | * @} |
| mbed_official | 497:d54623194236 | 594 | */ |
| mbed_official | 497:d54623194236 | 595 | |
| mbed_official | 497:d54623194236 | 596 | /** |
| mbed_official | 497:d54623194236 | 597 | * @} |
| mbed_official | 497:d54623194236 | 598 | */ |
| mbed_official | 497:d54623194236 | 599 | |
| mbed_official | 497:d54623194236 | 600 | /** |
| mbed_official | 497:d54623194236 | 601 | * @} |
| mbed_official | 497:d54623194236 | 602 | */ |
| mbed_official | 497:d54623194236 | 603 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |