Renesas / mbed-src_GR-PEACH_rev_b

mbed library sources for GR-PEACH rev.B.

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h@497:d54623194236, 2015-03-26 (annotated)

Committer:
mbed_official
Date:
Thu Mar 26 13:45:12 2015 +0000
Revision:
497:d54623194236
Synchronized with git revision 0251fefac99a5b59beb481e845c6fbf48736bac6



Full URL: https://github.com/mbedmicro/mbed/commit/0251fefac99a5b59beb481e845c6fbf48736bac6/



DISCO_F100RB -Support HAL driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 497:d54623194236 1 /**
mbed_official 497:d54623194236 2 ******************************************************************************
mbed_official 497:d54623194236 3 * @file stm32f100xb.h
mbed_official 497:d54623194236 4 * @author MCD Application Team
mbed_official 497:d54623194236 5 * @version V4.0.0
mbed_official 497:d54623194236 6 * @date 16-December-2014
mbed_official 497:d54623194236 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
mbed_official 497:d54623194236 8 * This file contains all the peripheral register's definitions, bits
mbed_official 497:d54623194236 9 * definitions and memory mapping for STM32F1xx devices.
mbed_official 497:d54623194236 10 *
mbed_official 497:d54623194236 11 * This file contains:
mbed_official 497:d54623194236 12 * - Data structures and the address mapping for all peripherals
mbed_official 497:d54623194236 13 * - Peripheral's registers declarations and bits definition
mbed_official 497:d54623194236 14 * - Macros to access peripheral’s registers hardware
mbed_official 497:d54623194236 15 *
mbed_official 497:d54623194236 16 ******************************************************************************
mbed_official 497:d54623194236 17 * @attention
mbed_official 497:d54623194236 18 *
mbed_official 497:d54623194236 19 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 497:d54623194236 20 *
mbed_official 497:d54623194236 21 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 497:d54623194236 22 * are permitted provided that the following conditions are met:
mbed_official 497:d54623194236 23 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 497:d54623194236 24 * this list of conditions and the following disclaimer.
mbed_official 497:d54623194236 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 497:d54623194236 26 * this list of conditions and the following disclaimer in the documentation
mbed_official 497:d54623194236 27 * and/or other materials provided with the distribution.
mbed_official 497:d54623194236 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 497:d54623194236 29 * may be used to endorse or promote products derived from this software
mbed_official 497:d54623194236 30 * without specific prior written permission.
mbed_official 497:d54623194236 31 *
mbed_official 497:d54623194236 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 497:d54623194236 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 497:d54623194236 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 497:d54623194236 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 497:d54623194236 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 497:d54623194236 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 497:d54623194236 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 497:d54623194236 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 497:d54623194236 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 497:d54623194236 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 497:d54623194236 42 *
mbed_official 497:d54623194236 43 ******************************************************************************
mbed_official 497:d54623194236 44 */
mbed_official 497:d54623194236 45
mbed_official 497:d54623194236 46
mbed_official 497:d54623194236 47 /** @addtogroup CMSIS
mbed_official 497:d54623194236 48 * @{
mbed_official 497:d54623194236 49 */
mbed_official 497:d54623194236 50
mbed_official 497:d54623194236 51 /** @addtogroup stm32f100xb
mbed_official 497:d54623194236 52 * @{
mbed_official 497:d54623194236 53 */
mbed_official 497:d54623194236 54
mbed_official 497:d54623194236 55 #ifndef __STM32F100xB_H
mbed_official 497:d54623194236 56 #define __STM32F100xB_H
mbed_official 497:d54623194236 57
mbed_official 497:d54623194236 58 #ifdef __cplusplus
mbed_official 497:d54623194236 59 extern "C" {
mbed_official 497:d54623194236 60 #endif
mbed_official 497:d54623194236 61
mbed_official 497:d54623194236 62 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 497:d54623194236 63 * @{
mbed_official 497:d54623194236 64 */
mbed_official 497:d54623194236 65 /**
mbed_official 497:d54623194236 66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
mbed_official 497:d54623194236 67 */
mbed_official 497:d54623194236 68 #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
mbed_official 497:d54623194236 69 #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
mbed_official 497:d54623194236 70 #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
mbed_official 497:d54623194236 71 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 497:d54623194236 72
mbed_official 497:d54623194236 73 /**
mbed_official 497:d54623194236 74 * @}
mbed_official 497:d54623194236 75 */
mbed_official 497:d54623194236 76
mbed_official 497:d54623194236 77 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 497:d54623194236 78 * @{
mbed_official 497:d54623194236 79 */
mbed_official 497:d54623194236 80
mbed_official 497:d54623194236 81 /**
mbed_official 497:d54623194236 82 * @brief STM32F10x Interrupt Number Definition, according to the selected device
mbed_official 497:d54623194236 83 * in @ref Library_configuration_section
mbed_official 497:d54623194236 84 */
mbed_official 497:d54623194236 85
mbed_official 497:d54623194236 86 /*!< Interrupt Number Definition */
mbed_official 497:d54623194236 87 typedef enum
mbed_official 497:d54623194236 88 {
mbed_official 497:d54623194236 89 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
mbed_official 497:d54623194236 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 497:d54623194236 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
mbed_official 497:d54623194236 92 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
mbed_official 497:d54623194236 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
mbed_official 497:d54623194236 94 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
mbed_official 497:d54623194236 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
mbed_official 497:d54623194236 96 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
mbed_official 497:d54623194236 97 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
mbed_official 497:d54623194236 98
mbed_official 497:d54623194236 99 /****** STM32 specific Interrupt Numbers *********************************************************/
mbed_official 497:d54623194236 100 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 497:d54623194236 101 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 497:d54623194236 102 TAMPER_IRQn = 2, /*!< Tamper Interrupt */
mbed_official 497:d54623194236 103 RTC_IRQn = 3, /*!< RTC global Interrupt */
mbed_official 497:d54623194236 104 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 497:d54623194236 105 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 497:d54623194236 106 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 497:d54623194236 107 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 497:d54623194236 108 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 497:d54623194236 109 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 497:d54623194236 110 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 497:d54623194236 111 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
mbed_official 497:d54623194236 112 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
mbed_official 497:d54623194236 113 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
mbed_official 497:d54623194236 114 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
mbed_official 497:d54623194236 115 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
mbed_official 497:d54623194236 116 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
mbed_official 497:d54623194236 117 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
mbed_official 497:d54623194236 118 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
mbed_official 497:d54623194236 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 497:d54623194236 120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
mbed_official 497:d54623194236 121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
mbed_official 497:d54623194236 122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
mbed_official 497:d54623194236 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 497:d54623194236 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 497:d54623194236 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 497:d54623194236 126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 497:d54623194236 127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 497:d54623194236 128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 497:d54623194236 129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 497:d54623194236 130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 497:d54623194236 131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 497:d54623194236 132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 497:d54623194236 133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 497:d54623194236 134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 497:d54623194236 135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 497:d54623194236 136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 497:d54623194236 137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
mbed_official 497:d54623194236 138 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
mbed_official 497:d54623194236 139 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
mbed_official 497:d54623194236 140 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
mbed_official 497:d54623194236 141 } IRQn_Type;
mbed_official 497:d54623194236 142
mbed_official 497:d54623194236 143
mbed_official 497:d54623194236 144 /**
mbed_official 497:d54623194236 145 * @}
mbed_official 497:d54623194236 146 */
mbed_official 497:d54623194236 147
mbed_official 497:d54623194236 148 #include "core_cm3.h"
mbed_official 497:d54623194236 149 #include "system_stm32f1xx.h"
mbed_official 497:d54623194236 150 #include <stdint.h>
mbed_official 497:d54623194236 151
mbed_official 497:d54623194236 152 /** @addtogroup Peripheral_registers_structures
mbed_official 497:d54623194236 153 * @{
mbed_official 497:d54623194236 154 */
mbed_official 497:d54623194236 155
mbed_official 497:d54623194236 156 /**
mbed_official 497:d54623194236 157 * @brief Analog to Digital Converter
mbed_official 497:d54623194236 158 */
mbed_official 497:d54623194236 159
mbed_official 497:d54623194236 160 typedef struct
mbed_official 497:d54623194236 161 {
mbed_official 497:d54623194236 162 __IO uint32_t SR;
mbed_official 497:d54623194236 163 __IO uint32_t CR1;
mbed_official 497:d54623194236 164 __IO uint32_t CR2;
mbed_official 497:d54623194236 165 __IO uint32_t SMPR1;
mbed_official 497:d54623194236 166 __IO uint32_t SMPR2;
mbed_official 497:d54623194236 167 __IO uint32_t JOFR1;
mbed_official 497:d54623194236 168 __IO uint32_t JOFR2;
mbed_official 497:d54623194236 169 __IO uint32_t JOFR3;
mbed_official 497:d54623194236 170 __IO uint32_t JOFR4;
mbed_official 497:d54623194236 171 __IO uint32_t HTR;
mbed_official 497:d54623194236 172 __IO uint32_t LTR;
mbed_official 497:d54623194236 173 __IO uint32_t SQR1;
mbed_official 497:d54623194236 174 __IO uint32_t SQR2;
mbed_official 497:d54623194236 175 __IO uint32_t SQR3;
mbed_official 497:d54623194236 176 __IO uint32_t JSQR;
mbed_official 497:d54623194236 177 __IO uint32_t JDR1;
mbed_official 497:d54623194236 178 __IO uint32_t JDR2;
mbed_official 497:d54623194236 179 __IO uint32_t JDR3;
mbed_official 497:d54623194236 180 __IO uint32_t JDR4;
mbed_official 497:d54623194236 181 __IO uint32_t DR;
mbed_official 497:d54623194236 182 } ADC_TypeDef;
mbed_official 497:d54623194236 183
mbed_official 497:d54623194236 184 /**
mbed_official 497:d54623194236 185 * @brief Backup Registers
mbed_official 497:d54623194236 186 */
mbed_official 497:d54623194236 187
mbed_official 497:d54623194236 188 typedef struct
mbed_official 497:d54623194236 189 {
mbed_official 497:d54623194236 190 uint32_t RESERVED0;
mbed_official 497:d54623194236 191 __IO uint32_t DR1;
mbed_official 497:d54623194236 192 __IO uint32_t DR2;
mbed_official 497:d54623194236 193 __IO uint32_t DR3;
mbed_official 497:d54623194236 194 __IO uint32_t DR4;
mbed_official 497:d54623194236 195 __IO uint32_t DR5;
mbed_official 497:d54623194236 196 __IO uint32_t DR6;
mbed_official 497:d54623194236 197 __IO uint32_t DR7;
mbed_official 497:d54623194236 198 __IO uint32_t DR8;
mbed_official 497:d54623194236 199 __IO uint32_t DR9;
mbed_official 497:d54623194236 200 __IO uint32_t DR10;
mbed_official 497:d54623194236 201 __IO uint32_t RTCCR;
mbed_official 497:d54623194236 202 __IO uint32_t CR;
mbed_official 497:d54623194236 203 __IO uint32_t CSR;
mbed_official 497:d54623194236 204 } BKP_TypeDef;
mbed_official 497:d54623194236 205
mbed_official 497:d54623194236 206
mbed_official 497:d54623194236 207 /**
mbed_official 497:d54623194236 208 * @brief Consumer Electronics Control (CEC)
mbed_official 497:d54623194236 209 */
mbed_official 497:d54623194236 210 typedef struct
mbed_official 497:d54623194236 211 {
mbed_official 497:d54623194236 212 __IO uint32_t CFGR;
mbed_official 497:d54623194236 213 __IO uint32_t OAR;
mbed_official 497:d54623194236 214 __IO uint32_t PRES;
mbed_official 497:d54623194236 215 __IO uint32_t ESR;
mbed_official 497:d54623194236 216 __IO uint32_t CSR;
mbed_official 497:d54623194236 217 __IO uint32_t TXD;
mbed_official 497:d54623194236 218 __IO uint32_t RXD;
mbed_official 497:d54623194236 219 } CEC_TypeDef;
mbed_official 497:d54623194236 220
mbed_official 497:d54623194236 221 /**
mbed_official 497:d54623194236 222 * @brief CRC calculation unit
mbed_official 497:d54623194236 223 */
mbed_official 497:d54623194236 224
mbed_official 497:d54623194236 225 typedef struct
mbed_official 497:d54623194236 226 {
mbed_official 497:d54623194236 227 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 497:d54623194236 228 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 497:d54623194236 229 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 497:d54623194236 230 } CRC_TypeDef;
mbed_official 497:d54623194236 231
mbed_official 497:d54623194236 232 /**
mbed_official 497:d54623194236 233 * @brief Digital to Analog Converter
mbed_official 497:d54623194236 234 */
mbed_official 497:d54623194236 235
mbed_official 497:d54623194236 236 typedef struct
mbed_official 497:d54623194236 237 {
mbed_official 497:d54623194236 238 __IO uint32_t CR;
mbed_official 497:d54623194236 239 __IO uint32_t SWTRIGR;
mbed_official 497:d54623194236 240 __IO uint32_t DHR12R1;
mbed_official 497:d54623194236 241 __IO uint32_t DHR12L1;
mbed_official 497:d54623194236 242 __IO uint32_t DHR8R1;
mbed_official 497:d54623194236 243 __IO uint32_t DHR12R2;
mbed_official 497:d54623194236 244 __IO uint32_t DHR12L2;
mbed_official 497:d54623194236 245 __IO uint32_t DHR8R2;
mbed_official 497:d54623194236 246 __IO uint32_t DHR12RD;
mbed_official 497:d54623194236 247 __IO uint32_t DHR12LD;
mbed_official 497:d54623194236 248 __IO uint32_t DHR8RD;
mbed_official 497:d54623194236 249 __IO uint32_t DOR1;
mbed_official 497:d54623194236 250 __IO uint32_t DOR2;
mbed_official 497:d54623194236 251 __IO uint32_t SR;
mbed_official 497:d54623194236 252 } DAC_TypeDef;
mbed_official 497:d54623194236 253
mbed_official 497:d54623194236 254 /**
mbed_official 497:d54623194236 255 * @brief Debug MCU
mbed_official 497:d54623194236 256 */
mbed_official 497:d54623194236 257
mbed_official 497:d54623194236 258 typedef struct
mbed_official 497:d54623194236 259 {
mbed_official 497:d54623194236 260 __IO uint32_t IDCODE;
mbed_official 497:d54623194236 261 __IO uint32_t CR;
mbed_official 497:d54623194236 262 }DBGMCU_TypeDef;
mbed_official 497:d54623194236 263
mbed_official 497:d54623194236 264 /**
mbed_official 497:d54623194236 265 * @brief DMA Controller
mbed_official 497:d54623194236 266 */
mbed_official 497:d54623194236 267
mbed_official 497:d54623194236 268 typedef struct
mbed_official 497:d54623194236 269 {
mbed_official 497:d54623194236 270 __IO uint32_t CCR;
mbed_official 497:d54623194236 271 __IO uint32_t CNDTR;
mbed_official 497:d54623194236 272 __IO uint32_t CPAR;
mbed_official 497:d54623194236 273 __IO uint32_t CMAR;
mbed_official 497:d54623194236 274 } DMA_Channel_TypeDef;
mbed_official 497:d54623194236 275
mbed_official 497:d54623194236 276 typedef struct
mbed_official 497:d54623194236 277 {
mbed_official 497:d54623194236 278 __IO uint32_t ISR;
mbed_official 497:d54623194236 279 __IO uint32_t IFCR;
mbed_official 497:d54623194236 280 } DMA_TypeDef;
mbed_official 497:d54623194236 281
mbed_official 497:d54623194236 282
mbed_official 497:d54623194236 283
mbed_official 497:d54623194236 284 /**
mbed_official 497:d54623194236 285 * @brief External Interrupt/Event Controller
mbed_official 497:d54623194236 286 */
mbed_official 497:d54623194236 287
mbed_official 497:d54623194236 288 typedef struct
mbed_official 497:d54623194236 289 {
mbed_official 497:d54623194236 290 __IO uint32_t IMR;
mbed_official 497:d54623194236 291 __IO uint32_t EMR;
mbed_official 497:d54623194236 292 __IO uint32_t RTSR;
mbed_official 497:d54623194236 293 __IO uint32_t FTSR;
mbed_official 497:d54623194236 294 __IO uint32_t SWIER;
mbed_official 497:d54623194236 295 __IO uint32_t PR;
mbed_official 497:d54623194236 296 } EXTI_TypeDef;
mbed_official 497:d54623194236 297
mbed_official 497:d54623194236 298 /**
mbed_official 497:d54623194236 299 * @brief FLASH Registers
mbed_official 497:d54623194236 300 */
mbed_official 497:d54623194236 301
mbed_official 497:d54623194236 302 typedef struct
mbed_official 497:d54623194236 303 {
mbed_official 497:d54623194236 304 __IO uint32_t ACR;
mbed_official 497:d54623194236 305 __IO uint32_t KEYR;
mbed_official 497:d54623194236 306 __IO uint32_t OPTKEYR;
mbed_official 497:d54623194236 307 __IO uint32_t SR;
mbed_official 497:d54623194236 308 __IO uint32_t CR;
mbed_official 497:d54623194236 309 __IO uint32_t AR;
mbed_official 497:d54623194236 310 __IO uint32_t RESERVED;
mbed_official 497:d54623194236 311 __IO uint32_t OBR;
mbed_official 497:d54623194236 312 __IO uint32_t WRPR;
mbed_official 497:d54623194236 313 } FLASH_TypeDef;
mbed_official 497:d54623194236 314
mbed_official 497:d54623194236 315 /**
mbed_official 497:d54623194236 316 * @brief Option Bytes Registers
mbed_official 497:d54623194236 317 */
mbed_official 497:d54623194236 318
mbed_official 497:d54623194236 319 typedef struct
mbed_official 497:d54623194236 320 {
mbed_official 497:d54623194236 321 __IO uint16_t RDP;
mbed_official 497:d54623194236 322 __IO uint16_t USER;
mbed_official 497:d54623194236 323 __IO uint16_t Data0;
mbed_official 497:d54623194236 324 __IO uint16_t Data1;
mbed_official 497:d54623194236 325 __IO uint16_t WRP0;
mbed_official 497:d54623194236 326 __IO uint16_t WRP1;
mbed_official 497:d54623194236 327 __IO uint16_t WRP2;
mbed_official 497:d54623194236 328 __IO uint16_t WRP3;
mbed_official 497:d54623194236 329 } OB_TypeDef;
mbed_official 497:d54623194236 330
mbed_official 497:d54623194236 331 /**
mbed_official 497:d54623194236 332 * @brief General Purpose I/O
mbed_official 497:d54623194236 333 */
mbed_official 497:d54623194236 334
mbed_official 497:d54623194236 335 typedef struct
mbed_official 497:d54623194236 336 {
mbed_official 497:d54623194236 337 __IO uint32_t CRL;
mbed_official 497:d54623194236 338 __IO uint32_t CRH;
mbed_official 497:d54623194236 339 __IO uint32_t IDR;
mbed_official 497:d54623194236 340 __IO uint32_t ODR;
mbed_official 497:d54623194236 341 __IO uint32_t BSRR;
mbed_official 497:d54623194236 342 __IO uint32_t BRR;
mbed_official 497:d54623194236 343 __IO uint32_t LCKR;
mbed_official 497:d54623194236 344 } GPIO_TypeDef;
mbed_official 497:d54623194236 345
mbed_official 497:d54623194236 346 /**
mbed_official 497:d54623194236 347 * @brief Alternate Function I/O
mbed_official 497:d54623194236 348 */
mbed_official 497:d54623194236 349
mbed_official 497:d54623194236 350 typedef struct
mbed_official 497:d54623194236 351 {
mbed_official 497:d54623194236 352 __IO uint32_t EVCR;
mbed_official 497:d54623194236 353 __IO uint32_t MAPR;
mbed_official 497:d54623194236 354 __IO uint32_t EXTICR[4];
mbed_official 497:d54623194236 355 uint32_t RESERVED0;
mbed_official 497:d54623194236 356 __IO uint32_t MAPR2;
mbed_official 497:d54623194236 357 } AFIO_TypeDef;
mbed_official 497:d54623194236 358 /**
mbed_official 497:d54623194236 359 * @brief Inter Integrated Circuit Interface
mbed_official 497:d54623194236 360 */
mbed_official 497:d54623194236 361
mbed_official 497:d54623194236 362 typedef struct
mbed_official 497:d54623194236 363 {
mbed_official 497:d54623194236 364 __IO uint32_t CR1;
mbed_official 497:d54623194236 365 __IO uint32_t CR2;
mbed_official 497:d54623194236 366 __IO uint32_t OAR1;
mbed_official 497:d54623194236 367 __IO uint32_t OAR2;
mbed_official 497:d54623194236 368 __IO uint32_t DR;
mbed_official 497:d54623194236 369 __IO uint32_t SR1;
mbed_official 497:d54623194236 370 __IO uint32_t SR2;
mbed_official 497:d54623194236 371 __IO uint32_t CCR;
mbed_official 497:d54623194236 372 __IO uint32_t TRISE;
mbed_official 497:d54623194236 373 } I2C_TypeDef;
mbed_official 497:d54623194236 374
mbed_official 497:d54623194236 375 /**
mbed_official 497:d54623194236 376 * @brief Independent WATCHDOG
mbed_official 497:d54623194236 377 */
mbed_official 497:d54623194236 378
mbed_official 497:d54623194236 379 typedef struct
mbed_official 497:d54623194236 380 {
mbed_official 497:d54623194236 381 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
mbed_official 497:d54623194236 382 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
mbed_official 497:d54623194236 383 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
mbed_official 497:d54623194236 384 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
mbed_official 497:d54623194236 385 } IWDG_TypeDef;
mbed_official 497:d54623194236 386
mbed_official 497:d54623194236 387 /**
mbed_official 497:d54623194236 388 * @brief Power Control
mbed_official 497:d54623194236 389 */
mbed_official 497:d54623194236 390
mbed_official 497:d54623194236 391 typedef struct
mbed_official 497:d54623194236 392 {
mbed_official 497:d54623194236 393 __IO uint32_t CR;
mbed_official 497:d54623194236 394 __IO uint32_t CSR;
mbed_official 497:d54623194236 395 } PWR_TypeDef;
mbed_official 497:d54623194236 396
mbed_official 497:d54623194236 397 /**
mbed_official 497:d54623194236 398 * @brief Reset and Clock Control
mbed_official 497:d54623194236 399 */
mbed_official 497:d54623194236 400
mbed_official 497:d54623194236 401 typedef struct
mbed_official 497:d54623194236 402 {
mbed_official 497:d54623194236 403 __IO uint32_t CR;
mbed_official 497:d54623194236 404 __IO uint32_t CFGR;
mbed_official 497:d54623194236 405 __IO uint32_t CIR;
mbed_official 497:d54623194236 406 __IO uint32_t APB2RSTR;
mbed_official 497:d54623194236 407 __IO uint32_t APB1RSTR;
mbed_official 497:d54623194236 408 __IO uint32_t AHBENR;
mbed_official 497:d54623194236 409 __IO uint32_t APB2ENR;
mbed_official 497:d54623194236 410 __IO uint32_t APB1ENR;
mbed_official 497:d54623194236 411 __IO uint32_t BDCR;
mbed_official 497:d54623194236 412 __IO uint32_t CSR;
mbed_official 497:d54623194236 413
mbed_official 497:d54623194236 414
mbed_official 497:d54623194236 415 uint32_t RESERVED0;
mbed_official 497:d54623194236 416 __IO uint32_t CFGR2;
mbed_official 497:d54623194236 417 } RCC_TypeDef;
mbed_official 497:d54623194236 418
mbed_official 497:d54623194236 419 /**
mbed_official 497:d54623194236 420 * @brief Real-Time Clock
mbed_official 497:d54623194236 421 */
mbed_official 497:d54623194236 422
mbed_official 497:d54623194236 423 typedef struct
mbed_official 497:d54623194236 424 {
mbed_official 497:d54623194236 425 __IO uint32_t CRH;
mbed_official 497:d54623194236 426 __IO uint32_t CRL;
mbed_official 497:d54623194236 427 __IO uint32_t PRLH;
mbed_official 497:d54623194236 428 __IO uint32_t PRLL;
mbed_official 497:d54623194236 429 __IO uint32_t DIVH;
mbed_official 497:d54623194236 430 __IO uint32_t DIVL;
mbed_official 497:d54623194236 431 __IO uint32_t CNTH;
mbed_official 497:d54623194236 432 __IO uint32_t CNTL;
mbed_official 497:d54623194236 433 __IO uint32_t ALRH;
mbed_official 497:d54623194236 434 __IO uint32_t ALRL;
mbed_official 497:d54623194236 435 } RTC_TypeDef;
mbed_official 497:d54623194236 436
mbed_official 497:d54623194236 437 /**
mbed_official 497:d54623194236 438 * @brief SD host Interface
mbed_official 497:d54623194236 439 */
mbed_official 497:d54623194236 440
mbed_official 497:d54623194236 441 typedef struct
mbed_official 497:d54623194236 442 {
mbed_official 497:d54623194236 443 __IO uint32_t POWER;
mbed_official 497:d54623194236 444 __IO uint32_t CLKCR;
mbed_official 497:d54623194236 445 __IO uint32_t ARG;
mbed_official 497:d54623194236 446 __IO uint32_t CMD;
mbed_official 497:d54623194236 447 __I uint32_t RESPCMD;
mbed_official 497:d54623194236 448 __I uint32_t RESP1;
mbed_official 497:d54623194236 449 __I uint32_t RESP2;
mbed_official 497:d54623194236 450 __I uint32_t RESP3;
mbed_official 497:d54623194236 451 __I uint32_t RESP4;
mbed_official 497:d54623194236 452 __IO uint32_t DTIMER;
mbed_official 497:d54623194236 453 __IO uint32_t DLEN;
mbed_official 497:d54623194236 454 __IO uint32_t DCTRL;
mbed_official 497:d54623194236 455 __I uint32_t DCOUNT;
mbed_official 497:d54623194236 456 __I uint32_t STA;
mbed_official 497:d54623194236 457 __IO uint32_t ICR;
mbed_official 497:d54623194236 458 __IO uint32_t MASK;
mbed_official 497:d54623194236 459 uint32_t RESERVED0[2];
mbed_official 497:d54623194236 460 __I uint32_t FIFOCNT;
mbed_official 497:d54623194236 461 uint32_t RESERVED1[13];
mbed_official 497:d54623194236 462 __IO uint32_t FIFO;
mbed_official 497:d54623194236 463 } SDIO_TypeDef;
mbed_official 497:d54623194236 464
mbed_official 497:d54623194236 465 /**
mbed_official 497:d54623194236 466 * @brief Serial Peripheral Interface
mbed_official 497:d54623194236 467 */
mbed_official 497:d54623194236 468
mbed_official 497:d54623194236 469 typedef struct
mbed_official 497:d54623194236 470 {
mbed_official 497:d54623194236 471 __IO uint32_t CR1;
mbed_official 497:d54623194236 472 __IO uint32_t CR2;
mbed_official 497:d54623194236 473 __IO uint32_t SR;
mbed_official 497:d54623194236 474 __IO uint32_t DR;
mbed_official 497:d54623194236 475 __IO uint32_t CRCPR;
mbed_official 497:d54623194236 476 __IO uint32_t RXCRCR;
mbed_official 497:d54623194236 477 __IO uint32_t TXCRCR;
mbed_official 497:d54623194236 478 } SPI_TypeDef;
mbed_official 497:d54623194236 479
mbed_official 497:d54623194236 480 /**
mbed_official 497:d54623194236 481 * @brief TIM Timers
mbed_official 497:d54623194236 482 */
mbed_official 497:d54623194236 483 typedef struct
mbed_official 497:d54623194236 484 {
mbed_official 497:d54623194236 485 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 497:d54623194236 486 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 497:d54623194236 487 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 497:d54623194236 488 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 497:d54623194236 489 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 497:d54623194236 490 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 497:d54623194236 491 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 497:d54623194236 492 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 497:d54623194236 493 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 497:d54623194236 494 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 497:d54623194236 495 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 497:d54623194236 496 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 497:d54623194236 497 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 497:d54623194236 498 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 497:d54623194236 499 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 497:d54623194236 500 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 497:d54623194236 501 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 497:d54623194236 502 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 497:d54623194236 503 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 497:d54623194236 504 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
mbed_official 497:d54623194236 505 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 497:d54623194236 506 }TIM_TypeDef;
mbed_official 497:d54623194236 507
mbed_official 497:d54623194236 508
mbed_official 497:d54623194236 509 /**
mbed_official 497:d54623194236 510 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 497:d54623194236 511 */
mbed_official 497:d54623194236 512
mbed_official 497:d54623194236 513 typedef struct
mbed_official 497:d54623194236 514 {
mbed_official 497:d54623194236 515 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 497:d54623194236 516 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 497:d54623194236 517 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 497:d54623194236 518 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 497:d54623194236 519 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 497:d54623194236 520 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 497:d54623194236 521 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 497:d54623194236 522 } USART_TypeDef;
mbed_official 497:d54623194236 523
mbed_official 497:d54623194236 524
mbed_official 497:d54623194236 525
mbed_official 497:d54623194236 526 /**
mbed_official 497:d54623194236 527 * @brief Window WATCHDOG
mbed_official 497:d54623194236 528 */
mbed_official 497:d54623194236 529
mbed_official 497:d54623194236 530 typedef struct
mbed_official 497:d54623194236 531 {
mbed_official 497:d54623194236 532 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 497:d54623194236 533 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 497:d54623194236 534 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 497:d54623194236 535 } WWDG_TypeDef;
mbed_official 497:d54623194236 536
mbed_official 497:d54623194236 537 /**
mbed_official 497:d54623194236 538 * @}
mbed_official 497:d54623194236 539 */
mbed_official 497:d54623194236 540
mbed_official 497:d54623194236 541 /** @addtogroup Peripheral_memory_map
mbed_official 497:d54623194236 542 * @{
mbed_official 497:d54623194236 543 */
mbed_official 497:d54623194236 544
mbed_official 497:d54623194236 545
mbed_official 497:d54623194236 546 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 497:d54623194236 547 #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
mbed_official 497:d54623194236 548 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 497:d54623194236 549 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 497:d54623194236 550
mbed_official 497:d54623194236 551 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
mbed_official 497:d54623194236 552 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 497:d54623194236 553
mbed_official 497:d54623194236 554
mbed_official 497:d54623194236 555 /*!< Peripheral memory map */
mbed_official 497:d54623194236 556 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 497:d54623194236 557 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
mbed_official 497:d54623194236 558 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
mbed_official 497:d54623194236 559
mbed_official 497:d54623194236 560 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
mbed_official 497:d54623194236 561 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
mbed_official 497:d54623194236 562 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
mbed_official 497:d54623194236 563 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
mbed_official 497:d54623194236 564 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
mbed_official 497:d54623194236 565 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official 497:d54623194236 566 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official 497:d54623194236 567 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official 497:d54623194236 568 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official 497:d54623194236 569 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official 497:d54623194236 570 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
mbed_official 497:d54623194236 571 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official 497:d54623194236 572 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official 497:d54623194236 573 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
mbed_official 497:d54623194236 574 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official 497:d54623194236 575 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
mbed_official 497:d54623194236 576 #define CEC_BASE (APB1PERIPH_BASE + 0x7800)
mbed_official 497:d54623194236 577 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official 497:d54623194236 578 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
mbed_official 497:d54623194236 579 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
mbed_official 497:d54623194236 580 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
mbed_official 497:d54623194236 581 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official 497:d54623194236 582 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
mbed_official 497:d54623194236 583 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
mbed_official 497:d54623194236 584 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
mbed_official 497:d54623194236 585 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
mbed_official 497:d54623194236 586 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official 497:d54623194236 587 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official 497:d54623194236 588 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
mbed_official 497:d54623194236 589 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
mbed_official 497:d54623194236 590 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
mbed_official 497:d54623194236 591
mbed_official 497:d54623194236 592 #define SDIO_BASE (PERIPH_BASE + 0x18000)
mbed_official 497:d54623194236 593
mbed_official 497:d54623194236 594 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
mbed_official 497:d54623194236 595 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
mbed_official 497:d54623194236 596 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
mbed_official 497:d54623194236 597 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
mbed_official 497:d54623194236 598 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
mbed_official 497:d54623194236 599 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
mbed_official 497:d54623194236 600 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
mbed_official 497:d54623194236 601 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
mbed_official 497:d54623194236 602 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
mbed_official 497:d54623194236 603 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
mbed_official 497:d54623194236 604
mbed_official 497:d54623194236 605 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
mbed_official 497:d54623194236 606 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
mbed_official 497:d54623194236 607
mbed_official 497:d54623194236 608
mbed_official 497:d54623194236 609
mbed_official 497:d54623194236 610 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
mbed_official 497:d54623194236 611
mbed_official 497:d54623194236 612
mbed_official 497:d54623194236 613
mbed_official 497:d54623194236 614 /**
mbed_official 497:d54623194236 615 * @}
mbed_official 497:d54623194236 616 */
mbed_official 497:d54623194236 617
mbed_official 497:d54623194236 618 /** @addtogroup Peripheral_declaration
mbed_official 497:d54623194236 619 * @{
mbed_official 497:d54623194236 620 */
mbed_official 497:d54623194236 621
mbed_official 497:d54623194236 622 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 497:d54623194236 623 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 497:d54623194236 624 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 497:d54623194236 625 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 497:d54623194236 626 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 497:d54623194236 627 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 497:d54623194236 628 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 497:d54623194236 629 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 497:d54623194236 630 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 497:d54623194236 631 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 497:d54623194236 632 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 497:d54623194236 633 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 497:d54623194236 634 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 497:d54623194236 635 #define BKP ((BKP_TypeDef *) BKP_BASE)
mbed_official 497:d54623194236 636 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 497:d54623194236 637 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 497:d54623194236 638 #define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official 497:d54623194236 639 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
mbed_official 497:d54623194236 640 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 497:d54623194236 641 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 497:d54623194236 642 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 497:d54623194236 643 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 497:d54623194236 644 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 497:d54623194236 645 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 497:d54623194236 646 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 497:d54623194236 647 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 497:d54623194236 648 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 497:d54623194236 649 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 497:d54623194236 650 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 497:d54623194236 651 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 497:d54623194236 652 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 497:d54623194236 653 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
mbed_official 497:d54623194236 654 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 497:d54623194236 655 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 497:d54623194236 656 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 497:d54623194236 657 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 497:d54623194236 658 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 497:d54623194236 659 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 497:d54623194236 660 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 497:d54623194236 661 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 497:d54623194236 662 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 497:d54623194236 663 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 497:d54623194236 664 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 497:d54623194236 665 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 497:d54623194236 666 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 497:d54623194236 667
mbed_official 497:d54623194236 668
mbed_official 497:d54623194236 669 /**
mbed_official 497:d54623194236 670 * @}
mbed_official 497:d54623194236 671 */
mbed_official 497:d54623194236 672
mbed_official 497:d54623194236 673 /** @addtogroup Exported_constants
mbed_official 497:d54623194236 674 * @{
mbed_official 497:d54623194236 675 */
mbed_official 497:d54623194236 676
mbed_official 497:d54623194236 677 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 497:d54623194236 678 * @{
mbed_official 497:d54623194236 679 */
mbed_official 497:d54623194236 680
mbed_official 497:d54623194236 681 /******************************************************************************/
mbed_official 497:d54623194236 682 /* Peripheral Registers_Bits_Definition */
mbed_official 497:d54623194236 683 /******************************************************************************/
mbed_official 497:d54623194236 684
mbed_official 497:d54623194236 685 /******************************************************************************/
mbed_official 497:d54623194236 686 /* */
mbed_official 497:d54623194236 687 /* CRC calculation unit (CRC) */
mbed_official 497:d54623194236 688 /* */
mbed_official 497:d54623194236 689 /******************************************************************************/
mbed_official 497:d54623194236 690
mbed_official 497:d54623194236 691 /******************* Bit definition for CRC_DR register *********************/
mbed_official 497:d54623194236 692 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 497:d54623194236 693
mbed_official 497:d54623194236 694 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 497:d54623194236 695 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
mbed_official 497:d54623194236 696
mbed_official 497:d54623194236 697 /******************** Bit definition for CRC_CR register ********************/
mbed_official 497:d54623194236 698 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
mbed_official 497:d54623194236 699
mbed_official 497:d54623194236 700 /******************************************************************************/
mbed_official 497:d54623194236 701 /* */
mbed_official 497:d54623194236 702 /* Power Control */
mbed_official 497:d54623194236 703 /* */
mbed_official 497:d54623194236 704 /******************************************************************************/
mbed_official 497:d54623194236 705
mbed_official 497:d54623194236 706 /******************** Bit definition for PWR_CR register ********************/
mbed_official 497:d54623194236 707 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
mbed_official 497:d54623194236 708 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 497:d54623194236 709 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 497:d54623194236 710 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 497:d54623194236 711 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 497:d54623194236 712
mbed_official 497:d54623194236 713 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 497:d54623194236 714 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 497:d54623194236 715 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 497:d54623194236 716 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 497:d54623194236 717
mbed_official 497:d54623194236 718 /*!< PVD level configuration */
mbed_official 497:d54623194236 719 #define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
mbed_official 497:d54623194236 720 #define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
mbed_official 497:d54623194236 721 #define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
mbed_official 497:d54623194236 722 #define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
mbed_official 497:d54623194236 723 #define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
mbed_official 497:d54623194236 724 #define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
mbed_official 497:d54623194236 725 #define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
mbed_official 497:d54623194236 726 #define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
mbed_official 497:d54623194236 727
mbed_official 497:d54623194236 728 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 497:d54623194236 729
mbed_official 497:d54623194236 730
mbed_official 497:d54623194236 731 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 497:d54623194236 732 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 497:d54623194236 733 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 497:d54623194236 734 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 497:d54623194236 735 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
mbed_official 497:d54623194236 736
mbed_official 497:d54623194236 737 /******************************************************************************/
mbed_official 497:d54623194236 738 /* */
mbed_official 497:d54623194236 739 /* Backup registers */
mbed_official 497:d54623194236 740 /* */
mbed_official 497:d54623194236 741 /******************************************************************************/
mbed_official 497:d54623194236 742
mbed_official 497:d54623194236 743 /******************* Bit definition for BKP_DR1 register ********************/
mbed_official 497:d54623194236 744 #define BKP_DR1_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 745
mbed_official 497:d54623194236 746 /******************* Bit definition for BKP_DR2 register ********************/
mbed_official 497:d54623194236 747 #define BKP_DR2_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 748
mbed_official 497:d54623194236 749 /******************* Bit definition for BKP_DR3 register ********************/
mbed_official 497:d54623194236 750 #define BKP_DR3_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 751
mbed_official 497:d54623194236 752 /******************* Bit definition for BKP_DR4 register ********************/
mbed_official 497:d54623194236 753 #define BKP_DR4_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 754
mbed_official 497:d54623194236 755 /******************* Bit definition for BKP_DR5 register ********************/
mbed_official 497:d54623194236 756 #define BKP_DR5_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 757
mbed_official 497:d54623194236 758 /******************* Bit definition for BKP_DR6 register ********************/
mbed_official 497:d54623194236 759 #define BKP_DR6_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 760
mbed_official 497:d54623194236 761 /******************* Bit definition for BKP_DR7 register ********************/
mbed_official 497:d54623194236 762 #define BKP_DR7_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 763
mbed_official 497:d54623194236 764 /******************* Bit definition for BKP_DR8 register ********************/
mbed_official 497:d54623194236 765 #define BKP_DR8_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 766
mbed_official 497:d54623194236 767 /******************* Bit definition for BKP_DR9 register ********************/
mbed_official 497:d54623194236 768 #define BKP_DR9_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 769
mbed_official 497:d54623194236 770 /******************* Bit definition for BKP_DR10 register *******************/
mbed_official 497:d54623194236 771 #define BKP_DR10_D ((uint32_t)0x0000FFFF) /*!< Backup data */
mbed_official 497:d54623194236 772
mbed_official 497:d54623194236 773 #define RTC_BKP_NUMBER 10
mbed_official 497:d54623194236 774
mbed_official 497:d54623194236 775 /****************** Bit definition for BKP_RTCCR register *******************/
mbed_official 497:d54623194236 776 #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /*!< Calibration value */
mbed_official 497:d54623194236 777 #define BKP_RTCCR_CCO ((uint32_t)0x00000080) /*!< Calibration Clock Output */
mbed_official 497:d54623194236 778 #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /*!< Alarm or Second Output Enable */
mbed_official 497:d54623194236 779 #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /*!< Alarm or Second Output Selection */
mbed_official 497:d54623194236 780
mbed_official 497:d54623194236 781 /******************** Bit definition for BKP_CR register ********************/
mbed_official 497:d54623194236 782 #define BKP_CR_TPE ((uint32_t)0x00000001) /*!< TAMPER pin enable */
mbed_official 497:d54623194236 783 #define BKP_CR_TPAL ((uint32_t)0x00000002) /*!< TAMPER pin active level */
mbed_official 497:d54623194236 784
mbed_official 497:d54623194236 785 /******************* Bit definition for BKP_CSR register ********************/
mbed_official 497:d54623194236 786 #define BKP_CSR_CTE ((uint32_t)0x00000001) /*!< Clear Tamper event */
mbed_official 497:d54623194236 787 #define BKP_CSR_CTI ((uint32_t)0x00000002) /*!< Clear Tamper Interrupt */
mbed_official 497:d54623194236 788 #define BKP_CSR_TPIE ((uint32_t)0x00000004) /*!< TAMPER Pin interrupt enable */
mbed_official 497:d54623194236 789 #define BKP_CSR_TEF ((uint32_t)0x00000100) /*!< Tamper Event Flag */
mbed_official 497:d54623194236 790 #define BKP_CSR_TIF ((uint32_t)0x00000200) /*!< Tamper Interrupt Flag */
mbed_official 497:d54623194236 791
mbed_official 497:d54623194236 792 /******************************************************************************/
mbed_official 497:d54623194236 793 /* */
mbed_official 497:d54623194236 794 /* Reset and Clock Control */
mbed_official 497:d54623194236 795 /* */
mbed_official 497:d54623194236 796 /******************************************************************************/
mbed_official 497:d54623194236 797
mbed_official 497:d54623194236 798 /******************** Bit definition for RCC_CR register ********************/
mbed_official 497:d54623194236 799 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
mbed_official 497:d54623194236 800 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
mbed_official 497:d54623194236 801 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
mbed_official 497:d54623194236 802 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
mbed_official 497:d54623194236 803 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
mbed_official 497:d54623194236 804 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
mbed_official 497:d54623194236 805 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
mbed_official 497:d54623194236 806 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
mbed_official 497:d54623194236 807 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
mbed_official 497:d54623194236 808 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
mbed_official 497:d54623194236 809
mbed_official 497:d54623194236 810
mbed_official 497:d54623194236 811 /******************* Bit definition for RCC_CFGR register *******************/
mbed_official 497:d54623194236 812 /*!< SW configuration */
mbed_official 497:d54623194236 813 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 497:d54623194236 814 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 815 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 816
mbed_official 497:d54623194236 817 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 497:d54623194236 818 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 497:d54623194236 819 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 497:d54623194236 820
mbed_official 497:d54623194236 821 /*!< SWS configuration */
mbed_official 497:d54623194236 822 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 497:d54623194236 823 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 497:d54623194236 824 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 497:d54623194236 825
mbed_official 497:d54623194236 826 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 497:d54623194236 827 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 497:d54623194236 828 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 497:d54623194236 829
mbed_official 497:d54623194236 830 /*!< HPRE configuration */
mbed_official 497:d54623194236 831 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 497:d54623194236 832 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 497:d54623194236 833 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 497:d54623194236 834 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 497:d54623194236 835 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 497:d54623194236 836
mbed_official 497:d54623194236 837 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 497:d54623194236 838 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 497:d54623194236 839 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 497:d54623194236 840 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 497:d54623194236 841 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 497:d54623194236 842 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 497:d54623194236 843 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 497:d54623194236 844 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 497:d54623194236 845 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 497:d54623194236 846
mbed_official 497:d54623194236 847 /*!< PPRE1 configuration */
mbed_official 497:d54623194236 848 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 497:d54623194236 849 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 497:d54623194236 850 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 497:d54623194236 851 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 497:d54623194236 852
mbed_official 497:d54623194236 853 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 497:d54623194236 854 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 497:d54623194236 855 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 497:d54623194236 856 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 497:d54623194236 857 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 497:d54623194236 858
mbed_official 497:d54623194236 859 /*!< PPRE2 configuration */
mbed_official 497:d54623194236 860 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 497:d54623194236 861 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 497:d54623194236 862 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 497:d54623194236 863 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
mbed_official 497:d54623194236 864
mbed_official 497:d54623194236 865 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 497:d54623194236 866 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
mbed_official 497:d54623194236 867 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
mbed_official 497:d54623194236 868 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
mbed_official 497:d54623194236 869 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
mbed_official 497:d54623194236 870
mbed_official 497:d54623194236 871 /*!< ADCPPRE configuration */
mbed_official 497:d54623194236 872 #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
mbed_official 497:d54623194236 873 #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 497:d54623194236 874 #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 497:d54623194236 875
mbed_official 497:d54623194236 876 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
mbed_official 497:d54623194236 877 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
mbed_official 497:d54623194236 878 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
mbed_official 497:d54623194236 879 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
mbed_official 497:d54623194236 880
mbed_official 497:d54623194236 881 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
mbed_official 497:d54623194236 882
mbed_official 497:d54623194236 883 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 497:d54623194236 884
mbed_official 497:d54623194236 885 /*!< PLLMUL configuration */
mbed_official 497:d54623194236 886 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 497:d54623194236 887 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 497:d54623194236 888 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 497:d54623194236 889 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 497:d54623194236 890 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 497:d54623194236 891
mbed_official 497:d54623194236 892 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
mbed_official 497:d54623194236 893 #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
mbed_official 497:d54623194236 894
mbed_official 497:d54623194236 895 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 497:d54623194236 896 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 497:d54623194236 897 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 497:d54623194236 898 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 497:d54623194236 899 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 497:d54623194236 900 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 497:d54623194236 901 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 497:d54623194236 902 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 497:d54623194236 903 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 497:d54623194236 904 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 497:d54623194236 905 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 497:d54623194236 906 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 497:d54623194236 907 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 497:d54623194236 908 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 497:d54623194236 909 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 497:d54623194236 910
mbed_official 497:d54623194236 911 /*!< MCO configuration */
mbed_official 497:d54623194236 912 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
mbed_official 497:d54623194236 913 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 497:d54623194236 914 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 497:d54623194236 915 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 497:d54623194236 916
mbed_official 497:d54623194236 917 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 497:d54623194236 918 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 497:d54623194236 919 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 497:d54623194236 920 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 497:d54623194236 921 #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 497:d54623194236 922
mbed_official 497:d54623194236 923 /*!<****************** Bit definition for RCC_CIR register ********************/
mbed_official 497:d54623194236 924 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 497:d54623194236 925 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 497:d54623194236 926 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 497:d54623194236 927 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 497:d54623194236 928 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 497:d54623194236 929 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 497:d54623194236 930 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 497:d54623194236 931 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 497:d54623194236 932 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 497:d54623194236 933 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 497:d54623194236 934 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 497:d54623194236 935 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 497:d54623194236 936 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 497:d54623194236 937 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 497:d54623194236 938 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 497:d54623194236 939 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 497:d54623194236 940 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 497:d54623194236 941
mbed_official 497:d54623194236 942
mbed_official 497:d54623194236 943 /***************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 497:d54623194236 944 #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
mbed_official 497:d54623194236 945 #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
mbed_official 497:d54623194236 946 #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
mbed_official 497:d54623194236 947 #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
mbed_official 497:d54623194236 948 #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
mbed_official 497:d54623194236 949 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
mbed_official 497:d54623194236 950
mbed_official 497:d54623194236 951
mbed_official 497:d54623194236 952 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
mbed_official 497:d54623194236 953 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
mbed_official 497:d54623194236 954 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
mbed_official 497:d54623194236 955
mbed_official 497:d54623194236 956 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
mbed_official 497:d54623194236 957 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
mbed_official 497:d54623194236 958 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
mbed_official 497:d54623194236 959
mbed_official 497:d54623194236 960 #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
mbed_official 497:d54623194236 961
mbed_official 497:d54623194236 962
mbed_official 497:d54623194236 963
mbed_official 497:d54623194236 964
mbed_official 497:d54623194236 965 /***************** Bit definition for RCC_APB1RSTR register *****************/
mbed_official 497:d54623194236 966 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
mbed_official 497:d54623194236 967 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
mbed_official 497:d54623194236 968 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
mbed_official 497:d54623194236 969 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
mbed_official 497:d54623194236 970 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
mbed_official 497:d54623194236 971
mbed_official 497:d54623194236 972
mbed_official 497:d54623194236 973 #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
mbed_official 497:d54623194236 974 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
mbed_official 497:d54623194236 975
mbed_official 497:d54623194236 976 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
mbed_official 497:d54623194236 977 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
mbed_official 497:d54623194236 978 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
mbed_official 497:d54623194236 979 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
mbed_official 497:d54623194236 980
mbed_official 497:d54623194236 981
mbed_official 497:d54623194236 982
mbed_official 497:d54623194236 983 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
mbed_official 497:d54623194236 984 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
mbed_official 497:d54623194236 985 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
mbed_official 497:d54623194236 986
mbed_official 497:d54623194236 987
mbed_official 497:d54623194236 988
mbed_official 497:d54623194236 989 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
mbed_official 497:d54623194236 990
mbed_official 497:d54623194236 991 /****************** Bit definition for RCC_AHBENR register ******************/
mbed_official 497:d54623194236 992 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 497:d54623194236 993 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 497:d54623194236 994 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 497:d54623194236 995 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 497:d54623194236 996
mbed_official 497:d54623194236 997
mbed_official 497:d54623194236 998
mbed_official 497:d54623194236 999
mbed_official 497:d54623194236 1000 /****************** Bit definition for RCC_APB2ENR register *****************/
mbed_official 497:d54623194236 1001 #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
mbed_official 497:d54623194236 1002 #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
mbed_official 497:d54623194236 1003 #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
mbed_official 497:d54623194236 1004 #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
mbed_official 497:d54623194236 1005 #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
mbed_official 497:d54623194236 1006 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
mbed_official 497:d54623194236 1007
mbed_official 497:d54623194236 1008
mbed_official 497:d54623194236 1009 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
mbed_official 497:d54623194236 1010 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
mbed_official 497:d54623194236 1011 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 497:d54623194236 1012
mbed_official 497:d54623194236 1013 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
mbed_official 497:d54623194236 1014 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
mbed_official 497:d54623194236 1015 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
mbed_official 497:d54623194236 1016
mbed_official 497:d54623194236 1017 #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
mbed_official 497:d54623194236 1018
mbed_official 497:d54623194236 1019
mbed_official 497:d54623194236 1020
mbed_official 497:d54623194236 1021
mbed_official 497:d54623194236 1022 /***************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 497:d54623194236 1023 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
mbed_official 497:d54623194236 1024 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 497:d54623194236 1025 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 497:d54623194236 1026 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
mbed_official 497:d54623194236 1027 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
mbed_official 497:d54623194236 1028
mbed_official 497:d54623194236 1029
mbed_official 497:d54623194236 1030 #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
mbed_official 497:d54623194236 1031 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
mbed_official 497:d54623194236 1032
mbed_official 497:d54623194236 1033 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
mbed_official 497:d54623194236 1034 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
mbed_official 497:d54623194236 1035 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
mbed_official 497:d54623194236 1036 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
mbed_official 497:d54623194236 1037
mbed_official 497:d54623194236 1038
mbed_official 497:d54623194236 1039
mbed_official 497:d54623194236 1040 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 497:d54623194236 1041 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 497:d54623194236 1042 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
mbed_official 497:d54623194236 1043
mbed_official 497:d54623194236 1044
mbed_official 497:d54623194236 1045
mbed_official 497:d54623194236 1046 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
mbed_official 497:d54623194236 1047
mbed_official 497:d54623194236 1048 /******************* Bit definition for RCC_BDCR register *******************/
mbed_official 497:d54623194236 1049 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 497:d54623194236 1050 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 497:d54623194236 1051 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 497:d54623194236 1052
mbed_official 497:d54623194236 1053 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 497:d54623194236 1054 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 497:d54623194236 1055 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 497:d54623194236 1056
mbed_official 497:d54623194236 1057 /*!< RTC congiguration */
mbed_official 497:d54623194236 1058 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 497:d54623194236 1059 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 497:d54623194236 1060 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 497:d54623194236 1061 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
mbed_official 497:d54623194236 1062
mbed_official 497:d54623194236 1063 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 497:d54623194236 1064 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 497:d54623194236 1065
mbed_official 497:d54623194236 1066 /******************* Bit definition for RCC_CSR register ********************/
mbed_official 497:d54623194236 1067 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 497:d54623194236 1068 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 497:d54623194236 1069 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 497:d54623194236 1070 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 497:d54623194236 1071 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 497:d54623194236 1072 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 497:d54623194236 1073 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 497:d54623194236 1074 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 497:d54623194236 1075 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 497:d54623194236 1076
mbed_official 497:d54623194236 1077
mbed_official 497:d54623194236 1078 /******************* Bit definition for RCC_CFGR2 register ******************/
mbed_official 497:d54623194236 1079 /*!< PREDIV1 configuration */
mbed_official 497:d54623194236 1080 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
mbed_official 497:d54623194236 1081 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 1082 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 1083 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 1084 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 1085
mbed_official 497:d54623194236 1086 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
mbed_official 497:d54623194236 1087 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
mbed_official 497:d54623194236 1088 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
mbed_official 497:d54623194236 1089 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
mbed_official 497:d54623194236 1090 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
mbed_official 497:d54623194236 1091 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
mbed_official 497:d54623194236 1092 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
mbed_official 497:d54623194236 1093 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
mbed_official 497:d54623194236 1094 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
mbed_official 497:d54623194236 1095 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
mbed_official 497:d54623194236 1096 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
mbed_official 497:d54623194236 1097 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
mbed_official 497:d54623194236 1098 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
mbed_official 497:d54623194236 1099 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
mbed_official 497:d54623194236 1100 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
mbed_official 497:d54623194236 1101 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
mbed_official 497:d54623194236 1102
mbed_official 497:d54623194236 1103 /******************************************************************************/
mbed_official 497:d54623194236 1104 /* */
mbed_official 497:d54623194236 1105 /* General Purpose and Alternate Function I/O */
mbed_official 497:d54623194236 1106 /* */
mbed_official 497:d54623194236 1107 /******************************************************************************/
mbed_official 497:d54623194236 1108
mbed_official 497:d54623194236 1109 /******************* Bit definition for GPIO_CRL register *******************/
mbed_official 497:d54623194236 1110 #define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
mbed_official 497:d54623194236 1111
mbed_official 497:d54623194236 1112 #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
mbed_official 497:d54623194236 1113 #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 1114 #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 1115
mbed_official 497:d54623194236 1116 #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
mbed_official 497:d54623194236 1117 #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 497:d54623194236 1118 #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 497:d54623194236 1119
mbed_official 497:d54623194236 1120 #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
mbed_official 497:d54623194236 1121 #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 497:d54623194236 1122 #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 497:d54623194236 1123
mbed_official 497:d54623194236 1124 #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
mbed_official 497:d54623194236 1125 #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 497:d54623194236 1126 #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 497:d54623194236 1127
mbed_official 497:d54623194236 1128 #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
mbed_official 497:d54623194236 1129 #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 497:d54623194236 1130 #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 497:d54623194236 1131
mbed_official 497:d54623194236 1132 #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
mbed_official 497:d54623194236 1133 #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 497:d54623194236 1134 #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 497:d54623194236 1135
mbed_official 497:d54623194236 1136 #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
mbed_official 497:d54623194236 1137 #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1138 #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1139
mbed_official 497:d54623194236 1140 #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
mbed_official 497:d54623194236 1141 #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1142 #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1143
mbed_official 497:d54623194236 1144 #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
mbed_official 497:d54623194236 1145
mbed_official 497:d54623194236 1146 #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
mbed_official 497:d54623194236 1147 #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 497:d54623194236 1148 #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 497:d54623194236 1149
mbed_official 497:d54623194236 1150 #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
mbed_official 497:d54623194236 1151 #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 497:d54623194236 1152 #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 497:d54623194236 1153
mbed_official 497:d54623194236 1154 #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
mbed_official 497:d54623194236 1155 #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 497:d54623194236 1156 #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 497:d54623194236 1157
mbed_official 497:d54623194236 1158 #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
mbed_official 497:d54623194236 1159 #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 497:d54623194236 1160 #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 497:d54623194236 1161
mbed_official 497:d54623194236 1162 #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
mbed_official 497:d54623194236 1163 #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 497:d54623194236 1164 #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 497:d54623194236 1165
mbed_official 497:d54623194236 1166 #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
mbed_official 497:d54623194236 1167 #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 497:d54623194236 1168 #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 497:d54623194236 1169
mbed_official 497:d54623194236 1170 #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
mbed_official 497:d54623194236 1171 #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1172 #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1173
mbed_official 497:d54623194236 1174 #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
mbed_official 497:d54623194236 1175 #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1176 #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1177
mbed_official 497:d54623194236 1178 /******************* Bit definition for GPIO_CRH register *******************/
mbed_official 497:d54623194236 1179 #define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
mbed_official 497:d54623194236 1180
mbed_official 497:d54623194236 1181 #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
mbed_official 497:d54623194236 1182 #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 1183 #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 1184
mbed_official 497:d54623194236 1185 #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
mbed_official 497:d54623194236 1186 #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 497:d54623194236 1187 #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 497:d54623194236 1188
mbed_official 497:d54623194236 1189 #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
mbed_official 497:d54623194236 1190 #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 497:d54623194236 1191 #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 497:d54623194236 1192
mbed_official 497:d54623194236 1193 #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
mbed_official 497:d54623194236 1194 #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 497:d54623194236 1195 #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 497:d54623194236 1196
mbed_official 497:d54623194236 1197 #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
mbed_official 497:d54623194236 1198 #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 497:d54623194236 1199 #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 497:d54623194236 1200
mbed_official 497:d54623194236 1201 #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
mbed_official 497:d54623194236 1202 #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 497:d54623194236 1203 #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 497:d54623194236 1204
mbed_official 497:d54623194236 1205 #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
mbed_official 497:d54623194236 1206 #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1207 #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1208
mbed_official 497:d54623194236 1209 #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
mbed_official 497:d54623194236 1210 #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1211 #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1212
mbed_official 497:d54623194236 1213 #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
mbed_official 497:d54623194236 1214
mbed_official 497:d54623194236 1215 #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
mbed_official 497:d54623194236 1216 #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 497:d54623194236 1217 #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 497:d54623194236 1218
mbed_official 497:d54623194236 1219 #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
mbed_official 497:d54623194236 1220 #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 497:d54623194236 1221 #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 497:d54623194236 1222
mbed_official 497:d54623194236 1223 #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
mbed_official 497:d54623194236 1224 #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 497:d54623194236 1225 #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 497:d54623194236 1226
mbed_official 497:d54623194236 1227 #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
mbed_official 497:d54623194236 1228 #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 497:d54623194236 1229 #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 497:d54623194236 1230
mbed_official 497:d54623194236 1231 #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
mbed_official 497:d54623194236 1232 #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 497:d54623194236 1233 #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 497:d54623194236 1234
mbed_official 497:d54623194236 1235 #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
mbed_official 497:d54623194236 1236 #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 497:d54623194236 1237 #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 497:d54623194236 1238
mbed_official 497:d54623194236 1239 #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
mbed_official 497:d54623194236 1240 #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1241 #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1242
mbed_official 497:d54623194236 1243 #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
mbed_official 497:d54623194236 1244 #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1245 #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1246
mbed_official 497:d54623194236 1247 /*!<****************** Bit definition for GPIO_IDR register *******************/
mbed_official 497:d54623194236 1248 #define GPIO_IDR_IDR0 ((uint32_t)0x0001) /*!< Port input data, bit 0 */
mbed_official 497:d54623194236 1249 #define GPIO_IDR_IDR1 ((uint32_t)0x0002) /*!< Port input data, bit 1 */
mbed_official 497:d54623194236 1250 #define GPIO_IDR_IDR2 ((uint32_t)0x0004) /*!< Port input data, bit 2 */
mbed_official 497:d54623194236 1251 #define GPIO_IDR_IDR3 ((uint32_t)0x0008) /*!< Port input data, bit 3 */
mbed_official 497:d54623194236 1252 #define GPIO_IDR_IDR4 ((uint32_t)0x0010) /*!< Port input data, bit 4 */
mbed_official 497:d54623194236 1253 #define GPIO_IDR_IDR5 ((uint32_t)0x0020) /*!< Port input data, bit 5 */
mbed_official 497:d54623194236 1254 #define GPIO_IDR_IDR6 ((uint32_t)0x0040) /*!< Port input data, bit 6 */
mbed_official 497:d54623194236 1255 #define GPIO_IDR_IDR7 ((uint32_t)0x0080) /*!< Port input data, bit 7 */
mbed_official 497:d54623194236 1256 #define GPIO_IDR_IDR8 ((uint32_t)0x0100) /*!< Port input data, bit 8 */
mbed_official 497:d54623194236 1257 #define GPIO_IDR_IDR9 ((uint32_t)0x0200) /*!< Port input data, bit 9 */
mbed_official 497:d54623194236 1258 #define GPIO_IDR_IDR10 ((uint32_t)0x0400) /*!< Port input data, bit 10 */
mbed_official 497:d54623194236 1259 #define GPIO_IDR_IDR11 ((uint32_t)0x0800) /*!< Port input data, bit 11 */
mbed_official 497:d54623194236 1260 #define GPIO_IDR_IDR12 ((uint32_t)0x1000) /*!< Port input data, bit 12 */
mbed_official 497:d54623194236 1261 #define GPIO_IDR_IDR13 ((uint32_t)0x2000) /*!< Port input data, bit 13 */
mbed_official 497:d54623194236 1262 #define GPIO_IDR_IDR14 ((uint32_t)0x4000) /*!< Port input data, bit 14 */
mbed_official 497:d54623194236 1263 #define GPIO_IDR_IDR15 ((uint32_t)0x8000) /*!< Port input data, bit 15 */
mbed_official 497:d54623194236 1264
mbed_official 497:d54623194236 1265 /******************* Bit definition for GPIO_ODR register *******************/
mbed_official 497:d54623194236 1266 #define GPIO_ODR_ODR0 ((uint32_t)0x0001) /*!< Port output data, bit 0 */
mbed_official 497:d54623194236 1267 #define GPIO_ODR_ODR1 ((uint32_t)0x0002) /*!< Port output data, bit 1 */
mbed_official 497:d54623194236 1268 #define GPIO_ODR_ODR2 ((uint32_t)0x0004) /*!< Port output data, bit 2 */
mbed_official 497:d54623194236 1269 #define GPIO_ODR_ODR3 ((uint32_t)0x0008) /*!< Port output data, bit 3 */
mbed_official 497:d54623194236 1270 #define GPIO_ODR_ODR4 ((uint32_t)0x0010) /*!< Port output data, bit 4 */
mbed_official 497:d54623194236 1271 #define GPIO_ODR_ODR5 ((uint32_t)0x0020) /*!< Port output data, bit 5 */
mbed_official 497:d54623194236 1272 #define GPIO_ODR_ODR6 ((uint32_t)0x0040) /*!< Port output data, bit 6 */
mbed_official 497:d54623194236 1273 #define GPIO_ODR_ODR7 ((uint32_t)0x0080) /*!< Port output data, bit 7 */
mbed_official 497:d54623194236 1274 #define GPIO_ODR_ODR8 ((uint32_t)0x0100) /*!< Port output data, bit 8 */
mbed_official 497:d54623194236 1275 #define GPIO_ODR_ODR9 ((uint32_t)0x0200) /*!< Port output data, bit 9 */
mbed_official 497:d54623194236 1276 #define GPIO_ODR_ODR10 ((uint32_t)0x0400) /*!< Port output data, bit 10 */
mbed_official 497:d54623194236 1277 #define GPIO_ODR_ODR11 ((uint32_t)0x0800) /*!< Port output data, bit 11 */
mbed_official 497:d54623194236 1278 #define GPIO_ODR_ODR12 ((uint32_t)0x1000) /*!< Port output data, bit 12 */
mbed_official 497:d54623194236 1279 #define GPIO_ODR_ODR13 ((uint32_t)0x2000) /*!< Port output data, bit 13 */
mbed_official 497:d54623194236 1280 #define GPIO_ODR_ODR14 ((uint32_t)0x4000) /*!< Port output data, bit 14 */
mbed_official 497:d54623194236 1281 #define GPIO_ODR_ODR15 ((uint32_t)0x8000) /*!< Port output data, bit 15 */
mbed_official 497:d54623194236 1282
mbed_official 497:d54623194236 1283 /****************** Bit definition for GPIO_BSRR register *******************/
mbed_official 497:d54623194236 1284 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
mbed_official 497:d54623194236 1285 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
mbed_official 497:d54623194236 1286 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
mbed_official 497:d54623194236 1287 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
mbed_official 497:d54623194236 1288 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
mbed_official 497:d54623194236 1289 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
mbed_official 497:d54623194236 1290 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
mbed_official 497:d54623194236 1291 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
mbed_official 497:d54623194236 1292 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
mbed_official 497:d54623194236 1293 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
mbed_official 497:d54623194236 1294 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
mbed_official 497:d54623194236 1295 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
mbed_official 497:d54623194236 1296 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
mbed_official 497:d54623194236 1297 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
mbed_official 497:d54623194236 1298 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
mbed_official 497:d54623194236 1299 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
mbed_official 497:d54623194236 1300
mbed_official 497:d54623194236 1301 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
mbed_official 497:d54623194236 1302 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
mbed_official 497:d54623194236 1303 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
mbed_official 497:d54623194236 1304 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
mbed_official 497:d54623194236 1305 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
mbed_official 497:d54623194236 1306 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
mbed_official 497:d54623194236 1307 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
mbed_official 497:d54623194236 1308 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
mbed_official 497:d54623194236 1309 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
mbed_official 497:d54623194236 1310 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
mbed_official 497:d54623194236 1311 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
mbed_official 497:d54623194236 1312 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
mbed_official 497:d54623194236 1313 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
mbed_official 497:d54623194236 1314 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
mbed_official 497:d54623194236 1315 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
mbed_official 497:d54623194236 1316 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
mbed_official 497:d54623194236 1317
mbed_official 497:d54623194236 1318 /******************* Bit definition for GPIO_BRR register *******************/
mbed_official 497:d54623194236 1319 #define GPIO_BRR_BR0 ((uint32_t)0x0001) /*!< Port x Reset bit 0 */
mbed_official 497:d54623194236 1320 #define GPIO_BRR_BR1 ((uint32_t)0x0002) /*!< Port x Reset bit 1 */
mbed_official 497:d54623194236 1321 #define GPIO_BRR_BR2 ((uint32_t)0x0004) /*!< Port x Reset bit 2 */
mbed_official 497:d54623194236 1322 #define GPIO_BRR_BR3 ((uint32_t)0x0008) /*!< Port x Reset bit 3 */
mbed_official 497:d54623194236 1323 #define GPIO_BRR_BR4 ((uint32_t)0x0010) /*!< Port x Reset bit 4 */
mbed_official 497:d54623194236 1324 #define GPIO_BRR_BR5 ((uint32_t)0x0020) /*!< Port x Reset bit 5 */
mbed_official 497:d54623194236 1325 #define GPIO_BRR_BR6 ((uint32_t)0x0040) /*!< Port x Reset bit 6 */
mbed_official 497:d54623194236 1326 #define GPIO_BRR_BR7 ((uint32_t)0x0080) /*!< Port x Reset bit 7 */
mbed_official 497:d54623194236 1327 #define GPIO_BRR_BR8 ((uint32_t)0x0100) /*!< Port x Reset bit 8 */
mbed_official 497:d54623194236 1328 #define GPIO_BRR_BR9 ((uint32_t)0x0200) /*!< Port x Reset bit 9 */
mbed_official 497:d54623194236 1329 #define GPIO_BRR_BR10 ((uint32_t)0x0400) /*!< Port x Reset bit 10 */
mbed_official 497:d54623194236 1330 #define GPIO_BRR_BR11 ((uint32_t)0x0800) /*!< Port x Reset bit 11 */
mbed_official 497:d54623194236 1331 #define GPIO_BRR_BR12 ((uint32_t)0x1000) /*!< Port x Reset bit 12 */
mbed_official 497:d54623194236 1332 #define GPIO_BRR_BR13 ((uint32_t)0x2000) /*!< Port x Reset bit 13 */
mbed_official 497:d54623194236 1333 #define GPIO_BRR_BR14 ((uint32_t)0x4000) /*!< Port x Reset bit 14 */
mbed_official 497:d54623194236 1334 #define GPIO_BRR_BR15 ((uint32_t)0x8000) /*!< Port x Reset bit 15 */
mbed_official 497:d54623194236 1335
mbed_official 497:d54623194236 1336 /****************** Bit definition for GPIO_LCKR register *******************/
mbed_official 497:d54623194236 1337 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
mbed_official 497:d54623194236 1338 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
mbed_official 497:d54623194236 1339 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
mbed_official 497:d54623194236 1340 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
mbed_official 497:d54623194236 1341 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
mbed_official 497:d54623194236 1342 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
mbed_official 497:d54623194236 1343 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
mbed_official 497:d54623194236 1344 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
mbed_official 497:d54623194236 1345 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
mbed_official 497:d54623194236 1346 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
mbed_official 497:d54623194236 1347 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
mbed_official 497:d54623194236 1348 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
mbed_official 497:d54623194236 1349 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
mbed_official 497:d54623194236 1350 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
mbed_official 497:d54623194236 1351 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
mbed_official 497:d54623194236 1352 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
mbed_official 497:d54623194236 1353 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
mbed_official 497:d54623194236 1354
mbed_official 497:d54623194236 1355 /*----------------------------------------------------------------------------*/
mbed_official 497:d54623194236 1356
mbed_official 497:d54623194236 1357 /****************** Bit definition for AFIO_EVCR register *******************/
mbed_official 497:d54623194236 1358 #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /*!< PIN[3:0] bits (Pin selection) */
mbed_official 497:d54623194236 1359 #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 1360 #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 1361 #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 1362 #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 1363
mbed_official 497:d54623194236 1364 /*!< PIN configuration */
mbed_official 497:d54623194236 1365 #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
mbed_official 497:d54623194236 1366 #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /*!< Pin 1 selected */
mbed_official 497:d54623194236 1367 #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /*!< Pin 2 selected */
mbed_official 497:d54623194236 1368 #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /*!< Pin 3 selected */
mbed_official 497:d54623194236 1369 #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /*!< Pin 4 selected */
mbed_official 497:d54623194236 1370 #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /*!< Pin 5 selected */
mbed_official 497:d54623194236 1371 #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /*!< Pin 6 selected */
mbed_official 497:d54623194236 1372 #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /*!< Pin 7 selected */
mbed_official 497:d54623194236 1373 #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /*!< Pin 8 selected */
mbed_official 497:d54623194236 1374 #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /*!< Pin 9 selected */
mbed_official 497:d54623194236 1375 #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /*!< Pin 10 selected */
mbed_official 497:d54623194236 1376 #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /*!< Pin 11 selected */
mbed_official 497:d54623194236 1377 #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /*!< Pin 12 selected */
mbed_official 497:d54623194236 1378 #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /*!< Pin 13 selected */
mbed_official 497:d54623194236 1379 #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /*!< Pin 14 selected */
mbed_official 497:d54623194236 1380 #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /*!< Pin 15 selected */
mbed_official 497:d54623194236 1381
mbed_official 497:d54623194236 1382 #define AFIO_EVCR_PORT ((uint32_t)0x00000070) /*!< PORT[2:0] bits (Port selection) */
mbed_official 497:d54623194236 1383 #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 497:d54623194236 1384 #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 497:d54623194236 1385 #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 497:d54623194236 1386
mbed_official 497:d54623194236 1387 /*!< PORT configuration */
mbed_official 497:d54623194236 1388 #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
mbed_official 497:d54623194236 1389 #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /*!< Port B selected */
mbed_official 497:d54623194236 1390 #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /*!< Port C selected */
mbed_official 497:d54623194236 1391 #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /*!< Port D selected */
mbed_official 497:d54623194236 1392 #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /*!< Port E selected */
mbed_official 497:d54623194236 1393
mbed_official 497:d54623194236 1394 #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /*!< Event Output Enable */
mbed_official 497:d54623194236 1395
mbed_official 497:d54623194236 1396 /****************** Bit definition for AFIO_MAPR register *******************/
mbed_official 497:d54623194236 1397 #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
mbed_official 497:d54623194236 1398 #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
mbed_official 497:d54623194236 1399 #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
mbed_official 497:d54623194236 1400 #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
mbed_official 497:d54623194236 1401
mbed_official 497:d54623194236 1402 #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
mbed_official 497:d54623194236 1403 #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 497:d54623194236 1404 #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 497:d54623194236 1405
mbed_official 497:d54623194236 1406 /* USART3_REMAP configuration */
mbed_official 497:d54623194236 1407 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
mbed_official 497:d54623194236 1408 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
mbed_official 497:d54623194236 1409 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
mbed_official 497:d54623194236 1410
mbed_official 497:d54623194236 1411 #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
mbed_official 497:d54623194236 1412 #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 497:d54623194236 1413 #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 497:d54623194236 1414
mbed_official 497:d54623194236 1415 /*!< TIM1_REMAP configuration */
mbed_official 497:d54623194236 1416 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
mbed_official 497:d54623194236 1417 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
mbed_official 497:d54623194236 1418 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
mbed_official 497:d54623194236 1419
mbed_official 497:d54623194236 1420 #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
mbed_official 497:d54623194236 1421 #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 497:d54623194236 1422 #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 497:d54623194236 1423
mbed_official 497:d54623194236 1424 /*!< TIM2_REMAP configuration */
mbed_official 497:d54623194236 1425 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
mbed_official 497:d54623194236 1426 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
mbed_official 497:d54623194236 1427 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
mbed_official 497:d54623194236 1428 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
mbed_official 497:d54623194236 1429
mbed_official 497:d54623194236 1430 #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
mbed_official 497:d54623194236 1431 #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 497:d54623194236 1432 #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 497:d54623194236 1433
mbed_official 497:d54623194236 1434 /*!< TIM3_REMAP configuration */
mbed_official 497:d54623194236 1435 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
mbed_official 497:d54623194236 1436 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
mbed_official 497:d54623194236 1437 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
mbed_official 497:d54623194236 1438
mbed_official 497:d54623194236 1439 #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
mbed_official 497:d54623194236 1440
mbed_official 497:d54623194236 1441
mbed_official 497:d54623194236 1442 #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
mbed_official 497:d54623194236 1443
mbed_official 497:d54623194236 1444 /*!< SWJ_CFG configuration */
mbed_official 497:d54623194236 1445 #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
mbed_official 497:d54623194236 1446 #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 497:d54623194236 1447 #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 497:d54623194236 1448 #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 497:d54623194236 1449
mbed_official 497:d54623194236 1450 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
mbed_official 497:d54623194236 1451 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
mbed_official 497:d54623194236 1452 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
mbed_official 497:d54623194236 1453 #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
mbed_official 497:d54623194236 1454
mbed_official 497:d54623194236 1455
mbed_official 497:d54623194236 1456 /***************** Bit definition for AFIO_EXTICR1 register *****************/
mbed_official 497:d54623194236 1457 #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
mbed_official 497:d54623194236 1458 #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
mbed_official 497:d54623194236 1459 #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
mbed_official 497:d54623194236 1460 #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
mbed_official 497:d54623194236 1461
mbed_official 497:d54623194236 1462 /*!< EXTI0 configuration */
mbed_official 497:d54623194236 1463 #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
mbed_official 497:d54623194236 1464 #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
mbed_official 497:d54623194236 1465 #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
mbed_official 497:d54623194236 1466 #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
mbed_official 497:d54623194236 1467 #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
mbed_official 497:d54623194236 1468 #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
mbed_official 497:d54623194236 1469 #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
mbed_official 497:d54623194236 1470
mbed_official 497:d54623194236 1471 /*!< EXTI1 configuration */
mbed_official 497:d54623194236 1472 #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
mbed_official 497:d54623194236 1473 #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
mbed_official 497:d54623194236 1474 #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
mbed_official 497:d54623194236 1475 #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
mbed_official 497:d54623194236 1476 #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
mbed_official 497:d54623194236 1477 #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
mbed_official 497:d54623194236 1478 #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
mbed_official 497:d54623194236 1479
mbed_official 497:d54623194236 1480 /*!< EXTI2 configuration */
mbed_official 497:d54623194236 1481 #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
mbed_official 497:d54623194236 1482 #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
mbed_official 497:d54623194236 1483 #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
mbed_official 497:d54623194236 1484 #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
mbed_official 497:d54623194236 1485 #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
mbed_official 497:d54623194236 1486 #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
mbed_official 497:d54623194236 1487 #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
mbed_official 497:d54623194236 1488
mbed_official 497:d54623194236 1489 /*!< EXTI3 configuration */
mbed_official 497:d54623194236 1490 #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
mbed_official 497:d54623194236 1491 #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
mbed_official 497:d54623194236 1492 #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
mbed_official 497:d54623194236 1493 #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
mbed_official 497:d54623194236 1494 #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
mbed_official 497:d54623194236 1495 #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
mbed_official 497:d54623194236 1496 #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
mbed_official 497:d54623194236 1497
mbed_official 497:d54623194236 1498 /***************** Bit definition for AFIO_EXTICR2 register *****************/
mbed_official 497:d54623194236 1499 #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
mbed_official 497:d54623194236 1500 #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
mbed_official 497:d54623194236 1501 #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
mbed_official 497:d54623194236 1502 #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
mbed_official 497:d54623194236 1503
mbed_official 497:d54623194236 1504 /*!< EXTI4 configuration */
mbed_official 497:d54623194236 1505 #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
mbed_official 497:d54623194236 1506 #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
mbed_official 497:d54623194236 1507 #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
mbed_official 497:d54623194236 1508 #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
mbed_official 497:d54623194236 1509 #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
mbed_official 497:d54623194236 1510 #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
mbed_official 497:d54623194236 1511 #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
mbed_official 497:d54623194236 1512
mbed_official 497:d54623194236 1513 /* EXTI5 configuration */
mbed_official 497:d54623194236 1514 #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
mbed_official 497:d54623194236 1515 #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
mbed_official 497:d54623194236 1516 #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
mbed_official 497:d54623194236 1517 #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
mbed_official 497:d54623194236 1518 #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
mbed_official 497:d54623194236 1519 #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
mbed_official 497:d54623194236 1520 #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
mbed_official 497:d54623194236 1521
mbed_official 497:d54623194236 1522 /*!< EXTI6 configuration */
mbed_official 497:d54623194236 1523 #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
mbed_official 497:d54623194236 1524 #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
mbed_official 497:d54623194236 1525 #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
mbed_official 497:d54623194236 1526 #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
mbed_official 497:d54623194236 1527 #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
mbed_official 497:d54623194236 1528 #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
mbed_official 497:d54623194236 1529 #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
mbed_official 497:d54623194236 1530
mbed_official 497:d54623194236 1531 /*!< EXTI7 configuration */
mbed_official 497:d54623194236 1532 #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
mbed_official 497:d54623194236 1533 #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
mbed_official 497:d54623194236 1534 #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
mbed_official 497:d54623194236 1535 #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
mbed_official 497:d54623194236 1536 #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
mbed_official 497:d54623194236 1537 #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
mbed_official 497:d54623194236 1538 #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
mbed_official 497:d54623194236 1539
mbed_official 497:d54623194236 1540 /***************** Bit definition for AFIO_EXTICR3 register *****************/
mbed_official 497:d54623194236 1541 #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
mbed_official 497:d54623194236 1542 #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
mbed_official 497:d54623194236 1543 #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
mbed_official 497:d54623194236 1544 #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
mbed_official 497:d54623194236 1545
mbed_official 497:d54623194236 1546 /*!< EXTI8 configuration */
mbed_official 497:d54623194236 1547 #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
mbed_official 497:d54623194236 1548 #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
mbed_official 497:d54623194236 1549 #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
mbed_official 497:d54623194236 1550 #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
mbed_official 497:d54623194236 1551 #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
mbed_official 497:d54623194236 1552 #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
mbed_official 497:d54623194236 1553 #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
mbed_official 497:d54623194236 1554
mbed_official 497:d54623194236 1555 /*!< EXTI9 configuration */
mbed_official 497:d54623194236 1556 #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
mbed_official 497:d54623194236 1557 #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
mbed_official 497:d54623194236 1558 #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
mbed_official 497:d54623194236 1559 #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
mbed_official 497:d54623194236 1560 #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
mbed_official 497:d54623194236 1561 #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
mbed_official 497:d54623194236 1562 #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
mbed_official 497:d54623194236 1563
mbed_official 497:d54623194236 1564 /*!< EXTI10 configuration */
mbed_official 497:d54623194236 1565 #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
mbed_official 497:d54623194236 1566 #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
mbed_official 497:d54623194236 1567 #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
mbed_official 497:d54623194236 1568 #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
mbed_official 497:d54623194236 1569 #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
mbed_official 497:d54623194236 1570 #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
mbed_official 497:d54623194236 1571 #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
mbed_official 497:d54623194236 1572
mbed_official 497:d54623194236 1573 /*!< EXTI11 configuration */
mbed_official 497:d54623194236 1574 #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
mbed_official 497:d54623194236 1575 #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
mbed_official 497:d54623194236 1576 #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
mbed_official 497:d54623194236 1577 #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
mbed_official 497:d54623194236 1578 #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
mbed_official 497:d54623194236 1579 #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
mbed_official 497:d54623194236 1580 #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
mbed_official 497:d54623194236 1581
mbed_official 497:d54623194236 1582 /***************** Bit definition for AFIO_EXTICR4 register *****************/
mbed_official 497:d54623194236 1583 #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
mbed_official 497:d54623194236 1584 #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
mbed_official 497:d54623194236 1585 #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
mbed_official 497:d54623194236 1586 #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
mbed_official 497:d54623194236 1587
mbed_official 497:d54623194236 1588 /* EXTI12 configuration */
mbed_official 497:d54623194236 1589 #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
mbed_official 497:d54623194236 1590 #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
mbed_official 497:d54623194236 1591 #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
mbed_official 497:d54623194236 1592 #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
mbed_official 497:d54623194236 1593 #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
mbed_official 497:d54623194236 1594 #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
mbed_official 497:d54623194236 1595 #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
mbed_official 497:d54623194236 1596
mbed_official 497:d54623194236 1597 /* EXTI13 configuration */
mbed_official 497:d54623194236 1598 #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
mbed_official 497:d54623194236 1599 #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
mbed_official 497:d54623194236 1600 #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
mbed_official 497:d54623194236 1601 #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
mbed_official 497:d54623194236 1602 #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
mbed_official 497:d54623194236 1603 #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
mbed_official 497:d54623194236 1604 #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
mbed_official 497:d54623194236 1605
mbed_official 497:d54623194236 1606 /*!< EXTI14 configuration */
mbed_official 497:d54623194236 1607 #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
mbed_official 497:d54623194236 1608 #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
mbed_official 497:d54623194236 1609 #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
mbed_official 497:d54623194236 1610 #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
mbed_official 497:d54623194236 1611 #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
mbed_official 497:d54623194236 1612 #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
mbed_official 497:d54623194236 1613 #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
mbed_official 497:d54623194236 1614
mbed_official 497:d54623194236 1615 /*!< EXTI15 configuration */
mbed_official 497:d54623194236 1616 #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
mbed_official 497:d54623194236 1617 #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
mbed_official 497:d54623194236 1618 #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
mbed_official 497:d54623194236 1619 #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
mbed_official 497:d54623194236 1620 #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
mbed_official 497:d54623194236 1621 #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
mbed_official 497:d54623194236 1622 #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
mbed_official 497:d54623194236 1623
mbed_official 497:d54623194236 1624 /****************** Bit definition for AFIO_MAPR2 register ******************/
mbed_official 497:d54623194236 1625 #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
mbed_official 497:d54623194236 1626 #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
mbed_official 497:d54623194236 1627 #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
mbed_official 497:d54623194236 1628 #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
mbed_official 497:d54623194236 1629 #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
mbed_official 497:d54623194236 1630
mbed_official 497:d54623194236 1631 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
mbed_official 497:d54623194236 1632
mbed_official 497:d54623194236 1633
mbed_official 497:d54623194236 1634 /******************************************************************************/
mbed_official 497:d54623194236 1635 /* */
mbed_official 497:d54623194236 1636 /* SystemTick */
mbed_official 497:d54623194236 1637 /* */
mbed_official 497:d54623194236 1638 /******************************************************************************/
mbed_official 497:d54623194236 1639
mbed_official 497:d54623194236 1640 /***************** Bit definition for SysTick_CTRL register *****************/
mbed_official 497:d54623194236 1641 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
mbed_official 497:d54623194236 1642 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
mbed_official 497:d54623194236 1643 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
mbed_official 497:d54623194236 1644 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
mbed_official 497:d54623194236 1645
mbed_official 497:d54623194236 1646 /***************** Bit definition for SysTick_LOAD register *****************/
mbed_official 497:d54623194236 1647 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
mbed_official 497:d54623194236 1648
mbed_official 497:d54623194236 1649 /***************** Bit definition for SysTick_VAL register ******************/
mbed_official 497:d54623194236 1650 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
mbed_official 497:d54623194236 1651
mbed_official 497:d54623194236 1652 /***************** Bit definition for SysTick_CALIB register ****************/
mbed_official 497:d54623194236 1653 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
mbed_official 497:d54623194236 1654 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
mbed_official 497:d54623194236 1655 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
mbed_official 497:d54623194236 1656
mbed_official 497:d54623194236 1657 /******************************************************************************/
mbed_official 497:d54623194236 1658 /* */
mbed_official 497:d54623194236 1659 /* Nested Vectored Interrupt Controller */
mbed_official 497:d54623194236 1660 /* */
mbed_official 497:d54623194236 1661 /******************************************************************************/
mbed_official 497:d54623194236 1662
mbed_official 497:d54623194236 1663 /****************** Bit definition for NVIC_ISER register *******************/
mbed_official 497:d54623194236 1664 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
mbed_official 497:d54623194236 1665 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 497:d54623194236 1666 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 497:d54623194236 1667 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 497:d54623194236 1668 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 497:d54623194236 1669 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 497:d54623194236 1670 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 497:d54623194236 1671 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 497:d54623194236 1672 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 497:d54623194236 1673 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 497:d54623194236 1674 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 497:d54623194236 1675 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 497:d54623194236 1676 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 497:d54623194236 1677 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 497:d54623194236 1678 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 497:d54623194236 1679 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 497:d54623194236 1680 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 497:d54623194236 1681 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 497:d54623194236 1682 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 497:d54623194236 1683 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 497:d54623194236 1684 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 497:d54623194236 1685 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 497:d54623194236 1686 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 497:d54623194236 1687 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 497:d54623194236 1688 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 497:d54623194236 1689 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 497:d54623194236 1690 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 497:d54623194236 1691 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 497:d54623194236 1692 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 497:d54623194236 1693 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 497:d54623194236 1694 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 497:d54623194236 1695 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 497:d54623194236 1696 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 497:d54623194236 1697
mbed_official 497:d54623194236 1698 /****************** Bit definition for NVIC_ICER register *******************/
mbed_official 497:d54623194236 1699 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
mbed_official 497:d54623194236 1700 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 497:d54623194236 1701 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 497:d54623194236 1702 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 497:d54623194236 1703 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 497:d54623194236 1704 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 497:d54623194236 1705 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 497:d54623194236 1706 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 497:d54623194236 1707 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 497:d54623194236 1708 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 497:d54623194236 1709 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 497:d54623194236 1710 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 497:d54623194236 1711 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 497:d54623194236 1712 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 497:d54623194236 1713 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 497:d54623194236 1714 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 497:d54623194236 1715 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 497:d54623194236 1716 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 497:d54623194236 1717 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 497:d54623194236 1718 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 497:d54623194236 1719 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 497:d54623194236 1720 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 497:d54623194236 1721 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 497:d54623194236 1722 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 497:d54623194236 1723 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 497:d54623194236 1724 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 497:d54623194236 1725 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 497:d54623194236 1726 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 497:d54623194236 1727 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 497:d54623194236 1728 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 497:d54623194236 1729 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 497:d54623194236 1730 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 497:d54623194236 1731 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 497:d54623194236 1732
mbed_official 497:d54623194236 1733 /****************** Bit definition for NVIC_ISPR register *******************/
mbed_official 497:d54623194236 1734 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
mbed_official 497:d54623194236 1735 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 497:d54623194236 1736 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 497:d54623194236 1737 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 497:d54623194236 1738 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 497:d54623194236 1739 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 497:d54623194236 1740 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 497:d54623194236 1741 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 497:d54623194236 1742 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 497:d54623194236 1743 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 497:d54623194236 1744 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 497:d54623194236 1745 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 497:d54623194236 1746 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 497:d54623194236 1747 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 497:d54623194236 1748 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 497:d54623194236 1749 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 497:d54623194236 1750 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 497:d54623194236 1751 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 497:d54623194236 1752 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 497:d54623194236 1753 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 497:d54623194236 1754 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 497:d54623194236 1755 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 497:d54623194236 1756 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 497:d54623194236 1757 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 497:d54623194236 1758 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 497:d54623194236 1759 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 497:d54623194236 1760 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 497:d54623194236 1761 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 497:d54623194236 1762 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 497:d54623194236 1763 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 497:d54623194236 1764 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 497:d54623194236 1765 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 497:d54623194236 1766 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 497:d54623194236 1767
mbed_official 497:d54623194236 1768 /****************** Bit definition for NVIC_ICPR register *******************/
mbed_official 497:d54623194236 1769 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
mbed_official 497:d54623194236 1770 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 497:d54623194236 1771 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 497:d54623194236 1772 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 497:d54623194236 1773 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 497:d54623194236 1774 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 497:d54623194236 1775 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 497:d54623194236 1776 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 497:d54623194236 1777 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 497:d54623194236 1778 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 497:d54623194236 1779 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 497:d54623194236 1780 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 497:d54623194236 1781 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 497:d54623194236 1782 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 497:d54623194236 1783 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 497:d54623194236 1784 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 497:d54623194236 1785 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 497:d54623194236 1786 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 497:d54623194236 1787 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 497:d54623194236 1788 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 497:d54623194236 1789 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 497:d54623194236 1790 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 497:d54623194236 1791 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 497:d54623194236 1792 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 497:d54623194236 1793 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 497:d54623194236 1794 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 497:d54623194236 1795 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 497:d54623194236 1796 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 497:d54623194236 1797 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 497:d54623194236 1798 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 497:d54623194236 1799 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 497:d54623194236 1800 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 497:d54623194236 1801 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 497:d54623194236 1802
mbed_official 497:d54623194236 1803 /****************** Bit definition for NVIC_IABR register *******************/
mbed_official 497:d54623194236 1804 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
mbed_official 497:d54623194236 1805 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 497:d54623194236 1806 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 497:d54623194236 1807 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 497:d54623194236 1808 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 497:d54623194236 1809 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 497:d54623194236 1810 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 497:d54623194236 1811 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 497:d54623194236 1812 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 497:d54623194236 1813 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 497:d54623194236 1814 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 497:d54623194236 1815 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 497:d54623194236 1816 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 497:d54623194236 1817 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 497:d54623194236 1818 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 497:d54623194236 1819 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 497:d54623194236 1820 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 497:d54623194236 1821 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 497:d54623194236 1822 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 497:d54623194236 1823 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 497:d54623194236 1824 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 497:d54623194236 1825 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 497:d54623194236 1826 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 497:d54623194236 1827 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 497:d54623194236 1828 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 497:d54623194236 1829 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 497:d54623194236 1830 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 497:d54623194236 1831 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 497:d54623194236 1832 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 497:d54623194236 1833 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 497:d54623194236 1834 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 497:d54623194236 1835 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 497:d54623194236 1836 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 497:d54623194236 1837
mbed_official 497:d54623194236 1838 /****************** Bit definition for NVIC_PRI0 register *******************/
mbed_official 497:d54623194236 1839 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
mbed_official 497:d54623194236 1840 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
mbed_official 497:d54623194236 1841 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
mbed_official 497:d54623194236 1842 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
mbed_official 497:d54623194236 1843
mbed_official 497:d54623194236 1844 /****************** Bit definition for NVIC_PRI1 register *******************/
mbed_official 497:d54623194236 1845 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
mbed_official 497:d54623194236 1846 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
mbed_official 497:d54623194236 1847 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
mbed_official 497:d54623194236 1848 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
mbed_official 497:d54623194236 1849
mbed_official 497:d54623194236 1850 /****************** Bit definition for NVIC_PRI2 register *******************/
mbed_official 497:d54623194236 1851 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
mbed_official 497:d54623194236 1852 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
mbed_official 497:d54623194236 1853 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
mbed_official 497:d54623194236 1854 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
mbed_official 497:d54623194236 1855
mbed_official 497:d54623194236 1856 /****************** Bit definition for NVIC_PRI3 register *******************/
mbed_official 497:d54623194236 1857 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
mbed_official 497:d54623194236 1858 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
mbed_official 497:d54623194236 1859 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
mbed_official 497:d54623194236 1860 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
mbed_official 497:d54623194236 1861
mbed_official 497:d54623194236 1862 /****************** Bit definition for NVIC_PRI4 register *******************/
mbed_official 497:d54623194236 1863 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
mbed_official 497:d54623194236 1864 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
mbed_official 497:d54623194236 1865 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
mbed_official 497:d54623194236 1866 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
mbed_official 497:d54623194236 1867
mbed_official 497:d54623194236 1868 /****************** Bit definition for NVIC_PRI5 register *******************/
mbed_official 497:d54623194236 1869 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
mbed_official 497:d54623194236 1870 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
mbed_official 497:d54623194236 1871 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
mbed_official 497:d54623194236 1872 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
mbed_official 497:d54623194236 1873
mbed_official 497:d54623194236 1874 /****************** Bit definition for NVIC_PRI6 register *******************/
mbed_official 497:d54623194236 1875 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
mbed_official 497:d54623194236 1876 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
mbed_official 497:d54623194236 1877 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
mbed_official 497:d54623194236 1878 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
mbed_official 497:d54623194236 1879
mbed_official 497:d54623194236 1880 /****************** Bit definition for NVIC_PRI7 register *******************/
mbed_official 497:d54623194236 1881 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
mbed_official 497:d54623194236 1882 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
mbed_official 497:d54623194236 1883 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
mbed_official 497:d54623194236 1884 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
mbed_official 497:d54623194236 1885
mbed_official 497:d54623194236 1886 /****************** Bit definition for SCB_CPUID register *******************/
mbed_official 497:d54623194236 1887 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
mbed_official 497:d54623194236 1888 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
mbed_official 497:d54623194236 1889 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
mbed_official 497:d54623194236 1890 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
mbed_official 497:d54623194236 1891 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
mbed_official 497:d54623194236 1892
mbed_official 497:d54623194236 1893 /******************* Bit definition for SCB_ICSR register *******************/
mbed_official 497:d54623194236 1894 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
mbed_official 497:d54623194236 1895 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
mbed_official 497:d54623194236 1896 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
mbed_official 497:d54623194236 1897 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
mbed_official 497:d54623194236 1898 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
mbed_official 497:d54623194236 1899 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
mbed_official 497:d54623194236 1900 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
mbed_official 497:d54623194236 1901 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
mbed_official 497:d54623194236 1902 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
mbed_official 497:d54623194236 1903 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
mbed_official 497:d54623194236 1904
mbed_official 497:d54623194236 1905 /******************* Bit definition for SCB_VTOR register *******************/
mbed_official 497:d54623194236 1906 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
mbed_official 497:d54623194236 1907 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
mbed_official 497:d54623194236 1908
mbed_official 497:d54623194236 1909 /*!<***************** Bit definition for SCB_AIRCR register *******************/
mbed_official 497:d54623194236 1910 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
mbed_official 497:d54623194236 1911 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
mbed_official 497:d54623194236 1912 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
mbed_official 497:d54623194236 1913
mbed_official 497:d54623194236 1914 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
mbed_official 497:d54623194236 1915 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 497:d54623194236 1916 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 497:d54623194236 1917 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 497:d54623194236 1918
mbed_official 497:d54623194236 1919 /* prority group configuration */
mbed_official 497:d54623194236 1920 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
mbed_official 497:d54623194236 1921 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
mbed_official 497:d54623194236 1922 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
mbed_official 497:d54623194236 1923 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
mbed_official 497:d54623194236 1924 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
mbed_official 497:d54623194236 1925 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
mbed_official 497:d54623194236 1926 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
mbed_official 497:d54623194236 1927 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
mbed_official 497:d54623194236 1928
mbed_official 497:d54623194236 1929 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
mbed_official 497:d54623194236 1930 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
mbed_official 497:d54623194236 1931
mbed_official 497:d54623194236 1932 /******************* Bit definition for SCB_SCR register ********************/
mbed_official 497:d54623194236 1933 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
mbed_official 497:d54623194236 1934 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
mbed_official 497:d54623194236 1935 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
mbed_official 497:d54623194236 1936
mbed_official 497:d54623194236 1937 /******************** Bit definition for SCB_CCR register *******************/
mbed_official 497:d54623194236 1938 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
mbed_official 497:d54623194236 1939 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
mbed_official 497:d54623194236 1940 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
mbed_official 497:d54623194236 1941 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
mbed_official 497:d54623194236 1942 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
mbed_official 497:d54623194236 1943 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
mbed_official 497:d54623194236 1944
mbed_official 497:d54623194236 1945 /******************* Bit definition for SCB_SHPR register ********************/
mbed_official 497:d54623194236 1946 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
mbed_official 497:d54623194236 1947 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
mbed_official 497:d54623194236 1948 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
mbed_official 497:d54623194236 1949 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
mbed_official 497:d54623194236 1950
mbed_official 497:d54623194236 1951 /****************** Bit definition for SCB_SHCSR register *******************/
mbed_official 497:d54623194236 1952 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
mbed_official 497:d54623194236 1953 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
mbed_official 497:d54623194236 1954 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
mbed_official 497:d54623194236 1955 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
mbed_official 497:d54623194236 1956 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
mbed_official 497:d54623194236 1957 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
mbed_official 497:d54623194236 1958 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
mbed_official 497:d54623194236 1959 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
mbed_official 497:d54623194236 1960 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
mbed_official 497:d54623194236 1961 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
mbed_official 497:d54623194236 1962 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
mbed_official 497:d54623194236 1963 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
mbed_official 497:d54623194236 1964 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
mbed_official 497:d54623194236 1965 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
mbed_official 497:d54623194236 1966
mbed_official 497:d54623194236 1967 /******************* Bit definition for SCB_CFSR register *******************/
mbed_official 497:d54623194236 1968 /*!< MFSR */
mbed_official 497:d54623194236 1969 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
mbed_official 497:d54623194236 1970 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
mbed_official 497:d54623194236 1971 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
mbed_official 497:d54623194236 1972 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
mbed_official 497:d54623194236 1973 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
mbed_official 497:d54623194236 1974 /*!< BFSR */
mbed_official 497:d54623194236 1975 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
mbed_official 497:d54623194236 1976 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
mbed_official 497:d54623194236 1977 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
mbed_official 497:d54623194236 1978 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
mbed_official 497:d54623194236 1979 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
mbed_official 497:d54623194236 1980 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
mbed_official 497:d54623194236 1981 /*!< UFSR */
mbed_official 497:d54623194236 1982 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
mbed_official 497:d54623194236 1983 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
mbed_official 497:d54623194236 1984 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
mbed_official 497:d54623194236 1985 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
mbed_official 497:d54623194236 1986 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
mbed_official 497:d54623194236 1987 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
mbed_official 497:d54623194236 1988
mbed_official 497:d54623194236 1989 /******************* Bit definition for SCB_HFSR register *******************/
mbed_official 497:d54623194236 1990 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
mbed_official 497:d54623194236 1991 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
mbed_official 497:d54623194236 1992 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
mbed_official 497:d54623194236 1993
mbed_official 497:d54623194236 1994 /******************* Bit definition for SCB_DFSR register *******************/
mbed_official 497:d54623194236 1995 #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
mbed_official 497:d54623194236 1996 #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
mbed_official 497:d54623194236 1997 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
mbed_official 497:d54623194236 1998 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
mbed_official 497:d54623194236 1999 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
mbed_official 497:d54623194236 2000
mbed_official 497:d54623194236 2001 /******************* Bit definition for SCB_MMFAR register ******************/
mbed_official 497:d54623194236 2002 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
mbed_official 497:d54623194236 2003
mbed_official 497:d54623194236 2004 /******************* Bit definition for SCB_BFAR register *******************/
mbed_official 497:d54623194236 2005 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
mbed_official 497:d54623194236 2006
mbed_official 497:d54623194236 2007 /******************* Bit definition for SCB_afsr register *******************/
mbed_official 497:d54623194236 2008 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
mbed_official 497:d54623194236 2009
mbed_official 497:d54623194236 2010 /******************************************************************************/
mbed_official 497:d54623194236 2011 /* */
mbed_official 497:d54623194236 2012 /* External Interrupt/Event Controller */
mbed_official 497:d54623194236 2013 /* */
mbed_official 497:d54623194236 2014 /******************************************************************************/
mbed_official 497:d54623194236 2015
mbed_official 497:d54623194236 2016 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 497:d54623194236 2017 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 497:d54623194236 2018 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 497:d54623194236 2019 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 497:d54623194236 2020 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 497:d54623194236 2021 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 497:d54623194236 2022 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 497:d54623194236 2023 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 497:d54623194236 2024 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 497:d54623194236 2025 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 497:d54623194236 2026 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 497:d54623194236 2027 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 497:d54623194236 2028 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 497:d54623194236 2029 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 497:d54623194236 2030 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 497:d54623194236 2031 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 497:d54623194236 2032 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 497:d54623194236 2033 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 497:d54623194236 2034 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 497:d54623194236 2035 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 497:d54623194236 2036 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 497:d54623194236 2037
mbed_official 497:d54623194236 2038 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 497:d54623194236 2039 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 497:d54623194236 2040 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 497:d54623194236 2041 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 497:d54623194236 2042 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 497:d54623194236 2043 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 497:d54623194236 2044 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 497:d54623194236 2045 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 497:d54623194236 2046 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 497:d54623194236 2047 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 497:d54623194236 2048 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 497:d54623194236 2049 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 497:d54623194236 2050 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 497:d54623194236 2051 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 497:d54623194236 2052 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 497:d54623194236 2053 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 497:d54623194236 2054 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 497:d54623194236 2055 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 497:d54623194236 2056 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 497:d54623194236 2057 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 497:d54623194236 2058 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 497:d54623194236 2059
mbed_official 497:d54623194236 2060 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 497:d54623194236 2061 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 497:d54623194236 2062 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 497:d54623194236 2063 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 497:d54623194236 2064 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 497:d54623194236 2065 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 497:d54623194236 2066 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 497:d54623194236 2067 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 497:d54623194236 2068 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 497:d54623194236 2069 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 497:d54623194236 2070 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 497:d54623194236 2071 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 497:d54623194236 2072 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 497:d54623194236 2073 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 497:d54623194236 2074 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 497:d54623194236 2075 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 497:d54623194236 2076 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 497:d54623194236 2077 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 497:d54623194236 2078 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 497:d54623194236 2079 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 497:d54623194236 2080 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 497:d54623194236 2081
mbed_official 497:d54623194236 2082 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 497:d54623194236 2083 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 497:d54623194236 2084 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 497:d54623194236 2085 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 497:d54623194236 2086 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 497:d54623194236 2087 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 497:d54623194236 2088 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 497:d54623194236 2089 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 497:d54623194236 2090 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 497:d54623194236 2091 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 497:d54623194236 2092 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 497:d54623194236 2093 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 497:d54623194236 2094 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 497:d54623194236 2095 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 497:d54623194236 2096 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 497:d54623194236 2097 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 497:d54623194236 2098 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 497:d54623194236 2099 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 497:d54623194236 2100 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 497:d54623194236 2101 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 497:d54623194236 2102 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 497:d54623194236 2103
mbed_official 497:d54623194236 2104 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 497:d54623194236 2105 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 497:d54623194236 2106 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 497:d54623194236 2107 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 497:d54623194236 2108 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 497:d54623194236 2109 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 497:d54623194236 2110 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 497:d54623194236 2111 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 497:d54623194236 2112 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 497:d54623194236 2113 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 497:d54623194236 2114 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 497:d54623194236 2115 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 497:d54623194236 2116 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 497:d54623194236 2117 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 497:d54623194236 2118 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 497:d54623194236 2119 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 497:d54623194236 2120 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 497:d54623194236 2121 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 497:d54623194236 2122 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 497:d54623194236 2123 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 497:d54623194236 2124 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 497:d54623194236 2125
mbed_official 497:d54623194236 2126 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 497:d54623194236 2127 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 497:d54623194236 2128 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 497:d54623194236 2129 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 497:d54623194236 2130 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 497:d54623194236 2131 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 497:d54623194236 2132 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 497:d54623194236 2133 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 497:d54623194236 2134 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 497:d54623194236 2135 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 497:d54623194236 2136 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 497:d54623194236 2137 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 497:d54623194236 2138 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 497:d54623194236 2139 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 497:d54623194236 2140 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 497:d54623194236 2141 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 497:d54623194236 2142 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 497:d54623194236 2143 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 497:d54623194236 2144 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 497:d54623194236 2145 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 497:d54623194236 2146 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 497:d54623194236 2147
mbed_official 497:d54623194236 2148 /******************************************************************************/
mbed_official 497:d54623194236 2149 /* */
mbed_official 497:d54623194236 2150 /* DMA Controller */
mbed_official 497:d54623194236 2151 /* */
mbed_official 497:d54623194236 2152 /******************************************************************************/
mbed_official 497:d54623194236 2153
mbed_official 497:d54623194236 2154 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 497:d54623194236 2155 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 497:d54623194236 2156 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 497:d54623194236 2157 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 497:d54623194236 2158 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 497:d54623194236 2159 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 497:d54623194236 2160 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 497:d54623194236 2161 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 497:d54623194236 2162 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 497:d54623194236 2163 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 497:d54623194236 2164 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 497:d54623194236 2165 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 497:d54623194236 2166 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 497:d54623194236 2167 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 497:d54623194236 2168 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 497:d54623194236 2169 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 497:d54623194236 2170 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 497:d54623194236 2171 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 497:d54623194236 2172 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 497:d54623194236 2173 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 497:d54623194236 2174 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 497:d54623194236 2175 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 497:d54623194236 2176 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 497:d54623194236 2177 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 497:d54623194236 2178 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 497:d54623194236 2179 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 497:d54623194236 2180 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 497:d54623194236 2181 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 497:d54623194236 2182 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 497:d54623194236 2183
mbed_official 497:d54623194236 2184 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 497:d54623194236 2185 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 497:d54623194236 2186 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 497:d54623194236 2187 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 497:d54623194236 2188 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 497:d54623194236 2189 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 497:d54623194236 2190 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 497:d54623194236 2191 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 497:d54623194236 2192 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 497:d54623194236 2193 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 497:d54623194236 2194 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 497:d54623194236 2195 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 497:d54623194236 2196 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 497:d54623194236 2197 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 497:d54623194236 2198 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 497:d54623194236 2199 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 497:d54623194236 2200 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 497:d54623194236 2201 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 497:d54623194236 2202 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 497:d54623194236 2203 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 497:d54623194236 2204 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 497:d54623194236 2205 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 497:d54623194236 2206 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 497:d54623194236 2207 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 497:d54623194236 2208 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 497:d54623194236 2209 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 497:d54623194236 2210 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 497:d54623194236 2211 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 497:d54623194236 2212 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 497:d54623194236 2213
mbed_official 497:d54623194236 2214 /******************* Bit definition for DMA_CCR register *******************/
mbed_official 497:d54623194236 2215 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 497:d54623194236 2216 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 497:d54623194236 2217 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 497:d54623194236 2218 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 497:d54623194236 2219 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 497:d54623194236 2220 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 497:d54623194236 2221 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 497:d54623194236 2222 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 497:d54623194236 2223
mbed_official 497:d54623194236 2224 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 497:d54623194236 2225 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 497:d54623194236 2226 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 497:d54623194236 2227
mbed_official 497:d54623194236 2228 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 497:d54623194236 2229 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 497:d54623194236 2230 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 497:d54623194236 2231
mbed_official 497:d54623194236 2232 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
mbed_official 497:d54623194236 2233 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 497:d54623194236 2234 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 497:d54623194236 2235
mbed_official 497:d54623194236 2236 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 497:d54623194236 2237
mbed_official 497:d54623194236 2238 /****************** Bit definition for DMA_CNDTR register ******************/
mbed_official 497:d54623194236 2239 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 497:d54623194236 2240
mbed_official 497:d54623194236 2241 /****************** Bit definition for DMA_CPAR register *******************/
mbed_official 497:d54623194236 2242 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 497:d54623194236 2243
mbed_official 497:d54623194236 2244 /****************** Bit definition for DMA_CMAR register *******************/
mbed_official 497:d54623194236 2245 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 497:d54623194236 2246
mbed_official 497:d54623194236 2247 /******************************************************************************/
mbed_official 497:d54623194236 2248 /* */
mbed_official 497:d54623194236 2249 /* Analog to Digital Converter */
mbed_official 497:d54623194236 2250 /* */
mbed_official 497:d54623194236 2251 /******************************************************************************/
mbed_official 497:d54623194236 2252
mbed_official 497:d54623194236 2253 /******************** Bit definition for ADC_SR register ********************/
mbed_official 497:d54623194236 2254 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
mbed_official 497:d54623194236 2255 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
mbed_official 497:d54623194236 2256 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
mbed_official 497:d54623194236 2257 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
mbed_official 497:d54623194236 2258 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
mbed_official 497:d54623194236 2259
mbed_official 497:d54623194236 2260 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 497:d54623194236 2261 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 497:d54623194236 2262 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 2263 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 2264 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 2265 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 2266 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 2267
mbed_official 497:d54623194236 2268 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
mbed_official 497:d54623194236 2269 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
mbed_official 497:d54623194236 2270 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
mbed_official 497:d54623194236 2271 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
mbed_official 497:d54623194236 2272 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
mbed_official 497:d54623194236 2273 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
mbed_official 497:d54623194236 2274 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
mbed_official 497:d54623194236 2275 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
mbed_official 497:d54623194236 2276
mbed_official 497:d54623194236 2277 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 497:d54623194236 2278 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 497:d54623194236 2279 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 497:d54623194236 2280 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 497:d54623194236 2281
mbed_official 497:d54623194236 2282 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
mbed_official 497:d54623194236 2283 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
mbed_official 497:d54623194236 2284
mbed_official 497:d54623194236 2285
mbed_official 497:d54623194236 2286 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 497:d54623194236 2287 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
mbed_official 497:d54623194236 2288 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
mbed_official 497:d54623194236 2289 #define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
mbed_official 497:d54623194236 2290 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
mbed_official 497:d54623194236 2291 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
mbed_official 497:d54623194236 2292 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
mbed_official 497:d54623194236 2293
mbed_official 497:d54623194236 2294 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
mbed_official 497:d54623194236 2295 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 497:d54623194236 2296 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 497:d54623194236 2297 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 497:d54623194236 2298
mbed_official 497:d54623194236 2299 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
mbed_official 497:d54623194236 2300
mbed_official 497:d54623194236 2301 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
mbed_official 497:d54623194236 2302 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 497:d54623194236 2303 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 497:d54623194236 2304 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 497:d54623194236 2305
mbed_official 497:d54623194236 2306 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
mbed_official 497:d54623194236 2307 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
mbed_official 497:d54623194236 2308 #define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
mbed_official 497:d54623194236 2309 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
mbed_official 497:d54623194236 2310
mbed_official 497:d54623194236 2311 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 497:d54623194236 2312 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 497:d54623194236 2313 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 2314 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 2315 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 2316
mbed_official 497:d54623194236 2317 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 497:d54623194236 2318 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 497:d54623194236 2319 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 497:d54623194236 2320 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 497:d54623194236 2321
mbed_official 497:d54623194236 2322 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 497:d54623194236 2323 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 497:d54623194236 2324 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 497:d54623194236 2325 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 497:d54623194236 2326
mbed_official 497:d54623194236 2327 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 497:d54623194236 2328 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 497:d54623194236 2329 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 497:d54623194236 2330 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 497:d54623194236 2331
mbed_official 497:d54623194236 2332 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 497:d54623194236 2333 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 497:d54623194236 2334 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 497:d54623194236 2335 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 497:d54623194236 2336
mbed_official 497:d54623194236 2337 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
mbed_official 497:d54623194236 2338 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 497:d54623194236 2339 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 497:d54623194236 2340 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 497:d54623194236 2341
mbed_official 497:d54623194236 2342 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 497:d54623194236 2343 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 497:d54623194236 2344 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 497:d54623194236 2345 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 497:d54623194236 2346
mbed_official 497:d54623194236 2347 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 497:d54623194236 2348 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 497:d54623194236 2349 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 497:d54623194236 2350 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 497:d54623194236 2351
mbed_official 497:d54623194236 2352 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 497:d54623194236 2353 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 497:d54623194236 2354 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 2355 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 2356 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 2357
mbed_official 497:d54623194236 2358 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 497:d54623194236 2359 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 497:d54623194236 2360 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 497:d54623194236 2361 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 497:d54623194236 2362
mbed_official 497:d54623194236 2363 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 497:d54623194236 2364 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 497:d54623194236 2365 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 497:d54623194236 2366 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 497:d54623194236 2367
mbed_official 497:d54623194236 2368 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 497:d54623194236 2369 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 497:d54623194236 2370 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 497:d54623194236 2371 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 497:d54623194236 2372
mbed_official 497:d54623194236 2373 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 497:d54623194236 2374 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 497:d54623194236 2375 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 497:d54623194236 2376 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 497:d54623194236 2377
mbed_official 497:d54623194236 2378 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 497:d54623194236 2379 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 497:d54623194236 2380 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 497:d54623194236 2381 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 497:d54623194236 2382
mbed_official 497:d54623194236 2383 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 497:d54623194236 2384 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 497:d54623194236 2385 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 497:d54623194236 2386 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 497:d54623194236 2387
mbed_official 497:d54623194236 2388 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 497:d54623194236 2389 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 497:d54623194236 2390 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 497:d54623194236 2391 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 497:d54623194236 2392
mbed_official 497:d54623194236 2393 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 497:d54623194236 2394 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 497:d54623194236 2395 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 497:d54623194236 2396 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 497:d54623194236 2397
mbed_official 497:d54623194236 2398 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 497:d54623194236 2399 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
mbed_official 497:d54623194236 2400 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
mbed_official 497:d54623194236 2401 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
mbed_official 497:d54623194236 2402
mbed_official 497:d54623194236 2403 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 497:d54623194236 2404 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
mbed_official 497:d54623194236 2405
mbed_official 497:d54623194236 2406 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 497:d54623194236 2407 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
mbed_official 497:d54623194236 2408
mbed_official 497:d54623194236 2409 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 497:d54623194236 2410 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
mbed_official 497:d54623194236 2411
mbed_official 497:d54623194236 2412 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 497:d54623194236 2413 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
mbed_official 497:d54623194236 2414
mbed_official 497:d54623194236 2415 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 497:d54623194236 2416 #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
mbed_official 497:d54623194236 2417
mbed_official 497:d54623194236 2418 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 497:d54623194236 2419 #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
mbed_official 497:d54623194236 2420
mbed_official 497:d54623194236 2421 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 497:d54623194236 2422 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 497:d54623194236 2423 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 2424 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 2425 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 2426 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 2427 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 2428
mbed_official 497:d54623194236 2429 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 497:d54623194236 2430 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 497:d54623194236 2431 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 497:d54623194236 2432 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 497:d54623194236 2433 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 497:d54623194236 2434 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 497:d54623194236 2435
mbed_official 497:d54623194236 2436 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 497:d54623194236 2437 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 497:d54623194236 2438 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 497:d54623194236 2439 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 497:d54623194236 2440 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 497:d54623194236 2441 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 497:d54623194236 2442
mbed_official 497:d54623194236 2443 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 497:d54623194236 2444 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 497:d54623194236 2445 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 497:d54623194236 2446 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 497:d54623194236 2447 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 497:d54623194236 2448 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 497:d54623194236 2449
mbed_official 497:d54623194236 2450 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
mbed_official 497:d54623194236 2451 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 497:d54623194236 2452 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 497:d54623194236 2453 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 497:d54623194236 2454 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 497:d54623194236 2455
mbed_official 497:d54623194236 2456 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 497:d54623194236 2457 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 497:d54623194236 2458 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 2459 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 2460 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 2461 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 2462 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 2463
mbed_official 497:d54623194236 2464 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 497:d54623194236 2465 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 497:d54623194236 2466 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 497:d54623194236 2467 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 497:d54623194236 2468 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 497:d54623194236 2469 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 497:d54623194236 2470
mbed_official 497:d54623194236 2471 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 497:d54623194236 2472 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 497:d54623194236 2473 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 497:d54623194236 2474 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 497:d54623194236 2475 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 497:d54623194236 2476 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 497:d54623194236 2477
mbed_official 497:d54623194236 2478 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 497:d54623194236 2479 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 497:d54623194236 2480 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 497:d54623194236 2481 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 497:d54623194236 2482 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 497:d54623194236 2483 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 497:d54623194236 2484
mbed_official 497:d54623194236 2485 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 497:d54623194236 2486 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 497:d54623194236 2487 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 497:d54623194236 2488 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 497:d54623194236 2489 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 497:d54623194236 2490 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 497:d54623194236 2491
mbed_official 497:d54623194236 2492 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 497:d54623194236 2493 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 497:d54623194236 2494 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 497:d54623194236 2495 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 497:d54623194236 2496 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 497:d54623194236 2497 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 497:d54623194236 2498
mbed_official 497:d54623194236 2499 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 497:d54623194236 2500 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 497:d54623194236 2501 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 2502 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 2503 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 2504 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 2505 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 2506
mbed_official 497:d54623194236 2507 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 497:d54623194236 2508 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 497:d54623194236 2509 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 497:d54623194236 2510 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 497:d54623194236 2511 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 497:d54623194236 2512 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 497:d54623194236 2513
mbed_official 497:d54623194236 2514 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 497:d54623194236 2515 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 497:d54623194236 2516 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 497:d54623194236 2517 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 497:d54623194236 2518 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 497:d54623194236 2519 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 497:d54623194236 2520
mbed_official 497:d54623194236 2521 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 497:d54623194236 2522 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 497:d54623194236 2523 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 497:d54623194236 2524 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 497:d54623194236 2525 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 497:d54623194236 2526 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 497:d54623194236 2527
mbed_official 497:d54623194236 2528 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 497:d54623194236 2529 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 497:d54623194236 2530 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 497:d54623194236 2531 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 497:d54623194236 2532 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 497:d54623194236 2533 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 497:d54623194236 2534
mbed_official 497:d54623194236 2535 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 497:d54623194236 2536 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 497:d54623194236 2537 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 497:d54623194236 2538 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 497:d54623194236 2539 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 497:d54623194236 2540 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 497:d54623194236 2541
mbed_official 497:d54623194236 2542 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 497:d54623194236 2543 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 497:d54623194236 2544 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 2545 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 2546 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 2547 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 2548 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 2549
mbed_official 497:d54623194236 2550 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 497:d54623194236 2551 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 497:d54623194236 2552 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 497:d54623194236 2553 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 497:d54623194236 2554 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 497:d54623194236 2555 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 497:d54623194236 2556
mbed_official 497:d54623194236 2557 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 497:d54623194236 2558 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 497:d54623194236 2559 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 497:d54623194236 2560 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 497:d54623194236 2561 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 497:d54623194236 2562 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 497:d54623194236 2563
mbed_official 497:d54623194236 2564 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 497:d54623194236 2565 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 497:d54623194236 2566 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 497:d54623194236 2567 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 497:d54623194236 2568 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 497:d54623194236 2569 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 497:d54623194236 2570
mbed_official 497:d54623194236 2571 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
mbed_official 497:d54623194236 2572 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 497:d54623194236 2573 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 497:d54623194236 2574
mbed_official 497:d54623194236 2575 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 497:d54623194236 2576 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 497:d54623194236 2577
mbed_official 497:d54623194236 2578 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 497:d54623194236 2579 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 497:d54623194236 2580
mbed_official 497:d54623194236 2581 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 497:d54623194236 2582 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 497:d54623194236 2583
mbed_official 497:d54623194236 2584 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 497:d54623194236 2585 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 497:d54623194236 2586
mbed_official 497:d54623194236 2587 /******************** Bit definition for ADC_DR register ********************/
mbed_official 497:d54623194236 2588 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
mbed_official 497:d54623194236 2589 /******************************************************************************/
mbed_official 497:d54623194236 2590 /* */
mbed_official 497:d54623194236 2591 /* Digital to Analog Converter */
mbed_official 497:d54623194236 2592 /* */
mbed_official 497:d54623194236 2593 /******************************************************************************/
mbed_official 497:d54623194236 2594
mbed_official 497:d54623194236 2595 /******************** Bit definition for DAC_CR register ********************/
mbed_official 497:d54623194236 2596 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 497:d54623194236 2597 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 497:d54623194236 2598 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 497:d54623194236 2599
mbed_official 497:d54623194236 2600 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 497:d54623194236 2601 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 497:d54623194236 2602 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 497:d54623194236 2603 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 497:d54623194236 2604
mbed_official 497:d54623194236 2605 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 497:d54623194236 2606 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 497:d54623194236 2607 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 497:d54623194236 2608
mbed_official 497:d54623194236 2609 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 497:d54623194236 2610 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 497:d54623194236 2611 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 497:d54623194236 2612 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 497:d54623194236 2613 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 497:d54623194236 2614
mbed_official 497:d54623194236 2615 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 497:d54623194236 2616 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 497:d54623194236 2617 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 497:d54623194236 2618 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 497:d54623194236 2619
mbed_official 497:d54623194236 2620 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 497:d54623194236 2621 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 497:d54623194236 2622 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 497:d54623194236 2623 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 497:d54623194236 2624
mbed_official 497:d54623194236 2625 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 497:d54623194236 2626 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 497:d54623194236 2627 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 497:d54623194236 2628
mbed_official 497:d54623194236 2629 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 497:d54623194236 2630 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 497:d54623194236 2631 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 497:d54623194236 2632 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 497:d54623194236 2633 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 497:d54623194236 2634
mbed_official 497:d54623194236 2635 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 497:d54623194236 2636
mbed_official 497:d54623194236 2637 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */
mbed_official 497:d54623194236 2638 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */
mbed_official 497:d54623194236 2639
mbed_official 497:d54623194236 2640 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 497:d54623194236 2641 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
mbed_official 497:d54623194236 2642 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
mbed_official 497:d54623194236 2643
mbed_official 497:d54623194236 2644 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 497:d54623194236 2645 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 497:d54623194236 2646
mbed_official 497:d54623194236 2647 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 497:d54623194236 2648 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 497:d54623194236 2649
mbed_official 497:d54623194236 2650 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 497:d54623194236 2651 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 497:d54623194236 2652
mbed_official 497:d54623194236 2653 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 497:d54623194236 2654 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 497:d54623194236 2655
mbed_official 497:d54623194236 2656 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 497:d54623194236 2657 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 497:d54623194236 2658
mbed_official 497:d54623194236 2659 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 497:d54623194236 2660 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 497:d54623194236 2661
mbed_official 497:d54623194236 2662 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 497:d54623194236 2663 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 497:d54623194236 2664 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 497:d54623194236 2665
mbed_official 497:d54623194236 2666 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 497:d54623194236 2667 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 497:d54623194236 2668 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 497:d54623194236 2669
mbed_official 497:d54623194236 2670 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 497:d54623194236 2671 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 497:d54623194236 2672 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 497:d54623194236 2673
mbed_official 497:d54623194236 2674 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 497:d54623194236 2675 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
mbed_official 497:d54623194236 2676
mbed_official 497:d54623194236 2677 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 497:d54623194236 2678 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
mbed_official 497:d54623194236 2679
mbed_official 497:d54623194236 2680 /******************** Bit definition for DAC_SR register ********************/
mbed_official 497:d54623194236 2681 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 497:d54623194236 2682 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
mbed_official 497:d54623194236 2683
mbed_official 497:d54623194236 2684 /******************************************************************************/
mbed_official 497:d54623194236 2685 /* */
mbed_official 497:d54623194236 2686 /* CEC */
mbed_official 497:d54623194236 2687 /* */
mbed_official 497:d54623194236 2688 /******************************************************************************/
mbed_official 497:d54623194236 2689 /******************** Bit definition for CEC_CFGR register ******************/
mbed_official 497:d54623194236 2690 #define CEC_CFGR_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
mbed_official 497:d54623194236 2691 #define CEC_CFGR_IE ((uint32_t)0x00000002) /*!< Interrupt Enable */
mbed_official 497:d54623194236 2692 #define CEC_CFGR_BTEM ((uint32_t)0x00000004) /*!< Bit Timing Error Mode */
mbed_official 497:d54623194236 2693 #define CEC_CFGR_BPEM ((uint32_t)0x00000008) /*!< Bit Period Error Mode */
mbed_official 497:d54623194236 2694
mbed_official 497:d54623194236 2695 /******************** Bit definition for CEC_OAR register ******************/
mbed_official 497:d54623194236 2696 #define CEC_OAR_OA ((uint32_t)0x0000000F) /*!< OA[3:0]: Own Address */
mbed_official 497:d54623194236 2697 #define CEC_OAR_OA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 2698 #define CEC_OAR_OA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 2699 #define CEC_OAR_OA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 2700 #define CEC_OAR_OA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 2701
mbed_official 497:d54623194236 2702 /******************** Bit definition for CEC_PRES register ******************/
mbed_official 497:d54623194236 2703 #define CEC_PRES_PRES ((uint32_t)0x00003FFF) /*!< Prescaler Counter Value */
mbed_official 497:d54623194236 2704
mbed_official 497:d54623194236 2705 /******************** Bit definition for CEC_ESR register ******************/
mbed_official 497:d54623194236 2706 #define CEC_ESR_BTE ((uint32_t)0x00000001) /*!< Bit Timing Error */
mbed_official 497:d54623194236 2707 #define CEC_ESR_BPE ((uint32_t)0x00000002) /*!< Bit Period Error */
mbed_official 497:d54623194236 2708 #define CEC_ESR_RBTFE ((uint32_t)0x00000004) /*!< Rx Block Transfer Finished Error */
mbed_official 497:d54623194236 2709 #define CEC_ESR_SBE ((uint32_t)0x00000008) /*!< Start Bit Error */
mbed_official 497:d54623194236 2710 #define CEC_ESR_ACKE ((uint32_t)0x00000010) /*!< Block Acknowledge Error */
mbed_official 497:d54623194236 2711 #define CEC_ESR_LINE ((uint32_t)0x00000020) /*!< Line Error */
mbed_official 497:d54623194236 2712 #define CEC_ESR_TBTFE ((uint32_t)0x00000040) /*!< Tx Block Transfer Finished Error */
mbed_official 497:d54623194236 2713
mbed_official 497:d54623194236 2714 /******************** Bit definition for CEC_CSR register ******************/
mbed_official 497:d54623194236 2715 #define CEC_CSR_TSOM ((uint32_t)0x00000001) /*!< Tx Start Of Message */
mbed_official 497:d54623194236 2716 #define CEC_CSR_TEOM ((uint32_t)0x00000002) /*!< Tx End Of Message */
mbed_official 497:d54623194236 2717 #define CEC_CSR_TERR ((uint32_t)0x00000004) /*!< Tx Error */
mbed_official 497:d54623194236 2718 #define CEC_CSR_TBTRF ((uint32_t)0x00000008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
mbed_official 497:d54623194236 2719 #define CEC_CSR_RSOM ((uint32_t)0x00000010) /*!< Rx Start Of Message */
mbed_official 497:d54623194236 2720 #define CEC_CSR_REOM ((uint32_t)0x00000020) /*!< Rx End Of Message */
mbed_official 497:d54623194236 2721 #define CEC_CSR_RERR ((uint32_t)0x00000040) /*!< Rx Error */
mbed_official 497:d54623194236 2722 #define CEC_CSR_RBTF ((uint32_t)0x00000080) /*!< Rx Block Transfer Finished */
mbed_official 497:d54623194236 2723
mbed_official 497:d54623194236 2724 /******************** Bit definition for CEC_TXD register ******************/
mbed_official 497:d54623194236 2725 #define CEC_TXD_TXD ((uint32_t)0x000000FF) /*!< Tx Data register */
mbed_official 497:d54623194236 2726
mbed_official 497:d54623194236 2727 /******************** Bit definition for CEC_RXD register ******************/
mbed_official 497:d54623194236 2728 #define CEC_RXD_RXD ((uint32_t)0x000000FF) /*!< Rx Data register */
mbed_official 497:d54623194236 2729
mbed_official 497:d54623194236 2730 /*****************************************************************************/
mbed_official 497:d54623194236 2731 /* */
mbed_official 497:d54623194236 2732 /* Timers (TIM) */
mbed_official 497:d54623194236 2733 /* */
mbed_official 497:d54623194236 2734 /*****************************************************************************/
mbed_official 497:d54623194236 2735 /******************* Bit definition for TIM_CR1 register *******************/
mbed_official 497:d54623194236 2736 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 497:d54623194236 2737 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 497:d54623194236 2738 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 497:d54623194236 2739 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 497:d54623194236 2740 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 497:d54623194236 2741
mbed_official 497:d54623194236 2742 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 497:d54623194236 2743 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 497:d54623194236 2744 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 497:d54623194236 2745
mbed_official 497:d54623194236 2746 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 497:d54623194236 2747
mbed_official 497:d54623194236 2748 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 497:d54623194236 2749 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 497:d54623194236 2750 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 497:d54623194236 2751
mbed_official 497:d54623194236 2752 /******************* Bit definition for TIM_CR2 register *******************/
mbed_official 497:d54623194236 2753 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 497:d54623194236 2754 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 497:d54623194236 2755 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 497:d54623194236 2756
mbed_official 497:d54623194236 2757 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 497:d54623194236 2758 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 497:d54623194236 2759 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 497:d54623194236 2760 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 497:d54623194236 2761
mbed_official 497:d54623194236 2762 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 497:d54623194236 2763 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 497:d54623194236 2764 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 497:d54623194236 2765 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 497:d54623194236 2766 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 497:d54623194236 2767 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 497:d54623194236 2768 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 497:d54623194236 2769 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 497:d54623194236 2770
mbed_official 497:d54623194236 2771 /******************* Bit definition for TIM_SMCR register ******************/
mbed_official 497:d54623194236 2772 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 497:d54623194236 2773 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 497:d54623194236 2774 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 497:d54623194236 2775 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 497:d54623194236 2776
mbed_official 497:d54623194236 2777 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 497:d54623194236 2778
mbed_official 497:d54623194236 2779 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 497:d54623194236 2780 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 497:d54623194236 2781 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 497:d54623194236 2782 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 497:d54623194236 2783
mbed_official 497:d54623194236 2784 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 497:d54623194236 2785
mbed_official 497:d54623194236 2786 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 497:d54623194236 2787 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 497:d54623194236 2788 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 497:d54623194236 2789 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 497:d54623194236 2790 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 497:d54623194236 2791
mbed_official 497:d54623194236 2792 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 497:d54623194236 2793 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 497:d54623194236 2794 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 497:d54623194236 2795
mbed_official 497:d54623194236 2796 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 497:d54623194236 2797 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 497:d54623194236 2798
mbed_official 497:d54623194236 2799 /******************* Bit definition for TIM_DIER register ******************/
mbed_official 497:d54623194236 2800 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 497:d54623194236 2801 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 497:d54623194236 2802 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 497:d54623194236 2803 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 497:d54623194236 2804 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 497:d54623194236 2805 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
mbed_official 497:d54623194236 2806 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 497:d54623194236 2807 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
mbed_official 497:d54623194236 2808 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 497:d54623194236 2809 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 497:d54623194236 2810 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 497:d54623194236 2811 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 497:d54623194236 2812 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 497:d54623194236 2813 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
mbed_official 497:d54623194236 2814 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 497:d54623194236 2815
mbed_official 497:d54623194236 2816 /******************** Bit definition for TIM_SR register *******************/
mbed_official 497:d54623194236 2817 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 497:d54623194236 2818 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 497:d54623194236 2819 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 497:d54623194236 2820 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 497:d54623194236 2821 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 497:d54623194236 2822 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
mbed_official 497:d54623194236 2823 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 497:d54623194236 2824 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
mbed_official 497:d54623194236 2825 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 497:d54623194236 2826 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 497:d54623194236 2827 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 497:d54623194236 2828 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 497:d54623194236 2829
mbed_official 497:d54623194236 2830 /******************* Bit definition for TIM_EGR register *******************/
mbed_official 497:d54623194236 2831 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 497:d54623194236 2832 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 497:d54623194236 2833 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 497:d54623194236 2834 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 497:d54623194236 2835 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 497:d54623194236 2836 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
mbed_official 497:d54623194236 2837 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 497:d54623194236 2838 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
mbed_official 497:d54623194236 2839
mbed_official 497:d54623194236 2840 /****************** Bit definition for TIM_CCMR1 register ******************/
mbed_official 497:d54623194236 2841 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 497:d54623194236 2842 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 497:d54623194236 2843 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 497:d54623194236 2844
mbed_official 497:d54623194236 2845 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 497:d54623194236 2846 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 497:d54623194236 2847
mbed_official 497:d54623194236 2848 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 497:d54623194236 2849 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 497:d54623194236 2850 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 497:d54623194236 2851 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 497:d54623194236 2852
mbed_official 497:d54623194236 2853 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 497:d54623194236 2854
mbed_official 497:d54623194236 2855 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 497:d54623194236 2856 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 497:d54623194236 2857 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 497:d54623194236 2858
mbed_official 497:d54623194236 2859 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 497:d54623194236 2860 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 497:d54623194236 2861
mbed_official 497:d54623194236 2862 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 497:d54623194236 2863 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 497:d54623194236 2864 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 497:d54623194236 2865 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 497:d54623194236 2866
mbed_official 497:d54623194236 2867 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 497:d54623194236 2868
mbed_official 497:d54623194236 2869 /*---------------------------------------------------------------------------*/
mbed_official 497:d54623194236 2870
mbed_official 497:d54623194236 2871 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 497:d54623194236 2872 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 497:d54623194236 2873 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 497:d54623194236 2874
mbed_official 497:d54623194236 2875 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 497:d54623194236 2876 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 497:d54623194236 2877 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 497:d54623194236 2878 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 497:d54623194236 2879 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 497:d54623194236 2880
mbed_official 497:d54623194236 2881 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 497:d54623194236 2882 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 497:d54623194236 2883 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 497:d54623194236 2884
mbed_official 497:d54623194236 2885 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 497:d54623194236 2886 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 497:d54623194236 2887 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 497:d54623194236 2888 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 497:d54623194236 2889 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 497:d54623194236 2890
mbed_official 497:d54623194236 2891 /****************** Bit definition for TIM_CCMR2 register ******************/
mbed_official 497:d54623194236 2892 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 497:d54623194236 2893 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 497:d54623194236 2894 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 497:d54623194236 2895
mbed_official 497:d54623194236 2896 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 497:d54623194236 2897 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 497:d54623194236 2898
mbed_official 497:d54623194236 2899 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 497:d54623194236 2900 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 497:d54623194236 2901 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 497:d54623194236 2902 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 497:d54623194236 2903
mbed_official 497:d54623194236 2904 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 497:d54623194236 2905
mbed_official 497:d54623194236 2906 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 497:d54623194236 2907 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 497:d54623194236 2908 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 497:d54623194236 2909
mbed_official 497:d54623194236 2910 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 497:d54623194236 2911 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 497:d54623194236 2912
mbed_official 497:d54623194236 2913 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 497:d54623194236 2914 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 497:d54623194236 2915 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 497:d54623194236 2916 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 497:d54623194236 2917
mbed_official 497:d54623194236 2918 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 497:d54623194236 2919
mbed_official 497:d54623194236 2920 /*---------------------------------------------------------------------------*/
mbed_official 497:d54623194236 2921
mbed_official 497:d54623194236 2922 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 497:d54623194236 2923 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 497:d54623194236 2924 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 497:d54623194236 2925
mbed_official 497:d54623194236 2926 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 497:d54623194236 2927 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 497:d54623194236 2928 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 497:d54623194236 2929 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 497:d54623194236 2930 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 497:d54623194236 2931
mbed_official 497:d54623194236 2932 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 497:d54623194236 2933 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 497:d54623194236 2934 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 497:d54623194236 2935
mbed_official 497:d54623194236 2936 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 497:d54623194236 2937 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 497:d54623194236 2938 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 497:d54623194236 2939 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 497:d54623194236 2940 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 497:d54623194236 2941
mbed_official 497:d54623194236 2942 /******************* Bit definition for TIM_CCER register ******************/
mbed_official 497:d54623194236 2943 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 497:d54623194236 2944 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 497:d54623194236 2945 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 497:d54623194236 2946 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 497:d54623194236 2947 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 497:d54623194236 2948 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 497:d54623194236 2949 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 497:d54623194236 2950 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 497:d54623194236 2951 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 497:d54623194236 2952 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 497:d54623194236 2953 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 497:d54623194236 2954 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 497:d54623194236 2955 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 497:d54623194236 2956 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 497:d54623194236 2957 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 497:d54623194236 2958
mbed_official 497:d54623194236 2959 /******************* Bit definition for TIM_CNT register *******************/
mbed_official 497:d54623194236 2960 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 497:d54623194236 2961
mbed_official 497:d54623194236 2962 /******************* Bit definition for TIM_PSC register *******************/
mbed_official 497:d54623194236 2963 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 497:d54623194236 2964
mbed_official 497:d54623194236 2965 /******************* Bit definition for TIM_ARR register *******************/
mbed_official 497:d54623194236 2966 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
mbed_official 497:d54623194236 2967
mbed_official 497:d54623194236 2968 /******************* Bit definition for TIM_RCR register *******************/
mbed_official 497:d54623194236 2969 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
mbed_official 497:d54623194236 2970
mbed_official 497:d54623194236 2971 /******************* Bit definition for TIM_CCR1 register ******************/
mbed_official 497:d54623194236 2972 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 497:d54623194236 2973
mbed_official 497:d54623194236 2974 /******************* Bit definition for TIM_CCR2 register ******************/
mbed_official 497:d54623194236 2975 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 497:d54623194236 2976
mbed_official 497:d54623194236 2977 /******************* Bit definition for TIM_CCR3 register ******************/
mbed_official 497:d54623194236 2978 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 497:d54623194236 2979
mbed_official 497:d54623194236 2980 /******************* Bit definition for TIM_CCR4 register ******************/
mbed_official 497:d54623194236 2981 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 497:d54623194236 2982
mbed_official 497:d54623194236 2983 /******************* Bit definition for TIM_BDTR register ******************/
mbed_official 497:d54623194236 2984 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 497:d54623194236 2985 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 497:d54623194236 2986 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 497:d54623194236 2987 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 497:d54623194236 2988 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 497:d54623194236 2989 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 497:d54623194236 2990 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 497:d54623194236 2991 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 497:d54623194236 2992 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 497:d54623194236 2993
mbed_official 497:d54623194236 2994 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 497:d54623194236 2995 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 497:d54623194236 2996 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 497:d54623194236 2997
mbed_official 497:d54623194236 2998 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 497:d54623194236 2999 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 497:d54623194236 3000 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
mbed_official 497:d54623194236 3001 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
mbed_official 497:d54623194236 3002 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 497:d54623194236 3003 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 497:d54623194236 3004
mbed_official 497:d54623194236 3005 /******************* Bit definition for TIM_DCR register *******************/
mbed_official 497:d54623194236 3006 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 497:d54623194236 3007 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 497:d54623194236 3008 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 497:d54623194236 3009 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 497:d54623194236 3010 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 497:d54623194236 3011 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 497:d54623194236 3012
mbed_official 497:d54623194236 3013 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 497:d54623194236 3014 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 497:d54623194236 3015 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 497:d54623194236 3016 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 497:d54623194236 3017 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 497:d54623194236 3018 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 497:d54623194236 3019
mbed_official 497:d54623194236 3020 /******************* Bit definition for TIM_DMAR register ******************/
mbed_official 497:d54623194236 3021 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 497:d54623194236 3022
mbed_official 497:d54623194236 3023 /******************* Bit definition for TIM_OR register ********************/
mbed_official 497:d54623194236 3024
mbed_official 497:d54623194236 3025 /******************************************************************************/
mbed_official 497:d54623194236 3026 /* */
mbed_official 497:d54623194236 3027 /* Real-Time Clock */
mbed_official 497:d54623194236 3028 /* */
mbed_official 497:d54623194236 3029 /******************************************************************************/
mbed_official 497:d54623194236 3030
mbed_official 497:d54623194236 3031 /******************* Bit definition for RTC_CRH register ********************/
mbed_official 497:d54623194236 3032 #define RTC_CRH_SECIE ((uint32_t)0x00000001) /*!< Second Interrupt Enable */
mbed_official 497:d54623194236 3033 #define RTC_CRH_ALRIE ((uint32_t)0x00000002) /*!< Alarm Interrupt Enable */
mbed_official 497:d54623194236 3034 #define RTC_CRH_OWIE ((uint32_t)0x00000004) /*!< OverfloW Interrupt Enable */
mbed_official 497:d54623194236 3035
mbed_official 497:d54623194236 3036 /******************* Bit definition for RTC_CRL register ********************/
mbed_official 497:d54623194236 3037 #define RTC_CRL_SECF ((uint32_t)0x00000001) /*!< Second Flag */
mbed_official 497:d54623194236 3038 #define RTC_CRL_ALRF ((uint32_t)0x00000002) /*!< Alarm Flag */
mbed_official 497:d54623194236 3039 #define RTC_CRL_OWF ((uint32_t)0x00000004) /*!< OverfloW Flag */
mbed_official 497:d54623194236 3040 #define RTC_CRL_RSF ((uint32_t)0x00000008) /*!< Registers Synchronized Flag */
mbed_official 497:d54623194236 3041 #define RTC_CRL_CNF ((uint32_t)0x00000010) /*!< Configuration Flag */
mbed_official 497:d54623194236 3042 #define RTC_CRL_RTOFF ((uint32_t)0x00000020) /*!< RTC operation OFF */
mbed_official 497:d54623194236 3043
mbed_official 497:d54623194236 3044 /******************* Bit definition for RTC_PRLH register *******************/
mbed_official 497:d54623194236 3045 #define RTC_PRLH_PRL ((uint32_t)0x0000000F) /*!< RTC Prescaler Reload Value High */
mbed_official 497:d54623194236 3046
mbed_official 497:d54623194236 3047 /******************* Bit definition for RTC_PRLL register *******************/
mbed_official 497:d54623194236 3048 #define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /*!< RTC Prescaler Reload Value Low */
mbed_official 497:d54623194236 3049
mbed_official 497:d54623194236 3050 /******************* Bit definition for RTC_DIVH register *******************/
mbed_official 497:d54623194236 3051 #define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /*!< RTC Clock Divider High */
mbed_official 497:d54623194236 3052
mbed_official 497:d54623194236 3053 /******************* Bit definition for RTC_DIVL register *******************/
mbed_official 497:d54623194236 3054 #define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /*!< RTC Clock Divider Low */
mbed_official 497:d54623194236 3055
mbed_official 497:d54623194236 3056 /******************* Bit definition for RTC_CNTH register *******************/
mbed_official 497:d54623194236 3057 #define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter High */
mbed_official 497:d54623194236 3058
mbed_official 497:d54623194236 3059 /******************* Bit definition for RTC_CNTL register *******************/
mbed_official 497:d54623194236 3060 #define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter Low */
mbed_official 497:d54623194236 3061
mbed_official 497:d54623194236 3062 /******************* Bit definition for RTC_ALRH register *******************/
mbed_official 497:d54623194236 3063 #define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm High */
mbed_official 497:d54623194236 3064
mbed_official 497:d54623194236 3065 /******************* Bit definition for RTC_ALRL register *******************/
mbed_official 497:d54623194236 3066 #define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm Low */
mbed_official 497:d54623194236 3067
mbed_official 497:d54623194236 3068 /******************************************************************************/
mbed_official 497:d54623194236 3069 /* */
mbed_official 497:d54623194236 3070 /* Independent WATCHDOG (IWDG) */
mbed_official 497:d54623194236 3071 /* */
mbed_official 497:d54623194236 3072 /******************************************************************************/
mbed_official 497:d54623194236 3073
mbed_official 497:d54623194236 3074 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 497:d54623194236 3075 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
mbed_official 497:d54623194236 3076
mbed_official 497:d54623194236 3077 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 497:d54623194236 3078 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
mbed_official 497:d54623194236 3079 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 3080 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 3081 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 3082
mbed_official 497:d54623194236 3083 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 497:d54623194236 3084 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
mbed_official 497:d54623194236 3085
mbed_official 497:d54623194236 3086 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 497:d54623194236 3087 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
mbed_official 497:d54623194236 3088 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
mbed_official 497:d54623194236 3089
mbed_official 497:d54623194236 3090 /******************************************************************************/
mbed_official 497:d54623194236 3091 /* */
mbed_official 497:d54623194236 3092 /* Window WATCHDOG */
mbed_official 497:d54623194236 3093 /* */
mbed_official 497:d54623194236 3094 /******************************************************************************/
mbed_official 497:d54623194236 3095
mbed_official 497:d54623194236 3096 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 497:d54623194236 3097 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 497:d54623194236 3098 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 3099 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 3100 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 3101 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 3102 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 3103 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 497:d54623194236 3104 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 497:d54623194236 3105
mbed_official 497:d54623194236 3106 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
mbed_official 497:d54623194236 3107
mbed_official 497:d54623194236 3108 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 497:d54623194236 3109 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
mbed_official 497:d54623194236 3110 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 3111 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 3112 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 3113 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 3114 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 3115 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 497:d54623194236 3116 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 497:d54623194236 3117
mbed_official 497:d54623194236 3118 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
mbed_official 497:d54623194236 3119 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
mbed_official 497:d54623194236 3120 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
mbed_official 497:d54623194236 3121
mbed_official 497:d54623194236 3122 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
mbed_official 497:d54623194236 3123
mbed_official 497:d54623194236 3124 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 497:d54623194236 3125 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
mbed_official 497:d54623194236 3126
mbed_official 497:d54623194236 3127
mbed_official 497:d54623194236 3128 /******************************************************************************/
mbed_official 497:d54623194236 3129 /* */
mbed_official 497:d54623194236 3130 /* SD host Interface */
mbed_official 497:d54623194236 3131 /* */
mbed_official 497:d54623194236 3132 /******************************************************************************/
mbed_official 497:d54623194236 3133
mbed_official 497:d54623194236 3134 /****************** Bit definition for SDIO_POWER register ******************/
mbed_official 497:d54623194236 3135 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
mbed_official 497:d54623194236 3136 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!< Bit 0 */
mbed_official 497:d54623194236 3137 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!< Bit 1 */
mbed_official 497:d54623194236 3138
mbed_official 497:d54623194236 3139 /****************** Bit definition for SDIO_CLKCR register ******************/
mbed_official 497:d54623194236 3140 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!< Clock divide factor */
mbed_official 497:d54623194236 3141 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!< Clock enable bit */
mbed_official 497:d54623194236 3142 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!< Power saving configuration bit */
mbed_official 497:d54623194236 3143 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!< Clock divider bypass enable bit */
mbed_official 497:d54623194236 3144
mbed_official 497:d54623194236 3145 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
mbed_official 497:d54623194236 3146 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!< Bit 0 */
mbed_official 497:d54623194236 3147 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!< Bit 1 */
mbed_official 497:d54623194236 3148
mbed_official 497:d54623194236 3149 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!< SDIO_CK dephasing selection bit */
mbed_official 497:d54623194236 3150 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!< HW Flow Control enable */
mbed_official 497:d54623194236 3151
mbed_official 497:d54623194236 3152 /******************* Bit definition for SDIO_ARG register *******************/
mbed_official 497:d54623194236 3153 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
mbed_official 497:d54623194236 3154
mbed_official 497:d54623194236 3155 /******************* Bit definition for SDIO_CMD register *******************/
mbed_official 497:d54623194236 3156 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!< Command Index */
mbed_official 497:d54623194236 3157
mbed_official 497:d54623194236 3158 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
mbed_official 497:d54623194236 3159 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
mbed_official 497:d54623194236 3160 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
mbed_official 497:d54623194236 3161
mbed_official 497:d54623194236 3162 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!< CPSM Waits for Interrupt Request */
mbed_official 497:d54623194236 3163 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
mbed_official 497:d54623194236 3164 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
mbed_official 497:d54623194236 3165 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!< SD I/O suspend command */
mbed_official 497:d54623194236 3166 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!< Enable CMD completion */
mbed_official 497:d54623194236 3167 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!< Not Interrupt Enable */
mbed_official 497:d54623194236 3168 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!< CE-ATA command */
mbed_official 497:d54623194236 3169
mbed_official 497:d54623194236 3170 /***************** Bit definition for SDIO_RESPCMD register *****************/
mbed_official 497:d54623194236 3171 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!< Response command index */
mbed_official 497:d54623194236 3172
mbed_official 497:d54623194236 3173 /****************** Bit definition for SDIO_RESP0 register ******************/
mbed_official 497:d54623194236 3174 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
mbed_official 497:d54623194236 3175
mbed_official 497:d54623194236 3176 /****************** Bit definition for SDIO_RESP1 register ******************/
mbed_official 497:d54623194236 3177 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
mbed_official 497:d54623194236 3178
mbed_official 497:d54623194236 3179 /****************** Bit definition for SDIO_RESP2 register ******************/
mbed_official 497:d54623194236 3180 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
mbed_official 497:d54623194236 3181
mbed_official 497:d54623194236 3182 /****************** Bit definition for SDIO_RESP3 register ******************/
mbed_official 497:d54623194236 3183 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
mbed_official 497:d54623194236 3184
mbed_official 497:d54623194236 3185 /****************** Bit definition for SDIO_RESP4 register ******************/
mbed_official 497:d54623194236 3186 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
mbed_official 497:d54623194236 3187
mbed_official 497:d54623194236 3188 /****************** Bit definition for SDIO_DTIMER register *****************/
mbed_official 497:d54623194236 3189 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
mbed_official 497:d54623194236 3190
mbed_official 497:d54623194236 3191 /****************** Bit definition for SDIO_DLEN register *******************/
mbed_official 497:d54623194236 3192 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
mbed_official 497:d54623194236 3193
mbed_official 497:d54623194236 3194 /****************** Bit definition for SDIO_DCTRL register ******************/
mbed_official 497:d54623194236 3195 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!< Data transfer enabled bit */
mbed_official 497:d54623194236 3196 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!< Data transfer direction selection */
mbed_official 497:d54623194236 3197 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!< Data transfer mode selection */
mbed_official 497:d54623194236 3198 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!< DMA enabled bit */
mbed_official 497:d54623194236 3199
mbed_official 497:d54623194236 3200 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
mbed_official 497:d54623194236 3201 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!< Bit 0 */
mbed_official 497:d54623194236 3202 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!< Bit 1 */
mbed_official 497:d54623194236 3203 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!< Bit 2 */
mbed_official 497:d54623194236 3204 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!< Bit 3 */
mbed_official 497:d54623194236 3205
mbed_official 497:d54623194236 3206 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!< Read wait start */
mbed_official 497:d54623194236 3207 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!< Read wait stop */
mbed_official 497:d54623194236 3208 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!< Read wait mode */
mbed_official 497:d54623194236 3209 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!< SD I/O enable functions */
mbed_official 497:d54623194236 3210
mbed_official 497:d54623194236 3211 /****************** Bit definition for SDIO_DCOUNT register *****************/
mbed_official 497:d54623194236 3212 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
mbed_official 497:d54623194236 3213
mbed_official 497:d54623194236 3214 /****************** Bit definition for SDIO_STA register ********************/
mbed_official 497:d54623194236 3215 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
mbed_official 497:d54623194236 3216 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
mbed_official 497:d54623194236 3217 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
mbed_official 497:d54623194236 3218 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
mbed_official 497:d54623194236 3219 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
mbed_official 497:d54623194236 3220 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
mbed_official 497:d54623194236 3221 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
mbed_official 497:d54623194236 3222 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
mbed_official 497:d54623194236 3223 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
mbed_official 497:d54623194236 3224 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
mbed_official 497:d54623194236 3225 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
mbed_official 497:d54623194236 3226 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
mbed_official 497:d54623194236 3227 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
mbed_official 497:d54623194236 3228 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
mbed_official 497:d54623194236 3229 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
mbed_official 497:d54623194236 3230 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
mbed_official 497:d54623194236 3231 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
mbed_official 497:d54623194236 3232 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
mbed_official 497:d54623194236 3233 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
mbed_official 497:d54623194236 3234 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
mbed_official 497:d54623194236 3235 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
mbed_official 497:d54623194236 3236 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
mbed_official 497:d54623194236 3237 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
mbed_official 497:d54623194236 3238 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
mbed_official 497:d54623194236 3239
mbed_official 497:d54623194236 3240 /******************* Bit definition for SDIO_ICR register *******************/
mbed_official 497:d54623194236 3241 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
mbed_official 497:d54623194236 3242 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
mbed_official 497:d54623194236 3243 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
mbed_official 497:d54623194236 3244 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
mbed_official 497:d54623194236 3245 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
mbed_official 497:d54623194236 3246 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
mbed_official 497:d54623194236 3247 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
mbed_official 497:d54623194236 3248 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
mbed_official 497:d54623194236 3249 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
mbed_official 497:d54623194236 3250 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
mbed_official 497:d54623194236 3251 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
mbed_official 497:d54623194236 3252 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
mbed_official 497:d54623194236 3253 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
mbed_official 497:d54623194236 3254
mbed_official 497:d54623194236 3255 /****************** Bit definition for SDIO_MASK register *******************/
mbed_official 497:d54623194236 3256 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
mbed_official 497:d54623194236 3257 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
mbed_official 497:d54623194236 3258 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
mbed_official 497:d54623194236 3259 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
mbed_official 497:d54623194236 3260 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
mbed_official 497:d54623194236 3261 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
mbed_official 497:d54623194236 3262 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
mbed_official 497:d54623194236 3263 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
mbed_official 497:d54623194236 3264 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
mbed_official 497:d54623194236 3265 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
mbed_official 497:d54623194236 3266 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
mbed_official 497:d54623194236 3267 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
mbed_official 497:d54623194236 3268 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
mbed_official 497:d54623194236 3269 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
mbed_official 497:d54623194236 3270 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
mbed_official 497:d54623194236 3271 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
mbed_official 497:d54623194236 3272 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
mbed_official 497:d54623194236 3273 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
mbed_official 497:d54623194236 3274 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
mbed_official 497:d54623194236 3275 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
mbed_official 497:d54623194236 3276 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
mbed_official 497:d54623194236 3277 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
mbed_official 497:d54623194236 3278 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
mbed_official 497:d54623194236 3279 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
mbed_official 497:d54623194236 3280
mbed_official 497:d54623194236 3281 /***************** Bit definition for SDIO_FIFOCNT register *****************/
mbed_official 497:d54623194236 3282 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
mbed_official 497:d54623194236 3283
mbed_official 497:d54623194236 3284 /****************** Bit definition for SDIO_FIFO register *******************/
mbed_official 497:d54623194236 3285 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
mbed_official 497:d54623194236 3286
mbed_official 497:d54623194236 3287
mbed_official 497:d54623194236 3288
mbed_official 497:d54623194236 3289 /******************************************************************************/
mbed_official 497:d54623194236 3290 /* */
mbed_official 497:d54623194236 3291 /* Serial Peripheral Interface */
mbed_official 497:d54623194236 3292 /* */
mbed_official 497:d54623194236 3293 /******************************************************************************/
mbed_official 497:d54623194236 3294
mbed_official 497:d54623194236 3295 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 497:d54623194236 3296 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 497:d54623194236 3297 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 497:d54623194236 3298 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 497:d54623194236 3299
mbed_official 497:d54623194236 3300 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 497:d54623194236 3301 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 497:d54623194236 3302 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 497:d54623194236 3303 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 497:d54623194236 3304
mbed_official 497:d54623194236 3305 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 497:d54623194236 3306 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 497:d54623194236 3307 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 497:d54623194236 3308 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 497:d54623194236 3309 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 497:d54623194236 3310 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
mbed_official 497:d54623194236 3311 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 497:d54623194236 3312 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 497:d54623194236 3313 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 497:d54623194236 3314 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 497:d54623194236 3315
mbed_official 497:d54623194236 3316 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 497:d54623194236 3317 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 497:d54623194236 3318 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 497:d54623194236 3319 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 497:d54623194236 3320 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 497:d54623194236 3321 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 497:d54623194236 3322 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 497:d54623194236 3323
mbed_official 497:d54623194236 3324 /******************** Bit definition for SPI_SR register ********************/
mbed_official 497:d54623194236 3325 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 497:d54623194236 3326 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 497:d54623194236 3327 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 497:d54623194236 3328 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 497:d54623194236 3329 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 497:d54623194236 3330 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 497:d54623194236 3331 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 497:d54623194236 3332 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 497:d54623194236 3333
mbed_official 497:d54623194236 3334 /******************** Bit definition for SPI_DR register ********************/
mbed_official 497:d54623194236 3335 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
mbed_official 497:d54623194236 3336
mbed_official 497:d54623194236 3337 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 497:d54623194236 3338 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
mbed_official 497:d54623194236 3339
mbed_official 497:d54623194236 3340 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 497:d54623194236 3341 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
mbed_official 497:d54623194236 3342
mbed_official 497:d54623194236 3343 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 497:d54623194236 3344 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
mbed_official 497:d54623194236 3345
mbed_official 497:d54623194236 3346
mbed_official 497:d54623194236 3347
mbed_official 497:d54623194236 3348 /******************************************************************************/
mbed_official 497:d54623194236 3349 /* */
mbed_official 497:d54623194236 3350 /* Inter-integrated Circuit Interface */
mbed_official 497:d54623194236 3351 /* */
mbed_official 497:d54623194236 3352 /******************************************************************************/
mbed_official 497:d54623194236 3353
mbed_official 497:d54623194236 3354 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 497:d54623194236 3355 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
mbed_official 497:d54623194236 3356 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
mbed_official 497:d54623194236 3357 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
mbed_official 497:d54623194236 3358 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
mbed_official 497:d54623194236 3359 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
mbed_official 497:d54623194236 3360 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
mbed_official 497:d54623194236 3361 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
mbed_official 497:d54623194236 3362 #define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
mbed_official 497:d54623194236 3363 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
mbed_official 497:d54623194236 3364 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
mbed_official 497:d54623194236 3365 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
mbed_official 497:d54623194236 3366 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
mbed_official 497:d54623194236 3367 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
mbed_official 497:d54623194236 3368 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
mbed_official 497:d54623194236 3369
mbed_official 497:d54623194236 3370 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 497:d54623194236 3371 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 497:d54623194236 3372 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 3373 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 3374 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 3375 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 3376 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 3377 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 497:d54623194236 3378
mbed_official 497:d54623194236 3379 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
mbed_official 497:d54623194236 3380 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
mbed_official 497:d54623194236 3381 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
mbed_official 497:d54623194236 3382 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
mbed_official 497:d54623194236 3383 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
mbed_official 497:d54623194236 3384
mbed_official 497:d54623194236 3385 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 497:d54623194236 3386 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
mbed_official 497:d54623194236 3387 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
mbed_official 497:d54623194236 3388
mbed_official 497:d54623194236 3389 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 3390 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 3391 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 3392 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 3393 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 3394 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 497:d54623194236 3395 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 497:d54623194236 3396 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 497:d54623194236 3397 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 497:d54623194236 3398 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 497:d54623194236 3399
mbed_official 497:d54623194236 3400 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
mbed_official 497:d54623194236 3401
mbed_official 497:d54623194236 3402 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 497:d54623194236 3403 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
mbed_official 497:d54623194236 3404 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
mbed_official 497:d54623194236 3405
mbed_official 497:d54623194236 3406 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 497:d54623194236 3407 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
mbed_official 497:d54623194236 3408 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
mbed_official 497:d54623194236 3409 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
mbed_official 497:d54623194236 3410 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
mbed_official 497:d54623194236 3411 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
mbed_official 497:d54623194236 3412 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
mbed_official 497:d54623194236 3413 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
mbed_official 497:d54623194236 3414 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
mbed_official 497:d54623194236 3415 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
mbed_official 497:d54623194236 3416 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
mbed_official 497:d54623194236 3417 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
mbed_official 497:d54623194236 3418 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
mbed_official 497:d54623194236 3419 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
mbed_official 497:d54623194236 3420 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
mbed_official 497:d54623194236 3421
mbed_official 497:d54623194236 3422 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 497:d54623194236 3423 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
mbed_official 497:d54623194236 3424 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
mbed_official 497:d54623194236 3425 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
mbed_official 497:d54623194236 3426 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
mbed_official 497:d54623194236 3427 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
mbed_official 497:d54623194236 3428 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
mbed_official 497:d54623194236 3429 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
mbed_official 497:d54623194236 3430 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
mbed_official 497:d54623194236 3431
mbed_official 497:d54623194236 3432 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 497:d54623194236 3433 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 497:d54623194236 3434 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
mbed_official 497:d54623194236 3435 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
mbed_official 497:d54623194236 3436
mbed_official 497:d54623194236 3437 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 497:d54623194236 3438 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 497:d54623194236 3439
mbed_official 497:d54623194236 3440 /******************************************************************************/
mbed_official 497:d54623194236 3441 /* */
mbed_official 497:d54623194236 3442 /* Universal Synchronous Asynchronous Receiver Transmitter */
mbed_official 497:d54623194236 3443 /* */
mbed_official 497:d54623194236 3444 /******************************************************************************/
mbed_official 497:d54623194236 3445
mbed_official 497:d54623194236 3446 /******************* Bit definition for USART_SR register *******************/
mbed_official 497:d54623194236 3447 #define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 497:d54623194236 3448 #define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 497:d54623194236 3449 #define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
mbed_official 497:d54623194236 3450 #define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 497:d54623194236 3451 #define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 497:d54623194236 3452 #define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 497:d54623194236 3453 #define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 497:d54623194236 3454 #define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 497:d54623194236 3455 #define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 497:d54623194236 3456 #define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
mbed_official 497:d54623194236 3457
mbed_official 497:d54623194236 3458 /******************* Bit definition for USART_DR register *******************/
mbed_official 497:d54623194236 3459 #define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
mbed_official 497:d54623194236 3460
mbed_official 497:d54623194236 3461 /****************** Bit definition for USART_BRR register *******************/
mbed_official 497:d54623194236 3462 #define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 497:d54623194236 3463 #define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 497:d54623194236 3464
mbed_official 497:d54623194236 3465 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 497:d54623194236 3466 #define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
mbed_official 497:d54623194236 3467 #define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
mbed_official 497:d54623194236 3468 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 497:d54623194236 3469 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 497:d54623194236 3470 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 497:d54623194236 3471 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 497:d54623194236 3472 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 497:d54623194236 3473 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
mbed_official 497:d54623194236 3474 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 497:d54623194236 3475 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 497:d54623194236 3476 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 497:d54623194236 3477 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
mbed_official 497:d54623194236 3478 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
mbed_official 497:d54623194236 3479 #define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
mbed_official 497:d54623194236 3480
mbed_official 497:d54623194236 3481 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 497:d54623194236 3482 #define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
mbed_official 497:d54623194236 3483 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 497:d54623194236 3484 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 497:d54623194236 3485 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 497:d54623194236 3486 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 497:d54623194236 3487 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 497:d54623194236 3488 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 497:d54623194236 3489
mbed_official 497:d54623194236 3490 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 497:d54623194236 3491 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 497:d54623194236 3492 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 497:d54623194236 3493
mbed_official 497:d54623194236 3494 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 497:d54623194236 3495
mbed_official 497:d54623194236 3496 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 497:d54623194236 3497 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 497:d54623194236 3498 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 497:d54623194236 3499 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 497:d54623194236 3500 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 497:d54623194236 3501 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
mbed_official 497:d54623194236 3502 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
mbed_official 497:d54623194236 3503 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 497:d54623194236 3504 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 497:d54623194236 3505 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 497:d54623194236 3506 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 497:d54623194236 3507 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 497:d54623194236 3508
mbed_official 497:d54623194236 3509 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 497:d54623194236 3510 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 497:d54623194236 3511 #define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 497:d54623194236 3512 #define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 497:d54623194236 3513 #define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 497:d54623194236 3514 #define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 497:d54623194236 3515 #define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 497:d54623194236 3516 #define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 497:d54623194236 3517 #define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 497:d54623194236 3518 #define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 497:d54623194236 3519
mbed_official 497:d54623194236 3520 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
mbed_official 497:d54623194236 3521
mbed_official 497:d54623194236 3522 /******************************************************************************/
mbed_official 497:d54623194236 3523 /* */
mbed_official 497:d54623194236 3524 /* Debug MCU */
mbed_official 497:d54623194236 3525 /* */
mbed_official 497:d54623194236 3526 /******************************************************************************/
mbed_official 497:d54623194236 3527
mbed_official 497:d54623194236 3528 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 497:d54623194236 3529 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
mbed_official 497:d54623194236 3530
mbed_official 497:d54623194236 3531 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 497:d54623194236 3532 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 497:d54623194236 3533 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 497:d54623194236 3534 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 497:d54623194236 3535 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 497:d54623194236 3536 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 497:d54623194236 3537 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 497:d54623194236 3538 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 497:d54623194236 3539 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 497:d54623194236 3540 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 497:d54623194236 3541 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 497:d54623194236 3542 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 497:d54623194236 3543 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 497:d54623194236 3544 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 497:d54623194236 3545 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 497:d54623194236 3546 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 497:d54623194236 3547 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 497:d54623194236 3548
mbed_official 497:d54623194236 3549 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 497:d54623194236 3550 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
mbed_official 497:d54623194236 3551 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
mbed_official 497:d54623194236 3552 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
mbed_official 497:d54623194236 3553 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
mbed_official 497:d54623194236 3554
mbed_official 497:d54623194236 3555 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
mbed_official 497:d54623194236 3556 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 497:d54623194236 3557 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 497:d54623194236 3558
mbed_official 497:d54623194236 3559 #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 497:d54623194236 3560 #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 497:d54623194236 3561 #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
mbed_official 497:d54623194236 3562 #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
mbed_official 497:d54623194236 3563 #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
mbed_official 497:d54623194236 3564 #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
mbed_official 497:d54623194236 3565 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
mbed_official 497:d54623194236 3566 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
mbed_official 497:d54623194236 3567 #define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */
mbed_official 497:d54623194236 3568 #define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */
mbed_official 497:d54623194236 3569 #define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */
mbed_official 497:d54623194236 3570
mbed_official 497:d54623194236 3571 /******************************************************************************/
mbed_official 497:d54623194236 3572 /* */
mbed_official 497:d54623194236 3573 /* FLASH and Option Bytes Registers */
mbed_official 497:d54623194236 3574 /* */
mbed_official 497:d54623194236 3575 /******************************************************************************/
mbed_official 497:d54623194236 3576 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 497:d54623194236 3577 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
mbed_official 497:d54623194236 3578
mbed_official 497:d54623194236 3579 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 497:d54623194236 3580 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 497:d54623194236 3581
mbed_official 497:d54623194236 3582 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
mbed_official 497:d54623194236 3583 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
mbed_official 497:d54623194236 3584 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
mbed_official 497:d54623194236 3585
mbed_official 497:d54623194236 3586 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 497:d54623194236 3587 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 497:d54623194236 3588
mbed_official 497:d54623194236 3589 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
mbed_official 497:d54623194236 3590 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
mbed_official 497:d54623194236 3591
mbed_official 497:d54623194236 3592 /****************** Bit definition for FLASH_SR register ********************/
mbed_official 497:d54623194236 3593 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 497:d54623194236 3594 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 497:d54623194236 3595 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 497:d54623194236 3596 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 497:d54623194236 3597
mbed_official 497:d54623194236 3598 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 497:d54623194236 3599 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 497:d54623194236 3600 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 497:d54623194236 3601 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 497:d54623194236 3602 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 497:d54623194236 3603 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 497:d54623194236 3604 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 497:d54623194236 3605 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 497:d54623194236 3606 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 497:d54623194236 3607 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 497:d54623194236 3608 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 497:d54623194236 3609
mbed_official 497:d54623194236 3610 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 497:d54623194236 3611 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 497:d54623194236 3612
mbed_official 497:d54623194236 3613 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 497:d54623194236 3614 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 497:d54623194236 3615 #define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /*!< Read protection */
mbed_official 497:d54623194236 3616
mbed_official 497:d54623194236 3617 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /*!< IWDG SW */
mbed_official 497:d54623194236 3618 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /*!< nRST_STOP */
mbed_official 497:d54623194236 3619 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /*!< nRST_STDBY */
mbed_official 497:d54623194236 3620 #define FLASH_OBR_USER ((uint32_t)0x0000001C) /*!< User Option Bytes */
mbed_official 497:d54623194236 3621
mbed_official 497:d54623194236 3622 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 497:d54623194236 3623 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 497:d54623194236 3624
mbed_official 497:d54623194236 3625 /*----------------------------------------------------------------------------*/
mbed_official 497:d54623194236 3626
mbed_official 497:d54623194236 3627 /****************** Bit definition for FLASH_RDP register *******************/
mbed_official 497:d54623194236 3628 #define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 497:d54623194236 3629 #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 497:d54623194236 3630
mbed_official 497:d54623194236 3631 /****************** Bit definition for FLASH_USER register ******************/
mbed_official 497:d54623194236 3632 #define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 497:d54623194236 3633 #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 497:d54623194236 3634
mbed_official 497:d54623194236 3635 /****************** Bit definition for FLASH_Data0 register *****************/
mbed_official 497:d54623194236 3636 #define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
mbed_official 497:d54623194236 3637 #define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
mbed_official 497:d54623194236 3638
mbed_official 497:d54623194236 3639 /****************** Bit definition for FLASH_Data1 register *****************/
mbed_official 497:d54623194236 3640 #define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
mbed_official 497:d54623194236 3641 #define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
mbed_official 497:d54623194236 3642
mbed_official 497:d54623194236 3643 /****************** Bit definition for FLASH_WRP0 register ******************/
mbed_official 497:d54623194236 3644 #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 497:d54623194236 3645 #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 497:d54623194236 3646
mbed_official 497:d54623194236 3647 /****************** Bit definition for FLASH_WRP1 register ******************/
mbed_official 497:d54623194236 3648 #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 497:d54623194236 3649 #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 497:d54623194236 3650
mbed_official 497:d54623194236 3651 /****************** Bit definition for FLASH_WRP2 register ******************/
mbed_official 497:d54623194236 3652 #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 497:d54623194236 3653 #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 497:d54623194236 3654
mbed_official 497:d54623194236 3655 /****************** Bit definition for FLASH_WRP3 register ******************/
mbed_official 497:d54623194236 3656 #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 497:d54623194236 3657 #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 497:d54623194236 3658
mbed_official 497:d54623194236 3659
mbed_official 497:d54623194236 3660
mbed_official 497:d54623194236 3661 /**
mbed_official 497:d54623194236 3662 * @}
mbed_official 497:d54623194236 3663 */
mbed_official 497:d54623194236 3664
mbed_official 497:d54623194236 3665 /**
mbed_official 497:d54623194236 3666 * @}
mbed_official 497:d54623194236 3667 */
mbed_official 497:d54623194236 3668
mbed_official 497:d54623194236 3669 /** @addtogroup Exported_macro
mbed_official 497:d54623194236 3670 * @{
mbed_official 497:d54623194236 3671 */
mbed_official 497:d54623194236 3672
mbed_official 497:d54623194236 3673 /****************************** ADC Instances *********************************/
mbed_official 497:d54623194236 3674 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
mbed_official 497:d54623194236 3675
mbed_official 497:d54623194236 3676 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 497:d54623194236 3677
mbed_official 497:d54623194236 3678 /****************************** CEC Instances *********************************/
mbed_official 497:d54623194236 3679 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
mbed_official 497:d54623194236 3680
mbed_official 497:d54623194236 3681 /****************************** CRC Instances *********************************/
mbed_official 497:d54623194236 3682 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 497:d54623194236 3683
mbed_official 497:d54623194236 3684 /****************************** DAC Instances *********************************/
mbed_official 497:d54623194236 3685 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 497:d54623194236 3686
mbed_official 497:d54623194236 3687 /****************************** DMA Instances *********************************/
mbed_official 497:d54623194236 3688 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 497:d54623194236 3689 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 497:d54623194236 3690 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 497:d54623194236 3691 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 497:d54623194236 3692 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 497:d54623194236 3693 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 497:d54623194236 3694 ((INSTANCE) == DMA1_Channel7))
mbed_official 497:d54623194236 3695
mbed_official 497:d54623194236 3696 /******************************* GPIO Instances *******************************/
mbed_official 497:d54623194236 3697 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 497:d54623194236 3698 ((INSTANCE) == GPIOB) || \
mbed_official 497:d54623194236 3699 ((INSTANCE) == GPIOC) || \
mbed_official 497:d54623194236 3700 ((INSTANCE) == GPIOD) || \
mbed_official 497:d54623194236 3701 ((INSTANCE) == GPIOE))
mbed_official 497:d54623194236 3702
mbed_official 497:d54623194236 3703 /**************************** GPIO Alternate Function Instances ***************/
mbed_official 497:d54623194236 3704 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
mbed_official 497:d54623194236 3705
mbed_official 497:d54623194236 3706 /**************************** GPIO Lock Instances *****************************/
mbed_official 497:d54623194236 3707 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
mbed_official 497:d54623194236 3708
mbed_official 497:d54623194236 3709 /******************************** I2C Instances *******************************/
mbed_official 497:d54623194236 3710 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 497:d54623194236 3711 ((INSTANCE) == I2C2))
mbed_official 497:d54623194236 3712
mbed_official 497:d54623194236 3713 /****************************** IWDG Instances ********************************/
mbed_official 497:d54623194236 3714 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 497:d54623194236 3715
mbed_official 497:d54623194236 3716 /******************************** SPI Instances *******************************/
mbed_official 497:d54623194236 3717 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 497:d54623194236 3718 ((INSTANCE) == SPI2))
mbed_official 497:d54623194236 3719
mbed_official 497:d54623194236 3720 /****************************** START TIM Instances ***************************/
mbed_official 497:d54623194236 3721 /****************************** TIM Instances *********************************/
mbed_official 497:d54623194236 3722 #define IS_TIM_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3723 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3724 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3725 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3726 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3727 ((INSTANCE) == TIM6) || \
mbed_official 497:d54623194236 3728 ((INSTANCE) == TIM7) || \
mbed_official 497:d54623194236 3729 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3730 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3731 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3732
mbed_official 497:d54623194236 3733 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3734 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3735 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3736 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3737 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3738 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3739 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3740 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3741
mbed_official 497:d54623194236 3742 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3743 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3744 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3745 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3746 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3747 ((INSTANCE) == TIM15))
mbed_official 497:d54623194236 3748
mbed_official 497:d54623194236 3749 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3750 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3751 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3752 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3753 ((INSTANCE) == TIM4))
mbed_official 497:d54623194236 3754
mbed_official 497:d54623194236 3755 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3756 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3757 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3758 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3759 ((INSTANCE) == TIM4))
mbed_official 497:d54623194236 3760
mbed_official 497:d54623194236 3761 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3762 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3763 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3764 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3765 ((INSTANCE) == TIM4))
mbed_official 497:d54623194236 3766
mbed_official 497:d54623194236 3767 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3768 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3769 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3770 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3771 ((INSTANCE) == TIM4))
mbed_official 497:d54623194236 3772
mbed_official 497:d54623194236 3773 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3774 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3775 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3776 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3777 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3778 ((INSTANCE) == TIM15))
mbed_official 497:d54623194236 3779
mbed_official 497:d54623194236 3780 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3781 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3782 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3783 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3784 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3785 ((INSTANCE) == TIM15))
mbed_official 497:d54623194236 3786
mbed_official 497:d54623194236 3787 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3788 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3789 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3790 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3791 ((INSTANCE) == TIM4))
mbed_official 497:d54623194236 3792
mbed_official 497:d54623194236 3793 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3794 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3795 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3796 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3797 ((INSTANCE) == TIM4))
mbed_official 497:d54623194236 3798
mbed_official 497:d54623194236 3799 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3800 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3801 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3802 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3803 ((INSTANCE) == TIM4))
mbed_official 497:d54623194236 3804
mbed_official 497:d54623194236 3805 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3806 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3807 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3808 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3809 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3810 ((INSTANCE) == TIM6) || \
mbed_official 497:d54623194236 3811 ((INSTANCE) == TIM7) || \
mbed_official 497:d54623194236 3812 ((INSTANCE) == TIM15))
mbed_official 497:d54623194236 3813
mbed_official 497:d54623194236 3814 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3815 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3816 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3817 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3818 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3819 ((INSTANCE) == TIM15))
mbed_official 497:d54623194236 3820
mbed_official 497:d54623194236 3821 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3822 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3823 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3824 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3825 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3826 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3827 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3828 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3829
mbed_official 497:d54623194236 3830 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3831 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3832 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3833 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3834 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3835
mbed_official 497:d54623194236 3836 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 497:d54623194236 3837 ((((INSTANCE) == TIM1) && \
mbed_official 497:d54623194236 3838 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 497:d54623194236 3839 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 497:d54623194236 3840 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 497:d54623194236 3841 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 497:d54623194236 3842 || \
mbed_official 497:d54623194236 3843 (((INSTANCE) == TIM2) && \
mbed_official 497:d54623194236 3844 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 497:d54623194236 3845 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 497:d54623194236 3846 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 497:d54623194236 3847 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 497:d54623194236 3848 || \
mbed_official 497:d54623194236 3849 (((INSTANCE) == TIM3) && \
mbed_official 497:d54623194236 3850 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 497:d54623194236 3851 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 497:d54623194236 3852 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 497:d54623194236 3853 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 497:d54623194236 3854 || \
mbed_official 497:d54623194236 3855 (((INSTANCE) == TIM4) && \
mbed_official 497:d54623194236 3856 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 497:d54623194236 3857 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 497:d54623194236 3858 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 497:d54623194236 3859 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 497:d54623194236 3860 || \
mbed_official 497:d54623194236 3861 (((INSTANCE) == TIM15) && \
mbed_official 497:d54623194236 3862 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 497:d54623194236 3863 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 497:d54623194236 3864 || \
mbed_official 497:d54623194236 3865 (((INSTANCE) == TIM16) && \
mbed_official 497:d54623194236 3866 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 497:d54623194236 3867 || \
mbed_official 497:d54623194236 3868 (((INSTANCE) == TIM17) && \
mbed_official 497:d54623194236 3869 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 497:d54623194236 3870
mbed_official 497:d54623194236 3871 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 497:d54623194236 3872 ((((INSTANCE) == TIM1) && \
mbed_official 497:d54623194236 3873 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 497:d54623194236 3874 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 497:d54623194236 3875 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 497:d54623194236 3876 || \
mbed_official 497:d54623194236 3877 (((INSTANCE) == TIM15) && \
mbed_official 497:d54623194236 3878 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 497:d54623194236 3879 || \
mbed_official 497:d54623194236 3880 (((INSTANCE) == TIM16) && \
mbed_official 497:d54623194236 3881 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 497:d54623194236 3882 || \
mbed_official 497:d54623194236 3883 (((INSTANCE) == TIM17) && \
mbed_official 497:d54623194236 3884 ((CHANNEL) == TIM_CHANNEL_1)))
mbed_official 497:d54623194236 3885
mbed_official 497:d54623194236 3886 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3887 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3888 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3889 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3890 ((INSTANCE) == TIM4))
mbed_official 497:d54623194236 3891
mbed_official 497:d54623194236 3892 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3893 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3894 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3895 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3896 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3897
mbed_official 497:d54623194236 3898 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3899 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3900 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3901 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3902 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3903 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3904 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3905 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3906
mbed_official 497:d54623194236 3907 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3908 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3909 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3910 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3911 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3912 ((INSTANCE) == TIM6) || \
mbed_official 497:d54623194236 3913 ((INSTANCE) == TIM7) || \
mbed_official 497:d54623194236 3914 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3915 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3916 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3917
mbed_official 497:d54623194236 3918 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3919 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3920 ((INSTANCE) == TIM2) || \
mbed_official 497:d54623194236 3921 ((INSTANCE) == TIM3) || \
mbed_official 497:d54623194236 3922 ((INSTANCE) == TIM4) || \
mbed_official 497:d54623194236 3923 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3924 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3925 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3926
mbed_official 497:d54623194236 3927 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official 497:d54623194236 3928 (((INSTANCE) == TIM1) || \
mbed_official 497:d54623194236 3929 ((INSTANCE) == TIM15) || \
mbed_official 497:d54623194236 3930 ((INSTANCE) == TIM16) || \
mbed_official 497:d54623194236 3931 ((INSTANCE) == TIM17))
mbed_official 497:d54623194236 3932
mbed_official 497:d54623194236 3933 /****************************** END TIM Instances *****************************/
mbed_official 497:d54623194236 3934
mbed_official 497:d54623194236 3935
mbed_official 497:d54623194236 3936 /******************** USART Instances : Synchronous mode **********************/
mbed_official 497:d54623194236 3937 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3938 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3939 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3940
mbed_official 497:d54623194236 3941 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 497:d54623194236 3942 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3943 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3944 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3945
mbed_official 497:d54623194236 3946 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 497:d54623194236 3947 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3948 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3949 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3950
mbed_official 497:d54623194236 3951 /******************** UART Instances : LIN mode **********************/
mbed_official 497:d54623194236 3952 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3953 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3954 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3955
mbed_official 497:d54623194236 3956 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 497:d54623194236 3957 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3958 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3959 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3960
mbed_official 497:d54623194236 3961 /********************* UART Instances : Smard card mode ***********************/
mbed_official 497:d54623194236 3962 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3963 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3964 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3965
mbed_official 497:d54623194236 3966 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 497:d54623194236 3967 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3968 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3969 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3970
mbed_official 497:d54623194236 3971 /***************** UART Instances : Multi-Processor mode **********************/
mbed_official 497:d54623194236 3972 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3973 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3974 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3975
mbed_official 497:d54623194236 3976 /***************** UART Instances : DMA mode available **********************/
mbed_official 497:d54623194236 3977 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 497:d54623194236 3978 ((INSTANCE) == USART2) || \
mbed_official 497:d54623194236 3979 ((INSTANCE) == USART3))
mbed_official 497:d54623194236 3980
mbed_official 497:d54623194236 3981 /****************************** RTC Instances *********************************/
mbed_official 497:d54623194236 3982 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 497:d54623194236 3983
mbed_official 497:d54623194236 3984 /**************************** WWDG Instances *****************************/
mbed_official 497:d54623194236 3985 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 497:d54623194236 3986
mbed_official 497:d54623194236 3987
mbed_official 497:d54623194236 3988
mbed_official 497:d54623194236 3989
mbed_official 497:d54623194236 3990
mbed_official 497:d54623194236 3991 /**
mbed_official 497:d54623194236 3992 * @}
mbed_official 497:d54623194236 3993 */
mbed_official 497:d54623194236 3994 /******************************************************************************/
mbed_official 497:d54623194236 3995 /* For a painless codes migration between the STM32F1xx device product */
mbed_official 497:d54623194236 3996 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 497:d54623194236 3997 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 497:d54623194236 3998 /* No need to update developed interrupt code when moving across */
mbed_official 497:d54623194236 3999 /* product lines within the same STM32F1 Family */
mbed_official 497:d54623194236 4000 /******************************************************************************/
mbed_official 497:d54623194236 4001
mbed_official 497:d54623194236 4002 /* Aliases for __IRQn */
mbed_official 497:d54623194236 4003 #define ADC1_2_IRQn ADC1_IRQn
mbed_official 497:d54623194236 4004
mbed_official 497:d54623194236 4005
mbed_official 497:d54623194236 4006
mbed_official 497:d54623194236 4007 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
mbed_official 497:d54623194236 4008 #define TIM9_IRQn TIM1_BRK_TIM15_IRQn
mbed_official 497:d54623194236 4009 #define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
mbed_official 497:d54623194236 4010
mbed_official 497:d54623194236 4011 #define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
mbed_official 497:d54623194236 4012 #define TIM10_IRQn TIM1_UP_TIM16_IRQn
mbed_official 497:d54623194236 4013 #define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
mbed_official 497:d54623194236 4014
mbed_official 497:d54623194236 4015 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
mbed_official 497:d54623194236 4016 #define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
mbed_official 497:d54623194236 4017 #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
mbed_official 497:d54623194236 4018
mbed_official 497:d54623194236 4019
mbed_official 497:d54623194236 4020
mbed_official 497:d54623194236 4021 #define OTG_FS_WKUP_IRQn CEC_IRQn
mbed_official 497:d54623194236 4022 #define USBWakeUp_IRQn CEC_IRQn
mbed_official 497:d54623194236 4023
mbed_official 497:d54623194236 4024
mbed_official 497:d54623194236 4025
mbed_official 497:d54623194236 4026 #define TIM6_IRQn TIM6_DAC_IRQn
mbed_official 497:d54623194236 4027
mbed_official 497:d54623194236 4028
mbed_official 497:d54623194236 4029 /* Aliases for __IRQHandler */
mbed_official 497:d54623194236 4030 #define ADC1_2_IRQHandler ADC1_IRQHandler
mbed_official 497:d54623194236 4031
mbed_official 497:d54623194236 4032
mbed_official 497:d54623194236 4033
mbed_official 497:d54623194236 4034 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
mbed_official 497:d54623194236 4035 #define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
mbed_official 497:d54623194236 4036 #define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
mbed_official 497:d54623194236 4037
mbed_official 497:d54623194236 4038 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
mbed_official 497:d54623194236 4039 #define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
mbed_official 497:d54623194236 4040 #define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
mbed_official 497:d54623194236 4041
mbed_official 497:d54623194236 4042 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
mbed_official 497:d54623194236 4043 #define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
mbed_official 497:d54623194236 4044 #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
mbed_official 497:d54623194236 4045
mbed_official 497:d54623194236 4046
mbed_official 497:d54623194236 4047
mbed_official 497:d54623194236 4048 #define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
mbed_official 497:d54623194236 4049 #define USBWakeUp_IRQHandler CEC_IRQHandler
mbed_official 497:d54623194236 4050
mbed_official 497:d54623194236 4051
mbed_official 497:d54623194236 4052
mbed_official 497:d54623194236 4053 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
mbed_official 497:d54623194236 4054
mbed_official 497:d54623194236 4055
mbed_official 497:d54623194236 4056 /**
mbed_official 497:d54623194236 4057 * @}
mbed_official 497:d54623194236 4058 */
mbed_official 497:d54623194236 4059
mbed_official 497:d54623194236 4060 /**
mbed_official 497:d54623194236 4061 * @}
mbed_official 497:d54623194236 4062 */
mbed_official 497:d54623194236 4063
mbed_official 497:d54623194236 4064
mbed_official 497:d54623194236 4065 #ifdef __cplusplus
mbed_official 497:d54623194236 4066 }
mbed_official 497:d54623194236 4067 #endif /* __cplusplus */
mbed_official 497:d54623194236 4068
mbed_official 497:d54623194236 4069 #endif /* __STM32F100xB_H */
mbed_official 497:d54623194236 4070
mbed_official 497:d54623194236 4071
mbed_official 497:d54623194236 4072
mbed_official 497:d54623194236 4073 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/