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mbed library sources for GR-PEACH rev.B.
Fork of
mbed-src
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mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c@498:b3c41e21851c, 2015-03-27 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Mar 27 16:00:09 2015 +0000
- Revision:
- 498:b3c41e21851c
- Parent:
- 441:d2c15dda23c1
Synchronized with git revision cfb9dd117e202b83a2c72bad404184f9b6aa0a6a
Full URL: https://github.com/mbedmicro/mbed/commit/cfb9dd117e202b83a2c72bad404184f9b6aa0a6a/
Updated hal & cmsis support for MTS Dragonfly and MTS mDot
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 441:d2c15dda23c1 | 1 | /** |
| mbed_official | 441:d2c15dda23c1 | 2 | ****************************************************************************** |
| mbed_official | 441:d2c15dda23c1 | 3 | * @file system_stm32f4xx.c |
| mbed_official | 441:d2c15dda23c1 | 4 | * @author MCD Application Team |
| mbed_official | 441:d2c15dda23c1 | 5 | * @version V2.1.0 |
| mbed_official | 441:d2c15dda23c1 | 6 | * @date 19-June-2014 |
| mbed_official | 441:d2c15dda23c1 | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
| mbed_official | 441:d2c15dda23c1 | 8 | * |
| mbed_official | 441:d2c15dda23c1 | 9 | * This file provides two functions and one global variable to be called from |
| mbed_official | 441:d2c15dda23c1 | 10 | * user application: |
| mbed_official | 441:d2c15dda23c1 | 11 | * - SystemInit(): This function is called at startup just after reset and |
| mbed_official | 441:d2c15dda23c1 | 12 | * before branch to main program. This call is made inside |
| mbed_official | 441:d2c15dda23c1 | 13 | * the "startup_stm32f4xx.s" file. |
| mbed_official | 441:d2c15dda23c1 | 14 | * |
| mbed_official | 441:d2c15dda23c1 | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| mbed_official | 441:d2c15dda23c1 | 16 | * by the user application to setup the SysTick |
| mbed_official | 441:d2c15dda23c1 | 17 | * timer or configure other parameters. |
| mbed_official | 441:d2c15dda23c1 | 18 | * |
| mbed_official | 441:d2c15dda23c1 | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| mbed_official | 441:d2c15dda23c1 | 20 | * be called whenever the core clock is changed |
| mbed_official | 441:d2c15dda23c1 | 21 | * during program execution. |
| mbed_official | 441:d2c15dda23c1 | 22 | * |
| mbed_official | 441:d2c15dda23c1 | 23 | * This file configures the system clock as follows: |
| mbed_official | 441:d2c15dda23c1 | 24 | *----------------------------------------------------------------------------- |
| mbed_official | 441:d2c15dda23c1 | 25 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
| mbed_official | 441:d2c15dda23c1 | 26 | * | (external 8 MHz clock) | (internal 16 MHz) |
| mbed_official | 441:d2c15dda23c1 | 27 | * | 2- PLL_HSE_XTAL | |
| mbed_official | 441:d2c15dda23c1 | 28 | * | (external 8 MHz xtal) | |
| mbed_official | 441:d2c15dda23c1 | 29 | *----------------------------------------------------------------------------- |
| mbed_official | 441:d2c15dda23c1 | 30 | * SYSCLK(MHz) | 100 | 100 |
| mbed_official | 441:d2c15dda23c1 | 31 | *----------------------------------------------------------------------------- |
| mbed_official | 441:d2c15dda23c1 | 32 | * AHBCLK (MHz) | 100 | 100 |
| mbed_official | 441:d2c15dda23c1 | 33 | *----------------------------------------------------------------------------- |
| mbed_official | 441:d2c15dda23c1 | 34 | * APB1CLK (MHz) | 50 | 50 |
| mbed_official | 441:d2c15dda23c1 | 35 | *----------------------------------------------------------------------------- |
| mbed_official | 441:d2c15dda23c1 | 36 | * APB2CLK (MHz) | 100 | 100 |
| mbed_official | 441:d2c15dda23c1 | 37 | *----------------------------------------------------------------------------- |
| mbed_official | 441:d2c15dda23c1 | 38 | * USB capable (48 MHz precise clock) | NO | NO |
| mbed_official | 441:d2c15dda23c1 | 39 | *----------------------------------------------------------------------------- |
| mbed_official | 441:d2c15dda23c1 | 40 | ****************************************************************************** |
| mbed_official | 441:d2c15dda23c1 | 41 | * @attention |
| mbed_official | 441:d2c15dda23c1 | 42 | * |
| mbed_official | 441:d2c15dda23c1 | 43 | * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
| mbed_official | 441:d2c15dda23c1 | 44 | * |
| mbed_official | 441:d2c15dda23c1 | 45 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 441:d2c15dda23c1 | 46 | * are permitted provided that the following conditions are met: |
| mbed_official | 441:d2c15dda23c1 | 47 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 441:d2c15dda23c1 | 48 | * this list of conditions and the following disclaimer. |
| mbed_official | 441:d2c15dda23c1 | 49 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 441:d2c15dda23c1 | 50 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 441:d2c15dda23c1 | 51 | * and/or other materials provided with the distribution. |
| mbed_official | 441:d2c15dda23c1 | 52 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 441:d2c15dda23c1 | 53 | * may be used to endorse or promote products derived from this software |
| mbed_official | 441:d2c15dda23c1 | 54 | * without specific prior written permission. |
| mbed_official | 441:d2c15dda23c1 | 55 | * |
| mbed_official | 441:d2c15dda23c1 | 56 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 441:d2c15dda23c1 | 57 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 441:d2c15dda23c1 | 58 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 441:d2c15dda23c1 | 59 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 441:d2c15dda23c1 | 60 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 441:d2c15dda23c1 | 61 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 441:d2c15dda23c1 | 62 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 441:d2c15dda23c1 | 63 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 441:d2c15dda23c1 | 64 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 441:d2c15dda23c1 | 65 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 441:d2c15dda23c1 | 66 | * |
| mbed_official | 441:d2c15dda23c1 | 67 | ****************************************************************************** |
| mbed_official | 441:d2c15dda23c1 | 68 | */ |
| mbed_official | 441:d2c15dda23c1 | 69 | |
| mbed_official | 441:d2c15dda23c1 | 70 | /** @addtogroup CMSIS |
| mbed_official | 441:d2c15dda23c1 | 71 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 72 | */ |
| mbed_official | 441:d2c15dda23c1 | 73 | |
| mbed_official | 441:d2c15dda23c1 | 74 | /** @addtogroup stm32f4xx_system |
| mbed_official | 441:d2c15dda23c1 | 75 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 76 | */ |
| mbed_official | 441:d2c15dda23c1 | 77 | |
| mbed_official | 441:d2c15dda23c1 | 78 | /** @addtogroup STM32F4xx_System_Private_Includes |
| mbed_official | 441:d2c15dda23c1 | 79 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 80 | */ |
| mbed_official | 441:d2c15dda23c1 | 81 | |
| mbed_official | 441:d2c15dda23c1 | 82 | |
| mbed_official | 441:d2c15dda23c1 | 83 | #include "stm32f4xx.h" |
| mbed_official | 441:d2c15dda23c1 | 84 | #include "hal_tick.h" |
| mbed_official | 441:d2c15dda23c1 | 85 | #if !defined (HSE_VALUE) |
| mbed_official | 441:d2c15dda23c1 | 86 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ |
| mbed_official | 441:d2c15dda23c1 | 87 | #endif /* HSE_VALUE */ |
| mbed_official | 441:d2c15dda23c1 | 88 | |
| mbed_official | 441:d2c15dda23c1 | 89 | #if !defined (HSI_VALUE) |
| mbed_official | 441:d2c15dda23c1 | 90 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| mbed_official | 441:d2c15dda23c1 | 91 | #endif /* HSI_VALUE */ |
| mbed_official | 441:d2c15dda23c1 | 92 | |
| mbed_official | 441:d2c15dda23c1 | 93 | /** |
| mbed_official | 441:d2c15dda23c1 | 94 | * @} |
| mbed_official | 441:d2c15dda23c1 | 95 | */ |
| mbed_official | 441:d2c15dda23c1 | 96 | |
| mbed_official | 441:d2c15dda23c1 | 97 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions |
| mbed_official | 441:d2c15dda23c1 | 98 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 99 | */ |
| mbed_official | 441:d2c15dda23c1 | 100 | |
| mbed_official | 441:d2c15dda23c1 | 101 | /** |
| mbed_official | 441:d2c15dda23c1 | 102 | * @} |
| mbed_official | 441:d2c15dda23c1 | 103 | */ |
| mbed_official | 441:d2c15dda23c1 | 104 | |
| mbed_official | 441:d2c15dda23c1 | 105 | /** @addtogroup STM32F4xx_System_Private_Defines |
| mbed_official | 441:d2c15dda23c1 | 106 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 107 | */ |
| mbed_official | 441:d2c15dda23c1 | 108 | |
| mbed_official | 441:d2c15dda23c1 | 109 | /************************* Miscellaneous Configuration ************************/ |
| mbed_official | 441:d2c15dda23c1 | 110 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted |
| mbed_official | 441:d2c15dda23c1 | 111 | on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ |
| mbed_official | 441:d2c15dda23c1 | 112 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 441:d2c15dda23c1 | 113 | /* #define DATA_IN_ExtSRAM */ |
| mbed_official | 441:d2c15dda23c1 | 114 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 441:d2c15dda23c1 | 115 | |
| mbed_official | 441:d2c15dda23c1 | 116 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 441:d2c15dda23c1 | 117 | /* #define DATA_IN_ExtSDRAM */ |
| mbed_official | 441:d2c15dda23c1 | 118 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 441:d2c15dda23c1 | 119 | |
| mbed_official | 441:d2c15dda23c1 | 120 | #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) |
| mbed_official | 441:d2c15dda23c1 | 121 | #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " |
| mbed_official | 441:d2c15dda23c1 | 122 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ |
| mbed_official | 441:d2c15dda23c1 | 123 | |
| mbed_official | 441:d2c15dda23c1 | 124 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| mbed_official | 441:d2c15dda23c1 | 125 | Internal SRAM. */ |
| mbed_official | 441:d2c15dda23c1 | 126 | /* #define VECT_TAB_SRAM */ |
| mbed_official | 498:b3c41e21851c | 127 | #ifndef VECT_TAB_OFFSET |
| mbed_official | 441:d2c15dda23c1 | 128 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
| mbed_official | 441:d2c15dda23c1 | 129 | This value must be a multiple of 0x200. */ |
| mbed_official | 498:b3c41e21851c | 130 | #endif |
| mbed_official | 441:d2c15dda23c1 | 131 | /******************************************************************************/ |
| mbed_official | 441:d2c15dda23c1 | 132 | |
| mbed_official | 441:d2c15dda23c1 | 133 | /** |
| mbed_official | 441:d2c15dda23c1 | 134 | * @} |
| mbed_official | 441:d2c15dda23c1 | 135 | */ |
| mbed_official | 441:d2c15dda23c1 | 136 | |
| mbed_official | 441:d2c15dda23c1 | 137 | /** @addtogroup STM32F4xx_System_Private_Macros |
| mbed_official | 441:d2c15dda23c1 | 138 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 139 | */ |
| mbed_official | 441:d2c15dda23c1 | 140 | |
| mbed_official | 441:d2c15dda23c1 | 141 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| mbed_official | 441:d2c15dda23c1 | 142 | #define USE_PLL_HSE_EXTC (0) /* Use external clock */ |
| mbed_official | 441:d2c15dda23c1 | 143 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
| mbed_official | 441:d2c15dda23c1 | 144 | |
| mbed_official | 441:d2c15dda23c1 | 145 | /** |
| mbed_official | 441:d2c15dda23c1 | 146 | * @} |
| mbed_official | 441:d2c15dda23c1 | 147 | */ |
| mbed_official | 441:d2c15dda23c1 | 148 | |
| mbed_official | 441:d2c15dda23c1 | 149 | /** @addtogroup STM32F4xx_System_Private_Variables |
| mbed_official | 441:d2c15dda23c1 | 150 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 151 | */ |
| mbed_official | 441:d2c15dda23c1 | 152 | /* This variable is updated in three ways: |
| mbed_official | 441:d2c15dda23c1 | 153 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| mbed_official | 441:d2c15dda23c1 | 154 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| mbed_official | 441:d2c15dda23c1 | 155 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| mbed_official | 441:d2c15dda23c1 | 156 | Note: If you use this function to configure the system clock; then there |
| mbed_official | 441:d2c15dda23c1 | 157 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| mbed_official | 441:d2c15dda23c1 | 158 | variable is updated automatically. |
| mbed_official | 441:d2c15dda23c1 | 159 | */ |
| mbed_official | 441:d2c15dda23c1 | 160 | uint32_t SystemCoreClock = 16000000; |
| mbed_official | 441:d2c15dda23c1 | 161 | __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| mbed_official | 441:d2c15dda23c1 | 162 | |
| mbed_official | 441:d2c15dda23c1 | 163 | /** |
| mbed_official | 441:d2c15dda23c1 | 164 | * @} |
| mbed_official | 441:d2c15dda23c1 | 165 | */ |
| mbed_official | 441:d2c15dda23c1 | 166 | |
| mbed_official | 441:d2c15dda23c1 | 167 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes |
| mbed_official | 441:d2c15dda23c1 | 168 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 169 | */ |
| mbed_official | 441:d2c15dda23c1 | 170 | |
| mbed_official | 441:d2c15dda23c1 | 171 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 441:d2c15dda23c1 | 172 | static void SystemInit_ExtMemCtl(void); |
| mbed_official | 441:d2c15dda23c1 | 173 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 441:d2c15dda23c1 | 174 | |
| mbed_official | 441:d2c15dda23c1 | 175 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 441:d2c15dda23c1 | 176 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| mbed_official | 441:d2c15dda23c1 | 177 | #endif |
| mbed_official | 441:d2c15dda23c1 | 178 | |
| mbed_official | 441:d2c15dda23c1 | 179 | uint8_t SetSysClock_PLL_HSI(void); |
| mbed_official | 441:d2c15dda23c1 | 180 | |
| mbed_official | 441:d2c15dda23c1 | 181 | /** |
| mbed_official | 441:d2c15dda23c1 | 182 | * @} |
| mbed_official | 441:d2c15dda23c1 | 183 | */ |
| mbed_official | 441:d2c15dda23c1 | 184 | |
| mbed_official | 441:d2c15dda23c1 | 185 | /** @addtogroup STM32F4xx_System_Private_Functions |
| mbed_official | 441:d2c15dda23c1 | 186 | * @{ |
| mbed_official | 441:d2c15dda23c1 | 187 | */ |
| mbed_official | 441:d2c15dda23c1 | 188 | |
| mbed_official | 441:d2c15dda23c1 | 189 | /** |
| mbed_official | 441:d2c15dda23c1 | 190 | * @brief Setup the microcontroller system |
| mbed_official | 441:d2c15dda23c1 | 191 | * Initialize the FPU setting, vector table location and External memory |
| mbed_official | 441:d2c15dda23c1 | 192 | * configuration. |
| mbed_official | 441:d2c15dda23c1 | 193 | * @param None |
| mbed_official | 441:d2c15dda23c1 | 194 | * @retval None |
| mbed_official | 441:d2c15dda23c1 | 195 | */ |
| mbed_official | 441:d2c15dda23c1 | 196 | void SystemInit(void) |
| mbed_official | 441:d2c15dda23c1 | 197 | { |
| mbed_official | 441:d2c15dda23c1 | 198 | /* FPU settings ------------------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 199 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| mbed_official | 441:d2c15dda23c1 | 200 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
| mbed_official | 441:d2c15dda23c1 | 201 | #endif |
| mbed_official | 441:d2c15dda23c1 | 202 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| mbed_official | 441:d2c15dda23c1 | 203 | /* Set HSION bit */ |
| mbed_official | 441:d2c15dda23c1 | 204 | RCC->CR |= (uint32_t)0x00000001; |
| mbed_official | 441:d2c15dda23c1 | 205 | |
| mbed_official | 441:d2c15dda23c1 | 206 | /* Reset CFGR register */ |
| mbed_official | 441:d2c15dda23c1 | 207 | RCC->CFGR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 208 | |
| mbed_official | 441:d2c15dda23c1 | 209 | /* Reset HSEON, CSSON and PLLON bits */ |
| mbed_official | 441:d2c15dda23c1 | 210 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| mbed_official | 441:d2c15dda23c1 | 211 | |
| mbed_official | 441:d2c15dda23c1 | 212 | /* Reset PLLCFGR register */ |
| mbed_official | 441:d2c15dda23c1 | 213 | RCC->PLLCFGR = 0x24003010; |
| mbed_official | 441:d2c15dda23c1 | 214 | |
| mbed_official | 441:d2c15dda23c1 | 215 | /* Reset HSEBYP bit */ |
| mbed_official | 441:d2c15dda23c1 | 216 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| mbed_official | 441:d2c15dda23c1 | 217 | |
| mbed_official | 441:d2c15dda23c1 | 218 | /* Disable all interrupts */ |
| mbed_official | 441:d2c15dda23c1 | 219 | RCC->CIR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 220 | |
| mbed_official | 441:d2c15dda23c1 | 221 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 441:d2c15dda23c1 | 222 | SystemInit_ExtMemCtl(); |
| mbed_official | 441:d2c15dda23c1 | 223 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 441:d2c15dda23c1 | 224 | |
| mbed_official | 441:d2c15dda23c1 | 225 | /* Configure the Vector Table location add offset address ------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 226 | #ifdef VECT_TAB_SRAM |
| mbed_official | 441:d2c15dda23c1 | 227 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
| mbed_official | 441:d2c15dda23c1 | 228 | #else |
| mbed_official | 441:d2c15dda23c1 | 229 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| mbed_official | 441:d2c15dda23c1 | 230 | #endif |
| mbed_official | 441:d2c15dda23c1 | 231 | |
| mbed_official | 441:d2c15dda23c1 | 232 | /* Configure the Cube driver */ |
| mbed_official | 441:d2c15dda23c1 | 233 | SystemCoreClock = 16000000; // At this stage the HSI is used as system clock |
| mbed_official | 441:d2c15dda23c1 | 234 | HAL_Init(); |
| mbed_official | 441:d2c15dda23c1 | 235 | |
| mbed_official | 441:d2c15dda23c1 | 236 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 441:d2c15dda23c1 | 237 | AHB/APBx prescalers and Flash settings */ |
| mbed_official | 441:d2c15dda23c1 | 238 | SetSysClock(); |
| mbed_official | 441:d2c15dda23c1 | 239 | |
| mbed_official | 441:d2c15dda23c1 | 240 | /* Reset the timer to avoid issues after the RAM initialization */ |
| mbed_official | 441:d2c15dda23c1 | 241 | TIM_MST_RESET_ON; |
| mbed_official | 441:d2c15dda23c1 | 242 | TIM_MST_RESET_OFF; |
| mbed_official | 441:d2c15dda23c1 | 243 | } |
| mbed_official | 441:d2c15dda23c1 | 244 | |
| mbed_official | 441:d2c15dda23c1 | 245 | /** |
| mbed_official | 441:d2c15dda23c1 | 246 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| mbed_official | 441:d2c15dda23c1 | 247 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| mbed_official | 441:d2c15dda23c1 | 248 | * be used by the user application to setup the SysTick timer or configure |
| mbed_official | 441:d2c15dda23c1 | 249 | * other parameters. |
| mbed_official | 441:d2c15dda23c1 | 250 | * |
| mbed_official | 441:d2c15dda23c1 | 251 | * @note Each time the core clock (HCLK) changes, this function must be called |
| mbed_official | 441:d2c15dda23c1 | 252 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| mbed_official | 441:d2c15dda23c1 | 253 | * based on this variable will be incorrect. |
| mbed_official | 441:d2c15dda23c1 | 254 | * |
| mbed_official | 441:d2c15dda23c1 | 255 | * @note - The system frequency computed by this function is not the real |
| mbed_official | 441:d2c15dda23c1 | 256 | * frequency in the chip. It is calculated based on the predefined |
| mbed_official | 441:d2c15dda23c1 | 257 | * constant and the selected clock source: |
| mbed_official | 441:d2c15dda23c1 | 258 | * |
| mbed_official | 441:d2c15dda23c1 | 259 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| mbed_official | 441:d2c15dda23c1 | 260 | * |
| mbed_official | 441:d2c15dda23c1 | 261 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 441:d2c15dda23c1 | 262 | * |
| mbed_official | 441:d2c15dda23c1 | 263 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 441:d2c15dda23c1 | 264 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| mbed_official | 441:d2c15dda23c1 | 265 | * |
| mbed_official | 441:d2c15dda23c1 | 266 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
| mbed_official | 441:d2c15dda23c1 | 267 | * 16 MHz) but the real value may vary depending on the variations |
| mbed_official | 441:d2c15dda23c1 | 268 | * in voltage and temperature. |
| mbed_official | 441:d2c15dda23c1 | 269 | * |
| mbed_official | 441:d2c15dda23c1 | 270 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value |
| mbed_official | 441:d2c15dda23c1 | 271 | * depends on the application requirements), user has to ensure that HSE_VALUE |
| mbed_official | 441:d2c15dda23c1 | 272 | * is same as the real frequency of the crystal used. Otherwise, this function |
| mbed_official | 441:d2c15dda23c1 | 273 | * may have wrong result. |
| mbed_official | 441:d2c15dda23c1 | 274 | * |
| mbed_official | 441:d2c15dda23c1 | 275 | * - The result of this function could be not correct when using fractional |
| mbed_official | 441:d2c15dda23c1 | 276 | * value for HSE crystal. |
| mbed_official | 441:d2c15dda23c1 | 277 | * |
| mbed_official | 441:d2c15dda23c1 | 278 | * @param None |
| mbed_official | 441:d2c15dda23c1 | 279 | * @retval None |
| mbed_official | 441:d2c15dda23c1 | 280 | */ |
| mbed_official | 441:d2c15dda23c1 | 281 | void SystemCoreClockUpdate(void) |
| mbed_official | 441:d2c15dda23c1 | 282 | { |
| mbed_official | 441:d2c15dda23c1 | 283 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
| mbed_official | 441:d2c15dda23c1 | 284 | |
| mbed_official | 441:d2c15dda23c1 | 285 | /* Get SYSCLK source -------------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 286 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| mbed_official | 441:d2c15dda23c1 | 287 | |
| mbed_official | 441:d2c15dda23c1 | 288 | switch (tmp) |
| mbed_official | 441:d2c15dda23c1 | 289 | { |
| mbed_official | 441:d2c15dda23c1 | 290 | case 0x00: /* HSI used as system clock source */ |
| mbed_official | 441:d2c15dda23c1 | 291 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 441:d2c15dda23c1 | 292 | break; |
| mbed_official | 441:d2c15dda23c1 | 293 | case 0x04: /* HSE used as system clock source */ |
| mbed_official | 441:d2c15dda23c1 | 294 | SystemCoreClock = HSE_VALUE; |
| mbed_official | 441:d2c15dda23c1 | 295 | break; |
| mbed_official | 441:d2c15dda23c1 | 296 | case 0x08: /* PLL used as system clock source */ |
| mbed_official | 441:d2c15dda23c1 | 297 | |
| mbed_official | 441:d2c15dda23c1 | 298 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
| mbed_official | 441:d2c15dda23c1 | 299 | SYSCLK = PLL_VCO / PLL_P |
| mbed_official | 441:d2c15dda23c1 | 300 | */ |
| mbed_official | 441:d2c15dda23c1 | 301 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
| mbed_official | 441:d2c15dda23c1 | 302 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
| mbed_official | 441:d2c15dda23c1 | 303 | |
| mbed_official | 441:d2c15dda23c1 | 304 | if (pllsource != 0) |
| mbed_official | 441:d2c15dda23c1 | 305 | { |
| mbed_official | 441:d2c15dda23c1 | 306 | /* HSE used as PLL clock source */ |
| mbed_official | 441:d2c15dda23c1 | 307 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| mbed_official | 441:d2c15dda23c1 | 308 | } |
| mbed_official | 441:d2c15dda23c1 | 309 | else |
| mbed_official | 441:d2c15dda23c1 | 310 | { |
| mbed_official | 441:d2c15dda23c1 | 311 | /* HSI used as PLL clock source */ |
| mbed_official | 441:d2c15dda23c1 | 312 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| mbed_official | 441:d2c15dda23c1 | 313 | } |
| mbed_official | 441:d2c15dda23c1 | 314 | |
| mbed_official | 441:d2c15dda23c1 | 315 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
| mbed_official | 441:d2c15dda23c1 | 316 | SystemCoreClock = pllvco/pllp; |
| mbed_official | 441:d2c15dda23c1 | 317 | break; |
| mbed_official | 441:d2c15dda23c1 | 318 | default: |
| mbed_official | 441:d2c15dda23c1 | 319 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 441:d2c15dda23c1 | 320 | break; |
| mbed_official | 441:d2c15dda23c1 | 321 | } |
| mbed_official | 441:d2c15dda23c1 | 322 | /* Compute HCLK frequency --------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 323 | /* Get HCLK prescaler */ |
| mbed_official | 441:d2c15dda23c1 | 324 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| mbed_official | 441:d2c15dda23c1 | 325 | /* HCLK frequency */ |
| mbed_official | 441:d2c15dda23c1 | 326 | SystemCoreClock >>= tmp; |
| mbed_official | 441:d2c15dda23c1 | 327 | } |
| mbed_official | 441:d2c15dda23c1 | 328 | |
| mbed_official | 441:d2c15dda23c1 | 329 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 441:d2c15dda23c1 | 330 | /** |
| mbed_official | 441:d2c15dda23c1 | 331 | * @brief Setup the external memory controller. |
| mbed_official | 441:d2c15dda23c1 | 332 | * Called in startup_stm32f4xx.s before jump to main. |
| mbed_official | 441:d2c15dda23c1 | 333 | * This function configures the external memories (SRAM/SDRAM) |
| mbed_official | 441:d2c15dda23c1 | 334 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| mbed_official | 441:d2c15dda23c1 | 335 | * @param None |
| mbed_official | 441:d2c15dda23c1 | 336 | * @retval None |
| mbed_official | 441:d2c15dda23c1 | 337 | */ |
| mbed_official | 441:d2c15dda23c1 | 338 | void SystemInit_ExtMemCtl(void) |
| mbed_official | 441:d2c15dda23c1 | 339 | { |
| mbed_official | 441:d2c15dda23c1 | 340 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 441:d2c15dda23c1 | 341 | #if defined (DATA_IN_ExtSDRAM) |
| mbed_official | 441:d2c15dda23c1 | 342 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| mbed_official | 441:d2c15dda23c1 | 343 | register uint32_t index; |
| mbed_official | 441:d2c15dda23c1 | 344 | |
| mbed_official | 441:d2c15dda23c1 | 345 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| mbed_official | 441:d2c15dda23c1 | 346 | clock */ |
| mbed_official | 441:d2c15dda23c1 | 347 | RCC->AHB1ENR |= 0x000001F8; |
| mbed_official | 441:d2c15dda23c1 | 348 | |
| mbed_official | 441:d2c15dda23c1 | 349 | /* Connect PDx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 350 | GPIOD->AFR[0] = 0x000000CC; |
| mbed_official | 441:d2c15dda23c1 | 351 | GPIOD->AFR[1] = 0xCC000CCC; |
| mbed_official | 441:d2c15dda23c1 | 352 | /* Configure PDx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 353 | GPIOD->MODER = 0xA02A000A; |
| mbed_official | 441:d2c15dda23c1 | 354 | /* Configure PDx pins speed to 50 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 355 | GPIOD->OSPEEDR = 0xA02A000A; |
| mbed_official | 441:d2c15dda23c1 | 356 | /* Configure PDx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 357 | GPIOD->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 358 | /* No pull-up, pull-down for PDx pins */ |
| mbed_official | 441:d2c15dda23c1 | 359 | GPIOD->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 360 | |
| mbed_official | 441:d2c15dda23c1 | 361 | /* Connect PEx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 362 | GPIOE->AFR[0] = 0xC00000CC; |
| mbed_official | 441:d2c15dda23c1 | 363 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 364 | /* Configure PEx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 365 | GPIOE->MODER = 0xAAAA800A; |
| mbed_official | 441:d2c15dda23c1 | 366 | /* Configure PEx pins speed to 50 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 367 | GPIOE->OSPEEDR = 0xAAAA800A; |
| mbed_official | 441:d2c15dda23c1 | 368 | /* Configure PEx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 369 | GPIOE->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 370 | /* No pull-up, pull-down for PEx pins */ |
| mbed_official | 441:d2c15dda23c1 | 371 | GPIOE->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 372 | |
| mbed_official | 441:d2c15dda23c1 | 373 | /* Connect PFx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 374 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 375 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 376 | /* Configure PFx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 377 | GPIOF->MODER = 0xAA800AAA; |
| mbed_official | 441:d2c15dda23c1 | 378 | /* Configure PFx pins speed to 50 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 379 | GPIOF->OSPEEDR = 0xAA800AAA; |
| mbed_official | 441:d2c15dda23c1 | 380 | /* Configure PFx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 381 | GPIOF->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 382 | /* No pull-up, pull-down for PFx pins */ |
| mbed_official | 441:d2c15dda23c1 | 383 | GPIOF->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 384 | |
| mbed_official | 441:d2c15dda23c1 | 385 | /* Connect PGx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 386 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 387 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 388 | /* Configure PGx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 389 | GPIOG->MODER = 0xAAAAAAAA; |
| mbed_official | 441:d2c15dda23c1 | 390 | /* Configure PGx pins speed to 50 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 391 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| mbed_official | 441:d2c15dda23c1 | 392 | /* Configure PGx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 393 | GPIOG->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 394 | /* No pull-up, pull-down for PGx pins */ |
| mbed_official | 441:d2c15dda23c1 | 395 | GPIOG->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 396 | |
| mbed_official | 441:d2c15dda23c1 | 397 | /* Connect PHx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 398 | GPIOH->AFR[0] = 0x00C0CC00; |
| mbed_official | 441:d2c15dda23c1 | 399 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 400 | /* Configure PHx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 401 | GPIOH->MODER = 0xAAAA08A0; |
| mbed_official | 441:d2c15dda23c1 | 402 | /* Configure PHx pins speed to 50 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 403 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| mbed_official | 441:d2c15dda23c1 | 404 | /* Configure PHx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 405 | GPIOH->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 406 | /* No pull-up, pull-down for PHx pins */ |
| mbed_official | 441:d2c15dda23c1 | 407 | GPIOH->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 408 | |
| mbed_official | 441:d2c15dda23c1 | 409 | /* Connect PIx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 410 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 411 | GPIOI->AFR[1] = 0x00000CC0; |
| mbed_official | 441:d2c15dda23c1 | 412 | /* Configure PIx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 413 | GPIOI->MODER = 0x0028AAAA; |
| mbed_official | 441:d2c15dda23c1 | 414 | /* Configure PIx pins speed to 50 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 415 | GPIOI->OSPEEDR = 0x0028AAAA; |
| mbed_official | 441:d2c15dda23c1 | 416 | /* Configure PIx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 417 | GPIOI->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 418 | /* No pull-up, pull-down for PIx pins */ |
| mbed_official | 441:d2c15dda23c1 | 419 | GPIOI->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 420 | |
| mbed_official | 441:d2c15dda23c1 | 421 | /*-- FMC Configuration ------------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 422 | /* Enable the FMC interface clock */ |
| mbed_official | 441:d2c15dda23c1 | 423 | RCC->AHB3ENR |= 0x00000001; |
| mbed_official | 441:d2c15dda23c1 | 424 | |
| mbed_official | 441:d2c15dda23c1 | 425 | /* Configure and enable SDRAM bank1 */ |
| mbed_official | 441:d2c15dda23c1 | 426 | FMC_Bank5_6->SDCR[0] = 0x000019E0; |
| mbed_official | 441:d2c15dda23c1 | 427 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| mbed_official | 441:d2c15dda23c1 | 428 | |
| mbed_official | 441:d2c15dda23c1 | 429 | /* SDRAM initialization sequence */ |
| mbed_official | 441:d2c15dda23c1 | 430 | /* Clock enable command */ |
| mbed_official | 441:d2c15dda23c1 | 431 | FMC_Bank5_6->SDCMR = 0x00000011; |
| mbed_official | 441:d2c15dda23c1 | 432 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 441:d2c15dda23c1 | 433 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 441:d2c15dda23c1 | 434 | { |
| mbed_official | 441:d2c15dda23c1 | 435 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 441:d2c15dda23c1 | 436 | } |
| mbed_official | 441:d2c15dda23c1 | 437 | |
| mbed_official | 441:d2c15dda23c1 | 438 | /* Delay */ |
| mbed_official | 441:d2c15dda23c1 | 439 | for (index = 0; index<1000; index++); |
| mbed_official | 441:d2c15dda23c1 | 440 | |
| mbed_official | 441:d2c15dda23c1 | 441 | /* PALL command */ |
| mbed_official | 441:d2c15dda23c1 | 442 | FMC_Bank5_6->SDCMR = 0x00000012; |
| mbed_official | 441:d2c15dda23c1 | 443 | timeout = 0xFFFF; |
| mbed_official | 441:d2c15dda23c1 | 444 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 441:d2c15dda23c1 | 445 | { |
| mbed_official | 441:d2c15dda23c1 | 446 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 441:d2c15dda23c1 | 447 | } |
| mbed_official | 441:d2c15dda23c1 | 448 | |
| mbed_official | 441:d2c15dda23c1 | 449 | /* Auto refresh command */ |
| mbed_official | 441:d2c15dda23c1 | 450 | FMC_Bank5_6->SDCMR = 0x00000073; |
| mbed_official | 441:d2c15dda23c1 | 451 | timeout = 0xFFFF; |
| mbed_official | 441:d2c15dda23c1 | 452 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 441:d2c15dda23c1 | 453 | { |
| mbed_official | 441:d2c15dda23c1 | 454 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 441:d2c15dda23c1 | 455 | } |
| mbed_official | 441:d2c15dda23c1 | 456 | |
| mbed_official | 441:d2c15dda23c1 | 457 | /* MRD register program */ |
| mbed_official | 441:d2c15dda23c1 | 458 | FMC_Bank5_6->SDCMR = 0x00046014; |
| mbed_official | 441:d2c15dda23c1 | 459 | timeout = 0xFFFF; |
| mbed_official | 441:d2c15dda23c1 | 460 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 441:d2c15dda23c1 | 461 | { |
| mbed_official | 441:d2c15dda23c1 | 462 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 441:d2c15dda23c1 | 463 | } |
| mbed_official | 441:d2c15dda23c1 | 464 | |
| mbed_official | 441:d2c15dda23c1 | 465 | /* Set refresh count */ |
| mbed_official | 441:d2c15dda23c1 | 466 | tmpreg = FMC_Bank5_6->SDRTR; |
| mbed_official | 441:d2c15dda23c1 | 467 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| mbed_official | 441:d2c15dda23c1 | 468 | |
| mbed_official | 441:d2c15dda23c1 | 469 | /* Disable write protection */ |
| mbed_official | 441:d2c15dda23c1 | 470 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| mbed_official | 441:d2c15dda23c1 | 471 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| mbed_official | 441:d2c15dda23c1 | 472 | #endif /* DATA_IN_ExtSDRAM */ |
| mbed_official | 441:d2c15dda23c1 | 473 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 441:d2c15dda23c1 | 474 | |
| mbed_official | 441:d2c15dda23c1 | 475 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 441:d2c15dda23c1 | 476 | #if defined(DATA_IN_ExtSRAM) |
| mbed_official | 441:d2c15dda23c1 | 477 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 478 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| mbed_official | 441:d2c15dda23c1 | 479 | RCC->AHB1ENR |= 0x00000078; |
| mbed_official | 441:d2c15dda23c1 | 480 | |
| mbed_official | 441:d2c15dda23c1 | 481 | /* Connect PDx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 482 | GPIOD->AFR[0] = 0x00CCC0CC; |
| mbed_official | 441:d2c15dda23c1 | 483 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 484 | /* Configure PDx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 485 | GPIOD->MODER = 0xAAAA0A8A; |
| mbed_official | 441:d2c15dda23c1 | 486 | /* Configure PDx pins speed to 100 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 487 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| mbed_official | 441:d2c15dda23c1 | 488 | /* Configure PDx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 489 | GPIOD->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 490 | /* No pull-up, pull-down for PDx pins */ |
| mbed_official | 441:d2c15dda23c1 | 491 | GPIOD->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 492 | |
| mbed_official | 441:d2c15dda23c1 | 493 | /* Connect PEx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 494 | GPIOE->AFR[0] = 0xC00CC0CC; |
| mbed_official | 441:d2c15dda23c1 | 495 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 496 | /* Configure PEx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 497 | GPIOE->MODER = 0xAAAA828A; |
| mbed_official | 441:d2c15dda23c1 | 498 | /* Configure PEx pins speed to 100 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 499 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| mbed_official | 441:d2c15dda23c1 | 500 | /* Configure PEx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 501 | GPIOE->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 502 | /* No pull-up, pull-down for PEx pins */ |
| mbed_official | 441:d2c15dda23c1 | 503 | GPIOE->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 504 | |
| mbed_official | 441:d2c15dda23c1 | 505 | /* Connect PFx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 506 | GPIOF->AFR[0] = 0x00CCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 507 | GPIOF->AFR[1] = 0xCCCC0000; |
| mbed_official | 441:d2c15dda23c1 | 508 | /* Configure PFx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 509 | GPIOF->MODER = 0xAA000AAA; |
| mbed_official | 441:d2c15dda23c1 | 510 | /* Configure PFx pins speed to 100 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 511 | GPIOF->OSPEEDR = 0xFF000FFF; |
| mbed_official | 441:d2c15dda23c1 | 512 | /* Configure PFx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 513 | GPIOF->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 514 | /* No pull-up, pull-down for PFx pins */ |
| mbed_official | 441:d2c15dda23c1 | 515 | GPIOF->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 516 | |
| mbed_official | 441:d2c15dda23c1 | 517 | /* Connect PGx pins to FMC Alternate function */ |
| mbed_official | 441:d2c15dda23c1 | 518 | GPIOG->AFR[0] = 0x00CCCCCC; |
| mbed_official | 441:d2c15dda23c1 | 519 | GPIOG->AFR[1] = 0x000000C0; |
| mbed_official | 441:d2c15dda23c1 | 520 | /* Configure PGx pins in Alternate function mode */ |
| mbed_official | 441:d2c15dda23c1 | 521 | GPIOG->MODER = 0x00085AAA; |
| mbed_official | 441:d2c15dda23c1 | 522 | /* Configure PGx pins speed to 100 MHz */ |
| mbed_official | 441:d2c15dda23c1 | 523 | GPIOG->OSPEEDR = 0x000CAFFF; |
| mbed_official | 441:d2c15dda23c1 | 524 | /* Configure PGx pins Output type to push-pull */ |
| mbed_official | 441:d2c15dda23c1 | 525 | GPIOG->OTYPER = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 526 | /* No pull-up, pull-down for PGx pins */ |
| mbed_official | 441:d2c15dda23c1 | 527 | GPIOG->PUPDR = 0x00000000; |
| mbed_official | 441:d2c15dda23c1 | 528 | |
| mbed_official | 441:d2c15dda23c1 | 529 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 530 | /* Enable the FMC/FSMC interface clock */ |
| mbed_official | 441:d2c15dda23c1 | 531 | RCC->AHB3ENR |= 0x00000001; |
| mbed_official | 441:d2c15dda23c1 | 532 | |
| mbed_official | 441:d2c15dda23c1 | 533 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 441:d2c15dda23c1 | 534 | /* Configure and enable Bank1_SRAM2 */ |
| mbed_official | 441:d2c15dda23c1 | 535 | FMC_Bank1->BTCR[2] = 0x00001011; |
| mbed_official | 441:d2c15dda23c1 | 536 | FMC_Bank1->BTCR[3] = 0x00000201; |
| mbed_official | 441:d2c15dda23c1 | 537 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| mbed_official | 441:d2c15dda23c1 | 538 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 441:d2c15dda23c1 | 539 | |
| mbed_official | 441:d2c15dda23c1 | 540 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) |
| mbed_official | 441:d2c15dda23c1 | 541 | /* Configure and enable Bank1_SRAM2 */ |
| mbed_official | 441:d2c15dda23c1 | 542 | FSMC_Bank1->BTCR[2] = 0x00001011; |
| mbed_official | 441:d2c15dda23c1 | 543 | FSMC_Bank1->BTCR[3] = 0x00000201; |
| mbed_official | 441:d2c15dda23c1 | 544 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
| mbed_official | 441:d2c15dda23c1 | 545 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| mbed_official | 441:d2c15dda23c1 | 546 | |
| mbed_official | 441:d2c15dda23c1 | 547 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 441:d2c15dda23c1 | 548 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 441:d2c15dda23c1 | 549 | } |
| mbed_official | 441:d2c15dda23c1 | 550 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 441:d2c15dda23c1 | 551 | |
| mbed_official | 441:d2c15dda23c1 | 552 | /** |
| mbed_official | 441:d2c15dda23c1 | 553 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 441:d2c15dda23c1 | 554 | * AHB/APBx prescalers and Flash settings |
| mbed_official | 441:d2c15dda23c1 | 555 | * @note This function should be called only once the RCC clock configuration |
| mbed_official | 441:d2c15dda23c1 | 556 | * is reset to the default reset state (done in SystemInit() function). |
| mbed_official | 441:d2c15dda23c1 | 557 | * @param None |
| mbed_official | 441:d2c15dda23c1 | 558 | * @retval None |
| mbed_official | 441:d2c15dda23c1 | 559 | */ |
| mbed_official | 441:d2c15dda23c1 | 560 | void SetSysClock(void) |
| mbed_official | 441:d2c15dda23c1 | 561 | { |
| mbed_official | 441:d2c15dda23c1 | 562 | /* 1- Try to start with HSE and external clock */ |
| mbed_official | 441:d2c15dda23c1 | 563 | #if USE_PLL_HSE_EXTC != 0 |
| mbed_official | 441:d2c15dda23c1 | 564 | if (SetSysClock_PLL_HSE(1) == 0) |
| mbed_official | 441:d2c15dda23c1 | 565 | #endif |
| mbed_official | 441:d2c15dda23c1 | 566 | { |
| mbed_official | 441:d2c15dda23c1 | 567 | /* 2- If fail try to start with HSE and external xtal */ |
| mbed_official | 441:d2c15dda23c1 | 568 | #if USE_PLL_HSE_XTAL != 0 |
| mbed_official | 441:d2c15dda23c1 | 569 | if (SetSysClock_PLL_HSE(0) == 0) |
| mbed_official | 441:d2c15dda23c1 | 570 | #endif |
| mbed_official | 441:d2c15dda23c1 | 571 | { |
| mbed_official | 441:d2c15dda23c1 | 572 | /* 3- If fail start with HSI clock */ |
| mbed_official | 441:d2c15dda23c1 | 573 | if (SetSysClock_PLL_HSI() == 0) |
| mbed_official | 441:d2c15dda23c1 | 574 | { |
| mbed_official | 441:d2c15dda23c1 | 575 | while(1) |
| mbed_official | 441:d2c15dda23c1 | 576 | { |
| mbed_official | 441:d2c15dda23c1 | 577 | // [TODO] Put something here to tell the user that a problem occured... |
| mbed_official | 441:d2c15dda23c1 | 578 | } |
| mbed_official | 441:d2c15dda23c1 | 579 | } |
| mbed_official | 441:d2c15dda23c1 | 580 | } |
| mbed_official | 441:d2c15dda23c1 | 581 | } |
| mbed_official | 441:d2c15dda23c1 | 582 | |
| mbed_official | 441:d2c15dda23c1 | 583 | /* Output clock on MCO2 pin(PC9) for debugging purpose */ |
| mbed_official | 441:d2c15dda23c1 | 584 | //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz |
| mbed_official | 441:d2c15dda23c1 | 585 | } |
| mbed_official | 441:d2c15dda23c1 | 586 | |
| mbed_official | 441:d2c15dda23c1 | 587 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 441:d2c15dda23c1 | 588 | /******************************************************************************/ |
| mbed_official | 441:d2c15dda23c1 | 589 | /* PLL (clocked by HSE) used as System clock source */ |
| mbed_official | 441:d2c15dda23c1 | 590 | /******************************************************************************/ |
| mbed_official | 441:d2c15dda23c1 | 591 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| mbed_official | 441:d2c15dda23c1 | 592 | { |
| mbed_official | 441:d2c15dda23c1 | 593 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 441:d2c15dda23c1 | 594 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 441:d2c15dda23c1 | 595 | |
| mbed_official | 441:d2c15dda23c1 | 596 | /* The voltage scaling allows optimizing the power consumption when the device is |
| mbed_official | 441:d2c15dda23c1 | 597 | clocked below the maximum system frequency, to update the voltage scaling value |
| mbed_official | 441:d2c15dda23c1 | 598 | regarding system frequency refer to product datasheet. */ |
| mbed_official | 441:d2c15dda23c1 | 599 | __PWR_CLK_ENABLE(); |
| mbed_official | 441:d2c15dda23c1 | 600 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); |
| mbed_official | 441:d2c15dda23c1 | 601 | |
| mbed_official | 441:d2c15dda23c1 | 602 | /* Enable HSE oscillator and activate PLL with HSE as source */ |
| mbed_official | 441:d2c15dda23c1 | 603 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 441:d2c15dda23c1 | 604 | if (bypass == 0) |
| mbed_official | 441:d2c15dda23c1 | 605 | { |
| mbed_official | 441:d2c15dda23c1 | 606 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
| mbed_official | 441:d2c15dda23c1 | 607 | } |
| mbed_official | 441:d2c15dda23c1 | 608 | else |
| mbed_official | 441:d2c15dda23c1 | 609 | { |
| mbed_official | 441:d2c15dda23c1 | 610 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
| mbed_official | 441:d2c15dda23c1 | 611 | } |
| mbed_official | 441:d2c15dda23c1 | 612 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 441:d2c15dda23c1 | 613 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| mbed_official | 441:d2c15dda23c1 | 614 | //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) |
| mbed_official | 441:d2c15dda23c1 | 615 | //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) |
| mbed_official | 441:d2c15dda23c1 | 616 | RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4) |
| mbed_official | 441:d2c15dda23c1 | 617 | RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200) |
| mbed_official | 441:d2c15dda23c1 | 618 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) |
| mbed_official | 441:d2c15dda23c1 | 619 | RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB |
| mbed_official | 441:d2c15dda23c1 | 620 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 621 | { |
| mbed_official | 441:d2c15dda23c1 | 622 | return 0; // FAIL |
| mbed_official | 441:d2c15dda23c1 | 623 | } |
| mbed_official | 441:d2c15dda23c1 | 624 | |
| mbed_official | 441:d2c15dda23c1 | 625 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| mbed_official | 441:d2c15dda23c1 | 626 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| mbed_official | 441:d2c15dda23c1 | 627 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz |
| mbed_official | 441:d2c15dda23c1 | 628 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz |
| mbed_official | 441:d2c15dda23c1 | 629 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz |
| mbed_official | 441:d2c15dda23c1 | 630 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz |
| mbed_official | 441:d2c15dda23c1 | 631 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 632 | { |
| mbed_official | 441:d2c15dda23c1 | 633 | return 0; // FAIL |
| mbed_official | 441:d2c15dda23c1 | 634 | } |
| mbed_official | 441:d2c15dda23c1 | 635 | |
| mbed_official | 441:d2c15dda23c1 | 636 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 441:d2c15dda23c1 | 637 | |
| mbed_official | 441:d2c15dda23c1 | 638 | //if (bypass == 0) |
| mbed_official | 441:d2c15dda23c1 | 639 | // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal |
| mbed_official | 441:d2c15dda23c1 | 640 | //else |
| mbed_official | 441:d2c15dda23c1 | 641 | // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock |
| mbed_official | 441:d2c15dda23c1 | 642 | |
| mbed_official | 441:d2c15dda23c1 | 643 | return 1; // OK |
| mbed_official | 441:d2c15dda23c1 | 644 | } |
| mbed_official | 441:d2c15dda23c1 | 645 | #endif |
| mbed_official | 441:d2c15dda23c1 | 646 | |
| mbed_official | 441:d2c15dda23c1 | 647 | /******************************************************************************/ |
| mbed_official | 441:d2c15dda23c1 | 648 | /* PLL (clocked by HSI) used as System clock source */ |
| mbed_official | 441:d2c15dda23c1 | 649 | /******************************************************************************/ |
| mbed_official | 441:d2c15dda23c1 | 650 | uint8_t SetSysClock_PLL_HSI(void) |
| mbed_official | 441:d2c15dda23c1 | 651 | { |
| mbed_official | 441:d2c15dda23c1 | 652 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 441:d2c15dda23c1 | 653 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 441:d2c15dda23c1 | 654 | |
| mbed_official | 441:d2c15dda23c1 | 655 | /* The voltage scaling allows optimizing the power consumption when the device is |
| mbed_official | 441:d2c15dda23c1 | 656 | clocked below the maximum system frequency, to update the voltage scaling value |
| mbed_official | 441:d2c15dda23c1 | 657 | regarding system frequency refer to product datasheet. */ |
| mbed_official | 441:d2c15dda23c1 | 658 | __PWR_CLK_ENABLE(); |
| mbed_official | 441:d2c15dda23c1 | 659 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); |
| mbed_official | 441:d2c15dda23c1 | 660 | |
| mbed_official | 441:d2c15dda23c1 | 661 | /* Enable HSI oscillator and activate PLL with HSI as source */ |
| mbed_official | 441:d2c15dda23c1 | 662 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 441:d2c15dda23c1 | 663 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| mbed_official | 441:d2c15dda23c1 | 664 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
| mbed_official | 441:d2c15dda23c1 | 665 | RCC_OscInitStruct.HSICalibrationValue = 16; |
| mbed_official | 441:d2c15dda23c1 | 666 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 441:d2c15dda23c1 | 667 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
| mbed_official | 441:d2c15dda23c1 | 668 | //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) |
| mbed_official | 441:d2c15dda23c1 | 669 | //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) |
| mbed_official | 441:d2c15dda23c1 | 670 | RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) |
| mbed_official | 441:d2c15dda23c1 | 671 | RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) |
| mbed_official | 441:d2c15dda23c1 | 672 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) |
| mbed_official | 441:d2c15dda23c1 | 673 | RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB |
| mbed_official | 441:d2c15dda23c1 | 674 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 675 | { |
| mbed_official | 441:d2c15dda23c1 | 676 | return 0; // FAIL |
| mbed_official | 441:d2c15dda23c1 | 677 | } |
| mbed_official | 441:d2c15dda23c1 | 678 | |
| mbed_official | 441:d2c15dda23c1 | 679 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| mbed_official | 441:d2c15dda23c1 | 680 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| mbed_official | 441:d2c15dda23c1 | 681 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz |
| mbed_official | 441:d2c15dda23c1 | 682 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz |
| mbed_official | 441:d2c15dda23c1 | 683 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz |
| mbed_official | 441:d2c15dda23c1 | 684 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz |
| mbed_official | 441:d2c15dda23c1 | 685 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 686 | { |
| mbed_official | 441:d2c15dda23c1 | 687 | return 0; // FAIL |
| mbed_official | 441:d2c15dda23c1 | 688 | } |
| mbed_official | 441:d2c15dda23c1 | 689 | |
| mbed_official | 441:d2c15dda23c1 | 690 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 441:d2c15dda23c1 | 691 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
| mbed_official | 441:d2c15dda23c1 | 692 | |
| mbed_official | 441:d2c15dda23c1 | 693 | return 1; // OK |
| mbed_official | 441:d2c15dda23c1 | 694 | } |
| mbed_official | 441:d2c15dda23c1 | 695 | |
| mbed_official | 441:d2c15dda23c1 | 696 | /** |
| mbed_official | 441:d2c15dda23c1 | 697 | * @} |
| mbed_official | 441:d2c15dda23c1 | 698 | */ |
| mbed_official | 441:d2c15dda23c1 | 699 | |
| mbed_official | 441:d2c15dda23c1 | 700 | /** |
| mbed_official | 441:d2c15dda23c1 | 701 | * @} |
| mbed_official | 441:d2c15dda23c1 | 702 | */ |
| mbed_official | 441:d2c15dda23c1 | 703 | |
| mbed_official | 441:d2c15dda23c1 | 704 | /** |
| mbed_official | 441:d2c15dda23c1 | 705 | * @} |
| mbed_official | 441:d2c15dda23c1 | 706 | */ |
| mbed_official | 441:d2c15dda23c1 | 707 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |