nrf51-sdk - Nordic nrf51 sdk sources. Mirrored from https://…

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Nordic nrf51 sdk sources. Mirrored from https://github.com/ARMmbed/nrf51-sdk.

source/nordic_sdk/components/device/nrf51.h@19:47192cb9def7, 2016-04-07 (annotated)

Committer:: vcoubard
Date:: Thu Apr 07 17:37:40 2016 +0100
Revision:: 19:47192cb9def7
Parent:: 13:7dbdb4ea405b
Child:: 20:a90c48eb1d30

Synchronized with git rev 9251259f

Author: Liyou Zhou

Copy over coresponding files from nordic-sdk 9.0.0

Who changed what in which revision?

User	Revision	Line number	New contents of line
vcoubard	19:47192cb9def7	1
vcoubard	19:47192cb9def7	2	/**************************************************************************************************//
vcoubard	19:47192cb9def7	3	* @file nrf51.h
vcoubard	19:47192cb9def7	4	*
vcoubard	19:47192cb9def7	5	* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
vcoubard	19:47192cb9def7	6	* nrf51 from Nordic Semiconductor.
vcoubard	19:47192cb9def7	7	*
vcoubard	19:47192cb9def7	8	* @version V522
vcoubard	19:47192cb9def7	9	* @date 15. June 2015
vcoubard	19:47192cb9def7	10	*
vcoubard	19:47192cb9def7	11	* @note Generated with SVDConv V2.81d
vcoubard	19:47192cb9def7	12	* from CMSIS SVD File 'nrf51.xml' Version 522,
vcoubard	19:47192cb9def7	13	*
vcoubard	19:47192cb9def7	14	* @par Copyright (c) 2013, Nordic Semiconductor ASA
vcoubard	19:47192cb9def7	15	* All rights reserved.
vcoubard	19:47192cb9def7	16	*
vcoubard	19:47192cb9def7	17	* Redistribution and use in source and binary forms, with or without
vcoubard	19:47192cb9def7	18	* modification, are permitted provided that the following conditions are met:
vcoubard	19:47192cb9def7	19	*
vcoubard	19:47192cb9def7	20	* * Redistributions of source code must retain the above copyright notice, this
vcoubard	19:47192cb9def7	21	* list of conditions and the following disclaimer.
vcoubard	19:47192cb9def7	22	*
vcoubard	19:47192cb9def7	23	* * Redistributions in binary form must reproduce the above copyright notice,
vcoubard	19:47192cb9def7	24	* this list of conditions and the following disclaimer in the documentation
vcoubard	19:47192cb9def7	25	* and/or other materials provided with the distribution.
vcoubard	19:47192cb9def7	26	*
vcoubard	19:47192cb9def7	27	* * Neither the name of Nordic Semiconductor ASA nor the names of its
vcoubard	19:47192cb9def7	28	* contributors may be used to endorse or promote products derived from
vcoubard	19:47192cb9def7	29	* this software without specific prior written permission.
vcoubard	19:47192cb9def7	30	*
vcoubard	19:47192cb9def7	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vcoubard	19:47192cb9def7	32	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vcoubard	19:47192cb9def7	33	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vcoubard	19:47192cb9def7	34	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vcoubard	19:47192cb9def7	35	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vcoubard	19:47192cb9def7	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vcoubard	19:47192cb9def7	37	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vcoubard	19:47192cb9def7	38	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vcoubard	19:47192cb9def7	39	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vcoubard	19:47192cb9def7	40	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vcoubard	19:47192cb9def7	41	*
vcoubard	19:47192cb9def7	42	*
vcoubard	19:47192cb9def7	43	*******************************************************************************************************/
vcoubard	19:47192cb9def7	44
vcoubard	19:47192cb9def7	45
vcoubard	19:47192cb9def7	46
vcoubard	19:47192cb9def7	47	/** @addtogroup Nordic Semiconductor
vcoubard	19:47192cb9def7	48	* @{
vcoubard	19:47192cb9def7	49	*/
vcoubard	19:47192cb9def7	50
vcoubard	19:47192cb9def7	51	/** @addtogroup nrf51
vcoubard	19:47192cb9def7	52	* @{
vcoubard	19:47192cb9def7	53	*/
vcoubard	1:ebc0e0ef0a11	54
vcoubard	1:ebc0e0ef0a11	55	#ifndef NRF51_H
vcoubard	1:ebc0e0ef0a11	56	#define NRF51_H
vcoubard	1:ebc0e0ef0a11	57
vcoubard	1:ebc0e0ef0a11	58	#ifdef __cplusplus
vcoubard	1:ebc0e0ef0a11	59	extern "C" {
vcoubard	1:ebc0e0ef0a11	60	#endif
vcoubard	1:ebc0e0ef0a11	61
vcoubard	1:ebc0e0ef0a11	62
vcoubard	1:ebc0e0ef0a11	63	/* ------------------------- Interrupt Number Definition ------------------------ */
vcoubard	1:ebc0e0ef0a11	64
vcoubard	1:ebc0e0ef0a11	65	typedef enum {
vcoubard	1:ebc0e0ef0a11	66	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
vcoubard	1:ebc0e0ef0a11	67	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
vcoubard	1:ebc0e0ef0a11	68	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
vcoubard	1:ebc0e0ef0a11	69	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
vcoubard	1:ebc0e0ef0a11	70	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
vcoubard	1:ebc0e0ef0a11	71	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
vcoubard	1:ebc0e0ef0a11	72	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
vcoubard	1:ebc0e0ef0a11	73	SysTick_IRQn = -1, /!< 15 System Tick Timer /
vcoubard	1:ebc0e0ef0a11	74	/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
vcoubard	1:ebc0e0ef0a11	75	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
vcoubard	1:ebc0e0ef0a11	76	RADIO_IRQn = 1, /!< 1 RADIO /
vcoubard	1:ebc0e0ef0a11	77	UART0_IRQn = 2, /!< 2 UART0 /
vcoubard	1:ebc0e0ef0a11	78	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
vcoubard	1:ebc0e0ef0a11	79	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
vcoubard	1:ebc0e0ef0a11	80	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
vcoubard	1:ebc0e0ef0a11	81	ADC_IRQn = 7, /!< 7 ADC /
vcoubard	1:ebc0e0ef0a11	82	TIMER0_IRQn = 8, /!< 8 TIMER0 /
vcoubard	1:ebc0e0ef0a11	83	TIMER1_IRQn = 9, /!< 9 TIMER1 /
vcoubard	1:ebc0e0ef0a11	84	TIMER2_IRQn = 10, /!< 10 TIMER2 /
vcoubard	1:ebc0e0ef0a11	85	RTC0_IRQn = 11, /!< 11 RTC0 /
vcoubard	1:ebc0e0ef0a11	86	TEMP_IRQn = 12, /!< 12 TEMP /
vcoubard	1:ebc0e0ef0a11	87	RNG_IRQn = 13, /!< 13 RNG /
vcoubard	1:ebc0e0ef0a11	88	ECB_IRQn = 14, /!< 14 ECB /
vcoubard	1:ebc0e0ef0a11	89	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
vcoubard	1:ebc0e0ef0a11	90	WDT_IRQn = 16, /!< 16 WDT /
vcoubard	1:ebc0e0ef0a11	91	RTC1_IRQn = 17, /!< 17 RTC1 /
vcoubard	1:ebc0e0ef0a11	92	QDEC_IRQn = 18, /!< 18 QDEC /
vcoubard	1:ebc0e0ef0a11	93	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
vcoubard	1:ebc0e0ef0a11	94	SWI0_IRQn = 20, /!< 20 SWI0 /
vcoubard	1:ebc0e0ef0a11	95	SWI1_IRQn = 21, /!< 21 SWI1 /
vcoubard	1:ebc0e0ef0a11	96	SWI2_IRQn = 22, /!< 22 SWI2 /
vcoubard	1:ebc0e0ef0a11	97	SWI3_IRQn = 23, /!< 23 SWI3 /
vcoubard	1:ebc0e0ef0a11	98	SWI4_IRQn = 24, /!< 24 SWI4 /
vcoubard	1:ebc0e0ef0a11	99	SWI5_IRQn = 25 /!< 25 SWI5 /
vcoubard	1:ebc0e0ef0a11	100	} IRQn_Type;
vcoubard	1:ebc0e0ef0a11	101
vcoubard	1:ebc0e0ef0a11	102
vcoubard	1:ebc0e0ef0a11	103	/** @addtogroup Configuration_of_CMSIS
vcoubard	1:ebc0e0ef0a11	104	* @{
vcoubard	1:ebc0e0ef0a11	105	*/
vcoubard	1:ebc0e0ef0a11	106
vcoubard	1:ebc0e0ef0a11	107
vcoubard	1:ebc0e0ef0a11	108	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	109	/* ================ Processor and Core Peripheral Section ================ */
vcoubard	1:ebc0e0ef0a11	110	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	111
vcoubard	1:ebc0e0ef0a11	112	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
vcoubard	1:ebc0e0ef0a11	113	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
vcoubard	1:ebc0e0ef0a11	114	#define __MPU_PRESENT 0 /!< MPU present or not /
vcoubard	1:ebc0e0ef0a11	115	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
vcoubard	1:ebc0e0ef0a11	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
vcoubard	1:ebc0e0ef0a11	117	/** @} / / End of group Configuration_of_CMSIS */
vcoubard	1:ebc0e0ef0a11	118
vcoubard	1:ebc0e0ef0a11	119	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
vcoubard	1:ebc0e0ef0a11	120	#include "system_nrf51.h" /!< nrf51 System /
vcoubard	1:ebc0e0ef0a11	121
vcoubard	1:ebc0e0ef0a11	122
vcoubard	1:ebc0e0ef0a11	123	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	124	/* ================ Device Specific Peripheral Section ================ */
vcoubard	1:ebc0e0ef0a11	125	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	126
vcoubard	1:ebc0e0ef0a11	127
vcoubard	1:ebc0e0ef0a11	128	/** @addtogroup Device_Peripheral_Registers
vcoubard	1:ebc0e0ef0a11	129	* @{
vcoubard	1:ebc0e0ef0a11	130	*/
vcoubard	1:ebc0e0ef0a11	131
vcoubard	1:ebc0e0ef0a11	132
vcoubard	1:ebc0e0ef0a11	133	/* ------------------- Start of section using anonymous unions ------------------ */
vcoubard	1:ebc0e0ef0a11	134	#if defined(__CC_ARM)
vcoubard	1:ebc0e0ef0a11	135	#pragma push
vcoubard	1:ebc0e0ef0a11	136	#pragma anon_unions
vcoubard	1:ebc0e0ef0a11	137	#elif defined(__ICCARM__)
vcoubard	1:ebc0e0ef0a11	138	#pragma language=extended
vcoubard	1:ebc0e0ef0a11	139	#elif defined(__GNUC__)
vcoubard	1:ebc0e0ef0a11	140	/* anonymous unions are enabled by default */
vcoubard	1:ebc0e0ef0a11	141	#elif defined(__TMS470__)
vcoubard	1:ebc0e0ef0a11	142	/* anonymous unions are enabled by default */
vcoubard	1:ebc0e0ef0a11	143	#elif defined(__TASKING__)
vcoubard	1:ebc0e0ef0a11	144	#pragma warning 586
vcoubard	1:ebc0e0ef0a11	145	#else
vcoubard	1:ebc0e0ef0a11	146	#warning Not supported compiler type
vcoubard	1:ebc0e0ef0a11	147	#endif
vcoubard	1:ebc0e0ef0a11	148
vcoubard	1:ebc0e0ef0a11	149
vcoubard	1:ebc0e0ef0a11	150	typedef struct {
vcoubard	1:ebc0e0ef0a11	151	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
vcoubard	1:ebc0e0ef0a11	152	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
vcoubard	1:ebc0e0ef0a11	153	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
vcoubard	1:ebc0e0ef0a11	154	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
vcoubard	1:ebc0e0ef0a11	155	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
vcoubard	1:ebc0e0ef0a11	156	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
vcoubard	1:ebc0e0ef0a11	157	} AMLI_RAMPRI_Type;
vcoubard	1:ebc0e0ef0a11	158
vcoubard	1:ebc0e0ef0a11	159	typedef struct {
vcoubard	1:ebc0e0ef0a11	160	__IO uint32_t SCK; /!< Pin select for SCK. /
vcoubard	1:ebc0e0ef0a11	161	__IO uint32_t MOSI; /!< Pin select for MOSI. /
vcoubard	1:ebc0e0ef0a11	162	__IO uint32_t MISO; /!< Pin select for MISO. /
vcoubard	1:ebc0e0ef0a11	163	} SPIM_PSEL_Type;
vcoubard	1:ebc0e0ef0a11	164
vcoubard	1:ebc0e0ef0a11	165	typedef struct {
vcoubard	1:ebc0e0ef0a11	166	__IO uint32_t PTR; /!< Data pointer. /
vcoubard	1:ebc0e0ef0a11	167	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
vcoubard	1:ebc0e0ef0a11	168	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
vcoubard	1:ebc0e0ef0a11	169	} SPIM_RXD_Type;
vcoubard	1:ebc0e0ef0a11	170
vcoubard	1:ebc0e0ef0a11	171	typedef struct {
vcoubard	1:ebc0e0ef0a11	172	__IO uint32_t PTR; /!< Data pointer. /
vcoubard	1:ebc0e0ef0a11	173	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
vcoubard	1:ebc0e0ef0a11	174	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
vcoubard	1:ebc0e0ef0a11	175	} SPIM_TXD_Type;
vcoubard	1:ebc0e0ef0a11	176
vcoubard	1:ebc0e0ef0a11	177	typedef struct {
vcoubard	1:ebc0e0ef0a11	178	__O uint32_t EN; /!< Enable channel group. /
vcoubard	1:ebc0e0ef0a11	179	__O uint32_t DIS; /!< Disable channel group. /
vcoubard	1:ebc0e0ef0a11	180	} PPI_TASKS_CHG_Type;
vcoubard	1:ebc0e0ef0a11	181
vcoubard	1:ebc0e0ef0a11	182	typedef struct {
vcoubard	1:ebc0e0ef0a11	183	__IO uint32_t EEP; /!< Channel event end-point. /
vcoubard	1:ebc0e0ef0a11	184	__IO uint32_t TEP; /!< Channel task end-point. /
vcoubard	1:ebc0e0ef0a11	185	} PPI_CH_Type;
vcoubard	1:ebc0e0ef0a11	186
vcoubard	1:ebc0e0ef0a11	187
vcoubard	1:ebc0e0ef0a11	188	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	189	/* ================ POWER ================ */
vcoubard	1:ebc0e0ef0a11	190	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	191
vcoubard	1:ebc0e0ef0a11	192
vcoubard	1:ebc0e0ef0a11	193	/**
vcoubard	1:ebc0e0ef0a11	194	* @brief Power Control. (POWER)
vcoubard	1:ebc0e0ef0a11	195	*/
vcoubard	1:ebc0e0ef0a11	196
vcoubard	1:ebc0e0ef0a11	197	typedef struct { /!< POWER Structure /
vcoubard	1:ebc0e0ef0a11	198	__I uint32_t RESERVED0[30];
vcoubard	1:ebc0e0ef0a11	199	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
vcoubard	1:ebc0e0ef0a11	200	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
vcoubard	1:ebc0e0ef0a11	201	__I uint32_t RESERVED1[34];
vcoubard	1:ebc0e0ef0a11	202	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
vcoubard	1:ebc0e0ef0a11	203	__I uint32_t RESERVED2[126];
vcoubard	1:ebc0e0ef0a11	204	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	205	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	206	__I uint32_t RESERVED3[61];
vcoubard	1:ebc0e0ef0a11	207	__IO uint32_t RESETREAS; /!< Reset reason. /
vcoubard	1:ebc0e0ef0a11	208	__I uint32_t RESERVED4[9];
vcoubard	1:ebc0e0ef0a11	209	__I uint32_t RAMSTATUS; /!< Ram status register. /
vcoubard	1:ebc0e0ef0a11	210	__I uint32_t RESERVED5[53];
vcoubard	1:ebc0e0ef0a11	211	__O uint32_t SYSTEMOFF; /!< System off register. /
vcoubard	1:ebc0e0ef0a11	212	__I uint32_t RESERVED6[3];
vcoubard	1:ebc0e0ef0a11	213	__IO uint32_t POFCON; /!< Power failure configuration. /
vcoubard	1:ebc0e0ef0a11	214	__I uint32_t RESERVED7[2];
vcoubard	1:ebc0e0ef0a11	215	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
vcoubard	1:ebc0e0ef0a11	216	register. */
vcoubard	1:ebc0e0ef0a11	217	__I uint32_t RESERVED8;
vcoubard	1:ebc0e0ef0a11	218	__IO uint32_t RAMON; /!< Ram on/off. /
vcoubard	1:ebc0e0ef0a11	219	__I uint32_t RESERVED9[7];
vcoubard	1:ebc0e0ef0a11	220	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
vcoubard	1:ebc0e0ef0a11	221	is a retained register. */
vcoubard	1:ebc0e0ef0a11	222	__I uint32_t RESERVED10[3];
vcoubard	1:ebc0e0ef0a11	223	__IO uint32_t RAMONB; /!< Ram on/off. /
vcoubard	1:ebc0e0ef0a11	224	__I uint32_t RESERVED11[8];
vcoubard	1:ebc0e0ef0a11	225	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
vcoubard	1:ebc0e0ef0a11	226	__I uint32_t RESERVED12[291];
vcoubard	1:ebc0e0ef0a11	227	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
vcoubard	1:ebc0e0ef0a11	228	} NRF_POWER_Type;
vcoubard	1:ebc0e0ef0a11	229
vcoubard	1:ebc0e0ef0a11	230
vcoubard	1:ebc0e0ef0a11	231	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	232	/* ================ CLOCK ================ */
vcoubard	1:ebc0e0ef0a11	233	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	234
vcoubard	1:ebc0e0ef0a11	235
vcoubard	1:ebc0e0ef0a11	236	/**
vcoubard	1:ebc0e0ef0a11	237	* @brief Clock control. (CLOCK)
vcoubard	1:ebc0e0ef0a11	238	*/
vcoubard	1:ebc0e0ef0a11	239
vcoubard	1:ebc0e0ef0a11	240	typedef struct { /!< CLOCK Structure /
vcoubard	1:ebc0e0ef0a11	241	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
vcoubard	1:ebc0e0ef0a11	242	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
vcoubard	1:ebc0e0ef0a11	243	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
vcoubard	1:ebc0e0ef0a11	244	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
vcoubard	1:ebc0e0ef0a11	245	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
vcoubard	1:ebc0e0ef0a11	246	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
vcoubard	1:ebc0e0ef0a11	247	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
vcoubard	1:ebc0e0ef0a11	248	__I uint32_t RESERVED0[57];
vcoubard	1:ebc0e0ef0a11	249	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
vcoubard	1:ebc0e0ef0a11	250	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
vcoubard	1:ebc0e0ef0a11	251	__I uint32_t RESERVED1;
vcoubard	1:ebc0e0ef0a11	252	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
vcoubard	1:ebc0e0ef0a11	253	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
vcoubard	1:ebc0e0ef0a11	254	__I uint32_t RESERVED2[124];
vcoubard	1:ebc0e0ef0a11	255	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	256	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	257	__I uint32_t RESERVED3[63];
vcoubard	1:ebc0e0ef0a11	258	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
vcoubard	1:ebc0e0ef0a11	259	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
vcoubard	1:ebc0e0ef0a11	260	__I uint32_t RESERVED4;
vcoubard	1:ebc0e0ef0a11	261	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
vcoubard	1:ebc0e0ef0a11	262	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
vcoubard	1:ebc0e0ef0a11	263	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
vcoubard	1:ebc0e0ef0a11	264	triggered. */
vcoubard	1:ebc0e0ef0a11	265	__I uint32_t RESERVED5[62];
vcoubard	1:ebc0e0ef0a11	266	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
vcoubard	1:ebc0e0ef0a11	267	__I uint32_t RESERVED6[7];
vcoubard	1:ebc0e0ef0a11	268	__IO uint32_t CTIV; /!< Calibration timer interval. /
vcoubard	1:ebc0e0ef0a11	269	__I uint32_t RESERVED7[5];
vcoubard	1:ebc0e0ef0a11	270	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
vcoubard	1:ebc0e0ef0a11	271	} NRF_CLOCK_Type;
vcoubard	1:ebc0e0ef0a11	272
vcoubard	1:ebc0e0ef0a11	273
vcoubard	1:ebc0e0ef0a11	274	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	275	/* ================ MPU ================ */
vcoubard	1:ebc0e0ef0a11	276	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	277
vcoubard	1:ebc0e0ef0a11	278
vcoubard	1:ebc0e0ef0a11	279	/**
vcoubard	1:ebc0e0ef0a11	280	* @brief Memory Protection Unit. (MPU)
vcoubard	1:ebc0e0ef0a11	281	*/
vcoubard	1:ebc0e0ef0a11	282
vcoubard	1:ebc0e0ef0a11	283	typedef struct { /!< MPU Structure /
vcoubard	1:ebc0e0ef0a11	284	__I uint32_t RESERVED0[330];
vcoubard	1:ebc0e0ef0a11	285	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
vcoubard	1:ebc0e0ef0a11	286	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
vcoubard	1:ebc0e0ef0a11	287	__I uint32_t RESERVED1[52];
vcoubard	1:ebc0e0ef0a11	288	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
vcoubard	1:ebc0e0ef0a11	289	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
vcoubard	1:ebc0e0ef0a11	290	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
vcoubard	1:ebc0e0ef0a11	291	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
vcoubard	1:ebc0e0ef0a11	292	} NRF_MPU_Type;
vcoubard	1:ebc0e0ef0a11	293
vcoubard	1:ebc0e0ef0a11	294
vcoubard	1:ebc0e0ef0a11	295	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	296	/* ================ AMLI ================ */
vcoubard	1:ebc0e0ef0a11	297	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	298
vcoubard	1:ebc0e0ef0a11	299
vcoubard	1:ebc0e0ef0a11	300	/**
vcoubard	1:ebc0e0ef0a11	301	* @brief AHB Multi-Layer Interface. (AMLI)
vcoubard	1:ebc0e0ef0a11	302	*/
vcoubard	1:ebc0e0ef0a11	303
vcoubard	1:ebc0e0ef0a11	304	typedef struct { /!< AMLI Structure /
vcoubard	1:ebc0e0ef0a11	305	__I uint32_t RESERVED0[896];
vcoubard	1:ebc0e0ef0a11	306	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
vcoubard	1:ebc0e0ef0a11	307	} NRF_AMLI_Type;
vcoubard	1:ebc0e0ef0a11	308
vcoubard	1:ebc0e0ef0a11	309
vcoubard	1:ebc0e0ef0a11	310	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	311	/* ================ RADIO ================ */
vcoubard	1:ebc0e0ef0a11	312	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	313
vcoubard	1:ebc0e0ef0a11	314
vcoubard	1:ebc0e0ef0a11	315	/**
vcoubard	1:ebc0e0ef0a11	316	* @brief The radio. (RADIO)
vcoubard	1:ebc0e0ef0a11	317	*/
vcoubard	1:ebc0e0ef0a11	318
vcoubard	1:ebc0e0ef0a11	319	typedef struct { /!< RADIO Structure /
vcoubard	1:ebc0e0ef0a11	320	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
vcoubard	1:ebc0e0ef0a11	321	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
vcoubard	1:ebc0e0ef0a11	322	__O uint32_t TASKS_START; /!< Start radio. /
vcoubard	1:ebc0e0ef0a11	323	__O uint32_t TASKS_STOP; /!< Stop radio. /
vcoubard	1:ebc0e0ef0a11	324	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
vcoubard	1:ebc0e0ef0a11	325	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
vcoubard	1:ebc0e0ef0a11	326	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
vcoubard	1:ebc0e0ef0a11	327	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
vcoubard	1:ebc0e0ef0a11	328	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
vcoubard	1:ebc0e0ef0a11	329	__I uint32_t RESERVED0[55];
vcoubard	1:ebc0e0ef0a11	330	__IO uint32_t EVENTS_READY; /!< Ready event. /
vcoubard	1:ebc0e0ef0a11	331	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
vcoubard	1:ebc0e0ef0a11	332	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
vcoubard	1:ebc0e0ef0a11	333	__IO uint32_t EVENTS_END; /!< End event. /
vcoubard	1:ebc0e0ef0a11	334	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
vcoubard	1:ebc0e0ef0a11	335	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
vcoubard	1:ebc0e0ef0a11	336	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
vcoubard	1:ebc0e0ef0a11	337	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
vcoubard	1:ebc0e0ef0a11	338	sample is ready for readout at the RSSISAMPLE register. */
vcoubard	1:ebc0e0ef0a11	339	__I uint32_t RESERVED1[2];
vcoubard	1:ebc0e0ef0a11	340	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BCC register. /
vcoubard	1:ebc0e0ef0a11	341	__I uint32_t RESERVED2[53];
vcoubard	1:ebc0e0ef0a11	342	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
vcoubard	1:ebc0e0ef0a11	343	__I uint32_t RESERVED3[64];
vcoubard	1:ebc0e0ef0a11	344	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	345	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	346	__I uint32_t RESERVED4[61];
vcoubard	1:ebc0e0ef0a11	347	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
vcoubard	19:47192cb9def7	348	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	349	__I uint32_t RXMATCH; /!< Received address. /
vcoubard	1:ebc0e0ef0a11	350	__I uint32_t RXCRC; /!< Received CRC. /
vcoubard	1:ebc0e0ef0a11	351	__I uint32_t DAI; /!< Device address match index. /
vcoubard	19:47192cb9def7	352	__I uint32_t RESERVED6[60];
vcoubard	1:ebc0e0ef0a11	353	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
vcoubard	1:ebc0e0ef0a11	354	__IO uint32_t FREQUENCY; /!< Frequency. /
vcoubard	1:ebc0e0ef0a11	355	__IO uint32_t TXPOWER; /!< Output power. /
vcoubard	1:ebc0e0ef0a11	356	__IO uint32_t MODE; /!< Data rate and modulation. /
vcoubard	1:ebc0e0ef0a11	357	__IO uint32_t PCNF0; /!< Packet configuration 0. /
vcoubard	1:ebc0e0ef0a11	358	__IO uint32_t PCNF1; /!< Packet configuration 1. /
vcoubard	1:ebc0e0ef0a11	359	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
vcoubard	1:ebc0e0ef0a11	360	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
vcoubard	1:ebc0e0ef0a11	361	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
vcoubard	1:ebc0e0ef0a11	362	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
vcoubard	1:ebc0e0ef0a11	363	__IO uint32_t TXADDRESS; /!< Transmit address select. /
vcoubard	1:ebc0e0ef0a11	364	__IO uint32_t RXADDRESSES; /!< Receive address select. /
vcoubard	1:ebc0e0ef0a11	365	__IO uint32_t CRCCNF; /!< CRC configuration. /
vcoubard	1:ebc0e0ef0a11	366	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
vcoubard	1:ebc0e0ef0a11	367	__IO uint32_t CRCINIT; /!< CRC initial value. /
vcoubard	1:ebc0e0ef0a11	368	__IO uint32_t TEST; /!< Test features enable register. /
vcoubard	1:ebc0e0ef0a11	369	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
vcoubard	1:ebc0e0ef0a11	370	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
vcoubard	19:47192cb9def7	371	__I uint32_t RESERVED7;
vcoubard	1:ebc0e0ef0a11	372	__I uint32_t STATE; /!< Current radio state. /
vcoubard	1:ebc0e0ef0a11	373	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
vcoubard	19:47192cb9def7	374	__I uint32_t RESERVED8[2];
vcoubard	1:ebc0e0ef0a11	375	__IO uint32_t BCC; /!< Bit counter compare. /
vcoubard	19:47192cb9def7	376	__I uint32_t RESERVED9[39];
vcoubard	1:ebc0e0ef0a11	377	__IO uint32_t DAB[8]; /!< Device address base segment. /
vcoubard	1:ebc0e0ef0a11	378	__IO uint32_t DAP[8]; /!< Device address prefix. /
vcoubard	1:ebc0e0ef0a11	379	__IO uint32_t DACNF; /!< Device address match configuration. /
vcoubard	19:47192cb9def7	380	__I uint32_t RESERVED10[56];
vcoubard	1:ebc0e0ef0a11	381	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
vcoubard	1:ebc0e0ef0a11	382	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
vcoubard	1:ebc0e0ef0a11	383	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
vcoubard	1:ebc0e0ef0a11	384	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
vcoubard	1:ebc0e0ef0a11	385	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
vcoubard	19:47192cb9def7	386	__I uint32_t RESERVED11[561];
vcoubard	1:ebc0e0ef0a11	387	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	388	} NRF_RADIO_Type;
vcoubard	1:ebc0e0ef0a11	389
vcoubard	1:ebc0e0ef0a11	390
vcoubard	1:ebc0e0ef0a11	391	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	392	/* ================ UART ================ */
vcoubard	1:ebc0e0ef0a11	393	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	394
vcoubard	1:ebc0e0ef0a11	395
vcoubard	1:ebc0e0ef0a11	396	/**
vcoubard	1:ebc0e0ef0a11	397	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
vcoubard	1:ebc0e0ef0a11	398	*/
vcoubard	1:ebc0e0ef0a11	399
vcoubard	1:ebc0e0ef0a11	400	typedef struct { /!< UART Structure /
vcoubard	1:ebc0e0ef0a11	401	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
vcoubard	1:ebc0e0ef0a11	402	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
vcoubard	1:ebc0e0ef0a11	403	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
vcoubard	1:ebc0e0ef0a11	404	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
vcoubard	1:ebc0e0ef0a11	405	__I uint32_t RESERVED0[3];
vcoubard	1:ebc0e0ef0a11	406	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
vcoubard	1:ebc0e0ef0a11	407	__I uint32_t RESERVED1[56];
vcoubard	1:ebc0e0ef0a11	408	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
vcoubard	1:ebc0e0ef0a11	409	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
vcoubard	1:ebc0e0ef0a11	410	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
vcoubard	1:ebc0e0ef0a11	411	__I uint32_t RESERVED2[4];
vcoubard	1:ebc0e0ef0a11	412	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
vcoubard	1:ebc0e0ef0a11	413	__I uint32_t RESERVED3;
vcoubard	1:ebc0e0ef0a11	414	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
vcoubard	1:ebc0e0ef0a11	415	__I uint32_t RESERVED4[7];
vcoubard	1:ebc0e0ef0a11	416	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
vcoubard	19:47192cb9def7	417	__I uint32_t RESERVED5[46];
vcoubard	19:47192cb9def7	418	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
vcoubard	19:47192cb9def7	419	__I uint32_t RESERVED6[64];
vcoubard	1:ebc0e0ef0a11	420	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	421	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	19:47192cb9def7	422	__I uint32_t RESERVED7[93];
vcoubard	1:ebc0e0ef0a11	423	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
vcoubard	19:47192cb9def7	424	__I uint32_t RESERVED8[31];
vcoubard	1:ebc0e0ef0a11	425	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
vcoubard	19:47192cb9def7	426	__I uint32_t RESERVED9;
vcoubard	1:ebc0e0ef0a11	427	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
vcoubard	1:ebc0e0ef0a11	428	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
vcoubard	1:ebc0e0ef0a11	429	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
vcoubard	1:ebc0e0ef0a11	430	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
vcoubard	1:ebc0e0ef0a11	431	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
vcoubard	1:ebc0e0ef0a11	432	Once read the character is consumed. If read when no character
vcoubard	1:ebc0e0ef0a11	433	available, the UART will stop working. */
vcoubard	1:ebc0e0ef0a11	434	__O uint32_t TXD; /!< TXD register. /
vcoubard	19:47192cb9def7	435	__I uint32_t RESERVED10;
vcoubard	1:ebc0e0ef0a11	436	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
vcoubard	19:47192cb9def7	437	__I uint32_t RESERVED11[17];
vcoubard	1:ebc0e0ef0a11	438	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
vcoubard	19:47192cb9def7	439	__I uint32_t RESERVED12[675];
vcoubard	1:ebc0e0ef0a11	440	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	441	} NRF_UART_Type;
vcoubard	1:ebc0e0ef0a11	442
vcoubard	1:ebc0e0ef0a11	443
vcoubard	1:ebc0e0ef0a11	444	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	445	/* ================ SPI ================ */
vcoubard	1:ebc0e0ef0a11	446	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	447
vcoubard	1:ebc0e0ef0a11	448
vcoubard	1:ebc0e0ef0a11	449	/**
vcoubard	1:ebc0e0ef0a11	450	* @brief SPI master 0. (SPI)
vcoubard	1:ebc0e0ef0a11	451	*/
vcoubard	1:ebc0e0ef0a11	452
vcoubard	1:ebc0e0ef0a11	453	typedef struct { /!< SPI Structure /
vcoubard	1:ebc0e0ef0a11	454	__I uint32_t RESERVED0[66];
vcoubard	1:ebc0e0ef0a11	455	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
vcoubard	1:ebc0e0ef0a11	456	__I uint32_t RESERVED1[126];
vcoubard	1:ebc0e0ef0a11	457	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	458	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	459	__I uint32_t RESERVED2[125];
vcoubard	1:ebc0e0ef0a11	460	__IO uint32_t ENABLE; /!< Enable SPI. /
vcoubard	1:ebc0e0ef0a11	461	__I uint32_t RESERVED3;
vcoubard	1:ebc0e0ef0a11	462	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
vcoubard	1:ebc0e0ef0a11	463	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
vcoubard	1:ebc0e0ef0a11	464	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
vcoubard	1:ebc0e0ef0a11	465	__I uint32_t RESERVED4;
vcoubard	1:ebc0e0ef0a11	466	__I uint32_t RXD; /!< RX data. /
vcoubard	1:ebc0e0ef0a11	467	__IO uint32_t TXD; /!< TX data. /
vcoubard	1:ebc0e0ef0a11	468	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	469	__IO uint32_t FREQUENCY; /!< SPI frequency /
vcoubard	1:ebc0e0ef0a11	470	__I uint32_t RESERVED6[11];
vcoubard	1:ebc0e0ef0a11	471	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	472	__I uint32_t RESERVED7[681];
vcoubard	1:ebc0e0ef0a11	473	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	474	} NRF_SPI_Type;
vcoubard	1:ebc0e0ef0a11	475
vcoubard	1:ebc0e0ef0a11	476
vcoubard	1:ebc0e0ef0a11	477	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	478	/* ================ TWI ================ */
vcoubard	1:ebc0e0ef0a11	479	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	480
vcoubard	1:ebc0e0ef0a11	481
vcoubard	1:ebc0e0ef0a11	482	/**
vcoubard	1:ebc0e0ef0a11	483	* @brief Two-wire interface master 0. (TWI)
vcoubard	1:ebc0e0ef0a11	484	*/
vcoubard	1:ebc0e0ef0a11	485
vcoubard	1:ebc0e0ef0a11	486	typedef struct { /!< TWI Structure /
vcoubard	1:ebc0e0ef0a11	487	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
vcoubard	1:ebc0e0ef0a11	488	__I uint32_t RESERVED0;
vcoubard	1:ebc0e0ef0a11	489	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
vcoubard	1:ebc0e0ef0a11	490	__I uint32_t RESERVED1[2];
vcoubard	1:ebc0e0ef0a11	491	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
vcoubard	1:ebc0e0ef0a11	492	__I uint32_t RESERVED2;
vcoubard	1:ebc0e0ef0a11	493	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
vcoubard	1:ebc0e0ef0a11	494	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
vcoubard	1:ebc0e0ef0a11	495	__I uint32_t RESERVED3[56];
vcoubard	1:ebc0e0ef0a11	496	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
vcoubard	1:ebc0e0ef0a11	497	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
vcoubard	1:ebc0e0ef0a11	498	__I uint32_t RESERVED4[4];
vcoubard	1:ebc0e0ef0a11	499	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
vcoubard	1:ebc0e0ef0a11	500	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	501	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
vcoubard	1:ebc0e0ef0a11	502	__I uint32_t RESERVED6[4];
vcoubard	1:ebc0e0ef0a11	503	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
vcoubard	1:ebc0e0ef0a11	504	__I uint32_t RESERVED7[3];
vcoubard	1:ebc0e0ef0a11	505	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
vcoubard	1:ebc0e0ef0a11	506	__I uint32_t RESERVED8[45];
vcoubard	1:ebc0e0ef0a11	507	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
vcoubard	1:ebc0e0ef0a11	508	__I uint32_t RESERVED9[64];
vcoubard	1:ebc0e0ef0a11	509	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	510	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	511	__I uint32_t RESERVED10[110];
vcoubard	1:ebc0e0ef0a11	512	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
vcoubard	1:ebc0e0ef0a11	513	__I uint32_t RESERVED11[14];
vcoubard	1:ebc0e0ef0a11	514	__IO uint32_t ENABLE; /!< Enable two-wire master. /
vcoubard	1:ebc0e0ef0a11	515	__I uint32_t RESERVED12;
vcoubard	1:ebc0e0ef0a11	516	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
vcoubard	1:ebc0e0ef0a11	517	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
vcoubard	1:ebc0e0ef0a11	518	__I uint32_t RESERVED13[2];
vcoubard	1:ebc0e0ef0a11	519	__I uint32_t RXD; /!< RX data register. /
vcoubard	1:ebc0e0ef0a11	520	__IO uint32_t TXD; /!< TX data register. /
vcoubard	1:ebc0e0ef0a11	521	__I uint32_t RESERVED14;
vcoubard	1:ebc0e0ef0a11	522	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
vcoubard	1:ebc0e0ef0a11	523	__I uint32_t RESERVED15[24];
vcoubard	1:ebc0e0ef0a11	524	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
vcoubard	1:ebc0e0ef0a11	525	__I uint32_t RESERVED16[668];
vcoubard	1:ebc0e0ef0a11	526	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	527	} NRF_TWI_Type;
vcoubard	1:ebc0e0ef0a11	528
vcoubard	1:ebc0e0ef0a11	529
vcoubard	1:ebc0e0ef0a11	530	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	531	/* ================ SPIS ================ */
vcoubard	1:ebc0e0ef0a11	532	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	533
vcoubard	1:ebc0e0ef0a11	534
vcoubard	1:ebc0e0ef0a11	535	/**
vcoubard	1:ebc0e0ef0a11	536	* @brief SPI slave 1. (SPIS)
vcoubard	1:ebc0e0ef0a11	537	*/
vcoubard	1:ebc0e0ef0a11	538
vcoubard	1:ebc0e0ef0a11	539	typedef struct { /!< SPIS Structure /
vcoubard	1:ebc0e0ef0a11	540	__I uint32_t RESERVED0[9];
vcoubard	1:ebc0e0ef0a11	541	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
vcoubard	1:ebc0e0ef0a11	542	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
vcoubard	1:ebc0e0ef0a11	543	__I uint32_t RESERVED1[54];
vcoubard	1:ebc0e0ef0a11	544	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
vcoubard	1:ebc0e0ef0a11	545	__I uint32_t RESERVED2[8];
vcoubard	1:ebc0e0ef0a11	546	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
vcoubard	1:ebc0e0ef0a11	547	__I uint32_t RESERVED3[53];
vcoubard	1:ebc0e0ef0a11	548	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
vcoubard	1:ebc0e0ef0a11	549	__I uint32_t RESERVED4[64];
vcoubard	1:ebc0e0ef0a11	550	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	551	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	552	__I uint32_t RESERVED5[61];
vcoubard	1:ebc0e0ef0a11	553	__I uint32_t SEMSTAT; /!< Semaphore status. /
vcoubard	1:ebc0e0ef0a11	554	__I uint32_t RESERVED6[15];
vcoubard	1:ebc0e0ef0a11	555	__IO uint32_t STATUS; /!< Status from last transaction. /
vcoubard	1:ebc0e0ef0a11	556	__I uint32_t RESERVED7[47];
vcoubard	1:ebc0e0ef0a11	557	__IO uint32_t ENABLE; /!< Enable SPIS. /
vcoubard	1:ebc0e0ef0a11	558	__I uint32_t RESERVED8;
vcoubard	1:ebc0e0ef0a11	559	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
vcoubard	1:ebc0e0ef0a11	560	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
vcoubard	1:ebc0e0ef0a11	561	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
vcoubard	1:ebc0e0ef0a11	562	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
vcoubard	1:ebc0e0ef0a11	563	__I uint32_t RESERVED9[7];
vcoubard	1:ebc0e0ef0a11	564	__IO uint32_t RXDPTR; /!< RX data pointer. /
vcoubard	1:ebc0e0ef0a11	565	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
vcoubard	1:ebc0e0ef0a11	566	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
vcoubard	1:ebc0e0ef0a11	567	__I uint32_t RESERVED10;
vcoubard	1:ebc0e0ef0a11	568	__IO uint32_t TXDPTR; /!< TX data pointer. /
vcoubard	1:ebc0e0ef0a11	569	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
vcoubard	1:ebc0e0ef0a11	570	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
vcoubard	1:ebc0e0ef0a11	571	__I uint32_t RESERVED11;
vcoubard	1:ebc0e0ef0a11	572	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	573	__I uint32_t RESERVED12;
vcoubard	1:ebc0e0ef0a11	574	__IO uint32_t DEF; /!< Default character. /
vcoubard	1:ebc0e0ef0a11	575	__I uint32_t RESERVED13[24];
vcoubard	1:ebc0e0ef0a11	576	__IO uint32_t ORC; /!< Over-read character. /
vcoubard	1:ebc0e0ef0a11	577	__I uint32_t RESERVED14[654];
vcoubard	1:ebc0e0ef0a11	578	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	579	} NRF_SPIS_Type;
vcoubard	1:ebc0e0ef0a11	580
vcoubard	1:ebc0e0ef0a11	581
vcoubard	1:ebc0e0ef0a11	582	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	583	/* ================ SPIM ================ */
vcoubard	1:ebc0e0ef0a11	584	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	585
vcoubard	1:ebc0e0ef0a11	586
vcoubard	1:ebc0e0ef0a11	587	/**
vcoubard	1:ebc0e0ef0a11	588	* @brief SPI master with easyDMA 1. (SPIM)
vcoubard	1:ebc0e0ef0a11	589	*/
vcoubard	1:ebc0e0ef0a11	590
vcoubard	1:ebc0e0ef0a11	591	typedef struct { /!< SPIM Structure /
vcoubard	1:ebc0e0ef0a11	592	__I uint32_t RESERVED0[4];
vcoubard	1:ebc0e0ef0a11	593	__O uint32_t TASKS_START; /!< Start SPI transaction. /
vcoubard	1:ebc0e0ef0a11	594	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
vcoubard	1:ebc0e0ef0a11	595	__I uint32_t RESERVED1;
vcoubard	1:ebc0e0ef0a11	596	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
vcoubard	1:ebc0e0ef0a11	597	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
vcoubard	1:ebc0e0ef0a11	598	__I uint32_t RESERVED2[56];
vcoubard	1:ebc0e0ef0a11	599	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
vcoubard	1:ebc0e0ef0a11	600	__I uint32_t RESERVED3[2];
vcoubard	1:ebc0e0ef0a11	601	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
vcoubard	19:47192cb9def7	602	__I uint32_t RESERVED4[3];
vcoubard	1:ebc0e0ef0a11	603	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
vcoubard	19:47192cb9def7	604	__I uint32_t RESERVED5[10];
vcoubard	1:ebc0e0ef0a11	605	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
vcoubard	19:47192cb9def7	606	__I uint32_t RESERVED6[109];
vcoubard	1:ebc0e0ef0a11	607	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	608	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	19:47192cb9def7	609	__I uint32_t RESERVED7[125];
vcoubard	1:ebc0e0ef0a11	610	__IO uint32_t ENABLE; /!< Enable SPIM. /
vcoubard	19:47192cb9def7	611	__I uint32_t RESERVED8;
vcoubard	1:ebc0e0ef0a11	612	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
vcoubard	19:47192cb9def7	613	__I uint32_t RESERVED9[4];
vcoubard	1:ebc0e0ef0a11	614	__IO uint32_t FREQUENCY; /!< SPI frequency. /
vcoubard	19:47192cb9def7	615	__I uint32_t RESERVED10[3];
vcoubard	1:ebc0e0ef0a11	616	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
vcoubard	19:47192cb9def7	617	__I uint32_t RESERVED11;
vcoubard	1:ebc0e0ef0a11	618	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
vcoubard	19:47192cb9def7	619	__I uint32_t RESERVED12;
vcoubard	1:ebc0e0ef0a11	620	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	19:47192cb9def7	621	__I uint32_t RESERVED13[26];
vcoubard	1:ebc0e0ef0a11	622	__IO uint32_t ORC; /!< Over-read character. /
vcoubard	19:47192cb9def7	623	__I uint32_t RESERVED14[654];
vcoubard	1:ebc0e0ef0a11	624	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	625	} NRF_SPIM_Type;
vcoubard	1:ebc0e0ef0a11	626
vcoubard	1:ebc0e0ef0a11	627
vcoubard	1:ebc0e0ef0a11	628	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	629	/* ================ GPIOTE ================ */
vcoubard	1:ebc0e0ef0a11	630	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	631
vcoubard	1:ebc0e0ef0a11	632
vcoubard	1:ebc0e0ef0a11	633	/**
vcoubard	1:ebc0e0ef0a11	634	* @brief GPIO tasks and events. (GPIOTE)
vcoubard	1:ebc0e0ef0a11	635	*/
vcoubard	1:ebc0e0ef0a11	636
vcoubard	1:ebc0e0ef0a11	637	typedef struct { /!< GPIOTE Structure /
vcoubard	1:ebc0e0ef0a11	638	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
vcoubard	1:ebc0e0ef0a11	639	__I uint32_t RESERVED0[60];
vcoubard	1:ebc0e0ef0a11	640	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
vcoubard	1:ebc0e0ef0a11	641	__I uint32_t RESERVED1[27];
vcoubard	1:ebc0e0ef0a11	642	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
vcoubard	1:ebc0e0ef0a11	643	__I uint32_t RESERVED2[97];
vcoubard	1:ebc0e0ef0a11	644	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	645	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	646	__I uint32_t RESERVED3[129];
vcoubard	1:ebc0e0ef0a11	647	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
vcoubard	1:ebc0e0ef0a11	648	__I uint32_t RESERVED4[695];
vcoubard	1:ebc0e0ef0a11	649	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	650	} NRF_GPIOTE_Type;
vcoubard	1:ebc0e0ef0a11	651
vcoubard	1:ebc0e0ef0a11	652
vcoubard	1:ebc0e0ef0a11	653	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	654	/* ================ ADC ================ */
vcoubard	1:ebc0e0ef0a11	655	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	656
vcoubard	1:ebc0e0ef0a11	657
vcoubard	1:ebc0e0ef0a11	658	/**
vcoubard	1:ebc0e0ef0a11	659	* @brief Analog to digital converter. (ADC)
vcoubard	1:ebc0e0ef0a11	660	*/
vcoubard	1:ebc0e0ef0a11	661
vcoubard	1:ebc0e0ef0a11	662	typedef struct { /!< ADC Structure /
vcoubard	1:ebc0e0ef0a11	663	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
vcoubard	1:ebc0e0ef0a11	664	__O uint32_t TASKS_STOP; /!< Stop ADC. /
vcoubard	1:ebc0e0ef0a11	665	__I uint32_t RESERVED0[62];
vcoubard	1:ebc0e0ef0a11	666	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
vcoubard	1:ebc0e0ef0a11	667	__I uint32_t RESERVED1[128];
vcoubard	1:ebc0e0ef0a11	668	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	669	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	670	__I uint32_t RESERVED2[61];
vcoubard	1:ebc0e0ef0a11	671	__I uint32_t BUSY; /!< ADC busy register. /
vcoubard	1:ebc0e0ef0a11	672	__I uint32_t RESERVED3[63];
vcoubard	1:ebc0e0ef0a11	673	__IO uint32_t ENABLE; /!< ADC enable. /
vcoubard	1:ebc0e0ef0a11	674	__IO uint32_t CONFIG; /!< ADC configuration register. /
vcoubard	1:ebc0e0ef0a11	675	__I uint32_t RESULT; /!< Result of ADC conversion. /
vcoubard	1:ebc0e0ef0a11	676	__I uint32_t RESERVED4[700];
vcoubard	1:ebc0e0ef0a11	677	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	678	} NRF_ADC_Type;
vcoubard	1:ebc0e0ef0a11	679
vcoubard	1:ebc0e0ef0a11	680
vcoubard	1:ebc0e0ef0a11	681	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	682	/* ================ TIMER ================ */
vcoubard	1:ebc0e0ef0a11	683	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	684
vcoubard	1:ebc0e0ef0a11	685
vcoubard	1:ebc0e0ef0a11	686	/**
vcoubard	1:ebc0e0ef0a11	687	* @brief Timer 0. (TIMER)
vcoubard	1:ebc0e0ef0a11	688	*/
vcoubard	1:ebc0e0ef0a11	689
vcoubard	1:ebc0e0ef0a11	690	typedef struct { /!< TIMER Structure /
vcoubard	1:ebc0e0ef0a11	691	__O uint32_t TASKS_START; /!< Start Timer. /
vcoubard	1:ebc0e0ef0a11	692	__O uint32_t TASKS_STOP; /!< Stop Timer. /
vcoubard	1:ebc0e0ef0a11	693	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
vcoubard	1:ebc0e0ef0a11	694	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
vcoubard	1:ebc0e0ef0a11	695	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
vcoubard	1:ebc0e0ef0a11	696	__I uint32_t RESERVED0[11];
vcoubard	1:ebc0e0ef0a11	697	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
vcoubard	1:ebc0e0ef0a11	698	__I uint32_t RESERVED1[60];
vcoubard	1:ebc0e0ef0a11	699	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
vcoubard	1:ebc0e0ef0a11	700	__I uint32_t RESERVED2[44];
vcoubard	1:ebc0e0ef0a11	701	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
vcoubard	1:ebc0e0ef0a11	702	__I uint32_t RESERVED3[64];
vcoubard	1:ebc0e0ef0a11	703	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	704	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	705	__I uint32_t RESERVED4[126];
vcoubard	1:ebc0e0ef0a11	706	__IO uint32_t MODE; /!< Timer Mode selection. /
vcoubard	1:ebc0e0ef0a11	707	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
vcoubard	1:ebc0e0ef0a11	708	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	709	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
vcoubard	1:ebc0e0ef0a11	710	clock frequency is divided by 2^SCALE. */
vcoubard	1:ebc0e0ef0a11	711	__I uint32_t RESERVED6[11];
vcoubard	1:ebc0e0ef0a11	712	__IO uint32_t CC[4]; /!< Capture/compare registers. /
vcoubard	1:ebc0e0ef0a11	713	__I uint32_t RESERVED7[683];
vcoubard	1:ebc0e0ef0a11	714	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	715	} NRF_TIMER_Type;
vcoubard	1:ebc0e0ef0a11	716
vcoubard	1:ebc0e0ef0a11	717
vcoubard	1:ebc0e0ef0a11	718	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	719	/* ================ RTC ================ */
vcoubard	1:ebc0e0ef0a11	720	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	721
vcoubard	1:ebc0e0ef0a11	722
vcoubard	1:ebc0e0ef0a11	723	/**
vcoubard	1:ebc0e0ef0a11	724	* @brief Real time counter 0. (RTC)
vcoubard	1:ebc0e0ef0a11	725	*/
vcoubard	1:ebc0e0ef0a11	726
vcoubard	1:ebc0e0ef0a11	727	typedef struct { /!< RTC Structure /
vcoubard	1:ebc0e0ef0a11	728	__O uint32_t TASKS_START; /!< Start RTC Counter. /
vcoubard	1:ebc0e0ef0a11	729	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
vcoubard	1:ebc0e0ef0a11	730	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
vcoubard	1:ebc0e0ef0a11	731	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
vcoubard	1:ebc0e0ef0a11	732	__I uint32_t RESERVED0[60];
vcoubard	1:ebc0e0ef0a11	733	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
vcoubard	1:ebc0e0ef0a11	734	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
vcoubard	1:ebc0e0ef0a11	735	__I uint32_t RESERVED1[14];
vcoubard	1:ebc0e0ef0a11	736	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
vcoubard	1:ebc0e0ef0a11	737	__I uint32_t RESERVED2[109];
vcoubard	1:ebc0e0ef0a11	738	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	739	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	740	__I uint32_t RESERVED3[13];
vcoubard	1:ebc0e0ef0a11	741	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
vcoubard	1:ebc0e0ef0a11	742	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
vcoubard	1:ebc0e0ef0a11	743	the value of EVTEN. */
vcoubard	1:ebc0e0ef0a11	744	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
vcoubard	1:ebc0e0ef0a11	745	gives the value of EVTEN. */
vcoubard	1:ebc0e0ef0a11	746	__I uint32_t RESERVED4[110];
vcoubard	1:ebc0e0ef0a11	747	__I uint32_t COUNTER; /!< Current COUNTER value. /
vcoubard	1:ebc0e0ef0a11	748	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
vcoubard	1:ebc0e0ef0a11	749	Must be written when RTC is STOPed. */
vcoubard	1:ebc0e0ef0a11	750	__I uint32_t RESERVED5[13];
vcoubard	1:ebc0e0ef0a11	751	__IO uint32_t CC[4]; /!< Capture/compare registers. /
vcoubard	1:ebc0e0ef0a11	752	__I uint32_t RESERVED6[683];
vcoubard	1:ebc0e0ef0a11	753	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	754	} NRF_RTC_Type;
vcoubard	1:ebc0e0ef0a11	755
vcoubard	1:ebc0e0ef0a11	756
vcoubard	1:ebc0e0ef0a11	757	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	758	/* ================ TEMP ================ */
vcoubard	1:ebc0e0ef0a11	759	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	760
vcoubard	1:ebc0e0ef0a11	761
vcoubard	1:ebc0e0ef0a11	762	/**
vcoubard	1:ebc0e0ef0a11	763	* @brief Temperature Sensor. (TEMP)
vcoubard	1:ebc0e0ef0a11	764	*/
vcoubard	1:ebc0e0ef0a11	765
vcoubard	1:ebc0e0ef0a11	766	typedef struct { /!< TEMP Structure /
vcoubard	1:ebc0e0ef0a11	767	__O uint32_t TASKS_START; /!< Start temperature measurement. /
vcoubard	1:ebc0e0ef0a11	768	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
vcoubard	1:ebc0e0ef0a11	769	__I uint32_t RESERVED0[62];
vcoubard	1:ebc0e0ef0a11	770	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
vcoubard	1:ebc0e0ef0a11	771	__I uint32_t RESERVED1[128];
vcoubard	1:ebc0e0ef0a11	772	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	773	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	774	__I uint32_t RESERVED2[127];
vcoubard	1:ebc0e0ef0a11	775	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
vcoubard	1:ebc0e0ef0a11	776	__I uint32_t RESERVED3[700];
vcoubard	1:ebc0e0ef0a11	777	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	778	} NRF_TEMP_Type;
vcoubard	1:ebc0e0ef0a11	779
vcoubard	1:ebc0e0ef0a11	780
vcoubard	1:ebc0e0ef0a11	781	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	782	/* ================ RNG ================ */
vcoubard	1:ebc0e0ef0a11	783	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	784
vcoubard	1:ebc0e0ef0a11	785
vcoubard	1:ebc0e0ef0a11	786	/**
vcoubard	1:ebc0e0ef0a11	787	* @brief Random Number Generator. (RNG)
vcoubard	1:ebc0e0ef0a11	788	*/
vcoubard	1:ebc0e0ef0a11	789
vcoubard	1:ebc0e0ef0a11	790	typedef struct { /!< RNG Structure /
vcoubard	1:ebc0e0ef0a11	791	__O uint32_t TASKS_START; /!< Start the random number generator. /
vcoubard	1:ebc0e0ef0a11	792	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
vcoubard	1:ebc0e0ef0a11	793	__I uint32_t RESERVED0[62];
vcoubard	1:ebc0e0ef0a11	794	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
vcoubard	1:ebc0e0ef0a11	795	__I uint32_t RESERVED1[63];
vcoubard	1:ebc0e0ef0a11	796	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
vcoubard	1:ebc0e0ef0a11	797	__I uint32_t RESERVED2[64];
vcoubard	1:ebc0e0ef0a11	798	__IO uint32_t INTENSET; /!< Interrupt enable set register /
vcoubard	1:ebc0e0ef0a11	799	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
vcoubard	1:ebc0e0ef0a11	800	__I uint32_t RESERVED3[126];
vcoubard	1:ebc0e0ef0a11	801	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	802	__I uint32_t VALUE; /!< RNG random number. /
vcoubard	1:ebc0e0ef0a11	803	__I uint32_t RESERVED4[700];
vcoubard	1:ebc0e0ef0a11	804	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	805	} NRF_RNG_Type;
vcoubard	1:ebc0e0ef0a11	806
vcoubard	1:ebc0e0ef0a11	807
vcoubard	1:ebc0e0ef0a11	808	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	809	/* ================ ECB ================ */
vcoubard	1:ebc0e0ef0a11	810	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	811
vcoubard	1:ebc0e0ef0a11	812
vcoubard	1:ebc0e0ef0a11	813	/**
vcoubard	1:ebc0e0ef0a11	814	* @brief AES ECB Mode Encryption. (ECB)
vcoubard	1:ebc0e0ef0a11	815	*/
vcoubard	1:ebc0e0ef0a11	816
vcoubard	1:ebc0e0ef0a11	817	typedef struct { /!< ECB Structure /
vcoubard	1:ebc0e0ef0a11	818	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
vcoubard	1:ebc0e0ef0a11	819	will not initiate a new encryption and the ERRORECB event will
vcoubard	1:ebc0e0ef0a11	820	be triggered. */
vcoubard	1:ebc0e0ef0a11	821	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
vcoubard	1:ebc0e0ef0a11	822	this will will trigger the ERRORECB event. */
vcoubard	1:ebc0e0ef0a11	823	__I uint32_t RESERVED0[62];
vcoubard	1:ebc0e0ef0a11	824	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
vcoubard	1:ebc0e0ef0a11	825	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
vcoubard	1:ebc0e0ef0a11	826	error. */
vcoubard	1:ebc0e0ef0a11	827	__I uint32_t RESERVED1[127];
vcoubard	1:ebc0e0ef0a11	828	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	829	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	830	__I uint32_t RESERVED2[126];
vcoubard	1:ebc0e0ef0a11	831	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
vcoubard	1:ebc0e0ef0a11	832	__I uint32_t RESERVED3[701];
vcoubard	1:ebc0e0ef0a11	833	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	834	} NRF_ECB_Type;
vcoubard	1:ebc0e0ef0a11	835
vcoubard	1:ebc0e0ef0a11	836
vcoubard	1:ebc0e0ef0a11	837	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	838	/* ================ AAR ================ */
vcoubard	1:ebc0e0ef0a11	839	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	840
vcoubard	1:ebc0e0ef0a11	841
vcoubard	1:ebc0e0ef0a11	842	/**
vcoubard	1:ebc0e0ef0a11	843	* @brief Accelerated Address Resolver. (AAR)
vcoubard	1:ebc0e0ef0a11	844	*/
vcoubard	1:ebc0e0ef0a11	845
vcoubard	1:ebc0e0ef0a11	846	typedef struct { /!< AAR Structure /
vcoubard	1:ebc0e0ef0a11	847	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
vcoubard	1:ebc0e0ef0a11	848	data structure. */
vcoubard	1:ebc0e0ef0a11	849	__I uint32_t RESERVED0;
vcoubard	1:ebc0e0ef0a11	850	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
vcoubard	1:ebc0e0ef0a11	851	__I uint32_t RESERVED1[61];
vcoubard	1:ebc0e0ef0a11	852	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
vcoubard	1:ebc0e0ef0a11	853	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
vcoubard	1:ebc0e0ef0a11	854	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
vcoubard	1:ebc0e0ef0a11	855	__I uint32_t RESERVED2[126];
vcoubard	1:ebc0e0ef0a11	856	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	857	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	858	__I uint32_t RESERVED3[61];
vcoubard	1:ebc0e0ef0a11	859	__I uint32_t STATUS; /!< Resolution status. /
vcoubard	1:ebc0e0ef0a11	860	__I uint32_t RESERVED4[63];
vcoubard	1:ebc0e0ef0a11	861	__IO uint32_t ENABLE; /!< Enable AAR. /
vcoubard	1:ebc0e0ef0a11	862	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
vcoubard	1:ebc0e0ef0a11	863	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
vcoubard	1:ebc0e0ef0a11	864	__I uint32_t RESERVED5;
vcoubard	1:ebc0e0ef0a11	865	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
vcoubard	1:ebc0e0ef0a11	866	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
vcoubard	1:ebc0e0ef0a11	867	during resolution. A minimum of 3 bytes must be reserved. */
vcoubard	1:ebc0e0ef0a11	868	__I uint32_t RESERVED6[697];
vcoubard	1:ebc0e0ef0a11	869	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	870	} NRF_AAR_Type;
vcoubard	1:ebc0e0ef0a11	871
vcoubard	1:ebc0e0ef0a11	872
vcoubard	1:ebc0e0ef0a11	873	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	874	/* ================ CCM ================ */
vcoubard	1:ebc0e0ef0a11	875	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	876
vcoubard	1:ebc0e0ef0a11	877
vcoubard	1:ebc0e0ef0a11	878	/**
vcoubard	1:ebc0e0ef0a11	879	* @brief AES CCM Mode Encryption. (CCM)
vcoubard	1:ebc0e0ef0a11	880	*/
vcoubard	1:ebc0e0ef0a11	881
vcoubard	1:ebc0e0ef0a11	882	typedef struct { /!< CCM Structure /
vcoubard	1:ebc0e0ef0a11	883	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
vcoubard	1:ebc0e0ef0a11	884	itself when completed. */
vcoubard	1:ebc0e0ef0a11	885	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
vcoubard	1:ebc0e0ef0a11	886	completed. */
vcoubard	1:ebc0e0ef0a11	887	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
vcoubard	1:ebc0e0ef0a11	888	__I uint32_t RESERVED0[61];
vcoubard	1:ebc0e0ef0a11	889	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
vcoubard	1:ebc0e0ef0a11	890	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
vcoubard	1:ebc0e0ef0a11	891	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
vcoubard	1:ebc0e0ef0a11	892	__I uint32_t RESERVED1[61];
vcoubard	1:ebc0e0ef0a11	893	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
vcoubard	1:ebc0e0ef0a11	894	__I uint32_t RESERVED2[64];
vcoubard	1:ebc0e0ef0a11	895	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	896	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	897	__I uint32_t RESERVED3[61];
vcoubard	1:ebc0e0ef0a11	898	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
vcoubard	1:ebc0e0ef0a11	899	__I uint32_t RESERVED4[63];
vcoubard	1:ebc0e0ef0a11	900	__IO uint32_t ENABLE; /!< CCM enable. /
vcoubard	1:ebc0e0ef0a11	901	__IO uint32_t MODE; /!< Operation mode. /
vcoubard	1:ebc0e0ef0a11	902	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
vcoubard	1:ebc0e0ef0a11	903	__IO uint32_t INPTR; /!< Pointer to the input packet. /
vcoubard	1:ebc0e0ef0a11	904	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
vcoubard	1:ebc0e0ef0a11	905	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
vcoubard	1:ebc0e0ef0a11	906	during resolution. A minimum of 43 bytes must be reserved. */
vcoubard	1:ebc0e0ef0a11	907	__I uint32_t RESERVED5[697];
vcoubard	1:ebc0e0ef0a11	908	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	909	} NRF_CCM_Type;
vcoubard	1:ebc0e0ef0a11	910
vcoubard	1:ebc0e0ef0a11	911
vcoubard	1:ebc0e0ef0a11	912	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	913	/* ================ WDT ================ */
vcoubard	1:ebc0e0ef0a11	914	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	915
vcoubard	1:ebc0e0ef0a11	916
vcoubard	1:ebc0e0ef0a11	917	/**
vcoubard	1:ebc0e0ef0a11	918	* @brief Watchdog Timer. (WDT)
vcoubard	1:ebc0e0ef0a11	919	*/
vcoubard	1:ebc0e0ef0a11	920
vcoubard	1:ebc0e0ef0a11	921	typedef struct { /!< WDT Structure /
vcoubard	1:ebc0e0ef0a11	922	__O uint32_t TASKS_START; /!< Start the watchdog. /
vcoubard	1:ebc0e0ef0a11	923	__I uint32_t RESERVED0[63];
vcoubard	1:ebc0e0ef0a11	924	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
vcoubard	1:ebc0e0ef0a11	925	__I uint32_t RESERVED1[128];
vcoubard	1:ebc0e0ef0a11	926	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	927	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	928	__I uint32_t RESERVED2[61];
vcoubard	1:ebc0e0ef0a11	929	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
vcoubard	1:ebc0e0ef0a11	930	__I uint32_t REQSTATUS; /!< Request status. /
vcoubard	1:ebc0e0ef0a11	931	__I uint32_t RESERVED3[63];
vcoubard	1:ebc0e0ef0a11	932	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
vcoubard	1:ebc0e0ef0a11	933	__IO uint32_t RREN; /!< Reload request enable. /
vcoubard	1:ebc0e0ef0a11	934	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	935	__I uint32_t RESERVED4[60];
vcoubard	1:ebc0e0ef0a11	936	__O uint32_t RR[8]; /!< Reload requests registers. /
vcoubard	1:ebc0e0ef0a11	937	__I uint32_t RESERVED5[631];
vcoubard	1:ebc0e0ef0a11	938	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	939	} NRF_WDT_Type;
vcoubard	1:ebc0e0ef0a11	940
vcoubard	1:ebc0e0ef0a11	941
vcoubard	1:ebc0e0ef0a11	942	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	943	/* ================ QDEC ================ */
vcoubard	1:ebc0e0ef0a11	944	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	945
vcoubard	1:ebc0e0ef0a11	946
vcoubard	1:ebc0e0ef0a11	947	/**
vcoubard	1:ebc0e0ef0a11	948	* @brief Rotary decoder. (QDEC)
vcoubard	1:ebc0e0ef0a11	949	*/
vcoubard	1:ebc0e0ef0a11	950
vcoubard	1:ebc0e0ef0a11	951	typedef struct { /!< QDEC Structure /
vcoubard	1:ebc0e0ef0a11	952	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
vcoubard	1:ebc0e0ef0a11	953	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
vcoubard	1:ebc0e0ef0a11	954	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
vcoubard	1:ebc0e0ef0a11	955	and clears the ACC registers. */
vcoubard	1:ebc0e0ef0a11	956	__I uint32_t RESERVED0[61];
vcoubard	1:ebc0e0ef0a11	957	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
vcoubard	1:ebc0e0ef0a11	958	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
vcoubard	1:ebc0e0ef0a11	959	ACC register different than zero. */
vcoubard	1:ebc0e0ef0a11	960	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
vcoubard	1:ebc0e0ef0a11	961	__I uint32_t RESERVED1[61];
vcoubard	1:ebc0e0ef0a11	962	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
vcoubard	1:ebc0e0ef0a11	963	__I uint32_t RESERVED2[64];
vcoubard	1:ebc0e0ef0a11	964	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	965	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	966	__I uint32_t RESERVED3[125];
vcoubard	1:ebc0e0ef0a11	967	__IO uint32_t ENABLE; /!< Enable the QDEC. /
vcoubard	1:ebc0e0ef0a11	968	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
vcoubard	1:ebc0e0ef0a11	969	__IO uint32_t SAMPLEPER; /!< Sample period. /
vcoubard	1:ebc0e0ef0a11	970	__I int32_t SAMPLE; /!< Motion sample value. /
vcoubard	1:ebc0e0ef0a11	971	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
vcoubard	1:ebc0e0ef0a11	972	__I int32_t ACC; /!< Accumulated valid transitions register. /
vcoubard	1:ebc0e0ef0a11	973	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
vcoubard	1:ebc0e0ef0a11	974	task. */
vcoubard	1:ebc0e0ef0a11	975	__IO uint32_t PSELLED; /!< Pin select for LED output. /
vcoubard	1:ebc0e0ef0a11	976	__IO uint32_t PSELA; /!< Pin select for phase A input. /
vcoubard	1:ebc0e0ef0a11	977	__IO uint32_t PSELB; /!< Pin select for phase B input. /
vcoubard	1:ebc0e0ef0a11	978	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
vcoubard	1:ebc0e0ef0a11	979	__I uint32_t RESERVED4[5];
vcoubard	1:ebc0e0ef0a11	980	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
vcoubard	1:ebc0e0ef0a11	981	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
vcoubard	1:ebc0e0ef0a11	982	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
vcoubard	1:ebc0e0ef0a11	983	task. */
vcoubard	1:ebc0e0ef0a11	984	__I uint32_t RESERVED5[684];
vcoubard	1:ebc0e0ef0a11	985	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	986	} NRF_QDEC_Type;
vcoubard	1:ebc0e0ef0a11	987
vcoubard	1:ebc0e0ef0a11	988
vcoubard	1:ebc0e0ef0a11	989	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	990	/* ================ LPCOMP ================ */
vcoubard	1:ebc0e0ef0a11	991	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	992
vcoubard	1:ebc0e0ef0a11	993
vcoubard	1:ebc0e0ef0a11	994	/**
vcoubard	1:ebc0e0ef0a11	995	* @brief Low power comparator. (LPCOMP)
vcoubard	1:ebc0e0ef0a11	996	*/
vcoubard	1:ebc0e0ef0a11	997
vcoubard	1:ebc0e0ef0a11	998	typedef struct { /!< LPCOMP Structure /
vcoubard	1:ebc0e0ef0a11	999	__O uint32_t TASKS_START; /!< Start the comparator. /
vcoubard	1:ebc0e0ef0a11	1000	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
vcoubard	1:ebc0e0ef0a11	1001	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
vcoubard	1:ebc0e0ef0a11	1002	__I uint32_t RESERVED0[61];
vcoubard	1:ebc0e0ef0a11	1003	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
vcoubard	1:ebc0e0ef0a11	1004	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
vcoubard	1:ebc0e0ef0a11	1005	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
vcoubard	1:ebc0e0ef0a11	1006	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
vcoubard	1:ebc0e0ef0a11	1007	__I uint32_t RESERVED1[60];
vcoubard	1:ebc0e0ef0a11	1008	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
vcoubard	1:ebc0e0ef0a11	1009	__I uint32_t RESERVED2[64];
vcoubard	1:ebc0e0ef0a11	1010	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	1:ebc0e0ef0a11	1011	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	1:ebc0e0ef0a11	1012	__I uint32_t RESERVED3[61];
vcoubard	1:ebc0e0ef0a11	1013	__I uint32_t RESULT; /!< Result of last compare. /
vcoubard	1:ebc0e0ef0a11	1014	__I uint32_t RESERVED4[63];
vcoubard	1:ebc0e0ef0a11	1015	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
vcoubard	1:ebc0e0ef0a11	1016	__IO uint32_t PSEL; /!< Input pin select. /
vcoubard	1:ebc0e0ef0a11	1017	__IO uint32_t REFSEL; /!< Reference select. /
vcoubard	1:ebc0e0ef0a11	1018	__IO uint32_t EXTREFSEL; /!< External reference select. /
vcoubard	1:ebc0e0ef0a11	1019	__I uint32_t RESERVED5[4];
vcoubard	1:ebc0e0ef0a11	1020	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
vcoubard	1:ebc0e0ef0a11	1021	__I uint32_t RESERVED6[694];
vcoubard	1:ebc0e0ef0a11	1022	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	1:ebc0e0ef0a11	1023	} NRF_LPCOMP_Type;
vcoubard	1:ebc0e0ef0a11	1024
vcoubard	1:ebc0e0ef0a11	1025
vcoubard	1:ebc0e0ef0a11	1026	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1027	/* ================ SWI ================ */
vcoubard	1:ebc0e0ef0a11	1028	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1029
vcoubard	1:ebc0e0ef0a11	1030
vcoubard	1:ebc0e0ef0a11	1031	/**
vcoubard	1:ebc0e0ef0a11	1032	* @brief SW Interrupts. (SWI)
vcoubard	1:ebc0e0ef0a11	1033	*/
vcoubard	1:ebc0e0ef0a11	1034
vcoubard	1:ebc0e0ef0a11	1035	typedef struct { /!< SWI Structure /
vcoubard	1:ebc0e0ef0a11	1036	__I uint32_t UNUSED; /!< Unused. /
vcoubard	1:ebc0e0ef0a11	1037	} NRF_SWI_Type;
vcoubard	1:ebc0e0ef0a11	1038
vcoubard	1:ebc0e0ef0a11	1039
vcoubard	1:ebc0e0ef0a11	1040	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1041	/* ================ NVMC ================ */
vcoubard	1:ebc0e0ef0a11	1042	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1043
vcoubard	1:ebc0e0ef0a11	1044
vcoubard	1:ebc0e0ef0a11	1045	/**
vcoubard	1:ebc0e0ef0a11	1046	* @brief Non Volatile Memory Controller. (NVMC)
vcoubard	1:ebc0e0ef0a11	1047	*/
vcoubard	1:ebc0e0ef0a11	1048
vcoubard	1:ebc0e0ef0a11	1049	typedef struct { /!< NVMC Structure /
vcoubard	1:ebc0e0ef0a11	1050	__I uint32_t RESERVED0[256];
vcoubard	1:ebc0e0ef0a11	1051	__I uint32_t READY; /!< Ready flag. /
vcoubard	1:ebc0e0ef0a11	1052	__I uint32_t RESERVED1[64];
vcoubard	1:ebc0e0ef0a11	1053	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	1:ebc0e0ef0a11	1054
vcoubard	1:ebc0e0ef0a11	1055	union {
vcoubard	1:ebc0e0ef0a11	1056	__IO uint32_t ERASEPCR1; /!< Register for erasing a non-protected non-volatile memory page. /
vcoubard	1:ebc0e0ef0a11	1057	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
vcoubard	1:ebc0e0ef0a11	1058	};
vcoubard	1:ebc0e0ef0a11	1059	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
vcoubard	1:ebc0e0ef0a11	1060	__IO uint32_t ERASEPCR0; /!< Register for erasing a protected non-volatile memory page. /
vcoubard	1:ebc0e0ef0a11	1061	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
vcoubard	1:ebc0e0ef0a11	1062	} NRF_NVMC_Type;
vcoubard	1:ebc0e0ef0a11	1063
vcoubard	1:ebc0e0ef0a11	1064
vcoubard	1:ebc0e0ef0a11	1065	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1066	/* ================ PPI ================ */
vcoubard	1:ebc0e0ef0a11	1067	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1068
vcoubard	1:ebc0e0ef0a11	1069
vcoubard	1:ebc0e0ef0a11	1070	/**
vcoubard	1:ebc0e0ef0a11	1071	* @brief PPI controller. (PPI)
vcoubard	1:ebc0e0ef0a11	1072	*/
vcoubard	1:ebc0e0ef0a11	1073
vcoubard	1:ebc0e0ef0a11	1074	typedef struct { /!< PPI Structure /
vcoubard	1:ebc0e0ef0a11	1075	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
vcoubard	1:ebc0e0ef0a11	1076	__I uint32_t RESERVED0[312];
vcoubard	1:ebc0e0ef0a11	1077	__IO uint32_t CHEN; /!< Channel enable. /
vcoubard	1:ebc0e0ef0a11	1078	__IO uint32_t CHENSET; /!< Channel enable set. /
vcoubard	1:ebc0e0ef0a11	1079	__IO uint32_t CHENCLR; /!< Channel enable clear. /
vcoubard	1:ebc0e0ef0a11	1080	__I uint32_t RESERVED1;
vcoubard	1:ebc0e0ef0a11	1081	PPI_CH_Type CH[16]; /!< PPI Channel. /
vcoubard	1:ebc0e0ef0a11	1082	__I uint32_t RESERVED2[156];
vcoubard	1:ebc0e0ef0a11	1083	__IO uint32_t CHG[4]; /!< Channel group configuration. /
vcoubard	1:ebc0e0ef0a11	1084	} NRF_PPI_Type;
vcoubard	1:ebc0e0ef0a11	1085
vcoubard	1:ebc0e0ef0a11	1086
vcoubard	1:ebc0e0ef0a11	1087	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1088	/* ================ FICR ================ */
vcoubard	1:ebc0e0ef0a11	1089	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1090
vcoubard	1:ebc0e0ef0a11	1091
vcoubard	1:ebc0e0ef0a11	1092	/**
vcoubard	1:ebc0e0ef0a11	1093	* @brief Factory Information Configuration. (FICR)
vcoubard	1:ebc0e0ef0a11	1094	*/
vcoubard	1:ebc0e0ef0a11	1095
vcoubard	1:ebc0e0ef0a11	1096	typedef struct { /!< FICR Structure /
vcoubard	1:ebc0e0ef0a11	1097	__I uint32_t RESERVED0[4];
vcoubard	1:ebc0e0ef0a11	1098	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
vcoubard	1:ebc0e0ef0a11	1099	__I uint32_t CODESIZE; /!< Code memory size in pages. /
vcoubard	1:ebc0e0ef0a11	1100	__I uint32_t RESERVED1[4];
vcoubard	1:ebc0e0ef0a11	1101	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
vcoubard	1:ebc0e0ef0a11	1102	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
vcoubard	1:ebc0e0ef0a11	1103	__I uint32_t RESERVED2;
vcoubard	1:ebc0e0ef0a11	1104	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
vcoubard	1:ebc0e0ef0a11	1105
vcoubard	1:ebc0e0ef0a11	1106	union {
vcoubard	1:ebc0e0ef0a11	1107	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
vcoubard	1:ebc0e0ef0a11	1108	kept for backward compatinility purposes. Use SIZERAMBLOCKS
vcoubard	1:ebc0e0ef0a11	1109	instead. */
vcoubard	1:ebc0e0ef0a11	1110	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
vcoubard	1:ebc0e0ef0a11	1111	};
vcoubard	1:ebc0e0ef0a11	1112	__I uint32_t RESERVED3[5];
vcoubard	1:ebc0e0ef0a11	1113	__I uint32_t CONFIGID; /!< Configuration identifier. /
vcoubard	1:ebc0e0ef0a11	1114	__I uint32_t DEVICEID[2]; /!< Device identifier. /
vcoubard	1:ebc0e0ef0a11	1115	__I uint32_t RESERVED4[6];
vcoubard	1:ebc0e0ef0a11	1116	__I uint32_t ER[4]; /!< Encryption root. /
vcoubard	1:ebc0e0ef0a11	1117	__I uint32_t IR[4]; /!< Identity root. /
vcoubard	1:ebc0e0ef0a11	1118	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
vcoubard	1:ebc0e0ef0a11	1119	__I uint32_t DEVICEADDR[2]; /!< Device address. /
vcoubard	1:ebc0e0ef0a11	1120	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
vcoubard	1:ebc0e0ef0a11	1121	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
vcoubard	1:ebc0e0ef0a11	1122	mode. */
vcoubard	1:ebc0e0ef0a11	1123	__I uint32_t RESERVED5[10];
vcoubard	1:ebc0e0ef0a11	1124	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
vcoubard	1:ebc0e0ef0a11	1125	mode. */
vcoubard	1:ebc0e0ef0a11	1126	} NRF_FICR_Type;
vcoubard	1:ebc0e0ef0a11	1127
vcoubard	1:ebc0e0ef0a11	1128
vcoubard	1:ebc0e0ef0a11	1129	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1130	/* ================ UICR ================ */
vcoubard	1:ebc0e0ef0a11	1131	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1132
vcoubard	1:ebc0e0ef0a11	1133
vcoubard	1:ebc0e0ef0a11	1134	/**
vcoubard	1:ebc0e0ef0a11	1135	* @brief User Information Configuration. (UICR)
vcoubard	1:ebc0e0ef0a11	1136	*/
vcoubard	1:ebc0e0ef0a11	1137
vcoubard	1:ebc0e0ef0a11	1138	typedef struct { /!< UICR Structure /
vcoubard	1:ebc0e0ef0a11	1139	__IO uint32_t CLENR0; /!< Length of code region 0. /
vcoubard	1:ebc0e0ef0a11	1140	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
vcoubard	1:ebc0e0ef0a11	1141	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
vcoubard	1:ebc0e0ef0a11	1142	__I uint32_t RESERVED0;
vcoubard	1:ebc0e0ef0a11	1143	__I uint32_t FWID; /!< Firmware ID. /
vcoubard	1:ebc0e0ef0a11	1144
vcoubard	1:ebc0e0ef0a11	1145	union {
vcoubard	1:ebc0e0ef0a11	1146	__IO uint32_t NRFFW[15]; /!< Reserved for Nordic firmware design. /
vcoubard	1:ebc0e0ef0a11	1147	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
vcoubard	1:ebc0e0ef0a11	1148	};
vcoubard	1:ebc0e0ef0a11	1149	__IO uint32_t NRFHW[12]; /!< Reserved for Nordic hardware design. /
vcoubard	1:ebc0e0ef0a11	1150	__IO uint32_t CUSTOMER[32]; /!< Reserved for customer. /
vcoubard	1:ebc0e0ef0a11	1151	} NRF_UICR_Type;
vcoubard	1:ebc0e0ef0a11	1152
vcoubard	1:ebc0e0ef0a11	1153
vcoubard	1:ebc0e0ef0a11	1154	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1155	/* ================ GPIO ================ */
vcoubard	1:ebc0e0ef0a11	1156	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1157
vcoubard	1:ebc0e0ef0a11	1158
vcoubard	1:ebc0e0ef0a11	1159	/**
vcoubard	1:ebc0e0ef0a11	1160	* @brief General purpose input and output. (GPIO)
vcoubard	1:ebc0e0ef0a11	1161	*/
vcoubard	1:ebc0e0ef0a11	1162
vcoubard	1:ebc0e0ef0a11	1163	typedef struct { /!< GPIO Structure /
vcoubard	1:ebc0e0ef0a11	1164	__I uint32_t RESERVED0[321];
vcoubard	1:ebc0e0ef0a11	1165	__IO uint32_t OUT; /!< Write GPIO port. /
vcoubard	1:ebc0e0ef0a11	1166	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
vcoubard	1:ebc0e0ef0a11	1167	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
vcoubard	1:ebc0e0ef0a11	1168	__I uint32_t IN; /!< Read GPIO port. /
vcoubard	1:ebc0e0ef0a11	1169	__IO uint32_t DIR; /!< Direction of GPIO pins. /
vcoubard	1:ebc0e0ef0a11	1170	__IO uint32_t DIRSET; /!< DIR set register. /
vcoubard	1:ebc0e0ef0a11	1171	__IO uint32_t DIRCLR; /!< DIR clear register. /
vcoubard	1:ebc0e0ef0a11	1172	__I uint32_t RESERVED1[120];
vcoubard	1:ebc0e0ef0a11	1173	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
vcoubard	1:ebc0e0ef0a11	1174	} NRF_GPIO_Type;
vcoubard	1:ebc0e0ef0a11	1175
vcoubard	1:ebc0e0ef0a11	1176
vcoubard	1:ebc0e0ef0a11	1177	/* -------------------- End of section using anonymous unions ------------------- */
vcoubard	1:ebc0e0ef0a11	1178	#if defined(__CC_ARM)
vcoubard	1:ebc0e0ef0a11	1179	#pragma pop
vcoubard	1:ebc0e0ef0a11	1180	#elif defined(__ICCARM__)
vcoubard	1:ebc0e0ef0a11	1181	/* leave anonymous unions enabled */
vcoubard	1:ebc0e0ef0a11	1182	#elif defined(__GNUC__)
vcoubard	1:ebc0e0ef0a11	1183	/* anonymous unions are enabled by default */
vcoubard	1:ebc0e0ef0a11	1184	#elif defined(__TMS470__)
vcoubard	1:ebc0e0ef0a11	1185	/* anonymous unions are enabled by default */
vcoubard	1:ebc0e0ef0a11	1186	#elif defined(__TASKING__)
vcoubard	1:ebc0e0ef0a11	1187	#pragma warning restore
vcoubard	1:ebc0e0ef0a11	1188	#else
vcoubard	1:ebc0e0ef0a11	1189	#warning Not supported compiler type
vcoubard	1:ebc0e0ef0a11	1190	#endif
vcoubard	1:ebc0e0ef0a11	1191
vcoubard	1:ebc0e0ef0a11	1192
vcoubard	1:ebc0e0ef0a11	1193
vcoubard	1:ebc0e0ef0a11	1194
vcoubard	1:ebc0e0ef0a11	1195	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1196	/* ================ Peripheral memory map ================ */
vcoubard	1:ebc0e0ef0a11	1197	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1198
vcoubard	1:ebc0e0ef0a11	1199	#define NRF_POWER_BASE 0x40000000UL
vcoubard	1:ebc0e0ef0a11	1200	#define NRF_CLOCK_BASE 0x40000000UL
vcoubard	1:ebc0e0ef0a11	1201	#define NRF_MPU_BASE 0x40000000UL
vcoubard	1:ebc0e0ef0a11	1202	#define NRF_AMLI_BASE 0x40000000UL
vcoubard	1:ebc0e0ef0a11	1203	#define NRF_RADIO_BASE 0x40001000UL
vcoubard	1:ebc0e0ef0a11	1204	#define NRF_UART0_BASE 0x40002000UL
vcoubard	1:ebc0e0ef0a11	1205	#define NRF_SPI0_BASE 0x40003000UL
vcoubard	1:ebc0e0ef0a11	1206	#define NRF_TWI0_BASE 0x40003000UL
vcoubard	1:ebc0e0ef0a11	1207	#define NRF_SPI1_BASE 0x40004000UL
vcoubard	1:ebc0e0ef0a11	1208	#define NRF_TWI1_BASE 0x40004000UL
vcoubard	1:ebc0e0ef0a11	1209	#define NRF_SPIS1_BASE 0x40004000UL
vcoubard	1:ebc0e0ef0a11	1210	#define NRF_SPIM1_BASE 0x40004000UL
vcoubard	1:ebc0e0ef0a11	1211	#define NRF_GPIOTE_BASE 0x40006000UL
vcoubard	1:ebc0e0ef0a11	1212	#define NRF_ADC_BASE 0x40007000UL
vcoubard	1:ebc0e0ef0a11	1213	#define NRF_TIMER0_BASE 0x40008000UL
vcoubard	1:ebc0e0ef0a11	1214	#define NRF_TIMER1_BASE 0x40009000UL
vcoubard	1:ebc0e0ef0a11	1215	#define NRF_TIMER2_BASE 0x4000A000UL
vcoubard	1:ebc0e0ef0a11	1216	#define NRF_RTC0_BASE 0x4000B000UL
vcoubard	1:ebc0e0ef0a11	1217	#define NRF_TEMP_BASE 0x4000C000UL
vcoubard	1:ebc0e0ef0a11	1218	#define NRF_RNG_BASE 0x4000D000UL
vcoubard	1:ebc0e0ef0a11	1219	#define NRF_ECB_BASE 0x4000E000UL
vcoubard	1:ebc0e0ef0a11	1220	#define NRF_AAR_BASE 0x4000F000UL
vcoubard	1:ebc0e0ef0a11	1221	#define NRF_CCM_BASE 0x4000F000UL
vcoubard	1:ebc0e0ef0a11	1222	#define NRF_WDT_BASE 0x40010000UL
vcoubard	1:ebc0e0ef0a11	1223	#define NRF_RTC1_BASE 0x40011000UL
vcoubard	1:ebc0e0ef0a11	1224	#define NRF_QDEC_BASE 0x40012000UL
vcoubard	1:ebc0e0ef0a11	1225	#define NRF_LPCOMP_BASE 0x40013000UL
vcoubard	1:ebc0e0ef0a11	1226	#define NRF_SWI_BASE 0x40014000UL
vcoubard	1:ebc0e0ef0a11	1227	#define NRF_NVMC_BASE 0x4001E000UL
vcoubard	1:ebc0e0ef0a11	1228	#define NRF_PPI_BASE 0x4001F000UL
vcoubard	1:ebc0e0ef0a11	1229	#define NRF_FICR_BASE 0x10000000UL
vcoubard	1:ebc0e0ef0a11	1230	#define NRF_UICR_BASE 0x10001000UL
vcoubard	1:ebc0e0ef0a11	1231	#define NRF_GPIO_BASE 0x50000000UL
vcoubard	1:ebc0e0ef0a11	1232
vcoubard	1:ebc0e0ef0a11	1233
vcoubard	1:ebc0e0ef0a11	1234	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1235	/* ================ Peripheral declaration ================ */
vcoubard	1:ebc0e0ef0a11	1236	/* ================================================================================ */
vcoubard	1:ebc0e0ef0a11	1237
vcoubard	1:ebc0e0ef0a11	1238	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
vcoubard	1:ebc0e0ef0a11	1239	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
vcoubard	1:ebc0e0ef0a11	1240	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
vcoubard	1:ebc0e0ef0a11	1241	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
vcoubard	1:ebc0e0ef0a11	1242	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
vcoubard	1:ebc0e0ef0a11	1243	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
vcoubard	1:ebc0e0ef0a11	1244	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
vcoubard	1:ebc0e0ef0a11	1245	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
vcoubard	1:ebc0e0ef0a11	1246	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
vcoubard	1:ebc0e0ef0a11	1247	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
vcoubard	1:ebc0e0ef0a11	1248	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
vcoubard	1:ebc0e0ef0a11	1249	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
vcoubard	1:ebc0e0ef0a11	1250	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
vcoubard	1:ebc0e0ef0a11	1251	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
vcoubard	1:ebc0e0ef0a11	1252	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
vcoubard	1:ebc0e0ef0a11	1253	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
vcoubard	1:ebc0e0ef0a11	1254	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
vcoubard	1:ebc0e0ef0a11	1255	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
vcoubard	1:ebc0e0ef0a11	1256	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
vcoubard	1:ebc0e0ef0a11	1257	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
vcoubard	1:ebc0e0ef0a11	1258	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
vcoubard	1:ebc0e0ef0a11	1259	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
vcoubard	1:ebc0e0ef0a11	1260	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
vcoubard	1:ebc0e0ef0a11	1261	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
vcoubard	1:ebc0e0ef0a11	1262	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
vcoubard	1:ebc0e0ef0a11	1263	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
vcoubard	1:ebc0e0ef0a11	1264	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
vcoubard	1:ebc0e0ef0a11	1265	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
vcoubard	1:ebc0e0ef0a11	1266	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
vcoubard	1:ebc0e0ef0a11	1267	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
vcoubard	1:ebc0e0ef0a11	1268	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
vcoubard	1:ebc0e0ef0a11	1269	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
vcoubard	1:ebc0e0ef0a11	1270	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
vcoubard	1:ebc0e0ef0a11	1271
vcoubard	1:ebc0e0ef0a11	1272
vcoubard	1:ebc0e0ef0a11	1273	/** @} / / End of group Device_Peripheral_Registers */
vcoubard	1:ebc0e0ef0a11	1274	/** @} / / End of group nrf51 */
vcoubard	1:ebc0e0ef0a11	1275	/** @} / / End of group Nordic Semiconductor */
vcoubard	1:ebc0e0ef0a11	1276
vcoubard	1:ebc0e0ef0a11	1277	#ifdef __cplusplus
vcoubard	1:ebc0e0ef0a11	1278	}
vcoubard	1:ebc0e0ef0a11	1279	#endif
vcoubard	1:ebc0e0ef0a11	1280
vcoubard	1:ebc0e0ef0a11	1281
vcoubard	1:ebc0e0ef0a11	1282	#endif /* nrf51_H */
vcoubard	1:ebc0e0ef0a11	1283

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Type:	Library
Created:	08 Apr 2016
Imports:	553
Forks:	7
Commits:	46
Dependents:	2
Dependencies:	0
Followers:	75

source/nordic_sdk/components/device/nrf51.h@19:47192cb9def7, 2016-04-07 (annotated)

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