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Nordic nrf51 sdk sources. Mirrored from https://github.com/ARMmbed/nrf51-sdk.

source/nordic_sdk/components/device/nrf51_bitfields.h@24:2aea0c1c57ee, 2016-04-07 (annotated)

Committer:: vcoubard
Date:: Thu Apr 07 17:37:49 2016 +0100
Revision:: 24:2aea0c1c57ee
Parent:: 22:67a8d2c0bbbf
Child:: 27:0fe148f1bca3

Synchronized with git rev 709d3cdb

Author: Liyou Zhou

Change version number in README

Who changed what in which revision?

User	Revision	Line number	New contents of line
vcoubard	20:a90c48eb1d30	1	/*
vcoubard	20:a90c48eb1d30	2	* Copyright (c) Nordic Semiconductor ASA
vcoubard	20:a90c48eb1d30	3	* All rights reserved.
vcoubard	20:a90c48eb1d30	4	*
vcoubard	20:a90c48eb1d30	5	* Redistribution and use in source and binary forms, with or without modification,
vcoubard	20:a90c48eb1d30	6	* are permitted provided that the following conditions are met:
vcoubard	20:a90c48eb1d30	7	*
vcoubard	20:a90c48eb1d30	8	* 1. Redistributions of source code must retain the above copyright notice, this
vcoubard	20:a90c48eb1d30	9	* list of conditions and the following disclaimer.
vcoubard	20:a90c48eb1d30	10	*
vcoubard	20:a90c48eb1d30	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
vcoubard	20:a90c48eb1d30	12	* list of conditions and the following disclaimer in the documentation and/or
vcoubard	20:a90c48eb1d30	13	* other materials provided with the distribution.
vcoubard	20:a90c48eb1d30	14	*
vcoubard	20:a90c48eb1d30	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
vcoubard	20:a90c48eb1d30	16	* contributors to this software may be used to endorse or promote products
vcoubard	20:a90c48eb1d30	17	* derived from this software without specific prior written permission.
vcoubard	20:a90c48eb1d30	18	*
vcoubard	20:a90c48eb1d30	19	*
vcoubard	20:a90c48eb1d30	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vcoubard	20:a90c48eb1d30	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vcoubard	20:a90c48eb1d30	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vcoubard	20:a90c48eb1d30	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vcoubard	20:a90c48eb1d30	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vcoubard	20:a90c48eb1d30	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vcoubard	20:a90c48eb1d30	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vcoubard	20:a90c48eb1d30	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vcoubard	20:a90c48eb1d30	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vcoubard	20:a90c48eb1d30	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vcoubard	20:a90c48eb1d30	30	*
vcoubard	1:ebc0e0ef0a11	31	*/
vcoubard	1:ebc0e0ef0a11	32	#ifndef __NRF51_BITS_H
vcoubard	1:ebc0e0ef0a11	33	#define __NRF51_BITS_H
vcoubard	1:ebc0e0ef0a11	34
vcoubard	1:ebc0e0ef0a11	35	/lint ++flb "Enter library region" /
vcoubard	1:ebc0e0ef0a11	36
vcoubard	1:ebc0e0ef0a11	37	/* Peripheral: AAR */
vcoubard	1:ebc0e0ef0a11	38	/* Description: Accelerated Address Resolver. */
vcoubard	1:ebc0e0ef0a11	39
vcoubard	1:ebc0e0ef0a11	40	/* Register: AAR_INTENSET */
vcoubard	1:ebc0e0ef0a11	41	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	42
vcoubard	1:ebc0e0ef0a11	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
vcoubard	1:ebc0e0ef0a11	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
vcoubard	1:ebc0e0ef0a11	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
vcoubard	1:ebc0e0ef0a11	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	49
vcoubard	1:ebc0e0ef0a11	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
vcoubard	1:ebc0e0ef0a11	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
vcoubard	1:ebc0e0ef0a11	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
vcoubard	1:ebc0e0ef0a11	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	56
vcoubard	1:ebc0e0ef0a11	57	/* Bit 0 : Enable interrupt on END event. */
vcoubard	1:ebc0e0ef0a11	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
vcoubard	1:ebc0e0ef0a11	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	1:ebc0e0ef0a11	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	63
vcoubard	1:ebc0e0ef0a11	64	/* Register: AAR_INTENCLR */
vcoubard	1:ebc0e0ef0a11	65	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	66
vcoubard	1:ebc0e0ef0a11	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
vcoubard	1:ebc0e0ef0a11	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
vcoubard	1:ebc0e0ef0a11	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
vcoubard	1:ebc0e0ef0a11	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	73
vcoubard	1:ebc0e0ef0a11	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
vcoubard	1:ebc0e0ef0a11	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
vcoubard	1:ebc0e0ef0a11	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
vcoubard	1:ebc0e0ef0a11	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	80
vcoubard	1:ebc0e0ef0a11	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
vcoubard	1:ebc0e0ef0a11	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
vcoubard	1:ebc0e0ef0a11	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	1:ebc0e0ef0a11	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	87
vcoubard	1:ebc0e0ef0a11	88	/* Register: AAR_STATUS */
vcoubard	1:ebc0e0ef0a11	89	/* Description: Resolution status. */
vcoubard	1:ebc0e0ef0a11	90
vcoubard	1:ebc0e0ef0a11	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
vcoubard	1:ebc0e0ef0a11	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	1:ebc0e0ef0a11	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	1:ebc0e0ef0a11	94
vcoubard	1:ebc0e0ef0a11	95	/* Register: AAR_ENABLE */
vcoubard	1:ebc0e0ef0a11	96	/* Description: Enable AAR. */
vcoubard	1:ebc0e0ef0a11	97
vcoubard	1:ebc0e0ef0a11	98	/* Bits 1..0 : Enable AAR. */
vcoubard	1:ebc0e0ef0a11	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
vcoubard	1:ebc0e0ef0a11	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
vcoubard	1:ebc0e0ef0a11	103
vcoubard	1:ebc0e0ef0a11	104	/* Register: AAR_NIRK */
vcoubard	1:ebc0e0ef0a11	105	/* Description: Number of Identity root Keys in the IRK data structure. */
vcoubard	1:ebc0e0ef0a11	106
vcoubard	1:ebc0e0ef0a11	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
vcoubard	1:ebc0e0ef0a11	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
vcoubard	1:ebc0e0ef0a11	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
vcoubard	1:ebc0e0ef0a11	110
vcoubard	1:ebc0e0ef0a11	111	/* Register: AAR_POWER */
vcoubard	1:ebc0e0ef0a11	112	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	113
vcoubard	1:ebc0e0ef0a11	114	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	119
vcoubard	1:ebc0e0ef0a11	120
vcoubard	1:ebc0e0ef0a11	121	/* Peripheral: ADC */
vcoubard	1:ebc0e0ef0a11	122	/* Description: Analog to digital converter. */
vcoubard	1:ebc0e0ef0a11	123
vcoubard	1:ebc0e0ef0a11	124	/* Register: ADC_INTENSET */
vcoubard	1:ebc0e0ef0a11	125	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	126
vcoubard	1:ebc0e0ef0a11	127	/* Bit 0 : Enable interrupt on END event. */
vcoubard	1:ebc0e0ef0a11	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
vcoubard	1:ebc0e0ef0a11	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	1:ebc0e0ef0a11	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	133
vcoubard	1:ebc0e0ef0a11	134	/* Register: ADC_INTENCLR */
vcoubard	1:ebc0e0ef0a11	135	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	136
vcoubard	1:ebc0e0ef0a11	137	/* Bit 0 : Disable interrupt on END event. */
vcoubard	1:ebc0e0ef0a11	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
vcoubard	1:ebc0e0ef0a11	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	1:ebc0e0ef0a11	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	143
vcoubard	1:ebc0e0ef0a11	144	/* Register: ADC_BUSY */
vcoubard	1:ebc0e0ef0a11	145	/* Description: ADC busy register. */
vcoubard	1:ebc0e0ef0a11	146
vcoubard	1:ebc0e0ef0a11	147	/* Bit 0 : ADC busy register. */
vcoubard	1:ebc0e0ef0a11	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
vcoubard	1:ebc0e0ef0a11	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
vcoubard	1:ebc0e0ef0a11	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
vcoubard	1:ebc0e0ef0a11	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
vcoubard	1:ebc0e0ef0a11	152
vcoubard	1:ebc0e0ef0a11	153	/* Register: ADC_ENABLE */
vcoubard	1:ebc0e0ef0a11	154	/* Description: ADC enable. */
vcoubard	1:ebc0e0ef0a11	155
vcoubard	1:ebc0e0ef0a11	156	/* Bits 1..0 : ADC enable. */
vcoubard	1:ebc0e0ef0a11	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
vcoubard	1:ebc0e0ef0a11	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
vcoubard	1:ebc0e0ef0a11	161
vcoubard	1:ebc0e0ef0a11	162	/* Register: ADC_CONFIG */
vcoubard	1:ebc0e0ef0a11	163	/* Description: ADC configuration register. */
vcoubard	1:ebc0e0ef0a11	164
vcoubard	1:ebc0e0ef0a11	165	/* Bits 17..16 : ADC external reference pin selection. */
vcoubard	1:ebc0e0ef0a11	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
vcoubard	1:ebc0e0ef0a11	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
vcoubard	1:ebc0e0ef0a11	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
vcoubard	1:ebc0e0ef0a11	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
vcoubard	1:ebc0e0ef0a11	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
vcoubard	1:ebc0e0ef0a11	171
vcoubard	1:ebc0e0ef0a11	172	/* Bits 15..8 : ADC analog pin selection. */
vcoubard	1:ebc0e0ef0a11	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
vcoubard	1:ebc0e0ef0a11	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	1:ebc0e0ef0a11	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
vcoubard	1:ebc0e0ef0a11	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
vcoubard	1:ebc0e0ef0a11	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
vcoubard	1:ebc0e0ef0a11	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
vcoubard	1:ebc0e0ef0a11	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
vcoubard	1:ebc0e0ef0a11	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
vcoubard	1:ebc0e0ef0a11	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
vcoubard	1:ebc0e0ef0a11	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
vcoubard	1:ebc0e0ef0a11	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
vcoubard	1:ebc0e0ef0a11	184
vcoubard	1:ebc0e0ef0a11	185	/* Bits 6..5 : ADC reference selection. */
vcoubard	1:ebc0e0ef0a11	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
vcoubard	1:ebc0e0ef0a11	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
vcoubard	1:ebc0e0ef0a11	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
vcoubard	1:ebc0e0ef0a11	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
vcoubard	1:ebc0e0ef0a11	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
vcoubard	1:ebc0e0ef0a11	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
vcoubard	1:ebc0e0ef0a11	192
vcoubard	1:ebc0e0ef0a11	193	/* Bits 4..2 : ADC input selection. */
vcoubard	1:ebc0e0ef0a11	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
vcoubard	1:ebc0e0ef0a11	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
vcoubard	1:ebc0e0ef0a11	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
vcoubard	1:ebc0e0ef0a11	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
vcoubard	1:ebc0e0ef0a11	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
vcoubard	1:ebc0e0ef0a11	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
vcoubard	1:ebc0e0ef0a11	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
vcoubard	1:ebc0e0ef0a11	201
vcoubard	1:ebc0e0ef0a11	202	/* Bits 1..0 : ADC resolution. */
vcoubard	1:ebc0e0ef0a11	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
vcoubard	1:ebc0e0ef0a11	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
vcoubard	1:ebc0e0ef0a11	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
vcoubard	1:ebc0e0ef0a11	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
vcoubard	1:ebc0e0ef0a11	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
vcoubard	1:ebc0e0ef0a11	208
vcoubard	1:ebc0e0ef0a11	209	/* Register: ADC_RESULT */
vcoubard	1:ebc0e0ef0a11	210	/* Description: Result of ADC conversion. */
vcoubard	1:ebc0e0ef0a11	211
vcoubard	1:ebc0e0ef0a11	212	/* Bits 9..0 : Result of ADC conversion. */
vcoubard	1:ebc0e0ef0a11	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
vcoubard	1:ebc0e0ef0a11	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
vcoubard	1:ebc0e0ef0a11	215
vcoubard	1:ebc0e0ef0a11	216	/* Register: ADC_POWER */
vcoubard	1:ebc0e0ef0a11	217	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	218
vcoubard	1:ebc0e0ef0a11	219	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	224
vcoubard	1:ebc0e0ef0a11	225
vcoubard	1:ebc0e0ef0a11	226	/* Peripheral: AMLI */
vcoubard	1:ebc0e0ef0a11	227	/* Description: AHB Multi-Layer Interface. */
vcoubard	1:ebc0e0ef0a11	228
vcoubard	1:ebc0e0ef0a11	229	/* Register: AMLI_RAMPRI_CPU0 */
vcoubard	1:ebc0e0ef0a11	230	/* Description: Configurable priority configuration register for CPU0. */
vcoubard	1:ebc0e0ef0a11	231
vcoubard	1:ebc0e0ef0a11	232	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	1:ebc0e0ef0a11	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	243
vcoubard	1:ebc0e0ef0a11	244	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	1:ebc0e0ef0a11	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	255
vcoubard	1:ebc0e0ef0a11	256	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	1:ebc0e0ef0a11	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	267
vcoubard	1:ebc0e0ef0a11	268	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	1:ebc0e0ef0a11	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	279
vcoubard	1:ebc0e0ef0a11	280	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	1:ebc0e0ef0a11	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	291
vcoubard	1:ebc0e0ef0a11	292	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	1:ebc0e0ef0a11	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	303
vcoubard	1:ebc0e0ef0a11	304	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	1:ebc0e0ef0a11	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	315
vcoubard	1:ebc0e0ef0a11	316	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	1:ebc0e0ef0a11	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	327
vcoubard	1:ebc0e0ef0a11	328	/* Register: AMLI_RAMPRI_SPIS1 */
vcoubard	1:ebc0e0ef0a11	329	/* Description: Configurable priority configuration register for SPIS1. */
vcoubard	1:ebc0e0ef0a11	330
vcoubard	1:ebc0e0ef0a11	331	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	1:ebc0e0ef0a11	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	342
vcoubard	1:ebc0e0ef0a11	343	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	1:ebc0e0ef0a11	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	354
vcoubard	1:ebc0e0ef0a11	355	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	1:ebc0e0ef0a11	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	366
vcoubard	1:ebc0e0ef0a11	367	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	1:ebc0e0ef0a11	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	378
vcoubard	1:ebc0e0ef0a11	379	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	1:ebc0e0ef0a11	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	390
vcoubard	1:ebc0e0ef0a11	391	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	1:ebc0e0ef0a11	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	402
vcoubard	1:ebc0e0ef0a11	403	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	1:ebc0e0ef0a11	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	414
vcoubard	1:ebc0e0ef0a11	415	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	1:ebc0e0ef0a11	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	426
vcoubard	1:ebc0e0ef0a11	427	/* Register: AMLI_RAMPRI_RADIO */
vcoubard	1:ebc0e0ef0a11	428	/* Description: Configurable priority configuration register for RADIO. */
vcoubard	1:ebc0e0ef0a11	429
vcoubard	1:ebc0e0ef0a11	430	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	1:ebc0e0ef0a11	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	441
vcoubard	1:ebc0e0ef0a11	442	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	1:ebc0e0ef0a11	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	453
vcoubard	1:ebc0e0ef0a11	454	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	1:ebc0e0ef0a11	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	465
vcoubard	1:ebc0e0ef0a11	466	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	1:ebc0e0ef0a11	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	477
vcoubard	1:ebc0e0ef0a11	478	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	1:ebc0e0ef0a11	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	489
vcoubard	1:ebc0e0ef0a11	490	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	1:ebc0e0ef0a11	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	501
vcoubard	1:ebc0e0ef0a11	502	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	1:ebc0e0ef0a11	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	513
vcoubard	1:ebc0e0ef0a11	514	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	1:ebc0e0ef0a11	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	525
vcoubard	1:ebc0e0ef0a11	526	/* Register: AMLI_RAMPRI_ECB */
vcoubard	1:ebc0e0ef0a11	527	/* Description: Configurable priority configuration register for ECB. */
vcoubard	1:ebc0e0ef0a11	528
vcoubard	1:ebc0e0ef0a11	529	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	1:ebc0e0ef0a11	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	540
vcoubard	1:ebc0e0ef0a11	541	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	1:ebc0e0ef0a11	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	552
vcoubard	1:ebc0e0ef0a11	553	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	1:ebc0e0ef0a11	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	564
vcoubard	1:ebc0e0ef0a11	565	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	1:ebc0e0ef0a11	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	576
vcoubard	1:ebc0e0ef0a11	577	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	1:ebc0e0ef0a11	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	588
vcoubard	1:ebc0e0ef0a11	589	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	1:ebc0e0ef0a11	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	600
vcoubard	1:ebc0e0ef0a11	601	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	1:ebc0e0ef0a11	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	612
vcoubard	1:ebc0e0ef0a11	613	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	1:ebc0e0ef0a11	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	624
vcoubard	1:ebc0e0ef0a11	625	/* Register: AMLI_RAMPRI_CCM */
vcoubard	1:ebc0e0ef0a11	626	/* Description: Configurable priority configuration register for CCM. */
vcoubard	1:ebc0e0ef0a11	627
vcoubard	1:ebc0e0ef0a11	628	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	1:ebc0e0ef0a11	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	639
vcoubard	1:ebc0e0ef0a11	640	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	1:ebc0e0ef0a11	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	651
vcoubard	1:ebc0e0ef0a11	652	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	1:ebc0e0ef0a11	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	663
vcoubard	1:ebc0e0ef0a11	664	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	1:ebc0e0ef0a11	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	675
vcoubard	1:ebc0e0ef0a11	676	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	1:ebc0e0ef0a11	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	687
vcoubard	1:ebc0e0ef0a11	688	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	1:ebc0e0ef0a11	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	699
vcoubard	1:ebc0e0ef0a11	700	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	1:ebc0e0ef0a11	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	711
vcoubard	1:ebc0e0ef0a11	712	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	1:ebc0e0ef0a11	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	723
vcoubard	1:ebc0e0ef0a11	724	/* Register: AMLI_RAMPRI_AAR */
vcoubard	1:ebc0e0ef0a11	725	/* Description: Configurable priority configuration register for AAR. */
vcoubard	1:ebc0e0ef0a11	726
vcoubard	1:ebc0e0ef0a11	727	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	1:ebc0e0ef0a11	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	1:ebc0e0ef0a11	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	738
vcoubard	1:ebc0e0ef0a11	739	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	1:ebc0e0ef0a11	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	1:ebc0e0ef0a11	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	750
vcoubard	1:ebc0e0ef0a11	751	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	1:ebc0e0ef0a11	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	1:ebc0e0ef0a11	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	762
vcoubard	1:ebc0e0ef0a11	763	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	1:ebc0e0ef0a11	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	1:ebc0e0ef0a11	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	774
vcoubard	1:ebc0e0ef0a11	775	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	1:ebc0e0ef0a11	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	1:ebc0e0ef0a11	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	786
vcoubard	1:ebc0e0ef0a11	787	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	1:ebc0e0ef0a11	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	1:ebc0e0ef0a11	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	798
vcoubard	1:ebc0e0ef0a11	799	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	1:ebc0e0ef0a11	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	1:ebc0e0ef0a11	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	810
vcoubard	1:ebc0e0ef0a11	811	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	1:ebc0e0ef0a11	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	1:ebc0e0ef0a11	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	1:ebc0e0ef0a11	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	1:ebc0e0ef0a11	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	1:ebc0e0ef0a11	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	1:ebc0e0ef0a11	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	1:ebc0e0ef0a11	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	1:ebc0e0ef0a11	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	1:ebc0e0ef0a11	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	1:ebc0e0ef0a11	822
vcoubard	1:ebc0e0ef0a11	823
vcoubard	1:ebc0e0ef0a11	824	/* Peripheral: CCM */
vcoubard	1:ebc0e0ef0a11	825	/* Description: AES CCM Mode Encryption. */
vcoubard	1:ebc0e0ef0a11	826
vcoubard	1:ebc0e0ef0a11	827	/* Register: CCM_SHORTS */
vcoubard	1:ebc0e0ef0a11	828	/* Description: Shortcuts for the CCM. */
vcoubard	1:ebc0e0ef0a11	829
vcoubard	1:ebc0e0ef0a11	830	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
vcoubard	1:ebc0e0ef0a11	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
vcoubard	1:ebc0e0ef0a11	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
vcoubard	1:ebc0e0ef0a11	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	834	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	835
vcoubard	1:ebc0e0ef0a11	836	/* Register: CCM_INTENSET */
vcoubard	1:ebc0e0ef0a11	837	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	838
vcoubard	1:ebc0e0ef0a11	839	/* Bit 2 : Enable interrupt on ERROR event. */
vcoubard	1:ebc0e0ef0a11	840	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
vcoubard	1:ebc0e0ef0a11	841	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	1:ebc0e0ef0a11	842	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	843	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	844	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	845
vcoubard	1:ebc0e0ef0a11	846	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
vcoubard	1:ebc0e0ef0a11	847	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
vcoubard	1:ebc0e0ef0a11	848	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
vcoubard	1:ebc0e0ef0a11	849	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	850	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	851	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	852
vcoubard	1:ebc0e0ef0a11	853	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
vcoubard	1:ebc0e0ef0a11	854	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
vcoubard	1:ebc0e0ef0a11	855	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
vcoubard	1:ebc0e0ef0a11	856	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	857	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	858	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	859
vcoubard	1:ebc0e0ef0a11	860	/* Register: CCM_INTENCLR */
vcoubard	1:ebc0e0ef0a11	861	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	862
vcoubard	1:ebc0e0ef0a11	863	/* Bit 2 : Disable interrupt on ERROR event. */
vcoubard	1:ebc0e0ef0a11	864	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
vcoubard	1:ebc0e0ef0a11	865	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	1:ebc0e0ef0a11	866	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	867	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	868	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	869
vcoubard	1:ebc0e0ef0a11	870	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
vcoubard	1:ebc0e0ef0a11	871	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
vcoubard	1:ebc0e0ef0a11	872	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
vcoubard	1:ebc0e0ef0a11	873	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	874	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	875	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	876
vcoubard	1:ebc0e0ef0a11	877	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
vcoubard	1:ebc0e0ef0a11	878	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
vcoubard	1:ebc0e0ef0a11	879	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
vcoubard	1:ebc0e0ef0a11	880	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	881	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	882	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	883
vcoubard	1:ebc0e0ef0a11	884	/* Register: CCM_MICSTATUS */
vcoubard	1:ebc0e0ef0a11	885	/* Description: CCM RX MIC check result. */
vcoubard	1:ebc0e0ef0a11	886
vcoubard	1:ebc0e0ef0a11	887	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
vcoubard	1:ebc0e0ef0a11	888	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
vcoubard	1:ebc0e0ef0a11	889	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
vcoubard	1:ebc0e0ef0a11	890	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
vcoubard	1:ebc0e0ef0a11	891	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
vcoubard	1:ebc0e0ef0a11	892
vcoubard	1:ebc0e0ef0a11	893	/* Register: CCM_ENABLE */
vcoubard	1:ebc0e0ef0a11	894	/* Description: CCM enable. */
vcoubard	1:ebc0e0ef0a11	895
vcoubard	1:ebc0e0ef0a11	896	/* Bits 1..0 : CCM enable. */
vcoubard	1:ebc0e0ef0a11	897	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	898	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	899	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
vcoubard	1:ebc0e0ef0a11	900	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
vcoubard	1:ebc0e0ef0a11	901
vcoubard	1:ebc0e0ef0a11	902	/* Register: CCM_MODE */
vcoubard	1:ebc0e0ef0a11	903	/* Description: Operation mode. */
vcoubard	1:ebc0e0ef0a11	904
vcoubard	1:ebc0e0ef0a11	905	/* Bit 0 : CCM mode operation. */
vcoubard	1:ebc0e0ef0a11	906	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	1:ebc0e0ef0a11	907	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	1:ebc0e0ef0a11	908	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
vcoubard	1:ebc0e0ef0a11	909	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
vcoubard	1:ebc0e0ef0a11	910
vcoubard	1:ebc0e0ef0a11	911	/* Register: CCM_POWER */
vcoubard	1:ebc0e0ef0a11	912	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	913
vcoubard	1:ebc0e0ef0a11	914	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	915	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	916	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	917	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	918	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	919
vcoubard	1:ebc0e0ef0a11	920
vcoubard	1:ebc0e0ef0a11	921	/* Peripheral: CLOCK */
vcoubard	1:ebc0e0ef0a11	922	/* Description: Clock control. */
vcoubard	1:ebc0e0ef0a11	923
vcoubard	1:ebc0e0ef0a11	924	/* Register: CLOCK_INTENSET */
vcoubard	1:ebc0e0ef0a11	925	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	926
vcoubard	1:ebc0e0ef0a11	927	/* Bit 4 : Enable interrupt on CTTO event. */
vcoubard	1:ebc0e0ef0a11	928	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
vcoubard	1:ebc0e0ef0a11	929	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
vcoubard	1:ebc0e0ef0a11	930	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	931	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	932	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	933
vcoubard	1:ebc0e0ef0a11	934	/* Bit 3 : Enable interrupt on DONE event. */
vcoubard	1:ebc0e0ef0a11	935	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
vcoubard	1:ebc0e0ef0a11	936	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
vcoubard	1:ebc0e0ef0a11	937	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	938	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	939	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	940
vcoubard	1:ebc0e0ef0a11	941	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
vcoubard	1:ebc0e0ef0a11	942	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
vcoubard	1:ebc0e0ef0a11	943	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
vcoubard	1:ebc0e0ef0a11	944	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	945	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	946	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	947
vcoubard	1:ebc0e0ef0a11	948	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
vcoubard	1:ebc0e0ef0a11	949	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
vcoubard	1:ebc0e0ef0a11	950	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
vcoubard	1:ebc0e0ef0a11	951	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	952	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	953	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	954
vcoubard	1:ebc0e0ef0a11	955	/* Register: CLOCK_INTENCLR */
vcoubard	1:ebc0e0ef0a11	956	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	957
vcoubard	1:ebc0e0ef0a11	958	/* Bit 4 : Disable interrupt on CTTO event. */
vcoubard	1:ebc0e0ef0a11	959	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
vcoubard	1:ebc0e0ef0a11	960	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
vcoubard	1:ebc0e0ef0a11	961	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	962	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	963	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	964
vcoubard	1:ebc0e0ef0a11	965	/* Bit 3 : Disable interrupt on DONE event. */
vcoubard	1:ebc0e0ef0a11	966	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
vcoubard	1:ebc0e0ef0a11	967	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
vcoubard	1:ebc0e0ef0a11	968	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	969	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	970	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	971
vcoubard	1:ebc0e0ef0a11	972	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
vcoubard	1:ebc0e0ef0a11	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
vcoubard	1:ebc0e0ef0a11	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
vcoubard	1:ebc0e0ef0a11	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	977	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	978
vcoubard	1:ebc0e0ef0a11	979	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
vcoubard	1:ebc0e0ef0a11	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
vcoubard	1:ebc0e0ef0a11	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
vcoubard	1:ebc0e0ef0a11	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	984	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	985
vcoubard	1:ebc0e0ef0a11	986	/* Register: CLOCK_HFCLKRUN */
vcoubard	1:ebc0e0ef0a11	987	/* Description: Task HFCLKSTART trigger status. */
vcoubard	1:ebc0e0ef0a11	988
vcoubard	1:ebc0e0ef0a11	989	/* Bit 0 : Task HFCLKSTART trigger status. */
vcoubard	1:ebc0e0ef0a11	990	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	1:ebc0e0ef0a11	991	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	1:ebc0e0ef0a11	992	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
vcoubard	1:ebc0e0ef0a11	993	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
vcoubard	1:ebc0e0ef0a11	994
vcoubard	1:ebc0e0ef0a11	995	/* Register: CLOCK_HFCLKSTAT */
vcoubard	1:ebc0e0ef0a11	996	/* Description: High frequency clock status. */
vcoubard	1:ebc0e0ef0a11	997
vcoubard	1:ebc0e0ef0a11	998	/* Bit 16 : State for the HFCLK. */
vcoubard	1:ebc0e0ef0a11	999	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
vcoubard	1:ebc0e0ef0a11	1000	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	1:ebc0e0ef0a11	1001	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
vcoubard	1:ebc0e0ef0a11	1002	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
vcoubard	1:ebc0e0ef0a11	1003
vcoubard	1:ebc0e0ef0a11	1004	/* Bit 0 : Active clock source for the HF clock. */
vcoubard	1:ebc0e0ef0a11	1005	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	1:ebc0e0ef0a11	1006	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	1:ebc0e0ef0a11	1007	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
vcoubard	1:ebc0e0ef0a11	1008	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
vcoubard	1:ebc0e0ef0a11	1009
vcoubard	1:ebc0e0ef0a11	1010	/* Register: CLOCK_LFCLKRUN */
vcoubard	1:ebc0e0ef0a11	1011	/* Description: Task LFCLKSTART triggered status. */
vcoubard	1:ebc0e0ef0a11	1012
vcoubard	1:ebc0e0ef0a11	1013	/* Bit 0 : Task LFCLKSTART triggered status. */
vcoubard	1:ebc0e0ef0a11	1014	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	1:ebc0e0ef0a11	1015	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	1:ebc0e0ef0a11	1016	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
vcoubard	1:ebc0e0ef0a11	1017	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
vcoubard	1:ebc0e0ef0a11	1018
vcoubard	1:ebc0e0ef0a11	1019	/* Register: CLOCK_LFCLKSTAT */
vcoubard	1:ebc0e0ef0a11	1020	/* Description: Low frequency clock status. */
vcoubard	1:ebc0e0ef0a11	1021
vcoubard	1:ebc0e0ef0a11	1022	/* Bit 16 : State for the LF clock. */
vcoubard	1:ebc0e0ef0a11	1023	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
vcoubard	1:ebc0e0ef0a11	1024	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	1:ebc0e0ef0a11	1025	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
vcoubard	1:ebc0e0ef0a11	1026	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
vcoubard	1:ebc0e0ef0a11	1027
vcoubard	1:ebc0e0ef0a11	1028	/* Bits 1..0 : Active clock source for the LF clock. */
vcoubard	1:ebc0e0ef0a11	1029	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	1:ebc0e0ef0a11	1030	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	1:ebc0e0ef0a11	1031	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
vcoubard	1:ebc0e0ef0a11	1032	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
vcoubard	1:ebc0e0ef0a11	1033	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
vcoubard	1:ebc0e0ef0a11	1034
vcoubard	1:ebc0e0ef0a11	1035	/* Register: CLOCK_LFCLKSRCCOPY */
vcoubard	1:ebc0e0ef0a11	1036	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
vcoubard	1:ebc0e0ef0a11	1037
vcoubard	1:ebc0e0ef0a11	1038	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
vcoubard	1:ebc0e0ef0a11	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	1:ebc0e0ef0a11	1040	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	1:ebc0e0ef0a11	1041	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
vcoubard	1:ebc0e0ef0a11	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
vcoubard	1:ebc0e0ef0a11	1043	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
vcoubard	1:ebc0e0ef0a11	1044
vcoubard	1:ebc0e0ef0a11	1045	/* Register: CLOCK_LFCLKSRC */
vcoubard	1:ebc0e0ef0a11	1046	/* Description: Clock source for the LFCLK clock. */
vcoubard	1:ebc0e0ef0a11	1047
vcoubard	1:ebc0e0ef0a11	1048	/* Bits 1..0 : Clock source. */
vcoubard	1:ebc0e0ef0a11	1049	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	1:ebc0e0ef0a11	1050	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	1:ebc0e0ef0a11	1051	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
vcoubard	1:ebc0e0ef0a11	1052	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
vcoubard	1:ebc0e0ef0a11	1053	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
vcoubard	1:ebc0e0ef0a11	1054
vcoubard	1:ebc0e0ef0a11	1055	/* Register: CLOCK_CTIV */
vcoubard	1:ebc0e0ef0a11	1056	/* Description: Calibration timer interval. */
vcoubard	1:ebc0e0ef0a11	1057
vcoubard	1:ebc0e0ef0a11	1058	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
vcoubard	1:ebc0e0ef0a11	1059	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
vcoubard	1:ebc0e0ef0a11	1060	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
vcoubard	1:ebc0e0ef0a11	1061
vcoubard	1:ebc0e0ef0a11	1062	/* Register: CLOCK_XTALFREQ */
vcoubard	1:ebc0e0ef0a11	1063	/* Description: Crystal frequency. */
vcoubard	1:ebc0e0ef0a11	1064
vcoubard	1:ebc0e0ef0a11	1065	/* Bits 7..0 : External Xtal frequency selection. */
vcoubard	1:ebc0e0ef0a11	1066	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
vcoubard	1:ebc0e0ef0a11	1067	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
vcoubard	1:ebc0e0ef0a11	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
vcoubard	1:ebc0e0ef0a11	1069	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
vcoubard	1:ebc0e0ef0a11	1070
vcoubard	1:ebc0e0ef0a11	1071
vcoubard	1:ebc0e0ef0a11	1072	/* Peripheral: ECB */
vcoubard	1:ebc0e0ef0a11	1073	/* Description: AES ECB Mode Encryption. */
vcoubard	1:ebc0e0ef0a11	1074
vcoubard	1:ebc0e0ef0a11	1075	/* Register: ECB_INTENSET */
vcoubard	1:ebc0e0ef0a11	1076	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	1077
vcoubard	1:ebc0e0ef0a11	1078	/* Bit 1 : Enable interrupt on ERRORECB event. */
vcoubard	1:ebc0e0ef0a11	1079	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
vcoubard	1:ebc0e0ef0a11	1080	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
vcoubard	1:ebc0e0ef0a11	1081	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	1082	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	1083	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	1084
vcoubard	1:ebc0e0ef0a11	1085	/* Bit 0 : Enable interrupt on ENDECB event. */
vcoubard	1:ebc0e0ef0a11	1086	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
vcoubard	1:ebc0e0ef0a11	1087	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
vcoubard	1:ebc0e0ef0a11	1088	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	1089	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	1090	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	1091
vcoubard	1:ebc0e0ef0a11	1092	/* Register: ECB_INTENCLR */
vcoubard	1:ebc0e0ef0a11	1093	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	1094
vcoubard	1:ebc0e0ef0a11	1095	/* Bit 1 : Disable interrupt on ERRORECB event. */
vcoubard	1:ebc0e0ef0a11	1096	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
vcoubard	1:ebc0e0ef0a11	1097	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
vcoubard	1:ebc0e0ef0a11	1098	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	1099	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	1100	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	1101
vcoubard	1:ebc0e0ef0a11	1102	/* Bit 0 : Disable interrupt on ENDECB event. */
vcoubard	1:ebc0e0ef0a11	1103	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
vcoubard	1:ebc0e0ef0a11	1104	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
vcoubard	1:ebc0e0ef0a11	1105	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	1106	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	1107	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	1108
vcoubard	1:ebc0e0ef0a11	1109	/* Register: ECB_POWER */
vcoubard	1:ebc0e0ef0a11	1110	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	1111
vcoubard	1:ebc0e0ef0a11	1112	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	1113	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	1114	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	1115	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	1116	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	1117
vcoubard	1:ebc0e0ef0a11	1118
vcoubard	1:ebc0e0ef0a11	1119	/* Peripheral: FICR */
vcoubard	1:ebc0e0ef0a11	1120	/* Description: Factory Information Configuration. */
vcoubard	1:ebc0e0ef0a11	1121
vcoubard	1:ebc0e0ef0a11	1122	/* Register: FICR_PPFC */
vcoubard	1:ebc0e0ef0a11	1123	/* Description: Pre-programmed factory code present. */
vcoubard	1:ebc0e0ef0a11	1124
vcoubard	1:ebc0e0ef0a11	1125	/* Bits 7..0 : Pre-programmed factory code present. */
vcoubard	1:ebc0e0ef0a11	1126	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
vcoubard	1:ebc0e0ef0a11	1127	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
vcoubard	1:ebc0e0ef0a11	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
vcoubard	1:ebc0e0ef0a11	1129	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
vcoubard	1:ebc0e0ef0a11	1130
vcoubard	1:ebc0e0ef0a11	1131	/* Register: FICR_CONFIGID */
vcoubard	1:ebc0e0ef0a11	1132	/* Description: Configuration identifier. */
vcoubard	1:ebc0e0ef0a11	1133
vcoubard	1:ebc0e0ef0a11	1134	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
vcoubard	1:ebc0e0ef0a11	1135	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
vcoubard	1:ebc0e0ef0a11	1136	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
vcoubard	1:ebc0e0ef0a11	1137
vcoubard	1:ebc0e0ef0a11	1138	/* Bits 15..0 : Hardware Identification Number. */
vcoubard	1:ebc0e0ef0a11	1139	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
vcoubard	1:ebc0e0ef0a11	1140	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
vcoubard	1:ebc0e0ef0a11	1141
vcoubard	1:ebc0e0ef0a11	1142	/* Register: FICR_DEVICEADDRTYPE */
vcoubard	1:ebc0e0ef0a11	1143	/* Description: Device address type. */
vcoubard	1:ebc0e0ef0a11	1144
vcoubard	1:ebc0e0ef0a11	1145	/* Bit 0 : Device address type. */
vcoubard	1:ebc0e0ef0a11	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
vcoubard	1:ebc0e0ef0a11	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
vcoubard	1:ebc0e0ef0a11	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
vcoubard	1:ebc0e0ef0a11	1149	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
vcoubard	1:ebc0e0ef0a11	1150
vcoubard	1:ebc0e0ef0a11	1151	/* Register: FICR_OVERRIDEEN */
vcoubard	1:ebc0e0ef0a11	1152	/* Description: Radio calibration override enable. */
vcoubard	1:ebc0e0ef0a11	1153
vcoubard	1:ebc0e0ef0a11	1154	/* Bit 3 : Override default values for BLE_1Mbit mode. */
vcoubard	1:ebc0e0ef0a11	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
vcoubard	1:ebc0e0ef0a11	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
vcoubard	1:ebc0e0ef0a11	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
vcoubard	1:ebc0e0ef0a11	1158	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
vcoubard	1:ebc0e0ef0a11	1159
vcoubard	1:ebc0e0ef0a11	1160	/* Bit 0 : Override default values for NRF_1Mbit mode. */
vcoubard	1:ebc0e0ef0a11	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
vcoubard	1:ebc0e0ef0a11	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
vcoubard	1:ebc0e0ef0a11	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
vcoubard	1:ebc0e0ef0a11	1164	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
vcoubard	1:ebc0e0ef0a11	1165
vcoubard	1:ebc0e0ef0a11	1166
vcoubard	1:ebc0e0ef0a11	1167	/* Peripheral: GPIO */
vcoubard	1:ebc0e0ef0a11	1168	/* Description: General purpose input and output. */
vcoubard	1:ebc0e0ef0a11	1169
vcoubard	1:ebc0e0ef0a11	1170	/* Register: GPIO_OUT */
vcoubard	1:ebc0e0ef0a11	1171	/* Description: Write GPIO port. */
vcoubard	1:ebc0e0ef0a11	1172
vcoubard	1:ebc0e0ef0a11	1173	/* Bit 31 : Pin 31. */
vcoubard	1:ebc0e0ef0a11	1174	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	1175	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	1176	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1177	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1178
vcoubard	1:ebc0e0ef0a11	1179	/* Bit 30 : Pin 30. */
vcoubard	1:ebc0e0ef0a11	1180	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	1181	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	1182	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1183	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1184
vcoubard	1:ebc0e0ef0a11	1185	/* Bit 29 : Pin 29. */
vcoubard	1:ebc0e0ef0a11	1186	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	1187	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	1188	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1189	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1190
vcoubard	1:ebc0e0ef0a11	1191	/* Bit 28 : Pin 28. */
vcoubard	1:ebc0e0ef0a11	1192	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	1193	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	1194	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1195	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1196
vcoubard	1:ebc0e0ef0a11	1197	/* Bit 27 : Pin 27. */
vcoubard	1:ebc0e0ef0a11	1198	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	1199	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	1200	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1201	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1202
vcoubard	1:ebc0e0ef0a11	1203	/* Bit 26 : Pin 26. */
vcoubard	1:ebc0e0ef0a11	1204	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	1205	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	1206	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1207	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1208
vcoubard	1:ebc0e0ef0a11	1209	/* Bit 25 : Pin 25. */
vcoubard	1:ebc0e0ef0a11	1210	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	1211	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	1212	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1213	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1214
vcoubard	1:ebc0e0ef0a11	1215	/* Bit 24 : Pin 24. */
vcoubard	1:ebc0e0ef0a11	1216	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	1217	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	1218	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1219	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1220
vcoubard	1:ebc0e0ef0a11	1221	/* Bit 23 : Pin 23. */
vcoubard	1:ebc0e0ef0a11	1222	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	1223	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	1224	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1225	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1226
vcoubard	1:ebc0e0ef0a11	1227	/* Bit 22 : Pin 22. */
vcoubard	1:ebc0e0ef0a11	1228	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	1229	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	1230	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1231	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1232
vcoubard	1:ebc0e0ef0a11	1233	/* Bit 21 : Pin 21. */
vcoubard	1:ebc0e0ef0a11	1234	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	1235	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	1236	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1237	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1238
vcoubard	1:ebc0e0ef0a11	1239	/* Bit 20 : Pin 20. */
vcoubard	1:ebc0e0ef0a11	1240	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	1241	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	1242	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1243	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1244
vcoubard	1:ebc0e0ef0a11	1245	/* Bit 19 : Pin 19. */
vcoubard	1:ebc0e0ef0a11	1246	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	1247	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	1248	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1249	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1250
vcoubard	1:ebc0e0ef0a11	1251	/* Bit 18 : Pin 18. */
vcoubard	1:ebc0e0ef0a11	1252	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	1253	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	1254	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1255	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1256
vcoubard	1:ebc0e0ef0a11	1257	/* Bit 17 : Pin 17. */
vcoubard	1:ebc0e0ef0a11	1258	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	1259	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	1260	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1261	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1262
vcoubard	1:ebc0e0ef0a11	1263	/* Bit 16 : Pin 16. */
vcoubard	1:ebc0e0ef0a11	1264	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	1265	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	1266	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1267	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1268
vcoubard	1:ebc0e0ef0a11	1269	/* Bit 15 : Pin 15. */
vcoubard	1:ebc0e0ef0a11	1270	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	1271	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	1272	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1273	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1274
vcoubard	1:ebc0e0ef0a11	1275	/* Bit 14 : Pin 14. */
vcoubard	1:ebc0e0ef0a11	1276	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	1277	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	1278	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1279	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1280
vcoubard	1:ebc0e0ef0a11	1281	/* Bit 13 : Pin 13. */
vcoubard	1:ebc0e0ef0a11	1282	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	1283	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	1284	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1285	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1286
vcoubard	1:ebc0e0ef0a11	1287	/* Bit 12 : Pin 12. */
vcoubard	1:ebc0e0ef0a11	1288	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	1289	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	1290	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1291	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1292
vcoubard	1:ebc0e0ef0a11	1293	/* Bit 11 : Pin 11. */
vcoubard	1:ebc0e0ef0a11	1294	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	1295	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	1296	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1297	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1298
vcoubard	1:ebc0e0ef0a11	1299	/* Bit 10 : Pin 10. */
vcoubard	1:ebc0e0ef0a11	1300	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	1301	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	1302	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1303	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1304
vcoubard	1:ebc0e0ef0a11	1305	/* Bit 9 : Pin 9. */
vcoubard	1:ebc0e0ef0a11	1306	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	1307	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	1308	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1309	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1310
vcoubard	1:ebc0e0ef0a11	1311	/* Bit 8 : Pin 8. */
vcoubard	1:ebc0e0ef0a11	1312	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	1313	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	1314	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1315	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1316
vcoubard	1:ebc0e0ef0a11	1317	/* Bit 7 : Pin 7. */
vcoubard	1:ebc0e0ef0a11	1318	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	1319	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	1320	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1321	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1322
vcoubard	1:ebc0e0ef0a11	1323	/* Bit 6 : Pin 6. */
vcoubard	1:ebc0e0ef0a11	1324	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	1325	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	1326	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1327	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1328
vcoubard	1:ebc0e0ef0a11	1329	/* Bit 5 : Pin 5. */
vcoubard	1:ebc0e0ef0a11	1330	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	1331	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	1332	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1333	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1334
vcoubard	1:ebc0e0ef0a11	1335	/* Bit 4 : Pin 4. */
vcoubard	1:ebc0e0ef0a11	1336	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	1337	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	1338	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1339	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1340
vcoubard	1:ebc0e0ef0a11	1341	/* Bit 3 : Pin 3. */
vcoubard	1:ebc0e0ef0a11	1342	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	1343	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	1344	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1345	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1346
vcoubard	1:ebc0e0ef0a11	1347	/* Bit 2 : Pin 2. */
vcoubard	1:ebc0e0ef0a11	1348	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	1349	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	1350	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1351	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1352
vcoubard	1:ebc0e0ef0a11	1353	/* Bit 1 : Pin 1. */
vcoubard	1:ebc0e0ef0a11	1354	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	1355	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	1356	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1357	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1358
vcoubard	1:ebc0e0ef0a11	1359	/* Bit 0 : Pin 0. */
vcoubard	1:ebc0e0ef0a11	1360	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	1361	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	1362	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1363	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1364
vcoubard	1:ebc0e0ef0a11	1365	/* Register: GPIO_OUTSET */
vcoubard	1:ebc0e0ef0a11	1366	/* Description: Set individual bits in GPIO port. */
vcoubard	1:ebc0e0ef0a11	1367
vcoubard	1:ebc0e0ef0a11	1368	/* Bit 31 : Pin 31. */
vcoubard	1:ebc0e0ef0a11	1369	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	1370	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	1371	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1372	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1373	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1374
vcoubard	1:ebc0e0ef0a11	1375	/* Bit 30 : Pin 30. */
vcoubard	1:ebc0e0ef0a11	1376	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	1377	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	1378	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1379	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1380	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1381
vcoubard	1:ebc0e0ef0a11	1382	/* Bit 29 : Pin 29. */
vcoubard	1:ebc0e0ef0a11	1383	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	1384	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	1385	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1386	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1387	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1388
vcoubard	1:ebc0e0ef0a11	1389	/* Bit 28 : Pin 28. */
vcoubard	1:ebc0e0ef0a11	1390	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	1391	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	1392	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1393	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1394	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1395
vcoubard	1:ebc0e0ef0a11	1396	/* Bit 27 : Pin 27. */
vcoubard	1:ebc0e0ef0a11	1397	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	1398	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	1399	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1400	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1401	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1402
vcoubard	1:ebc0e0ef0a11	1403	/* Bit 26 : Pin 26. */
vcoubard	1:ebc0e0ef0a11	1404	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	1405	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	1406	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1407	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1408	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1409
vcoubard	1:ebc0e0ef0a11	1410	/* Bit 25 : Pin 25. */
vcoubard	1:ebc0e0ef0a11	1411	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	1412	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	1413	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1414	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1415	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1416
vcoubard	1:ebc0e0ef0a11	1417	/* Bit 24 : Pin 24. */
vcoubard	1:ebc0e0ef0a11	1418	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	1419	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	1420	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1421	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1422	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1423
vcoubard	1:ebc0e0ef0a11	1424	/* Bit 23 : Pin 23. */
vcoubard	1:ebc0e0ef0a11	1425	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	1426	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	1427	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1428	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1429	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1430
vcoubard	1:ebc0e0ef0a11	1431	/* Bit 22 : Pin 22. */
vcoubard	1:ebc0e0ef0a11	1432	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	1433	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	1434	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1435	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1436	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1437
vcoubard	1:ebc0e0ef0a11	1438	/* Bit 21 : Pin 21. */
vcoubard	1:ebc0e0ef0a11	1439	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	1440	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	1441	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1442	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1443	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1444
vcoubard	1:ebc0e0ef0a11	1445	/* Bit 20 : Pin 20. */
vcoubard	1:ebc0e0ef0a11	1446	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	1447	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	1448	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1449	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1450	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1451
vcoubard	1:ebc0e0ef0a11	1452	/* Bit 19 : Pin 19. */
vcoubard	1:ebc0e0ef0a11	1453	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	1454	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	1455	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1456	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1457	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1458
vcoubard	1:ebc0e0ef0a11	1459	/* Bit 18 : Pin 18. */
vcoubard	1:ebc0e0ef0a11	1460	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	1461	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	1462	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1463	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1464	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1465
vcoubard	1:ebc0e0ef0a11	1466	/* Bit 17 : Pin 17. */
vcoubard	1:ebc0e0ef0a11	1467	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	1468	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	1469	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1470	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1471	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1472
vcoubard	1:ebc0e0ef0a11	1473	/* Bit 16 : Pin 16. */
vcoubard	1:ebc0e0ef0a11	1474	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	1475	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	1476	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1477	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1478	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1479
vcoubard	1:ebc0e0ef0a11	1480	/* Bit 15 : Pin 15. */
vcoubard	1:ebc0e0ef0a11	1481	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	1482	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	1483	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1484	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1485	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1486
vcoubard	1:ebc0e0ef0a11	1487	/* Bit 14 : Pin 14. */
vcoubard	1:ebc0e0ef0a11	1488	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	1489	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	1490	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1491	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1492	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1493
vcoubard	1:ebc0e0ef0a11	1494	/* Bit 13 : Pin 13. */
vcoubard	1:ebc0e0ef0a11	1495	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	1496	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	1497	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1498	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1499	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1500
vcoubard	1:ebc0e0ef0a11	1501	/* Bit 12 : Pin 12. */
vcoubard	1:ebc0e0ef0a11	1502	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	1503	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	1504	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1505	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1506	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1507
vcoubard	1:ebc0e0ef0a11	1508	/* Bit 11 : Pin 11. */
vcoubard	1:ebc0e0ef0a11	1509	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	1510	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	1511	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1512	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1513	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1514
vcoubard	1:ebc0e0ef0a11	1515	/* Bit 10 : Pin 10. */
vcoubard	1:ebc0e0ef0a11	1516	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	1517	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	1518	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1519	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1520	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1521
vcoubard	1:ebc0e0ef0a11	1522	/* Bit 9 : Pin 9. */
vcoubard	1:ebc0e0ef0a11	1523	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	1524	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	1525	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1526	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1527	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1528
vcoubard	1:ebc0e0ef0a11	1529	/* Bit 8 : Pin 8. */
vcoubard	1:ebc0e0ef0a11	1530	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	1531	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	1532	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1533	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1534	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1535
vcoubard	1:ebc0e0ef0a11	1536	/* Bit 7 : Pin 7. */
vcoubard	1:ebc0e0ef0a11	1537	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	1538	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	1539	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1540	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1541	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1542
vcoubard	1:ebc0e0ef0a11	1543	/* Bit 6 : Pin 6. */
vcoubard	1:ebc0e0ef0a11	1544	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	1545	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	1546	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1547	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1548	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1549
vcoubard	1:ebc0e0ef0a11	1550	/* Bit 5 : Pin 5. */
vcoubard	1:ebc0e0ef0a11	1551	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	1552	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	1553	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1554	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1555	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1556
vcoubard	1:ebc0e0ef0a11	1557	/* Bit 4 : Pin 4. */
vcoubard	1:ebc0e0ef0a11	1558	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	1559	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	1560	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1561	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1562	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1563
vcoubard	1:ebc0e0ef0a11	1564	/* Bit 3 : Pin 3. */
vcoubard	1:ebc0e0ef0a11	1565	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	1566	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	1567	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1568	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1569	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1570
vcoubard	1:ebc0e0ef0a11	1571	/* Bit 2 : Pin 2. */
vcoubard	1:ebc0e0ef0a11	1572	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	1573	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	1574	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1575	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1576	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1577
vcoubard	1:ebc0e0ef0a11	1578	/* Bit 1 : Pin 1. */
vcoubard	1:ebc0e0ef0a11	1579	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	1580	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	1581	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1582	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1583	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1584
vcoubard	1:ebc0e0ef0a11	1585	/* Bit 0 : Pin 0. */
vcoubard	1:ebc0e0ef0a11	1586	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	1587	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	1588	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1589	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1590	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
vcoubard	1:ebc0e0ef0a11	1591
vcoubard	1:ebc0e0ef0a11	1592	/* Register: GPIO_OUTCLR */
vcoubard	1:ebc0e0ef0a11	1593	/* Description: Clear individual bits in GPIO port. */
vcoubard	1:ebc0e0ef0a11	1594
vcoubard	1:ebc0e0ef0a11	1595	/* Bit 31 : Pin 31. */
vcoubard	1:ebc0e0ef0a11	1596	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	1597	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	1598	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1599	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1600	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1601
vcoubard	1:ebc0e0ef0a11	1602	/* Bit 30 : Pin 30. */
vcoubard	1:ebc0e0ef0a11	1603	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	1604	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	1605	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1606	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1607	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1608
vcoubard	1:ebc0e0ef0a11	1609	/* Bit 29 : Pin 29. */
vcoubard	1:ebc0e0ef0a11	1610	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	1611	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	1612	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1613	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1614	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1615
vcoubard	1:ebc0e0ef0a11	1616	/* Bit 28 : Pin 28. */
vcoubard	1:ebc0e0ef0a11	1617	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	1618	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	1619	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1620	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1621	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1622
vcoubard	1:ebc0e0ef0a11	1623	/* Bit 27 : Pin 27. */
vcoubard	1:ebc0e0ef0a11	1624	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	1625	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	1626	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1627	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1628	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1629
vcoubard	1:ebc0e0ef0a11	1630	/* Bit 26 : Pin 26. */
vcoubard	1:ebc0e0ef0a11	1631	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	1632	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	1633	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1634	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1635	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1636
vcoubard	1:ebc0e0ef0a11	1637	/* Bit 25 : Pin 25. */
vcoubard	1:ebc0e0ef0a11	1638	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	1639	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	1640	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1641	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1642	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1643
vcoubard	1:ebc0e0ef0a11	1644	/* Bit 24 : Pin 24. */
vcoubard	1:ebc0e0ef0a11	1645	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	1646	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	1647	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1648	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1649	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1650
vcoubard	1:ebc0e0ef0a11	1651	/* Bit 23 : Pin 23. */
vcoubard	1:ebc0e0ef0a11	1652	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	1653	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	1654	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1655	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1656	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1657
vcoubard	1:ebc0e0ef0a11	1658	/* Bit 22 : Pin 22. */
vcoubard	1:ebc0e0ef0a11	1659	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	1660	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	1661	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1662	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1663	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1664
vcoubard	1:ebc0e0ef0a11	1665	/* Bit 21 : Pin 21. */
vcoubard	1:ebc0e0ef0a11	1666	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	1667	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	1668	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1669	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1670	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1671
vcoubard	1:ebc0e0ef0a11	1672	/* Bit 20 : Pin 20. */
vcoubard	1:ebc0e0ef0a11	1673	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	1674	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	1675	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1676	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1677	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1678
vcoubard	1:ebc0e0ef0a11	1679	/* Bit 19 : Pin 19. */
vcoubard	1:ebc0e0ef0a11	1680	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	1681	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	1682	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1683	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1684	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1685
vcoubard	1:ebc0e0ef0a11	1686	/* Bit 18 : Pin 18. */
vcoubard	1:ebc0e0ef0a11	1687	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	1688	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	1689	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1690	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1691	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1692
vcoubard	1:ebc0e0ef0a11	1693	/* Bit 17 : Pin 17. */
vcoubard	1:ebc0e0ef0a11	1694	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	1695	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	1696	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1697	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1698	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1699
vcoubard	1:ebc0e0ef0a11	1700	/* Bit 16 : Pin 16. */
vcoubard	1:ebc0e0ef0a11	1701	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	1702	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	1703	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1704	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1705	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1706
vcoubard	1:ebc0e0ef0a11	1707	/* Bit 15 : Pin 15. */
vcoubard	1:ebc0e0ef0a11	1708	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	1709	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	1710	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1711	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1712	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1713
vcoubard	1:ebc0e0ef0a11	1714	/* Bit 14 : Pin 14. */
vcoubard	1:ebc0e0ef0a11	1715	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	1716	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	1717	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1718	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1719	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1720
vcoubard	1:ebc0e0ef0a11	1721	/* Bit 13 : Pin 13. */
vcoubard	1:ebc0e0ef0a11	1722	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	1723	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	1724	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1725	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1726	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1727
vcoubard	1:ebc0e0ef0a11	1728	/* Bit 12 : Pin 12. */
vcoubard	1:ebc0e0ef0a11	1729	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	1730	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	1731	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1732	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1733	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1734
vcoubard	1:ebc0e0ef0a11	1735	/* Bit 11 : Pin 11. */
vcoubard	1:ebc0e0ef0a11	1736	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	1737	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	1738	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1739	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1740	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1741
vcoubard	1:ebc0e0ef0a11	1742	/* Bit 10 : Pin 10. */
vcoubard	1:ebc0e0ef0a11	1743	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	1744	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	1745	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1746	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1747	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1748
vcoubard	1:ebc0e0ef0a11	1749	/* Bit 9 : Pin 9. */
vcoubard	1:ebc0e0ef0a11	1750	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	1751	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	1752	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1753	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1754	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1755
vcoubard	1:ebc0e0ef0a11	1756	/* Bit 8 : Pin 8. */
vcoubard	1:ebc0e0ef0a11	1757	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	1758	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	1759	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1760	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1761	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1762
vcoubard	1:ebc0e0ef0a11	1763	/* Bit 7 : Pin 7. */
vcoubard	1:ebc0e0ef0a11	1764	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	1765	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	1766	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1767	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1768	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1769
vcoubard	1:ebc0e0ef0a11	1770	/* Bit 6 : Pin 6. */
vcoubard	1:ebc0e0ef0a11	1771	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	1772	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	1773	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1774	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1775	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1776
vcoubard	1:ebc0e0ef0a11	1777	/* Bit 5 : Pin 5. */
vcoubard	1:ebc0e0ef0a11	1778	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	1779	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	1780	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1781	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1782	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1783
vcoubard	1:ebc0e0ef0a11	1784	/* Bit 4 : Pin 4. */
vcoubard	1:ebc0e0ef0a11	1785	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	1786	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	1787	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1788	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1789	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1790
vcoubard	1:ebc0e0ef0a11	1791	/* Bit 3 : Pin 3. */
vcoubard	1:ebc0e0ef0a11	1792	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	1793	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	1794	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1795	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1796	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1797
vcoubard	1:ebc0e0ef0a11	1798	/* Bit 2 : Pin 2. */
vcoubard	1:ebc0e0ef0a11	1799	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	1800	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	1801	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1802	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1803	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1804
vcoubard	1:ebc0e0ef0a11	1805	/* Bit 1 : Pin 1. */
vcoubard	1:ebc0e0ef0a11	1806	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	1807	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	1808	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1809	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1810	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1811
vcoubard	1:ebc0e0ef0a11	1812	/* Bit 0 : Pin 0. */
vcoubard	1:ebc0e0ef0a11	1813	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	1814	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	1815	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	1:ebc0e0ef0a11	1816	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	1:ebc0e0ef0a11	1817	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
vcoubard	1:ebc0e0ef0a11	1818
vcoubard	1:ebc0e0ef0a11	1819	/* Register: GPIO_IN */
vcoubard	1:ebc0e0ef0a11	1820	/* Description: Read GPIO port. */
vcoubard	1:ebc0e0ef0a11	1821
vcoubard	1:ebc0e0ef0a11	1822	/* Bit 31 : Pin 31. */
vcoubard	1:ebc0e0ef0a11	1823	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	1824	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	1825	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1826	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1827
vcoubard	1:ebc0e0ef0a11	1828	/* Bit 30 : Pin 30. */
vcoubard	1:ebc0e0ef0a11	1829	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	1830	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	1831	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1832	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1833
vcoubard	1:ebc0e0ef0a11	1834	/* Bit 29 : Pin 29. */
vcoubard	1:ebc0e0ef0a11	1835	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	1836	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	1837	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1838	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1839
vcoubard	1:ebc0e0ef0a11	1840	/* Bit 28 : Pin 28. */
vcoubard	1:ebc0e0ef0a11	1841	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	1842	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	1843	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1844	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1845
vcoubard	1:ebc0e0ef0a11	1846	/* Bit 27 : Pin 27. */
vcoubard	1:ebc0e0ef0a11	1847	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	1848	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	1849	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1850	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1851
vcoubard	1:ebc0e0ef0a11	1852	/* Bit 26 : Pin 26. */
vcoubard	1:ebc0e0ef0a11	1853	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	1854	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	1855	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1856	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1857
vcoubard	1:ebc0e0ef0a11	1858	/* Bit 25 : Pin 25. */
vcoubard	1:ebc0e0ef0a11	1859	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	1860	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	1861	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1862	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1863
vcoubard	1:ebc0e0ef0a11	1864	/* Bit 24 : Pin 24. */
vcoubard	1:ebc0e0ef0a11	1865	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	1866	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	1867	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1868	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1869
vcoubard	1:ebc0e0ef0a11	1870	/* Bit 23 : Pin 23. */
vcoubard	1:ebc0e0ef0a11	1871	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	1872	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	1873	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1874	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1875
vcoubard	1:ebc0e0ef0a11	1876	/* Bit 22 : Pin 22. */
vcoubard	1:ebc0e0ef0a11	1877	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	1878	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	1879	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1880	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1881
vcoubard	1:ebc0e0ef0a11	1882	/* Bit 21 : Pin 21. */
vcoubard	1:ebc0e0ef0a11	1883	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	1884	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	1885	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1886	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1887
vcoubard	1:ebc0e0ef0a11	1888	/* Bit 20 : Pin 20. */
vcoubard	1:ebc0e0ef0a11	1889	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	1890	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	1891	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1892	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1893
vcoubard	1:ebc0e0ef0a11	1894	/* Bit 19 : Pin 19. */
vcoubard	1:ebc0e0ef0a11	1895	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	1896	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	1897	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1898	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1899
vcoubard	1:ebc0e0ef0a11	1900	/* Bit 18 : Pin 18. */
vcoubard	1:ebc0e0ef0a11	1901	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	1902	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	1903	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1904	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1905
vcoubard	1:ebc0e0ef0a11	1906	/* Bit 17 : Pin 17. */
vcoubard	1:ebc0e0ef0a11	1907	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	1908	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	1909	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1910	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1911
vcoubard	1:ebc0e0ef0a11	1912	/* Bit 16 : Pin 16. */
vcoubard	1:ebc0e0ef0a11	1913	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	1914	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	1915	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1916	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1917
vcoubard	1:ebc0e0ef0a11	1918	/* Bit 15 : Pin 15. */
vcoubard	1:ebc0e0ef0a11	1919	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	1920	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	1921	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1922	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1923
vcoubard	1:ebc0e0ef0a11	1924	/* Bit 14 : Pin 14. */
vcoubard	1:ebc0e0ef0a11	1925	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	1926	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	1927	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1928	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1929
vcoubard	1:ebc0e0ef0a11	1930	/* Bit 13 : Pin 13. */
vcoubard	1:ebc0e0ef0a11	1931	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	1932	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	1933	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1934	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1935
vcoubard	1:ebc0e0ef0a11	1936	/* Bit 12 : Pin 12. */
vcoubard	1:ebc0e0ef0a11	1937	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	1938	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	1939	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1940	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1941
vcoubard	1:ebc0e0ef0a11	1942	/* Bit 11 : Pin 11. */
vcoubard	1:ebc0e0ef0a11	1943	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	1944	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	1945	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1946	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1947
vcoubard	1:ebc0e0ef0a11	1948	/* Bit 10 : Pin 10. */
vcoubard	1:ebc0e0ef0a11	1949	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	1950	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	1951	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1952	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1953
vcoubard	1:ebc0e0ef0a11	1954	/* Bit 9 : Pin 9. */
vcoubard	1:ebc0e0ef0a11	1955	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	1956	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	1957	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1958	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1959
vcoubard	1:ebc0e0ef0a11	1960	/* Bit 8 : Pin 8. */
vcoubard	1:ebc0e0ef0a11	1961	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	1962	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	1963	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1964	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1965
vcoubard	1:ebc0e0ef0a11	1966	/* Bit 7 : Pin 7. */
vcoubard	1:ebc0e0ef0a11	1967	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	1968	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	1969	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1970	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1971
vcoubard	1:ebc0e0ef0a11	1972	/* Bit 6 : Pin 6. */
vcoubard	1:ebc0e0ef0a11	1973	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	1974	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	1975	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1976	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1977
vcoubard	1:ebc0e0ef0a11	1978	/* Bit 5 : Pin 5. */
vcoubard	1:ebc0e0ef0a11	1979	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	1980	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	1981	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1982	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1983
vcoubard	1:ebc0e0ef0a11	1984	/* Bit 4 : Pin 4. */
vcoubard	1:ebc0e0ef0a11	1985	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	1986	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	1987	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1988	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1989
vcoubard	1:ebc0e0ef0a11	1990	/* Bit 3 : Pin 3. */
vcoubard	1:ebc0e0ef0a11	1991	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	1992	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	1993	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	1994	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	1995
vcoubard	1:ebc0e0ef0a11	1996	/* Bit 2 : Pin 2. */
vcoubard	1:ebc0e0ef0a11	1997	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	1998	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	1999	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	2000	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	2001
vcoubard	1:ebc0e0ef0a11	2002	/* Bit 1 : Pin 1. */
vcoubard	1:ebc0e0ef0a11	2003	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	2004	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	2005	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	2006	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	2007
vcoubard	1:ebc0e0ef0a11	2008	/* Bit 0 : Pin 0. */
vcoubard	1:ebc0e0ef0a11	2009	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	2010	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	2011	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
vcoubard	1:ebc0e0ef0a11	2012	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
vcoubard	1:ebc0e0ef0a11	2013
vcoubard	1:ebc0e0ef0a11	2014	/* Register: GPIO_DIR */
vcoubard	1:ebc0e0ef0a11	2015	/* Description: Direction of GPIO pins. */
vcoubard	1:ebc0e0ef0a11	2016
vcoubard	1:ebc0e0ef0a11	2017	/* Bit 31 : Pin 31. */
vcoubard	1:ebc0e0ef0a11	2018	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	2019	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	2020	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2021	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2022
vcoubard	1:ebc0e0ef0a11	2023	/* Bit 30 : Pin 30. */
vcoubard	1:ebc0e0ef0a11	2024	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	2025	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	2026	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2027	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2028
vcoubard	1:ebc0e0ef0a11	2029	/* Bit 29 : Pin 29. */
vcoubard	1:ebc0e0ef0a11	2030	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	2031	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	2032	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2033	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2034
vcoubard	1:ebc0e0ef0a11	2035	/* Bit 28 : Pin 28. */
vcoubard	1:ebc0e0ef0a11	2036	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	2037	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	2038	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2039	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2040
vcoubard	1:ebc0e0ef0a11	2041	/* Bit 27 : Pin 27. */
vcoubard	1:ebc0e0ef0a11	2042	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	2043	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	2044	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2045	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2046
vcoubard	1:ebc0e0ef0a11	2047	/* Bit 26 : Pin 26. */
vcoubard	1:ebc0e0ef0a11	2048	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	2049	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	2050	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2051	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2052
vcoubard	1:ebc0e0ef0a11	2053	/* Bit 25 : Pin 25. */
vcoubard	1:ebc0e0ef0a11	2054	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	2055	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	2056	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2057	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2058
vcoubard	1:ebc0e0ef0a11	2059	/* Bit 24 : Pin 24. */
vcoubard	1:ebc0e0ef0a11	2060	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	2061	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	2062	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2063	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2064
vcoubard	1:ebc0e0ef0a11	2065	/* Bit 23 : Pin 23. */
vcoubard	1:ebc0e0ef0a11	2066	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	2067	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	2068	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2069	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2070
vcoubard	1:ebc0e0ef0a11	2071	/* Bit 22 : Pin 22. */
vcoubard	1:ebc0e0ef0a11	2072	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	2073	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	2074	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2075	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2076
vcoubard	1:ebc0e0ef0a11	2077	/* Bit 21 : Pin 21. */
vcoubard	1:ebc0e0ef0a11	2078	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	2079	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	2080	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2081	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2082
vcoubard	1:ebc0e0ef0a11	2083	/* Bit 20 : Pin 20. */
vcoubard	1:ebc0e0ef0a11	2084	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	2085	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	2086	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2087	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2088
vcoubard	1:ebc0e0ef0a11	2089	/* Bit 19 : Pin 19. */
vcoubard	1:ebc0e0ef0a11	2090	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	2091	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	2092	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2093	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2094
vcoubard	1:ebc0e0ef0a11	2095	/* Bit 18 : Pin 18. */
vcoubard	1:ebc0e0ef0a11	2096	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	2097	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	2098	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2099	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2100
vcoubard	1:ebc0e0ef0a11	2101	/* Bit 17 : Pin 17. */
vcoubard	1:ebc0e0ef0a11	2102	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	2103	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	2104	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2105	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2106
vcoubard	1:ebc0e0ef0a11	2107	/* Bit 16 : Pin 16. */
vcoubard	1:ebc0e0ef0a11	2108	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	2109	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	2110	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2111	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2112
vcoubard	1:ebc0e0ef0a11	2113	/* Bit 15 : Pin 15. */
vcoubard	1:ebc0e0ef0a11	2114	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	2115	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	2116	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2117	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2118
vcoubard	1:ebc0e0ef0a11	2119	/* Bit 14 : Pin 14. */
vcoubard	1:ebc0e0ef0a11	2120	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	2121	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	2122	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2123	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2124
vcoubard	1:ebc0e0ef0a11	2125	/* Bit 13 : Pin 13. */
vcoubard	1:ebc0e0ef0a11	2126	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	2127	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	2128	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2129	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2130
vcoubard	1:ebc0e0ef0a11	2131	/* Bit 12 : Pin 12. */
vcoubard	1:ebc0e0ef0a11	2132	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	2133	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	2134	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2135	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2136
vcoubard	1:ebc0e0ef0a11	2137	/* Bit 11 : Pin 11. */
vcoubard	1:ebc0e0ef0a11	2138	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	2139	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	2140	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2141	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2142
vcoubard	1:ebc0e0ef0a11	2143	/* Bit 10 : Pin 10. */
vcoubard	1:ebc0e0ef0a11	2144	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	2145	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	2146	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2147	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2148
vcoubard	1:ebc0e0ef0a11	2149	/* Bit 9 : Pin 9. */
vcoubard	1:ebc0e0ef0a11	2150	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	2151	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	2152	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2153	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2154
vcoubard	1:ebc0e0ef0a11	2155	/* Bit 8 : Pin 8. */
vcoubard	1:ebc0e0ef0a11	2156	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	2157	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	2158	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2159	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2160
vcoubard	1:ebc0e0ef0a11	2161	/* Bit 7 : Pin 7. */
vcoubard	1:ebc0e0ef0a11	2162	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	2163	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	2164	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2165	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2166
vcoubard	1:ebc0e0ef0a11	2167	/* Bit 6 : Pin 6. */
vcoubard	1:ebc0e0ef0a11	2168	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	2169	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	2170	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2171	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2172
vcoubard	1:ebc0e0ef0a11	2173	/* Bit 5 : Pin 5. */
vcoubard	1:ebc0e0ef0a11	2174	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	2175	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	2176	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2177	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2178
vcoubard	1:ebc0e0ef0a11	2179	/* Bit 4 : Pin 4. */
vcoubard	1:ebc0e0ef0a11	2180	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	2181	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	2182	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2183	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2184
vcoubard	1:ebc0e0ef0a11	2185	/* Bit 3 : Pin 3. */
vcoubard	1:ebc0e0ef0a11	2186	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	2187	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	2188	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2189	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2190
vcoubard	1:ebc0e0ef0a11	2191	/* Bit 2 : Pin 2. */
vcoubard	1:ebc0e0ef0a11	2192	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	2193	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	2194	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2195	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2196
vcoubard	1:ebc0e0ef0a11	2197	/* Bit 1 : Pin 1. */
vcoubard	1:ebc0e0ef0a11	2198	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	2199	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	2200	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2201	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2202
vcoubard	1:ebc0e0ef0a11	2203	/* Bit 0 : Pin 0. */
vcoubard	1:ebc0e0ef0a11	2204	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	2205	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	2206	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2207	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2208
vcoubard	1:ebc0e0ef0a11	2209	/* Register: GPIO_DIRSET */
vcoubard	1:ebc0e0ef0a11	2210	/* Description: DIR set register. */
vcoubard	1:ebc0e0ef0a11	2211
vcoubard	1:ebc0e0ef0a11	2212	/* Bit 31 : Set as output pin 31. */
vcoubard	1:ebc0e0ef0a11	2213	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	2214	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	2215	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2216	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2217	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2218
vcoubard	1:ebc0e0ef0a11	2219	/* Bit 30 : Set as output pin 30. */
vcoubard	1:ebc0e0ef0a11	2220	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	2221	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	2222	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2223	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2224	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2225
vcoubard	1:ebc0e0ef0a11	2226	/* Bit 29 : Set as output pin 29. */
vcoubard	1:ebc0e0ef0a11	2227	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	2228	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	2229	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2230	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2231	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2232
vcoubard	1:ebc0e0ef0a11	2233	/* Bit 28 : Set as output pin 28. */
vcoubard	1:ebc0e0ef0a11	2234	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	2235	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	2236	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2237	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2238	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2239
vcoubard	1:ebc0e0ef0a11	2240	/* Bit 27 : Set as output pin 27. */
vcoubard	1:ebc0e0ef0a11	2241	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	2242	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	2243	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2244	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2245	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2246
vcoubard	1:ebc0e0ef0a11	2247	/* Bit 26 : Set as output pin 26. */
vcoubard	1:ebc0e0ef0a11	2248	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	2249	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	2250	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2251	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2252	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2253
vcoubard	1:ebc0e0ef0a11	2254	/* Bit 25 : Set as output pin 25. */
vcoubard	1:ebc0e0ef0a11	2255	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	2256	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	2257	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2258	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2259	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2260
vcoubard	1:ebc0e0ef0a11	2261	/* Bit 24 : Set as output pin 24. */
vcoubard	1:ebc0e0ef0a11	2262	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	2263	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	2264	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2265	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2266	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2267
vcoubard	1:ebc0e0ef0a11	2268	/* Bit 23 : Set as output pin 23. */
vcoubard	1:ebc0e0ef0a11	2269	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	2270	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	2271	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2272	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2273	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2274
vcoubard	1:ebc0e0ef0a11	2275	/* Bit 22 : Set as output pin 22. */
vcoubard	1:ebc0e0ef0a11	2276	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	2277	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	2278	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2279	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2280	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2281
vcoubard	1:ebc0e0ef0a11	2282	/* Bit 21 : Set as output pin 21. */
vcoubard	1:ebc0e0ef0a11	2283	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	2284	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	2285	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2286	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2287	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2288
vcoubard	1:ebc0e0ef0a11	2289	/* Bit 20 : Set as output pin 20. */
vcoubard	1:ebc0e0ef0a11	2290	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	2291	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	2292	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2293	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2294	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2295
vcoubard	1:ebc0e0ef0a11	2296	/* Bit 19 : Set as output pin 19. */
vcoubard	1:ebc0e0ef0a11	2297	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	2298	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	2299	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2300	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2301	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2302
vcoubard	1:ebc0e0ef0a11	2303	/* Bit 18 : Set as output pin 18. */
vcoubard	1:ebc0e0ef0a11	2304	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	2305	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	2306	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2307	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2308	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2309
vcoubard	1:ebc0e0ef0a11	2310	/* Bit 17 : Set as output pin 17. */
vcoubard	1:ebc0e0ef0a11	2311	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	2312	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	2313	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2314	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2315	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2316
vcoubard	1:ebc0e0ef0a11	2317	/* Bit 16 : Set as output pin 16. */
vcoubard	1:ebc0e0ef0a11	2318	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	2319	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	2320	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2321	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2322	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2323
vcoubard	1:ebc0e0ef0a11	2324	/* Bit 15 : Set as output pin 15. */
vcoubard	1:ebc0e0ef0a11	2325	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	2326	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	2327	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2328	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2329	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2330
vcoubard	1:ebc0e0ef0a11	2331	/* Bit 14 : Set as output pin 14. */
vcoubard	1:ebc0e0ef0a11	2332	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	2333	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	2334	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2335	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2336	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2337
vcoubard	1:ebc0e0ef0a11	2338	/* Bit 13 : Set as output pin 13. */
vcoubard	1:ebc0e0ef0a11	2339	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	2340	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	2341	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2342	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2343	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2344
vcoubard	1:ebc0e0ef0a11	2345	/* Bit 12 : Set as output pin 12. */
vcoubard	1:ebc0e0ef0a11	2346	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	2347	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	2348	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2349	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2350	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2351
vcoubard	1:ebc0e0ef0a11	2352	/* Bit 11 : Set as output pin 11. */
vcoubard	1:ebc0e0ef0a11	2353	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	2354	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	2355	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2356	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2357	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2358
vcoubard	1:ebc0e0ef0a11	2359	/* Bit 10 : Set as output pin 10. */
vcoubard	1:ebc0e0ef0a11	2360	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	2361	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	2362	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2363	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2364	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2365
vcoubard	1:ebc0e0ef0a11	2366	/* Bit 9 : Set as output pin 9. */
vcoubard	1:ebc0e0ef0a11	2367	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	2368	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	2369	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2370	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2371	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2372
vcoubard	1:ebc0e0ef0a11	2373	/* Bit 8 : Set as output pin 8. */
vcoubard	1:ebc0e0ef0a11	2374	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	2375	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	2376	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2377	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2378	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2379
vcoubard	1:ebc0e0ef0a11	2380	/* Bit 7 : Set as output pin 7. */
vcoubard	1:ebc0e0ef0a11	2381	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	2382	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	2383	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2384	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2385	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2386
vcoubard	1:ebc0e0ef0a11	2387	/* Bit 6 : Set as output pin 6. */
vcoubard	1:ebc0e0ef0a11	2388	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	2389	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	2390	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2391	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2392	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2393
vcoubard	1:ebc0e0ef0a11	2394	/* Bit 5 : Set as output pin 5. */
vcoubard	1:ebc0e0ef0a11	2395	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	2396	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	2397	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2398	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2399	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2400
vcoubard	1:ebc0e0ef0a11	2401	/* Bit 4 : Set as output pin 4. */
vcoubard	1:ebc0e0ef0a11	2402	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	2403	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	2404	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2405	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2406	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2407
vcoubard	1:ebc0e0ef0a11	2408	/* Bit 3 : Set as output pin 3. */
vcoubard	1:ebc0e0ef0a11	2409	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	2410	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	2411	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2412	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2413	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2414
vcoubard	1:ebc0e0ef0a11	2415	/* Bit 2 : Set as output pin 2. */
vcoubard	1:ebc0e0ef0a11	2416	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	2417	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	2418	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2419	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2420	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2421
vcoubard	1:ebc0e0ef0a11	2422	/* Bit 1 : Set as output pin 1. */
vcoubard	1:ebc0e0ef0a11	2423	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	2424	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	2425	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2426	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2427	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2428
vcoubard	1:ebc0e0ef0a11	2429	/* Bit 0 : Set as output pin 0. */
vcoubard	1:ebc0e0ef0a11	2430	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	2431	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	2432	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2433	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2434	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
vcoubard	1:ebc0e0ef0a11	2435
vcoubard	1:ebc0e0ef0a11	2436	/* Register: GPIO_DIRCLR */
vcoubard	1:ebc0e0ef0a11	2437	/* Description: DIR clear register. */
vcoubard	1:ebc0e0ef0a11	2438
vcoubard	1:ebc0e0ef0a11	2439	/* Bit 31 : Set as input pin 31. */
vcoubard	1:ebc0e0ef0a11	2440	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	2441	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	1:ebc0e0ef0a11	2442	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2443	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2444	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2445
vcoubard	1:ebc0e0ef0a11	2446	/* Bit 30 : Set as input pin 30. */
vcoubard	1:ebc0e0ef0a11	2447	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	2448	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	1:ebc0e0ef0a11	2449	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2450	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2451	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2452
vcoubard	1:ebc0e0ef0a11	2453	/* Bit 29 : Set as input pin 29. */
vcoubard	1:ebc0e0ef0a11	2454	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	2455	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	1:ebc0e0ef0a11	2456	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2457	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2458	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2459
vcoubard	1:ebc0e0ef0a11	2460	/* Bit 28 : Set as input pin 28. */
vcoubard	1:ebc0e0ef0a11	2461	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	2462	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	1:ebc0e0ef0a11	2463	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2464	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2465	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2466
vcoubard	1:ebc0e0ef0a11	2467	/* Bit 27 : Set as input pin 27. */
vcoubard	1:ebc0e0ef0a11	2468	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	2469	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	1:ebc0e0ef0a11	2470	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2471	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2472	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2473
vcoubard	1:ebc0e0ef0a11	2474	/* Bit 26 : Set as input pin 26. */
vcoubard	1:ebc0e0ef0a11	2475	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	2476	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	1:ebc0e0ef0a11	2477	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2478	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2479	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2480
vcoubard	1:ebc0e0ef0a11	2481	/* Bit 25 : Set as input pin 25. */
vcoubard	1:ebc0e0ef0a11	2482	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	2483	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	1:ebc0e0ef0a11	2484	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2485	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2486	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2487
vcoubard	1:ebc0e0ef0a11	2488	/* Bit 24 : Set as input pin 24. */
vcoubard	1:ebc0e0ef0a11	2489	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	2490	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	1:ebc0e0ef0a11	2491	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2492	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2493	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2494
vcoubard	1:ebc0e0ef0a11	2495	/* Bit 23 : Set as input pin 23. */
vcoubard	1:ebc0e0ef0a11	2496	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	2497	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	1:ebc0e0ef0a11	2498	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2499	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2500	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2501
vcoubard	1:ebc0e0ef0a11	2502	/* Bit 22 : Set as input pin 22. */
vcoubard	1:ebc0e0ef0a11	2503	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	2504	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	1:ebc0e0ef0a11	2505	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2506	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2507	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2508
vcoubard	1:ebc0e0ef0a11	2509	/* Bit 21 : Set as input pin 21. */
vcoubard	1:ebc0e0ef0a11	2510	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	2511	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	1:ebc0e0ef0a11	2512	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2513	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2514	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2515
vcoubard	1:ebc0e0ef0a11	2516	/* Bit 20 : Set as input pin 20. */
vcoubard	1:ebc0e0ef0a11	2517	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	2518	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	1:ebc0e0ef0a11	2519	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2520	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2521	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2522
vcoubard	1:ebc0e0ef0a11	2523	/* Bit 19 : Set as input pin 19. */
vcoubard	1:ebc0e0ef0a11	2524	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	2525	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	1:ebc0e0ef0a11	2526	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2527	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2528	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2529
vcoubard	1:ebc0e0ef0a11	2530	/* Bit 18 : Set as input pin 18. */
vcoubard	1:ebc0e0ef0a11	2531	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	2532	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	1:ebc0e0ef0a11	2533	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2534	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2535	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2536
vcoubard	1:ebc0e0ef0a11	2537	/* Bit 17 : Set as input pin 17. */
vcoubard	1:ebc0e0ef0a11	2538	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	2539	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	1:ebc0e0ef0a11	2540	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2541	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2542	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2543
vcoubard	1:ebc0e0ef0a11	2544	/* Bit 16 : Set as input pin 16. */
vcoubard	1:ebc0e0ef0a11	2545	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	2546	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	1:ebc0e0ef0a11	2547	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2548	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2549	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2550
vcoubard	1:ebc0e0ef0a11	2551	/* Bit 15 : Set as input pin 15. */
vcoubard	1:ebc0e0ef0a11	2552	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	2553	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	1:ebc0e0ef0a11	2554	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2555	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2556	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2557
vcoubard	1:ebc0e0ef0a11	2558	/* Bit 14 : Set as input pin 14. */
vcoubard	1:ebc0e0ef0a11	2559	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	2560	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	1:ebc0e0ef0a11	2561	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2562	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2563	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2564
vcoubard	1:ebc0e0ef0a11	2565	/* Bit 13 : Set as input pin 13. */
vcoubard	1:ebc0e0ef0a11	2566	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	2567	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	1:ebc0e0ef0a11	2568	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2569	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2570	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2571
vcoubard	1:ebc0e0ef0a11	2572	/* Bit 12 : Set as input pin 12. */
vcoubard	1:ebc0e0ef0a11	2573	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	2574	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	1:ebc0e0ef0a11	2575	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2576	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2577	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2578
vcoubard	1:ebc0e0ef0a11	2579	/* Bit 11 : Set as input pin 11. */
vcoubard	1:ebc0e0ef0a11	2580	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	2581	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	1:ebc0e0ef0a11	2582	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2583	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2584	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2585
vcoubard	1:ebc0e0ef0a11	2586	/* Bit 10 : Set as input pin 10. */
vcoubard	1:ebc0e0ef0a11	2587	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	2588	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	1:ebc0e0ef0a11	2589	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2590	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2591	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2592
vcoubard	1:ebc0e0ef0a11	2593	/* Bit 9 : Set as input pin 9. */
vcoubard	1:ebc0e0ef0a11	2594	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	2595	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	1:ebc0e0ef0a11	2596	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2597	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2598	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2599
vcoubard	1:ebc0e0ef0a11	2600	/* Bit 8 : Set as input pin 8. */
vcoubard	1:ebc0e0ef0a11	2601	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	2602	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	1:ebc0e0ef0a11	2603	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2604	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2605	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2606
vcoubard	1:ebc0e0ef0a11	2607	/* Bit 7 : Set as input pin 7. */
vcoubard	1:ebc0e0ef0a11	2608	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	2609	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	1:ebc0e0ef0a11	2610	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2611	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2612	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2613
vcoubard	1:ebc0e0ef0a11	2614	/* Bit 6 : Set as input pin 6. */
vcoubard	1:ebc0e0ef0a11	2615	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	2616	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	1:ebc0e0ef0a11	2617	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2618	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2619	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2620
vcoubard	1:ebc0e0ef0a11	2621	/* Bit 5 : Set as input pin 5. */
vcoubard	1:ebc0e0ef0a11	2622	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	2623	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	1:ebc0e0ef0a11	2624	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2625	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2626	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2627
vcoubard	1:ebc0e0ef0a11	2628	/* Bit 4 : Set as input pin 4. */
vcoubard	1:ebc0e0ef0a11	2629	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	2630	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	1:ebc0e0ef0a11	2631	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2632	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2633	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2634
vcoubard	1:ebc0e0ef0a11	2635	/* Bit 3 : Set as input pin 3. */
vcoubard	1:ebc0e0ef0a11	2636	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	2637	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	1:ebc0e0ef0a11	2638	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2639	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2640	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2641
vcoubard	1:ebc0e0ef0a11	2642	/* Bit 2 : Set as input pin 2. */
vcoubard	1:ebc0e0ef0a11	2643	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	2644	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	1:ebc0e0ef0a11	2645	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2646	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2647	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2648
vcoubard	1:ebc0e0ef0a11	2649	/* Bit 1 : Set as input pin 1. */
vcoubard	1:ebc0e0ef0a11	2650	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	2651	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	1:ebc0e0ef0a11	2652	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2653	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2654	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2655
vcoubard	1:ebc0e0ef0a11	2656	/* Bit 0 : Set as input pin 0. */
vcoubard	1:ebc0e0ef0a11	2657	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	2658	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	1:ebc0e0ef0a11	2659	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	1:ebc0e0ef0a11	2660	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	1:ebc0e0ef0a11	2661	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
vcoubard	1:ebc0e0ef0a11	2662
vcoubard	1:ebc0e0ef0a11	2663	/* Register: GPIO_PIN_CNF */
vcoubard	1:ebc0e0ef0a11	2664	/* Description: Configuration of GPIO pins. */
vcoubard	1:ebc0e0ef0a11	2665
vcoubard	1:ebc0e0ef0a11	2666	/* Bits 17..16 : Pin sensing mechanism. */
vcoubard	1:ebc0e0ef0a11	2667	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
vcoubard	1:ebc0e0ef0a11	2668	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
vcoubard	1:ebc0e0ef0a11	2669	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	2670	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
vcoubard	1:ebc0e0ef0a11	2671	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
vcoubard	1:ebc0e0ef0a11	2672
vcoubard	1:ebc0e0ef0a11	2673	/* Bits 10..8 : Drive configuration. */
vcoubard	1:ebc0e0ef0a11	2674	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
vcoubard	1:ebc0e0ef0a11	2675	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
vcoubard	1:ebc0e0ef0a11	2676	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
vcoubard	1:ebc0e0ef0a11	2677	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
vcoubard	1:ebc0e0ef0a11	2678	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
vcoubard	1:ebc0e0ef0a11	2679	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
vcoubard	1:ebc0e0ef0a11	2680	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
vcoubard	1:ebc0e0ef0a11	2681	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
vcoubard	1:ebc0e0ef0a11	2682	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
vcoubard	1:ebc0e0ef0a11	2683	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
vcoubard	1:ebc0e0ef0a11	2684
vcoubard	1:ebc0e0ef0a11	2685	/* Bits 3..2 : Pull-up or -down configuration. */
vcoubard	1:ebc0e0ef0a11	2686	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
vcoubard	1:ebc0e0ef0a11	2687	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
vcoubard	1:ebc0e0ef0a11	2688	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
vcoubard	1:ebc0e0ef0a11	2689	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
vcoubard	1:ebc0e0ef0a11	2690	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
vcoubard	1:ebc0e0ef0a11	2691
vcoubard	1:ebc0e0ef0a11	2692	/* Bit 1 : Connect or disconnect input path. */
vcoubard	1:ebc0e0ef0a11	2693	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
vcoubard	1:ebc0e0ef0a11	2694	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
vcoubard	1:ebc0e0ef0a11	2695	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
vcoubard	1:ebc0e0ef0a11	2696	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
vcoubard	1:ebc0e0ef0a11	2697
vcoubard	1:ebc0e0ef0a11	2698	/* Bit 0 : Pin direction. */
vcoubard	1:ebc0e0ef0a11	2699	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
vcoubard	1:ebc0e0ef0a11	2700	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
vcoubard	1:ebc0e0ef0a11	2701	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
vcoubard	1:ebc0e0ef0a11	2702	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
vcoubard	1:ebc0e0ef0a11	2703
vcoubard	1:ebc0e0ef0a11	2704
vcoubard	1:ebc0e0ef0a11	2705	/* Peripheral: GPIOTE */
vcoubard	1:ebc0e0ef0a11	2706	/* Description: GPIO tasks and events. */
vcoubard	1:ebc0e0ef0a11	2707
vcoubard	1:ebc0e0ef0a11	2708	/* Register: GPIOTE_INTENSET */
vcoubard	1:ebc0e0ef0a11	2709	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	2710
vcoubard	1:ebc0e0ef0a11	2711	/* Bit 31 : Enable interrupt on PORT event. */
vcoubard	1:ebc0e0ef0a11	2712	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
vcoubard	1:ebc0e0ef0a11	2713	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
vcoubard	1:ebc0e0ef0a11	2714	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2715	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2716	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2717
vcoubard	1:ebc0e0ef0a11	2718	/* Bit 3 : Enable interrupt on IN[3] event. */
vcoubard	1:ebc0e0ef0a11	2719	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
vcoubard	1:ebc0e0ef0a11	2720	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
vcoubard	1:ebc0e0ef0a11	2721	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2722	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2723	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2724
vcoubard	1:ebc0e0ef0a11	2725	/* Bit 2 : Enable interrupt on IN[2] event. */
vcoubard	1:ebc0e0ef0a11	2726	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
vcoubard	1:ebc0e0ef0a11	2727	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
vcoubard	1:ebc0e0ef0a11	2728	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2729	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2730	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2731
vcoubard	1:ebc0e0ef0a11	2732	/* Bit 1 : Enable interrupt on IN[1] event. */
vcoubard	1:ebc0e0ef0a11	2733	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
vcoubard	1:ebc0e0ef0a11	2734	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
vcoubard	1:ebc0e0ef0a11	2735	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2736	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2737	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2738
vcoubard	1:ebc0e0ef0a11	2739	/* Bit 0 : Enable interrupt on IN[0] event. */
vcoubard	1:ebc0e0ef0a11	2740	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
vcoubard	1:ebc0e0ef0a11	2741	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
vcoubard	1:ebc0e0ef0a11	2742	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2743	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2744	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2745
vcoubard	1:ebc0e0ef0a11	2746	/* Register: GPIOTE_INTENCLR */
vcoubard	1:ebc0e0ef0a11	2747	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	2748
vcoubard	1:ebc0e0ef0a11	2749	/* Bit 31 : Disable interrupt on PORT event. */
vcoubard	1:ebc0e0ef0a11	2750	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
vcoubard	1:ebc0e0ef0a11	2751	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
vcoubard	1:ebc0e0ef0a11	2752	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2753	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2754	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2755
vcoubard	1:ebc0e0ef0a11	2756	/* Bit 3 : Disable interrupt on IN[3] event. */
vcoubard	1:ebc0e0ef0a11	2757	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
vcoubard	1:ebc0e0ef0a11	2758	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
vcoubard	1:ebc0e0ef0a11	2759	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2760	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2761	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2762
vcoubard	1:ebc0e0ef0a11	2763	/* Bit 2 : Disable interrupt on IN[2] event. */
vcoubard	1:ebc0e0ef0a11	2764	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
vcoubard	1:ebc0e0ef0a11	2765	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
vcoubard	1:ebc0e0ef0a11	2766	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2767	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2768	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2769
vcoubard	1:ebc0e0ef0a11	2770	/* Bit 1 : Disable interrupt on IN[1] event. */
vcoubard	1:ebc0e0ef0a11	2771	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
vcoubard	1:ebc0e0ef0a11	2772	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
vcoubard	1:ebc0e0ef0a11	2773	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2774	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2775	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2776
vcoubard	1:ebc0e0ef0a11	2777	/* Bit 0 : Disable interrupt on IN[0] event. */
vcoubard	1:ebc0e0ef0a11	2778	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
vcoubard	1:ebc0e0ef0a11	2779	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
vcoubard	1:ebc0e0ef0a11	2780	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2781	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2782	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2783
vcoubard	1:ebc0e0ef0a11	2784	/* Register: GPIOTE_CONFIG */
vcoubard	1:ebc0e0ef0a11	2785	/* Description: Channel configuration registers. */
vcoubard	1:ebc0e0ef0a11	2786
vcoubard	1:ebc0e0ef0a11	2787	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
vcoubard	1:ebc0e0ef0a11	2788	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
vcoubard	1:ebc0e0ef0a11	2789	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
vcoubard	1:ebc0e0ef0a11	2790	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
vcoubard	1:ebc0e0ef0a11	2791	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
vcoubard	1:ebc0e0ef0a11	2792
vcoubard	1:ebc0e0ef0a11	2793	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
vcoubard	1:ebc0e0ef0a11	2794	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
vcoubard	1:ebc0e0ef0a11	2795	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
vcoubard	1:ebc0e0ef0a11	2796	#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /!< No task or event. /
vcoubard	1:ebc0e0ef0a11	2797	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
vcoubard	1:ebc0e0ef0a11	2798	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
vcoubard	1:ebc0e0ef0a11	2799	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
vcoubard	1:ebc0e0ef0a11	2800
vcoubard	1:ebc0e0ef0a11	2801	/* Bits 12..8 : Pin select. */
vcoubard	1:ebc0e0ef0a11	2802	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
vcoubard	1:ebc0e0ef0a11	2803	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	1:ebc0e0ef0a11	2804
vcoubard	1:ebc0e0ef0a11	2805	/* Bits 1..0 : Mode */
vcoubard	1:ebc0e0ef0a11	2806	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	1:ebc0e0ef0a11	2807	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	1:ebc0e0ef0a11	2808	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	2809	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
vcoubard	1:ebc0e0ef0a11	2810	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
vcoubard	1:ebc0e0ef0a11	2811
vcoubard	1:ebc0e0ef0a11	2812	/* Register: GPIOTE_POWER */
vcoubard	1:ebc0e0ef0a11	2813	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	2814
vcoubard	1:ebc0e0ef0a11	2815	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	2816	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	2817	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	2818	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	2819	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	2820
vcoubard	1:ebc0e0ef0a11	2821
vcoubard	1:ebc0e0ef0a11	2822	/* Peripheral: LPCOMP */
vcoubard	1:ebc0e0ef0a11	2823	/* Description: Low power comparator. */
vcoubard	1:ebc0e0ef0a11	2824
vcoubard	1:ebc0e0ef0a11	2825	/* Register: LPCOMP_SHORTS */
vcoubard	1:ebc0e0ef0a11	2826	/* Description: Shortcuts for the LPCOMP. */
vcoubard	1:ebc0e0ef0a11	2827
vcoubard	1:ebc0e0ef0a11	2828	/* Bit 4 : Shortcut between CROSS event and STOP task. */
vcoubard	1:ebc0e0ef0a11	2829	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
vcoubard	1:ebc0e0ef0a11	2830	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
vcoubard	1:ebc0e0ef0a11	2831	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	2832	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	2833
vcoubard	1:ebc0e0ef0a11	2834	/* Bit 3 : Shortcut between UP event and STOP task. */
vcoubard	1:ebc0e0ef0a11	2835	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
vcoubard	1:ebc0e0ef0a11	2836	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
vcoubard	1:ebc0e0ef0a11	2837	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	2838	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	2839
vcoubard	1:ebc0e0ef0a11	2840	/* Bit 2 : Shortcut between DOWN event and STOP task. */
vcoubard	1:ebc0e0ef0a11	2841	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
vcoubard	1:ebc0e0ef0a11	2842	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
vcoubard	1:ebc0e0ef0a11	2843	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	2844	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	2845
vcoubard	1:ebc0e0ef0a11	2846	/* Bit 1 : Shortcut between RADY event and STOP task. */
vcoubard	1:ebc0e0ef0a11	2847	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
vcoubard	1:ebc0e0ef0a11	2848	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
vcoubard	1:ebc0e0ef0a11	2849	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	2850	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	2851
vcoubard	1:ebc0e0ef0a11	2852	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
vcoubard	1:ebc0e0ef0a11	2853	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
vcoubard	1:ebc0e0ef0a11	2854	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
vcoubard	1:ebc0e0ef0a11	2855	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	2856	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	2857
vcoubard	1:ebc0e0ef0a11	2858	/* Register: LPCOMP_INTENSET */
vcoubard	1:ebc0e0ef0a11	2859	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	2860
vcoubard	1:ebc0e0ef0a11	2861	/* Bit 3 : Enable interrupt on CROSS event. */
vcoubard	1:ebc0e0ef0a11	2862	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
vcoubard	1:ebc0e0ef0a11	2863	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
vcoubard	1:ebc0e0ef0a11	2864	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2865	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2866	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2867
vcoubard	1:ebc0e0ef0a11	2868	/* Bit 2 : Enable interrupt on UP event. */
vcoubard	1:ebc0e0ef0a11	2869	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
vcoubard	1:ebc0e0ef0a11	2870	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
vcoubard	1:ebc0e0ef0a11	2871	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2872	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2873	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2874
vcoubard	1:ebc0e0ef0a11	2875	/* Bit 1 : Enable interrupt on DOWN event. */
vcoubard	1:ebc0e0ef0a11	2876	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
vcoubard	1:ebc0e0ef0a11	2877	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
vcoubard	1:ebc0e0ef0a11	2878	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2879	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2880	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2881
vcoubard	1:ebc0e0ef0a11	2882	/* Bit 0 : Enable interrupt on READY event. */
vcoubard	1:ebc0e0ef0a11	2883	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	1:ebc0e0ef0a11	2884	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	1:ebc0e0ef0a11	2885	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2886	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2887	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2888
vcoubard	1:ebc0e0ef0a11	2889	/* Register: LPCOMP_INTENCLR */
vcoubard	1:ebc0e0ef0a11	2890	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	2891
vcoubard	1:ebc0e0ef0a11	2892	/* Bit 3 : Disable interrupt on CROSS event. */
vcoubard	1:ebc0e0ef0a11	2893	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
vcoubard	1:ebc0e0ef0a11	2894	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
vcoubard	1:ebc0e0ef0a11	2895	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2896	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2897	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2898
vcoubard	1:ebc0e0ef0a11	2899	/* Bit 2 : Disable interrupt on UP event. */
vcoubard	1:ebc0e0ef0a11	2900	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
vcoubard	1:ebc0e0ef0a11	2901	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
vcoubard	1:ebc0e0ef0a11	2902	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2903	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2904	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2905
vcoubard	1:ebc0e0ef0a11	2906	/* Bit 1 : Disable interrupt on DOWN event. */
vcoubard	1:ebc0e0ef0a11	2907	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
vcoubard	1:ebc0e0ef0a11	2908	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
vcoubard	1:ebc0e0ef0a11	2909	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2910	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2911	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2912
vcoubard	1:ebc0e0ef0a11	2913	/* Bit 0 : Disable interrupt on READY event. */
vcoubard	1:ebc0e0ef0a11	2914	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	1:ebc0e0ef0a11	2915	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	1:ebc0e0ef0a11	2916	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	2917	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	2918	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	2919
vcoubard	1:ebc0e0ef0a11	2920	/* Register: LPCOMP_RESULT */
vcoubard	1:ebc0e0ef0a11	2921	/* Description: Result of last compare. */
vcoubard	1:ebc0e0ef0a11	2922
vcoubard	1:ebc0e0ef0a11	2923	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
vcoubard	1:ebc0e0ef0a11	2924	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
vcoubard	1:ebc0e0ef0a11	2925	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
vcoubard	1:ebc0e0ef0a11	2926	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
vcoubard	1:ebc0e0ef0a11	2927	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
vcoubard	1:ebc0e0ef0a11	2928
vcoubard	1:ebc0e0ef0a11	2929	/* Register: LPCOMP_ENABLE */
vcoubard	1:ebc0e0ef0a11	2930	/* Description: Enable the LPCOMP. */
vcoubard	1:ebc0e0ef0a11	2931
vcoubard	1:ebc0e0ef0a11	2932	/* Bits 1..0 : Enable or disable LPCOMP. */
vcoubard	1:ebc0e0ef0a11	2933	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	2934	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	2935	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
vcoubard	1:ebc0e0ef0a11	2936	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
vcoubard	1:ebc0e0ef0a11	2937
vcoubard	1:ebc0e0ef0a11	2938	/* Register: LPCOMP_PSEL */
vcoubard	1:ebc0e0ef0a11	2939	/* Description: Input pin select. */
vcoubard	1:ebc0e0ef0a11	2940
vcoubard	1:ebc0e0ef0a11	2941	/* Bits 2..0 : Analog input pin select. */
vcoubard	1:ebc0e0ef0a11	2942	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
vcoubard	1:ebc0e0ef0a11	2943	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	1:ebc0e0ef0a11	2944	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
vcoubard	1:ebc0e0ef0a11	2945	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
vcoubard	1:ebc0e0ef0a11	2946	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
vcoubard	1:ebc0e0ef0a11	2947	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
vcoubard	1:ebc0e0ef0a11	2948	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
vcoubard	1:ebc0e0ef0a11	2949	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
vcoubard	1:ebc0e0ef0a11	2950	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
vcoubard	1:ebc0e0ef0a11	2951	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
vcoubard	1:ebc0e0ef0a11	2952
vcoubard	1:ebc0e0ef0a11	2953	/* Register: LPCOMP_REFSEL */
vcoubard	1:ebc0e0ef0a11	2954	/* Description: Reference select. */
vcoubard	1:ebc0e0ef0a11	2955
vcoubard	1:ebc0e0ef0a11	2956	/* Bits 2..0 : Reference select. */
vcoubard	1:ebc0e0ef0a11	2957	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
vcoubard	1:ebc0e0ef0a11	2958	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
vcoubard	1:ebc0e0ef0a11	2959	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
vcoubard	1:ebc0e0ef0a11	2960	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
vcoubard	1:ebc0e0ef0a11	2961	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
vcoubard	1:ebc0e0ef0a11	2962	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
vcoubard	1:ebc0e0ef0a11	2963	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
vcoubard	1:ebc0e0ef0a11	2964	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
vcoubard	1:ebc0e0ef0a11	2965	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
vcoubard	1:ebc0e0ef0a11	2966	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
vcoubard	1:ebc0e0ef0a11	2967
vcoubard	1:ebc0e0ef0a11	2968	/* Register: LPCOMP_EXTREFSEL */
vcoubard	1:ebc0e0ef0a11	2969	/* Description: External reference select. */
vcoubard	1:ebc0e0ef0a11	2970
vcoubard	1:ebc0e0ef0a11	2971	/* Bit 0 : External analog reference pin selection. */
vcoubard	1:ebc0e0ef0a11	2972	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
vcoubard	1:ebc0e0ef0a11	2973	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
vcoubard	1:ebc0e0ef0a11	2974	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
vcoubard	1:ebc0e0ef0a11	2975	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
vcoubard	1:ebc0e0ef0a11	2976
vcoubard	1:ebc0e0ef0a11	2977	/* Register: LPCOMP_ANADETECT */
vcoubard	1:ebc0e0ef0a11	2978	/* Description: Analog detect configuration. */
vcoubard	1:ebc0e0ef0a11	2979
vcoubard	1:ebc0e0ef0a11	2980	/* Bits 1..0 : Analog detect configuration. */
vcoubard	1:ebc0e0ef0a11	2981	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
vcoubard	1:ebc0e0ef0a11	2982	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
vcoubard	1:ebc0e0ef0a11	2983	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
vcoubard	1:ebc0e0ef0a11	2984	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
vcoubard	1:ebc0e0ef0a11	2985	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
vcoubard	1:ebc0e0ef0a11	2986
vcoubard	1:ebc0e0ef0a11	2987	/* Register: LPCOMP_POWER */
vcoubard	1:ebc0e0ef0a11	2988	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	2989
vcoubard	1:ebc0e0ef0a11	2990	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	2991	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	2992	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	2993	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	2994	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	2995
vcoubard	1:ebc0e0ef0a11	2996
vcoubard	1:ebc0e0ef0a11	2997	/* Peripheral: MPU */
vcoubard	1:ebc0e0ef0a11	2998	/* Description: Memory Protection Unit. */
vcoubard	1:ebc0e0ef0a11	2999
vcoubard	1:ebc0e0ef0a11	3000	/* Register: MPU_PERR0 */
vcoubard	1:ebc0e0ef0a11	3001	/* Description: Configuration of peripherals in mpu regions. */
vcoubard	1:ebc0e0ef0a11	3002
vcoubard	1:ebc0e0ef0a11	3003	/* Bit 31 : PPI region configuration. */
vcoubard	1:ebc0e0ef0a11	3004	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
vcoubard	1:ebc0e0ef0a11	3005	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
vcoubard	1:ebc0e0ef0a11	3006	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3007	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3008
vcoubard	1:ebc0e0ef0a11	3009	/* Bit 30 : NVMC region configuration. */
vcoubard	1:ebc0e0ef0a11	3010	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
vcoubard	1:ebc0e0ef0a11	3011	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
vcoubard	1:ebc0e0ef0a11	3012	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3013	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3014
vcoubard	1:ebc0e0ef0a11	3015	/* Bit 19 : LPCOMP region configuration. */
vcoubard	1:ebc0e0ef0a11	3016	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
vcoubard	1:ebc0e0ef0a11	3017	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
vcoubard	1:ebc0e0ef0a11	3018	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3019	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3020
vcoubard	1:ebc0e0ef0a11	3021	/* Bit 18 : QDEC region configuration. */
vcoubard	1:ebc0e0ef0a11	3022	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
vcoubard	1:ebc0e0ef0a11	3023	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
vcoubard	1:ebc0e0ef0a11	3024	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3025	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3026
vcoubard	1:ebc0e0ef0a11	3027	/* Bit 17 : RTC1 region configuration. */
vcoubard	1:ebc0e0ef0a11	3028	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
vcoubard	1:ebc0e0ef0a11	3029	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
vcoubard	1:ebc0e0ef0a11	3030	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3031	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3032
vcoubard	1:ebc0e0ef0a11	3033	/* Bit 16 : WDT region configuration. */
vcoubard	1:ebc0e0ef0a11	3034	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
vcoubard	1:ebc0e0ef0a11	3035	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
vcoubard	1:ebc0e0ef0a11	3036	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3037	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3038
vcoubard	1:ebc0e0ef0a11	3039	/* Bit 15 : CCM and AAR region configuration. */
vcoubard	1:ebc0e0ef0a11	3040	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
vcoubard	1:ebc0e0ef0a11	3041	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
vcoubard	1:ebc0e0ef0a11	3042	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3043	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3044
vcoubard	1:ebc0e0ef0a11	3045	/* Bit 14 : ECB region configuration. */
vcoubard	1:ebc0e0ef0a11	3046	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
vcoubard	1:ebc0e0ef0a11	3047	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
vcoubard	1:ebc0e0ef0a11	3048	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3049	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3050
vcoubard	1:ebc0e0ef0a11	3051	/* Bit 13 : RNG region configuration. */
vcoubard	1:ebc0e0ef0a11	3052	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
vcoubard	1:ebc0e0ef0a11	3053	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
vcoubard	1:ebc0e0ef0a11	3054	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3055	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3056
vcoubard	1:ebc0e0ef0a11	3057	/* Bit 12 : TEMP region configuration. */
vcoubard	1:ebc0e0ef0a11	3058	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
vcoubard	1:ebc0e0ef0a11	3059	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
vcoubard	1:ebc0e0ef0a11	3060	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3061	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3062
vcoubard	1:ebc0e0ef0a11	3063	/* Bit 11 : RTC0 region configuration. */
vcoubard	1:ebc0e0ef0a11	3064	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
vcoubard	1:ebc0e0ef0a11	3065	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
vcoubard	1:ebc0e0ef0a11	3066	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3067	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3068
vcoubard	1:ebc0e0ef0a11	3069	/* Bit 10 : TIMER2 region configuration. */
vcoubard	1:ebc0e0ef0a11	3070	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
vcoubard	1:ebc0e0ef0a11	3071	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
vcoubard	1:ebc0e0ef0a11	3072	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3073	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3074
vcoubard	1:ebc0e0ef0a11	3075	/* Bit 9 : TIMER1 region configuration. */
vcoubard	1:ebc0e0ef0a11	3076	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
vcoubard	1:ebc0e0ef0a11	3077	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
vcoubard	1:ebc0e0ef0a11	3078	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3079	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3080
vcoubard	1:ebc0e0ef0a11	3081	/* Bit 8 : TIMER0 region configuration. */
vcoubard	1:ebc0e0ef0a11	3082	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
vcoubard	1:ebc0e0ef0a11	3083	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
vcoubard	1:ebc0e0ef0a11	3084	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3085	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3086
vcoubard	1:ebc0e0ef0a11	3087	/* Bit 7 : ADC region configuration. */
vcoubard	1:ebc0e0ef0a11	3088	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
vcoubard	1:ebc0e0ef0a11	3089	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
vcoubard	1:ebc0e0ef0a11	3090	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3091	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3092
vcoubard	1:ebc0e0ef0a11	3093	/* Bit 6 : GPIOTE region configuration. */
vcoubard	1:ebc0e0ef0a11	3094	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
vcoubard	1:ebc0e0ef0a11	3095	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
vcoubard	1:ebc0e0ef0a11	3096	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3097	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3098
vcoubard	1:ebc0e0ef0a11	3099	/* Bit 4 : SPI1 and TWI1 region configuration. */
vcoubard	1:ebc0e0ef0a11	3100	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
vcoubard	1:ebc0e0ef0a11	3101	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
vcoubard	1:ebc0e0ef0a11	3102	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3103	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3104
vcoubard	1:ebc0e0ef0a11	3105	/* Bit 3 : SPI0 and TWI0 region configuration. */
vcoubard	1:ebc0e0ef0a11	3106	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
vcoubard	1:ebc0e0ef0a11	3107	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
vcoubard	1:ebc0e0ef0a11	3108	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3109	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3110
vcoubard	1:ebc0e0ef0a11	3111	/* Bit 2 : UART0 region configuration. */
vcoubard	1:ebc0e0ef0a11	3112	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
vcoubard	1:ebc0e0ef0a11	3113	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
vcoubard	1:ebc0e0ef0a11	3114	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3115	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3116
vcoubard	1:ebc0e0ef0a11	3117	/* Bit 1 : RADIO region configuration. */
vcoubard	1:ebc0e0ef0a11	3118	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
vcoubard	1:ebc0e0ef0a11	3119	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
vcoubard	1:ebc0e0ef0a11	3120	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3121	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3122
vcoubard	1:ebc0e0ef0a11	3123	/* Bit 0 : POWER_CLOCK region configuration. */
vcoubard	1:ebc0e0ef0a11	3124	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
vcoubard	1:ebc0e0ef0a11	3125	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
vcoubard	1:ebc0e0ef0a11	3126	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	1:ebc0e0ef0a11	3127	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	1:ebc0e0ef0a11	3128
vcoubard	1:ebc0e0ef0a11	3129	/* Register: MPU_PROTENSET0 */
vcoubard	1:ebc0e0ef0a11	3130	/* Description: Erase and write protection bit enable set register. */
vcoubard	1:ebc0e0ef0a11	3131
vcoubard	1:ebc0e0ef0a11	3132	/* Bit 31 : Protection enable for region 31. */
vcoubard	1:ebc0e0ef0a11	3133	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
vcoubard	1:ebc0e0ef0a11	3134	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
vcoubard	1:ebc0e0ef0a11	3135	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3136	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3137	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3138
vcoubard	1:ebc0e0ef0a11	3139	/* Bit 30 : Protection enable for region 30. */
vcoubard	1:ebc0e0ef0a11	3140	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
vcoubard	1:ebc0e0ef0a11	3141	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
vcoubard	1:ebc0e0ef0a11	3142	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3143	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3144	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3145
vcoubard	1:ebc0e0ef0a11	3146	/* Bit 29 : Protection enable for region 29. */
vcoubard	1:ebc0e0ef0a11	3147	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
vcoubard	1:ebc0e0ef0a11	3148	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
vcoubard	1:ebc0e0ef0a11	3149	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3150	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3151	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3152
vcoubard	1:ebc0e0ef0a11	3153	/* Bit 28 : Protection enable for region 28. */
vcoubard	1:ebc0e0ef0a11	3154	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
vcoubard	1:ebc0e0ef0a11	3155	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
vcoubard	1:ebc0e0ef0a11	3156	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3157	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3158	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3159
vcoubard	1:ebc0e0ef0a11	3160	/* Bit 27 : Protection enable for region 27. */
vcoubard	1:ebc0e0ef0a11	3161	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
vcoubard	1:ebc0e0ef0a11	3162	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
vcoubard	1:ebc0e0ef0a11	3163	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3164	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3165	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3166
vcoubard	1:ebc0e0ef0a11	3167	/* Bit 26 : Protection enable for region 26. */
vcoubard	1:ebc0e0ef0a11	3168	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
vcoubard	1:ebc0e0ef0a11	3169	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
vcoubard	1:ebc0e0ef0a11	3170	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3171	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3172	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3173
vcoubard	1:ebc0e0ef0a11	3174	/* Bit 25 : Protection enable for region 25. */
vcoubard	1:ebc0e0ef0a11	3175	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
vcoubard	1:ebc0e0ef0a11	3176	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
vcoubard	1:ebc0e0ef0a11	3177	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3178	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3179	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3180
vcoubard	1:ebc0e0ef0a11	3181	/* Bit 24 : Protection enable for region 24. */
vcoubard	1:ebc0e0ef0a11	3182	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
vcoubard	1:ebc0e0ef0a11	3183	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
vcoubard	1:ebc0e0ef0a11	3184	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3185	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3186	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3187
vcoubard	1:ebc0e0ef0a11	3188	/* Bit 23 : Protection enable for region 23. */
vcoubard	1:ebc0e0ef0a11	3189	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
vcoubard	1:ebc0e0ef0a11	3190	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
vcoubard	1:ebc0e0ef0a11	3191	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3192	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3193	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3194
vcoubard	1:ebc0e0ef0a11	3195	/* Bit 22 : Protection enable for region 22. */
vcoubard	1:ebc0e0ef0a11	3196	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
vcoubard	1:ebc0e0ef0a11	3197	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
vcoubard	1:ebc0e0ef0a11	3198	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3199	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3200	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3201
vcoubard	1:ebc0e0ef0a11	3202	/* Bit 21 : Protection enable for region 21. */
vcoubard	1:ebc0e0ef0a11	3203	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
vcoubard	1:ebc0e0ef0a11	3204	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
vcoubard	1:ebc0e0ef0a11	3205	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3206	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3207	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3208
vcoubard	1:ebc0e0ef0a11	3209	/* Bit 20 : Protection enable for region 20. */
vcoubard	1:ebc0e0ef0a11	3210	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
vcoubard	1:ebc0e0ef0a11	3211	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
vcoubard	1:ebc0e0ef0a11	3212	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3213	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3214	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3215
vcoubard	1:ebc0e0ef0a11	3216	/* Bit 19 : Protection enable for region 19. */
vcoubard	1:ebc0e0ef0a11	3217	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
vcoubard	1:ebc0e0ef0a11	3218	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
vcoubard	1:ebc0e0ef0a11	3219	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3220	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3221	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3222
vcoubard	1:ebc0e0ef0a11	3223	/* Bit 18 : Protection enable for region 18. */
vcoubard	1:ebc0e0ef0a11	3224	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
vcoubard	1:ebc0e0ef0a11	3225	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
vcoubard	1:ebc0e0ef0a11	3226	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3227	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3228	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3229
vcoubard	1:ebc0e0ef0a11	3230	/* Bit 17 : Protection enable for region 17. */
vcoubard	1:ebc0e0ef0a11	3231	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
vcoubard	1:ebc0e0ef0a11	3232	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
vcoubard	1:ebc0e0ef0a11	3233	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3234	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3235	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3236
vcoubard	1:ebc0e0ef0a11	3237	/* Bit 16 : Protection enable for region 16. */
vcoubard	1:ebc0e0ef0a11	3238	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
vcoubard	1:ebc0e0ef0a11	3239	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
vcoubard	1:ebc0e0ef0a11	3240	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3241	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3242	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3243
vcoubard	1:ebc0e0ef0a11	3244	/* Bit 15 : Protection enable for region 15. */
vcoubard	1:ebc0e0ef0a11	3245	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
vcoubard	1:ebc0e0ef0a11	3246	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
vcoubard	1:ebc0e0ef0a11	3247	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3248	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3249	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3250
vcoubard	1:ebc0e0ef0a11	3251	/* Bit 14 : Protection enable for region 14. */
vcoubard	1:ebc0e0ef0a11	3252	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
vcoubard	1:ebc0e0ef0a11	3253	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
vcoubard	1:ebc0e0ef0a11	3254	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3255	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3256	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3257
vcoubard	1:ebc0e0ef0a11	3258	/* Bit 13 : Protection enable for region 13. */
vcoubard	1:ebc0e0ef0a11	3259	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
vcoubard	1:ebc0e0ef0a11	3260	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
vcoubard	1:ebc0e0ef0a11	3261	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3262	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3263	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3264
vcoubard	1:ebc0e0ef0a11	3265	/* Bit 12 : Protection enable for region 12. */
vcoubard	1:ebc0e0ef0a11	3266	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
vcoubard	1:ebc0e0ef0a11	3267	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
vcoubard	1:ebc0e0ef0a11	3268	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3269	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3270	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3271
vcoubard	1:ebc0e0ef0a11	3272	/* Bit 11 : Protection enable for region 11. */
vcoubard	1:ebc0e0ef0a11	3273	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
vcoubard	1:ebc0e0ef0a11	3274	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
vcoubard	1:ebc0e0ef0a11	3275	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3276	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3277	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3278
vcoubard	1:ebc0e0ef0a11	3279	/* Bit 10 : Protection enable for region 10. */
vcoubard	1:ebc0e0ef0a11	3280	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
vcoubard	1:ebc0e0ef0a11	3281	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
vcoubard	1:ebc0e0ef0a11	3282	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3283	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3284	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3285
vcoubard	1:ebc0e0ef0a11	3286	/* Bit 9 : Protection enable for region 9. */
vcoubard	1:ebc0e0ef0a11	3287	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
vcoubard	1:ebc0e0ef0a11	3288	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
vcoubard	1:ebc0e0ef0a11	3289	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3290	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3291	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3292
vcoubard	1:ebc0e0ef0a11	3293	/* Bit 8 : Protection enable for region 8. */
vcoubard	1:ebc0e0ef0a11	3294	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
vcoubard	1:ebc0e0ef0a11	3295	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
vcoubard	1:ebc0e0ef0a11	3296	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3297	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3298	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3299
vcoubard	1:ebc0e0ef0a11	3300	/* Bit 7 : Protection enable for region 7. */
vcoubard	1:ebc0e0ef0a11	3301	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
vcoubard	1:ebc0e0ef0a11	3302	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
vcoubard	1:ebc0e0ef0a11	3303	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3304	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3305	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3306
vcoubard	1:ebc0e0ef0a11	3307	/* Bit 6 : Protection enable for region 6. */
vcoubard	1:ebc0e0ef0a11	3308	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
vcoubard	1:ebc0e0ef0a11	3309	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
vcoubard	1:ebc0e0ef0a11	3310	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3311	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3312	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3313
vcoubard	1:ebc0e0ef0a11	3314	/* Bit 5 : Protection enable for region 5. */
vcoubard	1:ebc0e0ef0a11	3315	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
vcoubard	1:ebc0e0ef0a11	3316	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
vcoubard	1:ebc0e0ef0a11	3317	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3318	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3319	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3320
vcoubard	1:ebc0e0ef0a11	3321	/* Bit 4 : Protection enable for region 4. */
vcoubard	1:ebc0e0ef0a11	3322	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
vcoubard	1:ebc0e0ef0a11	3323	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
vcoubard	1:ebc0e0ef0a11	3324	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3325	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3326	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3327
vcoubard	1:ebc0e0ef0a11	3328	/* Bit 3 : Protection enable for region 3. */
vcoubard	1:ebc0e0ef0a11	3329	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
vcoubard	1:ebc0e0ef0a11	3330	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
vcoubard	1:ebc0e0ef0a11	3331	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3332	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3333	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3334
vcoubard	1:ebc0e0ef0a11	3335	/* Bit 2 : Protection enable for region 2. */
vcoubard	1:ebc0e0ef0a11	3336	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
vcoubard	1:ebc0e0ef0a11	3337	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
vcoubard	1:ebc0e0ef0a11	3338	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3339	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3340	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3341
vcoubard	1:ebc0e0ef0a11	3342	/* Bit 1 : Protection enable for region 1. */
vcoubard	1:ebc0e0ef0a11	3343	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
vcoubard	1:ebc0e0ef0a11	3344	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
vcoubard	1:ebc0e0ef0a11	3345	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3346	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3347	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3348
vcoubard	1:ebc0e0ef0a11	3349	/* Bit 0 : Protection enable for region 0. */
vcoubard	1:ebc0e0ef0a11	3350	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
vcoubard	1:ebc0e0ef0a11	3351	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
vcoubard	1:ebc0e0ef0a11	3352	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3353	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3354	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3355
vcoubard	1:ebc0e0ef0a11	3356	/* Register: MPU_PROTENSET1 */
vcoubard	1:ebc0e0ef0a11	3357	/* Description: Erase and write protection bit enable set register. */
vcoubard	1:ebc0e0ef0a11	3358
vcoubard	1:ebc0e0ef0a11	3359	/* Bit 31 : Protection enable for region 63. */
vcoubard	1:ebc0e0ef0a11	3360	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
vcoubard	1:ebc0e0ef0a11	3361	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
vcoubard	1:ebc0e0ef0a11	3362	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3363	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3364	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3365
vcoubard	1:ebc0e0ef0a11	3366	/* Bit 30 : Protection enable for region 62. */
vcoubard	1:ebc0e0ef0a11	3367	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
vcoubard	1:ebc0e0ef0a11	3368	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
vcoubard	1:ebc0e0ef0a11	3369	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3370	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3371	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3372
vcoubard	1:ebc0e0ef0a11	3373	/* Bit 29 : Protection enable for region 61. */
vcoubard	1:ebc0e0ef0a11	3374	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
vcoubard	1:ebc0e0ef0a11	3375	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
vcoubard	1:ebc0e0ef0a11	3376	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3377	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3378	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3379
vcoubard	1:ebc0e0ef0a11	3380	/* Bit 28 : Protection enable for region 60. */
vcoubard	1:ebc0e0ef0a11	3381	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
vcoubard	1:ebc0e0ef0a11	3382	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
vcoubard	1:ebc0e0ef0a11	3383	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3384	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3385	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3386
vcoubard	1:ebc0e0ef0a11	3387	/* Bit 27 : Protection enable for region 59. */
vcoubard	1:ebc0e0ef0a11	3388	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
vcoubard	1:ebc0e0ef0a11	3389	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
vcoubard	1:ebc0e0ef0a11	3390	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3391	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3392	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3393
vcoubard	1:ebc0e0ef0a11	3394	/* Bit 26 : Protection enable for region 58. */
vcoubard	1:ebc0e0ef0a11	3395	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
vcoubard	1:ebc0e0ef0a11	3396	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
vcoubard	1:ebc0e0ef0a11	3397	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3398	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3399	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3400
vcoubard	1:ebc0e0ef0a11	3401	/* Bit 25 : Protection enable for region 57. */
vcoubard	1:ebc0e0ef0a11	3402	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
vcoubard	1:ebc0e0ef0a11	3403	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
vcoubard	1:ebc0e0ef0a11	3404	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3405	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3406	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3407
vcoubard	1:ebc0e0ef0a11	3408	/* Bit 24 : Protection enable for region 56. */
vcoubard	1:ebc0e0ef0a11	3409	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
vcoubard	1:ebc0e0ef0a11	3410	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
vcoubard	1:ebc0e0ef0a11	3411	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3412	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3413	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3414
vcoubard	1:ebc0e0ef0a11	3415	/* Bit 23 : Protection enable for region 55. */
vcoubard	1:ebc0e0ef0a11	3416	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
vcoubard	1:ebc0e0ef0a11	3417	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
vcoubard	1:ebc0e0ef0a11	3418	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3419	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3420	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3421
vcoubard	1:ebc0e0ef0a11	3422	/* Bit 22 : Protection enable for region 54. */
vcoubard	1:ebc0e0ef0a11	3423	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
vcoubard	1:ebc0e0ef0a11	3424	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
vcoubard	1:ebc0e0ef0a11	3425	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3426	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3427	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3428
vcoubard	1:ebc0e0ef0a11	3429	/* Bit 21 : Protection enable for region 53. */
vcoubard	1:ebc0e0ef0a11	3430	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
vcoubard	1:ebc0e0ef0a11	3431	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
vcoubard	1:ebc0e0ef0a11	3432	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3433	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3434	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3435
vcoubard	1:ebc0e0ef0a11	3436	/* Bit 20 : Protection enable for region 52. */
vcoubard	1:ebc0e0ef0a11	3437	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
vcoubard	1:ebc0e0ef0a11	3438	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
vcoubard	1:ebc0e0ef0a11	3439	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3440	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3441	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3442
vcoubard	1:ebc0e0ef0a11	3443	/* Bit 19 : Protection enable for region 51. */
vcoubard	1:ebc0e0ef0a11	3444	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
vcoubard	1:ebc0e0ef0a11	3445	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
vcoubard	1:ebc0e0ef0a11	3446	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3447	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3448	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3449
vcoubard	1:ebc0e0ef0a11	3450	/* Bit 18 : Protection enable for region 50. */
vcoubard	1:ebc0e0ef0a11	3451	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
vcoubard	1:ebc0e0ef0a11	3452	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
vcoubard	1:ebc0e0ef0a11	3453	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3454	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3455	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3456
vcoubard	1:ebc0e0ef0a11	3457	/* Bit 17 : Protection enable for region 49. */
vcoubard	1:ebc0e0ef0a11	3458	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
vcoubard	1:ebc0e0ef0a11	3459	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
vcoubard	1:ebc0e0ef0a11	3460	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3461	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3462	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3463
vcoubard	1:ebc0e0ef0a11	3464	/* Bit 16 : Protection enable for region 48. */
vcoubard	1:ebc0e0ef0a11	3465	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
vcoubard	1:ebc0e0ef0a11	3466	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
vcoubard	1:ebc0e0ef0a11	3467	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3468	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3469	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3470
vcoubard	1:ebc0e0ef0a11	3471	/* Bit 15 : Protection enable for region 47. */
vcoubard	1:ebc0e0ef0a11	3472	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
vcoubard	1:ebc0e0ef0a11	3473	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
vcoubard	1:ebc0e0ef0a11	3474	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3475	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3476	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3477
vcoubard	1:ebc0e0ef0a11	3478	/* Bit 14 : Protection enable for region 46. */
vcoubard	1:ebc0e0ef0a11	3479	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
vcoubard	1:ebc0e0ef0a11	3480	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
vcoubard	1:ebc0e0ef0a11	3481	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3482	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3483	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3484
vcoubard	1:ebc0e0ef0a11	3485	/* Bit 13 : Protection enable for region 45. */
vcoubard	1:ebc0e0ef0a11	3486	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
vcoubard	1:ebc0e0ef0a11	3487	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
vcoubard	1:ebc0e0ef0a11	3488	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3489	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3490	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3491
vcoubard	1:ebc0e0ef0a11	3492	/* Bit 12 : Protection enable for region 44. */
vcoubard	1:ebc0e0ef0a11	3493	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
vcoubard	1:ebc0e0ef0a11	3494	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
vcoubard	1:ebc0e0ef0a11	3495	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3496	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3497	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3498
vcoubard	1:ebc0e0ef0a11	3499	/* Bit 11 : Protection enable for region 43. */
vcoubard	1:ebc0e0ef0a11	3500	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
vcoubard	1:ebc0e0ef0a11	3501	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
vcoubard	1:ebc0e0ef0a11	3502	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3503	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3504	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3505
vcoubard	1:ebc0e0ef0a11	3506	/* Bit 10 : Protection enable for region 42. */
vcoubard	1:ebc0e0ef0a11	3507	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
vcoubard	1:ebc0e0ef0a11	3508	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
vcoubard	1:ebc0e0ef0a11	3509	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3510	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3511	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3512
vcoubard	1:ebc0e0ef0a11	3513	/* Bit 9 : Protection enable for region 41. */
vcoubard	1:ebc0e0ef0a11	3514	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
vcoubard	1:ebc0e0ef0a11	3515	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
vcoubard	1:ebc0e0ef0a11	3516	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3517	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3518	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3519
vcoubard	1:ebc0e0ef0a11	3520	/* Bit 8 : Protection enable for region 40. */
vcoubard	1:ebc0e0ef0a11	3521	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
vcoubard	1:ebc0e0ef0a11	3522	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
vcoubard	1:ebc0e0ef0a11	3523	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3524	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3525	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3526
vcoubard	1:ebc0e0ef0a11	3527	/* Bit 7 : Protection enable for region 39. */
vcoubard	1:ebc0e0ef0a11	3528	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
vcoubard	1:ebc0e0ef0a11	3529	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
vcoubard	1:ebc0e0ef0a11	3530	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3531	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3532	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3533
vcoubard	1:ebc0e0ef0a11	3534	/* Bit 6 : Protection enable for region 38. */
vcoubard	1:ebc0e0ef0a11	3535	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
vcoubard	1:ebc0e0ef0a11	3536	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
vcoubard	1:ebc0e0ef0a11	3537	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3538	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3539	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3540
vcoubard	1:ebc0e0ef0a11	3541	/* Bit 5 : Protection enable for region 37. */
vcoubard	1:ebc0e0ef0a11	3542	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
vcoubard	1:ebc0e0ef0a11	3543	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
vcoubard	1:ebc0e0ef0a11	3544	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3545	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3546	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3547
vcoubard	1:ebc0e0ef0a11	3548	/* Bit 4 : Protection enable for region 36. */
vcoubard	1:ebc0e0ef0a11	3549	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
vcoubard	1:ebc0e0ef0a11	3550	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
vcoubard	1:ebc0e0ef0a11	3551	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3552	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3553	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3554
vcoubard	1:ebc0e0ef0a11	3555	/* Bit 3 : Protection enable for region 35. */
vcoubard	1:ebc0e0ef0a11	3556	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
vcoubard	1:ebc0e0ef0a11	3557	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
vcoubard	1:ebc0e0ef0a11	3558	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3559	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3560	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3561
vcoubard	1:ebc0e0ef0a11	3562	/* Bit 2 : Protection enable for region 34. */
vcoubard	1:ebc0e0ef0a11	3563	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
vcoubard	1:ebc0e0ef0a11	3564	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
vcoubard	1:ebc0e0ef0a11	3565	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3566	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3567	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3568
vcoubard	1:ebc0e0ef0a11	3569	/* Bit 1 : Protection enable for region 33. */
vcoubard	1:ebc0e0ef0a11	3570	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
vcoubard	1:ebc0e0ef0a11	3571	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
vcoubard	1:ebc0e0ef0a11	3572	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3573	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3574	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3575
vcoubard	1:ebc0e0ef0a11	3576	/* Bit 0 : Protection enable for region 32. */
vcoubard	1:ebc0e0ef0a11	3577	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
vcoubard	1:ebc0e0ef0a11	3578	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
vcoubard	1:ebc0e0ef0a11	3579	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3580	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3581	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
vcoubard	1:ebc0e0ef0a11	3582
vcoubard	1:ebc0e0ef0a11	3583	/* Register: MPU_DISABLEINDEBUG */
vcoubard	1:ebc0e0ef0a11	3584	/* Description: Disable erase and write protection mechanism in debug mode. */
vcoubard	1:ebc0e0ef0a11	3585
vcoubard	1:ebc0e0ef0a11	3586	/* Bit 0 : Disable protection mechanism in debug mode. */
vcoubard	1:ebc0e0ef0a11	3587	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
vcoubard	1:ebc0e0ef0a11	3588	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
vcoubard	1:ebc0e0ef0a11	3589	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
vcoubard	1:ebc0e0ef0a11	3590	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
vcoubard	1:ebc0e0ef0a11	3591
vcoubard	1:ebc0e0ef0a11	3592	/* Register: MPU_PROTBLOCKSIZE */
vcoubard	1:ebc0e0ef0a11	3593	/* Description: Erase and write protection block size. */
vcoubard	1:ebc0e0ef0a11	3594
vcoubard	1:ebc0e0ef0a11	3595	/* Bits 1..0 : Erase and write protection block size. */
vcoubard	1:ebc0e0ef0a11	3596	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
vcoubard	1:ebc0e0ef0a11	3597	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
vcoubard	1:ebc0e0ef0a11	3598	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
vcoubard	1:ebc0e0ef0a11	3599
vcoubard	1:ebc0e0ef0a11	3600
vcoubard	1:ebc0e0ef0a11	3601	/* Peripheral: NVMC */
vcoubard	1:ebc0e0ef0a11	3602	/* Description: Non Volatile Memory Controller. */
vcoubard	1:ebc0e0ef0a11	3603
vcoubard	1:ebc0e0ef0a11	3604	/* Register: NVMC_READY */
vcoubard	1:ebc0e0ef0a11	3605	/* Description: Ready flag. */
vcoubard	1:ebc0e0ef0a11	3606
vcoubard	1:ebc0e0ef0a11	3607	/* Bit 0 : NVMC ready. */
vcoubard	1:ebc0e0ef0a11	3608	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	1:ebc0e0ef0a11	3609	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
vcoubard	1:ebc0e0ef0a11	3610	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
vcoubard	1:ebc0e0ef0a11	3611	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
vcoubard	1:ebc0e0ef0a11	3612
vcoubard	1:ebc0e0ef0a11	3613	/* Register: NVMC_CONFIG */
vcoubard	1:ebc0e0ef0a11	3614	/* Description: Configuration register. */
vcoubard	1:ebc0e0ef0a11	3615
vcoubard	1:ebc0e0ef0a11	3616	/* Bits 1..0 : Program write enable. */
vcoubard	1:ebc0e0ef0a11	3617	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
vcoubard	1:ebc0e0ef0a11	3618	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
vcoubard	1:ebc0e0ef0a11	3619	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
vcoubard	1:ebc0e0ef0a11	3620	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
vcoubard	1:ebc0e0ef0a11	3621	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
vcoubard	1:ebc0e0ef0a11	3622
vcoubard	1:ebc0e0ef0a11	3623	/* Register: NVMC_ERASEALL */
vcoubard	1:ebc0e0ef0a11	3624	/* Description: Register for erasing all non-volatile user memory. */
vcoubard	1:ebc0e0ef0a11	3625
vcoubard	1:ebc0e0ef0a11	3626	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
vcoubard	1:ebc0e0ef0a11	3627	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
vcoubard	1:ebc0e0ef0a11	3628	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
vcoubard	1:ebc0e0ef0a11	3629	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
vcoubard	1:ebc0e0ef0a11	3630	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
vcoubard	1:ebc0e0ef0a11	3631
vcoubard	1:ebc0e0ef0a11	3632	/* Register: NVMC_ERASEUICR */
vcoubard	1:ebc0e0ef0a11	3633	/* Description: Register for start erasing User Information Congfiguration Registers. */
vcoubard	1:ebc0e0ef0a11	3634
vcoubard	1:ebc0e0ef0a11	3635	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
vcoubard	1:ebc0e0ef0a11	3636	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
vcoubard	1:ebc0e0ef0a11	3637	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
vcoubard	1:ebc0e0ef0a11	3638	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
vcoubard	1:ebc0e0ef0a11	3639	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
vcoubard	1:ebc0e0ef0a11	3640
vcoubard	1:ebc0e0ef0a11	3641
vcoubard	1:ebc0e0ef0a11	3642	/* Peripheral: POWER */
vcoubard	1:ebc0e0ef0a11	3643	/* Description: Power Control. */
vcoubard	1:ebc0e0ef0a11	3644
vcoubard	1:ebc0e0ef0a11	3645	/* Register: POWER_INTENSET */
vcoubard	1:ebc0e0ef0a11	3646	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	3647
vcoubard	1:ebc0e0ef0a11	3648	/* Bit 2 : Enable interrupt on POFWARN event. */
vcoubard	1:ebc0e0ef0a11	3649	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
vcoubard	1:ebc0e0ef0a11	3650	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
vcoubard	1:ebc0e0ef0a11	3651	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	3652	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	3653	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	3654
vcoubard	1:ebc0e0ef0a11	3655	/* Register: POWER_INTENCLR */
vcoubard	1:ebc0e0ef0a11	3656	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	3657
vcoubard	1:ebc0e0ef0a11	3658	/* Bit 2 : Disable interrupt on POFWARN event. */
vcoubard	1:ebc0e0ef0a11	3659	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
vcoubard	1:ebc0e0ef0a11	3660	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
vcoubard	1:ebc0e0ef0a11	3661	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	3662	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	3663	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	3664
vcoubard	1:ebc0e0ef0a11	3665	/* Register: POWER_RESETREAS */
vcoubard	1:ebc0e0ef0a11	3666	/* Description: Reset reason. */
vcoubard	1:ebc0e0ef0a11	3667
vcoubard	1:ebc0e0ef0a11	3668	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
vcoubard	1:ebc0e0ef0a11	3669	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
vcoubard	1:ebc0e0ef0a11	3670	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
vcoubard	1:ebc0e0ef0a11	3671	#define POWER_RESETREAS_DIF_NotDetected (0UL) /!< Reset not detected. /
vcoubard	1:ebc0e0ef0a11	3672	#define POWER_RESETREAS_DIF_Detected (1UL) /!< Reset detected. /
vcoubard	1:ebc0e0ef0a11	3673
vcoubard	1:ebc0e0ef0a11	3674	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
vcoubard	1:ebc0e0ef0a11	3675	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
vcoubard	1:ebc0e0ef0a11	3676	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
vcoubard	1:ebc0e0ef0a11	3677	#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /!< Reset not detected. /
vcoubard	1:ebc0e0ef0a11	3678	#define POWER_RESETREAS_LPCOMP_Detected (1UL) /!< Reset detected. /
vcoubard	1:ebc0e0ef0a11	3679
vcoubard	1:ebc0e0ef0a11	3680	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
vcoubard	1:ebc0e0ef0a11	3681	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
vcoubard	1:ebc0e0ef0a11	3682	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
vcoubard	1:ebc0e0ef0a11	3683	#define POWER_RESETREAS_OFF_NotDetected (0UL) /!< Reset not detected. /
vcoubard	1:ebc0e0ef0a11	3684	#define POWER_RESETREAS_OFF_Detected (1UL) /!< Reset detected. /
vcoubard	1:ebc0e0ef0a11	3685
vcoubard	1:ebc0e0ef0a11	3686	/* Bit 3 : Reset from CPU lock-up detected. */
vcoubard	1:ebc0e0ef0a11	3687	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
vcoubard	1:ebc0e0ef0a11	3688	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
vcoubard	1:ebc0e0ef0a11	3689	#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /!< Reset not detected. /
vcoubard	1:ebc0e0ef0a11	3690	#define POWER_RESETREAS_LOCKUP_Detected (1UL) /!< Reset detected. /
vcoubard	1:ebc0e0ef0a11	3691
vcoubard	1:ebc0e0ef0a11	3692	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
vcoubard	1:ebc0e0ef0a11	3693	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
vcoubard	1:ebc0e0ef0a11	3694	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
vcoubard	1:ebc0e0ef0a11	3695	#define POWER_RESETREAS_SREQ_NotDetected (0UL) /!< Reset not detected. /
vcoubard	1:ebc0e0ef0a11	3696	#define POWER_RESETREAS_SREQ_Detected (1UL) /!< Reset detected. /
vcoubard	1:ebc0e0ef0a11	3697
vcoubard	1:ebc0e0ef0a11	3698	/* Bit 1 : Reset from watchdog detected. */
vcoubard	1:ebc0e0ef0a11	3699	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
vcoubard	1:ebc0e0ef0a11	3700	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
vcoubard	1:ebc0e0ef0a11	3701	#define POWER_RESETREAS_DOG_NotDetected (0UL) /!< Reset not detected. /
vcoubard	1:ebc0e0ef0a11	3702	#define POWER_RESETREAS_DOG_Detected (1UL) /!< Reset detected. /
vcoubard	1:ebc0e0ef0a11	3703
vcoubard	1:ebc0e0ef0a11	3704	/* Bit 0 : Reset from pin-reset detected. */
vcoubard	1:ebc0e0ef0a11	3705	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
vcoubard	1:ebc0e0ef0a11	3706	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
vcoubard	1:ebc0e0ef0a11	3707	#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /!< Reset not detected. /
vcoubard	1:ebc0e0ef0a11	3708	#define POWER_RESETREAS_RESETPIN_Detected (1UL) /!< Reset detected. /
vcoubard	1:ebc0e0ef0a11	3709
vcoubard	1:ebc0e0ef0a11	3710	/* Register: POWER_RAMSTATUS */
vcoubard	1:ebc0e0ef0a11	3711	/* Description: Ram status register. */
vcoubard	1:ebc0e0ef0a11	3712
vcoubard	1:ebc0e0ef0a11	3713	/* Bit 3 : RAM block 3 status. */
vcoubard	1:ebc0e0ef0a11	3714	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
vcoubard	1:ebc0e0ef0a11	3715	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
vcoubard	1:ebc0e0ef0a11	3716	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
vcoubard	1:ebc0e0ef0a11	3717	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
vcoubard	1:ebc0e0ef0a11	3718
vcoubard	1:ebc0e0ef0a11	3719	/* Bit 2 : RAM block 2 status. */
vcoubard	1:ebc0e0ef0a11	3720	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
vcoubard	1:ebc0e0ef0a11	3721	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
vcoubard	1:ebc0e0ef0a11	3722	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
vcoubard	1:ebc0e0ef0a11	3723	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
vcoubard	1:ebc0e0ef0a11	3724
vcoubard	1:ebc0e0ef0a11	3725	/* Bit 1 : RAM block 1 status. */
vcoubard	1:ebc0e0ef0a11	3726	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
vcoubard	1:ebc0e0ef0a11	3727	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
vcoubard	1:ebc0e0ef0a11	3728	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
vcoubard	1:ebc0e0ef0a11	3729	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
vcoubard	1:ebc0e0ef0a11	3730
vcoubard	1:ebc0e0ef0a11	3731	/* Bit 0 : RAM block 0 status. */
vcoubard	1:ebc0e0ef0a11	3732	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
vcoubard	1:ebc0e0ef0a11	3733	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
vcoubard	1:ebc0e0ef0a11	3734	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
vcoubard	1:ebc0e0ef0a11	3735	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
vcoubard	1:ebc0e0ef0a11	3736
vcoubard	1:ebc0e0ef0a11	3737	/* Register: POWER_SYSTEMOFF */
vcoubard	1:ebc0e0ef0a11	3738	/* Description: System off register. */
vcoubard	1:ebc0e0ef0a11	3739
vcoubard	1:ebc0e0ef0a11	3740	/* Bit 0 : Enter system off mode. */
vcoubard	1:ebc0e0ef0a11	3741	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
vcoubard	1:ebc0e0ef0a11	3742	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
vcoubard	1:ebc0e0ef0a11	3743	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
vcoubard	1:ebc0e0ef0a11	3744
vcoubard	1:ebc0e0ef0a11	3745	/* Register: POWER_POFCON */
vcoubard	1:ebc0e0ef0a11	3746	/* Description: Power failure configuration. */
vcoubard	1:ebc0e0ef0a11	3747
vcoubard	1:ebc0e0ef0a11	3748	/* Bits 2..1 : Set threshold level. */
vcoubard	1:ebc0e0ef0a11	3749	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
vcoubard	1:ebc0e0ef0a11	3750	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
vcoubard	1:ebc0e0ef0a11	3751	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
vcoubard	1:ebc0e0ef0a11	3752	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
vcoubard	1:ebc0e0ef0a11	3753	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
vcoubard	1:ebc0e0ef0a11	3754	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
vcoubard	1:ebc0e0ef0a11	3755
vcoubard	1:ebc0e0ef0a11	3756	/* Bit 0 : Power failure comparator enable. */
vcoubard	1:ebc0e0ef0a11	3757	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
vcoubard	1:ebc0e0ef0a11	3758	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
vcoubard	1:ebc0e0ef0a11	3759	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	3760	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	3761
vcoubard	1:ebc0e0ef0a11	3762	/* Register: POWER_GPREGRET */
vcoubard	1:ebc0e0ef0a11	3763	/* Description: General purpose retention register. This register is a retained register. */
vcoubard	1:ebc0e0ef0a11	3764
vcoubard	1:ebc0e0ef0a11	3765	/* Bits 7..0 : General purpose retention register. */
vcoubard	1:ebc0e0ef0a11	3766	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
vcoubard	1:ebc0e0ef0a11	3767	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
vcoubard	1:ebc0e0ef0a11	3768
vcoubard	1:ebc0e0ef0a11	3769	/* Register: POWER_RAMON */
vcoubard	1:ebc0e0ef0a11	3770	/* Description: Ram on/off. */
vcoubard	1:ebc0e0ef0a11	3771
vcoubard	1:ebc0e0ef0a11	3772	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
vcoubard	1:ebc0e0ef0a11	3773	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
vcoubard	1:ebc0e0ef0a11	3774	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
vcoubard	1:ebc0e0ef0a11	3775	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
vcoubard	1:ebc0e0ef0a11	3776	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
vcoubard	1:ebc0e0ef0a11	3777
vcoubard	1:ebc0e0ef0a11	3778	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
vcoubard	1:ebc0e0ef0a11	3779	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
vcoubard	1:ebc0e0ef0a11	3780	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
vcoubard	1:ebc0e0ef0a11	3781	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
vcoubard	1:ebc0e0ef0a11	3782	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
vcoubard	1:ebc0e0ef0a11	3783
vcoubard	1:ebc0e0ef0a11	3784	/* Bit 1 : RAM block 1 behaviour in ON mode. */
vcoubard	1:ebc0e0ef0a11	3785	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
vcoubard	1:ebc0e0ef0a11	3786	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
vcoubard	1:ebc0e0ef0a11	3787	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
vcoubard	1:ebc0e0ef0a11	3788	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
vcoubard	1:ebc0e0ef0a11	3789
vcoubard	1:ebc0e0ef0a11	3790	/* Bit 0 : RAM block 0 behaviour in ON mode. */
vcoubard	1:ebc0e0ef0a11	3791	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
vcoubard	1:ebc0e0ef0a11	3792	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
vcoubard	1:ebc0e0ef0a11	3793	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
vcoubard	1:ebc0e0ef0a11	3794	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
vcoubard	1:ebc0e0ef0a11	3795
vcoubard	1:ebc0e0ef0a11	3796	/* Register: POWER_RESET */
vcoubard	1:ebc0e0ef0a11	3797	/* Description: Pin reset functionality configuration register. This register is a retained register. */
vcoubard	1:ebc0e0ef0a11	3798
vcoubard	1:ebc0e0ef0a11	3799	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
vcoubard	1:ebc0e0ef0a11	3800	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
vcoubard	1:ebc0e0ef0a11	3801	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
vcoubard	1:ebc0e0ef0a11	3802	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
vcoubard	1:ebc0e0ef0a11	3803	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
vcoubard	1:ebc0e0ef0a11	3804
vcoubard	1:ebc0e0ef0a11	3805	/* Register: POWER_RAMONB */
vcoubard	1:ebc0e0ef0a11	3806	/* Description: Ram on/off. */
vcoubard	1:ebc0e0ef0a11	3807
vcoubard	1:ebc0e0ef0a11	3808	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
vcoubard	1:ebc0e0ef0a11	3809	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
vcoubard	1:ebc0e0ef0a11	3810	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
vcoubard	1:ebc0e0ef0a11	3811	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
vcoubard	1:ebc0e0ef0a11	3812	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
vcoubard	1:ebc0e0ef0a11	3813
vcoubard	1:ebc0e0ef0a11	3814	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
vcoubard	1:ebc0e0ef0a11	3815	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
vcoubard	1:ebc0e0ef0a11	3816	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
vcoubard	1:ebc0e0ef0a11	3817	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
vcoubard	1:ebc0e0ef0a11	3818	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
vcoubard	1:ebc0e0ef0a11	3819
vcoubard	1:ebc0e0ef0a11	3820	/* Bit 1 : RAM block 3 behaviour in ON mode. */
vcoubard	1:ebc0e0ef0a11	3821	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
vcoubard	1:ebc0e0ef0a11	3822	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
vcoubard	1:ebc0e0ef0a11	3823	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
vcoubard	1:ebc0e0ef0a11	3824	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
vcoubard	1:ebc0e0ef0a11	3825
vcoubard	1:ebc0e0ef0a11	3826	/* Bit 0 : RAM block 2 behaviour in ON mode. */
vcoubard	1:ebc0e0ef0a11	3827	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
vcoubard	1:ebc0e0ef0a11	3828	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
vcoubard	1:ebc0e0ef0a11	3829	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
vcoubard	1:ebc0e0ef0a11	3830	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
vcoubard	1:ebc0e0ef0a11	3831
vcoubard	1:ebc0e0ef0a11	3832	/* Register: POWER_DCDCEN */
vcoubard	1:ebc0e0ef0a11	3833	/* Description: DCDC converter enable configuration register. */
vcoubard	1:ebc0e0ef0a11	3834
vcoubard	1:ebc0e0ef0a11	3835	/* Bit 0 : Enable DCDC converter. */
vcoubard	1:ebc0e0ef0a11	3836	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
vcoubard	1:ebc0e0ef0a11	3837	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
vcoubard	1:ebc0e0ef0a11	3838	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
vcoubard	1:ebc0e0ef0a11	3839	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
vcoubard	1:ebc0e0ef0a11	3840
vcoubard	1:ebc0e0ef0a11	3841	/* Register: POWER_DCDCFORCE */
vcoubard	1:ebc0e0ef0a11	3842	/* Description: DCDC power-up force register. */
vcoubard	1:ebc0e0ef0a11	3843
vcoubard	1:ebc0e0ef0a11	3844	/* Bit 1 : DCDC power-up force on. */
vcoubard	1:ebc0e0ef0a11	3845	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
vcoubard	1:ebc0e0ef0a11	3846	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
vcoubard	1:ebc0e0ef0a11	3847	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
vcoubard	1:ebc0e0ef0a11	3848	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
vcoubard	1:ebc0e0ef0a11	3849
vcoubard	1:ebc0e0ef0a11	3850	/* Bit 0 : DCDC power-up force off. */
vcoubard	1:ebc0e0ef0a11	3851	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
vcoubard	1:ebc0e0ef0a11	3852	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
vcoubard	1:ebc0e0ef0a11	3853	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
vcoubard	1:ebc0e0ef0a11	3854	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
vcoubard	1:ebc0e0ef0a11	3855
vcoubard	1:ebc0e0ef0a11	3856
vcoubard	1:ebc0e0ef0a11	3857	/* Peripheral: PPI */
vcoubard	1:ebc0e0ef0a11	3858	/* Description: PPI controller. */
vcoubard	1:ebc0e0ef0a11	3859
vcoubard	1:ebc0e0ef0a11	3860	/* Register: PPI_CHEN */
vcoubard	1:ebc0e0ef0a11	3861	/* Description: Channel enable. */
vcoubard	1:ebc0e0ef0a11	3862
vcoubard	1:ebc0e0ef0a11	3863	/* Bit 31 : Enable PPI channel 31. */
vcoubard	1:ebc0e0ef0a11	3864	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	1:ebc0e0ef0a11	3865	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	1:ebc0e0ef0a11	3866	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3867	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3868
vcoubard	1:ebc0e0ef0a11	3869	/* Bit 30 : Enable PPI channel 30. */
vcoubard	1:ebc0e0ef0a11	3870	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	1:ebc0e0ef0a11	3871	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	1:ebc0e0ef0a11	3872	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3873	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3874
vcoubard	1:ebc0e0ef0a11	3875	/* Bit 29 : Enable PPI channel 29. */
vcoubard	1:ebc0e0ef0a11	3876	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	1:ebc0e0ef0a11	3877	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	1:ebc0e0ef0a11	3878	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3879	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3880
vcoubard	1:ebc0e0ef0a11	3881	/* Bit 28 : Enable PPI channel 28. */
vcoubard	1:ebc0e0ef0a11	3882	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	1:ebc0e0ef0a11	3883	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	1:ebc0e0ef0a11	3884	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3885	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3886
vcoubard	1:ebc0e0ef0a11	3887	/* Bit 27 : Enable PPI channel 27. */
vcoubard	1:ebc0e0ef0a11	3888	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	1:ebc0e0ef0a11	3889	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	1:ebc0e0ef0a11	3890	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3891	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3892
vcoubard	1:ebc0e0ef0a11	3893	/* Bit 26 : Enable PPI channel 26. */
vcoubard	1:ebc0e0ef0a11	3894	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	1:ebc0e0ef0a11	3895	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	1:ebc0e0ef0a11	3896	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3897	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3898
vcoubard	1:ebc0e0ef0a11	3899	/* Bit 25 : Enable PPI channel 25. */
vcoubard	1:ebc0e0ef0a11	3900	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	1:ebc0e0ef0a11	3901	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	1:ebc0e0ef0a11	3902	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3903	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3904
vcoubard	1:ebc0e0ef0a11	3905	/* Bit 24 : Enable PPI channel 24. */
vcoubard	1:ebc0e0ef0a11	3906	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	1:ebc0e0ef0a11	3907	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	1:ebc0e0ef0a11	3908	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3909	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3910
vcoubard	1:ebc0e0ef0a11	3911	/* Bit 23 : Enable PPI channel 23. */
vcoubard	1:ebc0e0ef0a11	3912	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	1:ebc0e0ef0a11	3913	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	1:ebc0e0ef0a11	3914	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3915	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3916
vcoubard	1:ebc0e0ef0a11	3917	/* Bit 22 : Enable PPI channel 22. */
vcoubard	1:ebc0e0ef0a11	3918	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	1:ebc0e0ef0a11	3919	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	1:ebc0e0ef0a11	3920	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3921	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3922
vcoubard	1:ebc0e0ef0a11	3923	/* Bit 21 : Enable PPI channel 21. */
vcoubard	1:ebc0e0ef0a11	3924	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	1:ebc0e0ef0a11	3925	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	1:ebc0e0ef0a11	3926	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3927	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3928
vcoubard	1:ebc0e0ef0a11	3929	/* Bit 20 : Enable PPI channel 20. */
vcoubard	1:ebc0e0ef0a11	3930	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	1:ebc0e0ef0a11	3931	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	1:ebc0e0ef0a11	3932	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3933	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3934
vcoubard	1:ebc0e0ef0a11	3935	/* Bit 15 : Enable PPI channel 15. */
vcoubard	1:ebc0e0ef0a11	3936	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	1:ebc0e0ef0a11	3937	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	1:ebc0e0ef0a11	3938	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3939	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3940
vcoubard	1:ebc0e0ef0a11	3941	/* Bit 14 : Enable PPI channel 14. */
vcoubard	1:ebc0e0ef0a11	3942	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	1:ebc0e0ef0a11	3943	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	1:ebc0e0ef0a11	3944	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3945	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3946
vcoubard	1:ebc0e0ef0a11	3947	/* Bit 13 : Enable PPI channel 13. */
vcoubard	1:ebc0e0ef0a11	3948	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	1:ebc0e0ef0a11	3949	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	1:ebc0e0ef0a11	3950	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3951	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3952
vcoubard	1:ebc0e0ef0a11	3953	/* Bit 12 : Enable PPI channel 12. */
vcoubard	1:ebc0e0ef0a11	3954	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	1:ebc0e0ef0a11	3955	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	1:ebc0e0ef0a11	3956	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3957	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3958
vcoubard	1:ebc0e0ef0a11	3959	/* Bit 11 : Enable PPI channel 11. */
vcoubard	1:ebc0e0ef0a11	3960	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	1:ebc0e0ef0a11	3961	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	1:ebc0e0ef0a11	3962	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3963	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3964
vcoubard	1:ebc0e0ef0a11	3965	/* Bit 10 : Enable PPI channel 10. */
vcoubard	1:ebc0e0ef0a11	3966	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	1:ebc0e0ef0a11	3967	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	1:ebc0e0ef0a11	3968	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3969	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3970
vcoubard	1:ebc0e0ef0a11	3971	/* Bit 9 : Enable PPI channel 9. */
vcoubard	1:ebc0e0ef0a11	3972	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	1:ebc0e0ef0a11	3973	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	1:ebc0e0ef0a11	3974	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3975	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3976
vcoubard	1:ebc0e0ef0a11	3977	/* Bit 8 : Enable PPI channel 8. */
vcoubard	1:ebc0e0ef0a11	3978	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	1:ebc0e0ef0a11	3979	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	1:ebc0e0ef0a11	3980	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3981	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3982
vcoubard	1:ebc0e0ef0a11	3983	/* Bit 7 : Enable PPI channel 7. */
vcoubard	1:ebc0e0ef0a11	3984	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	1:ebc0e0ef0a11	3985	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	1:ebc0e0ef0a11	3986	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3987	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3988
vcoubard	1:ebc0e0ef0a11	3989	/* Bit 6 : Enable PPI channel 6. */
vcoubard	1:ebc0e0ef0a11	3990	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	1:ebc0e0ef0a11	3991	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	1:ebc0e0ef0a11	3992	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3993	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	3994
vcoubard	1:ebc0e0ef0a11	3995	/* Bit 5 : Enable PPI channel 5. */
vcoubard	1:ebc0e0ef0a11	3996	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	1:ebc0e0ef0a11	3997	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	1:ebc0e0ef0a11	3998	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	3999	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4000
vcoubard	1:ebc0e0ef0a11	4001	/* Bit 4 : Enable PPI channel 4. */
vcoubard	1:ebc0e0ef0a11	4002	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	1:ebc0e0ef0a11	4003	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	1:ebc0e0ef0a11	4004	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4005	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4006
vcoubard	1:ebc0e0ef0a11	4007	/* Bit 3 : Enable PPI channel 3. */
vcoubard	1:ebc0e0ef0a11	4008	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	1:ebc0e0ef0a11	4009	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	1:ebc0e0ef0a11	4010	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
vcoubard	1:ebc0e0ef0a11	4011	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
vcoubard	1:ebc0e0ef0a11	4012
vcoubard	1:ebc0e0ef0a11	4013	/* Bit 2 : Enable PPI channel 2. */
vcoubard	1:ebc0e0ef0a11	4014	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	1:ebc0e0ef0a11	4015	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	1:ebc0e0ef0a11	4016	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4017	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4018
vcoubard	1:ebc0e0ef0a11	4019	/* Bit 1 : Enable PPI channel 1. */
vcoubard	1:ebc0e0ef0a11	4020	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	1:ebc0e0ef0a11	4021	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	1:ebc0e0ef0a11	4022	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4023	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4024
vcoubard	1:ebc0e0ef0a11	4025	/* Bit 0 : Enable PPI channel 0. */
vcoubard	1:ebc0e0ef0a11	4026	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	1:ebc0e0ef0a11	4027	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	1:ebc0e0ef0a11	4028	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4029	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4030
vcoubard	1:ebc0e0ef0a11	4031	/* Register: PPI_CHENSET */
vcoubard	1:ebc0e0ef0a11	4032	/* Description: Channel enable set. */
vcoubard	1:ebc0e0ef0a11	4033
vcoubard	1:ebc0e0ef0a11	4034	/* Bit 31 : Enable PPI channel 31. */
vcoubard	1:ebc0e0ef0a11	4035	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	1:ebc0e0ef0a11	4036	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	1:ebc0e0ef0a11	4037	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4038	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4039	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4040
vcoubard	1:ebc0e0ef0a11	4041	/* Bit 30 : Enable PPI channel 30. */
vcoubard	1:ebc0e0ef0a11	4042	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	1:ebc0e0ef0a11	4043	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	1:ebc0e0ef0a11	4044	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4045	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4046	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4047
vcoubard	1:ebc0e0ef0a11	4048	/* Bit 29 : Enable PPI channel 29. */
vcoubard	1:ebc0e0ef0a11	4049	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	1:ebc0e0ef0a11	4050	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	1:ebc0e0ef0a11	4051	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4052	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4053	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4054
vcoubard	1:ebc0e0ef0a11	4055	/* Bit 28 : Enable PPI channel 28. */
vcoubard	1:ebc0e0ef0a11	4056	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	1:ebc0e0ef0a11	4057	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	1:ebc0e0ef0a11	4058	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4059	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4060	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4061
vcoubard	1:ebc0e0ef0a11	4062	/* Bit 27 : Enable PPI channel 27. */
vcoubard	1:ebc0e0ef0a11	4063	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	1:ebc0e0ef0a11	4064	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	1:ebc0e0ef0a11	4065	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4066	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4067	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4068
vcoubard	1:ebc0e0ef0a11	4069	/* Bit 26 : Enable PPI channel 26. */
vcoubard	1:ebc0e0ef0a11	4070	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	1:ebc0e0ef0a11	4071	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	1:ebc0e0ef0a11	4072	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4073	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4074	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4075
vcoubard	1:ebc0e0ef0a11	4076	/* Bit 25 : Enable PPI channel 25. */
vcoubard	1:ebc0e0ef0a11	4077	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	1:ebc0e0ef0a11	4078	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	1:ebc0e0ef0a11	4079	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4080	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4081	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4082
vcoubard	1:ebc0e0ef0a11	4083	/* Bit 24 : Enable PPI channel 24. */
vcoubard	1:ebc0e0ef0a11	4084	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	1:ebc0e0ef0a11	4085	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	1:ebc0e0ef0a11	4086	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4087	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4088	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4089
vcoubard	1:ebc0e0ef0a11	4090	/* Bit 23 : Enable PPI channel 23. */
vcoubard	1:ebc0e0ef0a11	4091	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	1:ebc0e0ef0a11	4092	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	1:ebc0e0ef0a11	4093	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4094	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4095	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4096
vcoubard	1:ebc0e0ef0a11	4097	/* Bit 22 : Enable PPI channel 22. */
vcoubard	1:ebc0e0ef0a11	4098	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	1:ebc0e0ef0a11	4099	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	1:ebc0e0ef0a11	4100	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4101	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4102	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4103
vcoubard	1:ebc0e0ef0a11	4104	/* Bit 21 : Enable PPI channel 21. */
vcoubard	1:ebc0e0ef0a11	4105	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	1:ebc0e0ef0a11	4106	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	1:ebc0e0ef0a11	4107	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4108	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4109	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4110
vcoubard	1:ebc0e0ef0a11	4111	/* Bit 20 : Enable PPI channel 20. */
vcoubard	1:ebc0e0ef0a11	4112	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	1:ebc0e0ef0a11	4113	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	1:ebc0e0ef0a11	4114	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4115	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4116	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4117
vcoubard	1:ebc0e0ef0a11	4118	/* Bit 15 : Enable PPI channel 15. */
vcoubard	1:ebc0e0ef0a11	4119	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	1:ebc0e0ef0a11	4120	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	1:ebc0e0ef0a11	4121	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4122	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4123	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4124
vcoubard	1:ebc0e0ef0a11	4125	/* Bit 14 : Enable PPI channel 14. */
vcoubard	1:ebc0e0ef0a11	4126	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	1:ebc0e0ef0a11	4127	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	1:ebc0e0ef0a11	4128	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4129	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4130	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4131
vcoubard	1:ebc0e0ef0a11	4132	/* Bit 13 : Enable PPI channel 13. */
vcoubard	1:ebc0e0ef0a11	4133	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	1:ebc0e0ef0a11	4134	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	1:ebc0e0ef0a11	4135	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4136	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4137	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4138
vcoubard	1:ebc0e0ef0a11	4139	/* Bit 12 : Enable PPI channel 12. */
vcoubard	1:ebc0e0ef0a11	4140	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	1:ebc0e0ef0a11	4141	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	1:ebc0e0ef0a11	4142	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4143	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4144	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4145
vcoubard	1:ebc0e0ef0a11	4146	/* Bit 11 : Enable PPI channel 11. */
vcoubard	1:ebc0e0ef0a11	4147	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	1:ebc0e0ef0a11	4148	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	1:ebc0e0ef0a11	4149	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4150	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4151	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4152
vcoubard	1:ebc0e0ef0a11	4153	/* Bit 10 : Enable PPI channel 10. */
vcoubard	1:ebc0e0ef0a11	4154	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	1:ebc0e0ef0a11	4155	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	1:ebc0e0ef0a11	4156	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4157	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4158	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4159
vcoubard	1:ebc0e0ef0a11	4160	/* Bit 9 : Enable PPI channel 9. */
vcoubard	1:ebc0e0ef0a11	4161	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	1:ebc0e0ef0a11	4162	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	1:ebc0e0ef0a11	4163	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4164	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4165	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4166
vcoubard	1:ebc0e0ef0a11	4167	/* Bit 8 : Enable PPI channel 8. */
vcoubard	1:ebc0e0ef0a11	4168	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	1:ebc0e0ef0a11	4169	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	1:ebc0e0ef0a11	4170	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4171	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4172	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4173
vcoubard	1:ebc0e0ef0a11	4174	/* Bit 7 : Enable PPI channel 7. */
vcoubard	1:ebc0e0ef0a11	4175	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	1:ebc0e0ef0a11	4176	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	1:ebc0e0ef0a11	4177	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4178	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4179	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4180
vcoubard	1:ebc0e0ef0a11	4181	/* Bit 6 : Enable PPI channel 6. */
vcoubard	1:ebc0e0ef0a11	4182	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	1:ebc0e0ef0a11	4183	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	1:ebc0e0ef0a11	4184	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4185	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4186	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4187
vcoubard	1:ebc0e0ef0a11	4188	/* Bit 5 : Enable PPI channel 5. */
vcoubard	1:ebc0e0ef0a11	4189	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	1:ebc0e0ef0a11	4190	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	1:ebc0e0ef0a11	4191	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4192	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4193	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4194
vcoubard	1:ebc0e0ef0a11	4195	/* Bit 4 : Enable PPI channel 4. */
vcoubard	1:ebc0e0ef0a11	4196	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	1:ebc0e0ef0a11	4197	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	1:ebc0e0ef0a11	4198	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4199	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4200	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4201
vcoubard	1:ebc0e0ef0a11	4202	/* Bit 3 : Enable PPI channel 3. */
vcoubard	1:ebc0e0ef0a11	4203	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	1:ebc0e0ef0a11	4204	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	1:ebc0e0ef0a11	4205	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4206	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4207	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4208
vcoubard	1:ebc0e0ef0a11	4209	/* Bit 2 : Enable PPI channel 2. */
vcoubard	1:ebc0e0ef0a11	4210	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	1:ebc0e0ef0a11	4211	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	1:ebc0e0ef0a11	4212	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4213	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4214	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4215
vcoubard	1:ebc0e0ef0a11	4216	/* Bit 1 : Enable PPI channel 1. */
vcoubard	1:ebc0e0ef0a11	4217	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	1:ebc0e0ef0a11	4218	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	1:ebc0e0ef0a11	4219	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4220	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4221	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4222
vcoubard	1:ebc0e0ef0a11	4223	/* Bit 0 : Enable PPI channel 0. */
vcoubard	1:ebc0e0ef0a11	4224	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	1:ebc0e0ef0a11	4225	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	1:ebc0e0ef0a11	4226	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4227	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4228	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
vcoubard	1:ebc0e0ef0a11	4229
vcoubard	1:ebc0e0ef0a11	4230	/* Register: PPI_CHENCLR */
vcoubard	1:ebc0e0ef0a11	4231	/* Description: Channel enable clear. */
vcoubard	1:ebc0e0ef0a11	4232
vcoubard	1:ebc0e0ef0a11	4233	/* Bit 31 : Disable PPI channel 31. */
vcoubard	1:ebc0e0ef0a11	4234	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	1:ebc0e0ef0a11	4235	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	1:ebc0e0ef0a11	4236	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4237	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4238	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4239
vcoubard	1:ebc0e0ef0a11	4240	/* Bit 30 : Disable PPI channel 30. */
vcoubard	1:ebc0e0ef0a11	4241	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	1:ebc0e0ef0a11	4242	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	1:ebc0e0ef0a11	4243	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4244	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4245	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4246
vcoubard	1:ebc0e0ef0a11	4247	/* Bit 29 : Disable PPI channel 29. */
vcoubard	1:ebc0e0ef0a11	4248	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	1:ebc0e0ef0a11	4249	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	1:ebc0e0ef0a11	4250	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4251	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4252	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4253
vcoubard	1:ebc0e0ef0a11	4254	/* Bit 28 : Disable PPI channel 28. */
vcoubard	1:ebc0e0ef0a11	4255	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	1:ebc0e0ef0a11	4256	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	1:ebc0e0ef0a11	4257	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4258	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4259	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4260
vcoubard	1:ebc0e0ef0a11	4261	/* Bit 27 : Disable PPI channel 27. */
vcoubard	1:ebc0e0ef0a11	4262	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	1:ebc0e0ef0a11	4263	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	1:ebc0e0ef0a11	4264	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4265	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4266	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4267
vcoubard	1:ebc0e0ef0a11	4268	/* Bit 26 : Disable PPI channel 26. */
vcoubard	1:ebc0e0ef0a11	4269	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	1:ebc0e0ef0a11	4270	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	1:ebc0e0ef0a11	4271	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4272	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4273	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4274
vcoubard	1:ebc0e0ef0a11	4275	/* Bit 25 : Disable PPI channel 25. */
vcoubard	1:ebc0e0ef0a11	4276	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	1:ebc0e0ef0a11	4277	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	1:ebc0e0ef0a11	4278	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4279	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4280	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4281
vcoubard	1:ebc0e0ef0a11	4282	/* Bit 24 : Disable PPI channel 24. */
vcoubard	1:ebc0e0ef0a11	4283	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	1:ebc0e0ef0a11	4284	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	1:ebc0e0ef0a11	4285	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4286	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4287	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4288
vcoubard	1:ebc0e0ef0a11	4289	/* Bit 23 : Disable PPI channel 23. */
vcoubard	1:ebc0e0ef0a11	4290	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	1:ebc0e0ef0a11	4291	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	1:ebc0e0ef0a11	4292	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4293	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4294	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4295
vcoubard	1:ebc0e0ef0a11	4296	/* Bit 22 : Disable PPI channel 22. */
vcoubard	1:ebc0e0ef0a11	4297	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	1:ebc0e0ef0a11	4298	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	1:ebc0e0ef0a11	4299	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4300	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4301	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4302
vcoubard	1:ebc0e0ef0a11	4303	/* Bit 21 : Disable PPI channel 21. */
vcoubard	1:ebc0e0ef0a11	4304	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	1:ebc0e0ef0a11	4305	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	1:ebc0e0ef0a11	4306	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4307	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4308	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4309
vcoubard	1:ebc0e0ef0a11	4310	/* Bit 20 : Disable PPI channel 20. */
vcoubard	1:ebc0e0ef0a11	4311	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	1:ebc0e0ef0a11	4312	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	1:ebc0e0ef0a11	4313	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4314	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4315	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4316
vcoubard	1:ebc0e0ef0a11	4317	/* Bit 15 : Disable PPI channel 15. */
vcoubard	1:ebc0e0ef0a11	4318	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	1:ebc0e0ef0a11	4319	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	1:ebc0e0ef0a11	4320	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4321	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4322	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4323
vcoubard	1:ebc0e0ef0a11	4324	/* Bit 14 : Disable PPI channel 14. */
vcoubard	1:ebc0e0ef0a11	4325	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	1:ebc0e0ef0a11	4326	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	1:ebc0e0ef0a11	4327	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4328	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4329	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4330
vcoubard	1:ebc0e0ef0a11	4331	/* Bit 13 : Disable PPI channel 13. */
vcoubard	1:ebc0e0ef0a11	4332	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	1:ebc0e0ef0a11	4333	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	1:ebc0e0ef0a11	4334	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4335	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4336	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4337
vcoubard	1:ebc0e0ef0a11	4338	/* Bit 12 : Disable PPI channel 12. */
vcoubard	1:ebc0e0ef0a11	4339	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	1:ebc0e0ef0a11	4340	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	1:ebc0e0ef0a11	4341	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4342	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4343	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4344
vcoubard	1:ebc0e0ef0a11	4345	/* Bit 11 : Disable PPI channel 11. */
vcoubard	1:ebc0e0ef0a11	4346	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	1:ebc0e0ef0a11	4347	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	1:ebc0e0ef0a11	4348	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4349	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4350	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4351
vcoubard	1:ebc0e0ef0a11	4352	/* Bit 10 : Disable PPI channel 10. */
vcoubard	1:ebc0e0ef0a11	4353	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	1:ebc0e0ef0a11	4354	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	1:ebc0e0ef0a11	4355	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4356	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4357	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4358
vcoubard	1:ebc0e0ef0a11	4359	/* Bit 9 : Disable PPI channel 9. */
vcoubard	1:ebc0e0ef0a11	4360	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	1:ebc0e0ef0a11	4361	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	1:ebc0e0ef0a11	4362	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4363	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4364	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4365
vcoubard	1:ebc0e0ef0a11	4366	/* Bit 8 : Disable PPI channel 8. */
vcoubard	1:ebc0e0ef0a11	4367	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	1:ebc0e0ef0a11	4368	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	1:ebc0e0ef0a11	4369	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4370	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4371	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4372
vcoubard	1:ebc0e0ef0a11	4373	/* Bit 7 : Disable PPI channel 7. */
vcoubard	1:ebc0e0ef0a11	4374	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	1:ebc0e0ef0a11	4375	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	1:ebc0e0ef0a11	4376	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4377	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4378	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4379
vcoubard	1:ebc0e0ef0a11	4380	/* Bit 6 : Disable PPI channel 6. */
vcoubard	1:ebc0e0ef0a11	4381	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	1:ebc0e0ef0a11	4382	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	1:ebc0e0ef0a11	4383	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4384	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4385	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4386
vcoubard	1:ebc0e0ef0a11	4387	/* Bit 5 : Disable PPI channel 5. */
vcoubard	1:ebc0e0ef0a11	4388	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	1:ebc0e0ef0a11	4389	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	1:ebc0e0ef0a11	4390	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4391	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4392	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4393
vcoubard	1:ebc0e0ef0a11	4394	/* Bit 4 : Disable PPI channel 4. */
vcoubard	1:ebc0e0ef0a11	4395	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	1:ebc0e0ef0a11	4396	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	1:ebc0e0ef0a11	4397	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4398	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4399	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4400
vcoubard	1:ebc0e0ef0a11	4401	/* Bit 3 : Disable PPI channel 3. */
vcoubard	1:ebc0e0ef0a11	4402	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	1:ebc0e0ef0a11	4403	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	1:ebc0e0ef0a11	4404	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4405	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4406	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4407
vcoubard	1:ebc0e0ef0a11	4408	/* Bit 2 : Disable PPI channel 2. */
vcoubard	1:ebc0e0ef0a11	4409	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	1:ebc0e0ef0a11	4410	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	1:ebc0e0ef0a11	4411	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4412	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4413	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4414
vcoubard	1:ebc0e0ef0a11	4415	/* Bit 1 : Disable PPI channel 1. */
vcoubard	1:ebc0e0ef0a11	4416	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	1:ebc0e0ef0a11	4417	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	1:ebc0e0ef0a11	4418	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4419	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4420	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4421
vcoubard	1:ebc0e0ef0a11	4422	/* Bit 0 : Disable PPI channel 0. */
vcoubard	1:ebc0e0ef0a11	4423	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	1:ebc0e0ef0a11	4424	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	1:ebc0e0ef0a11	4425	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	1:ebc0e0ef0a11	4426	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	1:ebc0e0ef0a11	4427	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
vcoubard	1:ebc0e0ef0a11	4428
vcoubard	1:ebc0e0ef0a11	4429	/* Register: PPI_CHG */
vcoubard	1:ebc0e0ef0a11	4430	/* Description: Channel group configuration. */
vcoubard	1:ebc0e0ef0a11	4431
vcoubard	1:ebc0e0ef0a11	4432	/* Bit 31 : Include CH31 in channel group. */
vcoubard	1:ebc0e0ef0a11	4433	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	1:ebc0e0ef0a11	4434	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	1:ebc0e0ef0a11	4435	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4436	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4437
vcoubard	1:ebc0e0ef0a11	4438	/* Bit 30 : Include CH30 in channel group. */
vcoubard	1:ebc0e0ef0a11	4439	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	1:ebc0e0ef0a11	4440	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	1:ebc0e0ef0a11	4441	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4442	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4443
vcoubard	1:ebc0e0ef0a11	4444	/* Bit 29 : Include CH29 in channel group. */
vcoubard	1:ebc0e0ef0a11	4445	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	1:ebc0e0ef0a11	4446	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	1:ebc0e0ef0a11	4447	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4448	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4449
vcoubard	1:ebc0e0ef0a11	4450	/* Bit 28 : Include CH28 in channel group. */
vcoubard	1:ebc0e0ef0a11	4451	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	1:ebc0e0ef0a11	4452	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	1:ebc0e0ef0a11	4453	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4454	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4455
vcoubard	1:ebc0e0ef0a11	4456	/* Bit 27 : Include CH27 in channel group. */
vcoubard	1:ebc0e0ef0a11	4457	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	1:ebc0e0ef0a11	4458	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	1:ebc0e0ef0a11	4459	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4460	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4461
vcoubard	1:ebc0e0ef0a11	4462	/* Bit 26 : Include CH26 in channel group. */
vcoubard	1:ebc0e0ef0a11	4463	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	1:ebc0e0ef0a11	4464	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	1:ebc0e0ef0a11	4465	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4466	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4467
vcoubard	1:ebc0e0ef0a11	4468	/* Bit 25 : Include CH25 in channel group. */
vcoubard	1:ebc0e0ef0a11	4469	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	1:ebc0e0ef0a11	4470	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	1:ebc0e0ef0a11	4471	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4472	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4473
vcoubard	1:ebc0e0ef0a11	4474	/* Bit 24 : Include CH24 in channel group. */
vcoubard	1:ebc0e0ef0a11	4475	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	1:ebc0e0ef0a11	4476	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	1:ebc0e0ef0a11	4477	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4478	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4479
vcoubard	1:ebc0e0ef0a11	4480	/* Bit 23 : Include CH23 in channel group. */
vcoubard	1:ebc0e0ef0a11	4481	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	1:ebc0e0ef0a11	4482	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	1:ebc0e0ef0a11	4483	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4484	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4485
vcoubard	1:ebc0e0ef0a11	4486	/* Bit 22 : Include CH22 in channel group. */
vcoubard	1:ebc0e0ef0a11	4487	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	1:ebc0e0ef0a11	4488	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	1:ebc0e0ef0a11	4489	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4490	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4491
vcoubard	1:ebc0e0ef0a11	4492	/* Bit 21 : Include CH21 in channel group. */
vcoubard	1:ebc0e0ef0a11	4493	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	1:ebc0e0ef0a11	4494	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	1:ebc0e0ef0a11	4495	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4496	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4497
vcoubard	1:ebc0e0ef0a11	4498	/* Bit 20 : Include CH20 in channel group. */
vcoubard	1:ebc0e0ef0a11	4499	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	1:ebc0e0ef0a11	4500	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	1:ebc0e0ef0a11	4501	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4502	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4503
vcoubard	1:ebc0e0ef0a11	4504	/* Bit 15 : Include CH15 in channel group. */
vcoubard	1:ebc0e0ef0a11	4505	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	1:ebc0e0ef0a11	4506	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	1:ebc0e0ef0a11	4507	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4508	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4509
vcoubard	1:ebc0e0ef0a11	4510	/* Bit 14 : Include CH14 in channel group. */
vcoubard	1:ebc0e0ef0a11	4511	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	1:ebc0e0ef0a11	4512	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	1:ebc0e0ef0a11	4513	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4514	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4515
vcoubard	1:ebc0e0ef0a11	4516	/* Bit 13 : Include CH13 in channel group. */
vcoubard	1:ebc0e0ef0a11	4517	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	1:ebc0e0ef0a11	4518	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	1:ebc0e0ef0a11	4519	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4520	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4521
vcoubard	1:ebc0e0ef0a11	4522	/* Bit 12 : Include CH12 in channel group. */
vcoubard	1:ebc0e0ef0a11	4523	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	1:ebc0e0ef0a11	4524	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	1:ebc0e0ef0a11	4525	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4526	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4527
vcoubard	1:ebc0e0ef0a11	4528	/* Bit 11 : Include CH11 in channel group. */
vcoubard	1:ebc0e0ef0a11	4529	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	1:ebc0e0ef0a11	4530	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	1:ebc0e0ef0a11	4531	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4532	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4533
vcoubard	1:ebc0e0ef0a11	4534	/* Bit 10 : Include CH10 in channel group. */
vcoubard	1:ebc0e0ef0a11	4535	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	1:ebc0e0ef0a11	4536	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	1:ebc0e0ef0a11	4537	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4538	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4539
vcoubard	1:ebc0e0ef0a11	4540	/* Bit 9 : Include CH9 in channel group. */
vcoubard	1:ebc0e0ef0a11	4541	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	1:ebc0e0ef0a11	4542	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	1:ebc0e0ef0a11	4543	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4544	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4545
vcoubard	1:ebc0e0ef0a11	4546	/* Bit 8 : Include CH8 in channel group. */
vcoubard	1:ebc0e0ef0a11	4547	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	1:ebc0e0ef0a11	4548	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	1:ebc0e0ef0a11	4549	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4550	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4551
vcoubard	1:ebc0e0ef0a11	4552	/* Bit 7 : Include CH7 in channel group. */
vcoubard	1:ebc0e0ef0a11	4553	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	1:ebc0e0ef0a11	4554	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	1:ebc0e0ef0a11	4555	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4556	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4557
vcoubard	1:ebc0e0ef0a11	4558	/* Bit 6 : Include CH6 in channel group. */
vcoubard	1:ebc0e0ef0a11	4559	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	1:ebc0e0ef0a11	4560	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	1:ebc0e0ef0a11	4561	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4562	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4563
vcoubard	1:ebc0e0ef0a11	4564	/* Bit 5 : Include CH5 in channel group. */
vcoubard	1:ebc0e0ef0a11	4565	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	1:ebc0e0ef0a11	4566	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	1:ebc0e0ef0a11	4567	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4568	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4569
vcoubard	1:ebc0e0ef0a11	4570	/* Bit 4 : Include CH4 in channel group. */
vcoubard	1:ebc0e0ef0a11	4571	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	1:ebc0e0ef0a11	4572	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	1:ebc0e0ef0a11	4573	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4574	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4575
vcoubard	1:ebc0e0ef0a11	4576	/* Bit 3 : Include CH3 in channel group. */
vcoubard	1:ebc0e0ef0a11	4577	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	1:ebc0e0ef0a11	4578	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	1:ebc0e0ef0a11	4579	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4580	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4581
vcoubard	1:ebc0e0ef0a11	4582	/* Bit 2 : Include CH2 in channel group. */
vcoubard	1:ebc0e0ef0a11	4583	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	1:ebc0e0ef0a11	4584	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	1:ebc0e0ef0a11	4585	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4586	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4587
vcoubard	1:ebc0e0ef0a11	4588	/* Bit 1 : Include CH1 in channel group. */
vcoubard	1:ebc0e0ef0a11	4589	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	1:ebc0e0ef0a11	4590	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	1:ebc0e0ef0a11	4591	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4592	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4593
vcoubard	1:ebc0e0ef0a11	4594	/* Bit 0 : Include CH0 in channel group. */
vcoubard	1:ebc0e0ef0a11	4595	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	1:ebc0e0ef0a11	4596	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	1:ebc0e0ef0a11	4597	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
vcoubard	1:ebc0e0ef0a11	4598	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
vcoubard	1:ebc0e0ef0a11	4599
vcoubard	1:ebc0e0ef0a11	4600
vcoubard	1:ebc0e0ef0a11	4601	/* Peripheral: QDEC */
vcoubard	1:ebc0e0ef0a11	4602	/* Description: Rotary decoder. */
vcoubard	1:ebc0e0ef0a11	4603
vcoubard	1:ebc0e0ef0a11	4604	/* Register: QDEC_SHORTS */
vcoubard	1:ebc0e0ef0a11	4605	/* Description: Shortcuts for the QDEC. */
vcoubard	1:ebc0e0ef0a11	4606
vcoubard	1:ebc0e0ef0a11	4607	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
vcoubard	1:ebc0e0ef0a11	4608	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
vcoubard	1:ebc0e0ef0a11	4609	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
vcoubard	1:ebc0e0ef0a11	4610	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4611	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4612
vcoubard	1:ebc0e0ef0a11	4613	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
vcoubard	1:ebc0e0ef0a11	4614	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
vcoubard	1:ebc0e0ef0a11	4615	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
vcoubard	1:ebc0e0ef0a11	4616	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4617	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4618
vcoubard	1:ebc0e0ef0a11	4619	/* Register: QDEC_INTENSET */
vcoubard	1:ebc0e0ef0a11	4620	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	4621
vcoubard	1:ebc0e0ef0a11	4622	/* Bit 2 : Enable interrupt on ACCOF event. */
vcoubard	1:ebc0e0ef0a11	4623	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
vcoubard	1:ebc0e0ef0a11	4624	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
vcoubard	1:ebc0e0ef0a11	4625	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4626	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4627	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4628
vcoubard	1:ebc0e0ef0a11	4629	/* Bit 1 : Enable interrupt on REPORTRDY event. */
vcoubard	1:ebc0e0ef0a11	4630	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
vcoubard	1:ebc0e0ef0a11	4631	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
vcoubard	1:ebc0e0ef0a11	4632	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4633	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4634	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4635
vcoubard	1:ebc0e0ef0a11	4636	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
vcoubard	1:ebc0e0ef0a11	4637	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
vcoubard	1:ebc0e0ef0a11	4638	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
vcoubard	1:ebc0e0ef0a11	4639	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4640	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4641	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4642
vcoubard	1:ebc0e0ef0a11	4643	/* Register: QDEC_INTENCLR */
vcoubard	1:ebc0e0ef0a11	4644	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	4645
vcoubard	1:ebc0e0ef0a11	4646	/* Bit 2 : Disable interrupt on ACCOF event. */
vcoubard	1:ebc0e0ef0a11	4647	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
vcoubard	1:ebc0e0ef0a11	4648	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
vcoubard	1:ebc0e0ef0a11	4649	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4650	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4651	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4652
vcoubard	1:ebc0e0ef0a11	4653	/* Bit 1 : Disable interrupt on REPORTRDY event. */
vcoubard	1:ebc0e0ef0a11	4654	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
vcoubard	1:ebc0e0ef0a11	4655	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
vcoubard	1:ebc0e0ef0a11	4656	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4657	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4658	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4659
vcoubard	1:ebc0e0ef0a11	4660	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
vcoubard	1:ebc0e0ef0a11	4661	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
vcoubard	1:ebc0e0ef0a11	4662	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
vcoubard	1:ebc0e0ef0a11	4663	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4664	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4665	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4666
vcoubard	1:ebc0e0ef0a11	4667	/* Register: QDEC_ENABLE */
vcoubard	1:ebc0e0ef0a11	4668	/* Description: Enable the QDEC. */
vcoubard	1:ebc0e0ef0a11	4669
vcoubard	1:ebc0e0ef0a11	4670	/* Bit 0 : Enable or disable QDEC. */
vcoubard	1:ebc0e0ef0a11	4671	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	4672	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	4673	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
vcoubard	1:ebc0e0ef0a11	4674	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
vcoubard	1:ebc0e0ef0a11	4675
vcoubard	1:ebc0e0ef0a11	4676	/* Register: QDEC_LEDPOL */
vcoubard	1:ebc0e0ef0a11	4677	/* Description: LED output pin polarity. */
vcoubard	1:ebc0e0ef0a11	4678
vcoubard	1:ebc0e0ef0a11	4679	/* Bit 0 : LED output pin polarity. */
vcoubard	1:ebc0e0ef0a11	4680	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
vcoubard	1:ebc0e0ef0a11	4681	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
vcoubard	1:ebc0e0ef0a11	4682	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
vcoubard	1:ebc0e0ef0a11	4683	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
vcoubard	1:ebc0e0ef0a11	4684
vcoubard	1:ebc0e0ef0a11	4685	/* Register: QDEC_SAMPLEPER */
vcoubard	1:ebc0e0ef0a11	4686	/* Description: Sample period. */
vcoubard	1:ebc0e0ef0a11	4687
vcoubard	1:ebc0e0ef0a11	4688	/* Bits 2..0 : Sample period. */
vcoubard	1:ebc0e0ef0a11	4689	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
vcoubard	1:ebc0e0ef0a11	4690	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
vcoubard	1:ebc0e0ef0a11	4691	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
vcoubard	1:ebc0e0ef0a11	4692	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
vcoubard	1:ebc0e0ef0a11	4693	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
vcoubard	1:ebc0e0ef0a11	4694	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
vcoubard	1:ebc0e0ef0a11	4695	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
vcoubard	1:ebc0e0ef0a11	4696	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
vcoubard	1:ebc0e0ef0a11	4697	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
vcoubard	1:ebc0e0ef0a11	4698	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
vcoubard	1:ebc0e0ef0a11	4699
vcoubard	1:ebc0e0ef0a11	4700	/* Register: QDEC_SAMPLE */
vcoubard	1:ebc0e0ef0a11	4701	/* Description: Motion sample value. */
vcoubard	1:ebc0e0ef0a11	4702
vcoubard	1:ebc0e0ef0a11	4703	/* Bits 31..0 : Last sample taken in compliment to 2. */
vcoubard	1:ebc0e0ef0a11	4704	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
vcoubard	1:ebc0e0ef0a11	4705	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
vcoubard	1:ebc0e0ef0a11	4706
vcoubard	1:ebc0e0ef0a11	4707	/* Register: QDEC_REPORTPER */
vcoubard	1:ebc0e0ef0a11	4708	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
vcoubard	1:ebc0e0ef0a11	4709
vcoubard	1:ebc0e0ef0a11	4710	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
vcoubard	1:ebc0e0ef0a11	4711	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
vcoubard	1:ebc0e0ef0a11	4712	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
vcoubard	1:ebc0e0ef0a11	4713	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
vcoubard	1:ebc0e0ef0a11	4714	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
vcoubard	1:ebc0e0ef0a11	4715	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
vcoubard	1:ebc0e0ef0a11	4716	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
vcoubard	1:ebc0e0ef0a11	4717	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
vcoubard	1:ebc0e0ef0a11	4718	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
vcoubard	1:ebc0e0ef0a11	4719	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
vcoubard	1:ebc0e0ef0a11	4720	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
vcoubard	1:ebc0e0ef0a11	4721
vcoubard	1:ebc0e0ef0a11	4722	/* Register: QDEC_DBFEN */
vcoubard	1:ebc0e0ef0a11	4723	/* Description: Enable debouncer input filters. */
vcoubard	1:ebc0e0ef0a11	4724
vcoubard	1:ebc0e0ef0a11	4725	/* Bit 0 : Enable debounce input filters. */
vcoubard	1:ebc0e0ef0a11	4726	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
vcoubard	1:ebc0e0ef0a11	4727	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
vcoubard	1:ebc0e0ef0a11	4728	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
vcoubard	1:ebc0e0ef0a11	4729	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
vcoubard	1:ebc0e0ef0a11	4730
vcoubard	1:ebc0e0ef0a11	4731	/* Register: QDEC_LEDPRE */
vcoubard	1:ebc0e0ef0a11	4732	/* Description: Time LED is switched ON before the sample. */
vcoubard	1:ebc0e0ef0a11	4733
vcoubard	1:ebc0e0ef0a11	4734	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
vcoubard	1:ebc0e0ef0a11	4735	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
vcoubard	1:ebc0e0ef0a11	4736	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
vcoubard	1:ebc0e0ef0a11	4737
vcoubard	1:ebc0e0ef0a11	4738	/* Register: QDEC_ACCDBL */
vcoubard	1:ebc0e0ef0a11	4739	/* Description: Accumulated double (error) transitions register. */
vcoubard	1:ebc0e0ef0a11	4740
vcoubard	1:ebc0e0ef0a11	4741	/* Bits 3..0 : Accumulated double (error) transitions. */
vcoubard	1:ebc0e0ef0a11	4742	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
vcoubard	1:ebc0e0ef0a11	4743	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
vcoubard	1:ebc0e0ef0a11	4744
vcoubard	1:ebc0e0ef0a11	4745	/* Register: QDEC_ACCDBLREAD */
vcoubard	1:ebc0e0ef0a11	4746	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
vcoubard	1:ebc0e0ef0a11	4747
vcoubard	1:ebc0e0ef0a11	4748	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
vcoubard	1:ebc0e0ef0a11	4749	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
vcoubard	1:ebc0e0ef0a11	4750	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
vcoubard	1:ebc0e0ef0a11	4751
vcoubard	1:ebc0e0ef0a11	4752	/* Register: QDEC_POWER */
vcoubard	1:ebc0e0ef0a11	4753	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	4754
vcoubard	1:ebc0e0ef0a11	4755	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	4756	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	4757	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	4758	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	4759	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	4760
vcoubard	1:ebc0e0ef0a11	4761
vcoubard	1:ebc0e0ef0a11	4762	/* Peripheral: RADIO */
vcoubard	1:ebc0e0ef0a11	4763	/* Description: The radio. */
vcoubard	1:ebc0e0ef0a11	4764
vcoubard	1:ebc0e0ef0a11	4765	/* Register: RADIO_SHORTS */
vcoubard	1:ebc0e0ef0a11	4766	/* Description: Shortcuts for the radio. */
vcoubard	1:ebc0e0ef0a11	4767
vcoubard	1:ebc0e0ef0a11	4768	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
vcoubard	1:ebc0e0ef0a11	4769	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
vcoubard	1:ebc0e0ef0a11	4770	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
vcoubard	1:ebc0e0ef0a11	4771	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4772	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4773
vcoubard	1:ebc0e0ef0a11	4774	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
vcoubard	1:ebc0e0ef0a11	4775	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
vcoubard	1:ebc0e0ef0a11	4776	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
vcoubard	1:ebc0e0ef0a11	4777	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4778	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4779
vcoubard	1:ebc0e0ef0a11	4780	/* Bit 5 : Shortcut between END event and START task. */
vcoubard	1:ebc0e0ef0a11	4781	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
vcoubard	1:ebc0e0ef0a11	4782	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
vcoubard	1:ebc0e0ef0a11	4783	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4784	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4785
vcoubard	1:ebc0e0ef0a11	4786	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
vcoubard	1:ebc0e0ef0a11	4787	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
vcoubard	1:ebc0e0ef0a11	4788	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
vcoubard	1:ebc0e0ef0a11	4789	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4790	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4791
vcoubard	1:ebc0e0ef0a11	4792	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
vcoubard	1:ebc0e0ef0a11	4793	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
vcoubard	1:ebc0e0ef0a11	4794	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
vcoubard	1:ebc0e0ef0a11	4795	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4796	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4797
vcoubard	1:ebc0e0ef0a11	4798	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
vcoubard	1:ebc0e0ef0a11	4799	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
vcoubard	1:ebc0e0ef0a11	4800	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
vcoubard	1:ebc0e0ef0a11	4801	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4802	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4803
vcoubard	1:ebc0e0ef0a11	4804	/* Bit 1 : Shortcut between END event and DISABLE task. */
vcoubard	1:ebc0e0ef0a11	4805	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
vcoubard	1:ebc0e0ef0a11	4806	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
vcoubard	1:ebc0e0ef0a11	4807	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4808	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4809
vcoubard	1:ebc0e0ef0a11	4810	/* Bit 0 : Shortcut between READY event and START task. */
vcoubard	1:ebc0e0ef0a11	4811	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
vcoubard	1:ebc0e0ef0a11	4812	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
vcoubard	1:ebc0e0ef0a11	4813	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	4814	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	4815
vcoubard	1:ebc0e0ef0a11	4816	/* Register: RADIO_INTENSET */
vcoubard	1:ebc0e0ef0a11	4817	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	4818
vcoubard	1:ebc0e0ef0a11	4819	/* Bit 10 : Enable interrupt on BCMATCH event. */
vcoubard	1:ebc0e0ef0a11	4820	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
vcoubard	1:ebc0e0ef0a11	4821	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
vcoubard	1:ebc0e0ef0a11	4822	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4823	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4824	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4825
vcoubard	1:ebc0e0ef0a11	4826	/* Bit 7 : Enable interrupt on RSSIEND event. */
vcoubard	1:ebc0e0ef0a11	4827	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
vcoubard	1:ebc0e0ef0a11	4828	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
vcoubard	1:ebc0e0ef0a11	4829	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4830	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4831	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4832
vcoubard	1:ebc0e0ef0a11	4833	/* Bit 6 : Enable interrupt on DEVMISS event. */
vcoubard	1:ebc0e0ef0a11	4834	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
vcoubard	1:ebc0e0ef0a11	4835	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
vcoubard	1:ebc0e0ef0a11	4836	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4837	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4838	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4839
vcoubard	1:ebc0e0ef0a11	4840	/* Bit 5 : Enable interrupt on DEVMATCH event. */
vcoubard	1:ebc0e0ef0a11	4841	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
vcoubard	1:ebc0e0ef0a11	4842	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
vcoubard	1:ebc0e0ef0a11	4843	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4844	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4845	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4846
vcoubard	1:ebc0e0ef0a11	4847	/* Bit 4 : Enable interrupt on DISABLED event. */
vcoubard	1:ebc0e0ef0a11	4848	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
vcoubard	1:ebc0e0ef0a11	4849	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
vcoubard	1:ebc0e0ef0a11	4850	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4851	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4852	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4853
vcoubard	1:ebc0e0ef0a11	4854	/* Bit 3 : Enable interrupt on END event. */
vcoubard	1:ebc0e0ef0a11	4855	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
vcoubard	1:ebc0e0ef0a11	4856	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	1:ebc0e0ef0a11	4857	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4858	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4859	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4860
vcoubard	1:ebc0e0ef0a11	4861	/* Bit 2 : Enable interrupt on PAYLOAD event. */
vcoubard	1:ebc0e0ef0a11	4862	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
vcoubard	1:ebc0e0ef0a11	4863	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
vcoubard	1:ebc0e0ef0a11	4864	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4865	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4866	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4867
vcoubard	1:ebc0e0ef0a11	4868	/* Bit 1 : Enable interrupt on ADDRESS event. */
vcoubard	1:ebc0e0ef0a11	4869	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
vcoubard	1:ebc0e0ef0a11	4870	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	1:ebc0e0ef0a11	4871	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4872	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4873	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4874
vcoubard	1:ebc0e0ef0a11	4875	/* Bit 0 : Enable interrupt on READY event. */
vcoubard	1:ebc0e0ef0a11	4876	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	1:ebc0e0ef0a11	4877	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	1:ebc0e0ef0a11	4878	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4879	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4880	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4881
vcoubard	1:ebc0e0ef0a11	4882	/* Register: RADIO_INTENCLR */
vcoubard	1:ebc0e0ef0a11	4883	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	4884
vcoubard	1:ebc0e0ef0a11	4885	/* Bit 10 : Disable interrupt on BCMATCH event. */
vcoubard	1:ebc0e0ef0a11	4886	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
vcoubard	1:ebc0e0ef0a11	4887	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
vcoubard	1:ebc0e0ef0a11	4888	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4889	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4890	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4891
vcoubard	1:ebc0e0ef0a11	4892	/* Bit 7 : Disable interrupt on RSSIEND event. */
vcoubard	1:ebc0e0ef0a11	4893	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
vcoubard	1:ebc0e0ef0a11	4894	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
vcoubard	1:ebc0e0ef0a11	4895	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4896	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4897	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4898
vcoubard	1:ebc0e0ef0a11	4899	/* Bit 6 : Disable interrupt on DEVMISS event. */
vcoubard	1:ebc0e0ef0a11	4900	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
vcoubard	1:ebc0e0ef0a11	4901	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
vcoubard	1:ebc0e0ef0a11	4902	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4903	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4904	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4905
vcoubard	1:ebc0e0ef0a11	4906	/* Bit 5 : Disable interrupt on DEVMATCH event. */
vcoubard	1:ebc0e0ef0a11	4907	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
vcoubard	1:ebc0e0ef0a11	4908	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
vcoubard	1:ebc0e0ef0a11	4909	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4910	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4911	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4912
vcoubard	1:ebc0e0ef0a11	4913	/* Bit 4 : Disable interrupt on DISABLED event. */
vcoubard	1:ebc0e0ef0a11	4914	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
vcoubard	1:ebc0e0ef0a11	4915	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
vcoubard	1:ebc0e0ef0a11	4916	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4917	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4918	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4919
vcoubard	1:ebc0e0ef0a11	4920	/* Bit 3 : Disable interrupt on END event. */
vcoubard	1:ebc0e0ef0a11	4921	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
vcoubard	1:ebc0e0ef0a11	4922	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	1:ebc0e0ef0a11	4923	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4924	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4925	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4926
vcoubard	1:ebc0e0ef0a11	4927	/* Bit 2 : Disable interrupt on PAYLOAD event. */
vcoubard	1:ebc0e0ef0a11	4928	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
vcoubard	1:ebc0e0ef0a11	4929	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
vcoubard	1:ebc0e0ef0a11	4930	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4931	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4932	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4933
vcoubard	1:ebc0e0ef0a11	4934	/* Bit 1 : Disable interrupt on ADDRESS event. */
vcoubard	1:ebc0e0ef0a11	4935	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
vcoubard	1:ebc0e0ef0a11	4936	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	1:ebc0e0ef0a11	4937	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4938	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4939	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4940
vcoubard	1:ebc0e0ef0a11	4941	/* Bit 0 : Disable interrupt on READY event. */
vcoubard	1:ebc0e0ef0a11	4942	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	1:ebc0e0ef0a11	4943	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	1:ebc0e0ef0a11	4944	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	4945	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	4946	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	4947
vcoubard	1:ebc0e0ef0a11	4948	/* Register: RADIO_CRCSTATUS */
vcoubard	1:ebc0e0ef0a11	4949	/* Description: CRC status of received packet. */
vcoubard	1:ebc0e0ef0a11	4950
vcoubard	1:ebc0e0ef0a11	4951	/* Bit 0 : CRC status of received packet. */
vcoubard	1:ebc0e0ef0a11	4952	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
vcoubard	1:ebc0e0ef0a11	4953	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
vcoubard	1:ebc0e0ef0a11	4954	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
vcoubard	1:ebc0e0ef0a11	4955	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
vcoubard	1:ebc0e0ef0a11	4956
vcoubard	1:ebc0e0ef0a11	4957	/* Register: RADIO_RXMATCH */
vcoubard	1:ebc0e0ef0a11	4958	/* Description: Received address. */
vcoubard	1:ebc0e0ef0a11	4959
vcoubard	1:ebc0e0ef0a11	4960	/* Bits 2..0 : Logical address in which previous packet was received. */
vcoubard	1:ebc0e0ef0a11	4961	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
vcoubard	1:ebc0e0ef0a11	4962	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
vcoubard	1:ebc0e0ef0a11	4963
vcoubard	1:ebc0e0ef0a11	4964	/* Register: RADIO_RXCRC */
vcoubard	1:ebc0e0ef0a11	4965	/* Description: Received CRC. */
vcoubard	1:ebc0e0ef0a11	4966
vcoubard	1:ebc0e0ef0a11	4967	/* Bits 23..0 : CRC field of previously received packet. */
vcoubard	1:ebc0e0ef0a11	4968	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
vcoubard	1:ebc0e0ef0a11	4969	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
vcoubard	1:ebc0e0ef0a11	4970
vcoubard	1:ebc0e0ef0a11	4971	/* Register: RADIO_DAI */
vcoubard	1:ebc0e0ef0a11	4972	/* Description: Device address match index. */
vcoubard	1:ebc0e0ef0a11	4973
vcoubard	1:ebc0e0ef0a11	4974	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
vcoubard	1:ebc0e0ef0a11	4975	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
vcoubard	1:ebc0e0ef0a11	4976	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
vcoubard	1:ebc0e0ef0a11	4977
vcoubard	1:ebc0e0ef0a11	4978	/* Register: RADIO_FREQUENCY */
vcoubard	1:ebc0e0ef0a11	4979	/* Description: Frequency. */
vcoubard	1:ebc0e0ef0a11	4980
vcoubard	1:ebc0e0ef0a11	4981	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
vcoubard	1:ebc0e0ef0a11	4982	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	1:ebc0e0ef0a11	4983	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	1:ebc0e0ef0a11	4984
vcoubard	1:ebc0e0ef0a11	4985	/* Register: RADIO_TXPOWER */
vcoubard	1:ebc0e0ef0a11	4986	/* Description: Output power. */
vcoubard	1:ebc0e0ef0a11	4987
vcoubard	1:ebc0e0ef0a11	4988	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
vcoubard	1:ebc0e0ef0a11	4989	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
vcoubard	1:ebc0e0ef0a11	4990	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
vcoubard	1:ebc0e0ef0a11	4991	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
vcoubard	1:ebc0e0ef0a11	4992	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
vcoubard	1:ebc0e0ef0a11	4993	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
vcoubard	1:ebc0e0ef0a11	4994	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
vcoubard	1:ebc0e0ef0a11	4995	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
vcoubard	1:ebc0e0ef0a11	4996	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
vcoubard	1:ebc0e0ef0a11	4997	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
vcoubard	1:ebc0e0ef0a11	4998	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
vcoubard	1:ebc0e0ef0a11	4999
vcoubard	1:ebc0e0ef0a11	5000	/* Register: RADIO_MODE */
vcoubard	1:ebc0e0ef0a11	5001	/* Description: Data rate and modulation. */
vcoubard	1:ebc0e0ef0a11	5002
vcoubard	1:ebc0e0ef0a11	5003	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
vcoubard	1:ebc0e0ef0a11	5004	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	1:ebc0e0ef0a11	5005	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	1:ebc0e0ef0a11	5006	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
vcoubard	1:ebc0e0ef0a11	5007	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
vcoubard	1:ebc0e0ef0a11	5008	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
vcoubard	1:ebc0e0ef0a11	5009	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
vcoubard	1:ebc0e0ef0a11	5010
vcoubard	1:ebc0e0ef0a11	5011	/* Register: RADIO_PCNF0 */
vcoubard	1:ebc0e0ef0a11	5012	/* Description: Packet configuration 0. */
vcoubard	1:ebc0e0ef0a11	5013
vcoubard	1:ebc0e0ef0a11	5014	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5015	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
vcoubard	1:ebc0e0ef0a11	5016	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
vcoubard	1:ebc0e0ef0a11	5017
vcoubard	1:ebc0e0ef0a11	5018	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5019	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
vcoubard	1:ebc0e0ef0a11	5020	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
vcoubard	1:ebc0e0ef0a11	5021
vcoubard	1:ebc0e0ef0a11	5022	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5023	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
vcoubard	1:ebc0e0ef0a11	5024	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
vcoubard	1:ebc0e0ef0a11	5025
vcoubard	1:ebc0e0ef0a11	5026	/* Register: RADIO_PCNF1 */
vcoubard	1:ebc0e0ef0a11	5027	/* Description: Packet configuration 1. */
vcoubard	1:ebc0e0ef0a11	5028
vcoubard	1:ebc0e0ef0a11	5029	/* Bit 25 : Packet whitening enable. */
vcoubard	1:ebc0e0ef0a11	5030	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
vcoubard	1:ebc0e0ef0a11	5031	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
vcoubard	1:ebc0e0ef0a11	5032	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
vcoubard	1:ebc0e0ef0a11	5033	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
vcoubard	1:ebc0e0ef0a11	5034
vcoubard	1:ebc0e0ef0a11	5035	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5036	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
vcoubard	1:ebc0e0ef0a11	5037	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
vcoubard	1:ebc0e0ef0a11	5038	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
vcoubard	1:ebc0e0ef0a11	5039	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
vcoubard	1:ebc0e0ef0a11	5040
vcoubard	1:ebc0e0ef0a11	5041	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5042	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
vcoubard	1:ebc0e0ef0a11	5043	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
vcoubard	1:ebc0e0ef0a11	5044
vcoubard	1:ebc0e0ef0a11	5045	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5046	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
vcoubard	1:ebc0e0ef0a11	5047	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
vcoubard	1:ebc0e0ef0a11	5048
vcoubard	1:ebc0e0ef0a11	5049	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
vcoubard	1:ebc0e0ef0a11	5050	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
vcoubard	1:ebc0e0ef0a11	5051	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
vcoubard	1:ebc0e0ef0a11	5052
vcoubard	1:ebc0e0ef0a11	5053	/* Register: RADIO_PREFIX0 */
vcoubard	1:ebc0e0ef0a11	5054	/* Description: Prefixes bytes for logical addresses 0 to 3. */
vcoubard	1:ebc0e0ef0a11	5055
vcoubard	1:ebc0e0ef0a11	5056	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5057	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
vcoubard	1:ebc0e0ef0a11	5058	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
vcoubard	1:ebc0e0ef0a11	5059
vcoubard	1:ebc0e0ef0a11	5060	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5061	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
vcoubard	1:ebc0e0ef0a11	5062	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
vcoubard	1:ebc0e0ef0a11	5063
vcoubard	1:ebc0e0ef0a11	5064	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5065	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
vcoubard	1:ebc0e0ef0a11	5066	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
vcoubard	1:ebc0e0ef0a11	5067
vcoubard	1:ebc0e0ef0a11	5068	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5069	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
vcoubard	1:ebc0e0ef0a11	5070	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
vcoubard	1:ebc0e0ef0a11	5071
vcoubard	1:ebc0e0ef0a11	5072	/* Register: RADIO_PREFIX1 */
vcoubard	1:ebc0e0ef0a11	5073	/* Description: Prefixes bytes for logical addresses 4 to 7. */
vcoubard	1:ebc0e0ef0a11	5074
vcoubard	1:ebc0e0ef0a11	5075	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5076	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
vcoubard	1:ebc0e0ef0a11	5077	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
vcoubard	1:ebc0e0ef0a11	5078
vcoubard	1:ebc0e0ef0a11	5079	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5080	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
vcoubard	1:ebc0e0ef0a11	5081	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
vcoubard	1:ebc0e0ef0a11	5082
vcoubard	1:ebc0e0ef0a11	5083	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5084	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
vcoubard	1:ebc0e0ef0a11	5085	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
vcoubard	1:ebc0e0ef0a11	5086
vcoubard	1:ebc0e0ef0a11	5087	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5088	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
vcoubard	1:ebc0e0ef0a11	5089	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
vcoubard	1:ebc0e0ef0a11	5090
vcoubard	1:ebc0e0ef0a11	5091	/* Register: RADIO_TXADDRESS */
vcoubard	1:ebc0e0ef0a11	5092	/* Description: Transmit address select. */
vcoubard	1:ebc0e0ef0a11	5093
vcoubard	1:ebc0e0ef0a11	5094	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5095	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
vcoubard	1:ebc0e0ef0a11	5096	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
vcoubard	1:ebc0e0ef0a11	5097
vcoubard	1:ebc0e0ef0a11	5098	/* Register: RADIO_RXADDRESSES */
vcoubard	1:ebc0e0ef0a11	5099	/* Description: Receive address select. */
vcoubard	1:ebc0e0ef0a11	5100
vcoubard	1:ebc0e0ef0a11	5101	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5102	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
vcoubard	1:ebc0e0ef0a11	5103	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
vcoubard	1:ebc0e0ef0a11	5104	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
vcoubard	1:ebc0e0ef0a11	5105	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
vcoubard	1:ebc0e0ef0a11	5106
vcoubard	1:ebc0e0ef0a11	5107	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5108	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
vcoubard	1:ebc0e0ef0a11	5109	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
vcoubard	1:ebc0e0ef0a11	5110	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
vcoubard	1:ebc0e0ef0a11	5111	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
vcoubard	1:ebc0e0ef0a11	5112
vcoubard	1:ebc0e0ef0a11	5113	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5114	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
vcoubard	1:ebc0e0ef0a11	5115	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
vcoubard	1:ebc0e0ef0a11	5116	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
vcoubard	1:ebc0e0ef0a11	5117	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
vcoubard	1:ebc0e0ef0a11	5118
vcoubard	1:ebc0e0ef0a11	5119	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5120	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
vcoubard	1:ebc0e0ef0a11	5121	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
vcoubard	1:ebc0e0ef0a11	5122	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
vcoubard	1:ebc0e0ef0a11	5123	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
vcoubard	1:ebc0e0ef0a11	5124
vcoubard	1:ebc0e0ef0a11	5125	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5126	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
vcoubard	1:ebc0e0ef0a11	5127	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
vcoubard	1:ebc0e0ef0a11	5128	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
vcoubard	1:ebc0e0ef0a11	5129	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
vcoubard	1:ebc0e0ef0a11	5130
vcoubard	1:ebc0e0ef0a11	5131	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5132	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
vcoubard	1:ebc0e0ef0a11	5133	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
vcoubard	1:ebc0e0ef0a11	5134	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
vcoubard	1:ebc0e0ef0a11	5135	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
vcoubard	1:ebc0e0ef0a11	5136
vcoubard	1:ebc0e0ef0a11	5137	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5138	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
vcoubard	1:ebc0e0ef0a11	5139	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
vcoubard	1:ebc0e0ef0a11	5140	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
vcoubard	1:ebc0e0ef0a11	5141	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
vcoubard	1:ebc0e0ef0a11	5142
vcoubard	1:ebc0e0ef0a11	5143	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5144	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
vcoubard	1:ebc0e0ef0a11	5145	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
vcoubard	1:ebc0e0ef0a11	5146	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
vcoubard	1:ebc0e0ef0a11	5147	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
vcoubard	1:ebc0e0ef0a11	5148
vcoubard	1:ebc0e0ef0a11	5149	/* Register: RADIO_CRCCNF */
vcoubard	1:ebc0e0ef0a11	5150	/* Description: CRC configuration. */
vcoubard	1:ebc0e0ef0a11	5151
vcoubard	1:ebc0e0ef0a11	5152	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5153	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
vcoubard	1:ebc0e0ef0a11	5154	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
vcoubard	1:ebc0e0ef0a11	5155	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
vcoubard	1:ebc0e0ef0a11	5156	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
vcoubard	1:ebc0e0ef0a11	5157
vcoubard	1:ebc0e0ef0a11	5158	/* Bits 1..0 : CRC length. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5159	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
vcoubard	1:ebc0e0ef0a11	5160	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
vcoubard	1:ebc0e0ef0a11	5161	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
vcoubard	1:ebc0e0ef0a11	5162	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
vcoubard	1:ebc0e0ef0a11	5163	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
vcoubard	1:ebc0e0ef0a11	5164	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
vcoubard	1:ebc0e0ef0a11	5165
vcoubard	1:ebc0e0ef0a11	5166	/* Register: RADIO_CRCPOLY */
vcoubard	1:ebc0e0ef0a11	5167	/* Description: CRC polynomial. */
vcoubard	1:ebc0e0ef0a11	5168
vcoubard	1:ebc0e0ef0a11	5169	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5170	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
vcoubard	1:ebc0e0ef0a11	5171	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
vcoubard	1:ebc0e0ef0a11	5172
vcoubard	1:ebc0e0ef0a11	5173	/* Register: RADIO_CRCINIT */
vcoubard	1:ebc0e0ef0a11	5174	/* Description: CRC initial value. */
vcoubard	1:ebc0e0ef0a11	5175
vcoubard	1:ebc0e0ef0a11	5176	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
vcoubard	1:ebc0e0ef0a11	5177	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
vcoubard	1:ebc0e0ef0a11	5178	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
vcoubard	1:ebc0e0ef0a11	5179
vcoubard	1:ebc0e0ef0a11	5180	/* Register: RADIO_TEST */
vcoubard	1:ebc0e0ef0a11	5181	/* Description: Test features enable register. */
vcoubard	1:ebc0e0ef0a11	5182
vcoubard	1:ebc0e0ef0a11	5183	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
vcoubard	1:ebc0e0ef0a11	5184	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
vcoubard	1:ebc0e0ef0a11	5185	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
vcoubard	1:ebc0e0ef0a11	5186	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
vcoubard	1:ebc0e0ef0a11	5187	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
vcoubard	1:ebc0e0ef0a11	5188
vcoubard	1:ebc0e0ef0a11	5189	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
vcoubard	1:ebc0e0ef0a11	5190	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
vcoubard	1:ebc0e0ef0a11	5191	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
vcoubard	1:ebc0e0ef0a11	5192	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
vcoubard	1:ebc0e0ef0a11	5193	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
vcoubard	1:ebc0e0ef0a11	5194
vcoubard	1:ebc0e0ef0a11	5195	/* Register: RADIO_TIFS */
vcoubard	1:ebc0e0ef0a11	5196	/* Description: Inter Frame Spacing in microseconds. */
vcoubard	1:ebc0e0ef0a11	5197
vcoubard	1:ebc0e0ef0a11	5198	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
vcoubard	1:ebc0e0ef0a11	5199	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
vcoubard	1:ebc0e0ef0a11	5200	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
vcoubard	1:ebc0e0ef0a11	5201
vcoubard	1:ebc0e0ef0a11	5202	/* Register: RADIO_RSSISAMPLE */
vcoubard	1:ebc0e0ef0a11	5203	/* Description: RSSI sample. */
vcoubard	1:ebc0e0ef0a11	5204
vcoubard	1:ebc0e0ef0a11	5205	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
vcoubard	1:ebc0e0ef0a11	5206	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
vcoubard	1:ebc0e0ef0a11	5207	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
vcoubard	1:ebc0e0ef0a11	5208
vcoubard	1:ebc0e0ef0a11	5209	/* Register: RADIO_STATE */
vcoubard	1:ebc0e0ef0a11	5210	/* Description: Current radio state. */
vcoubard	1:ebc0e0ef0a11	5211
vcoubard	1:ebc0e0ef0a11	5212	/* Bits 3..0 : Current radio state. */
vcoubard	1:ebc0e0ef0a11	5213	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
vcoubard	1:ebc0e0ef0a11	5214	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	1:ebc0e0ef0a11	5215	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
vcoubard	1:ebc0e0ef0a11	5216	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
vcoubard	1:ebc0e0ef0a11	5217	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
vcoubard	1:ebc0e0ef0a11	5218	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
vcoubard	1:ebc0e0ef0a11	5219	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
vcoubard	1:ebc0e0ef0a11	5220	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
vcoubard	1:ebc0e0ef0a11	5221	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
vcoubard	1:ebc0e0ef0a11	5222	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
vcoubard	1:ebc0e0ef0a11	5223	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
vcoubard	1:ebc0e0ef0a11	5224
vcoubard	1:ebc0e0ef0a11	5225	/* Register: RADIO_DATAWHITEIV */
vcoubard	1:ebc0e0ef0a11	5226	/* Description: Data whitening initial value. */
vcoubard	1:ebc0e0ef0a11	5227
vcoubard	1:ebc0e0ef0a11	5228	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
vcoubard	1:ebc0e0ef0a11	5229	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
vcoubard	1:ebc0e0ef0a11	5230	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
vcoubard	1:ebc0e0ef0a11	5231
vcoubard	1:ebc0e0ef0a11	5232	/* Register: RADIO_DAP */
vcoubard	1:ebc0e0ef0a11	5233	/* Description: Device address prefix. */
vcoubard	1:ebc0e0ef0a11	5234
vcoubard	1:ebc0e0ef0a11	5235	/* Bits 15..0 : Device address prefix. */
vcoubard	1:ebc0e0ef0a11	5236	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
vcoubard	1:ebc0e0ef0a11	5237	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
vcoubard	1:ebc0e0ef0a11	5238
vcoubard	1:ebc0e0ef0a11	5239	/* Register: RADIO_DACNF */
vcoubard	1:ebc0e0ef0a11	5240	/* Description: Device address match configuration. */
vcoubard	1:ebc0e0ef0a11	5241
vcoubard	1:ebc0e0ef0a11	5242	/* Bit 15 : TxAdd for device address 7. */
vcoubard	1:ebc0e0ef0a11	5243	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
vcoubard	1:ebc0e0ef0a11	5244	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
vcoubard	1:ebc0e0ef0a11	5245
vcoubard	1:ebc0e0ef0a11	5246	/* Bit 14 : TxAdd for device address 6. */
vcoubard	1:ebc0e0ef0a11	5247	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
vcoubard	1:ebc0e0ef0a11	5248	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
vcoubard	1:ebc0e0ef0a11	5249
vcoubard	1:ebc0e0ef0a11	5250	/* Bit 13 : TxAdd for device address 5. */
vcoubard	1:ebc0e0ef0a11	5251	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
vcoubard	1:ebc0e0ef0a11	5252	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
vcoubard	1:ebc0e0ef0a11	5253
vcoubard	1:ebc0e0ef0a11	5254	/* Bit 12 : TxAdd for device address 4. */
vcoubard	1:ebc0e0ef0a11	5255	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
vcoubard	1:ebc0e0ef0a11	5256	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
vcoubard	1:ebc0e0ef0a11	5257
vcoubard	1:ebc0e0ef0a11	5258	/* Bit 11 : TxAdd for device address 3. */
vcoubard	1:ebc0e0ef0a11	5259	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
vcoubard	1:ebc0e0ef0a11	5260	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
vcoubard	1:ebc0e0ef0a11	5261
vcoubard	1:ebc0e0ef0a11	5262	/* Bit 10 : TxAdd for device address 2. */
vcoubard	1:ebc0e0ef0a11	5263	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
vcoubard	1:ebc0e0ef0a11	5264	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
vcoubard	1:ebc0e0ef0a11	5265
vcoubard	1:ebc0e0ef0a11	5266	/* Bit 9 : TxAdd for device address 1. */
vcoubard	1:ebc0e0ef0a11	5267	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
vcoubard	1:ebc0e0ef0a11	5268	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
vcoubard	1:ebc0e0ef0a11	5269
vcoubard	1:ebc0e0ef0a11	5270	/* Bit 8 : TxAdd for device address 0. */
vcoubard	1:ebc0e0ef0a11	5271	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
vcoubard	1:ebc0e0ef0a11	5272	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
vcoubard	1:ebc0e0ef0a11	5273
vcoubard	1:ebc0e0ef0a11	5274	/* Bit 7 : Enable or disable device address matching using device address 7. */
vcoubard	1:ebc0e0ef0a11	5275	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
vcoubard	1:ebc0e0ef0a11	5276	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
vcoubard	1:ebc0e0ef0a11	5277	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	5278	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	5279
vcoubard	1:ebc0e0ef0a11	5280	/* Bit 6 : Enable or disable device address matching using device address 6. */
vcoubard	1:ebc0e0ef0a11	5281	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
vcoubard	1:ebc0e0ef0a11	5282	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
vcoubard	1:ebc0e0ef0a11	5283	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	5284	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	5285
vcoubard	1:ebc0e0ef0a11	5286	/* Bit 5 : Enable or disable device address matching using device address 5. */
vcoubard	1:ebc0e0ef0a11	5287	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
vcoubard	1:ebc0e0ef0a11	5288	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
vcoubard	1:ebc0e0ef0a11	5289	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	5290	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	5291
vcoubard	1:ebc0e0ef0a11	5292	/* Bit 4 : Enable or disable device address matching using device address 4. */
vcoubard	1:ebc0e0ef0a11	5293	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
vcoubard	1:ebc0e0ef0a11	5294	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
vcoubard	1:ebc0e0ef0a11	5295	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	5296	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	5297
vcoubard	1:ebc0e0ef0a11	5298	/* Bit 3 : Enable or disable device address matching using device address 3. */
vcoubard	1:ebc0e0ef0a11	5299	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
vcoubard	1:ebc0e0ef0a11	5300	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
vcoubard	1:ebc0e0ef0a11	5301	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	5302	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	5303
vcoubard	1:ebc0e0ef0a11	5304	/* Bit 2 : Enable or disable device address matching using device address 2. */
vcoubard	1:ebc0e0ef0a11	5305	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
vcoubard	1:ebc0e0ef0a11	5306	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
vcoubard	1:ebc0e0ef0a11	5307	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	5308	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	5309
vcoubard	1:ebc0e0ef0a11	5310	/* Bit 1 : Enable or disable device address matching using device address 1. */
vcoubard	1:ebc0e0ef0a11	5311	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
vcoubard	1:ebc0e0ef0a11	5312	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
vcoubard	1:ebc0e0ef0a11	5313	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	5314	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	5315
vcoubard	1:ebc0e0ef0a11	5316	/* Bit 0 : Enable or disable device address matching using device address 0. */
vcoubard	1:ebc0e0ef0a11	5317	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
vcoubard	1:ebc0e0ef0a11	5318	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
vcoubard	1:ebc0e0ef0a11	5319	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	5320	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	5321
vcoubard	1:ebc0e0ef0a11	5322	/* Register: RADIO_OVERRIDE0 */
vcoubard	1:ebc0e0ef0a11	5323	/* Description: Trim value override register 0. */
vcoubard	1:ebc0e0ef0a11	5324
vcoubard	1:ebc0e0ef0a11	5325	/* Bits 31..0 : Trim value override 0. */
vcoubard	1:ebc0e0ef0a11	5326	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
vcoubard	1:ebc0e0ef0a11	5327	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
vcoubard	1:ebc0e0ef0a11	5328
vcoubard	1:ebc0e0ef0a11	5329	/* Register: RADIO_OVERRIDE1 */
vcoubard	1:ebc0e0ef0a11	5330	/* Description: Trim value override register 1. */
vcoubard	1:ebc0e0ef0a11	5331
vcoubard	1:ebc0e0ef0a11	5332	/* Bits 31..0 : Trim value override 1. */
vcoubard	1:ebc0e0ef0a11	5333	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
vcoubard	1:ebc0e0ef0a11	5334	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
vcoubard	1:ebc0e0ef0a11	5335
vcoubard	1:ebc0e0ef0a11	5336	/* Register: RADIO_OVERRIDE2 */
vcoubard	1:ebc0e0ef0a11	5337	/* Description: Trim value override register 2. */
vcoubard	1:ebc0e0ef0a11	5338
vcoubard	1:ebc0e0ef0a11	5339	/* Bits 31..0 : Trim value override 2. */
vcoubard	1:ebc0e0ef0a11	5340	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
vcoubard	1:ebc0e0ef0a11	5341	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
vcoubard	1:ebc0e0ef0a11	5342
vcoubard	1:ebc0e0ef0a11	5343	/* Register: RADIO_OVERRIDE3 */
vcoubard	1:ebc0e0ef0a11	5344	/* Description: Trim value override register 3. */
vcoubard	1:ebc0e0ef0a11	5345
vcoubard	1:ebc0e0ef0a11	5346	/* Bits 31..0 : Trim value override 3. */
vcoubard	1:ebc0e0ef0a11	5347	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
vcoubard	1:ebc0e0ef0a11	5348	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
vcoubard	1:ebc0e0ef0a11	5349
vcoubard	1:ebc0e0ef0a11	5350	/* Register: RADIO_OVERRIDE4 */
vcoubard	1:ebc0e0ef0a11	5351	/* Description: Trim value override register 4. */
vcoubard	1:ebc0e0ef0a11	5352
vcoubard	1:ebc0e0ef0a11	5353	/* Bit 31 : Enable or disable override of default trim values. */
vcoubard	1:ebc0e0ef0a11	5354	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	5355	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	5356	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
vcoubard	1:ebc0e0ef0a11	5357	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
vcoubard	1:ebc0e0ef0a11	5358
vcoubard	1:ebc0e0ef0a11	5359	/* Bits 27..0 : Trim value override 4. */
vcoubard	1:ebc0e0ef0a11	5360	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
vcoubard	1:ebc0e0ef0a11	5361	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
vcoubard	1:ebc0e0ef0a11	5362
vcoubard	1:ebc0e0ef0a11	5363	/* Register: RADIO_POWER */
vcoubard	1:ebc0e0ef0a11	5364	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5365
vcoubard	1:ebc0e0ef0a11	5366	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5367	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	5368	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	5369	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	5370	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	5371
vcoubard	1:ebc0e0ef0a11	5372
vcoubard	1:ebc0e0ef0a11	5373	/* Peripheral: RNG */
vcoubard	1:ebc0e0ef0a11	5374	/* Description: Random Number Generator. */
vcoubard	1:ebc0e0ef0a11	5375
vcoubard	1:ebc0e0ef0a11	5376	/* Register: RNG_SHORTS */
vcoubard	1:ebc0e0ef0a11	5377	/* Description: Shortcuts for the RNG. */
vcoubard	1:ebc0e0ef0a11	5378
vcoubard	1:ebc0e0ef0a11	5379	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
vcoubard	1:ebc0e0ef0a11	5380	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
vcoubard	1:ebc0e0ef0a11	5381	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
vcoubard	1:ebc0e0ef0a11	5382	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	5383	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	5384
vcoubard	1:ebc0e0ef0a11	5385	/* Register: RNG_INTENSET */
vcoubard	1:ebc0e0ef0a11	5386	/* Description: Interrupt enable set register */
vcoubard	1:ebc0e0ef0a11	5387
vcoubard	1:ebc0e0ef0a11	5388	/* Bit 0 : Enable interrupt on VALRDY event. */
vcoubard	1:ebc0e0ef0a11	5389	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
vcoubard	1:ebc0e0ef0a11	5390	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
vcoubard	1:ebc0e0ef0a11	5391	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5392	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5393	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5394
vcoubard	1:ebc0e0ef0a11	5395	/* Register: RNG_INTENCLR */
vcoubard	1:ebc0e0ef0a11	5396	/* Description: Interrupt enable clear register */
vcoubard	1:ebc0e0ef0a11	5397
vcoubard	1:ebc0e0ef0a11	5398	/* Bit 0 : Disable interrupt on VALRDY event. */
vcoubard	1:ebc0e0ef0a11	5399	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
vcoubard	1:ebc0e0ef0a11	5400	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
vcoubard	1:ebc0e0ef0a11	5401	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5402	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5403	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5404
vcoubard	1:ebc0e0ef0a11	5405	/* Register: RNG_CONFIG */
vcoubard	1:ebc0e0ef0a11	5406	/* Description: Configuration register. */
vcoubard	1:ebc0e0ef0a11	5407
vcoubard	1:ebc0e0ef0a11	5408	/* Bit 0 : Digital error correction enable. */
vcoubard	1:ebc0e0ef0a11	5409	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
vcoubard	1:ebc0e0ef0a11	5410	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
vcoubard	1:ebc0e0ef0a11	5411	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
vcoubard	1:ebc0e0ef0a11	5412	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
vcoubard	1:ebc0e0ef0a11	5413
vcoubard	1:ebc0e0ef0a11	5414	/* Register: RNG_VALUE */
vcoubard	1:ebc0e0ef0a11	5415	/* Description: RNG random number. */
vcoubard	1:ebc0e0ef0a11	5416
vcoubard	1:ebc0e0ef0a11	5417	/* Bits 7..0 : Generated random number. */
vcoubard	1:ebc0e0ef0a11	5418	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
vcoubard	1:ebc0e0ef0a11	5419	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
vcoubard	1:ebc0e0ef0a11	5420
vcoubard	1:ebc0e0ef0a11	5421	/* Register: RNG_POWER */
vcoubard	1:ebc0e0ef0a11	5422	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5423
vcoubard	1:ebc0e0ef0a11	5424	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5425	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	5426	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	5427	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	5428	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	5429
vcoubard	1:ebc0e0ef0a11	5430
vcoubard	1:ebc0e0ef0a11	5431	/* Peripheral: RTC */
vcoubard	1:ebc0e0ef0a11	5432	/* Description: Real time counter 0. */
vcoubard	1:ebc0e0ef0a11	5433
vcoubard	1:ebc0e0ef0a11	5434	/* Register: RTC_INTENSET */
vcoubard	1:ebc0e0ef0a11	5435	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	5436
vcoubard	1:ebc0e0ef0a11	5437	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
vcoubard	1:ebc0e0ef0a11	5438	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5439	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5440	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5441	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5442	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5443
vcoubard	1:ebc0e0ef0a11	5444	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
vcoubard	1:ebc0e0ef0a11	5445	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5446	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5447	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5448	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5449	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5450
vcoubard	1:ebc0e0ef0a11	5451	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
vcoubard	1:ebc0e0ef0a11	5452	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5453	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5454	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5455	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5456	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5457
vcoubard	1:ebc0e0ef0a11	5458	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
vcoubard	1:ebc0e0ef0a11	5459	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5460	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5461	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5462	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5463	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5464
vcoubard	1:ebc0e0ef0a11	5465	/* Bit 1 : Enable interrupt on OVRFLW event. */
vcoubard	1:ebc0e0ef0a11	5466	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5467	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5468	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5469	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5470	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5471
vcoubard	1:ebc0e0ef0a11	5472	/* Bit 0 : Enable interrupt on TICK event. */
vcoubard	1:ebc0e0ef0a11	5473	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	1:ebc0e0ef0a11	5474	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	1:ebc0e0ef0a11	5475	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5476	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5477	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5478
vcoubard	1:ebc0e0ef0a11	5479	/* Register: RTC_INTENCLR */
vcoubard	1:ebc0e0ef0a11	5480	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	5481
vcoubard	1:ebc0e0ef0a11	5482	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
vcoubard	1:ebc0e0ef0a11	5483	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5484	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5485	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5486	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5487	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5488
vcoubard	1:ebc0e0ef0a11	5489	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
vcoubard	1:ebc0e0ef0a11	5490	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5491	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5492	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5493	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5494	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5495
vcoubard	1:ebc0e0ef0a11	5496	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
vcoubard	1:ebc0e0ef0a11	5497	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5498	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5499	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5500	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5501	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5502
vcoubard	1:ebc0e0ef0a11	5503	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
vcoubard	1:ebc0e0ef0a11	5504	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5505	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5506	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5507	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5508	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5509
vcoubard	1:ebc0e0ef0a11	5510	/* Bit 1 : Disable interrupt on OVRFLW event. */
vcoubard	1:ebc0e0ef0a11	5511	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5512	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5513	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5514	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5515	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5516
vcoubard	1:ebc0e0ef0a11	5517	/* Bit 0 : Disable interrupt on TICK event. */
vcoubard	1:ebc0e0ef0a11	5518	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	1:ebc0e0ef0a11	5519	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	1:ebc0e0ef0a11	5520	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5521	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5522	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5523
vcoubard	1:ebc0e0ef0a11	5524	/* Register: RTC_EVTEN */
vcoubard	1:ebc0e0ef0a11	5525	/* Description: Configures event enable routing to PPI for each RTC event. */
vcoubard	1:ebc0e0ef0a11	5526
vcoubard	1:ebc0e0ef0a11	5527	/* Bit 19 : COMPARE[3] event enable. */
vcoubard	1:ebc0e0ef0a11	5528	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5529	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5530	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5531	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5532
vcoubard	1:ebc0e0ef0a11	5533	/* Bit 18 : COMPARE[2] event enable. */
vcoubard	1:ebc0e0ef0a11	5534	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5535	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5536	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5537	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5538
vcoubard	1:ebc0e0ef0a11	5539	/* Bit 17 : COMPARE[1] event enable. */
vcoubard	1:ebc0e0ef0a11	5540	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5541	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5542	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5543	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5544
vcoubard	1:ebc0e0ef0a11	5545	/* Bit 16 : COMPARE[0] event enable. */
vcoubard	1:ebc0e0ef0a11	5546	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5547	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5548	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5549	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5550
vcoubard	1:ebc0e0ef0a11	5551	/* Bit 1 : OVRFLW event enable. */
vcoubard	1:ebc0e0ef0a11	5552	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5553	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5554	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5555	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5556
vcoubard	1:ebc0e0ef0a11	5557	/* Bit 0 : TICK event enable. */
vcoubard	1:ebc0e0ef0a11	5558	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	1:ebc0e0ef0a11	5559	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	1:ebc0e0ef0a11	5560	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5561	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5562
vcoubard	1:ebc0e0ef0a11	5563	/* Register: RTC_EVTENSET */
vcoubard	1:ebc0e0ef0a11	5564	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
vcoubard	1:ebc0e0ef0a11	5565
vcoubard	1:ebc0e0ef0a11	5566	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
vcoubard	1:ebc0e0ef0a11	5567	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5568	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5569	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5570	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5571	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
vcoubard	1:ebc0e0ef0a11	5572
vcoubard	1:ebc0e0ef0a11	5573	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
vcoubard	1:ebc0e0ef0a11	5574	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5575	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5576	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5577	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5578	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
vcoubard	1:ebc0e0ef0a11	5579
vcoubard	1:ebc0e0ef0a11	5580	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
vcoubard	1:ebc0e0ef0a11	5581	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5582	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5583	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5584	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5585	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
vcoubard	1:ebc0e0ef0a11	5586
vcoubard	1:ebc0e0ef0a11	5587	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
vcoubard	1:ebc0e0ef0a11	5588	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5589	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5590	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5591	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5592	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
vcoubard	1:ebc0e0ef0a11	5593
vcoubard	1:ebc0e0ef0a11	5594	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
vcoubard	1:ebc0e0ef0a11	5595	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5596	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5597	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5598	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5599	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
vcoubard	1:ebc0e0ef0a11	5600
vcoubard	1:ebc0e0ef0a11	5601	/* Bit 0 : Enable routing to PPI of TICK event. */
vcoubard	1:ebc0e0ef0a11	5602	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	1:ebc0e0ef0a11	5603	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	1:ebc0e0ef0a11	5604	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5605	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5606	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
vcoubard	1:ebc0e0ef0a11	5607
vcoubard	1:ebc0e0ef0a11	5608	/* Register: RTC_EVTENCLR */
vcoubard	1:ebc0e0ef0a11	5609	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
vcoubard	1:ebc0e0ef0a11	5610
vcoubard	1:ebc0e0ef0a11	5611	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
vcoubard	1:ebc0e0ef0a11	5612	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5613	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	5614	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5615	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5616	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
vcoubard	1:ebc0e0ef0a11	5617
vcoubard	1:ebc0e0ef0a11	5618	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
vcoubard	1:ebc0e0ef0a11	5619	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5620	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	5621	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5622	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5623	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
vcoubard	1:ebc0e0ef0a11	5624
vcoubard	1:ebc0e0ef0a11	5625	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
vcoubard	1:ebc0e0ef0a11	5626	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5627	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	5628	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5629	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5630	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
vcoubard	1:ebc0e0ef0a11	5631
vcoubard	1:ebc0e0ef0a11	5632	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
vcoubard	1:ebc0e0ef0a11	5633	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5634	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	5635	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5636	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5637	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
vcoubard	1:ebc0e0ef0a11	5638
vcoubard	1:ebc0e0ef0a11	5639	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
vcoubard	1:ebc0e0ef0a11	5640	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5641	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	1:ebc0e0ef0a11	5642	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5643	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5644	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
vcoubard	1:ebc0e0ef0a11	5645
vcoubard	1:ebc0e0ef0a11	5646	/* Bit 0 : Disable routing to PPI of TICK event. */
vcoubard	1:ebc0e0ef0a11	5647	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	1:ebc0e0ef0a11	5648	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	1:ebc0e0ef0a11	5649	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	1:ebc0e0ef0a11	5650	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	1:ebc0e0ef0a11	5651	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
vcoubard	1:ebc0e0ef0a11	5652
vcoubard	1:ebc0e0ef0a11	5653	/* Register: RTC_COUNTER */
vcoubard	1:ebc0e0ef0a11	5654	/* Description: Current COUNTER value. */
vcoubard	1:ebc0e0ef0a11	5655
vcoubard	1:ebc0e0ef0a11	5656	/* Bits 23..0 : Counter value. */
vcoubard	1:ebc0e0ef0a11	5657	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
vcoubard	1:ebc0e0ef0a11	5658	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
vcoubard	1:ebc0e0ef0a11	5659
vcoubard	1:ebc0e0ef0a11	5660	/* Register: RTC_PRESCALER */
vcoubard	1:ebc0e0ef0a11	5661	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
vcoubard	1:ebc0e0ef0a11	5662
vcoubard	1:ebc0e0ef0a11	5663	/* Bits 11..0 : RTC PRESCALER value. */
vcoubard	1:ebc0e0ef0a11	5664	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
vcoubard	1:ebc0e0ef0a11	5665	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
vcoubard	1:ebc0e0ef0a11	5666
vcoubard	1:ebc0e0ef0a11	5667	/* Register: RTC_CC */
vcoubard	1:ebc0e0ef0a11	5668	/* Description: Capture/compare registers. */
vcoubard	1:ebc0e0ef0a11	5669
vcoubard	1:ebc0e0ef0a11	5670	/* Bits 23..0 : Compare value. */
vcoubard	1:ebc0e0ef0a11	5671	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
vcoubard	1:ebc0e0ef0a11	5672	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
vcoubard	1:ebc0e0ef0a11	5673
vcoubard	1:ebc0e0ef0a11	5674	/* Register: RTC_POWER */
vcoubard	1:ebc0e0ef0a11	5675	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5676
vcoubard	1:ebc0e0ef0a11	5677	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5678	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	5679	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	5680	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	5681	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	5682
vcoubard	1:ebc0e0ef0a11	5683
vcoubard	1:ebc0e0ef0a11	5684	/* Peripheral: SPI */
vcoubard	1:ebc0e0ef0a11	5685	/* Description: SPI master 0. */
vcoubard	1:ebc0e0ef0a11	5686
vcoubard	1:ebc0e0ef0a11	5687	/* Register: SPI_INTENSET */
vcoubard	1:ebc0e0ef0a11	5688	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	5689
vcoubard	1:ebc0e0ef0a11	5690	/* Bit 2 : Enable interrupt on READY event. */
vcoubard	1:ebc0e0ef0a11	5691	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
vcoubard	1:ebc0e0ef0a11	5692	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	1:ebc0e0ef0a11	5693	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5694	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5695	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5696
vcoubard	1:ebc0e0ef0a11	5697	/* Register: SPI_INTENCLR */
vcoubard	1:ebc0e0ef0a11	5698	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	5699
vcoubard	1:ebc0e0ef0a11	5700	/* Bit 2 : Disable interrupt on READY event. */
vcoubard	1:ebc0e0ef0a11	5701	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
vcoubard	1:ebc0e0ef0a11	5702	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	1:ebc0e0ef0a11	5703	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5704	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5705	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5706
vcoubard	1:ebc0e0ef0a11	5707	/* Register: SPI_ENABLE */
vcoubard	1:ebc0e0ef0a11	5708	/* Description: Enable SPI. */
vcoubard	1:ebc0e0ef0a11	5709
vcoubard	1:ebc0e0ef0a11	5710	/* Bits 2..0 : Enable or disable SPI. */
vcoubard	1:ebc0e0ef0a11	5711	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	5712	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	5713	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
vcoubard	1:ebc0e0ef0a11	5714	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
vcoubard	1:ebc0e0ef0a11	5715
vcoubard	1:ebc0e0ef0a11	5716	/* Register: SPI_RXD */
vcoubard	1:ebc0e0ef0a11	5717	/* Description: RX data. */
vcoubard	1:ebc0e0ef0a11	5718
vcoubard	1:ebc0e0ef0a11	5719	/* Bits 7..0 : RX data from last transfer. */
vcoubard	1:ebc0e0ef0a11	5720	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	1:ebc0e0ef0a11	5721	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	1:ebc0e0ef0a11	5722
vcoubard	1:ebc0e0ef0a11	5723	/* Register: SPI_TXD */
vcoubard	1:ebc0e0ef0a11	5724	/* Description: TX data. */
vcoubard	1:ebc0e0ef0a11	5725
vcoubard	1:ebc0e0ef0a11	5726	/* Bits 7..0 : TX data for next transfer. */
vcoubard	1:ebc0e0ef0a11	5727	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	1:ebc0e0ef0a11	5728	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	1:ebc0e0ef0a11	5729
vcoubard	1:ebc0e0ef0a11	5730	/* Register: SPI_FREQUENCY */
vcoubard	1:ebc0e0ef0a11	5731	/* Description: SPI frequency */
vcoubard	1:ebc0e0ef0a11	5732
vcoubard	1:ebc0e0ef0a11	5733	/* Bits 31..0 : SPI data rate. */
vcoubard	1:ebc0e0ef0a11	5734	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	1:ebc0e0ef0a11	5735	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	1:ebc0e0ef0a11	5736	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
vcoubard	1:ebc0e0ef0a11	5737	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
vcoubard	1:ebc0e0ef0a11	5738	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
vcoubard	1:ebc0e0ef0a11	5739	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
vcoubard	1:ebc0e0ef0a11	5740	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
vcoubard	1:ebc0e0ef0a11	5741	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
vcoubard	1:ebc0e0ef0a11	5742	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
vcoubard	1:ebc0e0ef0a11	5743
vcoubard	1:ebc0e0ef0a11	5744	/* Register: SPI_CONFIG */
vcoubard	1:ebc0e0ef0a11	5745	/* Description: Configuration register. */
vcoubard	1:ebc0e0ef0a11	5746
vcoubard	1:ebc0e0ef0a11	5747	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	1:ebc0e0ef0a11	5748	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	1:ebc0e0ef0a11	5749	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	1:ebc0e0ef0a11	5750	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	1:ebc0e0ef0a11	5751	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	1:ebc0e0ef0a11	5752
vcoubard	1:ebc0e0ef0a11	5753	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	1:ebc0e0ef0a11	5754	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	1:ebc0e0ef0a11	5755	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	1:ebc0e0ef0a11	5756	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	1:ebc0e0ef0a11	5757	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	1:ebc0e0ef0a11	5758
vcoubard	1:ebc0e0ef0a11	5759	/* Bit 0 : Bit order. */
vcoubard	1:ebc0e0ef0a11	5760	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	1:ebc0e0ef0a11	5761	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	1:ebc0e0ef0a11	5762	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	1:ebc0e0ef0a11	5763	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	1:ebc0e0ef0a11	5764
vcoubard	1:ebc0e0ef0a11	5765	/* Register: SPI_POWER */
vcoubard	1:ebc0e0ef0a11	5766	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5767
vcoubard	1:ebc0e0ef0a11	5768	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5769	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	5770	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	5771	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	5772	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	5773
vcoubard	1:ebc0e0ef0a11	5774
vcoubard	1:ebc0e0ef0a11	5775	/* Peripheral: SPIM */
vcoubard	1:ebc0e0ef0a11	5776	/* Description: SPI master with easyDMA 1. */
vcoubard	1:ebc0e0ef0a11	5777
vcoubard	1:ebc0e0ef0a11	5778	/* Register: SPIM_INTENSET */
vcoubard	1:ebc0e0ef0a11	5779	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	5780
vcoubard	1:ebc0e0ef0a11	5781	/* Bit 19 : Enable interrupt on STARTED event. */
vcoubard	1:ebc0e0ef0a11	5782	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
vcoubard	1:ebc0e0ef0a11	5783	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
vcoubard	1:ebc0e0ef0a11	5784	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5785	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5786	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5787
vcoubard	1:ebc0e0ef0a11	5788	/* Bit 8 : Enable interrupt on ENDTX event. */
vcoubard	1:ebc0e0ef0a11	5789	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
vcoubard	1:ebc0e0ef0a11	5790	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
vcoubard	1:ebc0e0ef0a11	5791	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5792	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5793	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5794
vcoubard	1:ebc0e0ef0a11	5795	/* Bit 4 : Enable interrupt on ENDRX event. */
vcoubard	1:ebc0e0ef0a11	5796	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
vcoubard	1:ebc0e0ef0a11	5797	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
vcoubard	1:ebc0e0ef0a11	5798	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5799	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5800	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5801
vcoubard	1:ebc0e0ef0a11	5802	/* Bit 1 : Enable interrupt on STOPPED event. */
vcoubard	1:ebc0e0ef0a11	5803	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	1:ebc0e0ef0a11	5804	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	1:ebc0e0ef0a11	5805	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5806	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5807	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5808
vcoubard	1:ebc0e0ef0a11	5809	/* Register: SPIM_INTENCLR */
vcoubard	1:ebc0e0ef0a11	5810	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	5811
vcoubard	1:ebc0e0ef0a11	5812	/* Bit 19 : Disable interrupt on STARTED event. */
vcoubard	1:ebc0e0ef0a11	5813	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
vcoubard	1:ebc0e0ef0a11	5814	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
vcoubard	1:ebc0e0ef0a11	5815	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5816	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5817	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5818
vcoubard	1:ebc0e0ef0a11	5819	/* Bit 8 : Disable interrupt on ENDTX event. */
vcoubard	1:ebc0e0ef0a11	5820	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
vcoubard	1:ebc0e0ef0a11	5821	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
vcoubard	1:ebc0e0ef0a11	5822	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5823	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5824	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5825
vcoubard	1:ebc0e0ef0a11	5826	/* Bit 4 : Disable interrupt on ENDRX event. */
vcoubard	1:ebc0e0ef0a11	5827	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
vcoubard	1:ebc0e0ef0a11	5828	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
vcoubard	1:ebc0e0ef0a11	5829	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5830	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5831	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5832
vcoubard	1:ebc0e0ef0a11	5833	/* Bit 1 : Disable interrupt on STOPPED event. */
vcoubard	1:ebc0e0ef0a11	5834	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	1:ebc0e0ef0a11	5835	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	1:ebc0e0ef0a11	5836	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5837	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5838	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5839
vcoubard	1:ebc0e0ef0a11	5840	/* Register: SPIM_ENABLE */
vcoubard	1:ebc0e0ef0a11	5841	/* Description: Enable SPIM. */
vcoubard	1:ebc0e0ef0a11	5842
vcoubard	1:ebc0e0ef0a11	5843	/* Bits 3..0 : Enable or disable SPIM. */
vcoubard	1:ebc0e0ef0a11	5844	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	5845	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	5846	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
vcoubard	1:ebc0e0ef0a11	5847	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
vcoubard	1:ebc0e0ef0a11	5848
vcoubard	1:ebc0e0ef0a11	5849	/* Register: SPIM_FREQUENCY */
vcoubard	1:ebc0e0ef0a11	5850	/* Description: SPI frequency. */
vcoubard	1:ebc0e0ef0a11	5851
vcoubard	1:ebc0e0ef0a11	5852	/* Bits 31..0 : SPI master data rate. */
vcoubard	1:ebc0e0ef0a11	5853	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	1:ebc0e0ef0a11	5854	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	1:ebc0e0ef0a11	5855	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
vcoubard	1:ebc0e0ef0a11	5856	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
vcoubard	1:ebc0e0ef0a11	5857	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
vcoubard	1:ebc0e0ef0a11	5858	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
vcoubard	1:ebc0e0ef0a11	5859	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
vcoubard	1:ebc0e0ef0a11	5860	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
vcoubard	1:ebc0e0ef0a11	5861	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
vcoubard	1:ebc0e0ef0a11	5862
vcoubard	1:ebc0e0ef0a11	5863	/* Register: SPIM_RXD_PTR */
vcoubard	1:ebc0e0ef0a11	5864	/* Description: Data pointer. */
vcoubard	1:ebc0e0ef0a11	5865
vcoubard	1:ebc0e0ef0a11	5866	/* Bits 31..0 : Data pointer. */
vcoubard	1:ebc0e0ef0a11	5867	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
vcoubard	1:ebc0e0ef0a11	5868	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
vcoubard	1:ebc0e0ef0a11	5869
vcoubard	1:ebc0e0ef0a11	5870	/* Register: SPIM_RXD_MAXCNT */
vcoubard	1:ebc0e0ef0a11	5871	/* Description: Maximum number of buffer bytes to receive. */
vcoubard	1:ebc0e0ef0a11	5872
vcoubard	1:ebc0e0ef0a11	5873	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
vcoubard	1:ebc0e0ef0a11	5874	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
vcoubard	1:ebc0e0ef0a11	5875	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
vcoubard	1:ebc0e0ef0a11	5876
vcoubard	1:ebc0e0ef0a11	5877	/* Register: SPIM_RXD_AMOUNT */
vcoubard	1:ebc0e0ef0a11	5878	/* Description: Number of bytes received in the last transaction. */
vcoubard	1:ebc0e0ef0a11	5879
vcoubard	1:ebc0e0ef0a11	5880	/* Bits 7..0 : Number of bytes received in the last transaction. */
vcoubard	1:ebc0e0ef0a11	5881	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
vcoubard	1:ebc0e0ef0a11	5882	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
vcoubard	1:ebc0e0ef0a11	5883
vcoubard	1:ebc0e0ef0a11	5884	/* Register: SPIM_TXD_PTR */
vcoubard	1:ebc0e0ef0a11	5885	/* Description: Data pointer. */
vcoubard	1:ebc0e0ef0a11	5886
vcoubard	1:ebc0e0ef0a11	5887	/* Bits 31..0 : Data pointer. */
vcoubard	1:ebc0e0ef0a11	5888	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
vcoubard	1:ebc0e0ef0a11	5889	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
vcoubard	1:ebc0e0ef0a11	5890
vcoubard	1:ebc0e0ef0a11	5891	/* Register: SPIM_TXD_MAXCNT */
vcoubard	1:ebc0e0ef0a11	5892	/* Description: Maximum number of buffer bytes to send. */
vcoubard	1:ebc0e0ef0a11	5893
vcoubard	1:ebc0e0ef0a11	5894	/* Bits 7..0 : Maximum number of buffer bytes to send. */
vcoubard	1:ebc0e0ef0a11	5895	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
vcoubard	1:ebc0e0ef0a11	5896	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
vcoubard	1:ebc0e0ef0a11	5897
vcoubard	1:ebc0e0ef0a11	5898	/* Register: SPIM_TXD_AMOUNT */
vcoubard	1:ebc0e0ef0a11	5899	/* Description: Number of bytes sent in the last transaction. */
vcoubard	1:ebc0e0ef0a11	5900
vcoubard	1:ebc0e0ef0a11	5901	/* Bits 7..0 : Number of bytes sent in the last transaction. */
vcoubard	1:ebc0e0ef0a11	5902	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
vcoubard	1:ebc0e0ef0a11	5903	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
vcoubard	1:ebc0e0ef0a11	5904
vcoubard	1:ebc0e0ef0a11	5905	/* Register: SPIM_CONFIG */
vcoubard	1:ebc0e0ef0a11	5906	/* Description: Configuration register. */
vcoubard	1:ebc0e0ef0a11	5907
vcoubard	1:ebc0e0ef0a11	5908	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	1:ebc0e0ef0a11	5909	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	1:ebc0e0ef0a11	5910	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	1:ebc0e0ef0a11	5911	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	1:ebc0e0ef0a11	5912	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	1:ebc0e0ef0a11	5913
vcoubard	1:ebc0e0ef0a11	5914	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	1:ebc0e0ef0a11	5915	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	1:ebc0e0ef0a11	5916	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	1:ebc0e0ef0a11	5917	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	1:ebc0e0ef0a11	5918	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	1:ebc0e0ef0a11	5919
vcoubard	1:ebc0e0ef0a11	5920	/* Bit 0 : Bit order. */
vcoubard	1:ebc0e0ef0a11	5921	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	1:ebc0e0ef0a11	5922	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	1:ebc0e0ef0a11	5923	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	1:ebc0e0ef0a11	5924	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	1:ebc0e0ef0a11	5925
vcoubard	1:ebc0e0ef0a11	5926	/* Register: SPIM_ORC */
vcoubard	1:ebc0e0ef0a11	5927	/* Description: Over-read character. */
vcoubard	1:ebc0e0ef0a11	5928
vcoubard	1:ebc0e0ef0a11	5929	/* Bits 7..0 : Over-read character. */
vcoubard	1:ebc0e0ef0a11	5930	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
vcoubard	1:ebc0e0ef0a11	5931	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
vcoubard	1:ebc0e0ef0a11	5932
vcoubard	1:ebc0e0ef0a11	5933	/* Register: SPIM_POWER */
vcoubard	1:ebc0e0ef0a11	5934	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5935
vcoubard	1:ebc0e0ef0a11	5936	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	5937	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	5938	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	5939	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	5940	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	5941
vcoubard	1:ebc0e0ef0a11	5942
vcoubard	1:ebc0e0ef0a11	5943	/* Peripheral: SPIS */
vcoubard	1:ebc0e0ef0a11	5944	/* Description: SPI slave 1. */
vcoubard	1:ebc0e0ef0a11	5945
vcoubard	1:ebc0e0ef0a11	5946	/* Register: SPIS_SHORTS */
vcoubard	1:ebc0e0ef0a11	5947	/* Description: Shortcuts for SPIS. */
vcoubard	1:ebc0e0ef0a11	5948
vcoubard	1:ebc0e0ef0a11	5949	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
vcoubard	1:ebc0e0ef0a11	5950	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
vcoubard	1:ebc0e0ef0a11	5951	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
vcoubard	1:ebc0e0ef0a11	5952	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	5953	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	5954
vcoubard	1:ebc0e0ef0a11	5955	/* Register: SPIS_INTENSET */
vcoubard	1:ebc0e0ef0a11	5956	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	5957
vcoubard	1:ebc0e0ef0a11	5958	/* Bit 10 : Enable interrupt on ACQUIRED event. */
vcoubard	1:ebc0e0ef0a11	5959	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
vcoubard	1:ebc0e0ef0a11	5960	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
vcoubard	1:ebc0e0ef0a11	5961	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5962	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5963	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5964
vcoubard	1:ebc0e0ef0a11	5965	/* Bit 1 : Enable interrupt on END event. */
vcoubard	1:ebc0e0ef0a11	5966	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
vcoubard	1:ebc0e0ef0a11	5967	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	1:ebc0e0ef0a11	5968	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5969	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5970	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5971
vcoubard	1:ebc0e0ef0a11	5972	/* Register: SPIS_INTENCLR */
vcoubard	1:ebc0e0ef0a11	5973	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	5974
vcoubard	1:ebc0e0ef0a11	5975	/* Bit 10 : Disable interrupt on ACQUIRED event. */
vcoubard	1:ebc0e0ef0a11	5976	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
vcoubard	1:ebc0e0ef0a11	5977	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
vcoubard	1:ebc0e0ef0a11	5978	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5979	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5980	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5981
vcoubard	1:ebc0e0ef0a11	5982	/* Bit 1 : Disable interrupt on END event. */
vcoubard	1:ebc0e0ef0a11	5983	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
vcoubard	1:ebc0e0ef0a11	5984	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	1:ebc0e0ef0a11	5985	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	5986	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	5987	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	5988
vcoubard	1:ebc0e0ef0a11	5989	/* Register: SPIS_SEMSTAT */
vcoubard	1:ebc0e0ef0a11	5990	/* Description: Semaphore status. */
vcoubard	1:ebc0e0ef0a11	5991
vcoubard	1:ebc0e0ef0a11	5992	/* Bits 1..0 : Semaphore status. */
vcoubard	1:ebc0e0ef0a11	5993	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
vcoubard	1:ebc0e0ef0a11	5994	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
vcoubard	1:ebc0e0ef0a11	5995	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
vcoubard	1:ebc0e0ef0a11	5996	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
vcoubard	1:ebc0e0ef0a11	5997	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
vcoubard	1:ebc0e0ef0a11	5998	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
vcoubard	1:ebc0e0ef0a11	5999
vcoubard	1:ebc0e0ef0a11	6000	/* Register: SPIS_STATUS */
vcoubard	1:ebc0e0ef0a11	6001	/* Description: Status from last transaction. */
vcoubard	1:ebc0e0ef0a11	6002
vcoubard	1:ebc0e0ef0a11	6003	/* Bit 1 : RX buffer overflow detected, and prevented. */
vcoubard	1:ebc0e0ef0a11	6004	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
vcoubard	1:ebc0e0ef0a11	6005	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
vcoubard	1:ebc0e0ef0a11	6006	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6007	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6008	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
vcoubard	1:ebc0e0ef0a11	6009
vcoubard	1:ebc0e0ef0a11	6010	/* Bit 0 : TX buffer overread detected, and prevented. */
vcoubard	1:ebc0e0ef0a11	6011	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
vcoubard	1:ebc0e0ef0a11	6012	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
vcoubard	1:ebc0e0ef0a11	6013	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6014	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6015	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
vcoubard	1:ebc0e0ef0a11	6016
vcoubard	1:ebc0e0ef0a11	6017	/* Register: SPIS_ENABLE */
vcoubard	1:ebc0e0ef0a11	6018	/* Description: Enable SPIS. */
vcoubard	1:ebc0e0ef0a11	6019
vcoubard	1:ebc0e0ef0a11	6020	/* Bits 2..0 : Enable or disable SPIS. */
vcoubard	1:ebc0e0ef0a11	6021	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	6022	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	6023	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
vcoubard	1:ebc0e0ef0a11	6024	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
vcoubard	1:ebc0e0ef0a11	6025
vcoubard	1:ebc0e0ef0a11	6026	/* Register: SPIS_MAXRX */
vcoubard	1:ebc0e0ef0a11	6027	/* Description: Maximum number of bytes in the receive buffer. */
vcoubard	1:ebc0e0ef0a11	6028
vcoubard	1:ebc0e0ef0a11	6029	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
vcoubard	1:ebc0e0ef0a11	6030	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
vcoubard	1:ebc0e0ef0a11	6031	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
vcoubard	1:ebc0e0ef0a11	6032
vcoubard	1:ebc0e0ef0a11	6033	/* Register: SPIS_AMOUNTRX */
vcoubard	1:ebc0e0ef0a11	6034	/* Description: Number of bytes received in last granted transaction. */
vcoubard	1:ebc0e0ef0a11	6035
vcoubard	1:ebc0e0ef0a11	6036	/* Bits 7..0 : Number of bytes received in last granted transaction. */
vcoubard	1:ebc0e0ef0a11	6037	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
vcoubard	1:ebc0e0ef0a11	6038	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
vcoubard	1:ebc0e0ef0a11	6039
vcoubard	1:ebc0e0ef0a11	6040	/* Register: SPIS_MAXTX */
vcoubard	1:ebc0e0ef0a11	6041	/* Description: Maximum number of bytes in the transmit buffer. */
vcoubard	1:ebc0e0ef0a11	6042
vcoubard	1:ebc0e0ef0a11	6043	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
vcoubard	1:ebc0e0ef0a11	6044	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
vcoubard	1:ebc0e0ef0a11	6045	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
vcoubard	1:ebc0e0ef0a11	6046
vcoubard	1:ebc0e0ef0a11	6047	/* Register: SPIS_AMOUNTTX */
vcoubard	1:ebc0e0ef0a11	6048	/* Description: Number of bytes transmitted in last granted transaction. */
vcoubard	1:ebc0e0ef0a11	6049
vcoubard	1:ebc0e0ef0a11	6050	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
vcoubard	1:ebc0e0ef0a11	6051	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
vcoubard	1:ebc0e0ef0a11	6052	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
vcoubard	1:ebc0e0ef0a11	6053
vcoubard	1:ebc0e0ef0a11	6054	/* Register: SPIS_CONFIG */
vcoubard	1:ebc0e0ef0a11	6055	/* Description: Configuration register. */
vcoubard	1:ebc0e0ef0a11	6056
vcoubard	1:ebc0e0ef0a11	6057	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	1:ebc0e0ef0a11	6058	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	1:ebc0e0ef0a11	6059	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	1:ebc0e0ef0a11	6060	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	1:ebc0e0ef0a11	6061	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	1:ebc0e0ef0a11	6062
vcoubard	1:ebc0e0ef0a11	6063	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	1:ebc0e0ef0a11	6064	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	1:ebc0e0ef0a11	6065	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	1:ebc0e0ef0a11	6066	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	1:ebc0e0ef0a11	6067	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	1:ebc0e0ef0a11	6068
vcoubard	1:ebc0e0ef0a11	6069	/* Bit 0 : Bit order. */
vcoubard	1:ebc0e0ef0a11	6070	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	1:ebc0e0ef0a11	6071	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	1:ebc0e0ef0a11	6072	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	1:ebc0e0ef0a11	6073	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	1:ebc0e0ef0a11	6074
vcoubard	1:ebc0e0ef0a11	6075	/* Register: SPIS_DEF */
vcoubard	1:ebc0e0ef0a11	6076	/* Description: Default character. */
vcoubard	1:ebc0e0ef0a11	6077
vcoubard	1:ebc0e0ef0a11	6078	/* Bits 7..0 : Default character. */
vcoubard	1:ebc0e0ef0a11	6079	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
vcoubard	1:ebc0e0ef0a11	6080	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
vcoubard	1:ebc0e0ef0a11	6081
vcoubard	1:ebc0e0ef0a11	6082	/* Register: SPIS_ORC */
vcoubard	1:ebc0e0ef0a11	6083	/* Description: Over-read character. */
vcoubard	1:ebc0e0ef0a11	6084
vcoubard	1:ebc0e0ef0a11	6085	/* Bits 7..0 : Over-read character. */
vcoubard	1:ebc0e0ef0a11	6086	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
vcoubard	1:ebc0e0ef0a11	6087	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
vcoubard	1:ebc0e0ef0a11	6088
vcoubard	1:ebc0e0ef0a11	6089	/* Register: SPIS_POWER */
vcoubard	1:ebc0e0ef0a11	6090	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6091
vcoubard	1:ebc0e0ef0a11	6092	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6093	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	6094	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	6095	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	6096	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	6097
vcoubard	1:ebc0e0ef0a11	6098
vcoubard	1:ebc0e0ef0a11	6099	/* Peripheral: TEMP */
vcoubard	1:ebc0e0ef0a11	6100	/* Description: Temperature Sensor. */
vcoubard	1:ebc0e0ef0a11	6101
vcoubard	1:ebc0e0ef0a11	6102	/* Register: TEMP_INTENSET */
vcoubard	1:ebc0e0ef0a11	6103	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	6104
vcoubard	1:ebc0e0ef0a11	6105	/* Bit 0 : Enable interrupt on DATARDY event. */
vcoubard	1:ebc0e0ef0a11	6106	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
vcoubard	1:ebc0e0ef0a11	6107	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
vcoubard	1:ebc0e0ef0a11	6108	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6109	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6110	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6111
vcoubard	1:ebc0e0ef0a11	6112	/* Register: TEMP_INTENCLR */
vcoubard	1:ebc0e0ef0a11	6113	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	6114
vcoubard	1:ebc0e0ef0a11	6115	/* Bit 0 : Disable interrupt on DATARDY event. */
vcoubard	1:ebc0e0ef0a11	6116	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
vcoubard	1:ebc0e0ef0a11	6117	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
vcoubard	1:ebc0e0ef0a11	6118	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6119	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6120	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6121
vcoubard	1:ebc0e0ef0a11	6122	/* Register: TEMP_POWER */
vcoubard	1:ebc0e0ef0a11	6123	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6124
vcoubard	1:ebc0e0ef0a11	6125	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6126	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	6127	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	6128	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	6129	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	6130
vcoubard	1:ebc0e0ef0a11	6131
vcoubard	1:ebc0e0ef0a11	6132	/* Peripheral: TIMER */
vcoubard	1:ebc0e0ef0a11	6133	/* Description: Timer 0. */
vcoubard	1:ebc0e0ef0a11	6134
vcoubard	1:ebc0e0ef0a11	6135	/* Register: TIMER_SHORTS */
vcoubard	1:ebc0e0ef0a11	6136	/* Description: Shortcuts for Timer. */
vcoubard	1:ebc0e0ef0a11	6137
vcoubard	1:ebc0e0ef0a11	6138	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
vcoubard	1:ebc0e0ef0a11	6139	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
vcoubard	1:ebc0e0ef0a11	6140	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
vcoubard	1:ebc0e0ef0a11	6141	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6142	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6143
vcoubard	1:ebc0e0ef0a11	6144	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
vcoubard	1:ebc0e0ef0a11	6145	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
vcoubard	1:ebc0e0ef0a11	6146	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
vcoubard	1:ebc0e0ef0a11	6147	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6148	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6149
vcoubard	1:ebc0e0ef0a11	6150	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
vcoubard	1:ebc0e0ef0a11	6151	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
vcoubard	1:ebc0e0ef0a11	6152	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
vcoubard	1:ebc0e0ef0a11	6153	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6154	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6155
vcoubard	1:ebc0e0ef0a11	6156	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
vcoubard	1:ebc0e0ef0a11	6157	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
vcoubard	1:ebc0e0ef0a11	6158	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
vcoubard	1:ebc0e0ef0a11	6159	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6160	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6161
vcoubard	1:ebc0e0ef0a11	6162	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
vcoubard	1:ebc0e0ef0a11	6163	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
vcoubard	1:ebc0e0ef0a11	6164	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
vcoubard	1:ebc0e0ef0a11	6165	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6166	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6167
vcoubard	1:ebc0e0ef0a11	6168	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
vcoubard	1:ebc0e0ef0a11	6169	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
vcoubard	1:ebc0e0ef0a11	6170	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
vcoubard	1:ebc0e0ef0a11	6171	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6172	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6173
vcoubard	1:ebc0e0ef0a11	6174	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
vcoubard	1:ebc0e0ef0a11	6175	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
vcoubard	1:ebc0e0ef0a11	6176	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
vcoubard	1:ebc0e0ef0a11	6177	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6178	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6179
vcoubard	1:ebc0e0ef0a11	6180	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
vcoubard	1:ebc0e0ef0a11	6181	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
vcoubard	1:ebc0e0ef0a11	6182	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
vcoubard	1:ebc0e0ef0a11	6183	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6184	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6185
vcoubard	1:ebc0e0ef0a11	6186	/* Register: TIMER_INTENSET */
vcoubard	1:ebc0e0ef0a11	6187	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	6188
vcoubard	1:ebc0e0ef0a11	6189	/* Bit 19 : Enable interrupt on COMPARE[3] */
vcoubard	1:ebc0e0ef0a11	6190	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	6191	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	6192	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6193	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6194	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6195
vcoubard	1:ebc0e0ef0a11	6196	/* Bit 18 : Enable interrupt on COMPARE[2] */
vcoubard	1:ebc0e0ef0a11	6197	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	6198	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	6199	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6200	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6201	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6202
vcoubard	1:ebc0e0ef0a11	6203	/* Bit 17 : Enable interrupt on COMPARE[1] */
vcoubard	1:ebc0e0ef0a11	6204	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	6205	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	6206	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6207	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6208	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6209
vcoubard	1:ebc0e0ef0a11	6210	/* Bit 16 : Enable interrupt on COMPARE[0] */
vcoubard	1:ebc0e0ef0a11	6211	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	6212	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	6213	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6214	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6215	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6216
vcoubard	1:ebc0e0ef0a11	6217	/* Register: TIMER_INTENCLR */
vcoubard	1:ebc0e0ef0a11	6218	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	6219
vcoubard	1:ebc0e0ef0a11	6220	/* Bit 19 : Disable interrupt on COMPARE[3] */
vcoubard	1:ebc0e0ef0a11	6221	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	6222	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	1:ebc0e0ef0a11	6223	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6224	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6225	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6226
vcoubard	1:ebc0e0ef0a11	6227	/* Bit 18 : Disable interrupt on COMPARE[2] */
vcoubard	1:ebc0e0ef0a11	6228	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	6229	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	1:ebc0e0ef0a11	6230	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6231	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6232	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6233
vcoubard	1:ebc0e0ef0a11	6234	/* Bit 17 : Disable interrupt on COMPARE[1] */
vcoubard	1:ebc0e0ef0a11	6235	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	6236	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	1:ebc0e0ef0a11	6237	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6238	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6239	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6240
vcoubard	1:ebc0e0ef0a11	6241	/* Bit 16 : Disable interrupt on COMPARE[0] */
vcoubard	1:ebc0e0ef0a11	6242	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	6243	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	1:ebc0e0ef0a11	6244	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6245	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6246	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6247
vcoubard	1:ebc0e0ef0a11	6248	/* Register: TIMER_MODE */
vcoubard	1:ebc0e0ef0a11	6249	/* Description: Timer Mode selection. */
vcoubard	1:ebc0e0ef0a11	6250
vcoubard	1:ebc0e0ef0a11	6251	/* Bit 0 : Select Normal or Counter mode. */
vcoubard	1:ebc0e0ef0a11	6252	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	1:ebc0e0ef0a11	6253	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	1:ebc0e0ef0a11	6254	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
vcoubard	1:ebc0e0ef0a11	6255	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
vcoubard	1:ebc0e0ef0a11	6256
vcoubard	1:ebc0e0ef0a11	6257	/* Register: TIMER_BITMODE */
vcoubard	1:ebc0e0ef0a11	6258	/* Description: Sets timer behaviour. */
vcoubard	1:ebc0e0ef0a11	6259
vcoubard	1:ebc0e0ef0a11	6260	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
vcoubard	1:ebc0e0ef0a11	6261	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
vcoubard	1:ebc0e0ef0a11	6262	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
vcoubard	1:ebc0e0ef0a11	6263	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
vcoubard	1:ebc0e0ef0a11	6264	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
vcoubard	1:ebc0e0ef0a11	6265	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
vcoubard	1:ebc0e0ef0a11	6266	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
vcoubard	1:ebc0e0ef0a11	6267
vcoubard	1:ebc0e0ef0a11	6268	/* Register: TIMER_PRESCALER */
vcoubard	1:ebc0e0ef0a11	6269	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
vcoubard	1:ebc0e0ef0a11	6270
vcoubard	1:ebc0e0ef0a11	6271	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
vcoubard	1:ebc0e0ef0a11	6272	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
vcoubard	1:ebc0e0ef0a11	6273	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
vcoubard	1:ebc0e0ef0a11	6274
vcoubard	1:ebc0e0ef0a11	6275	/* Register: TIMER_POWER */
vcoubard	1:ebc0e0ef0a11	6276	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6277
vcoubard	1:ebc0e0ef0a11	6278	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6279	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	6280	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	6281	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	6282	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	6283
vcoubard	1:ebc0e0ef0a11	6284
vcoubard	1:ebc0e0ef0a11	6285	/* Peripheral: TWI */
vcoubard	1:ebc0e0ef0a11	6286	/* Description: Two-wire interface master 0. */
vcoubard	1:ebc0e0ef0a11	6287
vcoubard	1:ebc0e0ef0a11	6288	/* Register: TWI_SHORTS */
vcoubard	1:ebc0e0ef0a11	6289	/* Description: Shortcuts for TWI. */
vcoubard	1:ebc0e0ef0a11	6290
vcoubard	1:ebc0e0ef0a11	6291	/* Bit 1 : Shortcut between BB event and the STOP task. */
vcoubard	1:ebc0e0ef0a11	6292	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
vcoubard	1:ebc0e0ef0a11	6293	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
vcoubard	1:ebc0e0ef0a11	6294	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6295	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6296
vcoubard	1:ebc0e0ef0a11	6297	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
vcoubard	1:ebc0e0ef0a11	6298	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
vcoubard	1:ebc0e0ef0a11	6299	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
vcoubard	1:ebc0e0ef0a11	6300	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	1:ebc0e0ef0a11	6301	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	1:ebc0e0ef0a11	6302
vcoubard	1:ebc0e0ef0a11	6303	/* Register: TWI_INTENSET */
vcoubard	1:ebc0e0ef0a11	6304	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	6305
vcoubard	1:ebc0e0ef0a11	6306	/* Bit 18 : Enable interrupt on SUSPENDED event. */
vcoubard	1:ebc0e0ef0a11	6307	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
vcoubard	1:ebc0e0ef0a11	6308	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
vcoubard	1:ebc0e0ef0a11	6309	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6310	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6311	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6312
vcoubard	1:ebc0e0ef0a11	6313	/* Bit 14 : Enable interrupt on BB event. */
vcoubard	1:ebc0e0ef0a11	6314	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
vcoubard	1:ebc0e0ef0a11	6315	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
vcoubard	1:ebc0e0ef0a11	6316	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6317	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6318	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6319
vcoubard	1:ebc0e0ef0a11	6320	/* Bit 9 : Enable interrupt on ERROR event. */
vcoubard	1:ebc0e0ef0a11	6321	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	1:ebc0e0ef0a11	6322	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	1:ebc0e0ef0a11	6323	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6324	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6325	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6326
vcoubard	1:ebc0e0ef0a11	6327	/* Bit 7 : Enable interrupt on TXDSENT event. */
vcoubard	1:ebc0e0ef0a11	6328	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
vcoubard	1:ebc0e0ef0a11	6329	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
vcoubard	1:ebc0e0ef0a11	6330	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6331	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6332	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6333
vcoubard	1:ebc0e0ef0a11	6334	/* Bit 2 : Enable interrupt on READY event. */
vcoubard	1:ebc0e0ef0a11	6335	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
vcoubard	1:ebc0e0ef0a11	6336	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
vcoubard	1:ebc0e0ef0a11	6337	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6338	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6339	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6340
vcoubard	1:ebc0e0ef0a11	6341	/* Bit 1 : Enable interrupt on STOPPED event. */
vcoubard	1:ebc0e0ef0a11	6342	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	1:ebc0e0ef0a11	6343	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	1:ebc0e0ef0a11	6344	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6345	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6346	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6347
vcoubard	1:ebc0e0ef0a11	6348	/* Register: TWI_INTENCLR */
vcoubard	1:ebc0e0ef0a11	6349	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	6350
vcoubard	1:ebc0e0ef0a11	6351	/* Bit 18 : Disable interrupt on SUSPENDED event. */
vcoubard	1:ebc0e0ef0a11	6352	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
vcoubard	1:ebc0e0ef0a11	6353	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
vcoubard	1:ebc0e0ef0a11	6354	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6355	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6356	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6357
vcoubard	1:ebc0e0ef0a11	6358	/* Bit 14 : Disable interrupt on BB event. */
vcoubard	1:ebc0e0ef0a11	6359	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
vcoubard	1:ebc0e0ef0a11	6360	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
vcoubard	1:ebc0e0ef0a11	6361	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6362	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6363	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6364
vcoubard	1:ebc0e0ef0a11	6365	/* Bit 9 : Disable interrupt on ERROR event. */
vcoubard	1:ebc0e0ef0a11	6366	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	1:ebc0e0ef0a11	6367	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	1:ebc0e0ef0a11	6368	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6369	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6370	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6371
vcoubard	1:ebc0e0ef0a11	6372	/* Bit 7 : Disable interrupt on TXDSENT event. */
vcoubard	1:ebc0e0ef0a11	6373	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
vcoubard	1:ebc0e0ef0a11	6374	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
vcoubard	1:ebc0e0ef0a11	6375	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6376	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6377	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6378
vcoubard	1:ebc0e0ef0a11	6379	/* Bit 2 : Disable interrupt on RXDREADY event. */
vcoubard	1:ebc0e0ef0a11	6380	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
vcoubard	1:ebc0e0ef0a11	6381	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
vcoubard	1:ebc0e0ef0a11	6382	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6383	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6384	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6385
vcoubard	1:ebc0e0ef0a11	6386	/* Bit 1 : Disable interrupt on STOPPED event. */
vcoubard	1:ebc0e0ef0a11	6387	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	1:ebc0e0ef0a11	6388	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	1:ebc0e0ef0a11	6389	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6390	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6391	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6392
vcoubard	1:ebc0e0ef0a11	6393	/* Register: TWI_ERRORSRC */
vcoubard	1:ebc0e0ef0a11	6394	/* Description: Two-wire error source. Write error field to 1 to clear error. */
vcoubard	1:ebc0e0ef0a11	6395
vcoubard	1:ebc0e0ef0a11	6396	/* Bit 2 : NACK received after sending a data byte. */
vcoubard	1:ebc0e0ef0a11	6397	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
vcoubard	1:ebc0e0ef0a11	6398	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
vcoubard	1:ebc0e0ef0a11	6399	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6400	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6401	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
vcoubard	1:ebc0e0ef0a11	6402
vcoubard	1:ebc0e0ef0a11	6403	/* Bit 1 : NACK received after sending the address. */
vcoubard	1:ebc0e0ef0a11	6404	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
vcoubard	1:ebc0e0ef0a11	6405	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
vcoubard	1:ebc0e0ef0a11	6406	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6407	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6408	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
vcoubard	1:ebc0e0ef0a11	6409
vcoubard	1:ebc0e0ef0a11	6410	/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
vcoubard	1:ebc0e0ef0a11	6411	#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
vcoubard	1:ebc0e0ef0a11	6412	#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
vcoubard	1:ebc0e0ef0a11	6413	#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6414	#define TWI_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6415	#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
vcoubard	1:ebc0e0ef0a11	6416
vcoubard	1:ebc0e0ef0a11	6417	/* Register: TWI_ENABLE */
vcoubard	1:ebc0e0ef0a11	6418	/* Description: Enable two-wire master. */
vcoubard	1:ebc0e0ef0a11	6419
vcoubard	1:ebc0e0ef0a11	6420	/* Bits 2..0 : Enable or disable W2M */
vcoubard	1:ebc0e0ef0a11	6421	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	6422	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	6423	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	6424	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	6425
vcoubard	1:ebc0e0ef0a11	6426	/* Register: TWI_RXD */
vcoubard	1:ebc0e0ef0a11	6427	/* Description: RX data register. */
vcoubard	1:ebc0e0ef0a11	6428
vcoubard	1:ebc0e0ef0a11	6429	/* Bits 7..0 : RX data from last transfer. */
vcoubard	1:ebc0e0ef0a11	6430	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	1:ebc0e0ef0a11	6431	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	1:ebc0e0ef0a11	6432
vcoubard	1:ebc0e0ef0a11	6433	/* Register: TWI_TXD */
vcoubard	1:ebc0e0ef0a11	6434	/* Description: TX data register. */
vcoubard	1:ebc0e0ef0a11	6435
vcoubard	1:ebc0e0ef0a11	6436	/* Bits 7..0 : TX data for next transfer. */
vcoubard	1:ebc0e0ef0a11	6437	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	1:ebc0e0ef0a11	6438	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	1:ebc0e0ef0a11	6439
vcoubard	1:ebc0e0ef0a11	6440	/* Register: TWI_FREQUENCY */
vcoubard	1:ebc0e0ef0a11	6441	/* Description: Two-wire frequency. */
vcoubard	1:ebc0e0ef0a11	6442
vcoubard	1:ebc0e0ef0a11	6443	/* Bits 31..0 : Two-wire master clock frequency. */
vcoubard	1:ebc0e0ef0a11	6444	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	1:ebc0e0ef0a11	6445	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	1:ebc0e0ef0a11	6446	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
vcoubard	1:ebc0e0ef0a11	6447	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
vcoubard	1:ebc0e0ef0a11	6448	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
vcoubard	1:ebc0e0ef0a11	6449
vcoubard	1:ebc0e0ef0a11	6450	/* Register: TWI_ADDRESS */
vcoubard	1:ebc0e0ef0a11	6451	/* Description: Address used in the two-wire transfer. */
vcoubard	1:ebc0e0ef0a11	6452
vcoubard	1:ebc0e0ef0a11	6453	/* Bits 6..0 : Two-wire address. */
vcoubard	1:ebc0e0ef0a11	6454	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
vcoubard	1:ebc0e0ef0a11	6455	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	1:ebc0e0ef0a11	6456
vcoubard	1:ebc0e0ef0a11	6457	/* Register: TWI_POWER */
vcoubard	1:ebc0e0ef0a11	6458	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6459
vcoubard	1:ebc0e0ef0a11	6460	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6461	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	6462	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	6463	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	6464	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	6465
vcoubard	1:ebc0e0ef0a11	6466
vcoubard	1:ebc0e0ef0a11	6467	/* Peripheral: UART */
vcoubard	1:ebc0e0ef0a11	6468	/* Description: Universal Asynchronous Receiver/Transmitter. */
vcoubard	1:ebc0e0ef0a11	6469
vcoubard	24:2aea0c1c57ee	6470	/* Register: UART_SHORTS */
vcoubard	24:2aea0c1c57ee	6471	/* Description: Shortcuts for UART. */
vcoubard	24:2aea0c1c57ee	6472
vcoubard	24:2aea0c1c57ee	6473	/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
vcoubard	24:2aea0c1c57ee	6474	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
vcoubard	24:2aea0c1c57ee	6475	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
vcoubard	24:2aea0c1c57ee	6476	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	24:2aea0c1c57ee	6477	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	24:2aea0c1c57ee	6478
vcoubard	24:2aea0c1c57ee	6479	/* Bit 3 : Shortcut between CTS event and STARTRX task. */
vcoubard	24:2aea0c1c57ee	6480	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
vcoubard	24:2aea0c1c57ee	6481	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
vcoubard	24:2aea0c1c57ee	6482	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	24:2aea0c1c57ee	6483	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	24:2aea0c1c57ee	6484
vcoubard	1:ebc0e0ef0a11	6485	/* Register: UART_INTENSET */
vcoubard	1:ebc0e0ef0a11	6486	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	6487
vcoubard	1:ebc0e0ef0a11	6488	/* Bit 17 : Enable interrupt on RXTO event. */
vcoubard	1:ebc0e0ef0a11	6489	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
vcoubard	1:ebc0e0ef0a11	6490	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
vcoubard	1:ebc0e0ef0a11	6491	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6492	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6493	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6494
vcoubard	1:ebc0e0ef0a11	6495	/* Bit 9 : Enable interrupt on ERROR event. */
vcoubard	1:ebc0e0ef0a11	6496	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	1:ebc0e0ef0a11	6497	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	1:ebc0e0ef0a11	6498	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6499	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6500	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6501
vcoubard	1:ebc0e0ef0a11	6502	/* Bit 7 : Enable interrupt on TXRDY event. */
vcoubard	1:ebc0e0ef0a11	6503	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
vcoubard	1:ebc0e0ef0a11	6504	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
vcoubard	1:ebc0e0ef0a11	6505	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6506	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6507	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6508
vcoubard	1:ebc0e0ef0a11	6509	/* Bit 2 : Enable interrupt on RXRDY event. */
vcoubard	1:ebc0e0ef0a11	6510	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
vcoubard	1:ebc0e0ef0a11	6511	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
vcoubard	1:ebc0e0ef0a11	6512	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6513	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6514	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6515
vcoubard	1:ebc0e0ef0a11	6516	/* Bit 1 : Enable interrupt on NCTS event. */
vcoubard	1:ebc0e0ef0a11	6517	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
vcoubard	1:ebc0e0ef0a11	6518	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
vcoubard	1:ebc0e0ef0a11	6519	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6520	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6521	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6522
vcoubard	1:ebc0e0ef0a11	6523	/* Bit 0 : Enable interrupt on CTS event. */
vcoubard	1:ebc0e0ef0a11	6524	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
vcoubard	1:ebc0e0ef0a11	6525	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
vcoubard	1:ebc0e0ef0a11	6526	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6527	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6528	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6529
vcoubard	1:ebc0e0ef0a11	6530	/* Register: UART_INTENCLR */
vcoubard	1:ebc0e0ef0a11	6531	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	6532
vcoubard	1:ebc0e0ef0a11	6533	/* Bit 17 : Disable interrupt on RXTO event. */
vcoubard	1:ebc0e0ef0a11	6534	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
vcoubard	1:ebc0e0ef0a11	6535	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
vcoubard	1:ebc0e0ef0a11	6536	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6537	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6538	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6539
vcoubard	1:ebc0e0ef0a11	6540	/* Bit 9 : Disable interrupt on ERROR event. */
vcoubard	1:ebc0e0ef0a11	6541	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	1:ebc0e0ef0a11	6542	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	1:ebc0e0ef0a11	6543	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6544	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6545	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6546
vcoubard	1:ebc0e0ef0a11	6547	/* Bit 7 : Disable interrupt on TXRDY event. */
vcoubard	1:ebc0e0ef0a11	6548	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
vcoubard	1:ebc0e0ef0a11	6549	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
vcoubard	1:ebc0e0ef0a11	6550	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6551	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6552	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6553
vcoubard	1:ebc0e0ef0a11	6554	/* Bit 2 : Disable interrupt on RXRDY event. */
vcoubard	1:ebc0e0ef0a11	6555	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
vcoubard	1:ebc0e0ef0a11	6556	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
vcoubard	1:ebc0e0ef0a11	6557	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6558	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6559	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6560
vcoubard	1:ebc0e0ef0a11	6561	/* Bit 1 : Disable interrupt on NCTS event. */
vcoubard	1:ebc0e0ef0a11	6562	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
vcoubard	1:ebc0e0ef0a11	6563	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
vcoubard	1:ebc0e0ef0a11	6564	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6565	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6566	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6567
vcoubard	1:ebc0e0ef0a11	6568	/* Bit 0 : Disable interrupt on CTS event. */
vcoubard	1:ebc0e0ef0a11	6569	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
vcoubard	1:ebc0e0ef0a11	6570	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
vcoubard	1:ebc0e0ef0a11	6571	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6572	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6573	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6574
vcoubard	1:ebc0e0ef0a11	6575	/* Register: UART_ERRORSRC */
vcoubard	1:ebc0e0ef0a11	6576	/* Description: Error source. Write error field to 1 to clear error. */
vcoubard	1:ebc0e0ef0a11	6577
vcoubard	1:ebc0e0ef0a11	6578	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
vcoubard	1:ebc0e0ef0a11	6579	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
vcoubard	1:ebc0e0ef0a11	6580	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
vcoubard	1:ebc0e0ef0a11	6581	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6582	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6583	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
vcoubard	1:ebc0e0ef0a11	6584
vcoubard	1:ebc0e0ef0a11	6585	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
vcoubard	1:ebc0e0ef0a11	6586	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
vcoubard	1:ebc0e0ef0a11	6587	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
vcoubard	1:ebc0e0ef0a11	6588	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6589	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6590	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
vcoubard	1:ebc0e0ef0a11	6591
vcoubard	1:ebc0e0ef0a11	6592	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
vcoubard	1:ebc0e0ef0a11	6593	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
vcoubard	1:ebc0e0ef0a11	6594	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
vcoubard	1:ebc0e0ef0a11	6595	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6596	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6597	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
vcoubard	1:ebc0e0ef0a11	6598
vcoubard	1:ebc0e0ef0a11	6599	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
vcoubard	1:ebc0e0ef0a11	6600	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
vcoubard	1:ebc0e0ef0a11	6601	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
vcoubard	1:ebc0e0ef0a11	6602	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
vcoubard	1:ebc0e0ef0a11	6603	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
vcoubard	1:ebc0e0ef0a11	6604	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
vcoubard	1:ebc0e0ef0a11	6605
vcoubard	1:ebc0e0ef0a11	6606	/* Register: UART_ENABLE */
vcoubard	1:ebc0e0ef0a11	6607	/* Description: Enable UART and acquire IOs. */
vcoubard	1:ebc0e0ef0a11	6608
vcoubard	1:ebc0e0ef0a11	6609	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
vcoubard	1:ebc0e0ef0a11	6610	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	6611	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	1:ebc0e0ef0a11	6612	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
vcoubard	1:ebc0e0ef0a11	6613	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
vcoubard	1:ebc0e0ef0a11	6614
vcoubard	1:ebc0e0ef0a11	6615	/* Register: UART_RXD */
vcoubard	1:ebc0e0ef0a11	6616	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
vcoubard	1:ebc0e0ef0a11	6617
vcoubard	1:ebc0e0ef0a11	6618	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
vcoubard	1:ebc0e0ef0a11	6619	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	1:ebc0e0ef0a11	6620	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	1:ebc0e0ef0a11	6621
vcoubard	1:ebc0e0ef0a11	6622	/* Register: UART_TXD */
vcoubard	1:ebc0e0ef0a11	6623	/* Description: TXD register. */
vcoubard	1:ebc0e0ef0a11	6624
vcoubard	1:ebc0e0ef0a11	6625	/* Bits 7..0 : TX data for transfer. */
vcoubard	1:ebc0e0ef0a11	6626	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	1:ebc0e0ef0a11	6627	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	1:ebc0e0ef0a11	6628
vcoubard	1:ebc0e0ef0a11	6629	/* Register: UART_BAUDRATE */
vcoubard	1:ebc0e0ef0a11	6630	/* Description: UART Baudrate. */
vcoubard	1:ebc0e0ef0a11	6631
vcoubard	1:ebc0e0ef0a11	6632	/* Bits 31..0 : UART baudrate. */
vcoubard	1:ebc0e0ef0a11	6633	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
vcoubard	1:ebc0e0ef0a11	6634	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
vcoubard	1:ebc0e0ef0a11	6635	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
vcoubard	1:ebc0e0ef0a11	6636	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
vcoubard	1:ebc0e0ef0a11	6637	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
vcoubard	1:ebc0e0ef0a11	6638	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
vcoubard	1:ebc0e0ef0a11	6639	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
vcoubard	1:ebc0e0ef0a11	6640	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
vcoubard	1:ebc0e0ef0a11	6641	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
vcoubard	1:ebc0e0ef0a11	6642	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
vcoubard	1:ebc0e0ef0a11	6643	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
vcoubard	1:ebc0e0ef0a11	6644	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
vcoubard	1:ebc0e0ef0a11	6645	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
vcoubard	1:ebc0e0ef0a11	6646	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
vcoubard	1:ebc0e0ef0a11	6647	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
vcoubard	1:ebc0e0ef0a11	6648	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
vcoubard	1:ebc0e0ef0a11	6649	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /!< 921600 baud. /
vcoubard	1:ebc0e0ef0a11	6650	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
vcoubard	1:ebc0e0ef0a11	6651
vcoubard	1:ebc0e0ef0a11	6652	/* Register: UART_CONFIG */
vcoubard	1:ebc0e0ef0a11	6653	/* Description: Configuration of parity and hardware flow control register. */
vcoubard	1:ebc0e0ef0a11	6654
vcoubard	1:ebc0e0ef0a11	6655	/* Bits 3..1 : Include parity bit. */
vcoubard	1:ebc0e0ef0a11	6656	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
vcoubard	1:ebc0e0ef0a11	6657	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
vcoubard	1:ebc0e0ef0a11	6658	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
vcoubard	1:ebc0e0ef0a11	6659	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
vcoubard	1:ebc0e0ef0a11	6660
vcoubard	1:ebc0e0ef0a11	6661	/* Bit 0 : Hardware flow control. */
vcoubard	1:ebc0e0ef0a11	6662	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
vcoubard	1:ebc0e0ef0a11	6663	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
vcoubard	1:ebc0e0ef0a11	6664	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
vcoubard	1:ebc0e0ef0a11	6665	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
vcoubard	1:ebc0e0ef0a11	6666
vcoubard	1:ebc0e0ef0a11	6667	/* Register: UART_POWER */
vcoubard	1:ebc0e0ef0a11	6668	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6669
vcoubard	1:ebc0e0ef0a11	6670	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6671	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	6672	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	6673	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	6674	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	6675
vcoubard	1:ebc0e0ef0a11	6676
vcoubard	1:ebc0e0ef0a11	6677	/* Peripheral: UICR */
vcoubard	1:ebc0e0ef0a11	6678	/* Description: User Information Configuration. */
vcoubard	1:ebc0e0ef0a11	6679
vcoubard	1:ebc0e0ef0a11	6680	/* Register: UICR_RBPCONF */
vcoubard	1:ebc0e0ef0a11	6681	/* Description: Readback protection configuration. */
vcoubard	1:ebc0e0ef0a11	6682
vcoubard	1:ebc0e0ef0a11	6683	/* Bits 15..8 : Readback protect all code in the device. */
vcoubard	1:ebc0e0ef0a11	6684	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
vcoubard	1:ebc0e0ef0a11	6685	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
vcoubard	1:ebc0e0ef0a11	6686	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	6687	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	6688
vcoubard	1:ebc0e0ef0a11	6689	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
vcoubard	1:ebc0e0ef0a11	6690	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
vcoubard	1:ebc0e0ef0a11	6691	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
vcoubard	1:ebc0e0ef0a11	6692	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
vcoubard	1:ebc0e0ef0a11	6693	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
vcoubard	1:ebc0e0ef0a11	6694
vcoubard	1:ebc0e0ef0a11	6695	/* Register: UICR_XTALFREQ */
vcoubard	1:ebc0e0ef0a11	6696	/* Description: Reset value for CLOCK XTALFREQ register. */
vcoubard	1:ebc0e0ef0a11	6697
vcoubard	1:ebc0e0ef0a11	6698	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
vcoubard	1:ebc0e0ef0a11	6699	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
vcoubard	1:ebc0e0ef0a11	6700	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
vcoubard	1:ebc0e0ef0a11	6701	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
vcoubard	1:ebc0e0ef0a11	6702	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
vcoubard	1:ebc0e0ef0a11	6703
vcoubard	1:ebc0e0ef0a11	6704	/* Register: UICR_FWID */
vcoubard	1:ebc0e0ef0a11	6705	/* Description: Firmware ID. */
vcoubard	1:ebc0e0ef0a11	6706
vcoubard	1:ebc0e0ef0a11	6707	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
vcoubard	1:ebc0e0ef0a11	6708	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
vcoubard	1:ebc0e0ef0a11	6709	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
vcoubard	1:ebc0e0ef0a11	6710
vcoubard	1:ebc0e0ef0a11	6711
vcoubard	1:ebc0e0ef0a11	6712	/* Peripheral: WDT */
vcoubard	1:ebc0e0ef0a11	6713	/* Description: Watchdog Timer. */
vcoubard	1:ebc0e0ef0a11	6714
vcoubard	1:ebc0e0ef0a11	6715	/* Register: WDT_INTENSET */
vcoubard	1:ebc0e0ef0a11	6716	/* Description: Interrupt enable set register. */
vcoubard	1:ebc0e0ef0a11	6717
vcoubard	1:ebc0e0ef0a11	6718	/* Bit 0 : Enable interrupt on TIMEOUT event. */
vcoubard	1:ebc0e0ef0a11	6719	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
vcoubard	1:ebc0e0ef0a11	6720	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
vcoubard	1:ebc0e0ef0a11	6721	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6722	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6723	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6724
vcoubard	1:ebc0e0ef0a11	6725	/* Register: WDT_INTENCLR */
vcoubard	1:ebc0e0ef0a11	6726	/* Description: Interrupt enable clear register. */
vcoubard	1:ebc0e0ef0a11	6727
vcoubard	1:ebc0e0ef0a11	6728	/* Bit 0 : Disable interrupt on TIMEOUT event. */
vcoubard	1:ebc0e0ef0a11	6729	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
vcoubard	1:ebc0e0ef0a11	6730	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
vcoubard	1:ebc0e0ef0a11	6731	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	1:ebc0e0ef0a11	6732	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	1:ebc0e0ef0a11	6733	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	1:ebc0e0ef0a11	6734
vcoubard	1:ebc0e0ef0a11	6735	/* Register: WDT_RUNSTATUS */
vcoubard	1:ebc0e0ef0a11	6736	/* Description: Watchdog running status. */
vcoubard	1:ebc0e0ef0a11	6737
vcoubard	1:ebc0e0ef0a11	6738	/* Bit 0 : Watchdog running status. */
vcoubard	1:ebc0e0ef0a11	6739	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
vcoubard	1:ebc0e0ef0a11	6740	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
vcoubard	1:ebc0e0ef0a11	6741	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
vcoubard	1:ebc0e0ef0a11	6742	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
vcoubard	1:ebc0e0ef0a11	6743
vcoubard	1:ebc0e0ef0a11	6744	/* Register: WDT_REQSTATUS */
vcoubard	1:ebc0e0ef0a11	6745	/* Description: Request status. */
vcoubard	1:ebc0e0ef0a11	6746
vcoubard	1:ebc0e0ef0a11	6747	/* Bit 7 : Request status for RR[7]. */
vcoubard	1:ebc0e0ef0a11	6748	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
vcoubard	1:ebc0e0ef0a11	6749	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
vcoubard	1:ebc0e0ef0a11	6750	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
vcoubard	1:ebc0e0ef0a11	6751	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
vcoubard	1:ebc0e0ef0a11	6752
vcoubard	1:ebc0e0ef0a11	6753	/* Bit 6 : Request status for RR[6]. */
vcoubard	1:ebc0e0ef0a11	6754	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
vcoubard	1:ebc0e0ef0a11	6755	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
vcoubard	1:ebc0e0ef0a11	6756	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
vcoubard	1:ebc0e0ef0a11	6757	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
vcoubard	1:ebc0e0ef0a11	6758
vcoubard	1:ebc0e0ef0a11	6759	/* Bit 5 : Request status for RR[5]. */
vcoubard	1:ebc0e0ef0a11	6760	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
vcoubard	1:ebc0e0ef0a11	6761	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
vcoubard	1:ebc0e0ef0a11	6762	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
vcoubard	1:ebc0e0ef0a11	6763	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
vcoubard	1:ebc0e0ef0a11	6764
vcoubard	1:ebc0e0ef0a11	6765	/* Bit 4 : Request status for RR[4]. */
vcoubard	1:ebc0e0ef0a11	6766	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
vcoubard	1:ebc0e0ef0a11	6767	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
vcoubard	1:ebc0e0ef0a11	6768	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
vcoubard	1:ebc0e0ef0a11	6769	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
vcoubard	1:ebc0e0ef0a11	6770
vcoubard	1:ebc0e0ef0a11	6771	/* Bit 3 : Request status for RR[3]. */
vcoubard	1:ebc0e0ef0a11	6772	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
vcoubard	1:ebc0e0ef0a11	6773	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
vcoubard	1:ebc0e0ef0a11	6774	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
vcoubard	1:ebc0e0ef0a11	6775	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
vcoubard	1:ebc0e0ef0a11	6776
vcoubard	1:ebc0e0ef0a11	6777	/* Bit 2 : Request status for RR[2]. */
vcoubard	1:ebc0e0ef0a11	6778	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
vcoubard	1:ebc0e0ef0a11	6779	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
vcoubard	1:ebc0e0ef0a11	6780	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
vcoubard	1:ebc0e0ef0a11	6781	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
vcoubard	1:ebc0e0ef0a11	6782
vcoubard	1:ebc0e0ef0a11	6783	/* Bit 1 : Request status for RR[1]. */
vcoubard	1:ebc0e0ef0a11	6784	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
vcoubard	1:ebc0e0ef0a11	6785	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
vcoubard	1:ebc0e0ef0a11	6786	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
vcoubard	1:ebc0e0ef0a11	6787	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
vcoubard	1:ebc0e0ef0a11	6788
vcoubard	1:ebc0e0ef0a11	6789	/* Bit 0 : Request status for RR[0]. */
vcoubard	1:ebc0e0ef0a11	6790	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
vcoubard	1:ebc0e0ef0a11	6791	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
vcoubard	1:ebc0e0ef0a11	6792	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
vcoubard	1:ebc0e0ef0a11	6793	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
vcoubard	1:ebc0e0ef0a11	6794
vcoubard	1:ebc0e0ef0a11	6795	/* Register: WDT_RREN */
vcoubard	1:ebc0e0ef0a11	6796	/* Description: Reload request enable. */
vcoubard	1:ebc0e0ef0a11	6797
vcoubard	1:ebc0e0ef0a11	6798	/* Bit 7 : Enable or disable RR[7] register. */
vcoubard	1:ebc0e0ef0a11	6799	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
vcoubard	1:ebc0e0ef0a11	6800	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
vcoubard	1:ebc0e0ef0a11	6801	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
vcoubard	1:ebc0e0ef0a11	6802	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
vcoubard	1:ebc0e0ef0a11	6803
vcoubard	1:ebc0e0ef0a11	6804	/* Bit 6 : Enable or disable RR[6] register. */
vcoubard	1:ebc0e0ef0a11	6805	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
vcoubard	1:ebc0e0ef0a11	6806	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
vcoubard	1:ebc0e0ef0a11	6807	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
vcoubard	1:ebc0e0ef0a11	6808	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
vcoubard	1:ebc0e0ef0a11	6809
vcoubard	1:ebc0e0ef0a11	6810	/* Bit 5 : Enable or disable RR[5] register. */
vcoubard	1:ebc0e0ef0a11	6811	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
vcoubard	1:ebc0e0ef0a11	6812	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
vcoubard	1:ebc0e0ef0a11	6813	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
vcoubard	1:ebc0e0ef0a11	6814	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
vcoubard	1:ebc0e0ef0a11	6815
vcoubard	1:ebc0e0ef0a11	6816	/* Bit 4 : Enable or disable RR[4] register. */
vcoubard	1:ebc0e0ef0a11	6817	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
vcoubard	1:ebc0e0ef0a11	6818	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
vcoubard	1:ebc0e0ef0a11	6819	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
vcoubard	1:ebc0e0ef0a11	6820	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
vcoubard	1:ebc0e0ef0a11	6821
vcoubard	1:ebc0e0ef0a11	6822	/* Bit 3 : Enable or disable RR[3] register. */
vcoubard	1:ebc0e0ef0a11	6823	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
vcoubard	1:ebc0e0ef0a11	6824	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
vcoubard	1:ebc0e0ef0a11	6825	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
vcoubard	1:ebc0e0ef0a11	6826	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
vcoubard	1:ebc0e0ef0a11	6827
vcoubard	1:ebc0e0ef0a11	6828	/* Bit 2 : Enable or disable RR[2] register. */
vcoubard	1:ebc0e0ef0a11	6829	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
vcoubard	1:ebc0e0ef0a11	6830	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
vcoubard	1:ebc0e0ef0a11	6831	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
vcoubard	1:ebc0e0ef0a11	6832	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
vcoubard	1:ebc0e0ef0a11	6833
vcoubard	1:ebc0e0ef0a11	6834	/* Bit 1 : Enable or disable RR[1] register. */
vcoubard	1:ebc0e0ef0a11	6835	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
vcoubard	1:ebc0e0ef0a11	6836	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
vcoubard	1:ebc0e0ef0a11	6837	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
vcoubard	1:ebc0e0ef0a11	6838	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
vcoubard	1:ebc0e0ef0a11	6839
vcoubard	1:ebc0e0ef0a11	6840	/* Bit 0 : Enable or disable RR[0] register. */
vcoubard	1:ebc0e0ef0a11	6841	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
vcoubard	1:ebc0e0ef0a11	6842	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
vcoubard	1:ebc0e0ef0a11	6843	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
vcoubard	1:ebc0e0ef0a11	6844	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
vcoubard	1:ebc0e0ef0a11	6845
vcoubard	1:ebc0e0ef0a11	6846	/* Register: WDT_CONFIG */
vcoubard	1:ebc0e0ef0a11	6847	/* Description: Configuration register. */
vcoubard	1:ebc0e0ef0a11	6848
vcoubard	1:ebc0e0ef0a11	6849	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
vcoubard	1:ebc0e0ef0a11	6850	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
vcoubard	1:ebc0e0ef0a11	6851	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
vcoubard	1:ebc0e0ef0a11	6852	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
vcoubard	1:ebc0e0ef0a11	6853	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
vcoubard	1:ebc0e0ef0a11	6854
vcoubard	1:ebc0e0ef0a11	6855	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
vcoubard	1:ebc0e0ef0a11	6856	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
vcoubard	1:ebc0e0ef0a11	6857	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
vcoubard	1:ebc0e0ef0a11	6858	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
vcoubard	1:ebc0e0ef0a11	6859	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
vcoubard	1:ebc0e0ef0a11	6860
vcoubard	1:ebc0e0ef0a11	6861	/* Register: WDT_RR */
vcoubard	1:ebc0e0ef0a11	6862	/* Description: Reload requests registers. */
vcoubard	1:ebc0e0ef0a11	6863
vcoubard	1:ebc0e0ef0a11	6864	/* Bits 31..0 : Reload register. */
vcoubard	1:ebc0e0ef0a11	6865	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
vcoubard	1:ebc0e0ef0a11	6866	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
vcoubard	1:ebc0e0ef0a11	6867	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
vcoubard	1:ebc0e0ef0a11	6868
vcoubard	1:ebc0e0ef0a11	6869	/* Register: WDT_POWER */
vcoubard	1:ebc0e0ef0a11	6870	/* Description: Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6871
vcoubard	1:ebc0e0ef0a11	6872	/* Bit 0 : Peripheral power control. */
vcoubard	1:ebc0e0ef0a11	6873	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	1:ebc0e0ef0a11	6874	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	1:ebc0e0ef0a11	6875	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	1:ebc0e0ef0a11	6876	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	1:ebc0e0ef0a11	6877
vcoubard	1:ebc0e0ef0a11	6878
vcoubard	1:ebc0e0ef0a11	6879	/lint --flb "Leave library region" /
vcoubard	1:ebc0e0ef0a11	6880	#endif

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Type:	Library
Created:	08 Apr 2016
Imports:	553
Forks:	7
Commits:	46
Dependents:	2
Dependencies:	0
Followers:	75

source/nordic_sdk/components/device/nrf51_bitfields.h@24:2aea0c1c57ee, 2016-04-07 (annotated)

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