Lancaster University / mbed-src

Lancaster University's (short term!) clone of mbed-src for micro:bit. This is a copy of the github branch https://github.com/lancaster-university/mbed-classic

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samr21g18a.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMR21G18A_PIO_
mbed_official 579:53297373a894 2 #define _SAMR21G18A_PIO_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */
mbed_official 579:53297373a894 5 #define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
mbed_official 579:53297373a894 6 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */
mbed_official 579:53297373a894 7 #define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
mbed_official 579:53297373a894 8 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */
mbed_official 579:53297373a894 9 #define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
mbed_official 579:53297373a894 10 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */
mbed_official 579:53297373a894 11 #define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
mbed_official 579:53297373a894 12 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */
mbed_official 579:53297373a894 13 #define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
mbed_official 579:53297373a894 14 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */
mbed_official 579:53297373a894 15 #define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
mbed_official 579:53297373a894 16 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */
mbed_official 579:53297373a894 17 #define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
mbed_official 579:53297373a894 18 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */
mbed_official 579:53297373a894 19 #define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
mbed_official 579:53297373a894 20 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */
mbed_official 579:53297373a894 21 #define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
mbed_official 579:53297373a894 22 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */
mbed_official 579:53297373a894 23 #define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
mbed_official 579:53297373a894 24 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */
mbed_official 579:53297373a894 25 #define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
mbed_official 579:53297373a894 26 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */
mbed_official 579:53297373a894 27 #define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
mbed_official 579:53297373a894 28 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */
mbed_official 579:53297373a894 29 #define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
mbed_official 579:53297373a894 30 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */
mbed_official 579:53297373a894 31 #define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
mbed_official 579:53297373a894 32 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */
mbed_official 579:53297373a894 33 #define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
mbed_official 579:53297373a894 34 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */
mbed_official 579:53297373a894 35 #define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
mbed_official 579:53297373a894 36 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */
mbed_official 579:53297373a894 37 #define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
mbed_official 579:53297373a894 38 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */
mbed_official 579:53297373a894 39 #define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
mbed_official 579:53297373a894 40 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */
mbed_official 579:53297373a894 41 #define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
mbed_official 579:53297373a894 42 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */
mbed_official 579:53297373a894 43 #define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
mbed_official 579:53297373a894 44 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */
mbed_official 579:53297373a894 45 #define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
mbed_official 579:53297373a894 46 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */
mbed_official 579:53297373a894 47 #define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
mbed_official 579:53297373a894 48 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */
mbed_official 579:53297373a894 49 #define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
mbed_official 579:53297373a894 50 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */
mbed_official 579:53297373a894 51 #define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
mbed_official 579:53297373a894 52 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */
mbed_official 579:53297373a894 53 #define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
mbed_official 579:53297373a894 54 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */
mbed_official 579:53297373a894 55 #define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
mbed_official 579:53297373a894 56 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */
mbed_official 579:53297373a894 57 #define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
mbed_official 579:53297373a894 58 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */
mbed_official 579:53297373a894 59 #define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */
mbed_official 579:53297373a894 60 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */
mbed_official 579:53297373a894 61 #define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
mbed_official 579:53297373a894 62 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */
mbed_official 579:53297373a894 63 #define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
mbed_official 579:53297373a894 64 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */
mbed_official 579:53297373a894 65 #define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
mbed_official 579:53297373a894 66 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */
mbed_official 579:53297373a894 67 #define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
mbed_official 579:53297373a894 68 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */
mbed_official 579:53297373a894 69 #define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */
mbed_official 579:53297373a894 70 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */
mbed_official 579:53297373a894 71 #define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */
mbed_official 579:53297373a894 72 #define PIN_PB16 48 /**< \brief Pin Number for PB16 */
mbed_official 579:53297373a894 73 #define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */
mbed_official 579:53297373a894 74 #define PIN_PB17 49 /**< \brief Pin Number for PB17 */
mbed_official 579:53297373a894 75 #define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */
mbed_official 579:53297373a894 76 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */
mbed_official 579:53297373a894 77 #define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
mbed_official 579:53297373a894 78 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */
mbed_official 579:53297373a894 79 #define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
mbed_official 579:53297373a894 80 #define PIN_PB30 62 /**< \brief Pin Number for PB30 */
mbed_official 579:53297373a894 81 #define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */
mbed_official 579:53297373a894 82 #define PIN_PB31 63 /**< \brief Pin Number for PB31 */
mbed_official 579:53297373a894 83 #define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */
mbed_official 579:53297373a894 84 #define PIN_PC16 80 /**< \brief Pin Number for PC16 */
mbed_official 579:53297373a894 85 #define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */
mbed_official 579:53297373a894 86 #define PIN_PC18 82 /**< \brief Pin Number for PC18 */
mbed_official 579:53297373a894 87 #define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */
mbed_official 579:53297373a894 88 #define PIN_PC19 83 /**< \brief Pin Number for PC19 */
mbed_official 579:53297373a894 89 #define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */
mbed_official 579:53297373a894 90 /* ========== PORT definition for GCLK peripheral ========== */
mbed_official 579:53297373a894 91 #define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */
mbed_official 579:53297373a894 92 #define MUX_PB14H_GCLK_IO0 7L
mbed_official 579:53297373a894 93 #define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
mbed_official 579:53297373a894 94 #define PORT_PB14H_GCLK_IO0 (1ul << 14)
mbed_official 579:53297373a894 95 #define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
mbed_official 579:53297373a894 96 #define MUX_PB22H_GCLK_IO0 7L
mbed_official 579:53297373a894 97 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
mbed_official 579:53297373a894 98 #define PORT_PB22H_GCLK_IO0 (1ul << 22)
mbed_official 579:53297373a894 99 #define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
mbed_official 579:53297373a894 100 #define MUX_PA14H_GCLK_IO0 7L
mbed_official 579:53297373a894 101 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
mbed_official 579:53297373a894 102 #define PORT_PA14H_GCLK_IO0 (1ul << 14)
mbed_official 579:53297373a894 103 #define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
mbed_official 579:53297373a894 104 #define MUX_PA27H_GCLK_IO0 7L
mbed_official 579:53297373a894 105 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
mbed_official 579:53297373a894 106 #define PORT_PA27H_GCLK_IO0 (1ul << 27)
mbed_official 579:53297373a894 107 #define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
mbed_official 579:53297373a894 108 #define MUX_PA28H_GCLK_IO0 7L
mbed_official 579:53297373a894 109 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
mbed_official 579:53297373a894 110 #define PORT_PA28H_GCLK_IO0 (1ul << 28)
mbed_official 579:53297373a894 111 #define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
mbed_official 579:53297373a894 112 #define MUX_PA30H_GCLK_IO0 7L
mbed_official 579:53297373a894 113 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
mbed_official 579:53297373a894 114 #define PORT_PA30H_GCLK_IO0 (1ul << 30)
mbed_official 579:53297373a894 115 #define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */
mbed_official 579:53297373a894 116 #define MUX_PB15H_GCLK_IO1 7L
mbed_official 579:53297373a894 117 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
mbed_official 579:53297373a894 118 #define PORT_PB15H_GCLK_IO1 (1ul << 15)
mbed_official 579:53297373a894 119 #define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
mbed_official 579:53297373a894 120 #define MUX_PB23H_GCLK_IO1 7L
mbed_official 579:53297373a894 121 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
mbed_official 579:53297373a894 122 #define PORT_PB23H_GCLK_IO1 (1ul << 23)
mbed_official 579:53297373a894 123 #define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
mbed_official 579:53297373a894 124 #define MUX_PA15H_GCLK_IO1 7L
mbed_official 579:53297373a894 125 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
mbed_official 579:53297373a894 126 #define PORT_PA15H_GCLK_IO1 (1ul << 15)
mbed_official 579:53297373a894 127 #define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */
mbed_official 579:53297373a894 128 #define MUX_PC16F_GCLK_IO1 5L
mbed_official 579:53297373a894 129 #define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1)
mbed_official 579:53297373a894 130 #define PORT_PC16F_GCLK_IO1 (1ul << 16)
mbed_official 579:53297373a894 131 #define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */
mbed_official 579:53297373a894 132 #define MUX_PB16H_GCLK_IO2 7L
mbed_official 579:53297373a894 133 #define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
mbed_official 579:53297373a894 134 #define PORT_PB16H_GCLK_IO2 (1ul << 16)
mbed_official 579:53297373a894 135 #define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
mbed_official 579:53297373a894 136 #define MUX_PA16H_GCLK_IO2 7L
mbed_official 579:53297373a894 137 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
mbed_official 579:53297373a894 138 #define PORT_PA16H_GCLK_IO2 (1ul << 16)
mbed_official 579:53297373a894 139 #define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
mbed_official 579:53297373a894 140 #define MUX_PA17H_GCLK_IO3 7L
mbed_official 579:53297373a894 141 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
mbed_official 579:53297373a894 142 #define PORT_PA17H_GCLK_IO3 (1ul << 17)
mbed_official 579:53297373a894 143 #define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */
mbed_official 579:53297373a894 144 #define MUX_PB17H_GCLK_IO3 7L
mbed_official 579:53297373a894 145 #define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
mbed_official 579:53297373a894 146 #define PORT_PB17H_GCLK_IO3 (1ul << 17)
mbed_official 579:53297373a894 147 #define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
mbed_official 579:53297373a894 148 #define MUX_PA10H_GCLK_IO4 7L
mbed_official 579:53297373a894 149 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
mbed_official 579:53297373a894 150 #define PORT_PA10H_GCLK_IO4 (1ul << 10)
mbed_official 579:53297373a894 151 #define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
mbed_official 579:53297373a894 152 #define MUX_PA20H_GCLK_IO4 7L
mbed_official 579:53297373a894 153 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
mbed_official 579:53297373a894 154 #define PORT_PA20H_GCLK_IO4 (1ul << 20)
mbed_official 579:53297373a894 155 #define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
mbed_official 579:53297373a894 156 #define MUX_PA11H_GCLK_IO5 7L
mbed_official 579:53297373a894 157 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
mbed_official 579:53297373a894 158 #define PORT_PA11H_GCLK_IO5 (1ul << 11)
mbed_official 579:53297373a894 159 #define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
mbed_official 579:53297373a894 160 #define MUX_PA22H_GCLK_IO6 7L
mbed_official 579:53297373a894 161 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
mbed_official 579:53297373a894 162 #define PORT_PA22H_GCLK_IO6 (1ul << 22)
mbed_official 579:53297373a894 163 #define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
mbed_official 579:53297373a894 164 #define MUX_PA23H_GCLK_IO7 7L
mbed_official 579:53297373a894 165 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
mbed_official 579:53297373a894 166 #define PORT_PA23H_GCLK_IO7 (1ul << 23)
mbed_official 579:53297373a894 167 /* ========== PORT definition for EIC peripheral ========== */
mbed_official 579:53297373a894 168 #define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
mbed_official 579:53297373a894 169 #define MUX_PA16A_EIC_EXTINT0 0L
mbed_official 579:53297373a894 170 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
mbed_official 579:53297373a894 171 #define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
mbed_official 579:53297373a894 172 #define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */
mbed_official 579:53297373a894 173 #define MUX_PB00A_EIC_EXTINT0 0L
mbed_official 579:53297373a894 174 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
mbed_official 579:53297373a894 175 #define PORT_PB00A_EIC_EXTINT0 (1ul << 0)
mbed_official 579:53297373a894 176 #define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */
mbed_official 579:53297373a894 177 #define MUX_PB16A_EIC_EXTINT0 0L
mbed_official 579:53297373a894 178 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
mbed_official 579:53297373a894 179 #define PORT_PB16A_EIC_EXTINT0 (1ul << 16)
mbed_official 579:53297373a894 180 #define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
mbed_official 579:53297373a894 181 #define MUX_PA00A_EIC_EXTINT0 0L
mbed_official 579:53297373a894 182 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
mbed_official 579:53297373a894 183 #define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
mbed_official 579:53297373a894 184 #define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
mbed_official 579:53297373a894 185 #define MUX_PA17A_EIC_EXTINT1 0L
mbed_official 579:53297373a894 186 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
mbed_official 579:53297373a894 187 #define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
mbed_official 579:53297373a894 188 #define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */
mbed_official 579:53297373a894 189 #define MUX_PB17A_EIC_EXTINT1 0L
mbed_official 579:53297373a894 190 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
mbed_official 579:53297373a894 191 #define PORT_PB17A_EIC_EXTINT1 (1ul << 17)
mbed_official 579:53297373a894 192 #define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
mbed_official 579:53297373a894 193 #define MUX_PA01A_EIC_EXTINT1 0L
mbed_official 579:53297373a894 194 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
mbed_official 579:53297373a894 195 #define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
mbed_official 579:53297373a894 196 #define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
mbed_official 579:53297373a894 197 #define MUX_PA18A_EIC_EXTINT2 0L
mbed_official 579:53297373a894 198 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
mbed_official 579:53297373a894 199 #define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
mbed_official 579:53297373a894 200 #define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
mbed_official 579:53297373a894 201 #define MUX_PB02A_EIC_EXTINT2 0L
mbed_official 579:53297373a894 202 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
mbed_official 579:53297373a894 203 #define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
mbed_official 579:53297373a894 204 #define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
mbed_official 579:53297373a894 205 #define MUX_PA19A_EIC_EXTINT3 0L
mbed_official 579:53297373a894 206 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
mbed_official 579:53297373a894 207 #define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
mbed_official 579:53297373a894 208 #define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
mbed_official 579:53297373a894 209 #define MUX_PB03A_EIC_EXTINT3 0L
mbed_official 579:53297373a894 210 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
mbed_official 579:53297373a894 211 #define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
mbed_official 579:53297373a894 212 #define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
mbed_official 579:53297373a894 213 #define MUX_PA04A_EIC_EXTINT4 0L
mbed_official 579:53297373a894 214 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
mbed_official 579:53297373a894 215 #define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
mbed_official 579:53297373a894 216 #define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
mbed_official 579:53297373a894 217 #define MUX_PA20A_EIC_EXTINT4 0L
mbed_official 579:53297373a894 218 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
mbed_official 579:53297373a894 219 #define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
mbed_official 579:53297373a894 220 #define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
mbed_official 579:53297373a894 221 #define MUX_PA05A_EIC_EXTINT5 0L
mbed_official 579:53297373a894 222 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
mbed_official 579:53297373a894 223 #define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
mbed_official 579:53297373a894 224 #define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
mbed_official 579:53297373a894 225 #define MUX_PA06A_EIC_EXTINT6 0L
mbed_official 579:53297373a894 226 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
mbed_official 579:53297373a894 227 #define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
mbed_official 579:53297373a894 228 #define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
mbed_official 579:53297373a894 229 #define MUX_PA22A_EIC_EXTINT6 0L
mbed_official 579:53297373a894 230 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
mbed_official 579:53297373a894 231 #define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
mbed_official 579:53297373a894 232 #define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
mbed_official 579:53297373a894 233 #define MUX_PB22A_EIC_EXTINT6 0L
mbed_official 579:53297373a894 234 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
mbed_official 579:53297373a894 235 #define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
mbed_official 579:53297373a894 236 #define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
mbed_official 579:53297373a894 237 #define MUX_PA07A_EIC_EXTINT7 0L
mbed_official 579:53297373a894 238 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
mbed_official 579:53297373a894 239 #define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
mbed_official 579:53297373a894 240 #define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
mbed_official 579:53297373a894 241 #define MUX_PA23A_EIC_EXTINT7 0L
mbed_official 579:53297373a894 242 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
mbed_official 579:53297373a894 243 #define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
mbed_official 579:53297373a894 244 #define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
mbed_official 579:53297373a894 245 #define MUX_PB23A_EIC_EXTINT7 0L
mbed_official 579:53297373a894 246 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
mbed_official 579:53297373a894 247 #define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
mbed_official 579:53297373a894 248 #define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
mbed_official 579:53297373a894 249 #define MUX_PA28A_EIC_EXTINT8 0L
mbed_official 579:53297373a894 250 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
mbed_official 579:53297373a894 251 #define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
mbed_official 579:53297373a894 252 #define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
mbed_official 579:53297373a894 253 #define MUX_PB08A_EIC_EXTINT8 0L
mbed_official 579:53297373a894 254 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
mbed_official 579:53297373a894 255 #define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
mbed_official 579:53297373a894 256 #define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
mbed_official 579:53297373a894 257 #define MUX_PA09A_EIC_EXTINT9 0L
mbed_official 579:53297373a894 258 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
mbed_official 579:53297373a894 259 #define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
mbed_official 579:53297373a894 260 #define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
mbed_official 579:53297373a894 261 #define MUX_PB09A_EIC_EXTINT9 0L
mbed_official 579:53297373a894 262 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
mbed_official 579:53297373a894 263 #define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
mbed_official 579:53297373a894 264 #define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
mbed_official 579:53297373a894 265 #define MUX_PA10A_EIC_EXTINT10 0L
mbed_official 579:53297373a894 266 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
mbed_official 579:53297373a894 267 #define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
mbed_official 579:53297373a894 268 #define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
mbed_official 579:53297373a894 269 #define MUX_PA30A_EIC_EXTINT10 0L
mbed_official 579:53297373a894 270 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
mbed_official 579:53297373a894 271 #define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
mbed_official 579:53297373a894 272 #define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
mbed_official 579:53297373a894 273 #define MUX_PA11A_EIC_EXTINT11 0L
mbed_official 579:53297373a894 274 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
mbed_official 579:53297373a894 275 #define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
mbed_official 579:53297373a894 276 #define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
mbed_official 579:53297373a894 277 #define MUX_PA31A_EIC_EXTINT11 0L
mbed_official 579:53297373a894 278 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
mbed_official 579:53297373a894 279 #define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
mbed_official 579:53297373a894 280 #define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
mbed_official 579:53297373a894 281 #define MUX_PA12A_EIC_EXTINT12 0L
mbed_official 579:53297373a894 282 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
mbed_official 579:53297373a894 283 #define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
mbed_official 579:53297373a894 284 #define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
mbed_official 579:53297373a894 285 #define MUX_PA24A_EIC_EXTINT12 0L
mbed_official 579:53297373a894 286 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
mbed_official 579:53297373a894 287 #define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
mbed_official 579:53297373a894 288 #define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
mbed_official 579:53297373a894 289 #define MUX_PA13A_EIC_EXTINT13 0L
mbed_official 579:53297373a894 290 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
mbed_official 579:53297373a894 291 #define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
mbed_official 579:53297373a894 292 #define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
mbed_official 579:53297373a894 293 #define MUX_PA25A_EIC_EXTINT13 0L
mbed_official 579:53297373a894 294 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
mbed_official 579:53297373a894 295 #define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
mbed_official 579:53297373a894 296 #define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */
mbed_official 579:53297373a894 297 #define MUX_PB14A_EIC_EXTINT14 0L
mbed_official 579:53297373a894 298 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
mbed_official 579:53297373a894 299 #define PORT_PB14A_EIC_EXTINT14 (1ul << 14)
mbed_official 579:53297373a894 300 #define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */
mbed_official 579:53297373a894 301 #define MUX_PB30A_EIC_EXTINT14 0L
mbed_official 579:53297373a894 302 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
mbed_official 579:53297373a894 303 #define PORT_PB30A_EIC_EXTINT14 (1ul << 30)
mbed_official 579:53297373a894 304 #define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
mbed_official 579:53297373a894 305 #define MUX_PA14A_EIC_EXTINT14 0L
mbed_official 579:53297373a894 306 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
mbed_official 579:53297373a894 307 #define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
mbed_official 579:53297373a894 308 #define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
mbed_official 579:53297373a894 309 #define MUX_PA15A_EIC_EXTINT15 0L
mbed_official 579:53297373a894 310 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
mbed_official 579:53297373a894 311 #define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
mbed_official 579:53297373a894 312 #define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
mbed_official 579:53297373a894 313 #define MUX_PA27A_EIC_EXTINT15 0L
mbed_official 579:53297373a894 314 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
mbed_official 579:53297373a894 315 #define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
mbed_official 579:53297373a894 316 #define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */
mbed_official 579:53297373a894 317 #define MUX_PB15A_EIC_EXTINT15 0L
mbed_official 579:53297373a894 318 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
mbed_official 579:53297373a894 319 #define PORT_PB15A_EIC_EXTINT15 (1ul << 15)
mbed_official 579:53297373a894 320 #define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */
mbed_official 579:53297373a894 321 #define MUX_PB31A_EIC_EXTINT15 0L
mbed_official 579:53297373a894 322 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
mbed_official 579:53297373a894 323 #define PORT_PB31A_EIC_EXTINT15 (1ul << 31)
mbed_official 579:53297373a894 324 #define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
mbed_official 579:53297373a894 325 #define MUX_PA08A_EIC_NMI 0L
mbed_official 579:53297373a894 326 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
mbed_official 579:53297373a894 327 #define PORT_PA08A_EIC_NMI (1ul << 8)
mbed_official 579:53297373a894 328 /* ========== PORT definition for USB peripheral ========== */
mbed_official 579:53297373a894 329 #define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
mbed_official 579:53297373a894 330 #define MUX_PA24G_USB_DM 6L
mbed_official 579:53297373a894 331 #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
mbed_official 579:53297373a894 332 #define PORT_PA24G_USB_DM (1ul << 24)
mbed_official 579:53297373a894 333 #define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
mbed_official 579:53297373a894 334 #define MUX_PA25G_USB_DP 6L
mbed_official 579:53297373a894 335 #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
mbed_official 579:53297373a894 336 #define PORT_PA25G_USB_DP (1ul << 25)
mbed_official 579:53297373a894 337 #define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
mbed_official 579:53297373a894 338 #define MUX_PA23G_USB_SOF_1KHZ 6L
mbed_official 579:53297373a894 339 #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
mbed_official 579:53297373a894 340 #define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
mbed_official 579:53297373a894 341 /* ========== PORT definition for SERCOM0 peripheral ========== */
mbed_official 579:53297373a894 342 #define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
mbed_official 579:53297373a894 343 #define MUX_PA04D_SERCOM0_PAD0 3L
mbed_official 579:53297373a894 344 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
mbed_official 579:53297373a894 345 #define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
mbed_official 579:53297373a894 346 #define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
mbed_official 579:53297373a894 347 #define MUX_PA08C_SERCOM0_PAD0 2L
mbed_official 579:53297373a894 348 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
mbed_official 579:53297373a894 349 #define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
mbed_official 579:53297373a894 350 #define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
mbed_official 579:53297373a894 351 #define MUX_PA05D_SERCOM0_PAD1 3L
mbed_official 579:53297373a894 352 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
mbed_official 579:53297373a894 353 #define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
mbed_official 579:53297373a894 354 #define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
mbed_official 579:53297373a894 355 #define MUX_PA09C_SERCOM0_PAD1 2L
mbed_official 579:53297373a894 356 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
mbed_official 579:53297373a894 357 #define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
mbed_official 579:53297373a894 358 #define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
mbed_official 579:53297373a894 359 #define MUX_PA06D_SERCOM0_PAD2 3L
mbed_official 579:53297373a894 360 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
mbed_official 579:53297373a894 361 #define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
mbed_official 579:53297373a894 362 #define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
mbed_official 579:53297373a894 363 #define MUX_PA10C_SERCOM0_PAD2 2L
mbed_official 579:53297373a894 364 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
mbed_official 579:53297373a894 365 #define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
mbed_official 579:53297373a894 366 #define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
mbed_official 579:53297373a894 367 #define MUX_PA07D_SERCOM0_PAD3 3L
mbed_official 579:53297373a894 368 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
mbed_official 579:53297373a894 369 #define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
mbed_official 579:53297373a894 370 #define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
mbed_official 579:53297373a894 371 #define MUX_PA11C_SERCOM0_PAD3 2L
mbed_official 579:53297373a894 372 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
mbed_official 579:53297373a894 373 #define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
mbed_official 579:53297373a894 374 /* ========== PORT definition for SERCOM1 peripheral ========== */
mbed_official 579:53297373a894 375 #define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
mbed_official 579:53297373a894 376 #define MUX_PA16C_SERCOM1_PAD0 2L
mbed_official 579:53297373a894 377 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
mbed_official 579:53297373a894 378 #define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
mbed_official 579:53297373a894 379 #define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
mbed_official 579:53297373a894 380 #define MUX_PA00D_SERCOM1_PAD0 3L
mbed_official 579:53297373a894 381 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
mbed_official 579:53297373a894 382 #define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
mbed_official 579:53297373a894 383 #define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
mbed_official 579:53297373a894 384 #define MUX_PA17C_SERCOM1_PAD1 2L
mbed_official 579:53297373a894 385 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
mbed_official 579:53297373a894 386 #define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
mbed_official 579:53297373a894 387 #define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
mbed_official 579:53297373a894 388 #define MUX_PA01D_SERCOM1_PAD1 3L
mbed_official 579:53297373a894 389 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
mbed_official 579:53297373a894 390 #define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
mbed_official 579:53297373a894 391 #define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
mbed_official 579:53297373a894 392 #define MUX_PA30D_SERCOM1_PAD2 3L
mbed_official 579:53297373a894 393 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
mbed_official 579:53297373a894 394 #define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
mbed_official 579:53297373a894 395 #define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
mbed_official 579:53297373a894 396 #define MUX_PA18C_SERCOM1_PAD2 2L
mbed_official 579:53297373a894 397 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
mbed_official 579:53297373a894 398 #define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
mbed_official 579:53297373a894 399 #define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
mbed_official 579:53297373a894 400 #define MUX_PA31D_SERCOM1_PAD3 3L
mbed_official 579:53297373a894 401 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
mbed_official 579:53297373a894 402 #define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
mbed_official 579:53297373a894 403 #define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
mbed_official 579:53297373a894 404 #define MUX_PA19C_SERCOM1_PAD3 2L
mbed_official 579:53297373a894 405 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
mbed_official 579:53297373a894 406 #define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
mbed_official 579:53297373a894 407 /* ========== PORT definition for SERCOM2 peripheral ========== */
mbed_official 579:53297373a894 408 #define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
mbed_official 579:53297373a894 409 #define MUX_PA08D_SERCOM2_PAD0 3L
mbed_official 579:53297373a894 410 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
mbed_official 579:53297373a894 411 #define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
mbed_official 579:53297373a894 412 #define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
mbed_official 579:53297373a894 413 #define MUX_PA12C_SERCOM2_PAD0 2L
mbed_official 579:53297373a894 414 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
mbed_official 579:53297373a894 415 #define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
mbed_official 579:53297373a894 416 #define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
mbed_official 579:53297373a894 417 #define MUX_PA09D_SERCOM2_PAD1 3L
mbed_official 579:53297373a894 418 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
mbed_official 579:53297373a894 419 #define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
mbed_official 579:53297373a894 420 #define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
mbed_official 579:53297373a894 421 #define MUX_PA13C_SERCOM2_PAD1 2L
mbed_official 579:53297373a894 422 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
mbed_official 579:53297373a894 423 #define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
mbed_official 579:53297373a894 424 #define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
mbed_official 579:53297373a894 425 #define MUX_PA10D_SERCOM2_PAD2 3L
mbed_official 579:53297373a894 426 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
mbed_official 579:53297373a894 427 #define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
mbed_official 579:53297373a894 428 #define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
mbed_official 579:53297373a894 429 #define MUX_PA14C_SERCOM2_PAD2 2L
mbed_official 579:53297373a894 430 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
mbed_official 579:53297373a894 431 #define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
mbed_official 579:53297373a894 432 #define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
mbed_official 579:53297373a894 433 #define MUX_PA11D_SERCOM2_PAD3 3L
mbed_official 579:53297373a894 434 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
mbed_official 579:53297373a894 435 #define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
mbed_official 579:53297373a894 436 #define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
mbed_official 579:53297373a894 437 #define MUX_PA15C_SERCOM2_PAD3 2L
mbed_official 579:53297373a894 438 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
mbed_official 579:53297373a894 439 #define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
mbed_official 579:53297373a894 440 /* ========== PORT definition for SERCOM3 peripheral ========== */
mbed_official 579:53297373a894 441 #define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
mbed_official 579:53297373a894 442 #define MUX_PA16D_SERCOM3_PAD0 3L
mbed_official 579:53297373a894 443 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
mbed_official 579:53297373a894 444 #define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
mbed_official 579:53297373a894 445 #define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
mbed_official 579:53297373a894 446 #define MUX_PA22C_SERCOM3_PAD0 2L
mbed_official 579:53297373a894 447 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
mbed_official 579:53297373a894 448 #define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
mbed_official 579:53297373a894 449 #define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
mbed_official 579:53297373a894 450 #define MUX_PA27F_SERCOM3_PAD0 5L
mbed_official 579:53297373a894 451 #define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
mbed_official 579:53297373a894 452 #define PORT_PA27F_SERCOM3_PAD0 (1ul << 27)
mbed_official 579:53297373a894 453 #define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
mbed_official 579:53297373a894 454 #define MUX_PA17D_SERCOM3_PAD1 3L
mbed_official 579:53297373a894 455 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
mbed_official 579:53297373a894 456 #define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
mbed_official 579:53297373a894 457 #define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
mbed_official 579:53297373a894 458 #define MUX_PA23C_SERCOM3_PAD1 2L
mbed_official 579:53297373a894 459 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
mbed_official 579:53297373a894 460 #define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
mbed_official 579:53297373a894 461 #define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
mbed_official 579:53297373a894 462 #define MUX_PA28F_SERCOM3_PAD1 5L
mbed_official 579:53297373a894 463 #define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
mbed_official 579:53297373a894 464 #define PORT_PA28F_SERCOM3_PAD1 (1ul << 28)
mbed_official 579:53297373a894 465 #define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
mbed_official 579:53297373a894 466 #define MUX_PA18D_SERCOM3_PAD2 3L
mbed_official 579:53297373a894 467 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
mbed_official 579:53297373a894 468 #define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
mbed_official 579:53297373a894 469 #define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
mbed_official 579:53297373a894 470 #define MUX_PA20D_SERCOM3_PAD2 3L
mbed_official 579:53297373a894 471 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
mbed_official 579:53297373a894 472 #define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
mbed_official 579:53297373a894 473 #define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
mbed_official 579:53297373a894 474 #define MUX_PA24C_SERCOM3_PAD2 2L
mbed_official 579:53297373a894 475 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
mbed_official 579:53297373a894 476 #define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
mbed_official 579:53297373a894 477 #define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
mbed_official 579:53297373a894 478 #define MUX_PA19D_SERCOM3_PAD3 3L
mbed_official 579:53297373a894 479 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
mbed_official 579:53297373a894 480 #define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
mbed_official 579:53297373a894 481 #define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
mbed_official 579:53297373a894 482 #define MUX_PA25C_SERCOM3_PAD3 2L
mbed_official 579:53297373a894 483 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
mbed_official 579:53297373a894 484 #define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
mbed_official 579:53297373a894 485 /* ========== PORT definition for SERCOM4 peripheral ========== */
mbed_official 579:53297373a894 486 #define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
mbed_official 579:53297373a894 487 #define MUX_PA12D_SERCOM4_PAD0 3L
mbed_official 579:53297373a894 488 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
mbed_official 579:53297373a894 489 #define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
mbed_official 579:53297373a894 490 #define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
mbed_official 579:53297373a894 491 #define MUX_PB08D_SERCOM4_PAD0 3L
mbed_official 579:53297373a894 492 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
mbed_official 579:53297373a894 493 #define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
mbed_official 579:53297373a894 494 #define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */
mbed_official 579:53297373a894 495 #define MUX_PC19F_SERCOM4_PAD0 5L
mbed_official 579:53297373a894 496 #define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0)
mbed_official 579:53297373a894 497 #define PORT_PC19F_SERCOM4_PAD0 (1ul << 19)
mbed_official 579:53297373a894 498 #define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
mbed_official 579:53297373a894 499 #define MUX_PA13D_SERCOM4_PAD1 3L
mbed_official 579:53297373a894 500 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
mbed_official 579:53297373a894 501 #define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
mbed_official 579:53297373a894 502 #define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
mbed_official 579:53297373a894 503 #define MUX_PB09D_SERCOM4_PAD1 3L
mbed_official 579:53297373a894 504 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
mbed_official 579:53297373a894 505 #define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
mbed_official 579:53297373a894 506 #define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */
mbed_official 579:53297373a894 507 #define MUX_PB31F_SERCOM4_PAD1 5L
mbed_official 579:53297373a894 508 #define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1)
mbed_official 579:53297373a894 509 #define PORT_PB31F_SERCOM4_PAD1 (1ul << 31)
mbed_official 579:53297373a894 510 #define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
mbed_official 579:53297373a894 511 #define MUX_PA14D_SERCOM4_PAD2 3L
mbed_official 579:53297373a894 512 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
mbed_official 579:53297373a894 513 #define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
mbed_official 579:53297373a894 514 #define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
mbed_official 579:53297373a894 515 #define MUX_PB14C_SERCOM4_PAD2 2L
mbed_official 579:53297373a894 516 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
mbed_official 579:53297373a894 517 #define PORT_PB14C_SERCOM4_PAD2 (1ul << 14)
mbed_official 579:53297373a894 518 #define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */
mbed_official 579:53297373a894 519 #define MUX_PB30F_SERCOM4_PAD2 5L
mbed_official 579:53297373a894 520 #define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2)
mbed_official 579:53297373a894 521 #define PORT_PB30F_SERCOM4_PAD2 (1ul << 30)
mbed_official 579:53297373a894 522 #define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
mbed_official 579:53297373a894 523 #define MUX_PA15D_SERCOM4_PAD3 3L
mbed_official 579:53297373a894 524 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
mbed_official 579:53297373a894 525 #define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
mbed_official 579:53297373a894 526 #define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
mbed_official 579:53297373a894 527 #define MUX_PB15C_SERCOM4_PAD3 2L
mbed_official 579:53297373a894 528 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
mbed_official 579:53297373a894 529 #define PORT_PB15C_SERCOM4_PAD3 (1ul << 15)
mbed_official 579:53297373a894 530 #define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */
mbed_official 579:53297373a894 531 #define MUX_PC18F_SERCOM4_PAD3 5L
mbed_official 579:53297373a894 532 #define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3)
mbed_official 579:53297373a894 533 #define PORT_PC18F_SERCOM4_PAD3 (1ul << 18)
mbed_official 579:53297373a894 534 /* ========== PORT definition for SERCOM5 peripheral ========== */
mbed_official 579:53297373a894 535 #define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
mbed_official 579:53297373a894 536 #define MUX_PB16C_SERCOM5_PAD0 2L
mbed_official 579:53297373a894 537 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
mbed_official 579:53297373a894 538 #define PORT_PB16C_SERCOM5_PAD0 (1ul << 16)
mbed_official 579:53297373a894 539 #define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
mbed_official 579:53297373a894 540 #define MUX_PA22D_SERCOM5_PAD0 3L
mbed_official 579:53297373a894 541 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
mbed_official 579:53297373a894 542 #define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
mbed_official 579:53297373a894 543 #define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
mbed_official 579:53297373a894 544 #define MUX_PB02D_SERCOM5_PAD0 3L
mbed_official 579:53297373a894 545 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
mbed_official 579:53297373a894 546 #define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
mbed_official 579:53297373a894 547 #define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
mbed_official 579:53297373a894 548 #define MUX_PB30D_SERCOM5_PAD0 3L
mbed_official 579:53297373a894 549 #define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
mbed_official 579:53297373a894 550 #define PORT_PB30D_SERCOM5_PAD0 (1ul << 30)
mbed_official 579:53297373a894 551 #define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
mbed_official 579:53297373a894 552 #define MUX_PB17C_SERCOM5_PAD1 2L
mbed_official 579:53297373a894 553 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
mbed_official 579:53297373a894 554 #define PORT_PB17C_SERCOM5_PAD1 (1ul << 17)
mbed_official 579:53297373a894 555 #define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
mbed_official 579:53297373a894 556 #define MUX_PA23D_SERCOM5_PAD1 3L
mbed_official 579:53297373a894 557 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
mbed_official 579:53297373a894 558 #define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
mbed_official 579:53297373a894 559 #define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
mbed_official 579:53297373a894 560 #define MUX_PB03D_SERCOM5_PAD1 3L
mbed_official 579:53297373a894 561 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
mbed_official 579:53297373a894 562 #define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
mbed_official 579:53297373a894 563 #define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
mbed_official 579:53297373a894 564 #define MUX_PB31D_SERCOM5_PAD1 3L
mbed_official 579:53297373a894 565 #define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
mbed_official 579:53297373a894 566 #define PORT_PB31D_SERCOM5_PAD1 (1ul << 31)
mbed_official 579:53297373a894 567 #define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
mbed_official 579:53297373a894 568 #define MUX_PA24D_SERCOM5_PAD2 3L
mbed_official 579:53297373a894 569 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
mbed_official 579:53297373a894 570 #define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
mbed_official 579:53297373a894 571 #define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
mbed_official 579:53297373a894 572 #define MUX_PB00D_SERCOM5_PAD2 3L
mbed_official 579:53297373a894 573 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
mbed_official 579:53297373a894 574 #define PORT_PB00D_SERCOM5_PAD2 (1ul << 0)
mbed_official 579:53297373a894 575 #define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
mbed_official 579:53297373a894 576 #define MUX_PB22D_SERCOM5_PAD2 3L
mbed_official 579:53297373a894 577 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
mbed_official 579:53297373a894 578 #define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
mbed_official 579:53297373a894 579 #define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
mbed_official 579:53297373a894 580 #define MUX_PA20C_SERCOM5_PAD2 2L
mbed_official 579:53297373a894 581 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
mbed_official 579:53297373a894 582 #define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
mbed_official 579:53297373a894 583 #define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
mbed_official 579:53297373a894 584 #define MUX_PA25D_SERCOM5_PAD3 3L
mbed_official 579:53297373a894 585 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
mbed_official 579:53297373a894 586 #define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
mbed_official 579:53297373a894 587 #define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
mbed_official 579:53297373a894 588 #define MUX_PB23D_SERCOM5_PAD3 3L
mbed_official 579:53297373a894 589 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
mbed_official 579:53297373a894 590 #define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
mbed_official 579:53297373a894 591 /* ========== PORT definition for TCC0 peripheral ========== */
mbed_official 579:53297373a894 592 #define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
mbed_official 579:53297373a894 593 #define MUX_PA04E_TCC0_WO0 4L
mbed_official 579:53297373a894 594 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
mbed_official 579:53297373a894 595 #define PORT_PA04E_TCC0_WO0 (1ul << 4)
mbed_official 579:53297373a894 596 #define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
mbed_official 579:53297373a894 597 #define MUX_PA08E_TCC0_WO0 4L
mbed_official 579:53297373a894 598 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
mbed_official 579:53297373a894 599 #define PORT_PA08E_TCC0_WO0 (1ul << 8)
mbed_official 579:53297373a894 600 #define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */
mbed_official 579:53297373a894 601 #define MUX_PB30E_TCC0_WO0 4L
mbed_official 579:53297373a894 602 #define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
mbed_official 579:53297373a894 603 #define PORT_PB30E_TCC0_WO0 (1ul << 30)
mbed_official 579:53297373a894 604 #define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */
mbed_official 579:53297373a894 605 #define MUX_PA16F_TCC0_WO0 5L
mbed_official 579:53297373a894 606 #define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
mbed_official 579:53297373a894 607 #define PORT_PA16F_TCC0_WO0 (1ul << 16)
mbed_official 579:53297373a894 608 #define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
mbed_official 579:53297373a894 609 #define MUX_PA05E_TCC0_WO1 4L
mbed_official 579:53297373a894 610 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
mbed_official 579:53297373a894 611 #define PORT_PA05E_TCC0_WO1 (1ul << 5)
mbed_official 579:53297373a894 612 #define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
mbed_official 579:53297373a894 613 #define MUX_PA09E_TCC0_WO1 4L
mbed_official 579:53297373a894 614 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
mbed_official 579:53297373a894 615 #define PORT_PA09E_TCC0_WO1 (1ul << 9)
mbed_official 579:53297373a894 616 #define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */
mbed_official 579:53297373a894 617 #define MUX_PB31E_TCC0_WO1 4L
mbed_official 579:53297373a894 618 #define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
mbed_official 579:53297373a894 619 #define PORT_PB31E_TCC0_WO1 (1ul << 31)
mbed_official 579:53297373a894 620 #define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */
mbed_official 579:53297373a894 621 #define MUX_PA17F_TCC0_WO1 5L
mbed_official 579:53297373a894 622 #define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
mbed_official 579:53297373a894 623 #define PORT_PA17F_TCC0_WO1 (1ul << 17)
mbed_official 579:53297373a894 624 #define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
mbed_official 579:53297373a894 625 #define MUX_PA10F_TCC0_WO2 5L
mbed_official 579:53297373a894 626 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
mbed_official 579:53297373a894 627 #define PORT_PA10F_TCC0_WO2 (1ul << 10)
mbed_official 579:53297373a894 628 #define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
mbed_official 579:53297373a894 629 #define MUX_PA18F_TCC0_WO2 5L
mbed_official 579:53297373a894 630 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
mbed_official 579:53297373a894 631 #define PORT_PA18F_TCC0_WO2 (1ul << 18)
mbed_official 579:53297373a894 632 #define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
mbed_official 579:53297373a894 633 #define MUX_PA11F_TCC0_WO3 5L
mbed_official 579:53297373a894 634 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
mbed_official 579:53297373a894 635 #define PORT_PA11F_TCC0_WO3 (1ul << 11)
mbed_official 579:53297373a894 636 #define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
mbed_official 579:53297373a894 637 #define MUX_PA19F_TCC0_WO3 5L
mbed_official 579:53297373a894 638 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
mbed_official 579:53297373a894 639 #define PORT_PA19F_TCC0_WO3 (1ul << 19)
mbed_official 579:53297373a894 640 #define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
mbed_official 579:53297373a894 641 #define MUX_PA22F_TCC0_WO4 5L
mbed_official 579:53297373a894 642 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
mbed_official 579:53297373a894 643 #define PORT_PA22F_TCC0_WO4 (1ul << 22)
mbed_official 579:53297373a894 644 #define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */
mbed_official 579:53297373a894 645 #define MUX_PB16F_TCC0_WO4 5L
mbed_official 579:53297373a894 646 #define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
mbed_official 579:53297373a894 647 #define PORT_PB16F_TCC0_WO4 (1ul << 16)
mbed_official 579:53297373a894 648 #define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
mbed_official 579:53297373a894 649 #define MUX_PA23F_TCC0_WO5 5L
mbed_official 579:53297373a894 650 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
mbed_official 579:53297373a894 651 #define PORT_PA23F_TCC0_WO5 (1ul << 23)
mbed_official 579:53297373a894 652 #define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */
mbed_official 579:53297373a894 653 #define MUX_PB17F_TCC0_WO5 5L
mbed_official 579:53297373a894 654 #define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
mbed_official 579:53297373a894 655 #define PORT_PB17F_TCC0_WO5 (1ul << 17)
mbed_official 579:53297373a894 656 #define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
mbed_official 579:53297373a894 657 #define MUX_PA20F_TCC0_WO6 5L
mbed_official 579:53297373a894 658 #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
mbed_official 579:53297373a894 659 #define PORT_PA20F_TCC0_WO6 (1ul << 20)
mbed_official 579:53297373a894 660 /* ========== PORT definition for TCC1 peripheral ========== */
mbed_official 579:53297373a894 661 #define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
mbed_official 579:53297373a894 662 #define MUX_PA06E_TCC1_WO0 4L
mbed_official 579:53297373a894 663 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
mbed_official 579:53297373a894 664 #define PORT_PA06E_TCC1_WO0 (1ul << 6)
mbed_official 579:53297373a894 665 #define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
mbed_official 579:53297373a894 666 #define MUX_PA10E_TCC1_WO0 4L
mbed_official 579:53297373a894 667 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
mbed_official 579:53297373a894 668 #define PORT_PA10E_TCC1_WO0 (1ul << 10)
mbed_official 579:53297373a894 669 #define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
mbed_official 579:53297373a894 670 #define MUX_PA30E_TCC1_WO0 4L
mbed_official 579:53297373a894 671 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
mbed_official 579:53297373a894 672 #define PORT_PA30E_TCC1_WO0 (1ul << 30)
mbed_official 579:53297373a894 673 #define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
mbed_official 579:53297373a894 674 #define MUX_PA07E_TCC1_WO1 4L
mbed_official 579:53297373a894 675 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
mbed_official 579:53297373a894 676 #define PORT_PA07E_TCC1_WO1 (1ul << 7)
mbed_official 579:53297373a894 677 #define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
mbed_official 579:53297373a894 678 #define MUX_PA11E_TCC1_WO1 4L
mbed_official 579:53297373a894 679 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
mbed_official 579:53297373a894 680 #define PORT_PA11E_TCC1_WO1 (1ul << 11)
mbed_official 579:53297373a894 681 #define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
mbed_official 579:53297373a894 682 #define MUX_PA31E_TCC1_WO1 4L
mbed_official 579:53297373a894 683 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
mbed_official 579:53297373a894 684 #define PORT_PA31E_TCC1_WO1 (1ul << 31)
mbed_official 579:53297373a894 685 #define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
mbed_official 579:53297373a894 686 #define MUX_PA24F_TCC1_WO2 5L
mbed_official 579:53297373a894 687 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
mbed_official 579:53297373a894 688 #define PORT_PA24F_TCC1_WO2 (1ul << 24)
mbed_official 579:53297373a894 689 #define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
mbed_official 579:53297373a894 690 #define MUX_PA25F_TCC1_WO3 5L
mbed_official 579:53297373a894 691 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
mbed_official 579:53297373a894 692 #define PORT_PA25F_TCC1_WO3 (1ul << 25)
mbed_official 579:53297373a894 693 /* ========== PORT definition for TCC2 peripheral ========== */
mbed_official 579:53297373a894 694 #define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
mbed_official 579:53297373a894 695 #define MUX_PA12E_TCC2_WO0 4L
mbed_official 579:53297373a894 696 #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
mbed_official 579:53297373a894 697 #define PORT_PA12E_TCC2_WO0 (1ul << 12)
mbed_official 579:53297373a894 698 #define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
mbed_official 579:53297373a894 699 #define MUX_PA16E_TCC2_WO0 4L
mbed_official 579:53297373a894 700 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
mbed_official 579:53297373a894 701 #define PORT_PA16E_TCC2_WO0 (1ul << 16)
mbed_official 579:53297373a894 702 #define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
mbed_official 579:53297373a894 703 #define MUX_PA00E_TCC2_WO0 4L
mbed_official 579:53297373a894 704 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
mbed_official 579:53297373a894 705 #define PORT_PA00E_TCC2_WO0 (1ul << 0)
mbed_official 579:53297373a894 706 #define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
mbed_official 579:53297373a894 707 #define MUX_PA13E_TCC2_WO1 4L
mbed_official 579:53297373a894 708 #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
mbed_official 579:53297373a894 709 #define PORT_PA13E_TCC2_WO1 (1ul << 13)
mbed_official 579:53297373a894 710 #define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
mbed_official 579:53297373a894 711 #define MUX_PA17E_TCC2_WO1 4L
mbed_official 579:53297373a894 712 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
mbed_official 579:53297373a894 713 #define PORT_PA17E_TCC2_WO1 (1ul << 17)
mbed_official 579:53297373a894 714 #define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
mbed_official 579:53297373a894 715 #define MUX_PA01E_TCC2_WO1 4L
mbed_official 579:53297373a894 716 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
mbed_official 579:53297373a894 717 #define PORT_PA01E_TCC2_WO1 (1ul << 1)
mbed_official 579:53297373a894 718 /* ========== PORT definition for TC3 peripheral ========== */
mbed_official 579:53297373a894 719 #define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
mbed_official 579:53297373a894 720 #define MUX_PA18E_TC3_WO0 4L
mbed_official 579:53297373a894 721 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
mbed_official 579:53297373a894 722 #define PORT_PA18E_TC3_WO0 (1ul << 18)
mbed_official 579:53297373a894 723 #define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
mbed_official 579:53297373a894 724 #define MUX_PA14E_TC3_WO0 4L
mbed_official 579:53297373a894 725 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
mbed_official 579:53297373a894 726 #define PORT_PA14E_TC3_WO0 (1ul << 14)
mbed_official 579:53297373a894 727 #define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
mbed_official 579:53297373a894 728 #define MUX_PA19E_TC3_WO1 4L
mbed_official 579:53297373a894 729 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
mbed_official 579:53297373a894 730 #define PORT_PA19E_TC3_WO1 (1ul << 19)
mbed_official 579:53297373a894 731 #define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
mbed_official 579:53297373a894 732 #define MUX_PA15E_TC3_WO1 4L
mbed_official 579:53297373a894 733 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
mbed_official 579:53297373a894 734 #define PORT_PA15E_TC3_WO1 (1ul << 15)
mbed_official 579:53297373a894 735 /* ========== PORT definition for TC4 peripheral ========== */
mbed_official 579:53297373a894 736 #define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
mbed_official 579:53297373a894 737 #define MUX_PA22E_TC4_WO0 4L
mbed_official 579:53297373a894 738 #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
mbed_official 579:53297373a894 739 #define PORT_PA22E_TC4_WO0 (1ul << 22)
mbed_official 579:53297373a894 740 #define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
mbed_official 579:53297373a894 741 #define MUX_PB08E_TC4_WO0 4L
mbed_official 579:53297373a894 742 #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
mbed_official 579:53297373a894 743 #define PORT_PB08E_TC4_WO0 (1ul << 8)
mbed_official 579:53297373a894 744 #define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
mbed_official 579:53297373a894 745 #define MUX_PA23E_TC4_WO1 4L
mbed_official 579:53297373a894 746 #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
mbed_official 579:53297373a894 747 #define PORT_PA23E_TC4_WO1 (1ul << 23)
mbed_official 579:53297373a894 748 #define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
mbed_official 579:53297373a894 749 #define MUX_PB09E_TC4_WO1 4L
mbed_official 579:53297373a894 750 #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
mbed_official 579:53297373a894 751 #define PORT_PB09E_TC4_WO1 (1ul << 9)
mbed_official 579:53297373a894 752 /* ========== PORT definition for TC5 peripheral ========== */
mbed_official 579:53297373a894 753 #define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
mbed_official 579:53297373a894 754 #define MUX_PA24E_TC5_WO0 4L
mbed_official 579:53297373a894 755 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
mbed_official 579:53297373a894 756 #define PORT_PA24E_TC5_WO0 (1ul << 24)
mbed_official 579:53297373a894 757 #define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */
mbed_official 579:53297373a894 758 #define MUX_PB14E_TC5_WO0 4L
mbed_official 579:53297373a894 759 #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
mbed_official 579:53297373a894 760 #define PORT_PB14E_TC5_WO0 (1ul << 14)
mbed_official 579:53297373a894 761 #define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
mbed_official 579:53297373a894 762 #define MUX_PA25E_TC5_WO1 4L
mbed_official 579:53297373a894 763 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
mbed_official 579:53297373a894 764 #define PORT_PA25E_TC5_WO1 (1ul << 25)
mbed_official 579:53297373a894 765 #define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */
mbed_official 579:53297373a894 766 #define MUX_PB15E_TC5_WO1 4L
mbed_official 579:53297373a894 767 #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
mbed_official 579:53297373a894 768 #define PORT_PB15E_TC5_WO1 (1ul << 15)
mbed_official 579:53297373a894 769 /* ========== PORT definition for ADC peripheral ========== */
mbed_official 579:53297373a894 770 #define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
mbed_official 579:53297373a894 771 #define MUX_PB08B_ADC_AIN2 1L
mbed_official 579:53297373a894 772 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
mbed_official 579:53297373a894 773 #define PORT_PB08B_ADC_AIN2 (1ul << 8)
mbed_official 579:53297373a894 774 #define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
mbed_official 579:53297373a894 775 #define MUX_PB09B_ADC_AIN3 1L
mbed_official 579:53297373a894 776 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
mbed_official 579:53297373a894 777 #define PORT_PB09B_ADC_AIN3 (1ul << 9)
mbed_official 579:53297373a894 778 #define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
mbed_official 579:53297373a894 779 #define MUX_PA04B_ADC_AIN4 1L
mbed_official 579:53297373a894 780 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
mbed_official 579:53297373a894 781 #define PORT_PA04B_ADC_AIN4 (1ul << 4)
mbed_official 579:53297373a894 782 #define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
mbed_official 579:53297373a894 783 #define MUX_PA05B_ADC_AIN5 1L
mbed_official 579:53297373a894 784 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
mbed_official 579:53297373a894 785 #define PORT_PA05B_ADC_AIN5 (1ul << 5)
mbed_official 579:53297373a894 786 #define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
mbed_official 579:53297373a894 787 #define MUX_PA06B_ADC_AIN6 1L
mbed_official 579:53297373a894 788 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
mbed_official 579:53297373a894 789 #define PORT_PA06B_ADC_AIN6 (1ul << 6)
mbed_official 579:53297373a894 790 #define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
mbed_official 579:53297373a894 791 #define MUX_PA07B_ADC_AIN7 1L
mbed_official 579:53297373a894 792 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
mbed_official 579:53297373a894 793 #define PORT_PA07B_ADC_AIN7 (1ul << 7)
mbed_official 579:53297373a894 794 #define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */
mbed_official 579:53297373a894 795 #define MUX_PB00B_ADC_AIN8 1L
mbed_official 579:53297373a894 796 #define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
mbed_official 579:53297373a894 797 #define PORT_PB00B_ADC_AIN8 (1ul << 0)
mbed_official 579:53297373a894 798 #define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
mbed_official 579:53297373a894 799 #define MUX_PB02B_ADC_AIN10 1L
mbed_official 579:53297373a894 800 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
mbed_official 579:53297373a894 801 #define PORT_PB02B_ADC_AIN10 (1ul << 2)
mbed_official 579:53297373a894 802 #define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
mbed_official 579:53297373a894 803 #define MUX_PB03B_ADC_AIN11 1L
mbed_official 579:53297373a894 804 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
mbed_official 579:53297373a894 805 #define PORT_PB03B_ADC_AIN11 (1ul << 3)
mbed_official 579:53297373a894 806 #define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
mbed_official 579:53297373a894 807 #define MUX_PA08B_ADC_AIN16 1L
mbed_official 579:53297373a894 808 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
mbed_official 579:53297373a894 809 #define PORT_PA08B_ADC_AIN16 (1ul << 8)
mbed_official 579:53297373a894 810 #define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
mbed_official 579:53297373a894 811 #define MUX_PA09B_ADC_AIN17 1L
mbed_official 579:53297373a894 812 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
mbed_official 579:53297373a894 813 #define PORT_PA09B_ADC_AIN17 (1ul << 9)
mbed_official 579:53297373a894 814 #define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
mbed_official 579:53297373a894 815 #define MUX_PA10B_ADC_AIN18 1L
mbed_official 579:53297373a894 816 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
mbed_official 579:53297373a894 817 #define PORT_PA10B_ADC_AIN18 (1ul << 10)
mbed_official 579:53297373a894 818 #define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
mbed_official 579:53297373a894 819 #define MUX_PA11B_ADC_AIN19 1L
mbed_official 579:53297373a894 820 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
mbed_official 579:53297373a894 821 #define PORT_PA11B_ADC_AIN19 (1ul << 11)
mbed_official 579:53297373a894 822 #define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
mbed_official 579:53297373a894 823 #define MUX_PA04B_ADC_VREFP 1L
mbed_official 579:53297373a894 824 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
mbed_official 579:53297373a894 825 #define PORT_PA04B_ADC_VREFP (1ul << 4)
mbed_official 579:53297373a894 826 /* ========== PORT definition for AC peripheral ========== */
mbed_official 579:53297373a894 827 #define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
mbed_official 579:53297373a894 828 #define MUX_PA04B_AC_AIN0 1L
mbed_official 579:53297373a894 829 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
mbed_official 579:53297373a894 830 #define PORT_PA04B_AC_AIN0 (1ul << 4)
mbed_official 579:53297373a894 831 #define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
mbed_official 579:53297373a894 832 #define MUX_PA05B_AC_AIN1 1L
mbed_official 579:53297373a894 833 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
mbed_official 579:53297373a894 834 #define PORT_PA05B_AC_AIN1 (1ul << 5)
mbed_official 579:53297373a894 835 #define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
mbed_official 579:53297373a894 836 #define MUX_PA06B_AC_AIN2 1L
mbed_official 579:53297373a894 837 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
mbed_official 579:53297373a894 838 #define PORT_PA06B_AC_AIN2 (1ul << 6)
mbed_official 579:53297373a894 839 #define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
mbed_official 579:53297373a894 840 #define MUX_PA07B_AC_AIN3 1L
mbed_official 579:53297373a894 841 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
mbed_official 579:53297373a894 842 #define PORT_PA07B_AC_AIN3 (1ul << 7)
mbed_official 579:53297373a894 843 #define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
mbed_official 579:53297373a894 844 #define MUX_PA12H_AC_CMP0 7L
mbed_official 579:53297373a894 845 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
mbed_official 579:53297373a894 846 #define PORT_PA12H_AC_CMP0 (1ul << 12)
mbed_official 579:53297373a894 847 #define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
mbed_official 579:53297373a894 848 #define MUX_PA18H_AC_CMP0 7L
mbed_official 579:53297373a894 849 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
mbed_official 579:53297373a894 850 #define PORT_PA18H_AC_CMP0 (1ul << 18)
mbed_official 579:53297373a894 851 #define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
mbed_official 579:53297373a894 852 #define MUX_PA13H_AC_CMP1 7L
mbed_official 579:53297373a894 853 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
mbed_official 579:53297373a894 854 #define PORT_PA13H_AC_CMP1 (1ul << 13)
mbed_official 579:53297373a894 855 #define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
mbed_official 579:53297373a894 856 #define MUX_PA19H_AC_CMP1 7L
mbed_official 579:53297373a894 857 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
mbed_official 579:53297373a894 858 #define PORT_PA19H_AC_CMP1 (1ul << 19)
mbed_official 579:53297373a894 859 /* ========== PORT definition for RFCTRL peripheral ========== */
mbed_official 579:53297373a894 860 #define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */
mbed_official 579:53297373a894 861 #define MUX_PA08F_RFCTRL_FECTRL0 5L
mbed_official 579:53297373a894 862 #define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0)
mbed_official 579:53297373a894 863 #define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8)
mbed_official 579:53297373a894 864 #define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */
mbed_official 579:53297373a894 865 #define MUX_PA09F_RFCTRL_FECTRL1 5L
mbed_official 579:53297373a894 866 #define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1)
mbed_official 579:53297373a894 867 #define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9)
mbed_official 579:53297373a894 868 #define PIN_PA12F_RFCTRL_FECTRL2 12L /**< \brief RFCTRL signal: FECTRL2 on PA12 mux F */
mbed_official 579:53297373a894 869 #define MUX_PA12F_RFCTRL_FECTRL2 5L
mbed_official 579:53297373a894 870 #define PINMUX_PA12F_RFCTRL_FECTRL2 ((PIN_PA12F_RFCTRL_FECTRL2 << 16) | MUX_PA12F_RFCTRL_FECTRL2)
mbed_official 579:53297373a894 871 #define PORT_PA12F_RFCTRL_FECTRL2 (1ul << 12)
mbed_official 579:53297373a894 872 #define PIN_PA13F_RFCTRL_FECTRL3 13L /**< \brief RFCTRL signal: FECTRL3 on PA13 mux F */
mbed_official 579:53297373a894 873 #define MUX_PA13F_RFCTRL_FECTRL3 5L
mbed_official 579:53297373a894 874 #define PINMUX_PA13F_RFCTRL_FECTRL3 ((PIN_PA13F_RFCTRL_FECTRL3 << 16) | MUX_PA13F_RFCTRL_FECTRL3)
mbed_official 579:53297373a894 875 #define PORT_PA13F_RFCTRL_FECTRL3 (1ul << 13)
mbed_official 579:53297373a894 876 #define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */
mbed_official 579:53297373a894 877 #define MUX_PA14F_RFCTRL_FECTRL4 5L
mbed_official 579:53297373a894 878 #define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4)
mbed_official 579:53297373a894 879 #define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14)
mbed_official 579:53297373a894 880 #define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */
mbed_official 579:53297373a894 881 #define MUX_PA15F_RFCTRL_FECTRL5 5L
mbed_official 579:53297373a894 882 #define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5)
mbed_official 579:53297373a894 883 #define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15)
mbed_official 579:53297373a894 884
mbed_official 579:53297373a894 885 #endif /* _SAMR21G18A_PIO_ */