Lancaster University / mbed-src

Lancaster University's (short term!) clone of mbed-src for micro:bit. This is a copy of the github branch https://github.com/lancaster-university/mbed-classic

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_port.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_PORT_COMPONENT_
mbed_official 579:53297373a894 2 #define _SAMD21_PORT_COMPONENT_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========================================================================== */
mbed_official 579:53297373a894 5 /** SOFTWARE API DEFINITION FOR PORT */
mbed_official 579:53297373a894 6 /* ========================================================================== */
mbed_official 579:53297373a894 7 /** \addtogroup SAMD21_PORT Port Module */
mbed_official 579:53297373a894 8 /*@{*/
mbed_official 579:53297373a894 9
mbed_official 579:53297373a894 10 #define PORT_U2210
mbed_official 579:53297373a894 11 #define REV_PORT 0x100
mbed_official 579:53297373a894 12
mbed_official 579:53297373a894 13 /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
mbed_official 579:53297373a894 14 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 15 typedef union {
mbed_official 579:53297373a894 16 struct {
mbed_official 579:53297373a894 17 uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
mbed_official 579:53297373a894 18 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 19 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 20 } PORT_DIR_Type;
mbed_official 579:53297373a894 21 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 22
mbed_official 579:53297373a894 23 #define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
mbed_official 579:53297373a894 24 #define PORT_DIR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */
mbed_official 579:53297373a894 25
mbed_official 579:53297373a894 26 #define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
mbed_official 579:53297373a894 27 #define PORT_DIR_DIR_Msk (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
mbed_official 579:53297373a894 28 #define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
mbed_official 579:53297373a894 29 #define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
mbed_official 579:53297373a894 30
mbed_official 579:53297373a894 31 /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
mbed_official 579:53297373a894 32 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 33 typedef union {
mbed_official 579:53297373a894 34 struct {
mbed_official 579:53297373a894 35 uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
mbed_official 579:53297373a894 36 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 37 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 38 } PORT_DIRCLR_Type;
mbed_official 579:53297373a894 39 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 40
mbed_official 579:53297373a894 41 #define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
mbed_official 579:53297373a894 42 #define PORT_DIRCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
mbed_official 579:53297373a894 43
mbed_official 579:53297373a894 44 #define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
mbed_official 579:53297373a894 45 #define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
mbed_official 579:53297373a894 46 #define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
mbed_official 579:53297373a894 47 #define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
mbed_official 579:53297373a894 48
mbed_official 579:53297373a894 49 /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
mbed_official 579:53297373a894 50 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 51 typedef union {
mbed_official 579:53297373a894 52 struct {
mbed_official 579:53297373a894 53 uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
mbed_official 579:53297373a894 54 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 55 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 56 } PORT_DIRSET_Type;
mbed_official 579:53297373a894 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 58
mbed_official 579:53297373a894 59 #define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
mbed_official 579:53297373a894 60 #define PORT_DIRSET_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
mbed_official 579:53297373a894 61
mbed_official 579:53297373a894 62 #define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
mbed_official 579:53297373a894 63 #define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
mbed_official 579:53297373a894 64 #define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
mbed_official 579:53297373a894 65 #define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
mbed_official 579:53297373a894 66
mbed_official 579:53297373a894 67 /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
mbed_official 579:53297373a894 68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 69 typedef union {
mbed_official 579:53297373a894 70 struct {
mbed_official 579:53297373a894 71 uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
mbed_official 579:53297373a894 72 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 73 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 74 } PORT_DIRTGL_Type;
mbed_official 579:53297373a894 75 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 76
mbed_official 579:53297373a894 77 #define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
mbed_official 579:53297373a894 78 #define PORT_DIRTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
mbed_official 579:53297373a894 79
mbed_official 579:53297373a894 80 #define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
mbed_official 579:53297373a894 81 #define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
mbed_official 579:53297373a894 82 #define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
mbed_official 579:53297373a894 83 #define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
mbed_official 579:53297373a894 84
mbed_official 579:53297373a894 85 /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
mbed_official 579:53297373a894 86 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 87 typedef union {
mbed_official 579:53297373a894 88 struct {
mbed_official 579:53297373a894 89 uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
mbed_official 579:53297373a894 90 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 91 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 92 } PORT_OUT_Type;
mbed_official 579:53297373a894 93 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 94
mbed_official 579:53297373a894 95 #define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
mbed_official 579:53297373a894 96 #define PORT_OUT_RESETVALUE 0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */
mbed_official 579:53297373a894 97
mbed_official 579:53297373a894 98 #define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
mbed_official 579:53297373a894 99 #define PORT_OUT_OUT_Msk (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
mbed_official 579:53297373a894 100 #define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
mbed_official 579:53297373a894 101 #define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
mbed_official 579:53297373a894 102
mbed_official 579:53297373a894 103 /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
mbed_official 579:53297373a894 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 105 typedef union {
mbed_official 579:53297373a894 106 struct {
mbed_official 579:53297373a894 107 uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
mbed_official 579:53297373a894 108 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 109 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 110 } PORT_OUTCLR_Type;
mbed_official 579:53297373a894 111 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 112
mbed_official 579:53297373a894 113 #define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
mbed_official 579:53297373a894 114 #define PORT_OUTCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
mbed_official 579:53297373a894 115
mbed_official 579:53297373a894 116 #define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
mbed_official 579:53297373a894 117 #define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
mbed_official 579:53297373a894 118 #define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
mbed_official 579:53297373a894 119 #define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
mbed_official 579:53297373a894 120
mbed_official 579:53297373a894 121 /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
mbed_official 579:53297373a894 122 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 123 typedef union {
mbed_official 579:53297373a894 124 struct {
mbed_official 579:53297373a894 125 uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
mbed_official 579:53297373a894 126 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 127 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 128 } PORT_OUTSET_Type;
mbed_official 579:53297373a894 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 130
mbed_official 579:53297373a894 131 #define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
mbed_official 579:53297373a894 132 #define PORT_OUTSET_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
mbed_official 579:53297373a894 133
mbed_official 579:53297373a894 134 #define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
mbed_official 579:53297373a894 135 #define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
mbed_official 579:53297373a894 136 #define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
mbed_official 579:53297373a894 137 #define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
mbed_official 579:53297373a894 138
mbed_official 579:53297373a894 139 /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
mbed_official 579:53297373a894 140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 141 typedef union {
mbed_official 579:53297373a894 142 struct {
mbed_official 579:53297373a894 143 uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
mbed_official 579:53297373a894 144 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 145 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 146 } PORT_OUTTGL_Type;
mbed_official 579:53297373a894 147 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 148
mbed_official 579:53297373a894 149 #define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
mbed_official 579:53297373a894 150 #define PORT_OUTTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
mbed_official 579:53297373a894 151
mbed_official 579:53297373a894 152 #define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
mbed_official 579:53297373a894 153 #define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
mbed_official 579:53297373a894 154 #define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
mbed_official 579:53297373a894 155 #define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
mbed_official 579:53297373a894 156
mbed_official 579:53297373a894 157 /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
mbed_official 579:53297373a894 158 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 159 typedef union {
mbed_official 579:53297373a894 160 struct {
mbed_official 579:53297373a894 161 uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
mbed_official 579:53297373a894 162 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 163 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 164 } PORT_IN_Type;
mbed_official 579:53297373a894 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 166
mbed_official 579:53297373a894 167 #define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
mbed_official 579:53297373a894 168 #define PORT_IN_RESETVALUE 0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */
mbed_official 579:53297373a894 169
mbed_official 579:53297373a894 170 #define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
mbed_official 579:53297373a894 171 #define PORT_IN_IN_Msk (0xFFFFFFFFul << PORT_IN_IN_Pos)
mbed_official 579:53297373a894 172 #define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
mbed_official 579:53297373a894 173 #define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
mbed_official 579:53297373a894 174
mbed_official 579:53297373a894 175 /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
mbed_official 579:53297373a894 176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 177 typedef union {
mbed_official 579:53297373a894 178 struct {
mbed_official 579:53297373a894 179 uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
mbed_official 579:53297373a894 180 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 181 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 182 } PORT_CTRL_Type;
mbed_official 579:53297373a894 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 184
mbed_official 579:53297373a894 185 #define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
mbed_official 579:53297373a894 186 #define PORT_CTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */
mbed_official 579:53297373a894 187
mbed_official 579:53297373a894 188 #define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
mbed_official 579:53297373a894 189 #define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
mbed_official 579:53297373a894 190 #define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
mbed_official 579:53297373a894 191 #define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
mbed_official 579:53297373a894 192
mbed_official 579:53297373a894 193 /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
mbed_official 579:53297373a894 194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 195 typedef union {
mbed_official 579:53297373a894 196 struct {
mbed_official 579:53297373a894 197 uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
mbed_official 579:53297373a894 198 uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
mbed_official 579:53297373a894 199 uint32_t INEN:1; /*!< bit: 17 Input Enable */
mbed_official 579:53297373a894 200 uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
mbed_official 579:53297373a894 201 uint32_t :3; /*!< bit: 19..21 Reserved */
mbed_official 579:53297373a894 202 uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
mbed_official 579:53297373a894 203 uint32_t :1; /*!< bit: 23 Reserved */
mbed_official 579:53297373a894 204 uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
mbed_official 579:53297373a894 205 uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
mbed_official 579:53297373a894 206 uint32_t :1; /*!< bit: 29 Reserved */
mbed_official 579:53297373a894 207 uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
mbed_official 579:53297373a894 208 uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
mbed_official 579:53297373a894 209 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 210 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 211 } PORT_WRCONFIG_Type;
mbed_official 579:53297373a894 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 213
mbed_official 579:53297373a894 214 #define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
mbed_official 579:53297373a894 215 #define PORT_WRCONFIG_RESETVALUE 0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
mbed_official 579:53297373a894 216
mbed_official 579:53297373a894 217 #define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
mbed_official 579:53297373a894 218 #define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
mbed_official 579:53297373a894 219 #define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
mbed_official 579:53297373a894 220 #define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
mbed_official 579:53297373a894 221 #define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
mbed_official 579:53297373a894 222 #define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
mbed_official 579:53297373a894 223 #define PORT_WRCONFIG_INEN (0x1ul << PORT_WRCONFIG_INEN_Pos)
mbed_official 579:53297373a894 224 #define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
mbed_official 579:53297373a894 225 #define PORT_WRCONFIG_PULLEN (0x1ul << PORT_WRCONFIG_PULLEN_Pos)
mbed_official 579:53297373a894 226 #define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
mbed_official 579:53297373a894 227 #define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
mbed_official 579:53297373a894 228 #define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
mbed_official 579:53297373a894 229 #define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos)
mbed_official 579:53297373a894 230 #define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
mbed_official 579:53297373a894 231 #define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
mbed_official 579:53297373a894 232 #define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
mbed_official 579:53297373a894 233 #define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
mbed_official 579:53297373a894 234 #define PORT_WRCONFIG_WRPINCFG (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos)
mbed_official 579:53297373a894 235 #define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
mbed_official 579:53297373a894 236 #define PORT_WRCONFIG_HWSEL (0x1ul << PORT_WRCONFIG_HWSEL_Pos)
mbed_official 579:53297373a894 237 #define PORT_WRCONFIG_MASK 0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */
mbed_official 579:53297373a894 238
mbed_official 579:53297373a894 239 /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
mbed_official 579:53297373a894 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 241 typedef union {
mbed_official 579:53297373a894 242 struct {
mbed_official 579:53297373a894 243 uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
mbed_official 579:53297373a894 244 uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
mbed_official 579:53297373a894 245 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 246 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 247 } PORT_PMUX_Type;
mbed_official 579:53297373a894 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 249
mbed_official 579:53297373a894 250 #define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
mbed_official 579:53297373a894 251 #define PORT_PMUX_RESETVALUE 0x00ul /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
mbed_official 579:53297373a894 252
mbed_official 579:53297373a894 253 #define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
mbed_official 579:53297373a894 254 #define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 255 #define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
mbed_official 579:53297373a894 256 #define PORT_PMUX_PMUXE_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
mbed_official 579:53297373a894 257 #define PORT_PMUX_PMUXE_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
mbed_official 579:53297373a894 258 #define PORT_PMUX_PMUXE_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
mbed_official 579:53297373a894 259 #define PORT_PMUX_PMUXE_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */
mbed_official 579:53297373a894 260 #define PORT_PMUX_PMUXE_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */
mbed_official 579:53297373a894 261 #define PORT_PMUX_PMUXE_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */
mbed_official 579:53297373a894 262 #define PORT_PMUX_PMUXE_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */
mbed_official 579:53297373a894 263 #define PORT_PMUX_PMUXE_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */
mbed_official 579:53297373a894 264 #define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 265 #define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 266 #define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 267 #define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 268 #define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 269 #define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 270 #define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 271 #define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
mbed_official 579:53297373a894 272 #define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
mbed_official 579:53297373a894 273 #define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 274 #define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
mbed_official 579:53297373a894 275 #define PORT_PMUX_PMUXO_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
mbed_official 579:53297373a894 276 #define PORT_PMUX_PMUXO_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
mbed_official 579:53297373a894 277 #define PORT_PMUX_PMUXO_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
mbed_official 579:53297373a894 278 #define PORT_PMUX_PMUXO_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */
mbed_official 579:53297373a894 279 #define PORT_PMUX_PMUXO_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */
mbed_official 579:53297373a894 280 #define PORT_PMUX_PMUXO_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */
mbed_official 579:53297373a894 281 #define PORT_PMUX_PMUXO_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */
mbed_official 579:53297373a894 282 #define PORT_PMUX_PMUXO_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */
mbed_official 579:53297373a894 283 #define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 284 #define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 285 #define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 286 #define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 287 #define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 288 #define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 289 #define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 290 #define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
mbed_official 579:53297373a894 291 #define PORT_PMUX_MASK 0xFFul /**< \brief (PORT_PMUX) MASK Register */
mbed_official 579:53297373a894 292
mbed_official 579:53297373a894 293 /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
mbed_official 579:53297373a894 294 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 295 typedef union {
mbed_official 579:53297373a894 296 struct {
mbed_official 579:53297373a894 297 uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
mbed_official 579:53297373a894 298 uint8_t INEN:1; /*!< bit: 1 Input Enable */
mbed_official 579:53297373a894 299 uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
mbed_official 579:53297373a894 300 uint8_t :3; /*!< bit: 3.. 5 Reserved */
mbed_official 579:53297373a894 301 uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
mbed_official 579:53297373a894 302 uint8_t :1; /*!< bit: 7 Reserved */
mbed_official 579:53297373a894 303 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 304 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 305 } PORT_PINCFG_Type;
mbed_official 579:53297373a894 306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 307
mbed_official 579:53297373a894 308 #define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
mbed_official 579:53297373a894 309 #define PORT_PINCFG_RESETVALUE 0x00ul /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
mbed_official 579:53297373a894 310
mbed_official 579:53297373a894 311 #define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
mbed_official 579:53297373a894 312 #define PORT_PINCFG_PMUXEN (0x1ul << PORT_PINCFG_PMUXEN_Pos)
mbed_official 579:53297373a894 313 #define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
mbed_official 579:53297373a894 314 #define PORT_PINCFG_INEN (0x1ul << PORT_PINCFG_INEN_Pos)
mbed_official 579:53297373a894 315 #define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
mbed_official 579:53297373a894 316 #define PORT_PINCFG_PULLEN (0x1ul << PORT_PINCFG_PULLEN_Pos)
mbed_official 579:53297373a894 317 #define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
mbed_official 579:53297373a894 318 #define PORT_PINCFG_DRVSTR (0x1ul << PORT_PINCFG_DRVSTR_Pos)
mbed_official 579:53297373a894 319 #define PORT_PINCFG_MASK 0x47ul /**< \brief (PORT_PINCFG) MASK Register */
mbed_official 579:53297373a894 320
mbed_official 579:53297373a894 321 /** \brief PortGroup hardware registers */
mbed_official 579:53297373a894 322 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 323 typedef struct {
mbed_official 579:53297373a894 324 __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
mbed_official 579:53297373a894 325 __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
mbed_official 579:53297373a894 326 __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
mbed_official 579:53297373a894 327 __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
mbed_official 579:53297373a894 328 __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
mbed_official 579:53297373a894 329 __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
mbed_official 579:53297373a894 330 __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
mbed_official 579:53297373a894 331 __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
mbed_official 579:53297373a894 332 __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
mbed_official 579:53297373a894 333 __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
mbed_official 579:53297373a894 334 __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
mbed_official 579:53297373a894 335 RoReg8 Reserved1[0x4];
mbed_official 579:53297373a894 336 __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
mbed_official 579:53297373a894 337 __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
mbed_official 579:53297373a894 338 RoReg8 Reserved2[0x20];
mbed_official 579:53297373a894 339 } PortGroup;
mbed_official 579:53297373a894 340 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 341
mbed_official 579:53297373a894 342 /** \brief PORT hardware registers */
mbed_official 579:53297373a894 343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 344 typedef struct {
mbed_official 579:53297373a894 345 PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
mbed_official 579:53297373a894 346 } Port;
mbed_official 579:53297373a894 347 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 348 #define SECTION_PORT_IOBUS
mbed_official 579:53297373a894 349
mbed_official 579:53297373a894 350 /*@}*/
mbed_official 579:53297373a894 351
mbed_official 579:53297373a894 352 #endif /* _SAMD21_PORT_COMPONENT_ */