Lancaster University / mbed-src

Lancaster University's (short term!) clone of mbed-src for micro:bit. This is a copy of the github branch https://github.com/lancaster-university/mbed-classic

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.c@585:a1ed5b41f74f, 2015-07-08 (annotated)

Committer:
mbed_official
Date:
Wed Jul 08 14:45:08 2015 +0100
Revision:
585:a1ed5b41f74f
Synchronized with git revision 7a2b57896e0263b82f31ddc5a0ad2443615db184



Full URL: https://github.com/mbedmicro/mbed/commit/7a2b57896e0263b82f31ddc5a0ad2443615db184/



Add rtc_api.c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 585:a1ed5b41f74f 1 /*
mbed_official 585:a1ed5b41f74f 2 ** ###################################################################
mbed_official 585:a1ed5b41f74f 3 ** Processors: MKL26Z128CAL4
mbed_official 585:a1ed5b41f74f 4 ** MKL26Z128VFM4
mbed_official 585:a1ed5b41f74f 5 ** MKL26Z64VFM4
mbed_official 585:a1ed5b41f74f 6 ** MKL26Z32VM4
mbed_official 585:a1ed5b41f74f 7 ** MKL26Z128VFT4
mbed_official 585:a1ed5b41f74f 8 ** MKL26Z64VFT4
mbed_official 585:a1ed5b41f74f 9 ** MKL26Z32VFT4
mbed_official 585:a1ed5b41f74f 10 ** MKL26Z128VLH4
mbed_official 585:a1ed5b41f74f 11 ** MKL26Z64VLH4
mbed_official 585:a1ed5b41f74f 12 ** MKL26Z32VLH4
mbed_official 585:a1ed5b41f74f 13 ** MKL26Z256VLH4
mbed_official 585:a1ed5b41f74f 14 ** MKL26Z256VLL4
mbed_official 585:a1ed5b41f74f 15 ** MKL26Z128VLL4
mbed_official 585:a1ed5b41f74f 16 ** MKL26Z256VMC4
mbed_official 585:a1ed5b41f74f 17 ** MKL26Z128VMC4
mbed_official 585:a1ed5b41f74f 18 ** MKL26Z256VMP4
mbed_official 585:a1ed5b41f74f 19 **
mbed_official 585:a1ed5b41f74f 20 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 585:a1ed5b41f74f 21 ** Freescale C/C++ for Embedded ARM
mbed_official 585:a1ed5b41f74f 22 ** GNU C Compiler
mbed_official 585:a1ed5b41f74f 23 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 585:a1ed5b41f74f 24 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 585:a1ed5b41f74f 25 **
mbed_official 585:a1ed5b41f74f 26 ** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
mbed_official 585:a1ed5b41f74f 27 ** KL26P121M48SF4RM, Rev.2, Dec 2012
mbed_official 585:a1ed5b41f74f 28 **
mbed_official 585:a1ed5b41f74f 29 ** Version: rev. 1.7, 2015-01-13
mbed_official 585:a1ed5b41f74f 30 ** Build: b150129
mbed_official 585:a1ed5b41f74f 31 **
mbed_official 585:a1ed5b41f74f 32 ** Abstract:
mbed_official 585:a1ed5b41f74f 33 ** Provides a system configuration function and a global variable that
mbed_official 585:a1ed5b41f74f 34 ** contains the system frequency. It configures the device and initializes
mbed_official 585:a1ed5b41f74f 35 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 585:a1ed5b41f74f 36 **
mbed_official 585:a1ed5b41f74f 37 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
mbed_official 585:a1ed5b41f74f 38 ** All rights reserved.
mbed_official 585:a1ed5b41f74f 39 **
mbed_official 585:a1ed5b41f74f 40 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 585:a1ed5b41f74f 41 ** are permitted provided that the following conditions are met:
mbed_official 585:a1ed5b41f74f 42 **
mbed_official 585:a1ed5b41f74f 43 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 585:a1ed5b41f74f 44 ** of conditions and the following disclaimer.
mbed_official 585:a1ed5b41f74f 45 **
mbed_official 585:a1ed5b41f74f 46 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 585:a1ed5b41f74f 47 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 585:a1ed5b41f74f 48 ** other materials provided with the distribution.
mbed_official 585:a1ed5b41f74f 49 **
mbed_official 585:a1ed5b41f74f 50 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 585:a1ed5b41f74f 51 ** contributors may be used to endorse or promote products derived from this
mbed_official 585:a1ed5b41f74f 52 ** software without specific prior written permission.
mbed_official 585:a1ed5b41f74f 53 **
mbed_official 585:a1ed5b41f74f 54 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 585:a1ed5b41f74f 55 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 585:a1ed5b41f74f 56 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 585:a1ed5b41f74f 57 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 585:a1ed5b41f74f 58 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 585:a1ed5b41f74f 59 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 585:a1ed5b41f74f 60 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 585:a1ed5b41f74f 61 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 585:a1ed5b41f74f 62 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 585:a1ed5b41f74f 63 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 585:a1ed5b41f74f 64 **
mbed_official 585:a1ed5b41f74f 65 ** http: www.freescale.com
mbed_official 585:a1ed5b41f74f 66 ** mail: support@freescale.com
mbed_official 585:a1ed5b41f74f 67 **
mbed_official 585:a1ed5b41f74f 68 ** Revisions:
mbed_official 585:a1ed5b41f74f 69 ** - rev. 1.0 (2012-12-12)
mbed_official 585:a1ed5b41f74f 70 ** Initial version.
mbed_official 585:a1ed5b41f74f 71 ** - rev. 1.1 (2013-04-05)
mbed_official 585:a1ed5b41f74f 72 ** Changed start of doxygen comment.
mbed_official 585:a1ed5b41f74f 73 ** - rev. 1.2 (2013-04-12)
mbed_official 585:a1ed5b41f74f 74 ** SystemInit function fixed for clock configuration 1.
mbed_official 585:a1ed5b41f74f 75 ** Name of the interrupt num. 31 updated to reflect proper function.
mbed_official 585:a1ed5b41f74f 76 ** - rev. 1.3 (2014-05-27)
mbed_official 585:a1ed5b41f74f 77 ** Updated to Kinetis SDK support standard.
mbed_official 585:a1ed5b41f74f 78 ** MCG OSC clock select supported (MCG_C7[OSCSEL]).
mbed_official 585:a1ed5b41f74f 79 ** - rev. 1.4 (2014-07-25)
mbed_official 585:a1ed5b41f74f 80 ** System initialization updated:
mbed_official 585:a1ed5b41f74f 81 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
mbed_official 585:a1ed5b41f74f 82 ** - VLLSx wake-up recovery added.
mbed_official 585:a1ed5b41f74f 83 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
mbed_official 585:a1ed5b41f74f 84 ** - rev. 1.5 (2014-08-28)
mbed_official 585:a1ed5b41f74f 85 ** Update of system files - default clock configuration changed, fix of OSC initialization.
mbed_official 585:a1ed5b41f74f 86 ** Update of startup files - possibility to override DefaultISR added.
mbed_official 585:a1ed5b41f74f 87 ** - rev. 1.6 (2014-10-14)
mbed_official 585:a1ed5b41f74f 88 ** Renamed interrupt vector LPTimer to LPTMR0
mbed_official 585:a1ed5b41f74f 89 ** - rev. 1.7 (2015-01-13)
mbed_official 585:a1ed5b41f74f 90 ** Update of the copyright.
mbed_official 585:a1ed5b41f74f 91 **
mbed_official 585:a1ed5b41f74f 92 ** ###################################################################
mbed_official 585:a1ed5b41f74f 93 */
mbed_official 585:a1ed5b41f74f 94
mbed_official 585:a1ed5b41f74f 95 /*!
mbed_official 585:a1ed5b41f74f 96 * @file MKL26Z4
mbed_official 585:a1ed5b41f74f 97 * @version 1.7
mbed_official 585:a1ed5b41f74f 98 * @date 2015-01-13
mbed_official 585:a1ed5b41f74f 99 * @brief Device specific configuration file for MKL26Z4 (implementation file)
mbed_official 585:a1ed5b41f74f 100 *
mbed_official 585:a1ed5b41f74f 101 * Provides a system configuration function and a global variable that contains
mbed_official 585:a1ed5b41f74f 102 * the system frequency. It configures the device and initializes the oscillator
mbed_official 585:a1ed5b41f74f 103 * (PLL) that is part of the microcontroller device.
mbed_official 585:a1ed5b41f74f 104 */
mbed_official 585:a1ed5b41f74f 105
mbed_official 585:a1ed5b41f74f 106 #include <stdint.h>
mbed_official 585:a1ed5b41f74f 107 #include "MKL26Z4.h"
mbed_official 585:a1ed5b41f74f 108
mbed_official 585:a1ed5b41f74f 109
mbed_official 585:a1ed5b41f74f 110
mbed_official 585:a1ed5b41f74f 111 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 112 -- Core clock
mbed_official 585:a1ed5b41f74f 113 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 114
mbed_official 585:a1ed5b41f74f 115 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 585:a1ed5b41f74f 116
mbed_official 585:a1ed5b41f74f 117 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 118 -- SystemInit()
mbed_official 585:a1ed5b41f74f 119 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 120
mbed_official 585:a1ed5b41f74f 121 void SystemInit (void) {
mbed_official 585:a1ed5b41f74f 122
mbed_official 585:a1ed5b41f74f 123 #if (ACK_ISOLATION)
mbed_official 585:a1ed5b41f74f 124 if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) {
mbed_official 585:a1ed5b41f74f 125 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
mbed_official 585:a1ed5b41f74f 126 }
mbed_official 585:a1ed5b41f74f 127 #endif
mbed_official 585:a1ed5b41f74f 128
mbed_official 585:a1ed5b41f74f 129 /* Watchdog disable */
mbed_official 585:a1ed5b41f74f 130 #if (DISABLE_WDOG)
mbed_official 585:a1ed5b41f74f 131 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
mbed_official 585:a1ed5b41f74f 132 SIM->COPC = (uint32_t)0x00u;
mbed_official 585:a1ed5b41f74f 133 #endif /* (DISABLE_WDOG) */
mbed_official 585:a1ed5b41f74f 134
mbed_official 585:a1ed5b41f74f 135 #ifdef CLOCK_SETUP
mbed_official 585:a1ed5b41f74f 136 /* RTC_CLKIN route */
mbed_official 585:a1ed5b41f74f 137 #if (RTC_CLKIN_USED)
mbed_official 585:a1ed5b41f74f 138 /* SIM_SCGC5: PORTC=1 */
mbed_official 585:a1ed5b41f74f 139 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
mbed_official 585:a1ed5b41f74f 140 /* PORTC_PCR1: ISF=0,MUX=1 */
mbed_official 585:a1ed5b41f74f 141 PORTC->PCR[1] = (uint32_t)((PORTC->PCR[1] & (uint32_t)~(uint32_t)(
mbed_official 585:a1ed5b41f74f 142 PORT_PCR_ISF_MASK |
mbed_official 585:a1ed5b41f74f 143 PORT_PCR_MUX(0x06)
mbed_official 585:a1ed5b41f74f 144 )) | (uint32_t)(
mbed_official 585:a1ed5b41f74f 145 PORT_PCR_MUX(0x01)
mbed_official 585:a1ed5b41f74f 146 ));
mbed_official 585:a1ed5b41f74f 147 #endif /* (RTC_CLKIN_USED) */
mbed_official 585:a1ed5b41f74f 148
mbed_official 585:a1ed5b41f74f 149 /* Wake-up from VLLSx? */
mbed_official 585:a1ed5b41f74f 150 if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
mbed_official 585:a1ed5b41f74f 151 {
mbed_official 585:a1ed5b41f74f 152 /* VLLSx recovery */
mbed_official 585:a1ed5b41f74f 153 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
mbed_official 585:a1ed5b41f74f 154 {
mbed_official 585:a1ed5b41f74f 155 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
mbed_official 585:a1ed5b41f74f 156 }
mbed_official 585:a1ed5b41f74f 157 }
mbed_official 585:a1ed5b41f74f 158
mbed_official 585:a1ed5b41f74f 159 /* Power mode protection initialization */
mbed_official 585:a1ed5b41f74f 160 #ifdef SYSTEM_SMC_PMPROT_VALUE
mbed_official 585:a1ed5b41f74f 161 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
mbed_official 585:a1ed5b41f74f 162 #endif
mbed_official 585:a1ed5b41f74f 163
mbed_official 585:a1ed5b41f74f 164 /* System clock initialization */
mbed_official 585:a1ed5b41f74f 165 /* Internal reference clock trim initialization */
mbed_official 585:a1ed5b41f74f 166 #if defined(SLOW_TRIM_ADDRESS)
mbed_official 585:a1ed5b41f74f 167 if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
mbed_official 585:a1ed5b41f74f 168 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
mbed_official 585:a1ed5b41f74f 169 #endif /* defined(SLOW_TRIM_ADDRESS) */
mbed_official 585:a1ed5b41f74f 170 #if defined(SLOW_FINE_TRIM_ADDRESS)
mbed_official 585:a1ed5b41f74f 171 MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
mbed_official 585:a1ed5b41f74f 172 #endif
mbed_official 585:a1ed5b41f74f 173 #if defined(FAST_TRIM_ADDRESS)
mbed_official 585:a1ed5b41f74f 174 MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
mbed_official 585:a1ed5b41f74f 175 #endif
mbed_official 585:a1ed5b41f74f 176 #if defined(FAST_FINE_TRIM_ADDRESS)
mbed_official 585:a1ed5b41f74f 177 MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
mbed_official 585:a1ed5b41f74f 178 #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
mbed_official 585:a1ed5b41f74f 179 #if defined(SLOW_TRIM_ADDRESS)
mbed_official 585:a1ed5b41f74f 180 }
mbed_official 585:a1ed5b41f74f 181 #endif /* defined(SLOW_TRIM_ADDRESS) */
mbed_official 585:a1ed5b41f74f 182
mbed_official 585:a1ed5b41f74f 183 /* Set system prescalers and clock sources */
mbed_official 585:a1ed5b41f74f 184 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
mbed_official 585:a1ed5b41f74f 185 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
mbed_official 585:a1ed5b41f74f 186 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(
mbed_official 585:a1ed5b41f74f 187 SIM_SOPT2_TPMSRC_MASK |
mbed_official 585:a1ed5b41f74f 188 SIM_SOPT2_UART0SRC_MASK |
mbed_official 585:a1ed5b41f74f 189 SIM_SOPT2_PLLFLLSEL_MASK |
mbed_official 585:a1ed5b41f74f 190 SIM_SOPT2_USBSRC_MASK
mbed_official 585:a1ed5b41f74f 191 ))) | ((SYSTEM_SIM_SOPT2_VALUE) & (
mbed_official 585:a1ed5b41f74f 192 SIM_SOPT2_TPMSRC_MASK |
mbed_official 585:a1ed5b41f74f 193 SIM_SOPT2_UART0SRC_MASK |
mbed_official 585:a1ed5b41f74f 194 SIM_SOPT2_PLLFLLSEL_MASK |
mbed_official 585:a1ed5b41f74f 195 SIM_SOPT2_USBSRC_MASK
mbed_official 585:a1ed5b41f74f 196 )); /* Select TPM, LPUARTs, USB clock sources. */
mbed_official 585:a1ed5b41f74f 197 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
mbed_official 585:a1ed5b41f74f 198 /* Set MCG and OSC */
mbed_official 585:a1ed5b41f74f 199 #if ((((SYSTEM_OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U))
mbed_official 585:a1ed5b41f74f 200 /* SIM_SCGC5: PORTA=1 */
mbed_official 585:a1ed5b41f74f 201 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
mbed_official 585:a1ed5b41f74f 202 /* PORTA_PCR18: ISF=0,MUX=0 */
mbed_official 585:a1ed5b41f74f 203 PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 585:a1ed5b41f74f 204 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
mbed_official 585:a1ed5b41f74f 205 /* PORTA_PCR19: ISF=0,MUX=0 */
mbed_official 585:a1ed5b41f74f 206 PORTA->PCR[19] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 585:a1ed5b41f74f 207 }
mbed_official 585:a1ed5b41f74f 208 #endif
mbed_official 585:a1ed5b41f74f 209 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
mbed_official 585:a1ed5b41f74f 210 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
mbed_official 585:a1ed5b41f74f 211 /* Check that the source of the FLL reference clock is the requested one. */
mbed_official 585:a1ed5b41f74f 212 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
mbed_official 585:a1ed5b41f74f 213 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
mbed_official 585:a1ed5b41f74f 214 }
mbed_official 585:a1ed5b41f74f 215 } else {
mbed_official 585:a1ed5b41f74f 216 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
mbed_official 585:a1ed5b41f74f 217 }
mbed_official 585:a1ed5b41f74f 218 }
mbed_official 585:a1ed5b41f74f 219 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
mbed_official 585:a1ed5b41f74f 220 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
mbed_official 585:a1ed5b41f74f 221 OSC0->CR = SYSTEM_OSC0_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
mbed_official 585:a1ed5b41f74f 222
mbed_official 585:a1ed5b41f74f 223 #else /* MCG_MODE */
mbed_official 585:a1ed5b41f74f 224 /* Set MCG and OSC */
mbed_official 585:a1ed5b41f74f 225 /* SIM_SCGC5: PORTA=1 */
mbed_official 585:a1ed5b41f74f 226 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
mbed_official 585:a1ed5b41f74f 227 /* PORTA_PCR18: ISF=0,MUX=0 */
mbed_official 585:a1ed5b41f74f 228 PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 585:a1ed5b41f74f 229 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
mbed_official 585:a1ed5b41f74f 230 /* PORTA_PCR19: ISF=0,MUX=0 */
mbed_official 585:a1ed5b41f74f 231 PORTA->PCR[19] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 585:a1ed5b41f74f 232 }
mbed_official 585:a1ed5b41f74f 233 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
mbed_official 585:a1ed5b41f74f 234 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
mbed_official 585:a1ed5b41f74f 235 OSC0->CR = SYSTEM_OSC0_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
mbed_official 585:a1ed5b41f74f 236 #if (MCG_MODE == MCG_MODE_PEE)
mbed_official 585:a1ed5b41f74f 237 MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
mbed_official 585:a1ed5b41f74f 238 #else
mbed_official 585:a1ed5b41f74f 239 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
mbed_official 585:a1ed5b41f74f 240 #endif
mbed_official 585:a1ed5b41f74f 241 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
mbed_official 585:a1ed5b41f74f 242 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
mbed_official 585:a1ed5b41f74f 243 }
mbed_official 585:a1ed5b41f74f 244 }
mbed_official 585:a1ed5b41f74f 245 /* Check that the source of the FLL reference clock is the requested one. */
mbed_official 585:a1ed5b41f74f 246 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
mbed_official 585:a1ed5b41f74f 247 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
mbed_official 585:a1ed5b41f74f 248 }
mbed_official 585:a1ed5b41f74f 249 } else {
mbed_official 585:a1ed5b41f74f 250 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
mbed_official 585:a1ed5b41f74f 251 }
mbed_official 585:a1ed5b41f74f 252 }
mbed_official 585:a1ed5b41f74f 253 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
mbed_official 585:a1ed5b41f74f 254 #endif /* MCG_MODE */
mbed_official 585:a1ed5b41f74f 255
mbed_official 585:a1ed5b41f74f 256 /* Common for all MCG modes */
mbed_official 585:a1ed5b41f74f 257
mbed_official 585:a1ed5b41f74f 258 /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
mbed_official 585:a1ed5b41f74f 259 MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
mbed_official 585:a1ed5b41f74f 260 MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
mbed_official 585:a1ed5b41f74f 261 if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
mbed_official 585:a1ed5b41f74f 262 MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
mbed_official 585:a1ed5b41f74f 263 }
mbed_official 585:a1ed5b41f74f 264
mbed_official 585:a1ed5b41f74f 265 /* BLPI and BLPE MCG mode specific */
mbed_official 585:a1ed5b41f74f 266 #if ((MCG_MODE == MCG_MODE_BLPI) || (MCG_MODE == MCG_MODE_BLPE))
mbed_official 585:a1ed5b41f74f 267 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
mbed_official 585:a1ed5b41f74f 268 /* PEE and PBE MCG mode specific */
mbed_official 585:a1ed5b41f74f 269 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
mbed_official 585:a1ed5b41f74f 270 MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
mbed_official 585:a1ed5b41f74f 271 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
mbed_official 585:a1ed5b41f74f 272 }
mbed_official 585:a1ed5b41f74f 273 #if (MCG_MODE == MCG_MODE_PEE)
mbed_official 585:a1ed5b41f74f 274 MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
mbed_official 585:a1ed5b41f74f 275 #endif
mbed_official 585:a1ed5b41f74f 276 #endif
mbed_official 585:a1ed5b41f74f 277
mbed_official 585:a1ed5b41f74f 278 /* Clock mode status check */
mbed_official 585:a1ed5b41f74f 279 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
mbed_official 585:a1ed5b41f74f 280 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 585:a1ed5b41f74f 281 }
mbed_official 585:a1ed5b41f74f 282 /* Use LPTMR to wait for 1ms for FLL clock stabilization */
mbed_official 585:a1ed5b41f74f 283 SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* Allow software control of LPMTR */
mbed_official 585:a1ed5b41f74f 284 LPTMR0->CMR = LPTMR_CMR_COMPARE(0); /* Default 1 LPO tick */
mbed_official 585:a1ed5b41f74f 285 LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
mbed_official 585:a1ed5b41f74f 286 LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
mbed_official 585:a1ed5b41f74f 287 LPTMR0->CSR = LPTMR_CSR_TEN_MASK; /* LPMTR enable */
mbed_official 585:a1ed5b41f74f 288 while((LPTMR0->CSR & LPTMR_CSR_TCF_MASK) == 0u) {
mbed_official 585:a1ed5b41f74f 289 }
mbed_official 585:a1ed5b41f74f 290 LPTMR0->CSR = 0x00; /* Disable LPTMR */
mbed_official 585:a1ed5b41f74f 291 SIM->SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
mbed_official 585:a1ed5b41f74f 292 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
mbed_official 585:a1ed5b41f74f 293 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
mbed_official 585:a1ed5b41f74f 294 }
mbed_official 585:a1ed5b41f74f 295 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
mbed_official 585:a1ed5b41f74f 296 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 585:a1ed5b41f74f 297 }
mbed_official 585:a1ed5b41f74f 298 #elif (MCG_MODE == MCG_MODE_PEE)
mbed_official 585:a1ed5b41f74f 299 while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
mbed_official 585:a1ed5b41f74f 300 }
mbed_official 585:a1ed5b41f74f 301 #endif
mbed_official 585:a1ed5b41f74f 302
mbed_official 585:a1ed5b41f74f 303 /* Very-low-power run mode enable */
mbed_official 585:a1ed5b41f74f 304 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
mbed_official 585:a1ed5b41f74f 305 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
mbed_official 585:a1ed5b41f74f 306 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
mbed_official 585:a1ed5b41f74f 307 }
mbed_official 585:a1ed5b41f74f 308 #endif
mbed_official 585:a1ed5b41f74f 309
mbed_official 585:a1ed5b41f74f 310 /* PLL loss of lock interrupt request initialization */
mbed_official 585:a1ed5b41f74f 311 if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
mbed_official 585:a1ed5b41f74f 312 NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
mbed_official 585:a1ed5b41f74f 313 }
mbed_official 585:a1ed5b41f74f 314 #endif //#ifdef CLOCK_SETUP
mbed_official 585:a1ed5b41f74f 315
mbed_official 585:a1ed5b41f74f 316 }
mbed_official 585:a1ed5b41f74f 317
mbed_official 585:a1ed5b41f74f 318 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 319 -- SystemCoreClockUpdate()
mbed_official 585:a1ed5b41f74f 320 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 321
mbed_official 585:a1ed5b41f74f 322 void SystemCoreClockUpdate (void) {
mbed_official 585:a1ed5b41f74f 323
mbed_official 585:a1ed5b41f74f 324 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 585:a1ed5b41f74f 325 uint16_t Divider;
mbed_official 585:a1ed5b41f74f 326
mbed_official 585:a1ed5b41f74f 327 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
mbed_official 585:a1ed5b41f74f 328 /* Output of FLL or PLL is selected */
mbed_official 585:a1ed5b41f74f 329 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
mbed_official 585:a1ed5b41f74f 330 /* FLL is selected */
mbed_official 585:a1ed5b41f74f 331 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
mbed_official 585:a1ed5b41f74f 332 /* External reference clock is selected */
mbed_official 585:a1ed5b41f74f 333 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 585:a1ed5b41f74f 334 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) {
mbed_official 585:a1ed5b41f74f 335 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
mbed_official 585:a1ed5b41f74f 336 case 0x38U:
mbed_official 585:a1ed5b41f74f 337 Divider = 1536U;
mbed_official 585:a1ed5b41f74f 338 break;
mbed_official 585:a1ed5b41f74f 339 case 0x30U:
mbed_official 585:a1ed5b41f74f 340 Divider = 1280U;
mbed_official 585:a1ed5b41f74f 341 break;
mbed_official 585:a1ed5b41f74f 342 default:
mbed_official 585:a1ed5b41f74f 343 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 585:a1ed5b41f74f 344 break;
mbed_official 585:a1ed5b41f74f 345 }
mbed_official 585:a1ed5b41f74f 346 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
mbed_official 585:a1ed5b41f74f 347 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 585:a1ed5b41f74f 348 }
mbed_official 585:a1ed5b41f74f 349 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 585:a1ed5b41f74f 350 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
mbed_official 585:a1ed5b41f74f 351 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 585:a1ed5b41f74f 352 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
mbed_official 585:a1ed5b41f74f 353 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 585:a1ed5b41f74f 354 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 585:a1ed5b41f74f 355 case 0x00U:
mbed_official 585:a1ed5b41f74f 356 MCGOUTClock *= 640U;
mbed_official 585:a1ed5b41f74f 357 break;
mbed_official 585:a1ed5b41f74f 358 case 0x20U:
mbed_official 585:a1ed5b41f74f 359 MCGOUTClock *= 1280U;
mbed_official 585:a1ed5b41f74f 360 break;
mbed_official 585:a1ed5b41f74f 361 case 0x40U:
mbed_official 585:a1ed5b41f74f 362 MCGOUTClock *= 1920U;
mbed_official 585:a1ed5b41f74f 363 break;
mbed_official 585:a1ed5b41f74f 364 case 0x60U:
mbed_official 585:a1ed5b41f74f 365 MCGOUTClock *= 2560U;
mbed_official 585:a1ed5b41f74f 366 break;
mbed_official 585:a1ed5b41f74f 367 case 0x80U:
mbed_official 585:a1ed5b41f74f 368 MCGOUTClock *= 732U;
mbed_official 585:a1ed5b41f74f 369 break;
mbed_official 585:a1ed5b41f74f 370 case 0xA0U:
mbed_official 585:a1ed5b41f74f 371 MCGOUTClock *= 1464U;
mbed_official 585:a1ed5b41f74f 372 break;
mbed_official 585:a1ed5b41f74f 373 case 0xC0U:
mbed_official 585:a1ed5b41f74f 374 MCGOUTClock *= 2197U;
mbed_official 585:a1ed5b41f74f 375 break;
mbed_official 585:a1ed5b41f74f 376 case 0xE0U:
mbed_official 585:a1ed5b41f74f 377 MCGOUTClock *= 2929U;
mbed_official 585:a1ed5b41f74f 378 break;
mbed_official 585:a1ed5b41f74f 379 default:
mbed_official 585:a1ed5b41f74f 380 break;
mbed_official 585:a1ed5b41f74f 381 }
mbed_official 585:a1ed5b41f74f 382 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
mbed_official 585:a1ed5b41f74f 383 /* PLL is selected */
mbed_official 585:a1ed5b41f74f 384 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
mbed_official 585:a1ed5b41f74f 385 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 585:a1ed5b41f74f 386 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
mbed_official 585:a1ed5b41f74f 387 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 585:a1ed5b41f74f 388 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
mbed_official 585:a1ed5b41f74f 389 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
mbed_official 585:a1ed5b41f74f 390 /* Internal reference clock is selected */
mbed_official 585:a1ed5b41f74f 391 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
mbed_official 585:a1ed5b41f74f 392 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 585:a1ed5b41f74f 393 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
mbed_official 585:a1ed5b41f74f 394 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
mbed_official 585:a1ed5b41f74f 395 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
mbed_official 585:a1ed5b41f74f 396 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
mbed_official 585:a1ed5b41f74f 397 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
mbed_official 585:a1ed5b41f74f 398 /* External reference clock is selected */
mbed_official 585:a1ed5b41f74f 399 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 585:a1ed5b41f74f 400 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
mbed_official 585:a1ed5b41f74f 401 /* Reserved value */
mbed_official 585:a1ed5b41f74f 402 return;
mbed_official 585:a1ed5b41f74f 403 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
mbed_official 585:a1ed5b41f74f 404 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 585:a1ed5b41f74f 405
mbed_official 585:a1ed5b41f74f 406 }