Hexiwear_zeta / Mbed OS HexiHeart_Main

The HexiHeart is a demo project product that takes advantage of many of the onboard Hexiwear sensors and capabilities to create a multifunctional fitness and safety watch.

Dependencies:   FXAS21002 FXOS8700 Hexi_KW40Z Hexi_OLED_SSD1351 MAXIM W25Q64FVSSIG HTU21D MPL3115A2 TSL2561

Fork of HexiHeart_Alex by Hexiwear_zeta

Hexi_Battery/hexi_battery.cpp@22:3de592f8e696, 2018-05-10 (annotated)

Committer:
asong
Date:
Thu May 10 03:44:47 2018 +0000
Revision:
22:3de592f8e696
Parent:
4:0803151bc5e4 
Added stages to the heart rate simulation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nbaker 4:0803151bc5e4 1
nbaker 4:0803151bc5e4 2 #include "hexi_battery.h"
nbaker 4:0803151bc5e4 3 #include "mbed.h"
nbaker 4:0803151bc5e4 4
nbaker 4:0803151bc5e4 5 #define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
nbaker 4:0803151bc5e4 6 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
nbaker 4:0803151bc5e4 7 #define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
nbaker 4:0803151bc5e4 8 #define ADC_BRD_SC1_COCO(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT))
nbaker 4:0803151bc5e4 9 #define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
nbaker 4:0803151bc5e4 10 #define ADC_BRD_R_D(base, index) (ADC_RD_R_D(base, index))
nbaker 4:0803151bc5e4 11 #define ADC_R_REG(base,index) ((base)->R[index])
nbaker 4:0803151bc5e4 12 #define SIM_BWR_SCGC_BIT(base, index, value) (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)) = (uint32_t)(value))
nbaker 4:0803151bc5e4 13 #define SIM_SCGC_BIT_SHIFT(index) ((uint32_t)(index) & ((1U << 5) - 1U))
nbaker 4:0803151bc5e4 14 #define SIM_SCGC_BIT_REG(base, index) (*((volatile uint32_t *)&SIM_SCGC1_REG(base) + (((uint32_t)(index) >> 5) - 0U)))
nbaker 4:0803151bc5e4 15 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
nbaker 4:0803151bc5e4 16
nbaker 4:0803151bc5e4 17 #define ADC_RD_CFG1(base) (ADC_CFG1_REG(base))
nbaker 4:0803151bc5e4 18 #define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
nbaker 4:0803151bc5e4 19
nbaker 4:0803151bc5e4 20 #define ADC_CFG1_REG(base) ((base)->CFG1)
nbaker 4:0803151bc5e4 21 #define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
nbaker 4:0803151bc5e4 22 #define ADC_CFG2_REG(base) ((base)->CFG2)
nbaker 4:0803151bc5e4 23
nbaker 4:0803151bc5e4 24 #define ADC_WR_CV1(base, value) (ADC_CV1_REG(base) = (value))
nbaker 4:0803151bc5e4 25 #define ADC_CV1_REG(base) ((base)->CV1)
nbaker 4:0803151bc5e4 26 #define ADC_WR_CV2(base, value) (ADC_CV2_REG(base) = (value))
nbaker 4:0803151bc5e4 27 #define ADC_CV2_REG(base) ((base)->CV2)
nbaker 4:0803151bc5e4 28
nbaker 4:0803151bc5e4 29 #define ADC_WR_SC2(base, value) (ADC_SC2_REG(base) = (value))
nbaker 4:0803151bc5e4 30 #define ADC_SC2_REG(base) ((base)->SC2)
nbaker 4:0803151bc5e4 31
nbaker 4:0803151bc5e4 32 #define ADC_WR_SC3(base, value) (ADC_SC3_REG(base) = (value))
nbaker 4:0803151bc5e4 33 #define ADC_SC3_REG(base) ((base)->SC3)
nbaker 4:0803151bc5e4 34
nbaker 4:0803151bc5e4 35 #define ADC_RD_SC2(base) (ADC_SC2_REG(base))
nbaker 4:0803151bc5e4 36 #define ADC_RD_CFG2(base) (ADC_CFG2_REG(base))
nbaker 4:0803151bc5e4 37 #define ADC_CFG2_REG(base) ((base)->CFG2)
nbaker 4:0803151bc5e4 38
nbaker 4:0803151bc5e4 39 #define ADC_RD_SC3(base) (ADC_SC3_REG(base))
nbaker 4:0803151bc5e4 40 #define ADC_SC3_REG(base) ((base)->SC3)
nbaker 4:0803151bc5e4 41
nbaker 4:0803151bc5e4 42 #define ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
nbaker 4:0803151bc5e4 43 const IRQn_Type g_adcIrqId[ADC_INSTANCE_COUNT] = ADC_IRQS;
nbaker 4:0803151bc5e4 44
nbaker 4:0803151bc5e4 45 typedef enum _adc16_chn {
nbaker 4:0803151bc5e4 46 kAdc16Chn0 = 0U, /*!< AD0. */
nbaker 4:0803151bc5e4 47 kAdc16Chn1 = 1U, /*!< AD1. */
nbaker 4:0803151bc5e4 48 kAdc16Chn2 = 2U, /*!< AD2. */
nbaker 4:0803151bc5e4 49 kAdc16Chn3 = 3U, /*!< AD3. */
nbaker 4:0803151bc5e4 50 kAdc16Chn4 = 4U, /*!< AD4. */
nbaker 4:0803151bc5e4 51 kAdc16Chn5 = 5U, /*!< AD5. */
nbaker 4:0803151bc5e4 52 kAdc16Chn6 = 6U, /*!< AD6. */
nbaker 4:0803151bc5e4 53 kAdc16Chn7 = 7U, /*!< AD6. */
nbaker 4:0803151bc5e4 54 kAdc16Chn8 = 8U, /*!< AD8. */
nbaker 4:0803151bc5e4 55 kAdc16Chn9 = 9U, /*!< AD9. */
nbaker 4:0803151bc5e4 56 kAdc16Chn10 = 10U, /*!< AD10. */
nbaker 4:0803151bc5e4 57 kAdc16Chn11 = 11U, /*!< AD11. */
nbaker 4:0803151bc5e4 58 kAdc16Chn12 = 12U, /*!< AD12. */
nbaker 4:0803151bc5e4 59 kAdc16Chn13 = 13U, /*!< AD13. */
nbaker 4:0803151bc5e4 60 kAdc16Chn14 = 14U, /*!< AD14. */
nbaker 4:0803151bc5e4 61 kAdc16Chn15 = 15U, /*!< AD15. */
nbaker 4:0803151bc5e4 62 kAdc16Chn16 = 16U, /*!< AD16. */
nbaker 4:0803151bc5e4 63 kAdc16Chn17 = 17U, /*!< AD17. */
nbaker 4:0803151bc5e4 64 kAdc16Chn18 = 18U, /*!< AD18. */
nbaker 4:0803151bc5e4 65 kAdc16Chn19 = 19U, /*!< AD19. */
nbaker 4:0803151bc5e4 66 kAdc16Chn20 = 20U, /*!< AD20. */
nbaker 4:0803151bc5e4 67 kAdc16Chn21 = 21U, /*!< AD21. */
nbaker 4:0803151bc5e4 68 kAdc16Chn22 = 22U, /*!< AD22. */
nbaker 4:0803151bc5e4 69 kAdc16Chn23 = 23U, /*!< AD23. */
nbaker 4:0803151bc5e4 70 kAdc16Chn24 = 24U, /*!< AD24. */
nbaker 4:0803151bc5e4 71 kAdc16Chn25 = 25U, /*!< AD25. */
nbaker 4:0803151bc5e4 72 kAdc16Chn26 = 26U, /*!< AD26. */
nbaker 4:0803151bc5e4 73 kAdc16Chn27 = 27U, /*!< AD27. */
nbaker 4:0803151bc5e4 74 kAdc16Chn28 = 28U, /*!< AD28. */
nbaker 4:0803151bc5e4 75 kAdc16Chn29 = 29U, /*!< AD29. */
nbaker 4:0803151bc5e4 76 kAdc16Chn30 = 30U, /*!< AD30. */
nbaker 4:0803151bc5e4 77 kAdc16Chn31 = 31U, /*!< AD31. */
nbaker 4:0803151bc5e4 78
nbaker 4:0803151bc5e4 79 kAdc16Chn0d = kAdc16Chn0, /*!< DAD0. */
nbaker 4:0803151bc5e4 80 kAdc16Chn1d = kAdc16Chn1, /*!< DAD1. */
nbaker 4:0803151bc5e4 81 kAdc16Chn2d = kAdc16Chn2, /*!< DAD2. */
nbaker 4:0803151bc5e4 82 kAdc16Chn3d = kAdc16Chn3, /*!< DAD3. */
nbaker 4:0803151bc5e4 83 kAdc16Chn4a = kAdc16Chn4, /*!< AD4a. */
nbaker 4:0803151bc5e4 84 kAdc16Chn5a = kAdc16Chn5, /*!< AD5a. */
nbaker 4:0803151bc5e4 85 kAdc16Chn6a = kAdc16Chn6, /*!< AD6a. */
nbaker 4:0803151bc5e4 86 kAdc16Chn7a = kAdc16Chn7, /*!< AD7a. */
nbaker 4:0803151bc5e4 87 kAdc16Chn4b = kAdc16Chn4, /*!< AD4b. */
nbaker 4:0803151bc5e4 88 kAdc16Chn5b = kAdc16Chn5, /*!< AD5b. */
nbaker 4:0803151bc5e4 89 kAdc16Chn6b = kAdc16Chn6, /*!< AD6b. */
nbaker 4:0803151bc5e4 90 kAdc16Chn7b = kAdc16Chn7 /*!< AD7b. */
nbaker 4:0803151bc5e4 91
nbaker 4:0803151bc5e4 92 } adc16_chn_t;
nbaker 4:0803151bc5e4 93
nbaker 4:0803151bc5e4 94 typedef enum _adc16_status {
nbaker 4:0803151bc5e4 95 kStatus_ADC16_Success = 0U, /*!< Success. */
nbaker 4:0803151bc5e4 96 kStatus_ADC16_InvalidArgument = 1U, /*!< Invalid argument existed. */
nbaker 4:0803151bc5e4 97 kStatus_ADC16_Failed = 2U /*!< Execution failed. */
nbaker 4:0803151bc5e4 98 } adc16_status_t;
nbaker 4:0803151bc5e4 99
nbaker 4:0803151bc5e4 100 typedef struct Adc16ChnConfig {
nbaker 4:0803151bc5e4 101 adc16_chn_t chnIdx; /*!< Select the sample channel index. */
nbaker 4:0803151bc5e4 102 bool convCompletedIntEnable; /*!< Enable the conversion complete interrupt. */
nbaker 4:0803151bc5e4 103 #if FSL_FEATURE_ADC16_HAS_DIFF_MODE
nbaker 4:0803151bc5e4 104 bool diffConvEnable; /*!< Enable the differential conversion. */
nbaker 4:0803151bc5e4 105 #endif /** FSL_FEATURE_ADC16_HAS_DIFF_MODE */
nbaker 4:0803151bc5e4 106 } adc16_chn_config_t;
nbaker 4:0803151bc5e4 107
nbaker 4:0803151bc5e4 108 extern const adc16_chn_config_t BATTERY_ADC_ChnConfig;
nbaker 4:0803151bc5e4 109
nbaker 4:0803151bc5e4 110 const adc16_chn_config_t BATTERY_ADC_ChnConfig = {
nbaker 4:0803151bc5e4 111 .chnIdx = kAdc16Chn16,
nbaker 4:0803151bc5e4 112 .convCompletedIntEnable = false,
nbaker 4:0803151bc5e4 113 .diffConvEnable = false
nbaker 4:0803151bc5e4 114 };
nbaker 4:0803151bc5e4 115
nbaker 4:0803151bc5e4 116 ADC_Type * const g_adcBase[] = ADC_BASE_PTRS;
nbaker 4:0803151bc5e4 117
nbaker 4:0803151bc5e4 118
nbaker 4:0803151bc5e4 119 void ADC16_HAL_ConfigChn(ADC_Type * base, uint32_t chnGroup, const adc16_chn_config_t *configPtr)
nbaker 4:0803151bc5e4 120 {
nbaker 4:0803151bc5e4 121 uint16_t tmp = 0U;
nbaker 4:0803151bc5e4 122
nbaker 4:0803151bc5e4 123 /** Interrupt enable. */
nbaker 4:0803151bc5e4 124 if (configPtr->convCompletedIntEnable) {
nbaker 4:0803151bc5e4 125 tmp |= ADC_SC1_AIEN_MASK;
nbaker 4:0803151bc5e4 126 }
nbaker 4:0803151bc5e4 127
nbaker 4:0803151bc5e4 128 /** Differential mode enable. */
nbaker 4:0803151bc5e4 129 #if FSL_FEATURE_ADC16_HAS_DIFF_MODE
nbaker 4:0803151bc5e4 130 if (configPtr->diffConvEnable) {
nbaker 4:0803151bc5e4 131 tmp |= ADC_SC1_DIFF_MASK;
nbaker 4:0803151bc5e4 132 }
nbaker 4:0803151bc5e4 133 #endif /** FSL_FEATURE_ADC16_HAS_DIFF_MODE */
nbaker 4:0803151bc5e4 134
nbaker 4:0803151bc5e4 135 /** Input channel select. */
nbaker 4:0803151bc5e4 136 tmp |= ADC_SC1_ADCH((uint32_t)(configPtr->chnIdx));
nbaker 4:0803151bc5e4 137
nbaker 4:0803151bc5e4 138 ADC_WR_SC1(base, chnGroup, tmp);
nbaker 4:0803151bc5e4 139 }
nbaker 4:0803151bc5e4 140
nbaker 4:0803151bc5e4 141 adc16_status_t ADC16_DRV_ConfigConvChn(uint32_t instance,
nbaker 4:0803151bc5e4 142 uint32_t chnGroup, const adc16_chn_config_t *configPtr)
nbaker 4:0803151bc5e4 143 {
nbaker 4:0803151bc5e4 144 ADC_Type * base = g_adcBase[instance];
nbaker 4:0803151bc5e4 145
nbaker 4:0803151bc5e4 146 if (!configPtr) {
nbaker 4:0803151bc5e4 147 return kStatus_ADC16_InvalidArgument;
nbaker 4:0803151bc5e4 148 }
nbaker 4:0803151bc5e4 149
nbaker 4:0803151bc5e4 150 ADC16_HAL_ConfigChn(base, chnGroup, configPtr);
nbaker 4:0803151bc5e4 151
nbaker 4:0803151bc5e4 152 return kStatus_ADC16_Success;
nbaker 4:0803151bc5e4 153 }
nbaker 4:0803151bc5e4 154
nbaker 4:0803151bc5e4 155 static inline bool ADC16_HAL_GetChnConvCompletedFlag(ADC_Type * base, uint32_t chnGroup)
nbaker 4:0803151bc5e4 156 {
nbaker 4:0803151bc5e4 157 return (1U == ADC_BRD_SC1_COCO(base, chnGroup) );
nbaker 4:0803151bc5e4 158 }
nbaker 4:0803151bc5e4 159
nbaker 4:0803151bc5e4 160 void ADC16_DRV_WaitConvDone(uint32_t instance, uint32_t chnGroup)
nbaker 4:0803151bc5e4 161 {
nbaker 4:0803151bc5e4 162 ADC_Type * base = g_adcBase[instance];
nbaker 4:0803151bc5e4 163
nbaker 4:0803151bc5e4 164 while ( !ADC16_HAL_GetChnConvCompletedFlag(base, chnGroup) )
nbaker 4:0803151bc5e4 165 {}
nbaker 4:0803151bc5e4 166 }
nbaker 4:0803151bc5e4 167
nbaker 4:0803151bc5e4 168 static inline uint16_t ADC16_HAL_GetChnConvValue(ADC_Type * base, uint32_t chnGroup )
nbaker 4:0803151bc5e4 169 {
nbaker 4:0803151bc5e4 170 return (uint16_t)(ADC_BRD_R_D(base, chnGroup) );
nbaker 4:0803151bc5e4 171 }
nbaker 4:0803151bc5e4 172
nbaker 4:0803151bc5e4 173 uint16_t ADC16_DRV_GetConvValueRAW(uint32_t instance, uint32_t chnGroup)
nbaker 4:0803151bc5e4 174 {
nbaker 4:0803151bc5e4 175
nbaker 4:0803151bc5e4 176 ADC_Type * base = g_adcBase[instance];
nbaker 4:0803151bc5e4 177
nbaker 4:0803151bc5e4 178 return ADC16_HAL_GetChnConvValue(base, chnGroup);
nbaker 4:0803151bc5e4 179 }
nbaker 4:0803151bc5e4 180
nbaker 4:0803151bc5e4 181 int16_t ADC16_DRV_GetConvValueSigned(uint32_t instance, uint32_t chnGroup)
nbaker 4:0803151bc5e4 182 {
nbaker 4:0803151bc5e4 183 return (int16_t)ADC16_DRV_GetConvValueRAW(instance, chnGroup);
nbaker 4:0803151bc5e4 184 }
nbaker 4:0803151bc5e4 185
nbaker 4:0803151bc5e4 186 void ADC16_DRV_PauseConv(uint32_t instance, uint32_t chnGroup)
nbaker 4:0803151bc5e4 187 {
nbaker 4:0803151bc5e4 188 adc16_chn_config_t configStruct;
nbaker 4:0803151bc5e4 189
nbaker 4:0803151bc5e4 190 configStruct.chnIdx = kAdc16Chn31;
nbaker 4:0803151bc5e4 191 configStruct.convCompletedIntEnable = false;
nbaker 4:0803151bc5e4 192 #if FSL_FEATURE_ADC16_HAS_DIFF_MODE
nbaker 4:0803151bc5e4 193 configStruct.diffConvEnable = false;
nbaker 4:0803151bc5e4 194 #endif
nbaker 4:0803151bc5e4 195 ADC16_DRV_ConfigConvChn(instance, chnGroup, &configStruct);
nbaker 4:0803151bc5e4 196 }
nbaker 4:0803151bc5e4 197
nbaker 4:0803151bc5e4 198 typedef enum _adc16_clk_divider {
nbaker 4:0803151bc5e4 199 kAdc16ClkDividerOf1 = 0U, /*!< For divider 1 from the input clock to ADC16. @internal gui name="1" */
nbaker 4:0803151bc5e4 200 kAdc16ClkDividerOf2 = 1U, /*!< For divider 2 from the input clock to ADC16. @internal gui name="2" */
nbaker 4:0803151bc5e4 201 kAdc16ClkDividerOf4 = 2U, /*!< For divider 4 from the input clock to ADC16. @internal gui name="4" */
nbaker 4:0803151bc5e4 202 kAdc16ClkDividerOf8 = 3U /*!< For divider 8 from the input clock to ADC16. @internal gui name="8" */
nbaker 4:0803151bc5e4 203 } adc16_clk_divider_t;
nbaker 4:0803151bc5e4 204
nbaker 4:0803151bc5e4 205 typedef enum _adc16_resolution {
nbaker 4:0803151bc5e4 206 kAdc16ResolutionBitOf8or9 = 0U,
nbaker 4:0803151bc5e4 207 /*!< 8-bit for single end sample, or 9-bit for differential sample. @internal gui name="" */
nbaker 4:0803151bc5e4 208 kAdc16ResolutionBitOfSingleEndAs8 = kAdc16ResolutionBitOf8or9, /*!< 8-bit for single end sample. @internal gui name="8 bit in single mode" */
nbaker 4:0803151bc5e4 209 kAdc16ResolutionBitOfDiffModeAs9 = kAdc16ResolutionBitOf8or9, /*!< 9-bit for differential sample. @internal gui name="9 bit in differential mode" */
nbaker 4:0803151bc5e4 210
nbaker 4:0803151bc5e4 211 kAdc16ResolutionBitOf12or13 = 1U,
nbaker 4:0803151bc5e4 212 /*!< 12-bit for single end sample, or 13-bit for differential sample. @internal gui name="" */
nbaker 4:0803151bc5e4 213 kAdc16ResolutionBitOfSingleEndAs12 = kAdc16ResolutionBitOf12or13, /*!< 12-bit for single end sample. @internal gui name="12 bit in single mode" */
nbaker 4:0803151bc5e4 214 kAdc16ResolutionBitOfDiffModeAs13 = kAdc16ResolutionBitOf12or13, /*!< 13-bit for differential sample. @internal gui name="13 bit in differential mode" */
nbaker 4:0803151bc5e4 215
nbaker 4:0803151bc5e4 216 kAdc16ResolutionBitOf10or11 = 2U,
nbaker 4:0803151bc5e4 217 /*!< 10-bit for single end sample, or 11-bit for differential sample. @internal gui name="" */
nbaker 4:0803151bc5e4 218 kAdc16ResolutionBitOfSingleEndAs10 = kAdc16ResolutionBitOf10or11, /*!< 10-bit for single end sample. @internal gui name="10 bit in single mode" */
nbaker 4:0803151bc5e4 219 kAdc16ResolutionBitOfDiffModeAs11 = kAdc16ResolutionBitOf10or11 /*!< 11-bit for differential sample. @internal gui name="11 bit in differential mode" */
nbaker 4:0803151bc5e4 220 #if (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
nbaker 4:0803151bc5e4 221 , kAdc16ResolutionBitOf16 = 3U,
nbaker 4:0803151bc5e4 222 /*!< 16-bit for both single end sample and differential sample. @internal gui name="16-bit" */
nbaker 4:0803151bc5e4 223 kAdc16ResolutionBitOfSingleEndAs16 = kAdc16ResolutionBitOf16, /*!< 16-bit for single end sample. @internal gui name="" */
nbaker 4:0803151bc5e4 224 kAdc16ResolutionBitOfDiffModeAs16 = kAdc16ResolutionBitOf16 /*!< 16-bit for differential sample. @internal gui name="" */
nbaker 4:0803151bc5e4 225
nbaker 4:0803151bc5e4 226 #endif /** FSL_FEATURE_ADC16_MAX_RESOLUTION */
nbaker 4:0803151bc5e4 227 } adc16_resolution_t;
nbaker 4:0803151bc5e4 228
nbaker 4:0803151bc5e4 229 typedef enum _adc16_long_sample_cycle {
nbaker 4:0803151bc5e4 230 kAdc16LongSampleCycleOf24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
nbaker 4:0803151bc5e4 231 kAdc16LongSampleCycleOf16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
nbaker 4:0803151bc5e4 232 kAdc16LongSampleCycleOf10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
nbaker 4:0803151bc5e4 233 kAdc16LongSampleCycleOf4 = 3U /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
nbaker 4:0803151bc5e4 234 } adc16_long_sample_cycle_t;
nbaker 4:0803151bc5e4 235
nbaker 4:0803151bc5e4 236 typedef enum _adc16_clk_src_mode {
nbaker 4:0803151bc5e4 237 kAdc16ClkSrcOfBusClk = 0U, /*!< For input as bus clock. @internal gui name="Bus clock" */
nbaker 4:0803151bc5e4 238 kAdc16ClkSrcOfAltClk2 = 1U, /*!< For input as alternate clock 2 (AltClk2). @internal gui name="Alternate clock 2" */
nbaker 4:0803151bc5e4 239 kAdc16ClkSrcOfAltClk = 2U, /*!< For input as alternate clock (ALTCLK). @internal gui name="Alternate clock 1" */
nbaker 4:0803151bc5e4 240 kAdc16ClkSrcOfAsynClk = 3U /*!< For input as asynchronous clock (ADACK). @internal gui name="Asynchronous clock" */
nbaker 4:0803151bc5e4 241 } adc16_clk_src_mode_t;
nbaker 4:0803151bc5e4 242
nbaker 4:0803151bc5e4 243 typedef enum _adc16_ref_volt_src {
nbaker 4:0803151bc5e4 244 kAdc16RefVoltSrcOfVref = 0U, /*!< For external pins pair of VrefH and VrefL. @internal gui name="Vref pair" */
nbaker 4:0803151bc5e4 245 kAdc16RefVoltSrcOfValt = 1U /*!< For alternate reference pair of ValtH and ValtL. @internal gui name="Valt pair" */
nbaker 4:0803151bc5e4 246 } adc16_ref_volt_src_t;
nbaker 4:0803151bc5e4 247
nbaker 4:0803151bc5e4 248 typedef struct Adc16ConverterConfig {
nbaker 4:0803151bc5e4 249 bool lowPowerEnable; /*!< Enable low power. @internal gui name="Low power mode" id="LowPowerMode" */
nbaker 4:0803151bc5e4 250 adc16_clk_divider_t clkDividerMode; /*!< Select the divider of input clock source. @internal gui name="Clock divider" id="ClockDivider" */
nbaker 4:0803151bc5e4 251 bool longSampleTimeEnable; /*!< Enable the long sample time. @internal gui name="Long sample time" id="LongSampleTime" */
nbaker 4:0803151bc5e4 252 adc16_resolution_t resolution; /*!< Select the sample resolution mode. @internal gui name="Resolution" id="Resolution" */
nbaker 4:0803151bc5e4 253 adc16_clk_src_mode_t clkSrc; /*!< Select the input clock source to converter. @internal gui name="Clock source" id="ClockSource" */
nbaker 4:0803151bc5e4 254 bool asyncClkEnable; /*!< Enable the asynchronous clock inside the ADC. @internal gui name="Internal async. clock" id="InternalAsyncClock" */
nbaker 4:0803151bc5e4 255 bool highSpeedEnable; /*!< Enable the high speed mode. @internal gui name="High speed mode" id="HighSpeed" */
nbaker 4:0803151bc5e4 256 adc16_long_sample_cycle_t longSampleCycleMode; /*!< Select the long sample mode. @internal gui name="Long sample mode" id="LongSampleMode" */
nbaker 4:0803151bc5e4 257 bool hwTriggerEnable; /*!< Enable hardware trigger function. @internal gui name="Hardware trigger" id="HwTrigger" */
nbaker 4:0803151bc5e4 258 adc16_ref_volt_src_t refVoltSrc; /*!< Select the reference voltage source. @internal gui name="Voltage reference" id="ReferenceVoltage" */
nbaker 4:0803151bc5e4 259 bool continuousConvEnable; /*!< Enable continuous conversion mode. @internal gui name="Continuous mode" id="ContinuousMode" */
nbaker 4:0803151bc5e4 260 #if FSL_FEATURE_ADC16_HAS_DMA
nbaker 4:0803151bc5e4 261 bool dmaEnable; /*!< Enable the DMA for ADC converter. @internal gui name="DMA mode" id="DMASupport" */
nbaker 4:0803151bc5e4 262 #endif /** FSL_FEATURE_ADC16_HAS_DMA */
nbaker 4:0803151bc5e4 263 } adc16_converter_config_t;
nbaker 4:0803151bc5e4 264
nbaker 4:0803151bc5e4 265 const adc16_converter_config_t BATTERY_ADC_InitConfig = {
nbaker 4:0803151bc5e4 266 .lowPowerEnable = false,
nbaker 4:0803151bc5e4 267 .clkDividerMode = kAdc16ClkDividerOf1,
nbaker 4:0803151bc5e4 268 .longSampleTimeEnable = false,
nbaker 4:0803151bc5e4 269 .resolution = kAdc16ResolutionBitOf16,
nbaker 4:0803151bc5e4 270 .clkSrc = kAdc16ClkSrcOfBusClk,
nbaker 4:0803151bc5e4 271 .asyncClkEnable = false,
nbaker 4:0803151bc5e4 272 .highSpeedEnable = true,
nbaker 4:0803151bc5e4 273 .longSampleCycleMode = kAdc16LongSampleCycleOf4,
nbaker 4:0803151bc5e4 274 .hwTriggerEnable = false,
nbaker 4:0803151bc5e4 275 .refVoltSrc = kAdc16RefVoltSrcOfVref,
nbaker 4:0803151bc5e4 276 .continuousConvEnable = false,
nbaker 4:0803151bc5e4 277 .dmaEnable = false,
nbaker 4:0803151bc5e4 278 };
nbaker 4:0803151bc5e4 279
nbaker 4:0803151bc5e4 280 #define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
nbaker 4:0803151bc5e4 281
nbaker 4:0803151bc5e4 282 typedef enum _sim_clock_gate_name {
nbaker 4:0803151bc5e4 283 kSimClockGateI2c2 = FSL_SIM_SCGC_BIT(1U, 6U),
nbaker 4:0803151bc5e4 284 kSimClockGateUart4 = FSL_SIM_SCGC_BIT(1U, 10U),
nbaker 4:0803151bc5e4 285 kSimClockGateUart5 = FSL_SIM_SCGC_BIT(1U, 11U),
nbaker 4:0803151bc5e4 286 kSimClockGateEnet0 = FSL_SIM_SCGC_BIT(2U, 0U),
nbaker 4:0803151bc5e4 287 kSimClockGateDac0 = FSL_SIM_SCGC_BIT(2U, 12U),
nbaker 4:0803151bc5e4 288 kSimClockGateDac1 = FSL_SIM_SCGC_BIT(2U, 13U),
nbaker 4:0803151bc5e4 289 kSimClockGateSpi2 = FSL_SIM_SCGC_BIT(3U, 12U),
nbaker 4:0803151bc5e4 290 kSimClockGateSdhc0 = FSL_SIM_SCGC_BIT(3U, 17U),
nbaker 4:0803151bc5e4 291 kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(3U, 25U),
nbaker 4:0803151bc5e4 292 kSimClockGateAdc1 = FSL_SIM_SCGC_BIT(3U, 27U),
nbaker 4:0803151bc5e4 293 kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U),
nbaker 4:0803151bc5e4 294 kSimClockGateCmt0 = FSL_SIM_SCGC_BIT(4U, 2U),
nbaker 4:0803151bc5e4 295 kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
nbaker 4:0803151bc5e4 296 kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U),
nbaker 4:0803151bc5e4 297 kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U),
nbaker 4:0803151bc5e4 298 kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
nbaker 4:0803151bc5e4 299 kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U),
nbaker 4:0803151bc5e4 300 kSimClockGateUart3 = FSL_SIM_SCGC_BIT(4U, 13U),
nbaker 4:0803151bc5e4 301 kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U),
nbaker 4:0803151bc5e4 302 kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U),
nbaker 4:0803151bc5e4 303 kSimClockGateVref0 = FSL_SIM_SCGC_BIT(4U, 20U),
nbaker 4:0803151bc5e4 304 kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
nbaker 4:0803151bc5e4 305 kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
nbaker 4:0803151bc5e4 306 kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
nbaker 4:0803151bc5e4 307 kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
nbaker 4:0803151bc5e4 308 kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
nbaker 4:0803151bc5e4 309 kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
nbaker 4:0803151bc5e4 310 kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
nbaker 4:0803151bc5e4 311 kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
nbaker 4:0803151bc5e4 312 kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U),
nbaker 4:0803151bc5e4 313 kSimClockGateRnga0 = FSL_SIM_SCGC_BIT(6U, 9U),
nbaker 4:0803151bc5e4 314 kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U),
nbaker 4:0803151bc5e4 315 kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(6U, 13U),
nbaker 4:0803151bc5e4 316 kSimClockGateSai0 = FSL_SIM_SCGC_BIT(6U, 15U),
nbaker 4:0803151bc5e4 317 kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U),
nbaker 4:0803151bc5e4 318 kSimClockGateUsbdcd0 = FSL_SIM_SCGC_BIT(6U, 21U),
nbaker 4:0803151bc5e4 319 kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U),
nbaker 4:0803151bc5e4 320 kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
nbaker 4:0803151bc5e4 321 kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U),
nbaker 4:0803151bc5e4 322 kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U),
nbaker 4:0803151bc5e4 323 kSimClockGateFtm2 = FSL_SIM_SCGC_BIT(6U, 26U),
nbaker 4:0803151bc5e4 324 kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U),
nbaker 4:0803151bc5e4 325 kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U),
nbaker 4:0803151bc5e4 326 kSimClockGateFlexbus0 = FSL_SIM_SCGC_BIT(7U, 0U),
nbaker 4:0803151bc5e4 327 kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 1U),
nbaker 4:0803151bc5e4 328 kSimClockGateMpu0 = FSL_SIM_SCGC_BIT(7U, 2U),
nbaker 4:0803151bc5e4 329 #if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
nbaker 4:0803151bc5e4 330 } sim_clock_gate_name_k64f12_t;
nbaker 4:0803151bc5e4 331 #else
nbaker 4:0803151bc5e4 332 } sim_clock_gate_name_t;
nbaker 4:0803151bc5e4 333 #endif
nbaker 4:0803151bc5e4 334
nbaker 4:0803151bc5e4 335 static const sim_clock_gate_name_t adcGateTable[] = {
nbaker 4:0803151bc5e4 336 kSimClockGateAdc0,
nbaker 4:0803151bc5e4 337 kSimClockGateAdc1
nbaker 4:0803151bc5e4 338 };
nbaker 4:0803151bc5e4 339
nbaker 4:0803151bc5e4 340 static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
nbaker 4:0803151bc5e4 341 {
nbaker 4:0803151bc5e4 342 SIM_BWR_SCGC_BIT(base, name, 1U);
nbaker 4:0803151bc5e4 343 }
nbaker 4:0803151bc5e4 344
nbaker 4:0803151bc5e4 345 void CLOCK_SYS_EnableAdcClock(uint32_t instance)
nbaker 4:0803151bc5e4 346 {
nbaker 4:0803151bc5e4 347 SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
nbaker 4:0803151bc5e4 348 }
nbaker 4:0803151bc5e4 349
nbaker 4:0803151bc5e4 350 void ADC16_HAL_Init(ADC_Type * base)
nbaker 4:0803151bc5e4 351 {
nbaker 4:0803151bc5e4 352 ADC_WR_CFG1(base, 0U);
nbaker 4:0803151bc5e4 353 ADC_WR_CFG2(base, 0U);
nbaker 4:0803151bc5e4 354 ADC_WR_CV1(base, 0U);
nbaker 4:0803151bc5e4 355 ADC_WR_CV2(base, 0U);
nbaker 4:0803151bc5e4 356 ADC_WR_SC2(base, 0U);
nbaker 4:0803151bc5e4 357 ADC_WR_SC3(base, 0U);
nbaker 4:0803151bc5e4 358 #if FSL_FEATURE_ADC16_HAS_PGA
nbaker 4:0803151bc5e4 359 ADC_WR_PGA(base, 0U);
nbaker 4:0803151bc5e4 360 #endif /** FSL_FEATURE_ADC16_HAS_PGA */
nbaker 4:0803151bc5e4 361 }
nbaker 4:0803151bc5e4 362
nbaker 4:0803151bc5e4 363 void ADC16_HAL_ConfigConverter(ADC_Type * base, const adc16_converter_config_t *configPtr)
nbaker 4:0803151bc5e4 364 {
nbaker 4:0803151bc5e4 365 uint16_t cfg1, cfg2, sc2, sc3;
nbaker 4:0803151bc5e4 366
nbaker 4:0803151bc5e4 367 cfg1 = ADC_RD_CFG1(base);
nbaker 4:0803151bc5e4 368 cfg1 &= ~( ADC_CFG1_ADLPC_MASK
nbaker 4:0803151bc5e4 369 | ADC_CFG1_ADIV_MASK
nbaker 4:0803151bc5e4 370 | ADC_CFG1_ADLSMP_MASK
nbaker 4:0803151bc5e4 371 | ADC_CFG1_MODE_MASK
nbaker 4:0803151bc5e4 372 | ADC_CFG1_ADICLK_MASK );
nbaker 4:0803151bc5e4 373
nbaker 4:0803151bc5e4 374 /** Low power mode. */
nbaker 4:0803151bc5e4 375 if (configPtr->lowPowerEnable) {
nbaker 4:0803151bc5e4 376 cfg1 |= ADC_CFG1_ADLPC_MASK;
nbaker 4:0803151bc5e4 377 }
nbaker 4:0803151bc5e4 378 /** Clock divider. */
nbaker 4:0803151bc5e4 379 cfg1 |= ADC_CFG1_ADIV(configPtr->clkDividerMode);
nbaker 4:0803151bc5e4 380 /** Long sample time. */
nbaker 4:0803151bc5e4 381 if (configPtr->longSampleTimeEnable) {
nbaker 4:0803151bc5e4 382 cfg1 |= ADC_CFG1_ADLSMP_MASK;
nbaker 4:0803151bc5e4 383 }
nbaker 4:0803151bc5e4 384 /** Sample resolution mode. */
nbaker 4:0803151bc5e4 385 cfg1 |= ADC_CFG1_MODE(configPtr->resolution);
nbaker 4:0803151bc5e4 386 /** Clock source input. */
nbaker 4:0803151bc5e4 387 cfg1 |= ADC_CFG1_ADICLK(configPtr->clkSrc);
nbaker 4:0803151bc5e4 388
nbaker 4:0803151bc5e4 389 cfg2 = ADC_RD_CFG2(base);
nbaker 4:0803151bc5e4 390 cfg2 &= ~( ADC_CFG2_ADACKEN_MASK
nbaker 4:0803151bc5e4 391 | ADC_CFG2_ADHSC_MASK
nbaker 4:0803151bc5e4 392 | ADC_CFG2_ADLSTS_MASK );
nbaker 4:0803151bc5e4 393 /** Asynchronous clock output enable. */
nbaker 4:0803151bc5e4 394 if (configPtr->asyncClkEnable) {
nbaker 4:0803151bc5e4 395 cfg2 |= ADC_CFG2_ADACKEN_MASK;
nbaker 4:0803151bc5e4 396 }
nbaker 4:0803151bc5e4 397 /** High speed configuration. */
nbaker 4:0803151bc5e4 398 if (configPtr->highSpeedEnable) {
nbaker 4:0803151bc5e4 399 cfg2 |= ADC_CFG2_ADHSC_MASK;
nbaker 4:0803151bc5e4 400 }
nbaker 4:0803151bc5e4 401 /** Long sample time select. */
nbaker 4:0803151bc5e4 402 cfg2 |= ADC_CFG2_ADLSTS(configPtr->longSampleCycleMode);
nbaker 4:0803151bc5e4 403
nbaker 4:0803151bc5e4 404 sc2 = ADC_RD_SC2(base);
nbaker 4:0803151bc5e4 405 sc2 &= ~( ADC_SC2_ADTRG_MASK
nbaker 4:0803151bc5e4 406 | ADC_SC2_REFSEL_MASK
nbaker 4:0803151bc5e4 407 #if FSL_FEATURE_ADC16_HAS_DMA
nbaker 4:0803151bc5e4 408 | ADC_SC2_DMAEN_MASK
nbaker 4:0803151bc5e4 409 #endif /** FSL_FEATURE_ADC16_HAS_DMA */
nbaker 4:0803151bc5e4 410 );
nbaker 4:0803151bc5e4 411 /** Conversion trigger select. */
nbaker 4:0803151bc5e4 412 if (configPtr->hwTriggerEnable) {
nbaker 4:0803151bc5e4 413 sc2 |= ADC_SC2_ADTRG_MASK;
nbaker 4:0803151bc5e4 414 }
nbaker 4:0803151bc5e4 415 /** Voltage reference selection. */
nbaker 4:0803151bc5e4 416 sc2 |= ADC_SC2_REFSEL(configPtr->refVoltSrc);
nbaker 4:0803151bc5e4 417 #if FSL_FEATURE_ADC16_HAS_DMA
nbaker 4:0803151bc5e4 418 /** DMA. */
nbaker 4:0803151bc5e4 419 if (configPtr->dmaEnable) {
nbaker 4:0803151bc5e4 420 sc2 |= ADC_SC2_DMAEN_MASK;
nbaker 4:0803151bc5e4 421 }
nbaker 4:0803151bc5e4 422 #endif /** FSL_FEATURE_ADC16_HAS_DMA */
nbaker 4:0803151bc5e4 423
nbaker 4:0803151bc5e4 424 sc3 = ADC_RD_SC3(base);
nbaker 4:0803151bc5e4 425 sc3 &= ~( ADC_SC3_ADCO_MASK
nbaker 4:0803151bc5e4 426 | ADC_SC3_CALF_MASK );
nbaker 4:0803151bc5e4 427 /** Continuous conversion enable. */
nbaker 4:0803151bc5e4 428 if (configPtr->continuousConvEnable) {
nbaker 4:0803151bc5e4 429 sc3 |= ADC_SC3_ADCO_MASK;
nbaker 4:0803151bc5e4 430 }
nbaker 4:0803151bc5e4 431
nbaker 4:0803151bc5e4 432 ADC_WR_CFG1(base, cfg1);
nbaker 4:0803151bc5e4 433 ADC_WR_CFG2(base, cfg2);
nbaker 4:0803151bc5e4 434 ADC_WR_SC2(base, sc2);
nbaker 4:0803151bc5e4 435 ADC_WR_SC3(base, sc3);
nbaker 4:0803151bc5e4 436 }
nbaker 4:0803151bc5e4 437
nbaker 4:0803151bc5e4 438 static inline void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
nbaker 4:0803151bc5e4 439 {
nbaker 4:0803151bc5e4 440 /** call core API to enable the IRQ*/
nbaker 4:0803151bc5e4 441 NVIC_EnableIRQ(irqNumber);
nbaker 4:0803151bc5e4 442 }
nbaker 4:0803151bc5e4 443
nbaker 4:0803151bc5e4 444 adc16_status_t ADC16_DRV_Init(uint32_t instance, const adc16_converter_config_t *userConfigPtr)
nbaker 4:0803151bc5e4 445 {
nbaker 4:0803151bc5e4 446 ADC_Type * base = g_adcBase[instance];
nbaker 4:0803151bc5e4 447
nbaker 4:0803151bc5e4 448 if (!userConfigPtr) {
nbaker 4:0803151bc5e4 449 return kStatus_ADC16_InvalidArgument;
nbaker 4:0803151bc5e4 450 }
nbaker 4:0803151bc5e4 451 /** Enable clock for ADC. */
nbaker 4:0803151bc5e4 452 CLOCK_SYS_EnableAdcClock(instance);
nbaker 4:0803151bc5e4 453
nbaker 4:0803151bc5e4 454 /** Reset all the register to a known state. */
nbaker 4:0803151bc5e4 455 ADC16_HAL_Init(base);
nbaker 4:0803151bc5e4 456 ADC16_HAL_ConfigConverter(base, userConfigPtr);
nbaker 4:0803151bc5e4 457
nbaker 4:0803151bc5e4 458 /** Enable ADC interrupt in NVIC level.*/
nbaker 4:0803151bc5e4 459 INT_SYS_EnableIRQ(g_adcIrqId[instance] );
nbaker 4:0803151bc5e4 460
nbaker 4:0803151bc5e4 461 return kStatus_ADC16_Success;
nbaker 4:0803151bc5e4 462 }
nbaker 4:0803151bc5e4 463
nbaker 4:0803151bc5e4 464 static uint8_t bat_convert_data(uint16_t input)
nbaker 4:0803151bc5e4 465 {
nbaker 4:0803151bc5e4 466 uint8_t output = 0;
nbaker 4:0803151bc5e4 467
nbaker 4:0803151bc5e4 468 uint16_t bat_mvolts = (uint16_t)( ( (float)input * ( 3.3 / 65535.0 ) ) * 1000 );
nbaker 4:0803151bc5e4 469
nbaker 4:0803151bc5e4 470 if ( bat_mvolts > 2670 ) {
nbaker 4:0803151bc5e4 471 output = 100;
nbaker 4:0803151bc5e4 472 }
nbaker 4:0803151bc5e4 473
nbaker 4:0803151bc5e4 474 else if ( bat_mvolts > 2500 ) {
nbaker 4:0803151bc5e4 475 output = (uint8_t)( 50 + 50.0 * ( ( bat_mvolts - 2500 ) / 170.0 ) );
nbaker 4:0803151bc5e4 476 } else if ( bat_mvolts > 2430 ) {
nbaker 4:0803151bc5e4 477 output = (uint8_t)( 30 + 20.0 * ( ( bat_mvolts - 2430 ) / 70.0 ) );
nbaker 4:0803151bc5e4 478 } else if ( bat_mvolts > 2370 ) {
nbaker 4:0803151bc5e4 479 output = (uint8_t)( 10 + 20.0 * ( ( bat_mvolts - 2370 ) / 60.0 ) );
nbaker 4:0803151bc5e4 480 } else {
nbaker 4:0803151bc5e4 481 output = 0;
nbaker 4:0803151bc5e4 482 }
nbaker 4:0803151bc5e4 483 return output;
nbaker 4:0803151bc5e4 484
nbaker 4:0803151bc5e4 485 }
nbaker 4:0803151bc5e4 486
nbaker 4:0803151bc5e4 487 HexiwearBattery::HexiwearBattery()
nbaker 4:0803151bc5e4 488 {
nbaker 4:0803151bc5e4 489 batCharging = new DigitalIn(PTC12);
nbaker 4:0803151bc5e4 490 batSensSwitch = new DigitalOut(PTC14);
nbaker 4:0803151bc5e4 491 ADC16_DRV_Init(0, &BATTERY_ADC_InitConfig);
nbaker 4:0803151bc5e4 492 ADC16_DRV_ConfigConvChn(0, 0U, &BATTERY_ADC_ChnConfig);
nbaker 4:0803151bc5e4 493 }
nbaker 4:0803151bc5e4 494
nbaker 4:0803151bc5e4 495 HexiwearBattery::~HexiwearBattery()
nbaker 4:0803151bc5e4 496 {
nbaker 4:0803151bc5e4 497 delete batSensSwitch;
nbaker 4:0803151bc5e4 498 delete batCharging;
nbaker 4:0803151bc5e4 499 }
nbaker 4:0803151bc5e4 500
nbaker 4:0803151bc5e4 501 void HexiwearBattery::sensorOn()
nbaker 4:0803151bc5e4 502 {
nbaker 4:0803151bc5e4 503 *batSensSwitch = 0;
nbaker 4:0803151bc5e4 504 };
nbaker 4:0803151bc5e4 505
nbaker 4:0803151bc5e4 506
nbaker 4:0803151bc5e4 507 void HexiwearBattery::sensorOff()
nbaker 4:0803151bc5e4 508 {
nbaker 4:0803151bc5e4 509 *batSensSwitch = 1;
nbaker 4:0803151bc5e4 510 };
nbaker 4:0803151bc5e4 511
nbaker 4:0803151bc5e4 512 bool HexiwearBattery::isBatteryCharging()
nbaker 4:0803151bc5e4 513 {
nbaker 4:0803151bc5e4 514 return *batCharging == 0;
nbaker 4:0803151bc5e4 515 }
nbaker 4:0803151bc5e4 516
nbaker 4:0803151bc5e4 517 uint8_t HexiwearBattery::readLevelPercent()
nbaker 4:0803151bc5e4 518 {
nbaker 4:0803151bc5e4 519 ADC16_DRV_ConfigConvChn( 0, 0, &BATTERY_ADC_ChnConfig);
nbaker 4:0803151bc5e4 520 ADC16_DRV_WaitConvDone ( 0, 0 );
nbaker 4:0803151bc5e4 521 int16_t result = ADC16_DRV_GetConvValueSigned( 0, 0 );
nbaker 4:0803151bc5e4 522 ADC16_DRV_PauseConv(0, 0 );
nbaker 4:0803151bc5e4 523 return bat_convert_data(result);
nbaker 4:0803151bc5e4 524 }
nbaker 4:0803151bc5e4 525