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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Child:
592:a274ee790e56
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 /**
mbed_official 579:53297373a894 2 * \file
mbed_official 579:53297373a894 3 *
mbed_official 579:53297373a894 4 * \brief Instance description for SERCOM0
mbed_official 579:53297373a894 5 *
mbed_official 579:53297373a894 6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
mbed_official 579:53297373a894 7 *
mbed_official 579:53297373a894 8 * \asf_license_start
mbed_official 579:53297373a894 9 *
mbed_official 579:53297373a894 10 * \page License
mbed_official 579:53297373a894 11 *
mbed_official 579:53297373a894 12 * Redistribution and use in source and binary forms, with or without
mbed_official 579:53297373a894 13 * modification, are permitted provided that the following conditions are met:
mbed_official 579:53297373a894 14 *
mbed_official 579:53297373a894 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 579:53297373a894 16 * this list of conditions and the following disclaimer.
mbed_official 579:53297373a894 17 *
mbed_official 579:53297373a894 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 579:53297373a894 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 579:53297373a894 20 * and/or other materials provided with the distribution.
mbed_official 579:53297373a894 21 *
mbed_official 579:53297373a894 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 579:53297373a894 23 * from this software without specific prior written permission.
mbed_official 579:53297373a894 24 *
mbed_official 579:53297373a894 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 579:53297373a894 26 * Atmel microcontroller product.
mbed_official 579:53297373a894 27 *
mbed_official 579:53297373a894 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 579:53297373a894 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 579:53297373a894 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 579:53297373a894 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 579:53297373a894 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 579:53297373a894 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 579:53297373a894 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 579:53297373a894 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 579:53297373a894 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 579:53297373a894 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 579:53297373a894 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 579:53297373a894 39 *
mbed_official 579:53297373a894 40 * \asf_license_stop
mbed_official 579:53297373a894 41 *
mbed_official 579:53297373a894 42 */
mbed_official 579:53297373a894 43 /**
mbed_official 579:53297373a894 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 579:53297373a894 45 */
mbed_official 579:53297373a894 46
mbed_official 579:53297373a894 47 #ifndef _SAMD21_SERCOM0_INSTANCE_
mbed_official 579:53297373a894 48 #define _SAMD21_SERCOM0_INSTANCE_
mbed_official 579:53297373a894 49
mbed_official 579:53297373a894 50 /* ========== Register definition for SERCOM0 peripheral ========== */
mbed_official 579:53297373a894 51 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 52 #define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
mbed_official 579:53297373a894 53 #define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
mbed_official 579:53297373a894 54 #define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
mbed_official 579:53297373a894 55 #define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
mbed_official 579:53297373a894 56 #define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
mbed_official 579:53297373a894 57 #define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 58 #define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
mbed_official 579:53297373a894 59 #define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
mbed_official 579:53297373a894 60 #define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */
mbed_official 579:53297373a894 61 #define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */
mbed_official 579:53297373a894 62 #define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
mbed_official 579:53297373a894 63 #define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
mbed_official 579:53297373a894 64 #define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
mbed_official 579:53297373a894 65 #define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
mbed_official 579:53297373a894 66 #define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
mbed_official 579:53297373a894 67 #define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 68 #define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
mbed_official 579:53297373a894 69 #define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
mbed_official 579:53297373a894 70 #define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */
mbed_official 579:53297373a894 71 #define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */
mbed_official 579:53297373a894 72 #define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
mbed_official 579:53297373a894 73 #define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */
mbed_official 579:53297373a894 74 #define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
mbed_official 579:53297373a894 75 #define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
mbed_official 579:53297373a894 76 #define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
mbed_official 579:53297373a894 77 #define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 78 #define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */
mbed_official 579:53297373a894 79 #define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
mbed_official 579:53297373a894 80 #define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */
mbed_official 579:53297373a894 81 #define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */
mbed_official 579:53297373a894 82 #define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
mbed_official 579:53297373a894 83 #define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */
mbed_official 579:53297373a894 84 #define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */
mbed_official 579:53297373a894 85 #define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
mbed_official 579:53297373a894 86 #define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
mbed_official 579:53297373a894 87 #define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
mbed_official 579:53297373a894 88 #define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
mbed_official 579:53297373a894 89 #define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 90 #define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */
mbed_official 579:53297373a894 91 #define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
mbed_official 579:53297373a894 92 #define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */
mbed_official 579:53297373a894 93 #define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
mbed_official 579:53297373a894 94 #else
mbed_official 579:53297373a894 95 #define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
mbed_official 579:53297373a894 96 #define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
mbed_official 579:53297373a894 97 #define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
mbed_official 579:53297373a894 98 #define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
mbed_official 579:53297373a894 99 #define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
mbed_official 579:53297373a894 100 #define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 101 #define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
mbed_official 579:53297373a894 102 #define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
mbed_official 579:53297373a894 103 #define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */
mbed_official 579:53297373a894 104 #define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */
mbed_official 579:53297373a894 105 #define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
mbed_official 579:53297373a894 106 #define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
mbed_official 579:53297373a894 107 #define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
mbed_official 579:53297373a894 108 #define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
mbed_official 579:53297373a894 109 #define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
mbed_official 579:53297373a894 110 #define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 111 #define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
mbed_official 579:53297373a894 112 #define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
mbed_official 579:53297373a894 113 #define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */
mbed_official 579:53297373a894 114 #define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */
mbed_official 579:53297373a894 115 #define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
mbed_official 579:53297373a894 116 #define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */
mbed_official 579:53297373a894 117 #define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
mbed_official 579:53297373a894 118 #define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
mbed_official 579:53297373a894 119 #define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
mbed_official 579:53297373a894 120 #define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 121 #define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */
mbed_official 579:53297373a894 122 #define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
mbed_official 579:53297373a894 123 #define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */
mbed_official 579:53297373a894 124 #define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */
mbed_official 579:53297373a894 125 #define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
mbed_official 579:53297373a894 126 #define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */
mbed_official 579:53297373a894 127 #define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */
mbed_official 579:53297373a894 128 #define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
mbed_official 579:53297373a894 129 #define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
mbed_official 579:53297373a894 130 #define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
mbed_official 579:53297373a894 131 #define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
mbed_official 579:53297373a894 132 #define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 133 #define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */
mbed_official 579:53297373a894 134 #define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
mbed_official 579:53297373a894 135 #define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */
mbed_official 579:53297373a894 136 #define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
mbed_official 579:53297373a894 137 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 138
mbed_official 579:53297373a894 139 /* ========== Instance parameters for SERCOM0 peripheral ========== */
mbed_official 579:53297373a894 140 #define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger
mbed_official 579:53297373a894 141 #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
mbed_official 579:53297373a894 142 #define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
mbed_official 579:53297373a894 143 #define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
mbed_official 579:53297373a894 144 #define SERCOM0_INT_MSB 6
mbed_official 579:53297373a894 145
mbed_official 579:53297373a894 146 #endif /* _SAMD21_SERCOM0_INSTANCE_ */