Flotsam
Modified version of the mbed library for use with the Nucleo boards.
Dependents: EEPROMWrite Full-Project
Fork of
mbed-src
by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h
- Revision:
- 630:825f75ca301e
- Parent:
- 441:d2c15dda23c1
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -37,7 +37,7 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_RCC_EX_H
-#define __STM32F0xx_HAL_RCC_EX_H
+#define __HAL_RCC_STM32F0xx_HAL_RCC_EX_H
#ifdef __cplusplus
extern "C" {
@@ -50,10 +50,363 @@
* @{
*/
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
+
+#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
+#else
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\
+ || defined(STM32F070xB) || defined(STM32F030xC)
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14))
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14))
+
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI48))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Constants
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup RCC_PLL_Clock_Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
+#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Oscillator_Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Interrupt
+ * @{
+ */
+#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Flag
+ * @{
+ */
+#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_System_Clock_Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_System_Clock_Source_Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
+/**
+ * @}
+ */
+
+#else
+/** @addtogroup RCC_PLL_Clock_Source
+ * @{
+ */
+
+#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
+#else
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/** @addtogroup RCC_MCO_Clock_Source
+ * @{
+ */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\
+ || defined(STM32F070xB) || defined(STM32F030xC)
+
+#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
+#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/** @addtogroup RCCEx
* @{
*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F030xC)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_RTC))
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
+ STM32F030xC */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
+#endif /* STM32F070x6 || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F042x6 || STM32F048xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
+#endif /* STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC))
+#endif /* STM32F071xB */
+
+#if defined(STM32F072xB) || defined(STM32F078xx)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
+#endif /* STM32F072xB || STM32F078xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
+#endif /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
+ ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
+
+#endif /* STM32F070x6 || STM32F070xB */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+#endif /* STM32F091xC || STM32F098xx */
+
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
+
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB)\
+ || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
+ ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
+ ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
+ ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+ ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
+ ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
+#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
+#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
+ ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
+#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
+#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
+#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
+#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
+ ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
@@ -63,8 +416,8 @@
/**
* @brief RCC extended clocks structure definition
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F030xC)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
@@ -228,9 +581,9 @@
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief RCC_CRS Init structure definition
@@ -294,13 +647,22 @@
* @{
*/
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
+ * @{
+ */
+#define RCC_HSI48_OFF ((uint8_t)0x00)
+#define RCC_HSI48_ON ((uint8_t)0x01)
+
+/**
+ * @}
+ */
+
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
#define RCC_CRS_NONE ((uint32_t)0x00000000)
#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
@@ -309,24 +671,33 @@
#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
-#endif /* STM32F042x6 || STM32F048xx */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
/**
* @}
*/
+#else
+
+/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
+ * @{
+ */
+#define RCC_HSI48_OFF ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F030xC)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_RTC))
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
STM32F030xC */
@@ -336,8 +707,6 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx)
@@ -347,9 +716,6 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB))
#endif /* STM32F042x6 || STM32F048xx */
#if defined(STM32F051x8) || defined(STM32F058xx)
@@ -358,8 +724,6 @@
#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
#endif /* STM32F051x8 || STM32F058xx */
#if defined(STM32F071xB)
@@ -369,9 +733,6 @@
#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
- RCC_PERIPHCLK_RTC))
#endif /* STM32F071xB */
#if defined(STM32F072xB) || defined(STM32F078xx)
@@ -382,9 +743,6 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
#endif /* STM32F072xB || STM32F078xx */
#if defined(STM32F091xC) || defined(STM32F098xx)
@@ -395,80 +753,12 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
#endif /* STM32F091xC || STM32F098xx */
/**
* @}
*/
-/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
- * @{
- */
-
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030xC)
-
-#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
-
-#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
- ((SOURCE) == RCC_MCOSOURCE_LSI) || \
- ((SOURCE) == RCC_MCOSOURCE_LSE) || \
- ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI) || \
- ((SOURCE) == RCC_MCOSOURCE_HSE) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI14))
-
-#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
-
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
-
-#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
- ((SOURCE) == RCC_MCOSOURCE_LSI) || \
- ((SOURCE) == RCC_MCOSOURCE_LSE) || \
- ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI) || \
- ((SOURCE) == RCC_MCOSOURCE_HSE) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI14))
-
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
-#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
-#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
-
-#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
- ((SOURCE) == RCC_MCOSOURCE_LSI) || \
- ((SOURCE) == RCC_MCOSOURCE_LSE) || \
- ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI) || \
- ((SOURCE) == RCC_MCOSOURCE_HSE) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI48))
-
-#define RCC_IT_HSI48 ((uint8_t)0x40)
-
-/* Flags in the CR2 register */
-#define RCC_CR2_HSI48RDY_BitNumber 16
-
-#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
-
-#endif /* STM32F042x6 || STM32F048xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-/**
- * @}
- */
-
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
@@ -477,8 +767,6 @@
#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
-#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
- ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
/**
* @}
*/
@@ -492,15 +780,14 @@
*/
#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
-#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
/**
* @}
*/
#endif /* STM32F070x6 || STM32F070xB */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
* @{
@@ -510,10 +797,6 @@
#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
-#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
/**
* @}
*/
@@ -531,10 +814,6 @@
#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
-#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
/**
* @}
*/
@@ -542,10 +821,10 @@
#endif /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
* @{
@@ -553,8 +832,6 @@
#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
-#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_CECCLKSOURCE_LSE))
/**
* @}
*/
@@ -564,115 +841,20 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
-/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
- * @{
- */
-#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
-#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
- ((SOURCE) == RCC_PLLSOURCE_HSE))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
-
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
-
-#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
-
-#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
- * @{
- */
-#define RCC_HSI48_OFF ((uint8_t)0x00)
-#define RCC_HSI48_ON ((uint8_t)0x01)
-
-#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
-/**
- * @}
- */
-#else
-/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
- * @{
- */
-
-#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
-#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
-#else
-#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
-#endif
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_HSE))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
- * @{
- */
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
-
-#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
- * @{
- */
-#define RCC_HSI48_OFF ((uint8_t)0x00)
-
-#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
-/**
- * @}
- */
-
-#endif /* STM32F042x6 || STM32F048xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-
-
/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
* @{
*/
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
-#define RCC_MCO_NODIV ((uint32_t)0x00000000)
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB) || \
- defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB)\
+ || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
@@ -683,11 +865,6 @@
#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
- ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
- ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
- ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
-
#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
/* STM32F091xC || STM32F098xx || STM32F030xC */
@@ -696,9 +873,9 @@
* @}
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
* @{
@@ -707,9 +884,6 @@
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
-#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
- ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
- ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
/**
* @}
*/
@@ -726,10 +900,6 @@
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
/**
* @}
*/
@@ -740,8 +910,6 @@
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
- ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
/**
* @}
*/
@@ -752,7 +920,6 @@
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
-#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
/**
* @}
*/
@@ -762,7 +929,6 @@
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
-#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
/**
* @}
*/
@@ -774,7 +940,6 @@
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
-#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
/**
* @}
*/
@@ -785,8 +950,6 @@
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
-#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
- ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
/**
* @}
*/
@@ -841,38 +1004,56 @@
* using it.
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F030x8)\
+ || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
#endif /* STM32F030x6 || STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || STM32F070xB || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
+#define __HAL_RCC_TSC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
+#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
@@ -881,9 +1062,15 @@
#if defined(STM32F091xC) || defined(STM32F098xx)
-#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
#endif /* STM32F091xC || STM32F098xx */
@@ -892,32 +1079,63 @@
* is disabled and the application software has to enable this clock before
* using it.
*/
-#if defined(STM32F030x8) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || STM32F070x6 || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
-#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#if defined(STM32F030x8)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#endif /* STM32F031x6 || STM32F038xx || */
/* STM32F042x6 || STM32F048xx || */
@@ -925,88 +1143,148 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) \
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#endif /* STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#endif /* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
-#define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
-#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
+#define __HAL_RCC_USB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
+#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F072xB || STM32F078xx || STM32F070xB */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
-#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
+#define __HAL_RCC_CRS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
+#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
@@ -1014,9 +1292,15 @@
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_USART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
@@ -1025,14 +1309,20 @@
* is disabled and the application software has to enable this clock before
* using it.
*/
-#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
@@ -1041,19 +1331,37 @@
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F091xC) || defined(STM32F098xx)
-#define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
-#define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
+#define __HAL_RCC_USART7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
-#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
+#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
+#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
#endif /* STM32F091xC || STM32F098xx */
@@ -1069,38 +1377,38 @@
/** @brief Force or release AHB peripheral reset.
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F030x8)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
-#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
#endif /* STM32F030x6 || STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
-#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
-#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
@@ -1109,32 +1417,32 @@
/** @brief Force or release APB1 peripheral reset.
*/
-#if defined(STM32F030x8) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) \
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#endif /* STM32F031x6 || STM32F038xx || */
/* STM32F042x6 || STM32F048xx || */
@@ -1142,89 +1450,89 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) ||\
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) \
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#endif /* STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#endif /* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
-#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
-#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F072xB || STM32F078xx || STM32F070xB */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
-#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
+#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
-#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
+#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
@@ -1232,23 +1540,23 @@
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
-#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
/** @brief Force or release APB2 peripheral reset.
*/
-#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
-#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
@@ -1257,25 +1565,244 @@
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
-#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F091xC) || defined(STM32F098xx)
-#define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
-#define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
+#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
+#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
-#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
-#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
+#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
+#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
#endif /* STM32F091xC || STM32F098xx */
/**
* @}
*/
+
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+/** @brief AHB Peripheral Clock Enable Disable Status
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8)\
+ || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
+
+#endif /* STM32F030x6 || STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || STM32F070xB || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
+#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
+
+#endif /* STM32F091xC || STM32F098xx */
+
+/** @brief APB1 Peripheral Clock Enable Disable Status
+ */
+#if defined(STM32F030x8)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || STM32F070x6 || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F030x8)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+
+#endif /* STM32F031x6 || STM32F038xx || */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030x8) \
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+
+#endif /* STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
+
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+
+#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
+#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F072xB || STM32F078xx || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
+#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
+#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+/** @brief APB1 Peripheral Clock Enable Disable Status
+ */
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
+#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
+#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
+#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
+
+#endif /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
@@ -1289,9 +1816,9 @@
* clock cycles.
* @{
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
@@ -1323,9 +1850,9 @@
/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
* @{
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F070x6) || defined(STM32F070xB)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F070x6) || defined(STM32F070xB)
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSource__: specifies the USB clock source.
@@ -1338,7 +1865,7 @@
/** @brief Macro to get the USB clock source.
* @retval The clock source can be one of the following values:
- * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
+ * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
*/
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
@@ -1347,10 +1874,10 @@
/* STM32F072xB || STM32F078xx || */
/* STM32F070x6 || STM32F070xB */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @brief Macro to configure the CEC clock.
* @param __CECCLKSource__: specifies the CEC clock source.
@@ -1373,10 +1900,10 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || defined(STM32F098xx) */
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSource__: specifies the MCO clock source.
@@ -1418,7 +1945,7 @@
* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
* @param __MCODiv__: specifies the MCO clock prescaler.
* This parameter can be one of the following values:
- * @arg RCC_MCO_NODIV: No division applied on MCO clock source
+ * @arg RCC_MCODIV_1: No division applied on MCO clock source
*/
#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
@@ -1428,8 +1955,8 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @brief Macro to configure the USART2 clock (USART2CLK).
* @param __USART2CLKSource__: specifies the USART2 clock source.
* This parameter can be one of the following values:
@@ -1477,9 +2004,9 @@
* @}
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
* @{
@@ -1642,10 +2169,11 @@
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);