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Modified version of the mbed library for use with the Nucleo boards.

Dependents: EEPROMWrite Full-Project

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

Committer:: mbed_official
Date:: Thu Aug 20 10:45:13 2015 +0100
Revision:: 613:bc40b8d2aec4
Parent:: 532:fe11edbda85c

Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade

Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/

Nordic: update application start address in GCC linker script

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User	Revision	Line number	New contents of line
mbed_official	235:685d5f11838f	1	/**
mbed_official	235:685d5f11838f	2	******************************************************************************
mbed_official	235:685d5f11838f	3	* @file stm32f4xx_ll_fmc.h
mbed_official	235:685d5f11838f	4	* @author MCD Application Team
mbed_official	613:bc40b8d2aec4	5	* @version V1.3.2
mbed_official	613:bc40b8d2aec4	6	* @date 26-June-2015
mbed_official	235:685d5f11838f	7	* @brief Header file of FMC HAL module.
mbed_official	235:685d5f11838f	8	******************************************************************************
mbed_official	235:685d5f11838f	9	* @attention
mbed_official	235:685d5f11838f	10	*
mbed_official	532:fe11edbda85c	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	235:685d5f11838f	12	*
mbed_official	235:685d5f11838f	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	235:685d5f11838f	14	* are permitted provided that the following conditions are met:
mbed_official	235:685d5f11838f	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	235:685d5f11838f	16	* this list of conditions and the following disclaimer.
mbed_official	235:685d5f11838f	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	235:685d5f11838f	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	235:685d5f11838f	19	* and/or other materials provided with the distribution.
mbed_official	235:685d5f11838f	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	235:685d5f11838f	21	* may be used to endorse or promote products derived from this software
mbed_official	235:685d5f11838f	22	* without specific prior written permission.
mbed_official	235:685d5f11838f	23	*
mbed_official	235:685d5f11838f	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	235:685d5f11838f	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	235:685d5f11838f	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	235:685d5f11838f	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	235:685d5f11838f	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	235:685d5f11838f	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	235:685d5f11838f	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	235:685d5f11838f	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	235:685d5f11838f	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	235:685d5f11838f	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	235:685d5f11838f	34	*
mbed_official	235:685d5f11838f	35	******************************************************************************
mbed_official	235:685d5f11838f	36	*/
mbed_official	235:685d5f11838f	37
mbed_official	235:685d5f11838f	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	235:685d5f11838f	39	#ifndef __STM32F4xx_LL_FMC_H
mbed_official	235:685d5f11838f	40	#define __STM32F4xx_LL_FMC_H
mbed_official	235:685d5f11838f	41
mbed_official	235:685d5f11838f	42	#ifdef __cplusplus
mbed_official	235:685d5f11838f	43	extern "C" {
mbed_official	235:685d5f11838f	44	#endif
mbed_official	235:685d5f11838f	45
mbed_official	235:685d5f11838f	46	/* Includes ------------------------------------------------------------------*/
mbed_official	235:685d5f11838f	47	#include "stm32f4xx_hal_def.h"
mbed_official	235:685d5f11838f	48
mbed_official	235:685d5f11838f	49	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	235:685d5f11838f	50	* @{
mbed_official	235:685d5f11838f	51	*/
mbed_official	532:fe11edbda85c	52
mbed_official	532:fe11edbda85c	53	/** @addtogroup FMC_LL
mbed_official	235:685d5f11838f	54	* @{
mbed_official	235:685d5f11838f	55	*/
mbed_official	532:fe11edbda85c	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
mbed_official	532:fe11edbda85c	57	/* Private types -------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	58	/** @defgroup FMC_LL_Private_Types FMC Private Types
mbed_official	532:fe11edbda85c	59	* @{
mbed_official	532:fe11edbda85c	60	*/
mbed_official	235:685d5f11838f	61
mbed_official	235:685d5f11838f	62	/**
mbed_official	532:fe11edbda85c	63	* @brief FMC NORSRAM Configuration Structure definition
mbed_official	235:685d5f11838f	64	*/
mbed_official	235:685d5f11838f	65	typedef struct
mbed_official	235:685d5f11838f	66	{
mbed_official	235:685d5f11838f	67	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
mbed_official	235:685d5f11838f	68	This parameter can be a value of @ref FMC_NORSRAM_Bank */
mbed_official	235:685d5f11838f	69
mbed_official	235:685d5f11838f	70	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official	235:685d5f11838f	71	multiplexed on the data bus or not.
mbed_official	235:685d5f11838f	72	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
mbed_official	235:685d5f11838f	73
mbed_official	235:685d5f11838f	74	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
mbed_official	235:685d5f11838f	75	the corresponding memory device.
mbed_official	235:685d5f11838f	76	This parameter can be a value of @ref FMC_Memory_Type */
mbed_official	235:685d5f11838f	77
mbed_official	235:685d5f11838f	78	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	235:685d5f11838f	79	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
mbed_official	235:685d5f11838f	80
mbed_official	235:685d5f11838f	81	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official	235:685d5f11838f	82	valid only with synchronous burst Flash memories.
mbed_official	235:685d5f11838f	83	This parameter can be a value of @ref FMC_Burst_Access_Mode */
mbed_official	235:685d5f11838f	84
mbed_official	235:685d5f11838f	85	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official	235:685d5f11838f	86	the Flash memory in burst mode.
mbed_official	235:685d5f11838f	87	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
mbed_official	235:685d5f11838f	88
mbed_official	235:685d5f11838f	89	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official	235:685d5f11838f	90	memory, valid only when accessing Flash memories in burst mode.
mbed_official	532:fe11edbda85c	91	This parameter can be a value of @ref FMC_Wrap_Mode
mbed_official	532:fe11edbda85c	92	This mode is not available for the STM32F446xx devices */
mbed_official	235:685d5f11838f	93
mbed_official	235:685d5f11838f	94	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official	235:685d5f11838f	95	clock cycle before the wait state or during the wait state,
mbed_official	235:685d5f11838f	96	valid only when accessing memories in burst mode.
mbed_official	235:685d5f11838f	97	This parameter can be a value of @ref FMC_Wait_Timing */
mbed_official	235:685d5f11838f	98
mbed_official	235:685d5f11838f	99	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
mbed_official	235:685d5f11838f	100	This parameter can be a value of @ref FMC_Write_Operation */
mbed_official	235:685d5f11838f	101
mbed_official	235:685d5f11838f	102	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
mbed_official	235:685d5f11838f	103	signal, valid for Flash memory access in burst mode.
mbed_official	235:685d5f11838f	104	This parameter can be a value of @ref FMC_Wait_Signal */
mbed_official	235:685d5f11838f	105
mbed_official	235:685d5f11838f	106	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official	235:685d5f11838f	107	This parameter can be a value of @ref FMC_Extended_Mode */
mbed_official	235:685d5f11838f	108
mbed_official	235:685d5f11838f	109	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official	235:685d5f11838f	110	valid only with asynchronous Flash memories.
mbed_official	235:685d5f11838f	111	This parameter can be a value of @ref FMC_AsynchronousWait */
mbed_official	235:685d5f11838f	112
mbed_official	235:685d5f11838f	113	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official	235:685d5f11838f	114	This parameter can be a value of @ref FMC_Write_Burst */
mbed_official	235:685d5f11838f	115
mbed_official	235:685d5f11838f	116	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
mbed_official	235:685d5f11838f	117	This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official	235:685d5f11838f	118	through FMC_BCR2..4 registers.
mbed_official	235:685d5f11838f	119	This parameter can be a value of @ref FMC_Continous_Clock */
mbed_official	235:685d5f11838f	120
mbed_official	532:fe11edbda85c	121	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
mbed_official	532:fe11edbda85c	122	This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official	532:fe11edbda85c	123	through FMC_BCR2..4 registers.
mbed_official	532:fe11edbda85c	124	This parameter can be a value of @ref FMC_Write_FIFO
mbed_official	532:fe11edbda85c	125	This mode is available only for the STM32F446xx devices */
mbed_official	532:fe11edbda85c	126
mbed_official	532:fe11edbda85c	127	uint32_t PageSize; /*!< Specifies the memory page size.
mbed_official	532:fe11edbda85c	128	This parameter can be a value of @ref FMC_Page_Size
mbed_official	532:fe11edbda85c	129	This mode is available only for the STM32F446xx devices */
mbed_official	532:fe11edbda85c	130
mbed_official	235:685d5f11838f	131	}FMC_NORSRAM_InitTypeDef;
mbed_official	235:685d5f11838f	132
mbed_official	235:685d5f11838f	133	/**
mbed_official	532:fe11edbda85c	134	* @brief FMC NORSRAM Timing parameters structure definition
mbed_official	235:685d5f11838f	135	*/
mbed_official	235:685d5f11838f	136	typedef struct
mbed_official	235:685d5f11838f	137	{
mbed_official	235:685d5f11838f	138	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	235:685d5f11838f	139	the duration of the address setup time.
mbed_official	235:685d5f11838f	140	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	235:685d5f11838f	141	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	235:685d5f11838f	142
mbed_official	235:685d5f11838f	143	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	235:685d5f11838f	144	the duration of the address hold time.
mbed_official	235:685d5f11838f	145	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
mbed_official	235:685d5f11838f	146	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	235:685d5f11838f	147
mbed_official	235:685d5f11838f	148	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	235:685d5f11838f	149	the duration of the data setup time.
mbed_official	235:685d5f11838f	150	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
mbed_official	235:685d5f11838f	151	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
mbed_official	235:685d5f11838f	152	NOR Flash memories. */
mbed_official	235:685d5f11838f	153
mbed_official	235:685d5f11838f	154	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official	235:685d5f11838f	155	the duration of the bus turnaround.
mbed_official	235:685d5f11838f	156	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	235:685d5f11838f	157	@note This parameter is only used for multiplexed NOR Flash memories. */
mbed_official	235:685d5f11838f	158
mbed_official	235:685d5f11838f	159	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
mbed_official	235:685d5f11838f	160	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
mbed_official	235:685d5f11838f	161	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
mbed_official	235:685d5f11838f	162	accesses. */
mbed_official	235:685d5f11838f	163
mbed_official	235:685d5f11838f	164	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official	235:685d5f11838f	165	to the memory before getting the first data.
mbed_official	235:685d5f11838f	166	The parameter value depends on the memory type as shown below:
mbed_official	235:685d5f11838f	167	- It must be set to 0 in case of a CRAM
mbed_official	235:685d5f11838f	168	- It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official	235:685d5f11838f	169	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
mbed_official	235:685d5f11838f	170	with synchronous burst mode enable */
mbed_official	235:685d5f11838f	171
mbed_official	235:685d5f11838f	172	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official	235:685d5f11838f	173	This parameter can be a value of @ref FMC_Access_Mode */
mbed_official	235:685d5f11838f	174	}FMC_NORSRAM_TimingTypeDef;
mbed_official	235:685d5f11838f	175
mbed_official	235:685d5f11838f	176	/**
mbed_official	532:fe11edbda85c	177	* @brief FMC NAND Configuration Structure definition
mbed_official	235:685d5f11838f	178	*/
mbed_official	235:685d5f11838f	179	typedef struct
mbed_official	235:685d5f11838f	180	{
mbed_official	235:685d5f11838f	181	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
mbed_official	235:685d5f11838f	182	This parameter can be a value of @ref FMC_NAND_Bank */
mbed_official	235:685d5f11838f	183
mbed_official	235:685d5f11838f	184	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
mbed_official	235:685d5f11838f	185	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	235:685d5f11838f	186
mbed_official	235:685d5f11838f	187	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	235:685d5f11838f	188	This parameter can be any value of @ref FMC_NAND_Data_Width */
mbed_official	235:685d5f11838f	189
mbed_official	235:685d5f11838f	190	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
mbed_official	235:685d5f11838f	191	This parameter can be any value of @ref FMC_ECC */
mbed_official	235:685d5f11838f	192
mbed_official	235:685d5f11838f	193	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official	235:685d5f11838f	194	This parameter can be any value of @ref FMC_ECC_Page_Size */
mbed_official	235:685d5f11838f	195
mbed_official	235:685d5f11838f	196	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	235:685d5f11838f	197	delay between CLE low and RE low.
mbed_official	235:685d5f11838f	198	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	199
mbed_official	235:685d5f11838f	200	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	235:685d5f11838f	201	delay between ALE low and RE low.
mbed_official	235:685d5f11838f	202	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	203	}FMC_NAND_InitTypeDef;
mbed_official	235:685d5f11838f	204
mbed_official	235:685d5f11838f	205	/**
mbed_official	532:fe11edbda85c	206	* @brief FMC NAND/PCCARD Timing parameters structure definition
mbed_official	235:685d5f11838f	207	*/
mbed_official	235:685d5f11838f	208	typedef struct
mbed_official	235:685d5f11838f	209	{
mbed_official	235:685d5f11838f	210	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official	235:685d5f11838f	211	the command assertion for NAND-Flash read or write access
mbed_official	235:685d5f11838f	212	to common/Attribute or I/O memory space (depending on
mbed_official	235:685d5f11838f	213	the memory space timing to be configured).
mbed_official	235:685d5f11838f	214	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	215
mbed_official	235:685d5f11838f	216	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official	235:685d5f11838f	217	command for NAND-Flash read or write access to
mbed_official	235:685d5f11838f	218	common/Attribute or I/O memory space (depending on the
mbed_official	235:685d5f11838f	219	memory space timing to be configured).
mbed_official	235:685d5f11838f	220	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	221
mbed_official	235:685d5f11838f	222	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official	235:685d5f11838f	223	(and data for write access) after the command de-assertion
mbed_official	235:685d5f11838f	224	for NAND-Flash read or write access to common/Attribute
mbed_official	235:685d5f11838f	225	or I/O memory space (depending on the memory space timing
mbed_official	235:685d5f11838f	226	to be configured).
mbed_official	235:685d5f11838f	227	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	228
mbed_official	235:685d5f11838f	229	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official	235:685d5f11838f	230	data bus is kept in HiZ after the start of a NAND-Flash
mbed_official	235:685d5f11838f	231	write access to common/Attribute or I/O memory space (depending
mbed_official	235:685d5f11838f	232	on the memory space timing to be configured).
mbed_official	235:685d5f11838f	233	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	234	}FMC_NAND_PCC_TimingTypeDef;
mbed_official	235:685d5f11838f	235
mbed_official	235:685d5f11838f	236	/**
mbed_official	532:fe11edbda85c	237	* @brief FMC NAND Configuration Structure definition
mbed_official	235:685d5f11838f	238	*/
mbed_official	235:685d5f11838f	239	typedef struct
mbed_official	235:685d5f11838f	240	{
mbed_official	235:685d5f11838f	241	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
mbed_official	235:685d5f11838f	242	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	235:685d5f11838f	243
mbed_official	235:685d5f11838f	244	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	235:685d5f11838f	245	delay between CLE low and RE low.
mbed_official	235:685d5f11838f	246	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	247
mbed_official	235:685d5f11838f	248	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	235:685d5f11838f	249	delay between ALE low and RE low.
mbed_official	235:685d5f11838f	250	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	251	}FMC_PCCARD_InitTypeDef;
mbed_official	235:685d5f11838f	252
mbed_official	235:685d5f11838f	253	/**
mbed_official	532:fe11edbda85c	254	* @brief FMC SDRAM Configuration Structure definition
mbed_official	235:685d5f11838f	255	*/
mbed_official	235:685d5f11838f	256	typedef struct
mbed_official	235:685d5f11838f	257	{
mbed_official	235:685d5f11838f	258	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
mbed_official	235:685d5f11838f	259	This parameter can be a value of @ref FMC_SDRAM_Bank */
mbed_official	235:685d5f11838f	260
mbed_official	235:685d5f11838f	261	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	235:685d5f11838f	262	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
mbed_official	235:685d5f11838f	263
mbed_official	235:685d5f11838f	264	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	235:685d5f11838f	265	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
mbed_official	235:685d5f11838f	266
mbed_official	235:685d5f11838f	267	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
mbed_official	235:685d5f11838f	268	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
mbed_official	235:685d5f11838f	269
mbed_official	235:685d5f11838f	270	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
mbed_official	235:685d5f11838f	271	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
mbed_official	235:685d5f11838f	272
mbed_official	235:685d5f11838f	273	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
mbed_official	235:685d5f11838f	274	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
mbed_official	235:685d5f11838f	275
mbed_official	235:685d5f11838f	276	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
mbed_official	235:685d5f11838f	277	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
mbed_official	235:685d5f11838f	278
mbed_official	235:685d5f11838f	279	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
mbed_official	235:685d5f11838f	280	to disable the clock before changing frequency.
mbed_official	235:685d5f11838f	281	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
mbed_official	235:685d5f11838f	282
mbed_official	235:685d5f11838f	283	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
mbed_official	235:685d5f11838f	284	commands during the CAS latency and stores data in the Read FIFO.
mbed_official	235:685d5f11838f	285	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
mbed_official	235:685d5f11838f	286
mbed_official	235:685d5f11838f	287	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
mbed_official	235:685d5f11838f	288	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
mbed_official	235:685d5f11838f	289	}FMC_SDRAM_InitTypeDef;
mbed_official	235:685d5f11838f	290
mbed_official	235:685d5f11838f	291	/**
mbed_official	532:fe11edbda85c	292	* @brief FMC SDRAM Timing parameters structure definition
mbed_official	235:685d5f11838f	293	*/
mbed_official	235:685d5f11838f	294	typedef struct
mbed_official	235:685d5f11838f	295	{
mbed_official	235:685d5f11838f	296	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
mbed_official	235:685d5f11838f	297	an active or Refresh command in number of memory clock cycles.
mbed_official	235:685d5f11838f	298	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	299
mbed_official	235:685d5f11838f	300	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
mbed_official	235:685d5f11838f	301	issuing the Activate command in number of memory clock cycles.
mbed_official	235:685d5f11838f	302	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	303
mbed_official	235:685d5f11838f	304	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
mbed_official	235:685d5f11838f	305	cycles.
mbed_official	235:685d5f11838f	306	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	307
mbed_official	235:685d5f11838f	308	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
mbed_official	235:685d5f11838f	309	and the delay between two consecutive Refresh commands in number of
mbed_official	235:685d5f11838f	310	memory clock cycles.
mbed_official	235:685d5f11838f	311	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	312
mbed_official	235:685d5f11838f	313	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
mbed_official	235:685d5f11838f	314	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	315
mbed_official	235:685d5f11838f	316	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
mbed_official	235:685d5f11838f	317	in number of memory clock cycles.
mbed_official	235:685d5f11838f	318	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	319
mbed_official	235:685d5f11838f	320	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
mbed_official	235:685d5f11838f	321	command in number of memory clock cycles.
mbed_official	235:685d5f11838f	322	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	323	}FMC_SDRAM_TimingTypeDef;
mbed_official	235:685d5f11838f	324
mbed_official	235:685d5f11838f	325	/**
mbed_official	532:fe11edbda85c	326	* @brief SDRAM command parameters structure definition
mbed_official	235:685d5f11838f	327	*/
mbed_official	235:685d5f11838f	328	typedef struct
mbed_official	235:685d5f11838f	329	{
mbed_official	235:685d5f11838f	330	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
mbed_official	235:685d5f11838f	331	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
mbed_official	235:685d5f11838f	332
mbed_official	235:685d5f11838f	333	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
mbed_official	235:685d5f11838f	334	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
mbed_official	235:685d5f11838f	335
mbed_official	235:685d5f11838f	336	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
mbed_official	235:685d5f11838f	337	in auto refresh mode.
mbed_official	235:685d5f11838f	338	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	339	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
mbed_official	235:685d5f11838f	340	}FMC_SDRAM_CommandTypeDef;
mbed_official	532:fe11edbda85c	341	/**
mbed_official	532:fe11edbda85c	342	* @}
mbed_official	532:fe11edbda85c	343	*/
mbed_official	235:685d5f11838f	344
mbed_official	532:fe11edbda85c	345	/* Private constants ---------------------------------------------------------*/
mbed_official	532:fe11edbda85c	346	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
mbed_official	235:685d5f11838f	347	* @{
mbed_official	235:685d5f11838f	348	*/
mbed_official	235:685d5f11838f	349
mbed_official	532:fe11edbda85c	350	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
mbed_official	532:fe11edbda85c	351	* @{
mbed_official	532:fe11edbda85c	352	*/
mbed_official	532:fe11edbda85c	353	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
mbed_official	235:685d5f11838f	354	* @{
mbed_official	235:685d5f11838f	355	*/
mbed_official	235:685d5f11838f	356	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	357	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	358	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	359	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
mbed_official	235:685d5f11838f	360	/**
mbed_official	235:685d5f11838f	361	* @}
mbed_official	235:685d5f11838f	362	*/
mbed_official	235:685d5f11838f	363
mbed_official	532:fe11edbda85c	364	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
mbed_official	235:685d5f11838f	365	* @{
mbed_official	235:685d5f11838f	366	*/
mbed_official	235:685d5f11838f	367	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	368	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	369	/**
mbed_official	235:685d5f11838f	370	* @}
mbed_official	235:685d5f11838f	371	*/
mbed_official	235:685d5f11838f	372
mbed_official	532:fe11edbda85c	373	/** @defgroup FMC_Memory_Type FMC Memory Type
mbed_official	235:685d5f11838f	374	* @{
mbed_official	235:685d5f11838f	375	*/
mbed_official	235:685d5f11838f	376	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	377	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	378	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	379	/**
mbed_official	235:685d5f11838f	380	* @}
mbed_official	235:685d5f11838f	381	*/
mbed_official	235:685d5f11838f	382
mbed_official	532:fe11edbda85c	383	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
mbed_official	235:685d5f11838f	384	* @{
mbed_official	235:685d5f11838f	385	*/
mbed_official	235:685d5f11838f	386	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	388	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	235:685d5f11838f	389	/**
mbed_official	235:685d5f11838f	390	* @}
mbed_official	235:685d5f11838f	391	*/
mbed_official	235:685d5f11838f	392
mbed_official	532:fe11edbda85c	393	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
mbed_official	235:685d5f11838f	394	* @{
mbed_official	235:685d5f11838f	395	*/
mbed_official	235:685d5f11838f	396	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	397	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	398	/**
mbed_official	235:685d5f11838f	399	* @}
mbed_official	235:685d5f11838f	400	*/
mbed_official	235:685d5f11838f	401
mbed_official	532:fe11edbda85c	402	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
mbed_official	235:685d5f11838f	403	* @{
mbed_official	235:685d5f11838f	404	*/
mbed_official	235:685d5f11838f	405	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	406	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
mbed_official	235:685d5f11838f	407	/**
mbed_official	235:685d5f11838f	408	* @}
mbed_official	235:685d5f11838f	409	*/
mbed_official	235:685d5f11838f	410
mbed_official	532:fe11edbda85c	411	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
mbed_official	235:685d5f11838f	412	* @{
mbed_official	235:685d5f11838f	413	*/
mbed_official	235:685d5f11838f	414	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	415	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
mbed_official	235:685d5f11838f	416	/**
mbed_official	235:685d5f11838f	417	* @}
mbed_official	235:685d5f11838f	418	*/
mbed_official	235:685d5f11838f	419
mbed_official	532:fe11edbda85c	420	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
mbed_official	235:685d5f11838f	421	* @{
mbed_official	235:685d5f11838f	422	*/
mbed_official	532:fe11edbda85c	423	/** @note This mode is not available for the STM32F446xx devices
mbed_official	532:fe11edbda85c	424	*/
mbed_official	532:fe11edbda85c	425	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	426	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
mbed_official	235:685d5f11838f	427	/**
mbed_official	235:685d5f11838f	428	* @}
mbed_official	235:685d5f11838f	429	*/
mbed_official	235:685d5f11838f	430
mbed_official	532:fe11edbda85c	431	/** @defgroup FMC_Wait_Timing FMC Wait Timing
mbed_official	532:fe11edbda85c	432	* @{
mbed_official	532:fe11edbda85c	433	*/
mbed_official	532:fe11edbda85c	434	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	435	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
mbed_official	532:fe11edbda85c	436	/**
mbed_official	532:fe11edbda85c	437	* @}
mbed_official	532:fe11edbda85c	438	*/
mbed_official	532:fe11edbda85c	439
mbed_official	532:fe11edbda85c	440	/** @defgroup FMC_Write_Operation FMC Write Operation
mbed_official	235:685d5f11838f	441	* @{
mbed_official	235:685d5f11838f	442	*/
mbed_official	235:685d5f11838f	443	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	444	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
mbed_official	235:685d5f11838f	445	/**
mbed_official	235:685d5f11838f	446	* @}
mbed_official	235:685d5f11838f	447	*/
mbed_official	235:685d5f11838f	448
mbed_official	532:fe11edbda85c	449	/** @defgroup FMC_Wait_Signal FMC Wait Signal
mbed_official	235:685d5f11838f	450	* @{
mbed_official	235:685d5f11838f	451	*/
mbed_official	235:685d5f11838f	452	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	453	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
mbed_official	235:685d5f11838f	454	/**
mbed_official	235:685d5f11838f	455	* @}
mbed_official	235:685d5f11838f	456	*/
mbed_official	235:685d5f11838f	457
mbed_official	532:fe11edbda85c	458	/** @defgroup FMC_Extended_Mode FMC Extended Mode
mbed_official	532:fe11edbda85c	459	* @{
mbed_official	532:fe11edbda85c	460	*/
mbed_official	532:fe11edbda85c	461	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	462	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
mbed_official	532:fe11edbda85c	463	/**
mbed_official	532:fe11edbda85c	464	* @}
mbed_official	532:fe11edbda85c	465	*/
mbed_official	532:fe11edbda85c	466
mbed_official	532:fe11edbda85c	467	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
mbed_official	235:685d5f11838f	468	* @{
mbed_official	235:685d5f11838f	469	*/
mbed_official	235:685d5f11838f	470	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	471	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
mbed_official	235:685d5f11838f	472	/**
mbed_official	235:685d5f11838f	473	* @}
mbed_official	235:685d5f11838f	474	*/
mbed_official	235:685d5f11838f	475
mbed_official	532:fe11edbda85c	476	/** @defgroup FMC_Page_Size FMC Page Size
mbed_official	532:fe11edbda85c	477	* @note These values are available only for the STM32F446xx devices.
mbed_official	532:fe11edbda85c	478	* @{
mbed_official	532:fe11edbda85c	479	*/
mbed_official	532:fe11edbda85c	480	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	481	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
mbed_official	532:fe11edbda85c	482	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
mbed_official	532:fe11edbda85c	483	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
mbed_official	532:fe11edbda85c	484	/**
mbed_official	532:fe11edbda85c	485	* @}
mbed_official	532:fe11edbda85c	486	*/
mbed_official	532:fe11edbda85c	487
mbed_official	532:fe11edbda85c	488	/** @defgroup FMC_Write_FIFO FMC Write FIFO
mbed_official	532:fe11edbda85c	489	* @note These values are available only for the STM32F446xx devices.
mbed_official	532:fe11edbda85c	490	* @{
mbed_official	532:fe11edbda85c	491	*/
mbed_official	532:fe11edbda85c	492	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	493	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
mbed_official	532:fe11edbda85c	494	/**
mbed_official	532:fe11edbda85c	495	* @}
mbed_official	532:fe11edbda85c	496	*/
mbed_official	532:fe11edbda85c	497
mbed_official	532:fe11edbda85c	498	/** @defgroup FMC_Write_Burst FMC Write Burst
mbed_official	235:685d5f11838f	499	* @{
mbed_official	235:685d5f11838f	500	*/
mbed_official	235:685d5f11838f	501	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	502	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
mbed_official	235:685d5f11838f	503	/**
mbed_official	235:685d5f11838f	504	* @}
mbed_official	235:685d5f11838f	505	*/
mbed_official	235:685d5f11838f	506
mbed_official	532:fe11edbda85c	507	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
mbed_official	235:685d5f11838f	508	* @{
mbed_official	235:685d5f11838f	509	*/
mbed_official	532:fe11edbda85c	510	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	511	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
mbed_official	235:685d5f11838f	512	/**
mbed_official	235:685d5f11838f	513	* @}
mbed_official	235:685d5f11838f	514	*/
mbed_official	532:fe11edbda85c	515
mbed_official	532:fe11edbda85c	516	/** @defgroup FMC_Access_Mode FMC Access Mode
mbed_official	235:685d5f11838f	517	* @{
mbed_official	235:685d5f11838f	518	*/
mbed_official	235:685d5f11838f	519	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	520	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
mbed_official	235:685d5f11838f	521	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
mbed_official	235:685d5f11838f	522	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
mbed_official	235:685d5f11838f	523	/**
mbed_official	235:685d5f11838f	524	* @}
mbed_official	235:685d5f11838f	525	*/
mbed_official	235:685d5f11838f	526
mbed_official	235:685d5f11838f	527	/**
mbed_official	235:685d5f11838f	528	* @}
mbed_official	532:fe11edbda85c	529	*/
mbed_official	235:685d5f11838f	530
mbed_official	532:fe11edbda85c	531	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
mbed_official	235:685d5f11838f	532	* @{
mbed_official	235:685d5f11838f	533	*/
mbed_official	532:fe11edbda85c	534	/** @defgroup FMC_NAND_Bank FMC NAND Bank
mbed_official	235:685d5f11838f	535	* @{
mbed_official	532:fe11edbda85c	536	*/
mbed_official	235:685d5f11838f	537	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
mbed_official	532:fe11edbda85c	538	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
mbed_official	235:685d5f11838f	539	/**
mbed_official	235:685d5f11838f	540	* @}
mbed_official	235:685d5f11838f	541	*/
mbed_official	235:685d5f11838f	542
mbed_official	532:fe11edbda85c	543	/** @defgroup FMC_Wait_feature FMC Wait feature
mbed_official	235:685d5f11838f	544	* @{
mbed_official	235:685d5f11838f	545	*/
mbed_official	235:685d5f11838f	546	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	547	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	548	/**
mbed_official	235:685d5f11838f	549	* @}
mbed_official	235:685d5f11838f	550	*/
mbed_official	235:685d5f11838f	551
mbed_official	532:fe11edbda85c	552	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
mbed_official	235:685d5f11838f	553	* @{
mbed_official	235:685d5f11838f	554	*/
mbed_official	235:685d5f11838f	555	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	556	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	557	/**
mbed_official	235:685d5f11838f	558	* @}
mbed_official	235:685d5f11838f	559	*/
mbed_official	235:685d5f11838f	560
mbed_official	532:fe11edbda85c	561	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
mbed_official	235:685d5f11838f	562	* @{
mbed_official	235:685d5f11838f	563	*/
mbed_official	235:685d5f11838f	564	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	565	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	566	/**
mbed_official	235:685d5f11838f	567	* @}
mbed_official	235:685d5f11838f	568	*/
mbed_official	235:685d5f11838f	569
mbed_official	532:fe11edbda85c	570	/** @defgroup FMC_ECC FMC ECC
mbed_official	235:685d5f11838f	571	* @{
mbed_official	235:685d5f11838f	572	*/
mbed_official	235:685d5f11838f	573	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	574	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	575	/**
mbed_official	235:685d5f11838f	576	* @}
mbed_official	235:685d5f11838f	577	*/
mbed_official	235:685d5f11838f	578
mbed_official	532:fe11edbda85c	579	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
mbed_official	235:685d5f11838f	580	* @{
mbed_official	235:685d5f11838f	581	*/
mbed_official	235:685d5f11838f	582	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	583	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
mbed_official	235:685d5f11838f	584	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
mbed_official	235:685d5f11838f	585	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
mbed_official	235:685d5f11838f	586	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
mbed_official	235:685d5f11838f	587	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
mbed_official	235:685d5f11838f	588	/**
mbed_official	235:685d5f11838f	589	* @}
mbed_official	235:685d5f11838f	590	*/
mbed_official	532:fe11edbda85c	591
mbed_official	235:685d5f11838f	592	/**
mbed_official	235:685d5f11838f	593	* @}
mbed_official	532:fe11edbda85c	594	*/
mbed_official	235:685d5f11838f	595
mbed_official	532:fe11edbda85c	596	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
mbed_official	235:685d5f11838f	597	* @{
mbed_official	235:685d5f11838f	598	*/
mbed_official	532:fe11edbda85c	599	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
mbed_official	235:685d5f11838f	600	* @{
mbed_official	235:685d5f11838f	601	*/
mbed_official	532:fe11edbda85c	602	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	603	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	604	/**
mbed_official	235:685d5f11838f	605	* @}
mbed_official	235:685d5f11838f	606	*/
mbed_official	235:685d5f11838f	607
mbed_official	532:fe11edbda85c	608	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
mbed_official	235:685d5f11838f	609	* @{
mbed_official	235:685d5f11838f	610	*/
mbed_official	235:685d5f11838f	611	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	612	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	613	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	614	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
mbed_official	235:685d5f11838f	615	/**
mbed_official	235:685d5f11838f	616	* @}
mbed_official	235:685d5f11838f	617	*/
mbed_official	235:685d5f11838f	618
mbed_official	532:fe11edbda85c	619	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
mbed_official	235:685d5f11838f	620	* @{
mbed_official	235:685d5f11838f	621	*/
mbed_official	235:685d5f11838f	622	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	623	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	624	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	625	/**
mbed_official	235:685d5f11838f	626	* @}
mbed_official	235:685d5f11838f	627	*/
mbed_official	235:685d5f11838f	628
mbed_official	532:fe11edbda85c	629	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
mbed_official	235:685d5f11838f	630	* @{
mbed_official	235:685d5f11838f	631	*/
mbed_official	235:685d5f11838f	632	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	633	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	634	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	235:685d5f11838f	635	/**
mbed_official	235:685d5f11838f	636	* @}
mbed_official	235:685d5f11838f	637	*/
mbed_official	235:685d5f11838f	638
mbed_official	532:fe11edbda85c	639	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
mbed_official	235:685d5f11838f	640	* @{
mbed_official	235:685d5f11838f	641	*/
mbed_official	235:685d5f11838f	642	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	643	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	644	/**
mbed_official	235:685d5f11838f	645	* @}
mbed_official	235:685d5f11838f	646	*/
mbed_official	235:685d5f11838f	647
mbed_official	532:fe11edbda85c	648	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
mbed_official	235:685d5f11838f	649	* @{
mbed_official	235:685d5f11838f	650	*/
mbed_official	235:685d5f11838f	651	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
mbed_official	235:685d5f11838f	652	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
mbed_official	235:685d5f11838f	653	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
mbed_official	235:685d5f11838f	654	/**
mbed_official	235:685d5f11838f	655	* @}
mbed_official	235:685d5f11838f	656	*/
mbed_official	235:685d5f11838f	657
mbed_official	532:fe11edbda85c	658	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
mbed_official	235:685d5f11838f	659	* @{
mbed_official	235:685d5f11838f	660	*/
mbed_official	235:685d5f11838f	661	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	662	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
mbed_official	235:685d5f11838f	663
mbed_official	235:685d5f11838f	664	/**
mbed_official	235:685d5f11838f	665	* @}
mbed_official	235:685d5f11838f	666	*/
mbed_official	235:685d5f11838f	667
mbed_official	532:fe11edbda85c	668	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
mbed_official	235:685d5f11838f	669	* @{
mbed_official	235:685d5f11838f	670	*/
mbed_official	235:685d5f11838f	671	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	672	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
mbed_official	235:685d5f11838f	673	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
mbed_official	235:685d5f11838f	674	/**
mbed_official	235:685d5f11838f	675	* @}
mbed_official	235:685d5f11838f	676	*/
mbed_official	235:685d5f11838f	677
mbed_official	532:fe11edbda85c	678	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
mbed_official	235:685d5f11838f	679	* @{
mbed_official	235:685d5f11838f	680	*/
mbed_official	235:685d5f11838f	681	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	682	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
mbed_official	235:685d5f11838f	683	/**
mbed_official	235:685d5f11838f	684	* @}
mbed_official	235:685d5f11838f	685	*/
mbed_official	235:685d5f11838f	686
mbed_official	532:fe11edbda85c	687	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
mbed_official	235:685d5f11838f	688	* @{
mbed_official	235:685d5f11838f	689	*/
mbed_official	235:685d5f11838f	690	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	691	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
mbed_official	235:685d5f11838f	692	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
mbed_official	235:685d5f11838f	693	/**
mbed_official	235:685d5f11838f	694	* @}
mbed_official	235:685d5f11838f	695	*/
mbed_official	235:685d5f11838f	696
mbed_official	532:fe11edbda85c	697	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
mbed_official	235:685d5f11838f	698	* @{
mbed_official	235:685d5f11838f	699	*/
mbed_official	235:685d5f11838f	700	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	701	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	702	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	703	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
mbed_official	235:685d5f11838f	704	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	705	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
mbed_official	235:685d5f11838f	706	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
mbed_official	235:685d5f11838f	707	/**
mbed_official	235:685d5f11838f	708	* @}
mbed_official	235:685d5f11838f	709	*/
mbed_official	235:685d5f11838f	710
mbed_official	532:fe11edbda85c	711	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
mbed_official	235:685d5f11838f	712	* @{
mbed_official	235:685d5f11838f	713	*/
mbed_official	235:685d5f11838f	714	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
mbed_official	235:685d5f11838f	715	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
mbed_official	235:685d5f11838f	716	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
mbed_official	235:685d5f11838f	717	/**
mbed_official	235:685d5f11838f	718	* @}
mbed_official	235:685d5f11838f	719	*/
mbed_official	235:685d5f11838f	720
mbed_official	532:fe11edbda85c	721	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
mbed_official	235:685d5f11838f	722	* @{
mbed_official	235:685d5f11838f	723	*/
mbed_official	235:685d5f11838f	724	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	725	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
mbed_official	235:685d5f11838f	726	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
mbed_official	235:685d5f11838f	727	/**
mbed_official	235:685d5f11838f	728	* @}
mbed_official	235:685d5f11838f	729	*/
mbed_official	532:fe11edbda85c	730
mbed_official	235:685d5f11838f	731	/**
mbed_official	235:685d5f11838f	732	* @}
mbed_official	235:685d5f11838f	733	*/
mbed_official	235:685d5f11838f	734
mbed_official	532:fe11edbda85c	735	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
mbed_official	235:685d5f11838f	736	* @{
mbed_official	235:685d5f11838f	737	*/
mbed_official	235:685d5f11838f	738	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	739	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	740	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
mbed_official	235:685d5f11838f	741	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
mbed_official	235:685d5f11838f	742	/**
mbed_official	235:685d5f11838f	743	* @}
mbed_official	235:685d5f11838f	744	*/
mbed_official	235:685d5f11838f	745
mbed_official	532:fe11edbda85c	746	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
mbed_official	235:685d5f11838f	747	* @{
mbed_official	235:685d5f11838f	748	*/
mbed_official	235:685d5f11838f	749	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	750	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	751	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	752	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	753	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
mbed_official	235:685d5f11838f	754	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
mbed_official	235:685d5f11838f	755	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
mbed_official	235:685d5f11838f	756	/**
mbed_official	235:685d5f11838f	757	* @}
mbed_official	235:685d5f11838f	758	*/
mbed_official	235:685d5f11838f	759
mbed_official	532:fe11edbda85c	760	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
mbed_official	532:fe11edbda85c	761	* @{
mbed_official	532:fe11edbda85c	762	*/
mbed_official	532:fe11edbda85c	763	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	764	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
mbed_official	532:fe11edbda85c	765	#else
mbed_official	532:fe11edbda85c	766	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
mbed_official	532:fe11edbda85c	767	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
mbed_official	532:fe11edbda85c	768	#endif /* defined(STM32F446xx) */
mbed_official	532:fe11edbda85c	769	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
mbed_official	532:fe11edbda85c	770	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
mbed_official	532:fe11edbda85c	771	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
mbed_official	532:fe11edbda85c	772
mbed_official	235:685d5f11838f	773
mbed_official	532:fe11edbda85c	774	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	775	#define FMC_NAND_DEVICE FMC_Bank3
mbed_official	532:fe11edbda85c	776	#else
mbed_official	532:fe11edbda85c	777	#define FMC_NAND_DEVICE FMC_Bank2_3
mbed_official	532:fe11edbda85c	778	#define FMC_PCCARD_DEVICE FMC_Bank4
mbed_official	532:fe11edbda85c	779	#endif /* defined(STM32F446xx) */
mbed_official	532:fe11edbda85c	780	#define FMC_NORSRAM_DEVICE FMC_Bank1
mbed_official	532:fe11edbda85c	781	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
mbed_official	532:fe11edbda85c	782	#define FMC_SDRAM_DEVICE FMC_Bank5_6
mbed_official	532:fe11edbda85c	783	/**
mbed_official	532:fe11edbda85c	784	* @}
mbed_official	532:fe11edbda85c	785	*/
mbed_official	532:fe11edbda85c	786
mbed_official	532:fe11edbda85c	787	/**
mbed_official	532:fe11edbda85c	788	* @}
mbed_official	532:fe11edbda85c	789	*/
mbed_official	532:fe11edbda85c	790
mbed_official	532:fe11edbda85c	791	/* Private macro -------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	792	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
mbed_official	532:fe11edbda85c	793	* @{
mbed_official	532:fe11edbda85c	794	*/
mbed_official	532:fe11edbda85c	795
mbed_official	532:fe11edbda85c	796	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
mbed_official	235:685d5f11838f	797	* @brief macros to handle NOR device enable/disable and read/write operations
mbed_official	235:685d5f11838f	798	* @{
mbed_official	235:685d5f11838f	799	*/
mbed_official	235:685d5f11838f	800	/**
mbed_official	235:685d5f11838f	801	* @brief Enable the NORSRAM device access.
mbed_official	235:685d5f11838f	802	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	235:685d5f11838f	803	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	235:685d5f11838f	804	* @retval None
mbed_official	235:685d5f11838f	805	*/
mbed_official	235:685d5f11838f	806	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
mbed_official	235:685d5f11838f	807
mbed_official	235:685d5f11838f	808	/**
mbed_official	235:685d5f11838f	809	* @brief Disable the NORSRAM device access.
mbed_official	235:685d5f11838f	810	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	235:685d5f11838f	811	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	235:685d5f11838f	812	* @retval None
mbed_official	235:685d5f11838f	813	*/
mbed_official	235:685d5f11838f	814	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
mbed_official	235:685d5f11838f	815	/**
mbed_official	235:685d5f11838f	816	* @}
mbed_official	235:685d5f11838f	817	*/
mbed_official	235:685d5f11838f	818
mbed_official	532:fe11edbda85c	819	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
mbed_official	235:685d5f11838f	820	* @brief macros to handle NAND device enable/disable
mbed_official	235:685d5f11838f	821	* @{
mbed_official	235:685d5f11838f	822	*/
mbed_official	532:fe11edbda85c	823	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	824	/**
mbed_official	532:fe11edbda85c	825	* @brief Enable the NAND device access.
mbed_official	532:fe11edbda85c	826	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	532:fe11edbda85c	827	* @param __BANK__: FMC_NAND Bank
mbed_official	532:fe11edbda85c	828	* @retval None
mbed_official	532:fe11edbda85c	829	*/
mbed_official	532:fe11edbda85c	830	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
mbed_official	532:fe11edbda85c	831
mbed_official	532:fe11edbda85c	832	/**
mbed_official	532:fe11edbda85c	833	* @brief Disable the NAND device access.
mbed_official	532:fe11edbda85c	834	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	532:fe11edbda85c	835	* @param __BANK__: FMC_NAND Bank
mbed_official	532:fe11edbda85c	836	* @retval None
mbed_official	532:fe11edbda85c	837	*/
mbed_official	532:fe11edbda85c	838	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
mbed_official	532:fe11edbda85c	839	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
mbed_official	235:685d5f11838f	840	/**
mbed_official	235:685d5f11838f	841	* @brief Enable the NAND device access.
mbed_official	235:685d5f11838f	842	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	235:685d5f11838f	843	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	844	* @retval None
mbed_official	235:685d5f11838f	845	*/
mbed_official	235:685d5f11838f	846	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
mbed_official	235:685d5f11838f	847	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
mbed_official	235:685d5f11838f	848
mbed_official	235:685d5f11838f	849	/**
mbed_official	235:685d5f11838f	850	* @brief Disable the NAND device access.
mbed_official	235:685d5f11838f	851	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	235:685d5f11838f	852	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	853	* @retval None
mbed_official	235:685d5f11838f	854	*/
mbed_official	235:685d5f11838f	855	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
mbed_official	235:685d5f11838f	856	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
mbed_official	532:fe11edbda85c	857
mbed_official	532:fe11edbda85c	858	#endif /* defined(STM32F446xx)*/
mbed_official	235:685d5f11838f	859	/**
mbed_official	235:685d5f11838f	860	* @}
mbed_official	235:685d5f11838f	861	*/
mbed_official	532:fe11edbda85c	862	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	863	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
mbed_official	235:685d5f11838f	864	* @brief macros to handle SRAM read/write operations
mbed_official	235:685d5f11838f	865	* @{
mbed_official	235:685d5f11838f	866	*/
mbed_official	235:685d5f11838f	867	/**
mbed_official	235:685d5f11838f	868	* @brief Enable the PCCARD device access.
mbed_official	235:685d5f11838f	869	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	235:685d5f11838f	870	* @retval None
mbed_official	235:685d5f11838f	871	*/
mbed_official	235:685d5f11838f	872	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
mbed_official	235:685d5f11838f	873
mbed_official	235:685d5f11838f	874	/**
mbed_official	235:685d5f11838f	875	* @brief Disable the PCCARD device access.
mbed_official	235:685d5f11838f	876	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	235:685d5f11838f	877	* @retval None
mbed_official	235:685d5f11838f	878	*/
mbed_official	235:685d5f11838f	879	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
mbed_official	235:685d5f11838f	880	/**
mbed_official	235:685d5f11838f	881	* @}
mbed_official	235:685d5f11838f	882	*/
mbed_official	532:fe11edbda85c	883	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
mbed_official	532:fe11edbda85c	884
mbed_official	532:fe11edbda85c	885	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
mbed_official	532:fe11edbda85c	886	* @brief macros to handle FMC flags and interrupts
mbed_official	235:685d5f11838f	887	* @{
mbed_official	235:685d5f11838f	888	*/
mbed_official	532:fe11edbda85c	889	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	890	/**
mbed_official	532:fe11edbda85c	891	* @brief Enable the NAND device interrupt.
mbed_official	532:fe11edbda85c	892	* @param __INSTANCE__: FMC_NAND instance
mbed_official	532:fe11edbda85c	893	* @param __BANK__: FMC_NAND Bank
mbed_official	532:fe11edbda85c	894	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	532:fe11edbda85c	895	* This parameter can be any combination of the following values:
mbed_official	532:fe11edbda85c	896	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	532:fe11edbda85c	897	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	532:fe11edbda85c	898	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	532:fe11edbda85c	899	* @retval None
mbed_official	532:fe11edbda85c	900	*/
mbed_official	532:fe11edbda85c	901	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
mbed_official	235:685d5f11838f	902
mbed_official	235:685d5f11838f	903	/**
mbed_official	532:fe11edbda85c	904	* @brief Disable the NAND device interrupt.
mbed_official	532:fe11edbda85c	905	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	532:fe11edbda85c	906	* @param __BANK__: FMC_NAND Bank
mbed_official	532:fe11edbda85c	907	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	532:fe11edbda85c	908	* This parameter can be any combination of the following values:
mbed_official	532:fe11edbda85c	909	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	532:fe11edbda85c	910	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	532:fe11edbda85c	911	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	532:fe11edbda85c	912	* @retval None
mbed_official	532:fe11edbda85c	913	*/
mbed_official	532:fe11edbda85c	914	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
mbed_official	532:fe11edbda85c	915
mbed_official	532:fe11edbda85c	916	/**
mbed_official	532:fe11edbda85c	917	* @brief Get flag status of the NAND device.
mbed_official	532:fe11edbda85c	918	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	532:fe11edbda85c	919	* @param __BANK__: FMC_NAND Bank
mbed_official	532:fe11edbda85c	920	* @param __FLAG__: FMC_NAND flag
mbed_official	532:fe11edbda85c	921	* This parameter can be any combination of the following values:
mbed_official	532:fe11edbda85c	922	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	532:fe11edbda85c	923	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	532:fe11edbda85c	924	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	532:fe11edbda85c	925	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	532:fe11edbda85c	926	* @retval The state of FLAG (SET or RESET).
mbed_official	532:fe11edbda85c	927	*/
mbed_official	532:fe11edbda85c	928	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
mbed_official	532:fe11edbda85c	929	/**
mbed_official	532:fe11edbda85c	930	* @brief Clear flag status of the NAND device.
mbed_official	532:fe11edbda85c	931	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	532:fe11edbda85c	932	* @param __BANK__: FMC_NAND Bank
mbed_official	532:fe11edbda85c	933	* @param __FLAG__: FMC_NAND flag
mbed_official	532:fe11edbda85c	934	* This parameter can be any combination of the following values:
mbed_official	532:fe11edbda85c	935	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	532:fe11edbda85c	936	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	532:fe11edbda85c	937	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	532:fe11edbda85c	938	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	532:fe11edbda85c	939	* @retval None
mbed_official	532:fe11edbda85c	940	*/
mbed_official	532:fe11edbda85c	941	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
mbed_official	532:fe11edbda85c	942	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
mbed_official	532:fe11edbda85c	943	/**
mbed_official	235:685d5f11838f	944	* @brief Enable the NAND device interrupt.
mbed_official	235:685d5f11838f	945	* @param __INSTANCE__: FMC_NAND instance
mbed_official	235:685d5f11838f	946	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	947	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	235:685d5f11838f	948	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	949	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	235:685d5f11838f	950	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	235:685d5f11838f	951	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	235:685d5f11838f	952	* @retval None
mbed_official	235:685d5f11838f	953	*/
mbed_official	235:685d5f11838f	954	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
mbed_official	235:685d5f11838f	955	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
mbed_official	235:685d5f11838f	956
mbed_official	235:685d5f11838f	957	/**
mbed_official	235:685d5f11838f	958	* @brief Disable the NAND device interrupt.
mbed_official	532:fe11edbda85c	959	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	235:685d5f11838f	960	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	961	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	235:685d5f11838f	962	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	963	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	235:685d5f11838f	964	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	235:685d5f11838f	965	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	235:685d5f11838f	966	* @retval None
mbed_official	235:685d5f11838f	967	*/
mbed_official	235:685d5f11838f	968	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
mbed_official	235:685d5f11838f	969	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
mbed_official	235:685d5f11838f	970
mbed_official	235:685d5f11838f	971	/**
mbed_official	235:685d5f11838f	972	* @brief Get flag status of the NAND device.
mbed_official	532:fe11edbda85c	973	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	235:685d5f11838f	974	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	975	* @param __FLAG__: FMC_NAND flag
mbed_official	235:685d5f11838f	976	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	977	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	235:685d5f11838f	978	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	235:685d5f11838f	979	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	235:685d5f11838f	980	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	235:685d5f11838f	981	* @retval The state of FLAG (SET or RESET).
mbed_official	235:685d5f11838f	982	*/
mbed_official	235:685d5f11838f	983	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
mbed_official	235:685d5f11838f	984	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
mbed_official	235:685d5f11838f	985	/**
mbed_official	235:685d5f11838f	986	* @brief Clear flag status of the NAND device.
mbed_official	532:fe11edbda85c	987	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	235:685d5f11838f	988	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	989	* @param __FLAG__: FMC_NAND flag
mbed_official	235:685d5f11838f	990	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	991	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	235:685d5f11838f	992	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	235:685d5f11838f	993	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	235:685d5f11838f	994	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	235:685d5f11838f	995	* @retval None
mbed_official	235:685d5f11838f	996	*/
mbed_official	235:685d5f11838f	997	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
mbed_official	532:fe11edbda85c	998	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
mbed_official	532:fe11edbda85c	999	#endif /* defined(STM32F446xx) */
mbed_official	532:fe11edbda85c	1000
mbed_official	532:fe11edbda85c	1001	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	235:685d5f11838f	1002	/**
mbed_official	235:685d5f11838f	1003	* @brief Enable the PCCARD device interrupt.
mbed_official	235:685d5f11838f	1004	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	235:685d5f11838f	1005	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	235:685d5f11838f	1006	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1007	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	235:685d5f11838f	1008	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	235:685d5f11838f	1009	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	235:685d5f11838f	1010	* @retval None
mbed_official	235:685d5f11838f	1011	*/
mbed_official	235:685d5f11838f	1012	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
mbed_official	235:685d5f11838f	1013
mbed_official	235:685d5f11838f	1014	/**
mbed_official	235:685d5f11838f	1015	* @brief Disable the PCCARD device interrupt.
mbed_official	235:685d5f11838f	1016	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	235:685d5f11838f	1017	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	235:685d5f11838f	1018	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1019	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	235:685d5f11838f	1020	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	235:685d5f11838f	1021	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	235:685d5f11838f	1022	* @retval None
mbed_official	235:685d5f11838f	1023	*/
mbed_official	235:685d5f11838f	1024	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
mbed_official	235:685d5f11838f	1025
mbed_official	235:685d5f11838f	1026	/**
mbed_official	235:685d5f11838f	1027	* @brief Get flag status of the PCCARD device.
mbed_official	235:685d5f11838f	1028	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	235:685d5f11838f	1029	* @param __FLAG__: FMC_PCCARD flag
mbed_official	235:685d5f11838f	1030	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1031	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	235:685d5f11838f	1032	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	235:685d5f11838f	1033	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	235:685d5f11838f	1034	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	235:685d5f11838f	1035	* @retval The state of FLAG (SET or RESET).
mbed_official	235:685d5f11838f	1036	*/
mbed_official	235:685d5f11838f	1037	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
mbed_official	235:685d5f11838f	1038
mbed_official	235:685d5f11838f	1039	/**
mbed_official	235:685d5f11838f	1040	* @brief Clear flag status of the PCCARD device.
mbed_official	235:685d5f11838f	1041	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	235:685d5f11838f	1042	* @param __FLAG__: FMC_PCCARD flag
mbed_official	235:685d5f11838f	1043	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1044	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	235:685d5f11838f	1045	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	235:685d5f11838f	1046	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	235:685d5f11838f	1047	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	235:685d5f11838f	1048	* @retval None
mbed_official	235:685d5f11838f	1049	*/
mbed_official	235:685d5f11838f	1050	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
mbed_official	532:fe11edbda85c	1051	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
mbed_official	532:fe11edbda85c	1052
mbed_official	235:685d5f11838f	1053	/**
mbed_official	235:685d5f11838f	1054	* @brief Enable the SDRAM device interrupt.
mbed_official	235:685d5f11838f	1055	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	235:685d5f11838f	1056	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	235:685d5f11838f	1057	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1058	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	235:685d5f11838f	1059	* @retval None
mbed_official	235:685d5f11838f	1060	*/
mbed_official	235:685d5f11838f	1061	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
mbed_official	235:685d5f11838f	1062
mbed_official	235:685d5f11838f	1063	/**
mbed_official	235:685d5f11838f	1064	* @brief Disable the SDRAM device interrupt.
mbed_official	235:685d5f11838f	1065	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	235:685d5f11838f	1066	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	235:685d5f11838f	1067	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1068	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	235:685d5f11838f	1069	* @retval None
mbed_official	235:685d5f11838f	1070	*/
mbed_official	235:685d5f11838f	1071	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
mbed_official	235:685d5f11838f	1072
mbed_official	235:685d5f11838f	1073	/**
mbed_official	235:685d5f11838f	1074	* @brief Get flag status of the SDRAM device.
mbed_official	235:685d5f11838f	1075	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	235:685d5f11838f	1076	* @param __FLAG__: FMC_SDRAM flag
mbed_official	235:685d5f11838f	1077	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1078	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
mbed_official	235:685d5f11838f	1079	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
mbed_official	235:685d5f11838f	1080	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
mbed_official	235:685d5f11838f	1081	* @retval The state of FLAG (SET or RESET).
mbed_official	235:685d5f11838f	1082	*/
mbed_official	235:685d5f11838f	1083	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
mbed_official	235:685d5f11838f	1084
mbed_official	235:685d5f11838f	1085	/**
mbed_official	235:685d5f11838f	1086	* @brief Clear flag status of the SDRAM device.
mbed_official	235:685d5f11838f	1087	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	235:685d5f11838f	1088	* @param __FLAG__: FMC_SDRAM flag
mbed_official	235:685d5f11838f	1089	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1090	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
mbed_official	235:685d5f11838f	1091	* @retval None
mbed_official	235:685d5f11838f	1092	*/
mbed_official	235:685d5f11838f	1093	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
mbed_official	235:685d5f11838f	1094	/**
mbed_official	235:685d5f11838f	1095	* @}
mbed_official	532:fe11edbda85c	1096	*/
mbed_official	532:fe11edbda85c	1097
mbed_official	532:fe11edbda85c	1098	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
mbed_official	532:fe11edbda85c	1099	* @{
mbed_official	532:fe11edbda85c	1100	*/
mbed_official	532:fe11edbda85c	1101	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
mbed_official	532:fe11edbda85c	1102	((BANK) == FMC_NORSRAM_BANK2) \|\| \
mbed_official	532:fe11edbda85c	1103	((BANK) == FMC_NORSRAM_BANK3) \|\| \
mbed_official	532:fe11edbda85c	1104	((BANK) == FMC_NORSRAM_BANK4))
mbed_official	532:fe11edbda85c	1105
mbed_official	532:fe11edbda85c	1106	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1107	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
mbed_official	532:fe11edbda85c	1108
mbed_official	532:fe11edbda85c	1109	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
mbed_official	532:fe11edbda85c	1110	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
mbed_official	532:fe11edbda85c	1111	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
mbed_official	532:fe11edbda85c	1112
mbed_official	532:fe11edbda85c	1113	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	532:fe11edbda85c	1114	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	532:fe11edbda85c	1115	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
mbed_official	532:fe11edbda85c	1116
mbed_official	532:fe11edbda85c	1117	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
mbed_official	532:fe11edbda85c	1118	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
mbed_official	532:fe11edbda85c	1119	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
mbed_official	532:fe11edbda85c	1120	((__MODE__) == FMC_ACCESS_MODE_D))
mbed_official	532:fe11edbda85c	1121
mbed_official	532:fe11edbda85c	1122	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
mbed_official	532:fe11edbda85c	1123	((BANK) == FMC_NAND_BANK3))
mbed_official	532:fe11edbda85c	1124
mbed_official	532:fe11edbda85c	1125	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1126	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
mbed_official	532:fe11edbda85c	1127
mbed_official	532:fe11edbda85c	1128	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
mbed_official	532:fe11edbda85c	1129	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
mbed_official	532:fe11edbda85c	1130
mbed_official	532:fe11edbda85c	1131	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1132	((STATE) == FMC_NAND_ECC_ENABLE))
mbed_official	532:fe11edbda85c	1133
mbed_official	532:fe11edbda85c	1134	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
mbed_official	532:fe11edbda85c	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
mbed_official	532:fe11edbda85c	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
mbed_official	532:fe11edbda85c	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
mbed_official	532:fe11edbda85c	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
mbed_official	532:fe11edbda85c	1139	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
mbed_official	532:fe11edbda85c	1140
mbed_official	532:fe11edbda85c	1141	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
mbed_official	532:fe11edbda85c	1142
mbed_official	532:fe11edbda85c	1143	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
mbed_official	532:fe11edbda85c	1144
mbed_official	532:fe11edbda85c	1145	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
mbed_official	532:fe11edbda85c	1146
mbed_official	532:fe11edbda85c	1147	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
mbed_official	532:fe11edbda85c	1148
mbed_official	532:fe11edbda85c	1149	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
mbed_official	532:fe11edbda85c	1150
mbed_official	532:fe11edbda85c	1151	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
mbed_official	532:fe11edbda85c	1152
mbed_official	532:fe11edbda85c	1153	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
mbed_official	532:fe11edbda85c	1154
mbed_official	532:fe11edbda85c	1155	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
mbed_official	532:fe11edbda85c	1156
mbed_official	532:fe11edbda85c	1157	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
mbed_official	532:fe11edbda85c	1158
mbed_official	532:fe11edbda85c	1159	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
mbed_official	532:fe11edbda85c	1160
mbed_official	532:fe11edbda85c	1161	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1162	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
mbed_official	532:fe11edbda85c	1163
mbed_official	532:fe11edbda85c	1164	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
mbed_official	532:fe11edbda85c	1165	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
mbed_official	532:fe11edbda85c	1166
mbed_official	532:fe11edbda85c	1167	#if !defined (STM32F446xx)
mbed_official	532:fe11edbda85c	1168	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1169	((__MODE__) == FMC_WRAP_MODE_ENABLE))
mbed_official	532:fe11edbda85c	1170	#endif /* !defined (STM32F446xx) */
mbed_official	532:fe11edbda85c	1171
mbed_official	532:fe11edbda85c	1172	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
mbed_official	532:fe11edbda85c	1173	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
mbed_official	532:fe11edbda85c	1174
mbed_official	532:fe11edbda85c	1175	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1176	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
mbed_official	532:fe11edbda85c	1177
mbed_official	532:fe11edbda85c	1178	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1179	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
mbed_official	532:fe11edbda85c	1180
mbed_official	532:fe11edbda85c	1181	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1182	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
mbed_official	532:fe11edbda85c	1183
mbed_official	532:fe11edbda85c	1184	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1185	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
mbed_official	532:fe11edbda85c	1186
mbed_official	532:fe11edbda85c	1187	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1188	((__BURST__) == FMC_WRITE_BURST_ENABLE))
mbed_official	532:fe11edbda85c	1189
mbed_official	532:fe11edbda85c	1190	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
mbed_official	532:fe11edbda85c	1191	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
mbed_official	532:fe11edbda85c	1192
mbed_official	532:fe11edbda85c	1193	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
mbed_official	532:fe11edbda85c	1194
mbed_official	532:fe11edbda85c	1195	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
mbed_official	532:fe11edbda85c	1196
mbed_official	532:fe11edbda85c	1197	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
mbed_official	532:fe11edbda85c	1198
mbed_official	532:fe11edbda85c	1199	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
mbed_official	532:fe11edbda85c	1200
mbed_official	532:fe11edbda85c	1201	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
mbed_official	532:fe11edbda85c	1202
mbed_official	532:fe11edbda85c	1203	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
mbed_official	532:fe11edbda85c	1204
mbed_official	532:fe11edbda85c	1205	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
mbed_official	532:fe11edbda85c	1206	((BANK) == FMC_SDRAM_BANK2))
mbed_official	532:fe11edbda85c	1207
mbed_official	532:fe11edbda85c	1208	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
mbed_official	532:fe11edbda85c	1209	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
mbed_official	532:fe11edbda85c	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
mbed_official	532:fe11edbda85c	1211	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
mbed_official	532:fe11edbda85c	1212
mbed_official	532:fe11edbda85c	1213	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
mbed_official	532:fe11edbda85c	1214	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
mbed_official	532:fe11edbda85c	1215	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
mbed_official	532:fe11edbda85c	1216
mbed_official	532:fe11edbda85c	1217	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	532:fe11edbda85c	1218	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	532:fe11edbda85c	1219	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
mbed_official	532:fe11edbda85c	1220
mbed_official	532:fe11edbda85c	1221	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
mbed_official	532:fe11edbda85c	1222	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
mbed_official	532:fe11edbda85c	1223
mbed_official	532:fe11edbda85c	1224
mbed_official	532:fe11edbda85c	1225	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
mbed_official	532:fe11edbda85c	1226	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
mbed_official	532:fe11edbda85c	1227	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
mbed_official	532:fe11edbda85c	1228
mbed_official	532:fe11edbda85c	1229	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1230	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
mbed_official	532:fe11edbda85c	1231	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
mbed_official	532:fe11edbda85c	1232
mbed_official	532:fe11edbda85c	1233	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1234	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
mbed_official	532:fe11edbda85c	1235
mbed_official	532:fe11edbda85c	1236
mbed_official	532:fe11edbda85c	1237	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
mbed_official	532:fe11edbda85c	1238	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
mbed_official	532:fe11edbda85c	1239	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
mbed_official	532:fe11edbda85c	1240
mbed_official	532:fe11edbda85c	1241	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	532:fe11edbda85c	1242
mbed_official	532:fe11edbda85c	1243	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	532:fe11edbda85c	1244
mbed_official	532:fe11edbda85c	1245	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
mbed_official	532:fe11edbda85c	1246
mbed_official	532:fe11edbda85c	1247	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	532:fe11edbda85c	1248
mbed_official	532:fe11edbda85c	1249	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
mbed_official	532:fe11edbda85c	1250
mbed_official	532:fe11edbda85c	1251	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	532:fe11edbda85c	1252
mbed_official	532:fe11edbda85c	1253	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	532:fe11edbda85c	1254
mbed_official	532:fe11edbda85c	1255	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
mbed_official	532:fe11edbda85c	1256	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
mbed_official	532:fe11edbda85c	1257	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
mbed_official	532:fe11edbda85c	1258	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
mbed_official	532:fe11edbda85c	1259	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
mbed_official	532:fe11edbda85c	1260	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
mbed_official	532:fe11edbda85c	1261	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
mbed_official	532:fe11edbda85c	1262
mbed_official	532:fe11edbda85c	1263	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
mbed_official	532:fe11edbda85c	1264	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
mbed_official	532:fe11edbda85c	1265	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
mbed_official	532:fe11edbda85c	1266
mbed_official	532:fe11edbda85c	1267	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
mbed_official	532:fe11edbda85c	1268
mbed_official	532:fe11edbda85c	1269	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
mbed_official	532:fe11edbda85c	1270
mbed_official	532:fe11edbda85c	1271	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
mbed_official	532:fe11edbda85c	1272
mbed_official	532:fe11edbda85c	1273	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
mbed_official	532:fe11edbda85c	1274
mbed_official	532:fe11edbda85c	1275	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1276	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
mbed_official	532:fe11edbda85c	1277
mbed_official	532:fe11edbda85c	1278	#if defined (STM32F446xx)
mbed_official	532:fe11edbda85c	1279	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
mbed_official	532:fe11edbda85c	1280	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
mbed_official	532:fe11edbda85c	1281	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
mbed_official	532:fe11edbda85c	1282	((SIZE) == FMC_PAGE_SIZE_1024))
mbed_official	532:fe11edbda85c	1283
mbed_official	532:fe11edbda85c	1284	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1285	((FIFO) == FMC_WRITE_FIFO_ENABLE))
mbed_official	532:fe11edbda85c	1286	#endif /* defined (STM32F446xx) */
mbed_official	532:fe11edbda85c	1287
mbed_official	532:fe11edbda85c	1288	/**
mbed_official	532:fe11edbda85c	1289	* @}
mbed_official	532:fe11edbda85c	1290	*/
mbed_official	532:fe11edbda85c	1291
mbed_official	532:fe11edbda85c	1292	/**
mbed_official	532:fe11edbda85c	1293	* @}
mbed_official	235:685d5f11838f	1294	*/
mbed_official	235:685d5f11838f	1295
mbed_official	532:fe11edbda85c	1296	/* Private functions ---------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1297	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
mbed_official	532:fe11edbda85c	1298	* @{
mbed_official	532:fe11edbda85c	1299	*/
mbed_official	235:685d5f11838f	1300
mbed_official	532:fe11edbda85c	1301	/** @defgroup FMC_LL_NORSRAM NOR SRAM
mbed_official	532:fe11edbda85c	1302	* @{
mbed_official	532:fe11edbda85c	1303	*/
mbed_official	532:fe11edbda85c	1304	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
mbed_official	532:fe11edbda85c	1305	* @{
mbed_official	532:fe11edbda85c	1306	*/
mbed_official	235:685d5f11838f	1307	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
mbed_official	235:685d5f11838f	1308	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	235:685d5f11838f	1309	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
mbed_official	235:685d5f11838f	1310	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
mbed_official	532:fe11edbda85c	1311	/**
mbed_official	532:fe11edbda85c	1312	* @}
mbed_official	532:fe11edbda85c	1313	*/
mbed_official	235:685d5f11838f	1314
mbed_official	532:fe11edbda85c	1315	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
mbed_official	532:fe11edbda85c	1316	* @{
mbed_official	532:fe11edbda85c	1317	*/
mbed_official	235:685d5f11838f	1318	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	532:fe11edbda85c	1320	/**
mbed_official	532:fe11edbda85c	1321	* @}
mbed_official	532:fe11edbda85c	1322	*/
mbed_official	532:fe11edbda85c	1323	/**
mbed_official	532:fe11edbda85c	1324	* @}
mbed_official	532:fe11edbda85c	1325	*/
mbed_official	235:685d5f11838f	1326
mbed_official	532:fe11edbda85c	1327	/** @defgroup FMC_LL_NAND NAND
mbed_official	532:fe11edbda85c	1328	* @{
mbed_official	532:fe11edbda85c	1329	*/
mbed_official	532:fe11edbda85c	1330	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
mbed_official	532:fe11edbda85c	1331	* @{
mbed_official	532:fe11edbda85c	1332	*/
mbed_official	235:685d5f11838f	1333	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
mbed_official	235:685d5f11838f	1334	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	235:685d5f11838f	1335	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	235:685d5f11838f	1336	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	532:fe11edbda85c	1337	/**
mbed_official	532:fe11edbda85c	1338	* @}
mbed_official	532:fe11edbda85c	1339	*/
mbed_official	235:685d5f11838f	1340
mbed_official	532:fe11edbda85c	1341	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
mbed_official	532:fe11edbda85c	1342	* @{
mbed_official	532:fe11edbda85c	1343	*/
mbed_official	235:685d5f11838f	1344	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1345	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1346	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
mbed_official	235:685d5f11838f	1347
mbed_official	532:fe11edbda85c	1348	/**
mbed_official	532:fe11edbda85c	1349	* @}
mbed_official	532:fe11edbda85c	1350	*/
mbed_official	532:fe11edbda85c	1351	/**
mbed_official	532:fe11edbda85c	1352	* @}
mbed_official	532:fe11edbda85c	1353	*/
mbed_official	532:fe11edbda85c	1354	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	1355	/** @defgroup FMC_LL_PCCARD PCCARD
mbed_official	532:fe11edbda85c	1356	* @{
mbed_official	532:fe11edbda85c	1357	*/
mbed_official	532:fe11edbda85c	1358	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
mbed_official	532:fe11edbda85c	1359	* @{
mbed_official	532:fe11edbda85c	1360	*/
mbed_official	235:685d5f11838f	1361	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
mbed_official	235:685d5f11838f	1362	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	235:685d5f11838f	1363	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	235:685d5f11838f	1364	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	235:685d5f11838f	1365	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
mbed_official	532:fe11edbda85c	1366	/**
mbed_official	532:fe11edbda85c	1367	* @}
mbed_official	532:fe11edbda85c	1368	*/
mbed_official	532:fe11edbda85c	1369	/**
mbed_official	532:fe11edbda85c	1370	* @}
mbed_official	532:fe11edbda85c	1371	*/
mbed_official	532:fe11edbda85c	1372	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	1373
mbed_official	532:fe11edbda85c	1374	/** @defgroup FMC_LL_SDRAM SDRAM
mbed_official	532:fe11edbda85c	1375	* @{
mbed_official	532:fe11edbda85c	1376	*/
mbed_official	532:fe11edbda85c	1377	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
mbed_official	532:fe11edbda85c	1378	* @{
mbed_official	532:fe11edbda85c	1379	*/
mbed_official	235:685d5f11838f	1380	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
mbed_official	235:685d5f11838f	1381	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	235:685d5f11838f	1382	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	532:fe11edbda85c	1383	/**
mbed_official	532:fe11edbda85c	1384	* @}
mbed_official	532:fe11edbda85c	1385	*/
mbed_official	235:685d5f11838f	1386
mbed_official	532:fe11edbda85c	1387	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
mbed_official	532:fe11edbda85c	1388	* @{
mbed_official	532:fe11edbda85c	1389	*/
mbed_official	235:685d5f11838f	1390	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1392	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
mbed_official	235:685d5f11838f	1393	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
mbed_official	235:685d5f11838f	1394	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
mbed_official	235:685d5f11838f	1395	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1396	/**
mbed_official	235:685d5f11838f	1397	* @}
mbed_official	532:fe11edbda85c	1398	*/
mbed_official	532:fe11edbda85c	1399	/**
mbed_official	532:fe11edbda85c	1400	* @}
mbed_official	532:fe11edbda85c	1401	*/
mbed_official	235:685d5f11838f	1402
mbed_official	235:685d5f11838f	1403	/**
mbed_official	235:685d5f11838f	1404	* @}
mbed_official	235:685d5f11838f	1405	*/
mbed_official	532:fe11edbda85c	1406
mbed_official	532:fe11edbda85c	1407	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
mbed_official	532:fe11edbda85c	1408	/**
mbed_official	532:fe11edbda85c	1409	* @}
mbed_official	532:fe11edbda85c	1410	*/
mbed_official	532:fe11edbda85c	1411
mbed_official	532:fe11edbda85c	1412	/**
mbed_official	532:fe11edbda85c	1413	* @}
mbed_official	532:fe11edbda85c	1414	*/
mbed_official	235:685d5f11838f	1415	#ifdef __cplusplus
mbed_official	235:685d5f11838f	1416	}
mbed_official	235:685d5f11838f	1417	#endif
mbed_official	235:685d5f11838f	1418
mbed_official	235:685d5f11838f	1419	#endif /* __STM32F4xx_LL_FMC_H */
mbed_official	235:685d5f11838f	1420
mbed_official	235:685d5f11838f	1421	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	02 Nov 2015
Imports:	14
Forks:	0
Commits:	637
Dependents:	2
Dependencies:	0
Followers:	5

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

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