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Modified version of the mbed library for use with the Nucleo boards.

Dependents: EEPROMWrite Full-Project

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

Committer:: mbed_official
Date:: Thu Aug 20 10:45:13 2015 +0100
Revision:: 613:bc40b8d2aec4
Parent:: 532:fe11edbda85c

Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade

Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/

Nordic: update application start address in GCC linker script

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User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_tim.h
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	613:bc40b8d2aec4	5	* @version V1.3.2
mbed_official	613:bc40b8d2aec4	6	* @date 26-June-2015
mbed_official	87:085cde657901	7	* @brief Header file of TIM HAL module.
mbed_official	87:085cde657901	8	******************************************************************************
mbed_official	87:085cde657901	9	* @attention
mbed_official	87:085cde657901	10	*
mbed_official	532:fe11edbda85c	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	12	*
mbed_official	87:085cde657901	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	14	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	16	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	19	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	21	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	22	* without specific prior written permission.
mbed_official	87:085cde657901	23	*
mbed_official	87:085cde657901	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	34	*
mbed_official	87:085cde657901	35	******************************************************************************
mbed_official	87:085cde657901	36	*/
mbed_official	87:085cde657901	37
mbed_official	87:085cde657901	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	87:085cde657901	39	#ifndef __STM32F4xx_HAL_TIM_H
mbed_official	87:085cde657901	40	#define __STM32F4xx_HAL_TIM_H
mbed_official	87:085cde657901	41
mbed_official	87:085cde657901	42	#ifdef __cplusplus
mbed_official	87:085cde657901	43	extern "C" {
mbed_official	87:085cde657901	44	#endif
mbed_official	87:085cde657901	45
mbed_official	87:085cde657901	46	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	47	#include "stm32f4xx_hal_def.h"
mbed_official	87:085cde657901	48
mbed_official	532:fe11edbda85c	49	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	50	* @{
mbed_official	87:085cde657901	51	*/
mbed_official	87:085cde657901	52
mbed_official	87:085cde657901	53	/** @addtogroup TIM
mbed_official	87:085cde657901	54	* @{
mbed_official	226:b062af740e40	55	*/
mbed_official	87:085cde657901	56
mbed_official	226:b062af740e40	57	/* Exported types ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	58	/** @defgroup TIM_Exported_Types TIM Exported Types
mbed_official	532:fe11edbda85c	59	* @{
mbed_official	532:fe11edbda85c	60	*/
mbed_official	532:fe11edbda85c	61
mbed_official	87:085cde657901	62	/**
mbed_official	87:085cde657901	63	* @brief TIM Time base Configuration Structure definition
mbed_official	87:085cde657901	64	*/
mbed_official	87:085cde657901	65	typedef struct
mbed_official	87:085cde657901	66	{
mbed_official	87:085cde657901	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	87:085cde657901	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	87:085cde657901	69
mbed_official	87:085cde657901	70	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	87:085cde657901	71	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	87:085cde657901	72
mbed_official	87:085cde657901	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	87:085cde657901	74	Auto-Reload Register at the next update event.
mbed_official	226:b062af740e40	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	87:085cde657901	76
mbed_official	87:085cde657901	77	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	87:085cde657901	78	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	87:085cde657901	79
mbed_official	87:085cde657901	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
mbed_official	87:085cde657901	81	reaches zero, an update event is generated and counting restarts
mbed_official	87:085cde657901	82	from the RCR value (N).
mbed_official	87:085cde657901	83	This means in PWM mode that (N+1) corresponds to:
mbed_official	87:085cde657901	84	- the number of PWM periods in edge-aligned mode
mbed_official	87:085cde657901	85	- the number of half PWM period in center-aligned mode
mbed_official	87:085cde657901	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
mbed_official	87:085cde657901	87	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	88	} TIM_Base_InitTypeDef;
mbed_official	87:085cde657901	89
mbed_official	87:085cde657901	90	/**
mbed_official	87:085cde657901	91	* @brief TIM Output Compare Configuration Structure definition
mbed_official	87:085cde657901	92	*/
mbed_official	87:085cde657901	93
mbed_official	87:085cde657901	94	typedef struct
mbed_official	226:b062af740e40	95	{
mbed_official	87:085cde657901	96	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	87:085cde657901	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	87:085cde657901	98
mbed_official	87:085cde657901	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	226:b062af740e40	100	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	87:085cde657901	101
mbed_official	87:085cde657901	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	87:085cde657901	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	87:085cde657901	104
mbed_official	87:085cde657901	105	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	87:085cde657901	106	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	87:085cde657901	107	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	108
mbed_official	87:085cde657901	109	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	87:085cde657901	110	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	87:085cde657901	111	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	87:085cde657901	112
mbed_official	87:085cde657901	113
mbed_official	87:085cde657901	114	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	87:085cde657901	115	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	87:085cde657901	116	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	117
mbed_official	87:085cde657901	118	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	87:085cde657901	119	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	87:085cde657901	120	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	121	} TIM_OC_InitTypeDef;
mbed_official	87:085cde657901	122
mbed_official	87:085cde657901	123	/**
mbed_official	87:085cde657901	124	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	87:085cde657901	125	*/
mbed_official	87:085cde657901	126	typedef struct
mbed_official	226:b062af740e40	127	{
mbed_official	87:085cde657901	128	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	87:085cde657901	129	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	87:085cde657901	130
mbed_official	87:085cde657901	131	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	226:b062af740e40	132	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	87:085cde657901	133
mbed_official	87:085cde657901	134	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	87:085cde657901	135	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	87:085cde657901	136
mbed_official	87:085cde657901	137	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	87:085cde657901	138	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	87:085cde657901	139	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	140
mbed_official	87:085cde657901	141	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	87:085cde657901	142	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	87:085cde657901	143	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	144
mbed_official	87:085cde657901	145	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	87:085cde657901	146	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	87:085cde657901	147	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	148
mbed_official	87:085cde657901	149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	87:085cde657901	151
mbed_official	87:085cde657901	152	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	87:085cde657901	153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	87:085cde657901	154
mbed_official	87:085cde657901	155	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	87:085cde657901	156	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	157	} TIM_OnePulse_InitTypeDef;
mbed_official	87:085cde657901	158
mbed_official	87:085cde657901	159
mbed_official	87:085cde657901	160	/**
mbed_official	87:085cde657901	161	* @brief TIM Input Capture Configuration Structure definition
mbed_official	87:085cde657901	162	*/
mbed_official	87:085cde657901	163
mbed_official	87:085cde657901	164	typedef struct
mbed_official	226:b062af740e40	165	{
mbed_official	87:085cde657901	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	87:085cde657901	168
mbed_official	87:085cde657901	169	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	87:085cde657901	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	87:085cde657901	171
mbed_official	87:085cde657901	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	87:085cde657901	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	87:085cde657901	174
mbed_official	87:085cde657901	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	87:085cde657901	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	177	} TIM_IC_InitTypeDef;
mbed_official	87:085cde657901	178
mbed_official	87:085cde657901	179	/**
mbed_official	87:085cde657901	180	* @brief TIM Encoder Configuration Structure definition
mbed_official	87:085cde657901	181	*/
mbed_official	87:085cde657901	182
mbed_official	87:085cde657901	183	typedef struct
mbed_official	87:085cde657901	184	{
mbed_official	87:085cde657901	185	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	186	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	87:085cde657901	187
mbed_official	87:085cde657901	188	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	189	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	87:085cde657901	190
mbed_official	87:085cde657901	191	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	87:085cde657901	192	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	87:085cde657901	193
mbed_official	87:085cde657901	194	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	87:085cde657901	195	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	87:085cde657901	196
mbed_official	87:085cde657901	197	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	87:085cde657901	198	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	199
mbed_official	87:085cde657901	200	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	201	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	87:085cde657901	202
mbed_official	87:085cde657901	203	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	87:085cde657901	204	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	87:085cde657901	205
mbed_official	87:085cde657901	206	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	87:085cde657901	207	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	87:085cde657901	208
mbed_official	87:085cde657901	209	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	226:b062af740e40	210	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	211	} TIM_Encoder_InitTypeDef;
mbed_official	87:085cde657901	212
mbed_official	87:085cde657901	213	/**
mbed_official	87:085cde657901	214	* @brief Clock Configuration Handle Structure definition
mbed_official	87:085cde657901	215	*/
mbed_official	87:085cde657901	216	typedef struct
mbed_official	87:085cde657901	217	{
mbed_official	226:b062af740e40	218	uint32_t ClockSource; /*!< TIM clock sources.
mbed_official	87:085cde657901	219	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	226:b062af740e40	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
mbed_official	87:085cde657901	221	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	226:b062af740e40	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
mbed_official	87:085cde657901	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	226:b062af740e40	224	uint32_t ClockFilter; /*!< TIM clock filter.
mbed_official	226:b062af740e40	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	226	}TIM_ClockConfigTypeDef;
mbed_official	87:085cde657901	227
mbed_official	87:085cde657901	228	/**
mbed_official	87:085cde657901	229	* @brief Clear Input Configuration Handle Structure definition
mbed_official	87:085cde657901	230	*/
mbed_official	87:085cde657901	231	typedef struct
mbed_official	87:085cde657901	232	{
mbed_official	226:b062af740e40	233	uint32_t ClearInputState; /*!< TIM clear Input state.
mbed_official	87:085cde657901	234	This parameter can be ENABLE or DISABLE */
mbed_official	226:b062af740e40	235	uint32_t ClearInputSource; /*!< TIM clear Input sources.
mbed_official	87:085cde657901	236	This parameter can be a value of @ref TIM_ClearInput_Source */
mbed_official	226:b062af740e40	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
mbed_official	87:085cde657901	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	226:b062af740e40	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
mbed_official	87:085cde657901	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	226:b062af740e40	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
mbed_official	226:b062af740e40	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	243	}TIM_ClearInputConfigTypeDef;
mbed_official	87:085cde657901	244
mbed_official	87:085cde657901	245	/**
mbed_official	87:085cde657901	246	* @brief TIM Slave configuration Structure definition
mbed_official	87:085cde657901	247	*/
mbed_official	87:085cde657901	248	typedef struct {
mbed_official	87:085cde657901	249	uint32_t SlaveMode; /*!< Slave mode selection
mbed_official	87:085cde657901	250	This parameter can be a value of @ref TIM_Slave_Mode */
mbed_official	87:085cde657901	251	uint32_t InputTrigger; /*!< Input Trigger source
mbed_official	87:085cde657901	252	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	87:085cde657901	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
mbed_official	87:085cde657901	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	87:085cde657901	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
mbed_official	87:085cde657901	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	87:085cde657901	257	uint32_t TriggerFilter; /*!< Input trigger filter
mbed_official	226:b062af740e40	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	259
mbed_official	87:085cde657901	260	}TIM_SlaveConfigTypeDef;
mbed_official	87:085cde657901	261
mbed_official	87:085cde657901	262	/**
mbed_official	87:085cde657901	263	* @brief HAL State structures definition
mbed_official	87:085cde657901	264	*/
mbed_official	87:085cde657901	265	typedef enum
mbed_official	87:085cde657901	266	{
mbed_official	87:085cde657901	267	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	87:085cde657901	268	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	226:b062af740e40	269	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	226:b062af740e40	270	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	226:b062af740e40	271	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	87:085cde657901	272	}HAL_TIM_StateTypeDef;
mbed_official	87:085cde657901	273
mbed_official	87:085cde657901	274	/**
mbed_official	87:085cde657901	275	* @brief HAL Active channel structures definition
mbed_official	87:085cde657901	276	*/
mbed_official	87:085cde657901	277	typedef enum
mbed_official	87:085cde657901	278	{
mbed_official	87:085cde657901	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	87:085cde657901	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	226:b062af740e40	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	87:085cde657901	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	226:b062af740e40	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	87:085cde657901	284	}HAL_TIM_ActiveChannel;
mbed_official	87:085cde657901	285
mbed_official	87:085cde657901	286	/**
mbed_official	87:085cde657901	287	* @brief TIM Time Base Handle Structure definition
mbed_official	87:085cde657901	288	*/
mbed_official	87:085cde657901	289	typedef struct
mbed_official	87:085cde657901	290	{
mbed_official	226:b062af740e40	291	TIM_TypeDef Instance; /!< Register base address */
mbed_official	87:085cde657901	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	226:b062af740e40	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	87:085cde657901	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	87:085cde657901	295	This array is accessed by a @ref DMA_Handle_index */
mbed_official	87:085cde657901	296	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	226:b062af740e40	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	87:085cde657901	298	}TIM_HandleTypeDef;
mbed_official	532:fe11edbda85c	299	/**
mbed_official	532:fe11edbda85c	300	* @}
mbed_official	532:fe11edbda85c	301	*/
mbed_official	87:085cde657901	302
mbed_official	87:085cde657901	303	/* Exported constants --------------------------------------------------------*/
mbed_official	532:fe11edbda85c	304	/** @defgroup TIM_Exported_Constants TIM Exported Constants
mbed_official	87:085cde657901	305	* @{
mbed_official	87:085cde657901	306	*/
mbed_official	87:085cde657901	307
mbed_official	532:fe11edbda85c	308	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
mbed_official	87:085cde657901	309	* @{
mbed_official	87:085cde657901	310	*/
mbed_official	87:085cde657901	311	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	87:085cde657901	312	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	87:085cde657901	313	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	87:085cde657901	314	/**
mbed_official	87:085cde657901	315	* @}
mbed_official	87:085cde657901	316	*/
mbed_official	87:085cde657901	317
mbed_official	532:fe11edbda85c	318	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
mbed_official	87:085cde657901	319	* @{
mbed_official	87:085cde657901	320	*/
mbed_official	226:b062af740e40	321	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	226:b062af740e40	322	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	87:085cde657901	323	/**
mbed_official	87:085cde657901	324	* @}
mbed_official	87:085cde657901	325	*/
mbed_official	87:085cde657901	326
mbed_official	532:fe11edbda85c	327	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
mbed_official	87:085cde657901	328	* @{
mbed_official	226:b062af740e40	329	*/
mbed_official	87:085cde657901	330	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	87:085cde657901	331	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	87:085cde657901	332	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	87:085cde657901	333	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	87:085cde657901	334	/**
mbed_official	87:085cde657901	335	* @}
mbed_official	87:085cde657901	336	*/
mbed_official	87:085cde657901	337
mbed_official	532:fe11edbda85c	338	/** @defgroup TIM_Counter_Mode TIM Counter Mode
mbed_official	87:085cde657901	339	* @{
mbed_official	87:085cde657901	340	*/
mbed_official	87:085cde657901	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	87:085cde657901	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	87:085cde657901	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	87:085cde657901	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	87:085cde657901	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	87:085cde657901	346	/**
mbed_official	87:085cde657901	347	* @}
mbed_official	226:b062af740e40	348	*/
mbed_official	226:b062af740e40	349
mbed_official	532:fe11edbda85c	350	/** @defgroup TIM_ClockDivision TIM Clock Division
mbed_official	87:085cde657901	351	* @{
mbed_official	87:085cde657901	352	*/
mbed_official	87:085cde657901	353	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	87:085cde657901	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	87:085cde657901	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	87:085cde657901	356	/**
mbed_official	87:085cde657901	357	* @}
mbed_official	87:085cde657901	358	*/
mbed_official	87:085cde657901	359
mbed_official	532:fe11edbda85c	360	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
mbed_official	87:085cde657901	361	* @{
mbed_official	87:085cde657901	362	*/
mbed_official	87:085cde657901	363	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official	87:085cde657901	364	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
mbed_official	87:085cde657901	365	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
mbed_official	87:085cde657901	366	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
mbed_official	87:085cde657901	367	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
mbed_official	87:085cde657901	368	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
mbed_official	87:085cde657901	369	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
mbed_official	87:085cde657901	370	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
mbed_official	87:085cde657901	371
mbed_official	87:085cde657901	372	/**
mbed_official	87:085cde657901	373	* @}
mbed_official	87:085cde657901	374	*/
mbed_official	87:085cde657901	375
mbed_official	532:fe11edbda85c	376	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
mbed_official	87:085cde657901	377	* @{
mbed_official	87:085cde657901	378	*/
mbed_official	532:fe11edbda85c	379	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	532:fe11edbda85c	380	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	87:085cde657901	381	/**
mbed_official	87:085cde657901	382	* @}
mbed_official	226:b062af740e40	383	*/
mbed_official	226:b062af740e40	384
mbed_official	532:fe11edbda85c	385	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
mbed_official	87:085cde657901	386	* @{
mbed_official	87:085cde657901	387	*/
mbed_official	532:fe11edbda85c	388	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	532:fe11edbda85c	389	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	87:085cde657901	390	/**
mbed_official	87:085cde657901	391	* @}
mbed_official	226:b062af740e40	392	*/
mbed_official	226:b062af740e40	393
mbed_official	532:fe11edbda85c	394	/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
mbed_official	87:085cde657901	395	* @{
mbed_official	87:085cde657901	396	*/
mbed_official	87:085cde657901	397	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	87:085cde657901	398	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
mbed_official	87:085cde657901	399	/**
mbed_official	87:085cde657901	400	* @}
mbed_official	87:085cde657901	401	*/
mbed_official	87:085cde657901	402
mbed_official	532:fe11edbda85c	403	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
mbed_official	87:085cde657901	404	* @{
mbed_official	87:085cde657901	405	*/
mbed_official	87:085cde657901	406	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
mbed_official	87:085cde657901	407	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	87:085cde657901	408	/**
mbed_official	87:085cde657901	409	* @}
mbed_official	87:085cde657901	410	*/
mbed_official	87:085cde657901	411
mbed_official	532:fe11edbda85c	412	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
mbed_official	87:085cde657901	413	* @{
mbed_official	87:085cde657901	414	*/
mbed_official	87:085cde657901	415	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
mbed_official	87:085cde657901	416	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	87:085cde657901	417	/**
mbed_official	87:085cde657901	418	* @}
mbed_official	87:085cde657901	419	*/
mbed_official	87:085cde657901	420
mbed_official	532:fe11edbda85c	421	/** @defgroup TIM_Channel TIM Channel
mbed_official	87:085cde657901	422	* @{
mbed_official	87:085cde657901	423	*/
mbed_official	87:085cde657901	424	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official	87:085cde657901	425	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official	87:085cde657901	426	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official	87:085cde657901	427	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official	87:085cde657901	428	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official	87:085cde657901	429
mbed_official	87:085cde657901	430	/**
mbed_official	87:085cde657901	431	* @}
mbed_official	226:b062af740e40	432	*/
mbed_official	87:085cde657901	433
mbed_official	532:fe11edbda85c	434	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
mbed_official	87:085cde657901	435	* @{
mbed_official	87:085cde657901	436	*/
mbed_official	87:085cde657901	437	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	87:085cde657901	438	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	87:085cde657901	439	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	87:085cde657901	440	/**
mbed_official	87:085cde657901	441	* @}
mbed_official	226:b062af740e40	442	*/
mbed_official	87:085cde657901	443
mbed_official	532:fe11edbda85c	444	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
mbed_official	87:085cde657901	445	* @{
mbed_official	87:085cde657901	446	*/
mbed_official	87:085cde657901	447	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	87:085cde657901	448	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	87:085cde657901	449	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	87:085cde657901	450	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	87:085cde657901	451	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	87:085cde657901	452
mbed_official	87:085cde657901	453	/**
mbed_official	87:085cde657901	454	* @}
mbed_official	226:b062af740e40	455	*/
mbed_official	87:085cde657901	456
mbed_official	532:fe11edbda85c	457	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
mbed_official	87:085cde657901	458	* @{
mbed_official	87:085cde657901	459	*/
mbed_official	87:085cde657901	460	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	87:085cde657901	461	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	87:085cde657901	462	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	87:085cde657901	463	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	87:085cde657901	464	/**
mbed_official	87:085cde657901	465	* @}
mbed_official	87:085cde657901	466	*/
mbed_official	87:085cde657901	467
mbed_official	532:fe11edbda85c	468	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
mbed_official	87:085cde657901	469	* @{
mbed_official	87:085cde657901	470	*/
mbed_official	87:085cde657901	471	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	87:085cde657901	472	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	87:085cde657901	473	/**
mbed_official	87:085cde657901	474	* @}
mbed_official	226:b062af740e40	475	*/
mbed_official	226:b062af740e40	476
mbed_official	532:fe11edbda85c	477	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
mbed_official	87:085cde657901	478	* @{
mbed_official	226:b062af740e40	479	*/
mbed_official	87:085cde657901	480	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	87:085cde657901	481	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	87:085cde657901	482	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	532:fe11edbda85c	483
mbed_official	87:085cde657901	484	/**
mbed_official	87:085cde657901	485	* @}
mbed_official	226:b062af740e40	486	*/
mbed_official	226:b062af740e40	487
mbed_official	532:fe11edbda85c	488	/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
mbed_official	87:085cde657901	489	* @{
mbed_official	87:085cde657901	490	*/
mbed_official	87:085cde657901	491	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	87:085cde657901	492	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	87:085cde657901	493	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	87:085cde657901	494	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	87:085cde657901	495	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	87:085cde657901	496	#define TIM_IT_COM (TIM_DIER_COMIE)
mbed_official	87:085cde657901	497	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	87:085cde657901	498	#define TIM_IT_BREAK (TIM_DIER_BIE)
mbed_official	87:085cde657901	499	/**
mbed_official	87:085cde657901	500	* @}
mbed_official	87:085cde657901	501	*/
mbed_official	532:fe11edbda85c	502
mbed_official	532:fe11edbda85c	503	/** @defgroup TIM_Commutation_Source TIM Commutation Source
mbed_official	532:fe11edbda85c	504	* @{
mbed_official	532:fe11edbda85c	505	*/
mbed_official	369:2e96f1b71984	506	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
mbed_official	369:2e96f1b71984	507	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
mbed_official	532:fe11edbda85c	508	/**
mbed_official	532:fe11edbda85c	509	* @}
mbed_official	532:fe11edbda85c	510	*/
mbed_official	87:085cde657901	511
mbed_official	532:fe11edbda85c	512	/** @defgroup TIM_DMA_sources TIM DMA sources
mbed_official	87:085cde657901	513	* @{
mbed_official	87:085cde657901	514	*/
mbed_official	87:085cde657901	515	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	87:085cde657901	516	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	87:085cde657901	517	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	87:085cde657901	518	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	87:085cde657901	519	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	87:085cde657901	520	#define TIM_DMA_COM (TIM_DIER_COMDE)
mbed_official	87:085cde657901	521	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	87:085cde657901	522	/**
mbed_official	87:085cde657901	523	* @}
mbed_official	87:085cde657901	524	*/
mbed_official	226:b062af740e40	525
mbed_official	532:fe11edbda85c	526	/** @defgroup TIM_Event_Source TIM Event Source
mbed_official	87:085cde657901	527	* @{
mbed_official	87:085cde657901	528	*/
mbed_official	532:fe11edbda85c	529	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
mbed_official	532:fe11edbda85c	530	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
mbed_official	532:fe11edbda85c	531	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
mbed_official	532:fe11edbda85c	532	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
mbed_official	532:fe11edbda85c	533	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
mbed_official	532:fe11edbda85c	534	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
mbed_official	532:fe11edbda85c	535	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
mbed_official	532:fe11edbda85c	536	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
mbed_official	532:fe11edbda85c	537
mbed_official	87:085cde657901	538	/**
mbed_official	87:085cde657901	539	* @}
mbed_official	226:b062af740e40	540	*/
mbed_official	87:085cde657901	541
mbed_official	532:fe11edbda85c	542	/** @defgroup TIM_Flag_definition TIM Flag definition
mbed_official	87:085cde657901	543	* @{
mbed_official	226:b062af740e40	544	*/
mbed_official	87:085cde657901	545	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	87:085cde657901	546	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	87:085cde657901	547	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	87:085cde657901	548	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	87:085cde657901	549	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	87:085cde657901	550	#define TIM_FLAG_COM (TIM_SR_COMIF)
mbed_official	87:085cde657901	551	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	87:085cde657901	552	#define TIM_FLAG_BREAK (TIM_SR_BIF)
mbed_official	87:085cde657901	553	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	87:085cde657901	554	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	87:085cde657901	555	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	87:085cde657901	556	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	87:085cde657901	557	/**
mbed_official	87:085cde657901	558	* @}
mbed_official	87:085cde657901	559	*/
mbed_official	87:085cde657901	560
mbed_official	532:fe11edbda85c	561	/** @defgroup TIM_Clock_Source TIM Clock Source
mbed_official	87:085cde657901	562	* @{
mbed_official	226:b062af740e40	563	*/
mbed_official	87:085cde657901	564	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	87:085cde657901	565	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	87:085cde657901	566	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	87:085cde657901	567	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	87:085cde657901	568	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	87:085cde657901	569	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	87:085cde657901	570	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	87:085cde657901	571	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	87:085cde657901	572	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	87:085cde657901	573	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	87:085cde657901	574	/**
mbed_official	87:085cde657901	575	* @}
mbed_official	226:b062af740e40	576	*/
mbed_official	87:085cde657901	577
mbed_official	532:fe11edbda85c	578	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
mbed_official	87:085cde657901	579	* @{
mbed_official	87:085cde657901	580	*/
mbed_official	87:085cde657901	581	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	87:085cde657901	582	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	87:085cde657901	583	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	87:085cde657901	584	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	87:085cde657901	585	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	87:085cde657901	586	/**
mbed_official	87:085cde657901	587	* @}
mbed_official	87:085cde657901	588	*/
mbed_official	226:b062af740e40	589
mbed_official	532:fe11edbda85c	590	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
mbed_official	87:085cde657901	591	* @{
mbed_official	226:b062af740e40	592	*/
mbed_official	532:fe11edbda85c	593	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	532:fe11edbda85c	594	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	532:fe11edbda85c	595	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	532:fe11edbda85c	596	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	87:085cde657901	597	/**
mbed_official	87:085cde657901	598	* @}
mbed_official	226:b062af740e40	599	*/
mbed_official	226:b062af740e40	600
mbed_official	532:fe11edbda85c	601	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
mbed_official	87:085cde657901	602	* @{
mbed_official	87:085cde657901	603	*/
mbed_official	87:085cde657901	604	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official	87:085cde657901	605	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official	87:085cde657901	606	/**
mbed_official	87:085cde657901	607	* @}
mbed_official	87:085cde657901	608	*/
mbed_official	87:085cde657901	609
mbed_official	532:fe11edbda85c	610	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
mbed_official	87:085cde657901	611	* @{
mbed_official	87:085cde657901	612	*/
mbed_official	87:085cde657901	613	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	87:085cde657901	614	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	87:085cde657901	615	/**
mbed_official	87:085cde657901	616	* @}
mbed_official	226:b062af740e40	617	*/
mbed_official	87:085cde657901	618
mbed_official	532:fe11edbda85c	619	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
mbed_official	87:085cde657901	620	* @{
mbed_official	87:085cde657901	621	*/
mbed_official	87:085cde657901	622	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	87:085cde657901	623	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	87:085cde657901	624	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	87:085cde657901	625	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	87:085cde657901	626	/**
mbed_official	87:085cde657901	627	* @}
mbed_official	87:085cde657901	628	*/
mbed_official	87:085cde657901	629
mbed_official	532:fe11edbda85c	630	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
mbed_official	369:2e96f1b71984	631	* @{
mbed_official	369:2e96f1b71984	632	*/
mbed_official	369:2e96f1b71984	633	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
mbed_official	532:fe11edbda85c	634	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	635	/**
mbed_official	369:2e96f1b71984	636	* @}
mbed_official	369:2e96f1b71984	637	*/
mbed_official	369:2e96f1b71984	638
mbed_official	532:fe11edbda85c	639	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
mbed_official	369:2e96f1b71984	640	* @{
mbed_official	369:2e96f1b71984	641	*/
mbed_official	369:2e96f1b71984	642	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
mbed_official	369:2e96f1b71984	643	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	644	/**
mbed_official	369:2e96f1b71984	645	* @}
mbed_official	369:2e96f1b71984	646	*/
mbed_official	532:fe11edbda85c	647
mbed_official	532:fe11edbda85c	648	/** @defgroup TIM_Lock_level TIM Lock level
mbed_official	369:2e96f1b71984	649	* @{
mbed_official	369:2e96f1b71984	650	*/
mbed_official	369:2e96f1b71984	651	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	652	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
mbed_official	369:2e96f1b71984	653	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
mbed_official	369:2e96f1b71984	654	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
mbed_official	369:2e96f1b71984	655	/**
mbed_official	369:2e96f1b71984	656	* @}
mbed_official	369:2e96f1b71984	657	*/
mbed_official	532:fe11edbda85c	658	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
mbed_official	369:2e96f1b71984	659	* @{
mbed_official	369:2e96f1b71984	660	*/
mbed_official	369:2e96f1b71984	661	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
mbed_official	369:2e96f1b71984	662	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	663	/**
mbed_official	369:2e96f1b71984	664	* @}
mbed_official	369:2e96f1b71984	665	*/
mbed_official	532:fe11edbda85c	666
mbed_official	532:fe11edbda85c	667	/** @defgroup TIM_Break_Polarity TIM Break Polarity
mbed_official	369:2e96f1b71984	668	* @{
mbed_official	369:2e96f1b71984	669	*/
mbed_official	369:2e96f1b71984	670	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	671	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
mbed_official	369:2e96f1b71984	672	/**
mbed_official	369:2e96f1b71984	673	* @}
mbed_official	369:2e96f1b71984	674	*/
mbed_official	532:fe11edbda85c	675
mbed_official	532:fe11edbda85c	676	/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
mbed_official	369:2e96f1b71984	677	* @{
mbed_official	369:2e96f1b71984	678	*/
mbed_official	369:2e96f1b71984	679	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
mbed_official	369:2e96f1b71984	680	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	681	/**
mbed_official	369:2e96f1b71984	682	* @}
mbed_official	369:2e96f1b71984	683	*/
mbed_official	369:2e96f1b71984	684
mbed_official	532:fe11edbda85c	685	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
mbed_official	369:2e96f1b71984	686	* @{
mbed_official	369:2e96f1b71984	687	*/
mbed_official	369:2e96f1b71984	688	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	689	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	369:2e96f1b71984	690	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	369:2e96f1b71984	691	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	369:2e96f1b71984	692	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	369:2e96f1b71984	693	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	369:2e96f1b71984	694	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	532:fe11edbda85c	695	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	369:2e96f1b71984	696	/**
mbed_official	369:2e96f1b71984	697	* @}
mbed_official	369:2e96f1b71984	698	*/
mbed_official	532:fe11edbda85c	699
mbed_official	532:fe11edbda85c	700	/** @defgroup TIM_Slave_Mode TIM Slave Mode
mbed_official	87:085cde657901	701	* @{
mbed_official	87:085cde657901	702	*/
mbed_official	87:085cde657901	703	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	704	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
mbed_official	87:085cde657901	705	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
mbed_official	87:085cde657901	706	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
mbed_official	87:085cde657901	707	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
mbed_official	87:085cde657901	708	/**
mbed_official	87:085cde657901	709	* @}
mbed_official	87:085cde657901	710	*/
mbed_official	87:085cde657901	711
mbed_official	532:fe11edbda85c	712	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
mbed_official	369:2e96f1b71984	713	* @{
mbed_official	369:2e96f1b71984	714	*/
mbed_official	369:2e96f1b71984	715	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	369:2e96f1b71984	716	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	717	/**
mbed_official	369:2e96f1b71984	718	* @}
mbed_official	369:2e96f1b71984	719	*/
mbed_official	532:fe11edbda85c	720
mbed_official	532:fe11edbda85c	721	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
mbed_official	87:085cde657901	722	* @{
mbed_official	87:085cde657901	723	*/
mbed_official	87:085cde657901	724	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	87:085cde657901	725	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	87:085cde657901	726	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	87:085cde657901	727	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	87:085cde657901	728	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	87:085cde657901	729	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	87:085cde657901	730	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	87:085cde657901	731	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	87:085cde657901	732	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	87:085cde657901	733	/**
mbed_official	87:085cde657901	734	* @}
mbed_official	87:085cde657901	735	*/
mbed_official	87:085cde657901	736
mbed_official	532:fe11edbda85c	737	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
mbed_official	87:085cde657901	738	* @{
mbed_official	87:085cde657901	739	*/
mbed_official	87:085cde657901	740	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	87:085cde657901	741	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	87:085cde657901	742	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	87:085cde657901	743	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	87:085cde657901	744	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	87:085cde657901	745	/**
mbed_official	87:085cde657901	746	* @}
mbed_official	87:085cde657901	747	*/
mbed_official	87:085cde657901	748
mbed_official	532:fe11edbda85c	749	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
mbed_official	87:085cde657901	750	* @{
mbed_official	226:b062af740e40	751	*/
mbed_official	87:085cde657901	752	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	87:085cde657901	753	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	87:085cde657901	754	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	87:085cde657901	755	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	87:085cde657901	756	/**
mbed_official	87:085cde657901	757	* @}
mbed_official	87:085cde657901	758	*/
mbed_official	87:085cde657901	759
mbed_official	87:085cde657901	760
mbed_official	532:fe11edbda85c	761	/** @defgroup TIM_TI1_Selection TIM TI1 Selection
mbed_official	87:085cde657901	762	* @{
mbed_official	87:085cde657901	763	*/
mbed_official	87:085cde657901	764	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	87:085cde657901	765	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	87:085cde657901	766	/**
mbed_official	87:085cde657901	767	* @}
mbed_official	87:085cde657901	768	*/
mbed_official	226:b062af740e40	769
mbed_official	532:fe11edbda85c	770	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
mbed_official	87:085cde657901	771	* @{
mbed_official	87:085cde657901	772	*/
mbed_official	532:fe11edbda85c	773	#define TIM_DMABASE_CR1 (0x00000000)
mbed_official	532:fe11edbda85c	774	#define TIM_DMABASE_CR2 (0x00000001)
mbed_official	532:fe11edbda85c	775	#define TIM_DMABASE_SMCR (0x00000002)
mbed_official	532:fe11edbda85c	776	#define TIM_DMABASE_DIER (0x00000003)
mbed_official	532:fe11edbda85c	777	#define TIM_DMABASE_SR (0x00000004)
mbed_official	532:fe11edbda85c	778	#define TIM_DMABASE_EGR (0x00000005)
mbed_official	532:fe11edbda85c	779	#define TIM_DMABASE_CCMR1 (0x00000006)
mbed_official	532:fe11edbda85c	780	#define TIM_DMABASE_CCMR2 (0x00000007)
mbed_official	532:fe11edbda85c	781	#define TIM_DMABASE_CCER (0x00000008)
mbed_official	532:fe11edbda85c	782	#define TIM_DMABASE_CNT (0x00000009)
mbed_official	532:fe11edbda85c	783	#define TIM_DMABASE_PSC (0x0000000A)
mbed_official	532:fe11edbda85c	784	#define TIM_DMABASE_ARR (0x0000000B)
mbed_official	532:fe11edbda85c	785	#define TIM_DMABASE_RCR (0x0000000C)
mbed_official	532:fe11edbda85c	786	#define TIM_DMABASE_CCR1 (0x0000000D)
mbed_official	532:fe11edbda85c	787	#define TIM_DMABASE_CCR2 (0x0000000E)
mbed_official	532:fe11edbda85c	788	#define TIM_DMABASE_CCR3 (0x0000000F)
mbed_official	532:fe11edbda85c	789	#define TIM_DMABASE_CCR4 (0x00000010)
mbed_official	532:fe11edbda85c	790	#define TIM_DMABASE_BDTR (0x00000011)
mbed_official	532:fe11edbda85c	791	#define TIM_DMABASE_DCR (0x00000012)
mbed_official	532:fe11edbda85c	792	#define TIM_DMABASE_OR (0x00000013)
mbed_official	87:085cde657901	793	/**
mbed_official	87:085cde657901	794	* @}
mbed_official	87:085cde657901	795	*/
mbed_official	87:085cde657901	796
mbed_official	532:fe11edbda85c	797	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
mbed_official	87:085cde657901	798	* @{
mbed_official	87:085cde657901	799	*/
mbed_official	532:fe11edbda85c	800	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
mbed_official	532:fe11edbda85c	801	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
mbed_official	532:fe11edbda85c	802	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
mbed_official	532:fe11edbda85c	803	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
mbed_official	532:fe11edbda85c	804	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
mbed_official	532:fe11edbda85c	805	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
mbed_official	532:fe11edbda85c	806	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
mbed_official	532:fe11edbda85c	807	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
mbed_official	532:fe11edbda85c	808	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
mbed_official	532:fe11edbda85c	809	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
mbed_official	532:fe11edbda85c	810	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
mbed_official	532:fe11edbda85c	811	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
mbed_official	532:fe11edbda85c	812	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
mbed_official	532:fe11edbda85c	813	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
mbed_official	532:fe11edbda85c	814	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
mbed_official	532:fe11edbda85c	815	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
mbed_official	532:fe11edbda85c	816	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
mbed_official	532:fe11edbda85c	817	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
mbed_official	87:085cde657901	818	/**
mbed_official	87:085cde657901	819	* @}
mbed_official	226:b062af740e40	820	*/
mbed_official	226:b062af740e40	821
mbed_official	532:fe11edbda85c	822	/** @defgroup DMA_Handle_index DMA Handle index
mbed_official	87:085cde657901	823	* @{
mbed_official	87:085cde657901	824	*/
mbed_official	87:085cde657901	825	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	87:085cde657901	826	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	87:085cde657901	827	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	87:085cde657901	828	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	87:085cde657901	829	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	87:085cde657901	830	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
mbed_official	87:085cde657901	831	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	87:085cde657901	832	/**
mbed_official	87:085cde657901	833	* @}
mbed_official	87:085cde657901	834	*/
mbed_official	87:085cde657901	835
mbed_official	532:fe11edbda85c	836	/** @defgroup Channel_CC_State Channel CC State
mbed_official	87:085cde657901	837	* @{
mbed_official	87:085cde657901	838	*/
mbed_official	87:085cde657901	839	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	87:085cde657901	840	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	841	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
mbed_official	87:085cde657901	842	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	843	/**
mbed_official	87:085cde657901	844	* @}
mbed_official	87:085cde657901	845	*/
mbed_official	87:085cde657901	846
mbed_official	87:085cde657901	847	/**
mbed_official	87:085cde657901	848	* @}
mbed_official	87:085cde657901	849	*/
mbed_official	87:085cde657901	850
mbed_official	87:085cde657901	851	/* Exported macro ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	852	/** @defgroup TIM_Exported_Macros TIM Exported Macros
mbed_official	532:fe11edbda85c	853	* @{
mbed_official	532:fe11edbda85c	854	*/
mbed_official	226:b062af740e40	855	/** @brief Reset TIM handle state
mbed_official	226:b062af740e40	856	* @param __HANDLE__: TIM handle
mbed_official	226:b062af740e40	857	* @retval None
mbed_official	226:b062af740e40	858	*/
mbed_official	226:b062af740e40	859	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
mbed_official	226:b062af740e40	860
mbed_official	87:085cde657901	861	/**
mbed_official	87:085cde657901	862	* @brief Enable the TIM peripheral.
mbed_official	87:085cde657901	863	* @param __HANDLE__: TIM handle
mbed_official	87:085cde657901	864	* @retval None
mbed_official	87:085cde657901	865	*/
mbed_official	87:085cde657901	866	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	87:085cde657901	867
mbed_official	87:085cde657901	868	/**
mbed_official	87:085cde657901	869	* @brief Enable the TIM main Output.
mbed_official	87:085cde657901	870	* @param __HANDLE__: TIM handle
mbed_official	87:085cde657901	871	* @retval None
mbed_official	87:085cde657901	872	*/
mbed_official	87:085cde657901	873	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
mbed_official	87:085cde657901	874
mbed_official	87:085cde657901	875
mbed_official	87:085cde657901	876	/**
mbed_official	87:085cde657901	877	* @brief Disable the TIM peripheral.
mbed_official	87:085cde657901	878	* @param __HANDLE__: TIM handle
mbed_official	87:085cde657901	879	* @retval None
mbed_official	87:085cde657901	880	*/
mbed_official	87:085cde657901	881	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	87:085cde657901	882	do { \
mbed_official	532:fe11edbda85c	883	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
mbed_official	87:085cde657901	884	{ \
mbed_official	532:fe11edbda85c	885	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
mbed_official	87:085cde657901	886	{ \
mbed_official	87:085cde657901	887	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	87:085cde657901	888	} \
mbed_official	87:085cde657901	889	} \
mbed_official	87:085cde657901	890	} while(0)
mbed_official	87:085cde657901	891
mbed_official	226:b062af740e40	892	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
mbed_official	226:b062af740e40	893	channels have been disabled */
mbed_official	87:085cde657901	894	/**
mbed_official	87:085cde657901	895	* @brief Disable the TIM main Output.
mbed_official	87:085cde657901	896	* @param __HANDLE__: TIM handle
mbed_official	87:085cde657901	897	* @retval None
mbed_official	87:085cde657901	898	*/
mbed_official	87:085cde657901	899	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
mbed_official	87:085cde657901	900	do { \
mbed_official	532:fe11edbda85c	901	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
mbed_official	87:085cde657901	902	{ \
mbed_official	532:fe11edbda85c	903	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
mbed_official	87:085cde657901	904	{ \
mbed_official	87:085cde657901	905	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
mbed_official	87:085cde657901	906	} \
mbed_official	87:085cde657901	907	} \
mbed_official	226:b062af740e40	908	} while(0)
mbed_official	87:085cde657901	909
mbed_official	87:085cde657901	910	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	87:085cde657901	911	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	87:085cde657901	912	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	87:085cde657901	913	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	87:085cde657901	914	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	369:2e96f1b71984	915	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
mbed_official	87:085cde657901	916
mbed_official	532:fe11edbda85c	917	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	369:2e96f1b71984	918	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
mbed_official	87:085cde657901	919
mbed_official	532:fe11edbda85c	920	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	532:fe11edbda85c	921	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
mbed_official	87:085cde657901	922
mbed_official	532:fe11edbda85c	923	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	87:085cde657901	924	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	87:085cde657901	925	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	87:085cde657901	926	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	87:085cde657901	927	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	87:085cde657901	928
mbed_official	532:fe11edbda85c	929	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
mbed_official	87:085cde657901	930	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
mbed_official	87:085cde657901	931	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
mbed_official	87:085cde657901	932	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
mbed_official	87:085cde657901	933	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
mbed_official	226:b062af740e40	934
mbed_official	532:fe11edbda85c	935	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
mbed_official	532:fe11edbda85c	936	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
mbed_official	532:fe11edbda85c	937	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
mbed_official	532:fe11edbda85c	938	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
mbed_official	532:fe11edbda85c	939	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
mbed_official	532:fe11edbda85c	940
mbed_official	532:fe11edbda85c	941	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
mbed_official	532:fe11edbda85c	942	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
mbed_official	532:fe11edbda85c	943	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
mbed_official	532:fe11edbda85c	944	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
mbed_official	532:fe11edbda85c	945	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
mbed_official	532:fe11edbda85c	946
mbed_official	87:085cde657901	947	/**
mbed_official	87:085cde657901	948	* @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official	87:085cde657901	949	* calling another time ConfigChannel function.
mbed_official	87:085cde657901	950	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	951	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	87:085cde657901	952	* This parameter can be one of the following values:
mbed_official	87:085cde657901	953	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	954	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	955	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	956	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	957	* @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official	87:085cde657901	958	* @retval None
mbed_official	87:085cde657901	959	*/
mbed_official	532:fe11edbda85c	960	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official	87:085cde657901	961	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official	87:085cde657901	962
mbed_official	87:085cde657901	963	/**
mbed_official	226:b062af740e40	964	* @brief Gets the TIM Capture Compare Register value on runtime
mbed_official	226:b062af740e40	965	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	966	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official	226:b062af740e40	967	* This parameter can be one of the following values:
mbed_official	226:b062af740e40	968	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official	226:b062af740e40	969	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official	226:b062af740e40	970	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official	226:b062af740e40	971	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official	226:b062af740e40	972	* @retval None
mbed_official	226:b062af740e40	973	*/
mbed_official	532:fe11edbda85c	974	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
mbed_official	226:b062af740e40	975	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
mbed_official	226:b062af740e40	976
mbed_official	226:b062af740e40	977	/**
mbed_official	87:085cde657901	978	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	87:085cde657901	979	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	980	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	87:085cde657901	981	* @retval None
mbed_official	87:085cde657901	982	*/
mbed_official	532:fe11edbda85c	983	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	226:b062af740e40	984
mbed_official	226:b062af740e40	985	/**
mbed_official	226:b062af740e40	986	* @brief Gets the TIM Counter Register value on runtime.
mbed_official	226:b062af740e40	987	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	988	* @retval None
mbed_official	226:b062af740e40	989	*/
mbed_official	532:fe11edbda85c	990	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
mbed_official	87:085cde657901	991
mbed_official	87:085cde657901	992	/**
mbed_official	87:085cde657901	993	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	87:085cde657901	994	* another time any Init function.
mbed_official	87:085cde657901	995	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	996	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	87:085cde657901	997	* @retval None
mbed_official	87:085cde657901	998	*/
mbed_official	532:fe11edbda85c	999	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
mbed_official	226:b062af740e40	1000	do{ \
mbed_official	226:b062af740e40	1001	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	226:b062af740e40	1002	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	87:085cde657901	1003	} while(0)
mbed_official	226:b062af740e40	1004	/**
mbed_official	226:b062af740e40	1005	* @brief Gets the TIM Autoreload Register value on runtime
mbed_official	226:b062af740e40	1006	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	1007	* @retval None
mbed_official	226:b062af740e40	1008	*/
mbed_official	532:fe11edbda85c	1009	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
mbed_official	87:085cde657901	1010
mbed_official	87:085cde657901	1011	/**
mbed_official	87:085cde657901	1012	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	87:085cde657901	1013	* another time any Init function.
mbed_official	87:085cde657901	1014	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	1015	* @param __CKD__: specifies the clock division value.
mbed_official	87:085cde657901	1016	* This parameter can be one of the following value:
mbed_official	87:085cde657901	1017	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	87:085cde657901	1018	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	226:b062af740e40	1019	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	87:085cde657901	1020	* @retval None
mbed_official	87:085cde657901	1021	*/
mbed_official	532:fe11edbda85c	1022	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
mbed_official	226:b062af740e40	1023	do{ \
mbed_official	87:085cde657901	1024	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
mbed_official	226:b062af740e40	1025	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	87:085cde657901	1026	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	87:085cde657901	1027	} while(0)
mbed_official	226:b062af740e40	1028	/**
mbed_official	226:b062af740e40	1029	* @brief Gets the TIM Clock Division value on runtime
mbed_official	226:b062af740e40	1030	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	1031	* @retval None
mbed_official	226:b062af740e40	1032	*/
mbed_official	532:fe11edbda85c	1033	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
mbed_official	226:b062af740e40	1034
mbed_official	87:085cde657901	1035	/**
mbed_official	87:085cde657901	1036	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	87:085cde657901	1037	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	87:085cde657901	1038	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	1039	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	87:085cde657901	1040	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1041	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1042	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1043	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1044	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1045	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	87:085cde657901	1046	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1047	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	87:085cde657901	1048	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	87:085cde657901	1049	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	87:085cde657901	1050	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	87:085cde657901	1051	* @retval None
mbed_official	87:085cde657901	1052	*/
mbed_official	532:fe11edbda85c	1053	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	87:085cde657901	1054	do{ \
mbed_official	532:fe11edbda85c	1055	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
mbed_official	532:fe11edbda85c	1056	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	226:b062af740e40	1057	} while(0)
mbed_official	87:085cde657901	1058
mbed_official	87:085cde657901	1059	/**
mbed_official	226:b062af740e40	1060	* @brief Gets the TIM Input Capture prescaler on runtime
mbed_official	226:b062af740e40	1061	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	1062	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	226:b062af740e40	1063	* This parameter can be one of the following values:
mbed_official	226:b062af740e40	1064	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
mbed_official	226:b062af740e40	1065	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
mbed_official	226:b062af740e40	1066	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
mbed_official	226:b062af740e40	1067	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
mbed_official	226:b062af740e40	1068	* @retval None
mbed_official	226:b062af740e40	1069	*/
mbed_official	532:fe11edbda85c	1070	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
mbed_official	226:b062af740e40	1071	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
mbed_official	226:b062af740e40	1072	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
mbed_official	226:b062af740e40	1073	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
mbed_official	226:b062af740e40	1074	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
mbed_official	532:fe11edbda85c	1075
mbed_official	532:fe11edbda85c	1076	/**
mbed_official	532:fe11edbda85c	1077	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	532:fe11edbda85c	1078	* @param __HANDLE__: TIM handle.
mbed_official	532:fe11edbda85c	1079	* @note When the USR bit of the TIMx_CR1 register is set, only counter
mbed_official	532:fe11edbda85c	1080	* overflow/underflow generates an update interrupt or DMA request (if
mbed_official	532:fe11edbda85c	1081	* enabled)
mbed_official	532:fe11edbda85c	1082	* @retval None
mbed_official	532:fe11edbda85c	1083	*/
mbed_official	532:fe11edbda85c	1084	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
mbed_official	532:fe11edbda85c	1085	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
mbed_official	532:fe11edbda85c	1086
mbed_official	532:fe11edbda85c	1087	/**
mbed_official	532:fe11edbda85c	1088	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	532:fe11edbda85c	1089	* @param __HANDLE__: TIM handle.
mbed_official	532:fe11edbda85c	1090	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
mbed_official	532:fe11edbda85c	1091	* following events generate an update interrupt or DMA request (if
mbed_official	532:fe11edbda85c	1092	* enabled):
mbed_official	532:fe11edbda85c	1093	* Counter overflow/underflow
mbed_official	532:fe11edbda85c	1094	* Setting the UG bit
mbed_official	532:fe11edbda85c	1095	* Update generation through the slave mode controller
mbed_official	532:fe11edbda85c	1096	* @retval None
mbed_official	532:fe11edbda85c	1097	*/
mbed_official	532:fe11edbda85c	1098	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
mbed_official	532:fe11edbda85c	1099	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
mbed_official	532:fe11edbda85c	1100
mbed_official	532:fe11edbda85c	1101	/**
mbed_official	532:fe11edbda85c	1102	* @brief Sets the TIM Capture x input polarity on runtime.
mbed_official	532:fe11edbda85c	1103	* @param __HANDLE__: TIM handle.
mbed_official	532:fe11edbda85c	1104	* @param __CHANNEL__: TIM Channels to be configured.
mbed_official	532:fe11edbda85c	1105	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	1106	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	532:fe11edbda85c	1107	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	532:fe11edbda85c	1108	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	532:fe11edbda85c	1109	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	532:fe11edbda85c	1110	* @param __POLARITY__: Polarity for TIx source
mbed_official	532:fe11edbda85c	1111	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
mbed_official	532:fe11edbda85c	1112	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
mbed_official	532:fe11edbda85c	1113	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
mbed_official	532:fe11edbda85c	1114	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
mbed_official	532:fe11edbda85c	1115	* @retval None
mbed_official	532:fe11edbda85c	1116	*/
mbed_official	532:fe11edbda85c	1117	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
mbed_official	532:fe11edbda85c	1118	do{ \
mbed_official	532:fe11edbda85c	1119	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
mbed_official	532:fe11edbda85c	1120	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
mbed_official	532:fe11edbda85c	1121	}while(0)
mbed_official	226:b062af740e40	1122	/**
mbed_official	87:085cde657901	1123	* @}
mbed_official	87:085cde657901	1124	*/
mbed_official	87:085cde657901	1125
mbed_official	87:085cde657901	1126	/* Include TIM HAL Extension module */
mbed_official	87:085cde657901	1127	#include "stm32f4xx_hal_tim_ex.h"
mbed_official	87:085cde657901	1128
mbed_official	87:085cde657901	1129	/* Exported functions --------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1130	/** @addtogroup TIM_Exported_Functions
mbed_official	532:fe11edbda85c	1131	* @{
mbed_official	532:fe11edbda85c	1132	*/
mbed_official	532:fe11edbda85c	1133
mbed_official	532:fe11edbda85c	1134	/** @addtogroup TIM_Exported_Functions_Group1
mbed_official	532:fe11edbda85c	1135	* @{
mbed_official	532:fe11edbda85c	1136	*/
mbed_official	87:085cde657901	1137
mbed_official	87:085cde657901	1138	/* Time Base functions ********************************************************/
mbed_official	87:085cde657901	1139	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1140	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1141	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1142	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1143	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1144	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1145	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1146	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1147	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1148	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1149	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1150	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	87:085cde657901	1151	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	532:fe11edbda85c	1152	/**
mbed_official	532:fe11edbda85c	1153	* @}
mbed_official	532:fe11edbda85c	1154	*/
mbed_official	87:085cde657901	1155
mbed_official	532:fe11edbda85c	1156	/** @addtogroup TIM_Exported_Functions_Group2
mbed_official	532:fe11edbda85c	1157	* @{
mbed_official	532:fe11edbda85c	1158	*/
mbed_official	87:085cde657901	1159	/* Timer Output Compare functions **********************************************/
mbed_official	87:085cde657901	1160	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1161	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1162	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1163	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1164	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1165	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1166	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1167	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1168	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1169	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1170	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1171	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	87:085cde657901	1172	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1173
mbed_official	532:fe11edbda85c	1174	/**
mbed_official	532:fe11edbda85c	1175	* @}
mbed_official	532:fe11edbda85c	1176	*/
mbed_official	532:fe11edbda85c	1177
mbed_official	532:fe11edbda85c	1178	/** @addtogroup TIM_Exported_Functions_Group3
mbed_official	532:fe11edbda85c	1179	* @{
mbed_official	532:fe11edbda85c	1180	*/
mbed_official	87:085cde657901	1181	/* Timer PWM functions *********************************************************/
mbed_official	87:085cde657901	1182	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1183	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1184	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1185	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1186	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1187	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1188	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1189	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1190	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1191	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1192	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1193	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	87:085cde657901	1194	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1195
mbed_official	532:fe11edbda85c	1196	/**
mbed_official	532:fe11edbda85c	1197	* @}
mbed_official	532:fe11edbda85c	1198	*/
mbed_official	532:fe11edbda85c	1199
mbed_official	532:fe11edbda85c	1200	/** @addtogroup TIM_Exported_Functions_Group4
mbed_official	532:fe11edbda85c	1201	* @{
mbed_official	532:fe11edbda85c	1202	*/
mbed_official	87:085cde657901	1203	/* Timer Input Capture functions ***********************************************/
mbed_official	87:085cde657901	1204	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1205	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1206	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1207	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1208	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1209	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1210	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1211	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1212	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1213	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1214	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1215	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	87:085cde657901	1216	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1217
mbed_official	532:fe11edbda85c	1218	/**
mbed_official	532:fe11edbda85c	1219	* @}
mbed_official	532:fe11edbda85c	1220	*/
mbed_official	532:fe11edbda85c	1221
mbed_official	532:fe11edbda85c	1222	/** @addtogroup TIM_Exported_Functions_Group5
mbed_official	532:fe11edbda85c	1223	* @{
mbed_official	532:fe11edbda85c	1224	*/
mbed_official	87:085cde657901	1225	/* Timer One Pulse functions ***************************************************/
mbed_official	87:085cde657901	1226	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	87:085cde657901	1227	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1228	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1229	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1230	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1231	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	87:085cde657901	1232	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	87:085cde657901	1233
mbed_official	87:085cde657901	1234	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1235	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	87:085cde657901	1236	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	87:085cde657901	1237
mbed_official	532:fe11edbda85c	1238	/**
mbed_official	532:fe11edbda85c	1239	* @}
mbed_official	532:fe11edbda85c	1240	*/
mbed_official	532:fe11edbda85c	1241
mbed_official	532:fe11edbda85c	1242	/** @addtogroup TIM_Exported_Functions_Group6
mbed_official	532:fe11edbda85c	1243	* @{
mbed_official	532:fe11edbda85c	1244	*/
mbed_official	87:085cde657901	1245	/* Timer Encoder functions *****************************************************/
mbed_official	87:085cde657901	1246	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	87:085cde657901	1247	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1248	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1249	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1250	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1251	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1252	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1253	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1254	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1255	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1256	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1257	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	87:085cde657901	1258	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1259
mbed_official	532:fe11edbda85c	1260	/**
mbed_official	532:fe11edbda85c	1261	* @}
mbed_official	532:fe11edbda85c	1262	*/
mbed_official	532:fe11edbda85c	1263
mbed_official	532:fe11edbda85c	1264	/** @addtogroup TIM_Exported_Functions_Group7
mbed_official	532:fe11edbda85c	1265	* @{
mbed_official	532:fe11edbda85c	1266	*/
mbed_official	87:085cde657901	1267	/* Interrupt Handler functions **********************************************/
mbed_official	87:085cde657901	1268	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1269
mbed_official	532:fe11edbda85c	1270	/**
mbed_official	532:fe11edbda85c	1271	* @}
mbed_official	532:fe11edbda85c	1272	*/
mbed_official	532:fe11edbda85c	1273
mbed_official	532:fe11edbda85c	1274	/** @addtogroup TIM_Exported_Functions_Group8
mbed_official	532:fe11edbda85c	1275	* @{
mbed_official	532:fe11edbda85c	1276	*/
mbed_official	87:085cde657901	1277	/* Control functions *********************************************************/
mbed_official	87:085cde657901	1278	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	87:085cde657901	1279	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	87:085cde657901	1280	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	87:085cde657901	1281	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	87:085cde657901	1282	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	87:085cde657901	1283	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	87:085cde657901	1284	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	87:085cde657901	1285	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	532:fe11edbda85c	1286	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	87:085cde657901	1287	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	87:085cde657901	1288	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	87:085cde657901	1289	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	87:085cde657901	1290	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	87:085cde657901	1291	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	87:085cde657901	1292	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	87:085cde657901	1293	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	87:085cde657901	1294	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1295
mbed_official	532:fe11edbda85c	1296	/**
mbed_official	532:fe11edbda85c	1297	* @}
mbed_official	532:fe11edbda85c	1298	*/
mbed_official	532:fe11edbda85c	1299
mbed_official	532:fe11edbda85c	1300	/** @addtogroup TIM_Exported_Functions_Group9
mbed_official	532:fe11edbda85c	1301	* @{
mbed_official	532:fe11edbda85c	1302	*/
mbed_official	87:085cde657901	1303	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	106:ced8cbb51063	1304	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1305	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1306	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1307	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1308	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1309	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1310
mbed_official	532:fe11edbda85c	1311	/**
mbed_official	532:fe11edbda85c	1312	* @}
mbed_official	532:fe11edbda85c	1313	*/
mbed_official	532:fe11edbda85c	1314
mbed_official	532:fe11edbda85c	1315	/** @addtogroup TIM_Exported_Functions_Group10
mbed_official	532:fe11edbda85c	1316	* @{
mbed_official	532:fe11edbda85c	1317	*/
mbed_official	87:085cde657901	1318	/* Peripheral State functions **************************************************/
mbed_official	87:085cde657901	1319	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1320	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1321	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1322	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1323	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1324	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1325
mbed_official	532:fe11edbda85c	1326	/**
mbed_official	532:fe11edbda85c	1327	* @}
mbed_official	532:fe11edbda85c	1328	*/
mbed_official	532:fe11edbda85c	1329
mbed_official	532:fe11edbda85c	1330	/**
mbed_official	532:fe11edbda85c	1331	* @}
mbed_official	532:fe11edbda85c	1332	*/
mbed_official	532:fe11edbda85c	1333
mbed_official	532:fe11edbda85c	1334	/* Private macros ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1335	/** @defgroup TIM_Private_Macros TIM Private Macros
mbed_official	532:fe11edbda85c	1336	* @{
mbed_official	532:fe11edbda85c	1337	*/
mbed_official	532:fe11edbda85c	1338
mbed_official	532:fe11edbda85c	1339	/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
mbed_official	532:fe11edbda85c	1340	* @{
mbed_official	532:fe11edbda85c	1341	*/
mbed_official	532:fe11edbda85c	1342	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	532:fe11edbda85c	1343	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	532:fe11edbda85c	1344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	532:fe11edbda85c	1345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	532:fe11edbda85c	1346	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	532:fe11edbda85c	1347
mbed_official	532:fe11edbda85c	1348	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	532:fe11edbda85c	1349	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	532:fe11edbda85c	1350	((DIV) == TIM_CLOCKDIVISION_DIV4))
mbed_official	532:fe11edbda85c	1351
mbed_official	532:fe11edbda85c	1352	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
mbed_official	532:fe11edbda85c	1353	((MODE) == TIM_OCMODE_PWM2))
mbed_official	532:fe11edbda85c	1354
mbed_official	532:fe11edbda85c	1355	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
mbed_official	532:fe11edbda85c	1356	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
mbed_official	532:fe11edbda85c	1357	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
mbed_official	532:fe11edbda85c	1358	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
mbed_official	532:fe11edbda85c	1359	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
mbed_official	532:fe11edbda85c	1360	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official	532:fe11edbda85c	1361
mbed_official	532:fe11edbda85c	1362	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1363	((STATE) == TIM_OCFAST_ENABLE))
mbed_official	532:fe11edbda85c	1364
mbed_official	532:fe11edbda85c	1365	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	532:fe11edbda85c	1366	((POLARITY) == TIM_OCPOLARITY_LOW))
mbed_official	532:fe11edbda85c	1367
mbed_official	532:fe11edbda85c	1368	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
mbed_official	532:fe11edbda85c	1369	((POLARITY) == TIM_OCNPOLARITY_LOW))
mbed_official	532:fe11edbda85c	1370
mbed_official	532:fe11edbda85c	1371	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
mbed_official	532:fe11edbda85c	1372	((STATE) == TIM_OCIDLESTATE_RESET))
mbed_official	532:fe11edbda85c	1373
mbed_official	532:fe11edbda85c	1374	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
mbed_official	532:fe11edbda85c	1375	((STATE) == TIM_OCNIDLESTATE_RESET))
mbed_official	532:fe11edbda85c	1376
mbed_official	532:fe11edbda85c	1377	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	532:fe11edbda85c	1378	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	532:fe11edbda85c	1379	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	532:fe11edbda85c	1380	((CHANNEL) == TIM_CHANNEL_4) \|\| \
mbed_official	532:fe11edbda85c	1381	((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official	532:fe11edbda85c	1382
mbed_official	532:fe11edbda85c	1383	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	532:fe11edbda85c	1384	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	532:fe11edbda85c	1385
mbed_official	532:fe11edbda85c	1386	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	532:fe11edbda85c	1387	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	532:fe11edbda85c	1388	((CHANNEL) == TIM_CHANNEL_3))
mbed_official	532:fe11edbda85c	1389
mbed_official	532:fe11edbda85c	1390	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	532:fe11edbda85c	1391	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	532:fe11edbda85c	1392	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	532:fe11edbda85c	1393
mbed_official	532:fe11edbda85c	1394	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	532:fe11edbda85c	1395	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	532:fe11edbda85c	1396	((SELECTION) == TIM_ICSELECTION_TRC))
mbed_official	532:fe11edbda85c	1397
mbed_official	532:fe11edbda85c	1398	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
mbed_official	532:fe11edbda85c	1399	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
mbed_official	532:fe11edbda85c	1400	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
mbed_official	532:fe11edbda85c	1401	((PRESCALER) == TIM_ICPSC_DIV8))
mbed_official	532:fe11edbda85c	1402
mbed_official	532:fe11edbda85c	1403	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	532:fe11edbda85c	1404	((MODE) == TIM_OPMODE_REPETITIVE))
mbed_official	532:fe11edbda85c	1405
mbed_official	532:fe11edbda85c	1406	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	532:fe11edbda85c	1407
mbed_official	532:fe11edbda85c	1408	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	532:fe11edbda85c	1409	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	532:fe11edbda85c	1410	((MODE) == TIM_ENCODERMODE_TI12))
mbed_official	532:fe11edbda85c	1411
mbed_official	532:fe11edbda85c	1412	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	532:fe11edbda85c	1413
mbed_official	532:fe11edbda85c	1414	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	532:fe11edbda85c	1415	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	532:fe11edbda85c	1416	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	532:fe11edbda85c	1417	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	532:fe11edbda85c	1418	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	532:fe11edbda85c	1419	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	532:fe11edbda85c	1420	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	532:fe11edbda85c	1421	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	532:fe11edbda85c	1422	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	532:fe11edbda85c	1423	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	532:fe11edbda85c	1424
mbed_official	532:fe11edbda85c	1425	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	532:fe11edbda85c	1426	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	532:fe11edbda85c	1427	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	532:fe11edbda85c	1428	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	532:fe11edbda85c	1429	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	532:fe11edbda85c	1430
mbed_official	532:fe11edbda85c	1431	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	532:fe11edbda85c	1432	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	532:fe11edbda85c	1433	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	532:fe11edbda85c	1434	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	532:fe11edbda85c	1435
mbed_official	532:fe11edbda85c	1436	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	532:fe11edbda85c	1437
mbed_official	532:fe11edbda85c	1438	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
mbed_official	532:fe11edbda85c	1439	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
mbed_official	532:fe11edbda85c	1440
mbed_official	532:fe11edbda85c	1441	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	532:fe11edbda85c	1442	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	532:fe11edbda85c	1443
mbed_official	532:fe11edbda85c	1444	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	532:fe11edbda85c	1445	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	532:fe11edbda85c	1446	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	532:fe11edbda85c	1447	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	532:fe11edbda85c	1448
mbed_official	532:fe11edbda85c	1449	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	532:fe11edbda85c	1450
mbed_official	532:fe11edbda85c	1451	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
mbed_official	532:fe11edbda85c	1452	((STATE) == TIM_OSSR_DISABLE))
mbed_official	532:fe11edbda85c	1453
mbed_official	532:fe11edbda85c	1454	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
mbed_official	532:fe11edbda85c	1455	((STATE) == TIM_OSSI_DISABLE))
mbed_official	532:fe11edbda85c	1456
mbed_official	532:fe11edbda85c	1457	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
mbed_official	532:fe11edbda85c	1458	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
mbed_official	532:fe11edbda85c	1459	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
mbed_official	532:fe11edbda85c	1460	((LEVEL) == TIM_LOCKLEVEL_3))
mbed_official	532:fe11edbda85c	1461
mbed_official	532:fe11edbda85c	1462	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
mbed_official	532:fe11edbda85c	1463	((STATE) == TIM_BREAK_DISABLE))
mbed_official	532:fe11edbda85c	1464
mbed_official	532:fe11edbda85c	1465	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
mbed_official	532:fe11edbda85c	1466	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
mbed_official	532:fe11edbda85c	1467
mbed_official	532:fe11edbda85c	1468	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
mbed_official	532:fe11edbda85c	1469	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
mbed_official	532:fe11edbda85c	1470
mbed_official	532:fe11edbda85c	1471	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
mbed_official	532:fe11edbda85c	1472	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
mbed_official	532:fe11edbda85c	1473	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
mbed_official	532:fe11edbda85c	1474	((SOURCE) == TIM_TRGO_OC1) \|\| \
mbed_official	532:fe11edbda85c	1475	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
mbed_official	532:fe11edbda85c	1476	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
mbed_official	532:fe11edbda85c	1477	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
mbed_official	532:fe11edbda85c	1478	((SOURCE) == TIM_TRGO_OC4REF))
mbed_official	532:fe11edbda85c	1479
mbed_official	532:fe11edbda85c	1480	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
mbed_official	532:fe11edbda85c	1481	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
mbed_official	532:fe11edbda85c	1482	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
mbed_official	532:fe11edbda85c	1483	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
mbed_official	532:fe11edbda85c	1484	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official	532:fe11edbda85c	1485
mbed_official	532:fe11edbda85c	1486	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	532:fe11edbda85c	1487	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	532:fe11edbda85c	1488
mbed_official	532:fe11edbda85c	1489	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	532:fe11edbda85c	1490	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	532:fe11edbda85c	1491	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	532:fe11edbda85c	1492	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	532:fe11edbda85c	1493	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
mbed_official	532:fe11edbda85c	1494	((SELECTION) == TIM_TS_TI1FP1) \|\| \
mbed_official	532:fe11edbda85c	1495	((SELECTION) == TIM_TS_TI2FP2) \|\| \
mbed_official	532:fe11edbda85c	1496	((SELECTION) == TIM_TS_ETRF))
mbed_official	532:fe11edbda85c	1497
mbed_official	532:fe11edbda85c	1498	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	532:fe11edbda85c	1499	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	532:fe11edbda85c	1500	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	532:fe11edbda85c	1501	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	532:fe11edbda85c	1502	((SELECTION) == TIM_TS_NONE))
mbed_official	532:fe11edbda85c	1503	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	532:fe11edbda85c	1504	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	532:fe11edbda85c	1505	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	532:fe11edbda85c	1506	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	532:fe11edbda85c	1507	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	532:fe11edbda85c	1508
mbed_official	532:fe11edbda85c	1509	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	532:fe11edbda85c	1510	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	532:fe11edbda85c	1511	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	532:fe11edbda85c	1512	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	532:fe11edbda85c	1513
mbed_official	532:fe11edbda85c	1514	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	532:fe11edbda85c	1515
mbed_official	532:fe11edbda85c	1516	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	532:fe11edbda85c	1517	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	532:fe11edbda85c	1518
mbed_official	532:fe11edbda85c	1519	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
mbed_official	532:fe11edbda85c	1520	((BASE) == TIM_DMABASE_CR2) \|\| \
mbed_official	532:fe11edbda85c	1521	((BASE) == TIM_DMABASE_SMCR) \|\| \
mbed_official	532:fe11edbda85c	1522	((BASE) == TIM_DMABASE_DIER) \|\| \
mbed_official	532:fe11edbda85c	1523	((BASE) == TIM_DMABASE_SR) \|\| \
mbed_official	532:fe11edbda85c	1524	((BASE) == TIM_DMABASE_EGR) \|\| \
mbed_official	532:fe11edbda85c	1525	((BASE) == TIM_DMABASE_CCMR1) \|\| \
mbed_official	532:fe11edbda85c	1526	((BASE) == TIM_DMABASE_CCMR2) \|\| \
mbed_official	532:fe11edbda85c	1527	((BASE) == TIM_DMABASE_CCER) \|\| \
mbed_official	532:fe11edbda85c	1528	((BASE) == TIM_DMABASE_CNT) \|\| \
mbed_official	532:fe11edbda85c	1529	((BASE) == TIM_DMABASE_PSC) \|\| \
mbed_official	532:fe11edbda85c	1530	((BASE) == TIM_DMABASE_ARR) \|\| \
mbed_official	532:fe11edbda85c	1531	((BASE) == TIM_DMABASE_RCR) \|\| \
mbed_official	532:fe11edbda85c	1532	((BASE) == TIM_DMABASE_CCR1) \|\| \
mbed_official	532:fe11edbda85c	1533	((BASE) == TIM_DMABASE_CCR2) \|\| \
mbed_official	532:fe11edbda85c	1534	((BASE) == TIM_DMABASE_CCR3) \|\| \
mbed_official	532:fe11edbda85c	1535	((BASE) == TIM_DMABASE_CCR4) \|\| \
mbed_official	532:fe11edbda85c	1536	((BASE) == TIM_DMABASE_BDTR) \|\| \
mbed_official	532:fe11edbda85c	1537	((BASE) == TIM_DMABASE_DCR) \|\| \
mbed_official	532:fe11edbda85c	1538	((BASE) == TIM_DMABASE_OR))
mbed_official	532:fe11edbda85c	1539
mbed_official	532:fe11edbda85c	1540	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
mbed_official	532:fe11edbda85c	1541	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1542	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1543	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1544	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1545	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1546	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1547	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1548	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1549	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1550	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1551	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1552	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1553	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1554	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1555	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1556	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
mbed_official	532:fe11edbda85c	1557	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
mbed_official	532:fe11edbda85c	1558
mbed_official	532:fe11edbda85c	1559	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	532:fe11edbda85c	1560	/**
mbed_official	532:fe11edbda85c	1561	* @}
mbed_official	532:fe11edbda85c	1562	*/
mbed_official	532:fe11edbda85c	1563
mbed_official	532:fe11edbda85c	1564	/** @defgroup TIM_Mask_Definitions TIM Mask Definition
mbed_official	532:fe11edbda85c	1565	* @{
mbed_official	532:fe11edbda85c	1566	*/
mbed_official	532:fe11edbda85c	1567	/* The counter of a timer instance is disabled only if all the CCx and CCxN
mbed_official	532:fe11edbda85c	1568	channels have been disabled */
mbed_official	532:fe11edbda85c	1569	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	532:fe11edbda85c	1570	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
mbed_official	532:fe11edbda85c	1571	/**
mbed_official	532:fe11edbda85c	1572	* @}
mbed_official	532:fe11edbda85c	1573	*/
mbed_official	532:fe11edbda85c	1574
mbed_official	532:fe11edbda85c	1575	/**
mbed_official	532:fe11edbda85c	1576	* @}
mbed_official	532:fe11edbda85c	1577	*/
mbed_official	532:fe11edbda85c	1578
mbed_official	532:fe11edbda85c	1579	/* Private functions ---------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1580	/** @defgroup TIM_Private_Functions TIM Private Functions
mbed_official	532:fe11edbda85c	1581	* @{
mbed_official	532:fe11edbda85c	1582	*/
mbed_official	87:085cde657901	1583	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
mbed_official	87:085cde657901	1584	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	1585	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	532:fe11edbda85c	1586	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	532:fe11edbda85c	1587	void TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	532:fe11edbda85c	1588	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	532:fe11edbda85c	1589	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official	532:fe11edbda85c	1590	/**
mbed_official	532:fe11edbda85c	1591	* @}
mbed_official	532:fe11edbda85c	1592	*/
mbed_official	532:fe11edbda85c	1593
mbed_official	87:085cde657901	1594	/**
mbed_official	87:085cde657901	1595	* @}
mbed_official	87:085cde657901	1596	*/
mbed_official	87:085cde657901	1597
mbed_official	87:085cde657901	1598	/**
mbed_official	87:085cde657901	1599	* @}
mbed_official	87:085cde657901	1600	*/
mbed_official	87:085cde657901	1601
mbed_official	87:085cde657901	1602	#ifdef __cplusplus
mbed_official	87:085cde657901	1603	}
mbed_official	87:085cde657901	1604	#endif
mbed_official	87:085cde657901	1605
mbed_official	87:085cde657901	1606	#endif /* __STM32F4xx_HAL_TIM_H */
mbed_official	87:085cde657901	1607
mbed_official	87:085cde657901	1608	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	02 Nov 2015
Imports:	14
Forks:	0
Commits:	637
Dependents:	2
Dependencies:	0
Followers:	5

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

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