Flotsam
Modified version of the mbed library for use with the Nucleo boards.
Dependents: EEPROMWrite Full-Project
Fork of
mbed-src
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c@613:bc40b8d2aec4, 2015-08-20 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Aug 20 10:45:13 2015 +0100
- Revision:
- 613:bc40b8d2aec4
- Parent:
- 532:fe11edbda85c
Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade
Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/
Nordic: update application start address in GCC linker script
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 87:085cde657901 | 1 | /** |
| mbed_official | 87:085cde657901 | 2 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 3 | * @file stm32f4xx_hal_dma.c |
| mbed_official | 87:085cde657901 | 4 | * @author MCD Application Team |
| mbed_official | 613:bc40b8d2aec4 | 5 | * @version V1.3.2 |
| mbed_official | 613:bc40b8d2aec4 | 6 | * @date 26-June-2015 |
| mbed_official | 87:085cde657901 | 7 | * @brief DMA HAL module driver. |
| mbed_official | 87:085cde657901 | 8 | * |
| mbed_official | 87:085cde657901 | 9 | * This file provides firmware functions to manage the following |
| mbed_official | 87:085cde657901 | 10 | * functionalities of the Direct Memory Access (DMA) peripheral: |
| mbed_official | 87:085cde657901 | 11 | * + Initialization and de-initialization functions |
| mbed_official | 87:085cde657901 | 12 | * + IO operation functions |
| mbed_official | 87:085cde657901 | 13 | * + Peripheral State and errors functions |
| mbed_official | 87:085cde657901 | 14 | @verbatim |
| mbed_official | 87:085cde657901 | 15 | ============================================================================== |
| mbed_official | 87:085cde657901 | 16 | ##### How to use this driver ##### |
| mbed_official | 87:085cde657901 | 17 | ============================================================================== |
| mbed_official | 87:085cde657901 | 18 | [..] |
| mbed_official | 87:085cde657901 | 19 | (#) Enable and configure the peripheral to be connected to the DMA Stream |
| mbed_official | 87:085cde657901 | 20 | (except for internal SRAM/FLASH memories: no initialization is |
| mbed_official | 87:085cde657901 | 21 | necessary) please refer to Reference manual for connection between peripherals |
| mbed_official | 87:085cde657901 | 22 | and DMA requests . |
| mbed_official | 87:085cde657901 | 23 | |
| mbed_official | 87:085cde657901 | 24 | (#) For a given Stream, program the required configuration through the following parameters: |
| mbed_official | 87:085cde657901 | 25 | Transfer Direction, Source and Destination data formats, |
| mbed_official | 87:085cde657901 | 26 | Circular, Normal or peripheral flow control mode, Stream Priority level, |
| mbed_official | 87:085cde657901 | 27 | Source and Destination Increment mode, FIFO mode and its Threshold (if needed), |
| mbed_official | 87:085cde657901 | 28 | Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. |
| mbed_official | 87:085cde657901 | 29 | |
| mbed_official | 87:085cde657901 | 30 | *** Polling mode IO operation *** |
| mbed_official | 87:085cde657901 | 31 | ================================= |
| mbed_official | 87:085cde657901 | 32 | [..] |
| mbed_official | 87:085cde657901 | 33 | (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source |
| mbed_official | 87:085cde657901 | 34 | address and destination address and the Length of data to be transferred |
| mbed_official | 87:085cde657901 | 35 | (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this |
| mbed_official | 87:085cde657901 | 36 | case a fixed Timeout can be configured by User depending from his application. |
| mbed_official | 87:085cde657901 | 37 | |
| mbed_official | 87:085cde657901 | 38 | *** Interrupt mode IO operation *** |
| mbed_official | 87:085cde657901 | 39 | =================================== |
| mbed_official | 87:085cde657901 | 40 | [..] |
| mbed_official | 87:085cde657901 | 41 | (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
| mbed_official | 87:085cde657901 | 42 | (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() |
| mbed_official | 87:085cde657901 | 43 | (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of |
| mbed_official | 87:085cde657901 | 44 | Source address and destination address and the Length of data to be transferred. In this |
| mbed_official | 87:085cde657901 | 45 | case the DMA interrupt is configured |
| mbed_official | 87:085cde657901 | 46 | (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
| mbed_official | 87:085cde657901 | 47 | (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can |
| mbed_official | 87:085cde657901 | 48 | add his own function by customization of function pointer XferCpltCallback and |
| mbed_official | 87:085cde657901 | 49 | XferErrorCallback (i.e a member of DMA handle structure). |
| mbed_official | 226:b062af740e40 | 50 | [..] |
| mbed_official | 87:085cde657901 | 51 | (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error |
| mbed_official | 87:085cde657901 | 52 | detection. |
| mbed_official | 87:085cde657901 | 53 | |
| mbed_official | 87:085cde657901 | 54 | (#) Use HAL_DMA_Abort() function to abort the current transfer |
| mbed_official | 87:085cde657901 | 55 | |
| mbed_official | 87:085cde657901 | 56 | -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. |
| mbed_official | 87:085cde657901 | 57 | |
| mbed_official | 87:085cde657901 | 58 | -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is |
| mbed_official | 87:085cde657901 | 59 | possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set |
| mbed_official | 87:085cde657901 | 60 | Half-Word data size for the peripheral to access its data register and set Word data size |
| mbed_official | 87:085cde657901 | 61 | for the Memory to gain in access time. Each two half words will be packed and written in |
| mbed_official | 87:085cde657901 | 62 | a single access to a Word in the Memory). |
| mbed_official | 87:085cde657901 | 63 | |
| mbed_official | 87:085cde657901 | 64 | -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source |
| mbed_official | 87:085cde657901 | 65 | and Destination. In this case the Peripheral Data Size will be applied to both Source |
| mbed_official | 87:085cde657901 | 66 | and Destination. |
| mbed_official | 87:085cde657901 | 67 | |
| mbed_official | 87:085cde657901 | 68 | *** DMA HAL driver macros list *** |
| mbed_official | 87:085cde657901 | 69 | ============================================= |
| mbed_official | 87:085cde657901 | 70 | [..] |
| mbed_official | 87:085cde657901 | 71 | Below the list of most used macros in DMA HAL driver. |
| mbed_official | 87:085cde657901 | 72 | |
| mbed_official | 87:085cde657901 | 73 | (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 74 | (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 75 | (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. |
| mbed_official | 87:085cde657901 | 76 | (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags. |
| mbed_official | 87:085cde657901 | 77 | (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags. |
| mbed_official | 87:085cde657901 | 78 | (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. |
| mbed_official | 87:085cde657901 | 79 | (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. |
| mbed_official | 106:ced8cbb51063 | 80 | (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. |
| mbed_official | 87:085cde657901 | 81 | |
| mbed_official | 87:085cde657901 | 82 | [..] |
| mbed_official | 87:085cde657901 | 83 | (@) You can refer to the DMA HAL driver header file for more useful macros |
| mbed_official | 87:085cde657901 | 84 | |
| mbed_official | 87:085cde657901 | 85 | @endverbatim |
| mbed_official | 87:085cde657901 | 86 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 87 | * @attention |
| mbed_official | 87:085cde657901 | 88 | * |
| mbed_official | 532:fe11edbda85c | 89 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 87:085cde657901 | 90 | * |
| mbed_official | 87:085cde657901 | 91 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 87:085cde657901 | 92 | * are permitted provided that the following conditions are met: |
| mbed_official | 87:085cde657901 | 93 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 87:085cde657901 | 94 | * this list of conditions and the following disclaimer. |
| mbed_official | 87:085cde657901 | 95 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 87:085cde657901 | 96 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 87:085cde657901 | 97 | * and/or other materials provided with the distribution. |
| mbed_official | 87:085cde657901 | 98 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 87:085cde657901 | 99 | * may be used to endorse or promote products derived from this software |
| mbed_official | 87:085cde657901 | 100 | * without specific prior written permission. |
| mbed_official | 87:085cde657901 | 101 | * |
| mbed_official | 87:085cde657901 | 102 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 87:085cde657901 | 103 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 87:085cde657901 | 104 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 87:085cde657901 | 105 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 87:085cde657901 | 106 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 87:085cde657901 | 107 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 87:085cde657901 | 108 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 87:085cde657901 | 109 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 87:085cde657901 | 110 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 87:085cde657901 | 111 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 87:085cde657901 | 112 | * |
| mbed_official | 87:085cde657901 | 113 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 114 | */ |
| mbed_official | 87:085cde657901 | 115 | |
| mbed_official | 87:085cde657901 | 116 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 117 | #include "stm32f4xx_hal.h" |
| mbed_official | 87:085cde657901 | 118 | |
| mbed_official | 87:085cde657901 | 119 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 87:085cde657901 | 120 | * @{ |
| mbed_official | 87:085cde657901 | 121 | */ |
| mbed_official | 87:085cde657901 | 122 | |
| mbed_official | 532:fe11edbda85c | 123 | /** @defgroup DMA DMA |
| mbed_official | 87:085cde657901 | 124 | * @brief DMA HAL module driver |
| mbed_official | 87:085cde657901 | 125 | * @{ |
| mbed_official | 87:085cde657901 | 126 | */ |
| mbed_official | 87:085cde657901 | 127 | |
| mbed_official | 87:085cde657901 | 128 | #ifdef HAL_DMA_MODULE_ENABLED |
| mbed_official | 87:085cde657901 | 129 | |
| mbed_official | 532:fe11edbda85c | 130 | /* Private types -------------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 131 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 132 | /* Private constants ---------------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 133 | /** @addtogroup DMA_Private_Constants |
| mbed_official | 532:fe11edbda85c | 134 | * @{ |
| mbed_official | 532:fe11edbda85c | 135 | */ |
| mbed_official | 532:fe11edbda85c | 136 | #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ |
| mbed_official | 532:fe11edbda85c | 137 | /** |
| mbed_official | 532:fe11edbda85c | 138 | * @} |
| mbed_official | 532:fe11edbda85c | 139 | */ |
| mbed_official | 532:fe11edbda85c | 140 | /* Private macros ------------------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 141 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 142 | /** @addtogroup DMA_Private_Functions |
| mbed_official | 532:fe11edbda85c | 143 | * @{ |
| mbed_official | 532:fe11edbda85c | 144 | */ |
| mbed_official | 87:085cde657901 | 145 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| mbed_official | 532:fe11edbda85c | 146 | /** |
| mbed_official | 532:fe11edbda85c | 147 | * @} |
| mbed_official | 532:fe11edbda85c | 148 | */ |
| mbed_official | 532:fe11edbda85c | 149 | |
| mbed_official | 532:fe11edbda85c | 150 | /* Exported functions ---------------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 151 | /** @addtogroup DMA_Exported_Functions |
| mbed_official | 87:085cde657901 | 152 | * @{ |
| mbed_official | 87:085cde657901 | 153 | */ |
| mbed_official | 87:085cde657901 | 154 | |
| mbed_official | 532:fe11edbda85c | 155 | /** @addtogroup DMA_Exported_Functions_Group1 |
| mbed_official | 532:fe11edbda85c | 156 | * |
| mbed_official | 87:085cde657901 | 157 | @verbatim |
| mbed_official | 87:085cde657901 | 158 | =============================================================================== |
| mbed_official | 87:085cde657901 | 159 | ##### Initialization and de-initialization functions ##### |
| mbed_official | 87:085cde657901 | 160 | =============================================================================== |
| mbed_official | 87:085cde657901 | 161 | [..] |
| mbed_official | 87:085cde657901 | 162 | This section provides functions allowing to initialize the DMA Stream source |
| mbed_official | 87:085cde657901 | 163 | and destination addresses, incrementation and data sizes, transfer direction, |
| mbed_official | 87:085cde657901 | 164 | circular/normal mode selection, memory-to-memory mode selection and Stream priority value. |
| mbed_official | 87:085cde657901 | 165 | [..] |
| mbed_official | 87:085cde657901 | 166 | The HAL_DMA_Init() function follows the DMA configuration procedures as described in |
| mbed_official | 87:085cde657901 | 167 | reference manual. |
| mbed_official | 87:085cde657901 | 168 | |
| mbed_official | 87:085cde657901 | 169 | @endverbatim |
| mbed_official | 87:085cde657901 | 170 | * @{ |
| mbed_official | 87:085cde657901 | 171 | */ |
| mbed_official | 87:085cde657901 | 172 | |
| mbed_official | 87:085cde657901 | 173 | /** |
| mbed_official | 87:085cde657901 | 174 | * @brief Initializes the DMA according to the specified |
| mbed_official | 87:085cde657901 | 175 | * parameters in the DMA_InitTypeDef and create the associated handle. |
| mbed_official | 87:085cde657901 | 176 | * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 177 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 178 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 179 | */ |
| mbed_official | 87:085cde657901 | 180 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
| mbed_official | 87:085cde657901 | 181 | { |
| mbed_official | 87:085cde657901 | 182 | uint32_t tmp = 0; |
| mbed_official | 87:085cde657901 | 183 | |
| mbed_official | 87:085cde657901 | 184 | /* Check the DMA peripheral state */ |
| mbed_official | 613:bc40b8d2aec4 | 185 | if(hdma == NULL) |
| mbed_official | 87:085cde657901 | 186 | { |
| mbed_official | 87:085cde657901 | 187 | return HAL_ERROR; |
| mbed_official | 87:085cde657901 | 188 | } |
| mbed_official | 87:085cde657901 | 189 | |
| mbed_official | 87:085cde657901 | 190 | /* Check the parameters */ |
| mbed_official | 87:085cde657901 | 191 | assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); |
| mbed_official | 87:085cde657901 | 192 | assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); |
| mbed_official | 87:085cde657901 | 193 | assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
| mbed_official | 87:085cde657901 | 194 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
| mbed_official | 87:085cde657901 | 195 | assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
| mbed_official | 87:085cde657901 | 196 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
| mbed_official | 87:085cde657901 | 197 | assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
| mbed_official | 87:085cde657901 | 198 | assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
| mbed_official | 87:085cde657901 | 199 | assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
| mbed_official | 87:085cde657901 | 200 | assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); |
| mbed_official | 87:085cde657901 | 201 | /* Check the memory burst, peripheral burst and FIFO threshold parameters only |
| mbed_official | 87:085cde657901 | 202 | when FIFO mode is enabled */ |
| mbed_official | 87:085cde657901 | 203 | if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) |
| mbed_official | 87:085cde657901 | 204 | { |
| mbed_official | 87:085cde657901 | 205 | assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); |
| mbed_official | 87:085cde657901 | 206 | assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); |
| mbed_official | 87:085cde657901 | 207 | assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); |
| mbed_official | 87:085cde657901 | 208 | } |
| mbed_official | 87:085cde657901 | 209 | |
| mbed_official | 87:085cde657901 | 210 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 211 | hdma->State = HAL_DMA_STATE_BUSY; |
| mbed_official | 87:085cde657901 | 212 | |
| mbed_official | 87:085cde657901 | 213 | /* Get the CR register value */ |
| mbed_official | 87:085cde657901 | 214 | tmp = hdma->Instance->CR; |
| mbed_official | 87:085cde657901 | 215 | |
| mbed_official | 532:fe11edbda85c | 216 | /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ |
| mbed_official | 87:085cde657901 | 217 | tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ |
| mbed_official | 87:085cde657901 | 218 | DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ |
| mbed_official | 87:085cde657901 | 219 | DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ |
| mbed_official | 532:fe11edbda85c | 220 | DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); |
| mbed_official | 87:085cde657901 | 221 | |
| mbed_official | 87:085cde657901 | 222 | /* Prepare the DMA Stream configuration */ |
| mbed_official | 87:085cde657901 | 223 | tmp |= hdma->Init.Channel | hdma->Init.Direction | |
| mbed_official | 87:085cde657901 | 224 | hdma->Init.PeriphInc | hdma->Init.MemInc | |
| mbed_official | 87:085cde657901 | 225 | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
| mbed_official | 87:085cde657901 | 226 | hdma->Init.Mode | hdma->Init.Priority; |
| mbed_official | 87:085cde657901 | 227 | |
| mbed_official | 87:085cde657901 | 228 | /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ |
| mbed_official | 87:085cde657901 | 229 | if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) |
| mbed_official | 87:085cde657901 | 230 | { |
| mbed_official | 87:085cde657901 | 231 | /* Get memory burst and peripheral burst */ |
| mbed_official | 87:085cde657901 | 232 | tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; |
| mbed_official | 87:085cde657901 | 233 | } |
| mbed_official | 87:085cde657901 | 234 | |
| mbed_official | 87:085cde657901 | 235 | /* Write to DMA Stream CR register */ |
| mbed_official | 87:085cde657901 | 236 | hdma->Instance->CR = tmp; |
| mbed_official | 87:085cde657901 | 237 | |
| mbed_official | 87:085cde657901 | 238 | /* Get the FCR register value */ |
| mbed_official | 87:085cde657901 | 239 | tmp = hdma->Instance->FCR; |
| mbed_official | 87:085cde657901 | 240 | |
| mbed_official | 87:085cde657901 | 241 | /* Clear Direct mode and FIFO threshold bits */ |
| mbed_official | 87:085cde657901 | 242 | tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); |
| mbed_official | 87:085cde657901 | 243 | |
| mbed_official | 87:085cde657901 | 244 | /* Prepare the DMA Stream FIFO configuration */ |
| mbed_official | 87:085cde657901 | 245 | tmp |= hdma->Init.FIFOMode; |
| mbed_official | 87:085cde657901 | 246 | |
| mbed_official | 87:085cde657901 | 247 | /* the FIFO threshold is not used when the FIFO mode is disabled */ |
| mbed_official | 87:085cde657901 | 248 | if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) |
| mbed_official | 87:085cde657901 | 249 | { |
| mbed_official | 87:085cde657901 | 250 | /* Get the FIFO threshold */ |
| mbed_official | 87:085cde657901 | 251 | tmp |= hdma->Init.FIFOThreshold; |
| mbed_official | 87:085cde657901 | 252 | } |
| mbed_official | 87:085cde657901 | 253 | |
| mbed_official | 87:085cde657901 | 254 | /* Write to DMA Stream FCR */ |
| mbed_official | 87:085cde657901 | 255 | hdma->Instance->FCR = tmp; |
| mbed_official | 87:085cde657901 | 256 | |
| mbed_official | 532:fe11edbda85c | 257 | /* Initialize the error code */ |
| mbed_official | 87:085cde657901 | 258 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
| mbed_official | 87:085cde657901 | 259 | |
| mbed_official | 87:085cde657901 | 260 | /* Initialize the DMA state */ |
| mbed_official | 87:085cde657901 | 261 | hdma->State = HAL_DMA_STATE_READY; |
| mbed_official | 87:085cde657901 | 262 | |
| mbed_official | 87:085cde657901 | 263 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 264 | } |
| mbed_official | 87:085cde657901 | 265 | |
| mbed_official | 87:085cde657901 | 266 | /** |
| mbed_official | 87:085cde657901 | 267 | * @brief DeInitializes the DMA peripheral |
| mbed_official | 87:085cde657901 | 268 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 269 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 270 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 271 | */ |
| mbed_official | 87:085cde657901 | 272 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
| mbed_official | 87:085cde657901 | 273 | { |
| mbed_official | 87:085cde657901 | 274 | /* Check the DMA peripheral state */ |
| mbed_official | 613:bc40b8d2aec4 | 275 | if(hdma == NULL) |
| mbed_official | 369:2e96f1b71984 | 276 | { |
| mbed_official | 369:2e96f1b71984 | 277 | return HAL_ERROR; |
| mbed_official | 369:2e96f1b71984 | 278 | } |
| mbed_official | 369:2e96f1b71984 | 279 | |
| mbed_official | 369:2e96f1b71984 | 280 | /* Check the DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 281 | if(hdma->State == HAL_DMA_STATE_BUSY) |
| mbed_official | 87:085cde657901 | 282 | { |
| mbed_official | 87:085cde657901 | 283 | return HAL_ERROR; |
| mbed_official | 87:085cde657901 | 284 | } |
| mbed_official | 87:085cde657901 | 285 | |
| mbed_official | 87:085cde657901 | 286 | /* Disable the selected DMA Streamx */ |
| mbed_official | 87:085cde657901 | 287 | __HAL_DMA_DISABLE(hdma); |
| mbed_official | 87:085cde657901 | 288 | |
| mbed_official | 87:085cde657901 | 289 | /* Reset DMA Streamx control register */ |
| mbed_official | 87:085cde657901 | 290 | hdma->Instance->CR = 0; |
| mbed_official | 87:085cde657901 | 291 | |
| mbed_official | 87:085cde657901 | 292 | /* Reset DMA Streamx number of data to transfer register */ |
| mbed_official | 87:085cde657901 | 293 | hdma->Instance->NDTR = 0; |
| mbed_official | 87:085cde657901 | 294 | |
| mbed_official | 87:085cde657901 | 295 | /* Reset DMA Streamx peripheral address register */ |
| mbed_official | 87:085cde657901 | 296 | hdma->Instance->PAR = 0; |
| mbed_official | 87:085cde657901 | 297 | |
| mbed_official | 87:085cde657901 | 298 | /* Reset DMA Streamx memory 0 address register */ |
| mbed_official | 87:085cde657901 | 299 | hdma->Instance->M0AR = 0; |
| mbed_official | 87:085cde657901 | 300 | |
| mbed_official | 87:085cde657901 | 301 | /* Reset DMA Streamx memory 1 address register */ |
| mbed_official | 87:085cde657901 | 302 | hdma->Instance->M1AR = 0; |
| mbed_official | 87:085cde657901 | 303 | |
| mbed_official | 87:085cde657901 | 304 | /* Reset DMA Streamx FIFO control register */ |
| mbed_official | 87:085cde657901 | 305 | hdma->Instance->FCR = (uint32_t)0x00000021; |
| mbed_official | 87:085cde657901 | 306 | |
| mbed_official | 87:085cde657901 | 307 | /* Clear all flags */ |
| mbed_official | 87:085cde657901 | 308 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 309 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 310 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 311 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 312 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 313 | |
| mbed_official | 532:fe11edbda85c | 314 | /* Initialize the error code */ |
| mbed_official | 87:085cde657901 | 315 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
| mbed_official | 87:085cde657901 | 316 | |
| mbed_official | 87:085cde657901 | 317 | /* Initialize the DMA state */ |
| mbed_official | 87:085cde657901 | 318 | hdma->State = HAL_DMA_STATE_RESET; |
| mbed_official | 87:085cde657901 | 319 | |
| mbed_official | 106:ced8cbb51063 | 320 | /* Release Lock */ |
| mbed_official | 106:ced8cbb51063 | 321 | __HAL_UNLOCK(hdma); |
| mbed_official | 106:ced8cbb51063 | 322 | |
| mbed_official | 87:085cde657901 | 323 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 324 | } |
| mbed_official | 87:085cde657901 | 325 | |
| mbed_official | 87:085cde657901 | 326 | /** |
| mbed_official | 87:085cde657901 | 327 | * @} |
| mbed_official | 87:085cde657901 | 328 | */ |
| mbed_official | 87:085cde657901 | 329 | |
| mbed_official | 532:fe11edbda85c | 330 | /** @addtogroup DMA_Exported_Functions_Group2 |
| mbed_official | 532:fe11edbda85c | 331 | * |
| mbed_official | 87:085cde657901 | 332 | @verbatim |
| mbed_official | 87:085cde657901 | 333 | =============================================================================== |
| mbed_official | 87:085cde657901 | 334 | ##### IO operation functions ##### |
| mbed_official | 87:085cde657901 | 335 | =============================================================================== |
| mbed_official | 87:085cde657901 | 336 | [..] This section provides functions allowing to: |
| mbed_official | 87:085cde657901 | 337 | (+) Configure the source, destination address and data length and Start DMA transfer |
| mbed_official | 87:085cde657901 | 338 | (+) Configure the source, destination address and data length and |
| mbed_official | 87:085cde657901 | 339 | Start DMA transfer with interrupt |
| mbed_official | 87:085cde657901 | 340 | (+) Abort DMA transfer |
| mbed_official | 87:085cde657901 | 341 | (+) Poll for transfer complete |
| mbed_official | 87:085cde657901 | 342 | (+) Handle DMA interrupt request |
| mbed_official | 87:085cde657901 | 343 | |
| mbed_official | 87:085cde657901 | 344 | @endverbatim |
| mbed_official | 87:085cde657901 | 345 | * @{ |
| mbed_official | 87:085cde657901 | 346 | */ |
| mbed_official | 87:085cde657901 | 347 | |
| mbed_official | 87:085cde657901 | 348 | /** |
| mbed_official | 87:085cde657901 | 349 | * @brief Starts the DMA Transfer. |
| mbed_official | 87:085cde657901 | 350 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 351 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 352 | * @param SrcAddress: The source memory Buffer address |
| mbed_official | 87:085cde657901 | 353 | * @param DstAddress: The destination memory Buffer address |
| mbed_official | 87:085cde657901 | 354 | * @param DataLength: The length of data to be transferred from source to destination |
| mbed_official | 87:085cde657901 | 355 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 356 | */ |
| mbed_official | 87:085cde657901 | 357 | HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
| mbed_official | 87:085cde657901 | 358 | { |
| mbed_official | 87:085cde657901 | 359 | /* Process locked */ |
| mbed_official | 87:085cde657901 | 360 | __HAL_LOCK(hdma); |
| mbed_official | 87:085cde657901 | 361 | |
| mbed_official | 87:085cde657901 | 362 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 363 | hdma->State = HAL_DMA_STATE_BUSY; |
| mbed_official | 87:085cde657901 | 364 | |
| mbed_official | 87:085cde657901 | 365 | /* Check the parameters */ |
| mbed_official | 87:085cde657901 | 366 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
| mbed_official | 87:085cde657901 | 367 | |
| mbed_official | 87:085cde657901 | 368 | /* Disable the peripheral */ |
| mbed_official | 87:085cde657901 | 369 | __HAL_DMA_DISABLE(hdma); |
| mbed_official | 87:085cde657901 | 370 | |
| mbed_official | 87:085cde657901 | 371 | /* Configure the source, destination address and the data length */ |
| mbed_official | 87:085cde657901 | 372 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
| mbed_official | 87:085cde657901 | 373 | |
| mbed_official | 87:085cde657901 | 374 | /* Enable the Peripheral */ |
| mbed_official | 87:085cde657901 | 375 | __HAL_DMA_ENABLE(hdma); |
| mbed_official | 87:085cde657901 | 376 | |
| mbed_official | 87:085cde657901 | 377 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 378 | } |
| mbed_official | 87:085cde657901 | 379 | |
| mbed_official | 87:085cde657901 | 380 | /** |
| mbed_official | 87:085cde657901 | 381 | * @brief Start the DMA Transfer with interrupt enabled. |
| mbed_official | 87:085cde657901 | 382 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 383 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 384 | * @param SrcAddress: The source memory Buffer address |
| mbed_official | 87:085cde657901 | 385 | * @param DstAddress: The destination memory Buffer address |
| mbed_official | 87:085cde657901 | 386 | * @param DataLength: The length of data to be transferred from source to destination |
| mbed_official | 87:085cde657901 | 387 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 388 | */ |
| mbed_official | 87:085cde657901 | 389 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
| mbed_official | 87:085cde657901 | 390 | { |
| mbed_official | 87:085cde657901 | 391 | /* Process locked */ |
| mbed_official | 87:085cde657901 | 392 | __HAL_LOCK(hdma); |
| mbed_official | 87:085cde657901 | 393 | |
| mbed_official | 87:085cde657901 | 394 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 395 | hdma->State = HAL_DMA_STATE_BUSY; |
| mbed_official | 87:085cde657901 | 396 | |
| mbed_official | 87:085cde657901 | 397 | /* Check the parameters */ |
| mbed_official | 87:085cde657901 | 398 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
| mbed_official | 87:085cde657901 | 399 | |
| mbed_official | 87:085cde657901 | 400 | /* Disable the peripheral */ |
| mbed_official | 87:085cde657901 | 401 | __HAL_DMA_DISABLE(hdma); |
| mbed_official | 87:085cde657901 | 402 | |
| mbed_official | 87:085cde657901 | 403 | /* Configure the source, destination address and the data length */ |
| mbed_official | 87:085cde657901 | 404 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
| mbed_official | 87:085cde657901 | 405 | |
| mbed_official | 87:085cde657901 | 406 | /* Enable the transfer complete interrupt */ |
| mbed_official | 87:085cde657901 | 407 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); |
| mbed_official | 87:085cde657901 | 408 | |
| mbed_official | 87:085cde657901 | 409 | /* Enable the Half transfer complete interrupt */ |
| mbed_official | 87:085cde657901 | 410 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); |
| mbed_official | 87:085cde657901 | 411 | |
| mbed_official | 87:085cde657901 | 412 | /* Enable the transfer Error interrupt */ |
| mbed_official | 87:085cde657901 | 413 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); |
| mbed_official | 87:085cde657901 | 414 | |
| mbed_official | 87:085cde657901 | 415 | /* Enable the FIFO Error interrupt */ |
| mbed_official | 87:085cde657901 | 416 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE); |
| mbed_official | 87:085cde657901 | 417 | |
| mbed_official | 87:085cde657901 | 418 | /* Enable the direct mode Error interrupt */ |
| mbed_official | 87:085cde657901 | 419 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); |
| mbed_official | 87:085cde657901 | 420 | |
| mbed_official | 87:085cde657901 | 421 | /* Enable the Peripheral */ |
| mbed_official | 87:085cde657901 | 422 | __HAL_DMA_ENABLE(hdma); |
| mbed_official | 87:085cde657901 | 423 | |
| mbed_official | 87:085cde657901 | 424 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 425 | } |
| mbed_official | 87:085cde657901 | 426 | |
| mbed_official | 87:085cde657901 | 427 | /** |
| mbed_official | 87:085cde657901 | 428 | * @brief Aborts the DMA Transfer. |
| mbed_official | 87:085cde657901 | 429 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 430 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 431 | * |
| mbed_official | 87:085cde657901 | 432 | * @note After disabling a DMA Stream, a check for wait until the DMA Stream is |
| mbed_official | 87:085cde657901 | 433 | * effectively disabled is added. If a Stream is disabled |
| mbed_official | 87:085cde657901 | 434 | * while a data transfer is ongoing, the current data will be transferred |
| mbed_official | 87:085cde657901 | 435 | * and the Stream will be effectively disabled only after the transfer of |
| mbed_official | 87:085cde657901 | 436 | * this single data is finished. |
| mbed_official | 87:085cde657901 | 437 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 438 | */ |
| mbed_official | 87:085cde657901 | 439 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
| mbed_official | 87:085cde657901 | 440 | { |
| mbed_official | 369:2e96f1b71984 | 441 | uint32_t tickstart = 0; |
| mbed_official | 87:085cde657901 | 442 | |
| mbed_official | 87:085cde657901 | 443 | /* Disable the stream */ |
| mbed_official | 87:085cde657901 | 444 | __HAL_DMA_DISABLE(hdma); |
| mbed_official | 87:085cde657901 | 445 | |
| mbed_official | 369:2e96f1b71984 | 446 | /* Get tick */ |
| mbed_official | 369:2e96f1b71984 | 447 | tickstart = HAL_GetTick(); |
| mbed_official | 87:085cde657901 | 448 | |
| mbed_official | 87:085cde657901 | 449 | /* Check if the DMA Stream is effectively disabled */ |
| mbed_official | 87:085cde657901 | 450 | while((hdma->Instance->CR & DMA_SxCR_EN) != 0) |
| mbed_official | 87:085cde657901 | 451 | { |
| mbed_official | 87:085cde657901 | 452 | /* Check for the Timeout */ |
| mbed_official | 369:2e96f1b71984 | 453 | if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) |
| mbed_official | 87:085cde657901 | 454 | { |
| mbed_official | 87:085cde657901 | 455 | /* Update error code */ |
| mbed_official | 87:085cde657901 | 456 | hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; |
| mbed_official | 87:085cde657901 | 457 | |
| mbed_official | 87:085cde657901 | 458 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 459 | __HAL_UNLOCK(hdma); |
| mbed_official | 87:085cde657901 | 460 | |
| mbed_official | 87:085cde657901 | 461 | /* Change the DMA state */ |
| mbed_official | 87:085cde657901 | 462 | hdma->State = HAL_DMA_STATE_TIMEOUT; |
| mbed_official | 87:085cde657901 | 463 | |
| mbed_official | 87:085cde657901 | 464 | return HAL_TIMEOUT; |
| mbed_official | 87:085cde657901 | 465 | } |
| mbed_official | 87:085cde657901 | 466 | } |
| mbed_official | 87:085cde657901 | 467 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 468 | __HAL_UNLOCK(hdma); |
| mbed_official | 87:085cde657901 | 469 | |
| mbed_official | 87:085cde657901 | 470 | /* Change the DMA state*/ |
| mbed_official | 87:085cde657901 | 471 | hdma->State = HAL_DMA_STATE_READY; |
| mbed_official | 87:085cde657901 | 472 | |
| mbed_official | 87:085cde657901 | 473 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 474 | } |
| mbed_official | 87:085cde657901 | 475 | |
| mbed_official | 87:085cde657901 | 476 | /** |
| mbed_official | 87:085cde657901 | 477 | * @brief Polling for transfer complete. |
| mbed_official | 87:085cde657901 | 478 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 479 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 480 | * @param CompleteLevel: Specifies the DMA level complete. |
| mbed_official | 87:085cde657901 | 481 | * @param Timeout: Timeout duration. |
| mbed_official | 87:085cde657901 | 482 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 483 | */ |
| mbed_official | 87:085cde657901 | 484 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) |
| mbed_official | 87:085cde657901 | 485 | { |
| mbed_official | 87:085cde657901 | 486 | uint32_t temp, tmp, tmp1, tmp2; |
| mbed_official | 369:2e96f1b71984 | 487 | uint32_t tickstart = 0; |
| mbed_official | 87:085cde657901 | 488 | |
| mbed_official | 87:085cde657901 | 489 | /* Get the level transfer complete flag */ |
| mbed_official | 87:085cde657901 | 490 | if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
| mbed_official | 87:085cde657901 | 491 | { |
| mbed_official | 87:085cde657901 | 492 | /* Transfer Complete flag */ |
| mbed_official | 87:085cde657901 | 493 | temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); |
| mbed_official | 87:085cde657901 | 494 | } |
| mbed_official | 87:085cde657901 | 495 | else |
| mbed_official | 87:085cde657901 | 496 | { |
| mbed_official | 87:085cde657901 | 497 | /* Half Transfer Complete flag */ |
| mbed_official | 87:085cde657901 | 498 | temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); |
| mbed_official | 87:085cde657901 | 499 | } |
| mbed_official | 87:085cde657901 | 500 | |
| mbed_official | 369:2e96f1b71984 | 501 | /* Get tick */ |
| mbed_official | 369:2e96f1b71984 | 502 | tickstart = HAL_GetTick(); |
| mbed_official | 87:085cde657901 | 503 | |
| mbed_official | 87:085cde657901 | 504 | while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) |
| mbed_official | 87:085cde657901 | 505 | { |
| mbed_official | 87:085cde657901 | 506 | tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 507 | tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 508 | tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 509 | if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET)) |
| mbed_official | 87:085cde657901 | 510 | { |
| mbed_official | 369:2e96f1b71984 | 511 | if(tmp != RESET) |
| mbed_official | 369:2e96f1b71984 | 512 | { |
| mbed_official | 369:2e96f1b71984 | 513 | /* Update error code */ |
| mbed_official | 369:2e96f1b71984 | 514 | hdma->ErrorCode |= HAL_DMA_ERROR_TE; |
| mbed_official | 87:085cde657901 | 515 | |
| mbed_official | 369:2e96f1b71984 | 516 | /* Clear the transfer error flag */ |
| mbed_official | 369:2e96f1b71984 | 517 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
| mbed_official | 369:2e96f1b71984 | 518 | } |
| mbed_official | 369:2e96f1b71984 | 519 | if(tmp1 != RESET) |
| mbed_official | 369:2e96f1b71984 | 520 | { |
| mbed_official | 369:2e96f1b71984 | 521 | /* Update error code */ |
| mbed_official | 369:2e96f1b71984 | 522 | hdma->ErrorCode |= HAL_DMA_ERROR_FE; |
| mbed_official | 369:2e96f1b71984 | 523 | |
| mbed_official | 369:2e96f1b71984 | 524 | /* Clear the FIFO error flag */ |
| mbed_official | 369:2e96f1b71984 | 525 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); |
| mbed_official | 369:2e96f1b71984 | 526 | } |
| mbed_official | 369:2e96f1b71984 | 527 | if(tmp2 != RESET) |
| mbed_official | 369:2e96f1b71984 | 528 | { |
| mbed_official | 369:2e96f1b71984 | 529 | /* Update error code */ |
| mbed_official | 369:2e96f1b71984 | 530 | hdma->ErrorCode |= HAL_DMA_ERROR_DME; |
| mbed_official | 369:2e96f1b71984 | 531 | |
| mbed_official | 369:2e96f1b71984 | 532 | /* Clear the Direct Mode error flag */ |
| mbed_official | 369:2e96f1b71984 | 533 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); |
| mbed_official | 369:2e96f1b71984 | 534 | } |
| mbed_official | 87:085cde657901 | 535 | /* Change the DMA state */ |
| mbed_official | 87:085cde657901 | 536 | hdma->State= HAL_DMA_STATE_ERROR; |
| mbed_official | 87:085cde657901 | 537 | |
| mbed_official | 87:085cde657901 | 538 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 539 | __HAL_UNLOCK(hdma); |
| mbed_official | 87:085cde657901 | 540 | |
| mbed_official | 87:085cde657901 | 541 | return HAL_ERROR; |
| mbed_official | 87:085cde657901 | 542 | } |
| mbed_official | 87:085cde657901 | 543 | /* Check for the Timeout */ |
| mbed_official | 87:085cde657901 | 544 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 87:085cde657901 | 545 | { |
| mbed_official | 369:2e96f1b71984 | 546 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| mbed_official | 87:085cde657901 | 547 | { |
| mbed_official | 87:085cde657901 | 548 | /* Update error code */ |
| mbed_official | 87:085cde657901 | 549 | hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; |
| mbed_official | 87:085cde657901 | 550 | |
| mbed_official | 87:085cde657901 | 551 | /* Change the DMA state */ |
| mbed_official | 87:085cde657901 | 552 | hdma->State = HAL_DMA_STATE_TIMEOUT; |
| mbed_official | 87:085cde657901 | 553 | |
| mbed_official | 369:2e96f1b71984 | 554 | /* Process Unlocked */ |
| mbed_official | 369:2e96f1b71984 | 555 | __HAL_UNLOCK(hdma); |
| mbed_official | 369:2e96f1b71984 | 556 | |
| mbed_official | 87:085cde657901 | 557 | return HAL_TIMEOUT; |
| mbed_official | 87:085cde657901 | 558 | } |
| mbed_official | 87:085cde657901 | 559 | } |
| mbed_official | 87:085cde657901 | 560 | } |
| mbed_official | 87:085cde657901 | 561 | |
| mbed_official | 87:085cde657901 | 562 | if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
| mbed_official | 87:085cde657901 | 563 | { |
| mbed_official | 87:085cde657901 | 564 | /* Multi_Buffering mode enabled */ |
| mbed_official | 87:085cde657901 | 565 | if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) |
| mbed_official | 87:085cde657901 | 566 | { |
| mbed_official | 369:2e96f1b71984 | 567 | /* Clear the half transfer complete flag */ |
| mbed_official | 369:2e96f1b71984 | 568 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 569 | /* Clear the transfer complete flag */ |
| mbed_official | 87:085cde657901 | 570 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 571 | |
| mbed_official | 87:085cde657901 | 572 | /* Current memory buffer used is Memory 0 */ |
| mbed_official | 87:085cde657901 | 573 | if((hdma->Instance->CR & DMA_SxCR_CT) == 0) |
| mbed_official | 87:085cde657901 | 574 | { |
| mbed_official | 87:085cde657901 | 575 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 576 | hdma->State = HAL_DMA_STATE_READY_MEM0; |
| mbed_official | 87:085cde657901 | 577 | } |
| mbed_official | 87:085cde657901 | 578 | /* Current memory buffer used is Memory 1 */ |
| mbed_official | 87:085cde657901 | 579 | else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) |
| mbed_official | 87:085cde657901 | 580 | { |
| mbed_official | 87:085cde657901 | 581 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 582 | hdma->State = HAL_DMA_STATE_READY_MEM1; |
| mbed_official | 87:085cde657901 | 583 | } |
| mbed_official | 87:085cde657901 | 584 | } |
| mbed_official | 87:085cde657901 | 585 | else |
| mbed_official | 87:085cde657901 | 586 | { |
| mbed_official | 369:2e96f1b71984 | 587 | /* Clear the half transfer complete flag */ |
| mbed_official | 369:2e96f1b71984 | 588 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 589 | /* Clear the transfer complete flag */ |
| mbed_official | 87:085cde657901 | 590 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 591 | |
| mbed_official | 87:085cde657901 | 592 | /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers |
| mbed_official | 87:085cde657901 | 593 | are complete) */ |
| mbed_official | 87:085cde657901 | 594 | hdma->State = HAL_DMA_STATE_READY_MEM0; |
| mbed_official | 87:085cde657901 | 595 | } |
| mbed_official | 87:085cde657901 | 596 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 597 | __HAL_UNLOCK(hdma); |
| mbed_official | 87:085cde657901 | 598 | } |
| mbed_official | 87:085cde657901 | 599 | else |
| mbed_official | 87:085cde657901 | 600 | { |
| mbed_official | 87:085cde657901 | 601 | /* Multi_Buffering mode enabled */ |
| mbed_official | 87:085cde657901 | 602 | if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) |
| mbed_official | 87:085cde657901 | 603 | { |
| mbed_official | 87:085cde657901 | 604 | /* Clear the half transfer complete flag */ |
| mbed_official | 87:085cde657901 | 605 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 606 | |
| mbed_official | 87:085cde657901 | 607 | /* Current memory buffer used is Memory 0 */ |
| mbed_official | 87:085cde657901 | 608 | if((hdma->Instance->CR & DMA_SxCR_CT) == 0) |
| mbed_official | 87:085cde657901 | 609 | { |
| mbed_official | 87:085cde657901 | 610 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 611 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; |
| mbed_official | 87:085cde657901 | 612 | } |
| mbed_official | 87:085cde657901 | 613 | /* Current memory buffer used is Memory 1 */ |
| mbed_official | 87:085cde657901 | 614 | else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) |
| mbed_official | 87:085cde657901 | 615 | { |
| mbed_official | 87:085cde657901 | 616 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 617 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; |
| mbed_official | 87:085cde657901 | 618 | } |
| mbed_official | 87:085cde657901 | 619 | } |
| mbed_official | 87:085cde657901 | 620 | else |
| mbed_official | 87:085cde657901 | 621 | { |
| mbed_official | 87:085cde657901 | 622 | /* Clear the half transfer complete flag */ |
| mbed_official | 87:085cde657901 | 623 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 624 | |
| mbed_official | 87:085cde657901 | 625 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 626 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; |
| mbed_official | 87:085cde657901 | 627 | } |
| mbed_official | 87:085cde657901 | 628 | } |
| mbed_official | 87:085cde657901 | 629 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 630 | } |
| mbed_official | 87:085cde657901 | 631 | |
| mbed_official | 87:085cde657901 | 632 | /** |
| mbed_official | 87:085cde657901 | 633 | * @brief Handles DMA interrupt request. |
| mbed_official | 87:085cde657901 | 634 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 635 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 636 | * @retval None |
| mbed_official | 87:085cde657901 | 637 | */ |
| mbed_official | 87:085cde657901 | 638 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
| mbed_official | 87:085cde657901 | 639 | { |
| mbed_official | 87:085cde657901 | 640 | /* Transfer Error Interrupt management ***************************************/ |
| mbed_official | 87:085cde657901 | 641 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) |
| mbed_official | 87:085cde657901 | 642 | { |
| mbed_official | 106:ced8cbb51063 | 643 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) |
| mbed_official | 87:085cde657901 | 644 | { |
| mbed_official | 87:085cde657901 | 645 | /* Disable the transfer error interrupt */ |
| mbed_official | 87:085cde657901 | 646 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); |
| mbed_official | 87:085cde657901 | 647 | |
| mbed_official | 87:085cde657901 | 648 | /* Clear the transfer error flag */ |
| mbed_official | 87:085cde657901 | 649 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 650 | |
| mbed_official | 87:085cde657901 | 651 | /* Update error code */ |
| mbed_official | 87:085cde657901 | 652 | hdma->ErrorCode |= HAL_DMA_ERROR_TE; |
| mbed_official | 87:085cde657901 | 653 | |
| mbed_official | 87:085cde657901 | 654 | /* Change the DMA state */ |
| mbed_official | 87:085cde657901 | 655 | hdma->State = HAL_DMA_STATE_ERROR; |
| mbed_official | 87:085cde657901 | 656 | |
| mbed_official | 87:085cde657901 | 657 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 658 | __HAL_UNLOCK(hdma); |
| mbed_official | 87:085cde657901 | 659 | |
| mbed_official | 613:bc40b8d2aec4 | 660 | if(hdma->XferErrorCallback != NULL) |
| mbed_official | 87:085cde657901 | 661 | { |
| mbed_official | 87:085cde657901 | 662 | /* Transfer error callback */ |
| mbed_official | 87:085cde657901 | 663 | hdma->XferErrorCallback(hdma); |
| mbed_official | 87:085cde657901 | 664 | } |
| mbed_official | 87:085cde657901 | 665 | } |
| mbed_official | 87:085cde657901 | 666 | } |
| mbed_official | 87:085cde657901 | 667 | /* FIFO Error Interrupt management ******************************************/ |
| mbed_official | 87:085cde657901 | 668 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET) |
| mbed_official | 87:085cde657901 | 669 | { |
| mbed_official | 106:ced8cbb51063 | 670 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) |
| mbed_official | 87:085cde657901 | 671 | { |
| mbed_official | 87:085cde657901 | 672 | /* Disable the FIFO Error interrupt */ |
| mbed_official | 87:085cde657901 | 673 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE); |
| mbed_official | 87:085cde657901 | 674 | |
| mbed_official | 87:085cde657901 | 675 | /* Clear the FIFO error flag */ |
| mbed_official | 87:085cde657901 | 676 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 677 | |
| mbed_official | 87:085cde657901 | 678 | /* Update error code */ |
| mbed_official | 87:085cde657901 | 679 | hdma->ErrorCode |= HAL_DMA_ERROR_FE; |
| mbed_official | 87:085cde657901 | 680 | |
| mbed_official | 87:085cde657901 | 681 | /* Change the DMA state */ |
| mbed_official | 87:085cde657901 | 682 | hdma->State = HAL_DMA_STATE_ERROR; |
| mbed_official | 87:085cde657901 | 683 | |
| mbed_official | 87:085cde657901 | 684 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 685 | __HAL_UNLOCK(hdma); |
| mbed_official | 87:085cde657901 | 686 | |
| mbed_official | 613:bc40b8d2aec4 | 687 | if(hdma->XferErrorCallback != NULL) |
| mbed_official | 87:085cde657901 | 688 | { |
| mbed_official | 87:085cde657901 | 689 | /* Transfer error callback */ |
| mbed_official | 87:085cde657901 | 690 | hdma->XferErrorCallback(hdma); |
| mbed_official | 87:085cde657901 | 691 | } |
| mbed_official | 87:085cde657901 | 692 | } |
| mbed_official | 87:085cde657901 | 693 | } |
| mbed_official | 87:085cde657901 | 694 | /* Direct Mode Error Interrupt management ***********************************/ |
| mbed_official | 87:085cde657901 | 695 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET) |
| mbed_official | 87:085cde657901 | 696 | { |
| mbed_official | 106:ced8cbb51063 | 697 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) |
| mbed_official | 87:085cde657901 | 698 | { |
| mbed_official | 87:085cde657901 | 699 | /* Disable the direct mode Error interrupt */ |
| mbed_official | 87:085cde657901 | 700 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME); |
| mbed_official | 87:085cde657901 | 701 | |
| mbed_official | 87:085cde657901 | 702 | /* Clear the direct mode error flag */ |
| mbed_official | 87:085cde657901 | 703 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 704 | |
| mbed_official | 87:085cde657901 | 705 | /* Update error code */ |
| mbed_official | 87:085cde657901 | 706 | hdma->ErrorCode |= HAL_DMA_ERROR_DME; |
| mbed_official | 87:085cde657901 | 707 | |
| mbed_official | 87:085cde657901 | 708 | /* Change the DMA state */ |
| mbed_official | 87:085cde657901 | 709 | hdma->State = HAL_DMA_STATE_ERROR; |
| mbed_official | 87:085cde657901 | 710 | |
| mbed_official | 87:085cde657901 | 711 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 712 | __HAL_UNLOCK(hdma); |
| mbed_official | 87:085cde657901 | 713 | |
| mbed_official | 613:bc40b8d2aec4 | 714 | if(hdma->XferErrorCallback != NULL) |
| mbed_official | 87:085cde657901 | 715 | { |
| mbed_official | 87:085cde657901 | 716 | /* Transfer error callback */ |
| mbed_official | 87:085cde657901 | 717 | hdma->XferErrorCallback(hdma); |
| mbed_official | 87:085cde657901 | 718 | } |
| mbed_official | 87:085cde657901 | 719 | } |
| mbed_official | 87:085cde657901 | 720 | } |
| mbed_official | 87:085cde657901 | 721 | /* Half Transfer Complete Interrupt management ******************************/ |
| mbed_official | 87:085cde657901 | 722 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) |
| mbed_official | 87:085cde657901 | 723 | { |
| mbed_official | 106:ced8cbb51063 | 724 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) |
| mbed_official | 87:085cde657901 | 725 | { |
| mbed_official | 87:085cde657901 | 726 | /* Multi_Buffering mode enabled */ |
| mbed_official | 87:085cde657901 | 727 | if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) |
| mbed_official | 87:085cde657901 | 728 | { |
| mbed_official | 87:085cde657901 | 729 | /* Clear the half transfer complete flag */ |
| mbed_official | 87:085cde657901 | 730 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 731 | |
| mbed_official | 87:085cde657901 | 732 | /* Current memory buffer used is Memory 0 */ |
| mbed_official | 87:085cde657901 | 733 | if((hdma->Instance->CR & DMA_SxCR_CT) == 0) |
| mbed_official | 87:085cde657901 | 734 | { |
| mbed_official | 87:085cde657901 | 735 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 736 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; |
| mbed_official | 87:085cde657901 | 737 | } |
| mbed_official | 87:085cde657901 | 738 | /* Current memory buffer used is Memory 1 */ |
| mbed_official | 87:085cde657901 | 739 | else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) |
| mbed_official | 87:085cde657901 | 740 | { |
| mbed_official | 87:085cde657901 | 741 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 742 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; |
| mbed_official | 87:085cde657901 | 743 | } |
| mbed_official | 87:085cde657901 | 744 | } |
| mbed_official | 87:085cde657901 | 745 | else |
| mbed_official | 87:085cde657901 | 746 | { |
| mbed_official | 87:085cde657901 | 747 | /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
| mbed_official | 87:085cde657901 | 748 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
| mbed_official | 87:085cde657901 | 749 | { |
| mbed_official | 87:085cde657901 | 750 | /* Disable the half transfer interrupt */ |
| mbed_official | 87:085cde657901 | 751 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
| mbed_official | 87:085cde657901 | 752 | } |
| mbed_official | 87:085cde657901 | 753 | /* Clear the half transfer complete flag */ |
| mbed_official | 87:085cde657901 | 754 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 755 | |
| mbed_official | 87:085cde657901 | 756 | /* Change DMA peripheral state */ |
| mbed_official | 87:085cde657901 | 757 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; |
| mbed_official | 87:085cde657901 | 758 | } |
| mbed_official | 87:085cde657901 | 759 | |
| mbed_official | 613:bc40b8d2aec4 | 760 | if(hdma->XferHalfCpltCallback != NULL) |
| mbed_official | 87:085cde657901 | 761 | { |
| mbed_official | 87:085cde657901 | 762 | /* Half transfer callback */ |
| mbed_official | 87:085cde657901 | 763 | hdma->XferHalfCpltCallback(hdma); |
| mbed_official | 87:085cde657901 | 764 | } |
| mbed_official | 87:085cde657901 | 765 | } |
| mbed_official | 87:085cde657901 | 766 | } |
| mbed_official | 87:085cde657901 | 767 | /* Transfer Complete Interrupt management ***********************************/ |
| mbed_official | 87:085cde657901 | 768 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) |
| mbed_official | 87:085cde657901 | 769 | { |
| mbed_official | 106:ced8cbb51063 | 770 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) |
| mbed_official | 87:085cde657901 | 771 | { |
| mbed_official | 87:085cde657901 | 772 | if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) |
| mbed_official | 87:085cde657901 | 773 | { |
| mbed_official | 87:085cde657901 | 774 | /* Clear the transfer complete flag */ |
| mbed_official | 87:085cde657901 | 775 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 776 | |
| mbed_official | 87:085cde657901 | 777 | /* Current memory buffer used is Memory 1 */ |
| mbed_official | 87:085cde657901 | 778 | if((hdma->Instance->CR & DMA_SxCR_CT) == 0) |
| mbed_official | 87:085cde657901 | 779 | { |
| mbed_official | 613:bc40b8d2aec4 | 780 | if(hdma->XferM1CpltCallback != NULL) |
| mbed_official | 87:085cde657901 | 781 | { |
| mbed_official | 87:085cde657901 | 782 | /* Transfer complete Callback for memory1 */ |
| mbed_official | 87:085cde657901 | 783 | hdma->XferM1CpltCallback(hdma); |
| mbed_official | 87:085cde657901 | 784 | } |
| mbed_official | 87:085cde657901 | 785 | } |
| mbed_official | 87:085cde657901 | 786 | /* Current memory buffer used is Memory 0 */ |
| mbed_official | 87:085cde657901 | 787 | else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) |
| mbed_official | 87:085cde657901 | 788 | { |
| mbed_official | 613:bc40b8d2aec4 | 789 | if(hdma->XferCpltCallback != NULL) |
| mbed_official | 87:085cde657901 | 790 | { |
| mbed_official | 87:085cde657901 | 791 | /* Transfer complete Callback for memory0 */ |
| mbed_official | 87:085cde657901 | 792 | hdma->XferCpltCallback(hdma); |
| mbed_official | 87:085cde657901 | 793 | } |
| mbed_official | 87:085cde657901 | 794 | } |
| mbed_official | 87:085cde657901 | 795 | } |
| mbed_official | 87:085cde657901 | 796 | /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ |
| mbed_official | 87:085cde657901 | 797 | else |
| mbed_official | 87:085cde657901 | 798 | { |
| mbed_official | 87:085cde657901 | 799 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
| mbed_official | 87:085cde657901 | 800 | { |
| mbed_official | 87:085cde657901 | 801 | /* Disable the transfer complete interrupt */ |
| mbed_official | 87:085cde657901 | 802 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); |
| mbed_official | 87:085cde657901 | 803 | } |
| mbed_official | 87:085cde657901 | 804 | /* Clear the transfer complete flag */ |
| mbed_official | 87:085cde657901 | 805 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
| mbed_official | 87:085cde657901 | 806 | |
| mbed_official | 87:085cde657901 | 807 | /* Update error code */ |
| mbed_official | 87:085cde657901 | 808 | hdma->ErrorCode |= HAL_DMA_ERROR_NONE; |
| mbed_official | 87:085cde657901 | 809 | |
| mbed_official | 87:085cde657901 | 810 | /* Change the DMA state */ |
| mbed_official | 87:085cde657901 | 811 | hdma->State = HAL_DMA_STATE_READY_MEM0; |
| mbed_official | 87:085cde657901 | 812 | |
| mbed_official | 87:085cde657901 | 813 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 814 | __HAL_UNLOCK(hdma); |
| mbed_official | 87:085cde657901 | 815 | |
| mbed_official | 613:bc40b8d2aec4 | 816 | if(hdma->XferCpltCallback != NULL) |
| mbed_official | 87:085cde657901 | 817 | { |
| mbed_official | 87:085cde657901 | 818 | /* Transfer complete callback */ |
| mbed_official | 87:085cde657901 | 819 | hdma->XferCpltCallback(hdma); |
| mbed_official | 87:085cde657901 | 820 | } |
| mbed_official | 87:085cde657901 | 821 | } |
| mbed_official | 87:085cde657901 | 822 | } |
| mbed_official | 87:085cde657901 | 823 | } |
| mbed_official | 87:085cde657901 | 824 | } |
| mbed_official | 87:085cde657901 | 825 | |
| mbed_official | 87:085cde657901 | 826 | /** |
| mbed_official | 87:085cde657901 | 827 | * @} |
| mbed_official | 87:085cde657901 | 828 | */ |
| mbed_official | 87:085cde657901 | 829 | |
| mbed_official | 532:fe11edbda85c | 830 | /** @addtogroup DMA_Exported_Functions_Group3 |
| mbed_official | 532:fe11edbda85c | 831 | * |
| mbed_official | 87:085cde657901 | 832 | @verbatim |
| mbed_official | 87:085cde657901 | 833 | =============================================================================== |
| mbed_official | 87:085cde657901 | 834 | ##### State and Errors functions ##### |
| mbed_official | 87:085cde657901 | 835 | =============================================================================== |
| mbed_official | 87:085cde657901 | 836 | [..] |
| mbed_official | 87:085cde657901 | 837 | This subsection provides functions allowing to |
| mbed_official | 87:085cde657901 | 838 | (+) Check the DMA state |
| mbed_official | 87:085cde657901 | 839 | (+) Get error code |
| mbed_official | 87:085cde657901 | 840 | |
| mbed_official | 87:085cde657901 | 841 | @endverbatim |
| mbed_official | 87:085cde657901 | 842 | * @{ |
| mbed_official | 87:085cde657901 | 843 | */ |
| mbed_official | 87:085cde657901 | 844 | |
| mbed_official | 87:085cde657901 | 845 | /** |
| mbed_official | 87:085cde657901 | 846 | * @brief Returns the DMA state. |
| mbed_official | 87:085cde657901 | 847 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 848 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 849 | * @retval HAL state |
| mbed_official | 87:085cde657901 | 850 | */ |
| mbed_official | 87:085cde657901 | 851 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
| mbed_official | 87:085cde657901 | 852 | { |
| mbed_official | 87:085cde657901 | 853 | return hdma->State; |
| mbed_official | 87:085cde657901 | 854 | } |
| mbed_official | 87:085cde657901 | 855 | |
| mbed_official | 87:085cde657901 | 856 | /** |
| mbed_official | 87:085cde657901 | 857 | * @brief Return the DMA error code |
| mbed_official | 87:085cde657901 | 858 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 859 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 860 | * @retval DMA Error Code |
| mbed_official | 87:085cde657901 | 861 | */ |
| mbed_official | 87:085cde657901 | 862 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
| mbed_official | 87:085cde657901 | 863 | { |
| mbed_official | 87:085cde657901 | 864 | return hdma->ErrorCode; |
| mbed_official | 87:085cde657901 | 865 | } |
| mbed_official | 87:085cde657901 | 866 | |
| mbed_official | 87:085cde657901 | 867 | /** |
| mbed_official | 87:085cde657901 | 868 | * @} |
| mbed_official | 87:085cde657901 | 869 | */ |
| mbed_official | 87:085cde657901 | 870 | |
| mbed_official | 87:085cde657901 | 871 | /** |
| mbed_official | 532:fe11edbda85c | 872 | * @} |
| mbed_official | 532:fe11edbda85c | 873 | */ |
| mbed_official | 532:fe11edbda85c | 874 | |
| mbed_official | 532:fe11edbda85c | 875 | /** @addtogroup DMA_Private_Functions |
| mbed_official | 532:fe11edbda85c | 876 | * @{ |
| mbed_official | 532:fe11edbda85c | 877 | */ |
| mbed_official | 532:fe11edbda85c | 878 | |
| mbed_official | 532:fe11edbda85c | 879 | /** |
| mbed_official | 87:085cde657901 | 880 | * @brief Sets the DMA Transfer parameter. |
| mbed_official | 87:085cde657901 | 881 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 87:085cde657901 | 882 | * the configuration information for the specified DMA Stream. |
| mbed_official | 87:085cde657901 | 883 | * @param SrcAddress: The source memory Buffer address |
| mbed_official | 87:085cde657901 | 884 | * @param DstAddress: The destination memory Buffer address |
| mbed_official | 87:085cde657901 | 885 | * @param DataLength: The length of data to be transferred from source to destination |
| mbed_official | 87:085cde657901 | 886 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 887 | */ |
| mbed_official | 87:085cde657901 | 888 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
| mbed_official | 87:085cde657901 | 889 | { |
| mbed_official | 532:fe11edbda85c | 890 | /* Clear DBM bit */ |
| mbed_official | 532:fe11edbda85c | 891 | hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); |
| mbed_official | 532:fe11edbda85c | 892 | |
| mbed_official | 87:085cde657901 | 893 | /* Configure DMA Stream data length */ |
| mbed_official | 87:085cde657901 | 894 | hdma->Instance->NDTR = DataLength; |
| mbed_official | 87:085cde657901 | 895 | |
| mbed_official | 87:085cde657901 | 896 | /* Peripheral to Memory */ |
| mbed_official | 87:085cde657901 | 897 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
| mbed_official | 87:085cde657901 | 898 | { |
| mbed_official | 87:085cde657901 | 899 | /* Configure DMA Stream destination address */ |
| mbed_official | 87:085cde657901 | 900 | hdma->Instance->PAR = DstAddress; |
| mbed_official | 87:085cde657901 | 901 | |
| mbed_official | 87:085cde657901 | 902 | /* Configure DMA Stream source address */ |
| mbed_official | 87:085cde657901 | 903 | hdma->Instance->M0AR = SrcAddress; |
| mbed_official | 87:085cde657901 | 904 | } |
| mbed_official | 87:085cde657901 | 905 | /* Memory to Peripheral */ |
| mbed_official | 87:085cde657901 | 906 | else |
| mbed_official | 87:085cde657901 | 907 | { |
| mbed_official | 87:085cde657901 | 908 | /* Configure DMA Stream source address */ |
| mbed_official | 87:085cde657901 | 909 | hdma->Instance->PAR = SrcAddress; |
| mbed_official | 87:085cde657901 | 910 | |
| mbed_official | 87:085cde657901 | 911 | /* Configure DMA Stream destination address */ |
| mbed_official | 87:085cde657901 | 912 | hdma->Instance->M0AR = DstAddress; |
| mbed_official | 87:085cde657901 | 913 | } |
| mbed_official | 87:085cde657901 | 914 | } |
| mbed_official | 87:085cde657901 | 915 | /** |
| mbed_official | 87:085cde657901 | 916 | * @} |
| mbed_official | 532:fe11edbda85c | 917 | */ |
| mbed_official | 532:fe11edbda85c | 918 | |
| mbed_official | 87:085cde657901 | 919 | #endif /* HAL_DMA_MODULE_ENABLED */ |
| mbed_official | 87:085cde657901 | 920 | /** |
| mbed_official | 87:085cde657901 | 921 | * @} |
| mbed_official | 87:085cde657901 | 922 | */ |
| mbed_official | 87:085cde657901 | 923 | |
| mbed_official | 87:085cde657901 | 924 | /** |
| mbed_official | 87:085cde657901 | 925 | * @} |
| mbed_official | 87:085cde657901 | 926 | */ |
| mbed_official | 87:085cde657901 | 927 | |
| mbed_official | 87:085cde657901 | 928 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |