Flotsam / mbed-modifed

Modified version of the mbed library for use with the Nucleo boards.

Dependents:   EEPROMWrite Full-Project

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

Committer:
mbed_official
Date:
Thu Aug 20 10:45:13 2015 +0100
Revision:
613:bc40b8d2aec4
Parent:
532:fe11edbda85c 
Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade



Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/



Nordic: update application start address in GCC linker script

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 400:7fa56b1b9d45 1 /**
mbed_official 400:7fa56b1b9d45 2 ******************************************************************************
mbed_official 400:7fa56b1b9d45 3 * @file stm32f405xx.h
mbed_official 400:7fa56b1b9d45 4 * @author MCD Application Team
mbed_official 613:bc40b8d2aec4 5 * @version V2.3.2
mbed_official 613:bc40b8d2aec4 6 * @date 26-June-2015
mbed_official 400:7fa56b1b9d45 7 * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
mbed_official 400:7fa56b1b9d45 8 *
mbed_official 400:7fa56b1b9d45 9 * This file contains:
mbed_official 400:7fa56b1b9d45 10 * - Data structures and the address mapping for all peripherals
mbed_official 400:7fa56b1b9d45 11 * - Peripheral's registers declarations and bits definition
mbed_official 400:7fa56b1b9d45 12 * - Macros to access peripheral’s registers hardware
mbed_official 400:7fa56b1b9d45 13 *
mbed_official 400:7fa56b1b9d45 14 ******************************************************************************
mbed_official 400:7fa56b1b9d45 15 * @attention
mbed_official 400:7fa56b1b9d45 16 *
mbed_official 532:fe11edbda85c 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 400:7fa56b1b9d45 18 *
mbed_official 400:7fa56b1b9d45 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 400:7fa56b1b9d45 20 * are permitted provided that the following conditions are met:
mbed_official 400:7fa56b1b9d45 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 400:7fa56b1b9d45 22 * this list of conditions and the following disclaimer.
mbed_official 400:7fa56b1b9d45 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 400:7fa56b1b9d45 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 400:7fa56b1b9d45 25 * and/or other materials provided with the distribution.
mbed_official 400:7fa56b1b9d45 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 400:7fa56b1b9d45 27 * may be used to endorse or promote products derived from this software
mbed_official 400:7fa56b1b9d45 28 * without specific prior written permission.
mbed_official 400:7fa56b1b9d45 29 *
mbed_official 400:7fa56b1b9d45 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 400:7fa56b1b9d45 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 400:7fa56b1b9d45 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 400:7fa56b1b9d45 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 400:7fa56b1b9d45 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 400:7fa56b1b9d45 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 400:7fa56b1b9d45 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 400:7fa56b1b9d45 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 400:7fa56b1b9d45 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 400:7fa56b1b9d45 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 400:7fa56b1b9d45 40 *
mbed_official 400:7fa56b1b9d45 41 ******************************************************************************
mbed_official 400:7fa56b1b9d45 42 */
mbed_official 400:7fa56b1b9d45 43
mbed_official 400:7fa56b1b9d45 44 /** @addtogroup CMSIS
mbed_official 400:7fa56b1b9d45 45 * @{
mbed_official 400:7fa56b1b9d45 46 */
mbed_official 400:7fa56b1b9d45 47
mbed_official 400:7fa56b1b9d45 48 /** @addtogroup stm32f405xx
mbed_official 400:7fa56b1b9d45 49 * @{
mbed_official 400:7fa56b1b9d45 50 */
mbed_official 400:7fa56b1b9d45 51
mbed_official 400:7fa56b1b9d45 52 #ifndef __STM32F405xx_H
mbed_official 400:7fa56b1b9d45 53 #define __STM32F405xx_H
mbed_official 400:7fa56b1b9d45 54
mbed_official 400:7fa56b1b9d45 55 #ifdef __cplusplus
mbed_official 400:7fa56b1b9d45 56 extern "C" {
mbed_official 400:7fa56b1b9d45 57 #endif /* __cplusplus */
mbed_official 400:7fa56b1b9d45 58
mbed_official 400:7fa56b1b9d45 59
mbed_official 400:7fa56b1b9d45 60 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 400:7fa56b1b9d45 61 * @{
mbed_official 400:7fa56b1b9d45 62 */
mbed_official 400:7fa56b1b9d45 63
mbed_official 400:7fa56b1b9d45 64 /**
mbed_official 400:7fa56b1b9d45 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 400:7fa56b1b9d45 66 */
mbed_official 400:7fa56b1b9d45 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 400:7fa56b1b9d45 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
mbed_official 400:7fa56b1b9d45 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
mbed_official 400:7fa56b1b9d45 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 400:7fa56b1b9d45 71 #define __FPU_PRESENT 1 /*!< FPU present */
mbed_official 400:7fa56b1b9d45 72
mbed_official 400:7fa56b1b9d45 73 /**
mbed_official 400:7fa56b1b9d45 74 * @}
mbed_official 400:7fa56b1b9d45 75 */
mbed_official 400:7fa56b1b9d45 76
mbed_official 400:7fa56b1b9d45 77 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 400:7fa56b1b9d45 78 * @{
mbed_official 400:7fa56b1b9d45 79 */
mbed_official 400:7fa56b1b9d45 80
mbed_official 400:7fa56b1b9d45 81 /**
mbed_official 400:7fa56b1b9d45 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
mbed_official 400:7fa56b1b9d45 83 * in @ref Library_configuration_section
mbed_official 400:7fa56b1b9d45 84 */
mbed_official 400:7fa56b1b9d45 85 typedef enum
mbed_official 400:7fa56b1b9d45 86 {
mbed_official 400:7fa56b1b9d45 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 400:7fa56b1b9d45 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 400:7fa56b1b9d45 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 400:7fa56b1b9d45 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 400:7fa56b1b9d45 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 400:7fa56b1b9d45 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 400:7fa56b1b9d45 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 400:7fa56b1b9d45 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 400:7fa56b1b9d45 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 400:7fa56b1b9d45 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 400:7fa56b1b9d45 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 400:7fa56b1b9d45 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 400:7fa56b1b9d45 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 400:7fa56b1b9d45 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 400:7fa56b1b9d45 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 400:7fa56b1b9d45 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 400:7fa56b1b9d45 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 400:7fa56b1b9d45 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 400:7fa56b1b9d45 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 400:7fa56b1b9d45 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 400:7fa56b1b9d45 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 400:7fa56b1b9d45 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 400:7fa56b1b9d45 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 400:7fa56b1b9d45 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 400:7fa56b1b9d45 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 400:7fa56b1b9d45 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 400:7fa56b1b9d45 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 400:7fa56b1b9d45 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 400:7fa56b1b9d45 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
mbed_official 400:7fa56b1b9d45 116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
mbed_official 400:7fa56b1b9d45 117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
mbed_official 400:7fa56b1b9d45 118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 400:7fa56b1b9d45 119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 400:7fa56b1b9d45 120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 400:7fa56b1b9d45 121 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 400:7fa56b1b9d45 122 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
mbed_official 400:7fa56b1b9d45 123 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 400:7fa56b1b9d45 124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 400:7fa56b1b9d45 125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 400:7fa56b1b9d45 126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 400:7fa56b1b9d45 127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 400:7fa56b1b9d45 128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 400:7fa56b1b9d45 129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 400:7fa56b1b9d45 130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 400:7fa56b1b9d45 131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 400:7fa56b1b9d45 132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 400:7fa56b1b9d45 133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 400:7fa56b1b9d45 134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 400:7fa56b1b9d45 135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 400:7fa56b1b9d45 136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 400:7fa56b1b9d45 137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 400:7fa56b1b9d45 138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 400:7fa56b1b9d45 139 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
mbed_official 400:7fa56b1b9d45 140 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
mbed_official 400:7fa56b1b9d45 141 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
mbed_official 400:7fa56b1b9d45 142 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
mbed_official 400:7fa56b1b9d45 143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
mbed_official 400:7fa56b1b9d45 144 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 400:7fa56b1b9d45 145 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
mbed_official 400:7fa56b1b9d45 146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
mbed_official 400:7fa56b1b9d45 147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 400:7fa56b1b9d45 148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 400:7fa56b1b9d45 149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
mbed_official 400:7fa56b1b9d45 150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
mbed_official 400:7fa56b1b9d45 151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
mbed_official 400:7fa56b1b9d45 152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
mbed_official 400:7fa56b1b9d45 153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 400:7fa56b1b9d45 154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 400:7fa56b1b9d45 155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 400:7fa56b1b9d45 156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 400:7fa56b1b9d45 157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 400:7fa56b1b9d45 158 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
mbed_official 400:7fa56b1b9d45 159 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
mbed_official 400:7fa56b1b9d45 160 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
mbed_official 400:7fa56b1b9d45 161 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
mbed_official 400:7fa56b1b9d45 162 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
mbed_official 400:7fa56b1b9d45 163 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 400:7fa56b1b9d45 164 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 400:7fa56b1b9d45 165 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 400:7fa56b1b9d45 166 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 400:7fa56b1b9d45 167 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
mbed_official 400:7fa56b1b9d45 168 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
mbed_official 400:7fa56b1b9d45 169 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
mbed_official 400:7fa56b1b9d45 170 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
mbed_official 400:7fa56b1b9d45 171 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
mbed_official 400:7fa56b1b9d45 172 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
mbed_official 400:7fa56b1b9d45 173 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
mbed_official 400:7fa56b1b9d45 174 FPU_IRQn = 81 /*!< FPU global interrupt */
mbed_official 400:7fa56b1b9d45 175 } IRQn_Type;
mbed_official 400:7fa56b1b9d45 176
mbed_official 400:7fa56b1b9d45 177 /**
mbed_official 400:7fa56b1b9d45 178 * @}
mbed_official 400:7fa56b1b9d45 179 */
mbed_official 400:7fa56b1b9d45 180
mbed_official 400:7fa56b1b9d45 181 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 400:7fa56b1b9d45 182 #include "system_stm32f4xx.h"
mbed_official 400:7fa56b1b9d45 183 #include <stdint.h>
mbed_official 400:7fa56b1b9d45 184
mbed_official 400:7fa56b1b9d45 185 /** @addtogroup Peripheral_registers_structures
mbed_official 400:7fa56b1b9d45 186 * @{
mbed_official 400:7fa56b1b9d45 187 */
mbed_official 400:7fa56b1b9d45 188
mbed_official 400:7fa56b1b9d45 189 /**
mbed_official 400:7fa56b1b9d45 190 * @brief Analog to Digital Converter
mbed_official 400:7fa56b1b9d45 191 */
mbed_official 400:7fa56b1b9d45 192
mbed_official 400:7fa56b1b9d45 193 typedef struct
mbed_official 400:7fa56b1b9d45 194 {
mbed_official 400:7fa56b1b9d45 195 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 196 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 197 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 198 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 199 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 200 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 201 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 202 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 203 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 204 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 400:7fa56b1b9d45 205 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 400:7fa56b1b9d45 206 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 400:7fa56b1b9d45 207 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 400:7fa56b1b9d45 208 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 400:7fa56b1b9d45 209 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 400:7fa56b1b9d45 210 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 400:7fa56b1b9d45 211 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 400:7fa56b1b9d45 212 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 400:7fa56b1b9d45 213 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 400:7fa56b1b9d45 214 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 400:7fa56b1b9d45 215 } ADC_TypeDef;
mbed_official 400:7fa56b1b9d45 216
mbed_official 400:7fa56b1b9d45 217 typedef struct
mbed_official 400:7fa56b1b9d45 218 {
mbed_official 400:7fa56b1b9d45 219 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 400:7fa56b1b9d45 220 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 400:7fa56b1b9d45 221 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 400:7fa56b1b9d45 222 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 400:7fa56b1b9d45 223 } ADC_Common_TypeDef;
mbed_official 400:7fa56b1b9d45 224
mbed_official 400:7fa56b1b9d45 225
mbed_official 400:7fa56b1b9d45 226 /**
mbed_official 400:7fa56b1b9d45 227 * @brief Controller Area Network TxMailBox
mbed_official 400:7fa56b1b9d45 228 */
mbed_official 400:7fa56b1b9d45 229
mbed_official 400:7fa56b1b9d45 230 typedef struct
mbed_official 400:7fa56b1b9d45 231 {
mbed_official 400:7fa56b1b9d45 232 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 400:7fa56b1b9d45 233 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 400:7fa56b1b9d45 234 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 400:7fa56b1b9d45 235 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 400:7fa56b1b9d45 236 } CAN_TxMailBox_TypeDef;
mbed_official 400:7fa56b1b9d45 237
mbed_official 400:7fa56b1b9d45 238 /**
mbed_official 400:7fa56b1b9d45 239 * @brief Controller Area Network FIFOMailBox
mbed_official 400:7fa56b1b9d45 240 */
mbed_official 400:7fa56b1b9d45 241
mbed_official 400:7fa56b1b9d45 242 typedef struct
mbed_official 400:7fa56b1b9d45 243 {
mbed_official 400:7fa56b1b9d45 244 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 400:7fa56b1b9d45 245 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 400:7fa56b1b9d45 246 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 400:7fa56b1b9d45 247 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 400:7fa56b1b9d45 248 } CAN_FIFOMailBox_TypeDef;
mbed_official 400:7fa56b1b9d45 249
mbed_official 400:7fa56b1b9d45 250 /**
mbed_official 400:7fa56b1b9d45 251 * @brief Controller Area Network FilterRegister
mbed_official 400:7fa56b1b9d45 252 */
mbed_official 400:7fa56b1b9d45 253
mbed_official 400:7fa56b1b9d45 254 typedef struct
mbed_official 400:7fa56b1b9d45 255 {
mbed_official 400:7fa56b1b9d45 256 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 400:7fa56b1b9d45 257 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 400:7fa56b1b9d45 258 } CAN_FilterRegister_TypeDef;
mbed_official 400:7fa56b1b9d45 259
mbed_official 400:7fa56b1b9d45 260 /**
mbed_official 400:7fa56b1b9d45 261 * @brief Controller Area Network
mbed_official 400:7fa56b1b9d45 262 */
mbed_official 400:7fa56b1b9d45 263
mbed_official 400:7fa56b1b9d45 264 typedef struct
mbed_official 400:7fa56b1b9d45 265 {
mbed_official 400:7fa56b1b9d45 266 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 267 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 268 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 269 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 270 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 271 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 272 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 273 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 274 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 400:7fa56b1b9d45 275 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 400:7fa56b1b9d45 276 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 400:7fa56b1b9d45 277 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 400:7fa56b1b9d45 278 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 400:7fa56b1b9d45 279 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 400:7fa56b1b9d45 280 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 400:7fa56b1b9d45 281 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 400:7fa56b1b9d45 282 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 400:7fa56b1b9d45 283 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 400:7fa56b1b9d45 284 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 400:7fa56b1b9d45 285 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 400:7fa56b1b9d45 286 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 400:7fa56b1b9d45 287 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 400:7fa56b1b9d45 288 } CAN_TypeDef;
mbed_official 400:7fa56b1b9d45 289
mbed_official 400:7fa56b1b9d45 290 /**
mbed_official 400:7fa56b1b9d45 291 * @brief CRC calculation unit
mbed_official 400:7fa56b1b9d45 292 */
mbed_official 400:7fa56b1b9d45 293
mbed_official 400:7fa56b1b9d45 294 typedef struct
mbed_official 400:7fa56b1b9d45 295 {
mbed_official 400:7fa56b1b9d45 296 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 297 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 298 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 400:7fa56b1b9d45 299 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 400:7fa56b1b9d45 300 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 301 } CRC_TypeDef;
mbed_official 400:7fa56b1b9d45 302
mbed_official 400:7fa56b1b9d45 303 /**
mbed_official 400:7fa56b1b9d45 304 * @brief Digital to Analog Converter
mbed_official 400:7fa56b1b9d45 305 */
mbed_official 400:7fa56b1b9d45 306
mbed_official 400:7fa56b1b9d45 307 typedef struct
mbed_official 400:7fa56b1b9d45 308 {
mbed_official 400:7fa56b1b9d45 309 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 310 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 311 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 312 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 313 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 314 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 315 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 316 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 317 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 318 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 400:7fa56b1b9d45 319 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 400:7fa56b1b9d45 320 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 400:7fa56b1b9d45 321 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 400:7fa56b1b9d45 322 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 400:7fa56b1b9d45 323 } DAC_TypeDef;
mbed_official 400:7fa56b1b9d45 324
mbed_official 400:7fa56b1b9d45 325 /**
mbed_official 400:7fa56b1b9d45 326 * @brief Debug MCU
mbed_official 400:7fa56b1b9d45 327 */
mbed_official 400:7fa56b1b9d45 328
mbed_official 400:7fa56b1b9d45 329 typedef struct
mbed_official 400:7fa56b1b9d45 330 {
mbed_official 400:7fa56b1b9d45 331 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 332 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 333 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 334 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 335 }DBGMCU_TypeDef;
mbed_official 400:7fa56b1b9d45 336
mbed_official 400:7fa56b1b9d45 337
mbed_official 400:7fa56b1b9d45 338 /**
mbed_official 400:7fa56b1b9d45 339 * @brief DMA Controller
mbed_official 400:7fa56b1b9d45 340 */
mbed_official 400:7fa56b1b9d45 341
mbed_official 400:7fa56b1b9d45 342 typedef struct
mbed_official 400:7fa56b1b9d45 343 {
mbed_official 400:7fa56b1b9d45 344 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 400:7fa56b1b9d45 345 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 400:7fa56b1b9d45 346 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 400:7fa56b1b9d45 347 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 400:7fa56b1b9d45 348 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 400:7fa56b1b9d45 349 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 400:7fa56b1b9d45 350 } DMA_Stream_TypeDef;
mbed_official 400:7fa56b1b9d45 351
mbed_official 400:7fa56b1b9d45 352 typedef struct
mbed_official 400:7fa56b1b9d45 353 {
mbed_official 400:7fa56b1b9d45 354 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 355 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 356 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 357 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 358 } DMA_TypeDef;
mbed_official 400:7fa56b1b9d45 359
mbed_official 400:7fa56b1b9d45 360
mbed_official 400:7fa56b1b9d45 361 /**
mbed_official 400:7fa56b1b9d45 362 * @brief External Interrupt/Event Controller
mbed_official 400:7fa56b1b9d45 363 */
mbed_official 400:7fa56b1b9d45 364
mbed_official 400:7fa56b1b9d45 365 typedef struct
mbed_official 400:7fa56b1b9d45 366 {
mbed_official 400:7fa56b1b9d45 367 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 368 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 369 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 370 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 371 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 372 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 373 } EXTI_TypeDef;
mbed_official 400:7fa56b1b9d45 374
mbed_official 400:7fa56b1b9d45 375 /**
mbed_official 400:7fa56b1b9d45 376 * @brief FLASH Registers
mbed_official 400:7fa56b1b9d45 377 */
mbed_official 400:7fa56b1b9d45 378
mbed_official 400:7fa56b1b9d45 379 typedef struct
mbed_official 400:7fa56b1b9d45 380 {
mbed_official 400:7fa56b1b9d45 381 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 382 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 383 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 384 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 385 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 386 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 387 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 388 } FLASH_TypeDef;
mbed_official 400:7fa56b1b9d45 389
mbed_official 400:7fa56b1b9d45 390
mbed_official 400:7fa56b1b9d45 391 /**
mbed_official 400:7fa56b1b9d45 392 * @brief Flexible Static Memory Controller
mbed_official 400:7fa56b1b9d45 393 */
mbed_official 400:7fa56b1b9d45 394
mbed_official 400:7fa56b1b9d45 395 typedef struct
mbed_official 400:7fa56b1b9d45 396 {
mbed_official 400:7fa56b1b9d45 397 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
mbed_official 400:7fa56b1b9d45 398 } FSMC_Bank1_TypeDef;
mbed_official 400:7fa56b1b9d45 399
mbed_official 400:7fa56b1b9d45 400 /**
mbed_official 400:7fa56b1b9d45 401 * @brief Flexible Static Memory Controller Bank1E
mbed_official 400:7fa56b1b9d45 402 */
mbed_official 400:7fa56b1b9d45 403
mbed_official 400:7fa56b1b9d45 404 typedef struct
mbed_official 400:7fa56b1b9d45 405 {
mbed_official 400:7fa56b1b9d45 406 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
mbed_official 400:7fa56b1b9d45 407 } FSMC_Bank1E_TypeDef;
mbed_official 400:7fa56b1b9d45 408
mbed_official 400:7fa56b1b9d45 409 /**
mbed_official 400:7fa56b1b9d45 410 * @brief Flexible Static Memory Controller Bank2
mbed_official 400:7fa56b1b9d45 411 */
mbed_official 400:7fa56b1b9d45 412
mbed_official 400:7fa56b1b9d45 413 typedef struct
mbed_official 400:7fa56b1b9d45 414 {
mbed_official 400:7fa56b1b9d45 415 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
mbed_official 400:7fa56b1b9d45 416 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
mbed_official 400:7fa56b1b9d45 417 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
mbed_official 400:7fa56b1b9d45 418 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
mbed_official 400:7fa56b1b9d45 419 uint32_t RESERVED0; /*!< Reserved, 0x70 */
mbed_official 400:7fa56b1b9d45 420 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
mbed_official 400:7fa56b1b9d45 421 uint32_t RESERVED1; /*!< Reserved, 0x78 */
mbed_official 400:7fa56b1b9d45 422 uint32_t RESERVED2; /*!< Reserved, 0x7C */
mbed_official 400:7fa56b1b9d45 423 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
mbed_official 400:7fa56b1b9d45 424 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
mbed_official 400:7fa56b1b9d45 425 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
mbed_official 400:7fa56b1b9d45 426 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
mbed_official 400:7fa56b1b9d45 427 uint32_t RESERVED3; /*!< Reserved, 0x90 */
mbed_official 400:7fa56b1b9d45 428 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
mbed_official 400:7fa56b1b9d45 429 } FSMC_Bank2_3_TypeDef;
mbed_official 400:7fa56b1b9d45 430
mbed_official 400:7fa56b1b9d45 431 /**
mbed_official 400:7fa56b1b9d45 432 * @brief Flexible Static Memory Controller Bank4
mbed_official 400:7fa56b1b9d45 433 */
mbed_official 400:7fa56b1b9d45 434
mbed_official 400:7fa56b1b9d45 435 typedef struct
mbed_official 400:7fa56b1b9d45 436 {
mbed_official 400:7fa56b1b9d45 437 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
mbed_official 400:7fa56b1b9d45 438 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
mbed_official 400:7fa56b1b9d45 439 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
mbed_official 400:7fa56b1b9d45 440 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
mbed_official 400:7fa56b1b9d45 441 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
mbed_official 400:7fa56b1b9d45 442 } FSMC_Bank4_TypeDef;
mbed_official 400:7fa56b1b9d45 443
mbed_official 400:7fa56b1b9d45 444
mbed_official 400:7fa56b1b9d45 445 /**
mbed_official 400:7fa56b1b9d45 446 * @brief General Purpose I/O
mbed_official 400:7fa56b1b9d45 447 */
mbed_official 400:7fa56b1b9d45 448
mbed_official 400:7fa56b1b9d45 449 typedef struct
mbed_official 400:7fa56b1b9d45 450 {
mbed_official 400:7fa56b1b9d45 451 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 452 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 453 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 454 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 455 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 456 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 532:fe11edbda85c 457 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 458 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 459 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 400:7fa56b1b9d45 460 } GPIO_TypeDef;
mbed_official 400:7fa56b1b9d45 461
mbed_official 400:7fa56b1b9d45 462 /**
mbed_official 400:7fa56b1b9d45 463 * @brief System configuration controller
mbed_official 400:7fa56b1b9d45 464 */
mbed_official 400:7fa56b1b9d45 465
mbed_official 400:7fa56b1b9d45 466 typedef struct
mbed_official 400:7fa56b1b9d45 467 {
mbed_official 400:7fa56b1b9d45 468 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 469 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 470 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 400:7fa56b1b9d45 471 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
mbed_official 400:7fa56b1b9d45 472 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 473 } SYSCFG_TypeDef;
mbed_official 400:7fa56b1b9d45 474
mbed_official 400:7fa56b1b9d45 475 /**
mbed_official 400:7fa56b1b9d45 476 * @brief Inter-integrated Circuit Interface
mbed_official 400:7fa56b1b9d45 477 */
mbed_official 400:7fa56b1b9d45 478
mbed_official 400:7fa56b1b9d45 479 typedef struct
mbed_official 400:7fa56b1b9d45 480 {
mbed_official 400:7fa56b1b9d45 481 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 482 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 483 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 484 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 485 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 486 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 487 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 488 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 489 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 490 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
mbed_official 400:7fa56b1b9d45 491 } I2C_TypeDef;
mbed_official 400:7fa56b1b9d45 492
mbed_official 400:7fa56b1b9d45 493 /**
mbed_official 400:7fa56b1b9d45 494 * @brief Independent WATCHDOG
mbed_official 400:7fa56b1b9d45 495 */
mbed_official 400:7fa56b1b9d45 496
mbed_official 400:7fa56b1b9d45 497 typedef struct
mbed_official 400:7fa56b1b9d45 498 {
mbed_official 400:7fa56b1b9d45 499 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 500 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 501 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 502 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 503 } IWDG_TypeDef;
mbed_official 400:7fa56b1b9d45 504
mbed_official 400:7fa56b1b9d45 505 /**
mbed_official 400:7fa56b1b9d45 506 * @brief Power Control
mbed_official 400:7fa56b1b9d45 507 */
mbed_official 400:7fa56b1b9d45 508
mbed_official 400:7fa56b1b9d45 509 typedef struct
mbed_official 400:7fa56b1b9d45 510 {
mbed_official 400:7fa56b1b9d45 511 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 512 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 513 } PWR_TypeDef;
mbed_official 400:7fa56b1b9d45 514
mbed_official 400:7fa56b1b9d45 515 /**
mbed_official 400:7fa56b1b9d45 516 * @brief Reset and Clock Control
mbed_official 400:7fa56b1b9d45 517 */
mbed_official 400:7fa56b1b9d45 518
mbed_official 400:7fa56b1b9d45 519 typedef struct
mbed_official 400:7fa56b1b9d45 520 {
mbed_official 400:7fa56b1b9d45 521 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 522 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 523 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 524 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 525 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 526 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 527 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 528 uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 400:7fa56b1b9d45 529 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 530 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 400:7fa56b1b9d45 531 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 400:7fa56b1b9d45 532 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 400:7fa56b1b9d45 533 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
mbed_official 400:7fa56b1b9d45 534 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
mbed_official 400:7fa56b1b9d45 535 uint32_t RESERVED2; /*!< Reserved, 0x3C */
mbed_official 400:7fa56b1b9d45 536 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 400:7fa56b1b9d45 537 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 400:7fa56b1b9d45 538 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 400:7fa56b1b9d45 539 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 400:7fa56b1b9d45 540 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
mbed_official 400:7fa56b1b9d45 541 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
mbed_official 400:7fa56b1b9d45 542 uint32_t RESERVED4; /*!< Reserved, 0x5C */
mbed_official 400:7fa56b1b9d45 543 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 400:7fa56b1b9d45 544 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 400:7fa56b1b9d45 545 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 400:7fa56b1b9d45 546 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 400:7fa56b1b9d45 547 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 400:7fa56b1b9d45 548 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 400:7fa56b1b9d45 549 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 400:7fa56b1b9d45 550 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
mbed_official 400:7fa56b1b9d45 551
mbed_official 400:7fa56b1b9d45 552 } RCC_TypeDef;
mbed_official 400:7fa56b1b9d45 553
mbed_official 400:7fa56b1b9d45 554 /**
mbed_official 400:7fa56b1b9d45 555 * @brief Real-Time Clock
mbed_official 400:7fa56b1b9d45 556 */
mbed_official 400:7fa56b1b9d45 557
mbed_official 400:7fa56b1b9d45 558 typedef struct
mbed_official 400:7fa56b1b9d45 559 {
mbed_official 400:7fa56b1b9d45 560 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 561 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 562 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 563 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 564 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 565 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 566 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 567 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 568 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 569 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 400:7fa56b1b9d45 570 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 400:7fa56b1b9d45 571 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 400:7fa56b1b9d45 572 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 400:7fa56b1b9d45 573 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 400:7fa56b1b9d45 574 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 400:7fa56b1b9d45 575 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 400:7fa56b1b9d45 576 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 400:7fa56b1b9d45 577 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 400:7fa56b1b9d45 578 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 400:7fa56b1b9d45 579 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 400:7fa56b1b9d45 580 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
mbed_official 400:7fa56b1b9d45 581 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 400:7fa56b1b9d45 582 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 400:7fa56b1b9d45 583 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 400:7fa56b1b9d45 584 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 400:7fa56b1b9d45 585 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 400:7fa56b1b9d45 586 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 400:7fa56b1b9d45 587 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 400:7fa56b1b9d45 588 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 400:7fa56b1b9d45 589 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 400:7fa56b1b9d45 590 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 400:7fa56b1b9d45 591 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 400:7fa56b1b9d45 592 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 400:7fa56b1b9d45 593 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 400:7fa56b1b9d45 594 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 400:7fa56b1b9d45 595 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 400:7fa56b1b9d45 596 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 400:7fa56b1b9d45 597 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 400:7fa56b1b9d45 598 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 400:7fa56b1b9d45 599 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 400:7fa56b1b9d45 600 } RTC_TypeDef;
mbed_official 400:7fa56b1b9d45 601
mbed_official 400:7fa56b1b9d45 602
mbed_official 400:7fa56b1b9d45 603 /**
mbed_official 400:7fa56b1b9d45 604 * @brief SD host Interface
mbed_official 400:7fa56b1b9d45 605 */
mbed_official 400:7fa56b1b9d45 606
mbed_official 400:7fa56b1b9d45 607 typedef struct
mbed_official 400:7fa56b1b9d45 608 {
mbed_official 400:7fa56b1b9d45 609 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 610 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 611 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 612 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 613 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 614 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 615 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 616 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 617 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 618 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
mbed_official 400:7fa56b1b9d45 619 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
mbed_official 400:7fa56b1b9d45 620 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
mbed_official 400:7fa56b1b9d45 621 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
mbed_official 400:7fa56b1b9d45 622 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
mbed_official 400:7fa56b1b9d45 623 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
mbed_official 400:7fa56b1b9d45 624 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
mbed_official 400:7fa56b1b9d45 625 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
mbed_official 400:7fa56b1b9d45 626 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
mbed_official 400:7fa56b1b9d45 627 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
mbed_official 400:7fa56b1b9d45 628 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
mbed_official 400:7fa56b1b9d45 629 } SDIO_TypeDef;
mbed_official 400:7fa56b1b9d45 630
mbed_official 400:7fa56b1b9d45 631 /**
mbed_official 400:7fa56b1b9d45 632 * @brief Serial Peripheral Interface
mbed_official 400:7fa56b1b9d45 633 */
mbed_official 400:7fa56b1b9d45 634
mbed_official 400:7fa56b1b9d45 635 typedef struct
mbed_official 400:7fa56b1b9d45 636 {
mbed_official 400:7fa56b1b9d45 637 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 638 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 639 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 640 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 641 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 642 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 643 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 644 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 645 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 646 } SPI_TypeDef;
mbed_official 400:7fa56b1b9d45 647
mbed_official 400:7fa56b1b9d45 648 /**
mbed_official 400:7fa56b1b9d45 649 * @brief TIM
mbed_official 400:7fa56b1b9d45 650 */
mbed_official 400:7fa56b1b9d45 651
mbed_official 400:7fa56b1b9d45 652 typedef struct
mbed_official 400:7fa56b1b9d45 653 {
mbed_official 400:7fa56b1b9d45 654 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 655 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 656 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 657 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 658 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 659 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 660 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 661 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 400:7fa56b1b9d45 662 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 400:7fa56b1b9d45 663 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 400:7fa56b1b9d45 664 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 400:7fa56b1b9d45 665 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 400:7fa56b1b9d45 666 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 400:7fa56b1b9d45 667 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 400:7fa56b1b9d45 668 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 400:7fa56b1b9d45 669 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 400:7fa56b1b9d45 670 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 400:7fa56b1b9d45 671 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 400:7fa56b1b9d45 672 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 400:7fa56b1b9d45 673 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 400:7fa56b1b9d45 674 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 400:7fa56b1b9d45 675 } TIM_TypeDef;
mbed_official 400:7fa56b1b9d45 676
mbed_official 400:7fa56b1b9d45 677 /**
mbed_official 400:7fa56b1b9d45 678 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 400:7fa56b1b9d45 679 */
mbed_official 400:7fa56b1b9d45 680
mbed_official 400:7fa56b1b9d45 681 typedef struct
mbed_official 400:7fa56b1b9d45 682 {
mbed_official 400:7fa56b1b9d45 683 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 684 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 685 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 686 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 400:7fa56b1b9d45 687 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 400:7fa56b1b9d45 688 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 400:7fa56b1b9d45 689 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 400:7fa56b1b9d45 690 } USART_TypeDef;
mbed_official 400:7fa56b1b9d45 691
mbed_official 400:7fa56b1b9d45 692 /**
mbed_official 400:7fa56b1b9d45 693 * @brief Window WATCHDOG
mbed_official 400:7fa56b1b9d45 694 */
mbed_official 400:7fa56b1b9d45 695
mbed_official 400:7fa56b1b9d45 696 typedef struct
mbed_official 400:7fa56b1b9d45 697 {
mbed_official 400:7fa56b1b9d45 698 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 699 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 700 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 701 } WWDG_TypeDef;
mbed_official 400:7fa56b1b9d45 702
mbed_official 400:7fa56b1b9d45 703
mbed_official 400:7fa56b1b9d45 704 /**
mbed_official 400:7fa56b1b9d45 705 * @brief RNG
mbed_official 400:7fa56b1b9d45 706 */
mbed_official 400:7fa56b1b9d45 707
mbed_official 400:7fa56b1b9d45 708 typedef struct
mbed_official 400:7fa56b1b9d45 709 {
mbed_official 400:7fa56b1b9d45 710 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
mbed_official 400:7fa56b1b9d45 711 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
mbed_official 400:7fa56b1b9d45 712 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
mbed_official 400:7fa56b1b9d45 713 } RNG_TypeDef;
mbed_official 400:7fa56b1b9d45 714
mbed_official 400:7fa56b1b9d45 715
mbed_official 400:7fa56b1b9d45 716
mbed_official 400:7fa56b1b9d45 717 /**
mbed_official 400:7fa56b1b9d45 718 * @brief __USB_OTG_Core_register
mbed_official 400:7fa56b1b9d45 719 */
mbed_official 400:7fa56b1b9d45 720 typedef struct
mbed_official 400:7fa56b1b9d45 721 {
mbed_official 400:7fa56b1b9d45 722 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
mbed_official 400:7fa56b1b9d45 723 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
mbed_official 400:7fa56b1b9d45 724 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
mbed_official 400:7fa56b1b9d45 725 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
mbed_official 400:7fa56b1b9d45 726 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
mbed_official 400:7fa56b1b9d45 727 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
mbed_official 400:7fa56b1b9d45 728 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
mbed_official 400:7fa56b1b9d45 729 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
mbed_official 400:7fa56b1b9d45 730 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
mbed_official 400:7fa56b1b9d45 731 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
mbed_official 400:7fa56b1b9d45 732 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
mbed_official 400:7fa56b1b9d45 733 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
mbed_official 400:7fa56b1b9d45 734 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
mbed_official 400:7fa56b1b9d45 735 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
mbed_official 400:7fa56b1b9d45 736 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
mbed_official 400:7fa56b1b9d45 737 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
mbed_official 400:7fa56b1b9d45 738 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
mbed_official 400:7fa56b1b9d45 739 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
mbed_official 400:7fa56b1b9d45 740 }
mbed_official 400:7fa56b1b9d45 741 USB_OTG_GlobalTypeDef;
mbed_official 400:7fa56b1b9d45 742
mbed_official 400:7fa56b1b9d45 743
mbed_official 400:7fa56b1b9d45 744
mbed_official 400:7fa56b1b9d45 745 /**
mbed_official 400:7fa56b1b9d45 746 * @brief __device_Registers
mbed_official 400:7fa56b1b9d45 747 */
mbed_official 400:7fa56b1b9d45 748 typedef struct
mbed_official 400:7fa56b1b9d45 749 {
mbed_official 400:7fa56b1b9d45 750 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
mbed_official 400:7fa56b1b9d45 751 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
mbed_official 400:7fa56b1b9d45 752 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
mbed_official 400:7fa56b1b9d45 753 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
mbed_official 400:7fa56b1b9d45 754 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
mbed_official 400:7fa56b1b9d45 755 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
mbed_official 400:7fa56b1b9d45 756 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
mbed_official 400:7fa56b1b9d45 757 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
mbed_official 400:7fa56b1b9d45 758 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
mbed_official 400:7fa56b1b9d45 759 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
mbed_official 400:7fa56b1b9d45 760 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
mbed_official 400:7fa56b1b9d45 761 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
mbed_official 400:7fa56b1b9d45 762 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
mbed_official 400:7fa56b1b9d45 763 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
mbed_official 400:7fa56b1b9d45 764 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
mbed_official 400:7fa56b1b9d45 765 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
mbed_official 400:7fa56b1b9d45 766 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
mbed_official 400:7fa56b1b9d45 767 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
mbed_official 400:7fa56b1b9d45 768 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
mbed_official 400:7fa56b1b9d45 769 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
mbed_official 400:7fa56b1b9d45 770 }
mbed_official 400:7fa56b1b9d45 771 USB_OTG_DeviceTypeDef;
mbed_official 400:7fa56b1b9d45 772
mbed_official 400:7fa56b1b9d45 773
mbed_official 400:7fa56b1b9d45 774 /**
mbed_official 400:7fa56b1b9d45 775 * @brief __IN_Endpoint-Specific_Register
mbed_official 400:7fa56b1b9d45 776 */
mbed_official 400:7fa56b1b9d45 777 typedef struct
mbed_official 400:7fa56b1b9d45 778 {
mbed_official 400:7fa56b1b9d45 779 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
mbed_official 400:7fa56b1b9d45 780 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
mbed_official 400:7fa56b1b9d45 781 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
mbed_official 400:7fa56b1b9d45 782 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
mbed_official 400:7fa56b1b9d45 783 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
mbed_official 400:7fa56b1b9d45 784 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
mbed_official 400:7fa56b1b9d45 785 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
mbed_official 400:7fa56b1b9d45 786 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
mbed_official 400:7fa56b1b9d45 787 }
mbed_official 400:7fa56b1b9d45 788 USB_OTG_INEndpointTypeDef;
mbed_official 400:7fa56b1b9d45 789
mbed_official 400:7fa56b1b9d45 790
mbed_official 400:7fa56b1b9d45 791 /**
mbed_official 400:7fa56b1b9d45 792 * @brief __OUT_Endpoint-Specific_Registers
mbed_official 400:7fa56b1b9d45 793 */
mbed_official 400:7fa56b1b9d45 794 typedef struct
mbed_official 400:7fa56b1b9d45 795 {
mbed_official 400:7fa56b1b9d45 796 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
mbed_official 400:7fa56b1b9d45 797 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
mbed_official 400:7fa56b1b9d45 798 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
mbed_official 400:7fa56b1b9d45 799 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
mbed_official 400:7fa56b1b9d45 800 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
mbed_official 400:7fa56b1b9d45 801 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
mbed_official 400:7fa56b1b9d45 802 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
mbed_official 400:7fa56b1b9d45 803 }
mbed_official 400:7fa56b1b9d45 804 USB_OTG_OUTEndpointTypeDef;
mbed_official 400:7fa56b1b9d45 805
mbed_official 400:7fa56b1b9d45 806
mbed_official 400:7fa56b1b9d45 807 /**
mbed_official 400:7fa56b1b9d45 808 * @brief __Host_Mode_Register_Structures
mbed_official 400:7fa56b1b9d45 809 */
mbed_official 400:7fa56b1b9d45 810 typedef struct
mbed_official 400:7fa56b1b9d45 811 {
mbed_official 400:7fa56b1b9d45 812 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
mbed_official 400:7fa56b1b9d45 813 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
mbed_official 400:7fa56b1b9d45 814 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
mbed_official 400:7fa56b1b9d45 815 uint32_t Reserved40C; /* Reserved 40Ch*/
mbed_official 400:7fa56b1b9d45 816 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
mbed_official 400:7fa56b1b9d45 817 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
mbed_official 400:7fa56b1b9d45 818 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
mbed_official 400:7fa56b1b9d45 819 }
mbed_official 400:7fa56b1b9d45 820 USB_OTG_HostTypeDef;
mbed_official 400:7fa56b1b9d45 821
mbed_official 400:7fa56b1b9d45 822
mbed_official 400:7fa56b1b9d45 823 /**
mbed_official 400:7fa56b1b9d45 824 * @brief __Host_Channel_Specific_Registers
mbed_official 400:7fa56b1b9d45 825 */
mbed_official 400:7fa56b1b9d45 826 typedef struct
mbed_official 400:7fa56b1b9d45 827 {
mbed_official 400:7fa56b1b9d45 828 __IO uint32_t HCCHAR;
mbed_official 400:7fa56b1b9d45 829 __IO uint32_t HCSPLT;
mbed_official 400:7fa56b1b9d45 830 __IO uint32_t HCINT;
mbed_official 400:7fa56b1b9d45 831 __IO uint32_t HCINTMSK;
mbed_official 400:7fa56b1b9d45 832 __IO uint32_t HCTSIZ;
mbed_official 400:7fa56b1b9d45 833 __IO uint32_t HCDMA;
mbed_official 400:7fa56b1b9d45 834 uint32_t Reserved[2];
mbed_official 400:7fa56b1b9d45 835 }
mbed_official 400:7fa56b1b9d45 836 USB_OTG_HostChannelTypeDef;
mbed_official 400:7fa56b1b9d45 837
mbed_official 400:7fa56b1b9d45 838
mbed_official 400:7fa56b1b9d45 839 /**
mbed_official 400:7fa56b1b9d45 840 * @brief Peripheral_memory_map
mbed_official 400:7fa56b1b9d45 841 */
mbed_official 400:7fa56b1b9d45 842 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
mbed_official 400:7fa56b1b9d45 843 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
mbed_official 400:7fa56b1b9d45 844 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
mbed_official 400:7fa56b1b9d45 845 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
mbed_official 400:7fa56b1b9d45 846 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 400:7fa56b1b9d45 847 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
mbed_official 400:7fa56b1b9d45 848 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
mbed_official 400:7fa56b1b9d45 849 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
mbed_official 613:bc40b8d2aec4 850 #define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
mbed_official 400:7fa56b1b9d45 851 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 613:bc40b8d2aec4 852 #define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
mbed_official 400:7fa56b1b9d45 853 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
mbed_official 400:7fa56b1b9d45 854 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
mbed_official 400:7fa56b1b9d45 855
mbed_official 400:7fa56b1b9d45 856 /* Legacy defines */
mbed_official 400:7fa56b1b9d45 857 #define SRAM_BASE SRAM1_BASE
mbed_official 400:7fa56b1b9d45 858 #define SRAM_BB_BASE SRAM1_BB_BASE
mbed_official 400:7fa56b1b9d45 859
mbed_official 400:7fa56b1b9d45 860
mbed_official 400:7fa56b1b9d45 861 /*!< Peripheral memory map */
mbed_official 400:7fa56b1b9d45 862 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 400:7fa56b1b9d45 863 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 400:7fa56b1b9d45 864 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 400:7fa56b1b9d45 865 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 400:7fa56b1b9d45 866
mbed_official 400:7fa56b1b9d45 867 /*!< APB1 peripherals */
mbed_official 400:7fa56b1b9d45 868 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
mbed_official 400:7fa56b1b9d45 869 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
mbed_official 400:7fa56b1b9d45 870 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
mbed_official 400:7fa56b1b9d45 871 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
mbed_official 400:7fa56b1b9d45 872 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
mbed_official 400:7fa56b1b9d45 873 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
mbed_official 400:7fa56b1b9d45 874 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
mbed_official 400:7fa56b1b9d45 875 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
mbed_official 400:7fa56b1b9d45 876 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
mbed_official 400:7fa56b1b9d45 877 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official 400:7fa56b1b9d45 878 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official 400:7fa56b1b9d45 879 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official 400:7fa56b1b9d45 880 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
mbed_official 400:7fa56b1b9d45 881 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official 400:7fa56b1b9d45 882 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
mbed_official 400:7fa56b1b9d45 883 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
mbed_official 400:7fa56b1b9d45 884 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official 400:7fa56b1b9d45 885 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
mbed_official 400:7fa56b1b9d45 886 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
mbed_official 400:7fa56b1b9d45 887 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
mbed_official 400:7fa56b1b9d45 888 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official 400:7fa56b1b9d45 889 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official 400:7fa56b1b9d45 890 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
mbed_official 400:7fa56b1b9d45 891 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
mbed_official 400:7fa56b1b9d45 892 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
mbed_official 400:7fa56b1b9d45 893 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official 400:7fa56b1b9d45 894 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
mbed_official 400:7fa56b1b9d45 895
mbed_official 400:7fa56b1b9d45 896 /*!< APB2 peripherals */
mbed_official 400:7fa56b1b9d45 897 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official 400:7fa56b1b9d45 898 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
mbed_official 400:7fa56b1b9d45 899 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official 400:7fa56b1b9d45 900 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
mbed_official 400:7fa56b1b9d45 901 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
mbed_official 400:7fa56b1b9d45 902 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
mbed_official 400:7fa56b1b9d45 903 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
mbed_official 400:7fa56b1b9d45 904 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
mbed_official 400:7fa56b1b9d45 905 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
mbed_official 400:7fa56b1b9d45 906 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official 400:7fa56b1b9d45 907 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official 400:7fa56b1b9d45 908 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
mbed_official 400:7fa56b1b9d45 909 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
mbed_official 400:7fa56b1b9d45 910 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
mbed_official 400:7fa56b1b9d45 911 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
mbed_official 400:7fa56b1b9d45 912
mbed_official 400:7fa56b1b9d45 913 /*!< AHB1 peripherals */
mbed_official 400:7fa56b1b9d45 914 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
mbed_official 400:7fa56b1b9d45 915 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
mbed_official 400:7fa56b1b9d45 916 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
mbed_official 400:7fa56b1b9d45 917 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
mbed_official 400:7fa56b1b9d45 918 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
mbed_official 400:7fa56b1b9d45 919 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
mbed_official 400:7fa56b1b9d45 920 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
mbed_official 400:7fa56b1b9d45 921 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
mbed_official 400:7fa56b1b9d45 922 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
mbed_official 400:7fa56b1b9d45 923 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
mbed_official 400:7fa56b1b9d45 924 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
mbed_official 400:7fa56b1b9d45 925 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
mbed_official 400:7fa56b1b9d45 926 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
mbed_official 400:7fa56b1b9d45 927 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
mbed_official 400:7fa56b1b9d45 928 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
mbed_official 400:7fa56b1b9d45 929 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
mbed_official 400:7fa56b1b9d45 930 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
mbed_official 400:7fa56b1b9d45 931 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
mbed_official 400:7fa56b1b9d45 932 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
mbed_official 400:7fa56b1b9d45 933 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
mbed_official 400:7fa56b1b9d45 934 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
mbed_official 400:7fa56b1b9d45 935 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
mbed_official 400:7fa56b1b9d45 936 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
mbed_official 400:7fa56b1b9d45 937 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
mbed_official 400:7fa56b1b9d45 938 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
mbed_official 400:7fa56b1b9d45 939 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
mbed_official 400:7fa56b1b9d45 940 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
mbed_official 400:7fa56b1b9d45 941 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
mbed_official 400:7fa56b1b9d45 942 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
mbed_official 400:7fa56b1b9d45 943 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
mbed_official 400:7fa56b1b9d45 944
mbed_official 400:7fa56b1b9d45 945 /*!< AHB2 peripherals */
mbed_official 400:7fa56b1b9d45 946 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
mbed_official 400:7fa56b1b9d45 947
mbed_official 400:7fa56b1b9d45 948 /*!< FSMC Bankx registers base address */
mbed_official 400:7fa56b1b9d45 949 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
mbed_official 400:7fa56b1b9d45 950 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
mbed_official 400:7fa56b1b9d45 951 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
mbed_official 400:7fa56b1b9d45 952 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
mbed_official 400:7fa56b1b9d45 953
mbed_official 400:7fa56b1b9d45 954 /* Debug MCU registers base address */
mbed_official 400:7fa56b1b9d45 955 #define DBGMCU_BASE ((uint32_t )0xE0042000)
mbed_official 400:7fa56b1b9d45 956
mbed_official 400:7fa56b1b9d45 957 /*!< USB registers base address */
mbed_official 400:7fa56b1b9d45 958 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
mbed_official 400:7fa56b1b9d45 959 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
mbed_official 400:7fa56b1b9d45 960
mbed_official 400:7fa56b1b9d45 961 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
mbed_official 400:7fa56b1b9d45 962 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
mbed_official 400:7fa56b1b9d45 963 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
mbed_official 400:7fa56b1b9d45 964 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
mbed_official 400:7fa56b1b9d45 965 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
mbed_official 400:7fa56b1b9d45 966 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
mbed_official 400:7fa56b1b9d45 967 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
mbed_official 400:7fa56b1b9d45 968 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
mbed_official 400:7fa56b1b9d45 969 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
mbed_official 400:7fa56b1b9d45 970 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
mbed_official 400:7fa56b1b9d45 971 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
mbed_official 400:7fa56b1b9d45 972 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
mbed_official 400:7fa56b1b9d45 973
mbed_official 400:7fa56b1b9d45 974 /**
mbed_official 400:7fa56b1b9d45 975 * @}
mbed_official 400:7fa56b1b9d45 976 */
mbed_official 400:7fa56b1b9d45 977
mbed_official 400:7fa56b1b9d45 978 /** @addtogroup Peripheral_declaration
mbed_official 400:7fa56b1b9d45 979 * @{
mbed_official 400:7fa56b1b9d45 980 */
mbed_official 400:7fa56b1b9d45 981 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 400:7fa56b1b9d45 982 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 400:7fa56b1b9d45 983 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 400:7fa56b1b9d45 984 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 400:7fa56b1b9d45 985 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 400:7fa56b1b9d45 986 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 400:7fa56b1b9d45 987 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
mbed_official 400:7fa56b1b9d45 988 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
mbed_official 400:7fa56b1b9d45 989 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 400:7fa56b1b9d45 990 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 400:7fa56b1b9d45 991 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 400:7fa56b1b9d45 992 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 400:7fa56b1b9d45 993 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
mbed_official 400:7fa56b1b9d45 994 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 400:7fa56b1b9d45 995 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 400:7fa56b1b9d45 996 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
mbed_official 400:7fa56b1b9d45 997 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 400:7fa56b1b9d45 998 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 400:7fa56b1b9d45 999 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 400:7fa56b1b9d45 1000 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 400:7fa56b1b9d45 1001 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 400:7fa56b1b9d45 1002 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 400:7fa56b1b9d45 1003 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 400:7fa56b1b9d45 1004 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
mbed_official 400:7fa56b1b9d45 1005 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
mbed_official 400:7fa56b1b9d45 1006 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 400:7fa56b1b9d45 1007 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 400:7fa56b1b9d45 1008 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 400:7fa56b1b9d45 1009 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 400:7fa56b1b9d45 1010 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 400:7fa56b1b9d45 1011 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 400:7fa56b1b9d45 1012 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 400:7fa56b1b9d45 1013 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 400:7fa56b1b9d45 1014 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 400:7fa56b1b9d45 1015 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 400:7fa56b1b9d45 1016 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
mbed_official 400:7fa56b1b9d45 1017 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 400:7fa56b1b9d45 1018 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 400:7fa56b1b9d45 1019 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 400:7fa56b1b9d45 1020 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 400:7fa56b1b9d45 1021 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 400:7fa56b1b9d45 1022 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 400:7fa56b1b9d45 1023 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 400:7fa56b1b9d45 1024 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 400:7fa56b1b9d45 1025 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 400:7fa56b1b9d45 1026 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 400:7fa56b1b9d45 1027 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 400:7fa56b1b9d45 1028 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 400:7fa56b1b9d45 1029 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official 400:7fa56b1b9d45 1030 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 400:7fa56b1b9d45 1031 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
mbed_official 400:7fa56b1b9d45 1032 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 400:7fa56b1b9d45 1033 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 400:7fa56b1b9d45 1034 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 400:7fa56b1b9d45 1035 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 400:7fa56b1b9d45 1036 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 400:7fa56b1b9d45 1037 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 400:7fa56b1b9d45 1038 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 400:7fa56b1b9d45 1039 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 400:7fa56b1b9d45 1040 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 400:7fa56b1b9d45 1041 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 400:7fa56b1b9d45 1042 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 400:7fa56b1b9d45 1043 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 400:7fa56b1b9d45 1044 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 400:7fa56b1b9d45 1045 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 400:7fa56b1b9d45 1046 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 400:7fa56b1b9d45 1047 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 400:7fa56b1b9d45 1048 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 400:7fa56b1b9d45 1049 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 400:7fa56b1b9d45 1050 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 400:7fa56b1b9d45 1051 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 400:7fa56b1b9d45 1052 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 400:7fa56b1b9d45 1053 #define RNG ((RNG_TypeDef *) RNG_BASE)
mbed_official 400:7fa56b1b9d45 1054 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
mbed_official 400:7fa56b1b9d45 1055 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
mbed_official 400:7fa56b1b9d45 1056 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
mbed_official 400:7fa56b1b9d45 1057 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
mbed_official 400:7fa56b1b9d45 1058
mbed_official 400:7fa56b1b9d45 1059 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 400:7fa56b1b9d45 1060
mbed_official 400:7fa56b1b9d45 1061 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
mbed_official 400:7fa56b1b9d45 1062 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
mbed_official 400:7fa56b1b9d45 1063
mbed_official 400:7fa56b1b9d45 1064 /**
mbed_official 400:7fa56b1b9d45 1065 * @}
mbed_official 400:7fa56b1b9d45 1066 */
mbed_official 400:7fa56b1b9d45 1067
mbed_official 400:7fa56b1b9d45 1068 /** @addtogroup Exported_constants
mbed_official 400:7fa56b1b9d45 1069 * @{
mbed_official 400:7fa56b1b9d45 1070 */
mbed_official 400:7fa56b1b9d45 1071
mbed_official 400:7fa56b1b9d45 1072 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 400:7fa56b1b9d45 1073 * @{
mbed_official 400:7fa56b1b9d45 1074 */
mbed_official 400:7fa56b1b9d45 1075
mbed_official 400:7fa56b1b9d45 1076 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 1077 /* Peripheral Registers_Bits_Definition */
mbed_official 400:7fa56b1b9d45 1078 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 1079
mbed_official 400:7fa56b1b9d45 1080 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 1081 /* */
mbed_official 400:7fa56b1b9d45 1082 /* Analog to Digital Converter */
mbed_official 400:7fa56b1b9d45 1083 /* */
mbed_official 400:7fa56b1b9d45 1084 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 1085 /******************** Bit definition for ADC_SR register ********************/
mbed_official 400:7fa56b1b9d45 1086 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
mbed_official 400:7fa56b1b9d45 1087 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
mbed_official 400:7fa56b1b9d45 1088 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
mbed_official 400:7fa56b1b9d45 1089 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
mbed_official 400:7fa56b1b9d45 1090 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
mbed_official 400:7fa56b1b9d45 1091 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
mbed_official 400:7fa56b1b9d45 1092
mbed_official 400:7fa56b1b9d45 1093 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 400:7fa56b1b9d45 1094 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 400:7fa56b1b9d45 1095 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1096 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1097 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1098 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1099 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1100 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
mbed_official 400:7fa56b1b9d45 1101 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
mbed_official 400:7fa56b1b9d45 1102 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
mbed_official 400:7fa56b1b9d45 1103 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
mbed_official 400:7fa56b1b9d45 1104 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
mbed_official 400:7fa56b1b9d45 1105 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
mbed_official 400:7fa56b1b9d45 1106 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
mbed_official 400:7fa56b1b9d45 1107 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
mbed_official 400:7fa56b1b9d45 1108 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 400:7fa56b1b9d45 1109 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1110 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1111 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1112 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
mbed_official 400:7fa56b1b9d45 1113 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
mbed_official 400:7fa56b1b9d45 1114 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
mbed_official 400:7fa56b1b9d45 1115 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1116 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1117 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
mbed_official 400:7fa56b1b9d45 1118
mbed_official 400:7fa56b1b9d45 1119 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 400:7fa56b1b9d45 1120 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
mbed_official 400:7fa56b1b9d45 1121 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
mbed_official 400:7fa56b1b9d45 1122 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
mbed_official 400:7fa56b1b9d45 1123 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
mbed_official 400:7fa56b1b9d45 1124 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
mbed_official 400:7fa56b1b9d45 1125 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
mbed_official 400:7fa56b1b9d45 1126 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 400:7fa56b1b9d45 1127 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1128 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1129 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1130 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1131 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
mbed_official 400:7fa56b1b9d45 1132 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1133 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1134 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
mbed_official 400:7fa56b1b9d45 1135 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 400:7fa56b1b9d45 1136 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1137 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1138 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1139 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1140 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
mbed_official 400:7fa56b1b9d45 1141 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1142 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1143 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
mbed_official 400:7fa56b1b9d45 1144
mbed_official 400:7fa56b1b9d45 1145 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 400:7fa56b1b9d45 1146 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1147 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1148 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1149 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1150 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1151 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1152 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1153 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1154 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1155 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1156 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1157 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1158 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1159 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1160 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1161 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1162 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1163 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1164 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1165 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1166 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1167 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1168 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1169 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1170 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1171 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1172 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1173 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1174 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1175 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1176 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1177 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1178 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1179 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1180 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1181 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1182
mbed_official 400:7fa56b1b9d45 1183 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 400:7fa56b1b9d45 1184 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1185 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1186 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1187 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1188 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1189 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1190 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1191 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1192 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1193 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1194 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1195 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1196 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1197 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1198 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1199 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1200 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1201 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1202 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1203 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1204 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1205 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1206 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1207 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1208 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1209 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1210 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1211 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1212 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1213 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1214 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1215 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1216 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1217 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1218 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1219 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1220 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 400:7fa56b1b9d45 1221 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1222 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1223 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1224
mbed_official 400:7fa56b1b9d45 1225 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 400:7fa56b1b9d45 1226 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
mbed_official 400:7fa56b1b9d45 1227
mbed_official 400:7fa56b1b9d45 1228 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 400:7fa56b1b9d45 1229 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
mbed_official 400:7fa56b1b9d45 1230
mbed_official 400:7fa56b1b9d45 1231 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 400:7fa56b1b9d45 1232 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
mbed_official 400:7fa56b1b9d45 1233
mbed_official 400:7fa56b1b9d45 1234 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 400:7fa56b1b9d45 1235 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
mbed_official 400:7fa56b1b9d45 1236
mbed_official 400:7fa56b1b9d45 1237 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 400:7fa56b1b9d45 1238 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
mbed_official 400:7fa56b1b9d45 1239
mbed_official 400:7fa56b1b9d45 1240 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 400:7fa56b1b9d45 1241 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
mbed_official 400:7fa56b1b9d45 1242
mbed_official 400:7fa56b1b9d45 1243 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 400:7fa56b1b9d45 1244 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1245 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1246 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1247 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1248 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1249 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1250 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1251 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1252 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1253 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1254 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1255 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1256 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1257 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1258 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1259 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1260 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1261 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1262 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1263 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1264 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1265 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1266 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1267 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1268 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
mbed_official 400:7fa56b1b9d45 1269 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1270 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1271 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1272 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1273
mbed_official 400:7fa56b1b9d45 1274 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 400:7fa56b1b9d45 1275 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1276 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1277 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1278 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1279 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1280 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1281 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1282 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1283 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1284 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1285 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1286 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1287 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1288 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1289 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1290 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1291 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1292 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1293 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1294 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1295 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1296 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1297 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1298 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1299 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1300 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1301 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1302 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1303 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1304 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1305 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1306 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1307 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1308 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1309 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1310 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1311
mbed_official 400:7fa56b1b9d45 1312 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 400:7fa56b1b9d45 1313 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1314 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1315 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1316 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1317 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1318 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1319 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1320 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1321 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1322 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1323 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1324 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1325 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1326 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1327 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1328 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1329 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1330 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1331 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1332 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1333 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1334 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1335 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1336 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1337 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1338 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1339 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1340 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1341 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1342 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1343 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 400:7fa56b1b9d45 1344 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1345 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1346 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1347 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1348 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1349
mbed_official 400:7fa56b1b9d45 1350 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 400:7fa56b1b9d45 1351 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 400:7fa56b1b9d45 1352 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1353 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1354 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1355 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1356 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1357 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 400:7fa56b1b9d45 1358 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1359 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1360 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1361 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1362 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1363 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 400:7fa56b1b9d45 1364 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1365 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1366 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1367 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1368 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1369 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 400:7fa56b1b9d45 1370 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1371 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1372 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1373 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1374 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1375 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
mbed_official 400:7fa56b1b9d45 1376 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1377 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1378
mbed_official 400:7fa56b1b9d45 1379 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 400:7fa56b1b9d45 1380 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 400:7fa56b1b9d45 1381
mbed_official 400:7fa56b1b9d45 1382 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 400:7fa56b1b9d45 1383 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 400:7fa56b1b9d45 1384
mbed_official 400:7fa56b1b9d45 1385 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 400:7fa56b1b9d45 1386 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 400:7fa56b1b9d45 1387
mbed_official 400:7fa56b1b9d45 1388 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 400:7fa56b1b9d45 1389 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 400:7fa56b1b9d45 1390
mbed_official 400:7fa56b1b9d45 1391 /******************** Bit definition for ADC_DR register ********************/
mbed_official 400:7fa56b1b9d45 1392 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
mbed_official 400:7fa56b1b9d45 1393 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
mbed_official 400:7fa56b1b9d45 1394
mbed_official 400:7fa56b1b9d45 1395 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 400:7fa56b1b9d45 1396 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
mbed_official 400:7fa56b1b9d45 1397 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
mbed_official 400:7fa56b1b9d45 1398 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
mbed_official 400:7fa56b1b9d45 1399 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
mbed_official 400:7fa56b1b9d45 1400 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
mbed_official 400:7fa56b1b9d45 1401 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
mbed_official 400:7fa56b1b9d45 1402 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
mbed_official 400:7fa56b1b9d45 1403 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
mbed_official 400:7fa56b1b9d45 1404 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
mbed_official 400:7fa56b1b9d45 1405 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
mbed_official 400:7fa56b1b9d45 1406 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
mbed_official 400:7fa56b1b9d45 1407 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
mbed_official 400:7fa56b1b9d45 1408 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
mbed_official 400:7fa56b1b9d45 1409 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
mbed_official 400:7fa56b1b9d45 1410 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
mbed_official 400:7fa56b1b9d45 1411 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
mbed_official 400:7fa56b1b9d45 1412 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
mbed_official 400:7fa56b1b9d45 1413 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
mbed_official 400:7fa56b1b9d45 1414
mbed_official 400:7fa56b1b9d45 1415 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 400:7fa56b1b9d45 1416 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
mbed_official 400:7fa56b1b9d45 1417 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1418 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1419 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1420 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1421 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 1422 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
mbed_official 400:7fa56b1b9d45 1423 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1424 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1425 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1426 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1427 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
mbed_official 400:7fa56b1b9d45 1428 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
mbed_official 400:7fa56b1b9d45 1429 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1430 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1431 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
mbed_official 400:7fa56b1b9d45 1432 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1433 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1434 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
mbed_official 400:7fa56b1b9d45 1435 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
mbed_official 400:7fa56b1b9d45 1436
mbed_official 400:7fa56b1b9d45 1437 /******************* Bit definition for ADC_CDR register ********************/
mbed_official 400:7fa56b1b9d45 1438 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
mbed_official 400:7fa56b1b9d45 1439 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
mbed_official 400:7fa56b1b9d45 1440
mbed_official 400:7fa56b1b9d45 1441 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 1442 /* */
mbed_official 400:7fa56b1b9d45 1443 /* Controller Area Network */
mbed_official 400:7fa56b1b9d45 1444 /* */
mbed_official 400:7fa56b1b9d45 1445 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 1446 /*!<CAN control and status registers */
mbed_official 400:7fa56b1b9d45 1447 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 400:7fa56b1b9d45 1448 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 400:7fa56b1b9d45 1449 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 400:7fa56b1b9d45 1450 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 400:7fa56b1b9d45 1451 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 400:7fa56b1b9d45 1452 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 400:7fa56b1b9d45 1453 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 400:7fa56b1b9d45 1454 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 400:7fa56b1b9d45 1455 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 400:7fa56b1b9d45 1456 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 400:7fa56b1b9d45 1457 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
mbed_official 400:7fa56b1b9d45 1458 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 400:7fa56b1b9d45 1459 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
mbed_official 400:7fa56b1b9d45 1460 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
mbed_official 400:7fa56b1b9d45 1461 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
mbed_official 400:7fa56b1b9d45 1462 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
mbed_official 400:7fa56b1b9d45 1463 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
mbed_official 400:7fa56b1b9d45 1464 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
mbed_official 400:7fa56b1b9d45 1465 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
mbed_official 400:7fa56b1b9d45 1466 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
mbed_official 400:7fa56b1b9d45 1467 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
mbed_official 400:7fa56b1b9d45 1468
mbed_official 400:7fa56b1b9d45 1469 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 400:7fa56b1b9d45 1470 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 400:7fa56b1b9d45 1471 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 400:7fa56b1b9d45 1472 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 400:7fa56b1b9d45 1473 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 400:7fa56b1b9d45 1474 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 400:7fa56b1b9d45 1475 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 400:7fa56b1b9d45 1476 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 400:7fa56b1b9d45 1477 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 400:7fa56b1b9d45 1478 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 400:7fa56b1b9d45 1479 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 400:7fa56b1b9d45 1480 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 400:7fa56b1b9d45 1481 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 400:7fa56b1b9d45 1482 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 400:7fa56b1b9d45 1483 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 400:7fa56b1b9d45 1484 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 400:7fa56b1b9d45 1485 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 400:7fa56b1b9d45 1486
mbed_official 400:7fa56b1b9d45 1487 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 400:7fa56b1b9d45 1488 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 400:7fa56b1b9d45 1489 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 400:7fa56b1b9d45 1490 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 400:7fa56b1b9d45 1491
mbed_official 400:7fa56b1b9d45 1492 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 400:7fa56b1b9d45 1493 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 400:7fa56b1b9d45 1494 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 400:7fa56b1b9d45 1495 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 400:7fa56b1b9d45 1496
mbed_official 400:7fa56b1b9d45 1497 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 400:7fa56b1b9d45 1498 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
mbed_official 400:7fa56b1b9d45 1499 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
mbed_official 400:7fa56b1b9d45 1500 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
mbed_official 400:7fa56b1b9d45 1501 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
mbed_official 400:7fa56b1b9d45 1502
mbed_official 400:7fa56b1b9d45 1503 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 400:7fa56b1b9d45 1504 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
mbed_official 400:7fa56b1b9d45 1505 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
mbed_official 400:7fa56b1b9d45 1506 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
mbed_official 400:7fa56b1b9d45 1507 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
mbed_official 400:7fa56b1b9d45 1508
mbed_official 400:7fa56b1b9d45 1509 /******************** Bit definition for CAN_IER register *******************/
mbed_official 400:7fa56b1b9d45 1510 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1511 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1512 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1513 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1514 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1515 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1516 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1517 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1518 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1519 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1520 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1521 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1522 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1523 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 400:7fa56b1b9d45 1524 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
mbed_official 400:7fa56b1b9d45 1525 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
mbed_official 400:7fa56b1b9d45 1526 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
mbed_official 400:7fa56b1b9d45 1527 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
mbed_official 400:7fa56b1b9d45 1528 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
mbed_official 400:7fa56b1b9d45 1529
mbed_official 400:7fa56b1b9d45 1530
mbed_official 400:7fa56b1b9d45 1531 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 400:7fa56b1b9d45 1532 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 400:7fa56b1b9d45 1533 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 400:7fa56b1b9d45 1534 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 400:7fa56b1b9d45 1535
mbed_official 400:7fa56b1b9d45 1536 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 400:7fa56b1b9d45 1537 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1538 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1539 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1540
mbed_official 400:7fa56b1b9d45 1541 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 400:7fa56b1b9d45 1542 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 400:7fa56b1b9d45 1543
mbed_official 400:7fa56b1b9d45 1544 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 400:7fa56b1b9d45 1545 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 400:7fa56b1b9d45 1546 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 400:7fa56b1b9d45 1547 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1548 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1549 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1550 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 1551 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 400:7fa56b1b9d45 1552 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1553 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1554 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 1555 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 400:7fa56b1b9d45 1556 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 1557 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 1558 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 400:7fa56b1b9d45 1559 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 400:7fa56b1b9d45 1560
mbed_official 400:7fa56b1b9d45 1561
mbed_official 400:7fa56b1b9d45 1562 /*!<Mailbox registers */
mbed_official 400:7fa56b1b9d45 1563 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 400:7fa56b1b9d45 1564 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 400:7fa56b1b9d45 1565 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 400:7fa56b1b9d45 1566 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 400:7fa56b1b9d45 1567 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 400:7fa56b1b9d45 1568 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 400:7fa56b1b9d45 1569
mbed_official 400:7fa56b1b9d45 1570 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 400:7fa56b1b9d45 1571 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 400:7fa56b1b9d45 1572 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 400:7fa56b1b9d45 1573 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 400:7fa56b1b9d45 1574
mbed_official 400:7fa56b1b9d45 1575 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 400:7fa56b1b9d45 1576 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 400:7fa56b1b9d45 1577 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 400:7fa56b1b9d45 1578 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 400:7fa56b1b9d45 1579 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 400:7fa56b1b9d45 1580
mbed_official 400:7fa56b1b9d45 1581 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 400:7fa56b1b9d45 1582 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 400:7fa56b1b9d45 1583 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 400:7fa56b1b9d45 1584 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 400:7fa56b1b9d45 1585 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 400:7fa56b1b9d45 1586
mbed_official 400:7fa56b1b9d45 1587 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 400:7fa56b1b9d45 1588 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 400:7fa56b1b9d45 1589 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 400:7fa56b1b9d45 1590 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 400:7fa56b1b9d45 1591 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 400:7fa56b1b9d45 1592 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 400:7fa56b1b9d45 1593
mbed_official 400:7fa56b1b9d45 1594 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 400:7fa56b1b9d45 1595 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 400:7fa56b1b9d45 1596 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 400:7fa56b1b9d45 1597 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 400:7fa56b1b9d45 1598
mbed_official 400:7fa56b1b9d45 1599 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 400:7fa56b1b9d45 1600 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 400:7fa56b1b9d45 1601 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 400:7fa56b1b9d45 1602 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 400:7fa56b1b9d45 1603 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 400:7fa56b1b9d45 1604
mbed_official 400:7fa56b1b9d45 1605 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 400:7fa56b1b9d45 1606 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 400:7fa56b1b9d45 1607 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 400:7fa56b1b9d45 1608 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 400:7fa56b1b9d45 1609 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 400:7fa56b1b9d45 1610
mbed_official 400:7fa56b1b9d45 1611 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 400:7fa56b1b9d45 1612 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 400:7fa56b1b9d45 1613 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 400:7fa56b1b9d45 1614 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 400:7fa56b1b9d45 1615 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 400:7fa56b1b9d45 1616 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 400:7fa56b1b9d45 1617
mbed_official 400:7fa56b1b9d45 1618 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 400:7fa56b1b9d45 1619 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 400:7fa56b1b9d45 1620 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 400:7fa56b1b9d45 1621 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 400:7fa56b1b9d45 1622
mbed_official 400:7fa56b1b9d45 1623 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 400:7fa56b1b9d45 1624 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 400:7fa56b1b9d45 1625 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 400:7fa56b1b9d45 1626 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 400:7fa56b1b9d45 1627 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 400:7fa56b1b9d45 1628
mbed_official 400:7fa56b1b9d45 1629 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 400:7fa56b1b9d45 1630 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 400:7fa56b1b9d45 1631 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 400:7fa56b1b9d45 1632 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 400:7fa56b1b9d45 1633 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 400:7fa56b1b9d45 1634
mbed_official 400:7fa56b1b9d45 1635 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 400:7fa56b1b9d45 1636 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 400:7fa56b1b9d45 1637 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 400:7fa56b1b9d45 1638 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 400:7fa56b1b9d45 1639 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 400:7fa56b1b9d45 1640
mbed_official 400:7fa56b1b9d45 1641 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 400:7fa56b1b9d45 1642 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 400:7fa56b1b9d45 1643 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 400:7fa56b1b9d45 1644 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 400:7fa56b1b9d45 1645
mbed_official 400:7fa56b1b9d45 1646 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 400:7fa56b1b9d45 1647 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 400:7fa56b1b9d45 1648 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 400:7fa56b1b9d45 1649 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 400:7fa56b1b9d45 1650 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 400:7fa56b1b9d45 1651
mbed_official 400:7fa56b1b9d45 1652 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 400:7fa56b1b9d45 1653 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 400:7fa56b1b9d45 1654 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 400:7fa56b1b9d45 1655 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 400:7fa56b1b9d45 1656 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 400:7fa56b1b9d45 1657
mbed_official 400:7fa56b1b9d45 1658 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 400:7fa56b1b9d45 1659 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 400:7fa56b1b9d45 1660 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 400:7fa56b1b9d45 1661 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 400:7fa56b1b9d45 1662 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 400:7fa56b1b9d45 1663
mbed_official 400:7fa56b1b9d45 1664 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 400:7fa56b1b9d45 1665 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 400:7fa56b1b9d45 1666 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 400:7fa56b1b9d45 1667 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 400:7fa56b1b9d45 1668
mbed_official 400:7fa56b1b9d45 1669 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 400:7fa56b1b9d45 1670 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 400:7fa56b1b9d45 1671 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 400:7fa56b1b9d45 1672 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 400:7fa56b1b9d45 1673 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 400:7fa56b1b9d45 1674
mbed_official 400:7fa56b1b9d45 1675 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 400:7fa56b1b9d45 1676 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 400:7fa56b1b9d45 1677 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 400:7fa56b1b9d45 1678 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 400:7fa56b1b9d45 1679 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 400:7fa56b1b9d45 1680
mbed_official 400:7fa56b1b9d45 1681 /*!<CAN filter registers */
mbed_official 400:7fa56b1b9d45 1682 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 400:7fa56b1b9d45 1683 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
mbed_official 400:7fa56b1b9d45 1684 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
mbed_official 400:7fa56b1b9d45 1685
mbed_official 400:7fa56b1b9d45 1686 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 532:fe11edbda85c 1687 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
mbed_official 532:fe11edbda85c 1688 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
mbed_official 532:fe11edbda85c 1689 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
mbed_official 532:fe11edbda85c 1690 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
mbed_official 532:fe11edbda85c 1691 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
mbed_official 532:fe11edbda85c 1692 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
mbed_official 532:fe11edbda85c 1693 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
mbed_official 532:fe11edbda85c 1694 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
mbed_official 532:fe11edbda85c 1695 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
mbed_official 532:fe11edbda85c 1696 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
mbed_official 532:fe11edbda85c 1697 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
mbed_official 532:fe11edbda85c 1698 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
mbed_official 532:fe11edbda85c 1699 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
mbed_official 532:fe11edbda85c 1700 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
mbed_official 532:fe11edbda85c 1701 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
mbed_official 532:fe11edbda85c 1702 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
mbed_official 532:fe11edbda85c 1703 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
mbed_official 532:fe11edbda85c 1704 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
mbed_official 532:fe11edbda85c 1705 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
mbed_official 532:fe11edbda85c 1706 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
mbed_official 532:fe11edbda85c 1707 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
mbed_official 532:fe11edbda85c 1708 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
mbed_official 532:fe11edbda85c 1709 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
mbed_official 532:fe11edbda85c 1710 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
mbed_official 532:fe11edbda85c 1711 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
mbed_official 532:fe11edbda85c 1712 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
mbed_official 532:fe11edbda85c 1713 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
mbed_official 532:fe11edbda85c 1714 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
mbed_official 532:fe11edbda85c 1715 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
mbed_official 400:7fa56b1b9d45 1716
mbed_official 400:7fa56b1b9d45 1717 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 532:fe11edbda85c 1718 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
mbed_official 532:fe11edbda85c 1719 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 532:fe11edbda85c 1720 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 532:fe11edbda85c 1721 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 532:fe11edbda85c 1722 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 532:fe11edbda85c 1723 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 532:fe11edbda85c 1724 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 532:fe11edbda85c 1725 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 532:fe11edbda85c 1726 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 532:fe11edbda85c 1727 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 532:fe11edbda85c 1728 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 532:fe11edbda85c 1729 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 532:fe11edbda85c 1730 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 532:fe11edbda85c 1731 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 532:fe11edbda85c 1732 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 532:fe11edbda85c 1733 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
mbed_official 532:fe11edbda85c 1734 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
mbed_official 532:fe11edbda85c 1735 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
mbed_official 532:fe11edbda85c 1736 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
mbed_official 532:fe11edbda85c 1737 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
mbed_official 532:fe11edbda85c 1738 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
mbed_official 532:fe11edbda85c 1739 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
mbed_official 532:fe11edbda85c 1740 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
mbed_official 532:fe11edbda85c 1741 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
mbed_official 532:fe11edbda85c 1742 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
mbed_official 532:fe11edbda85c 1743 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
mbed_official 532:fe11edbda85c 1744 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
mbed_official 532:fe11edbda85c 1745 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
mbed_official 532:fe11edbda85c 1746 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
mbed_official 400:7fa56b1b9d45 1747
mbed_official 400:7fa56b1b9d45 1748 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 532:fe11edbda85c 1749 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
mbed_official 532:fe11edbda85c 1750 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
mbed_official 532:fe11edbda85c 1751 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
mbed_official 532:fe11edbda85c 1752 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
mbed_official 532:fe11edbda85c 1753 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
mbed_official 532:fe11edbda85c 1754 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
mbed_official 532:fe11edbda85c 1755 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
mbed_official 532:fe11edbda85c 1756 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
mbed_official 532:fe11edbda85c 1757 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
mbed_official 532:fe11edbda85c 1758 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
mbed_official 532:fe11edbda85c 1759 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
mbed_official 532:fe11edbda85c 1760 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
mbed_official 532:fe11edbda85c 1761 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
mbed_official 532:fe11edbda85c 1762 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
mbed_official 532:fe11edbda85c 1763 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
mbed_official 532:fe11edbda85c 1764 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
mbed_official 532:fe11edbda85c 1765 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
mbed_official 532:fe11edbda85c 1766 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
mbed_official 532:fe11edbda85c 1767 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
mbed_official 532:fe11edbda85c 1768 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
mbed_official 532:fe11edbda85c 1769 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
mbed_official 532:fe11edbda85c 1770 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
mbed_official 532:fe11edbda85c 1771 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
mbed_official 532:fe11edbda85c 1772 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
mbed_official 532:fe11edbda85c 1773 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
mbed_official 532:fe11edbda85c 1774 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
mbed_official 532:fe11edbda85c 1775 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
mbed_official 532:fe11edbda85c 1776 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
mbed_official 532:fe11edbda85c 1777 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
mbed_official 400:7fa56b1b9d45 1778
mbed_official 400:7fa56b1b9d45 1779 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 532:fe11edbda85c 1780 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
mbed_official 532:fe11edbda85c 1781 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
mbed_official 532:fe11edbda85c 1782 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
mbed_official 532:fe11edbda85c 1783 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
mbed_official 532:fe11edbda85c 1784 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
mbed_official 532:fe11edbda85c 1785 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
mbed_official 532:fe11edbda85c 1786 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
mbed_official 532:fe11edbda85c 1787 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
mbed_official 532:fe11edbda85c 1788 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
mbed_official 532:fe11edbda85c 1789 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
mbed_official 532:fe11edbda85c 1790 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
mbed_official 532:fe11edbda85c 1791 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
mbed_official 532:fe11edbda85c 1792 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
mbed_official 532:fe11edbda85c 1793 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
mbed_official 532:fe11edbda85c 1794 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
mbed_official 532:fe11edbda85c 1795 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
mbed_official 532:fe11edbda85c 1796 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
mbed_official 532:fe11edbda85c 1797 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
mbed_official 532:fe11edbda85c 1798 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
mbed_official 532:fe11edbda85c 1799 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
mbed_official 532:fe11edbda85c 1800 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
mbed_official 532:fe11edbda85c 1801 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
mbed_official 532:fe11edbda85c 1802 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
mbed_official 532:fe11edbda85c 1803 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
mbed_official 532:fe11edbda85c 1804 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
mbed_official 532:fe11edbda85c 1805 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
mbed_official 532:fe11edbda85c 1806 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
mbed_official 532:fe11edbda85c 1807 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
mbed_official 532:fe11edbda85c 1808 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
mbed_official 400:7fa56b1b9d45 1809
mbed_official 400:7fa56b1b9d45 1810 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 400:7fa56b1b9d45 1811 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 1812 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 1813 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 1814 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 1815 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 1816 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 1817 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 1818 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 1819 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 1820 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 1821 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 1822 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 1823 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 1824 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 1825 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 1826 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 1827 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 1828 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 1829 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 1830 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 1831 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 1832 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 1833 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 1834 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 1835 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 1836 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 1837 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 1838 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 1839 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 1840 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 1841 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 1842 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 1843
mbed_official 400:7fa56b1b9d45 1844 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 400:7fa56b1b9d45 1845 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 1846 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 1847 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 1848 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 1849 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 1850 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 1851 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 1852 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 1853 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 1854 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 1855 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 1856 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 1857 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 1858 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 1859 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 1860 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 1861 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 1862 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 1863 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 1864 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 1865 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 1866 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 1867 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 1868 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 1869 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 1870 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 1871 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 1872 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 1873 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 1874 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 1875 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 1876 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 1877
mbed_official 400:7fa56b1b9d45 1878 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 400:7fa56b1b9d45 1879 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 1880 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 1881 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 1882 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 1883 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 1884 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 1885 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 1886 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 1887 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 1888 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 1889 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 1890 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 1891 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 1892 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 1893 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 1894 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 1895 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 1896 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 1897 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 1898 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 1899 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 1900 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 1901 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 1902 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 1903 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 1904 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 1905 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 1906 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 1907 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 1908 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 1909 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 1910 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 1911
mbed_official 400:7fa56b1b9d45 1912 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 400:7fa56b1b9d45 1913 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 1914 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 1915 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 1916 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 1917 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 1918 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 1919 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 1920 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 1921 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 1922 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 1923 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 1924 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 1925 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 1926 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 1927 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 1928 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 1929 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 1930 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 1931 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 1932 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 1933 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 1934 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 1935 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 1936 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 1937 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 1938 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 1939 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 1940 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 1941 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 1942 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 1943 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 1944 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 1945
mbed_official 400:7fa56b1b9d45 1946 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 400:7fa56b1b9d45 1947 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 1948 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 1949 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 1950 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 1951 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 1952 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 1953 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 1954 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 1955 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 1956 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 1957 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 1958 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 1959 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 1960 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 1961 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 1962 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 1963 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 1964 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 1965 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 1966 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 1967 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 1968 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 1969 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 1970 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 1971 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 1972 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 1973 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 1974 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 1975 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 1976 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 1977 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 1978 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 1979
mbed_official 400:7fa56b1b9d45 1980 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 400:7fa56b1b9d45 1981 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 1982 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 1983 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 1984 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 1985 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 1986 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 1987 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 1988 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 1989 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 1990 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 1991 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 1992 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 1993 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 1994 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 1995 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 1996 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 1997 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 1998 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 1999 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2000 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2001 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2002 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2003 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2004 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2005 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2006 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2007 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2008 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2009 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2010 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2011 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2012 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2013
mbed_official 400:7fa56b1b9d45 2014 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 400:7fa56b1b9d45 2015 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2016 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2017 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2018 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2019 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2020 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2021 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2022 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2023 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2024 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2025 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2026 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2027 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2028 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2029 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2030 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2031 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2032 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2033 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2034 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2035 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2036 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2037 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2038 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2039 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2040 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2041 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2042 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2043 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2044 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2045 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2046 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2047
mbed_official 400:7fa56b1b9d45 2048 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 400:7fa56b1b9d45 2049 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2050 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2051 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2052 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2053 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2054 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2055 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2056 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2057 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2058 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2059 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2060 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2061 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2062 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2063 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2064 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2065 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2066 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2067 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2068 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2069 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2070 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2071 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2072 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2073 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2074 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2075 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2076 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2077 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2078 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2079 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2080 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2081
mbed_official 400:7fa56b1b9d45 2082 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 400:7fa56b1b9d45 2083 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2084 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2085 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2086 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2087 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2088 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2089 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2090 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2091 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2092 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2093 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2094 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2095 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2096 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2097 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2098 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2099 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2100 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2101 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2102 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2103 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2104 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2105 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2106 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2107 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2108 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2109 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2110 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2111 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2112 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2113 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2114 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2115
mbed_official 400:7fa56b1b9d45 2116 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 400:7fa56b1b9d45 2117 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2118 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2119 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2120 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2121 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2122 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2123 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2124 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2125 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2126 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2127 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2128 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2129 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2130 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2131 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2132 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2133 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2134 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2135 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2136 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2137 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2138 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2139 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2140 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2141 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2142 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2143 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2144 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2145 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2146 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2147 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2148 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2149
mbed_official 400:7fa56b1b9d45 2150 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 400:7fa56b1b9d45 2151 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2152 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2153 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2154 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2155 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2156 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2157 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2158 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2159 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2160 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2161 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2162 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2163 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2164 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2165 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2166 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2167 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2168 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2169 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2170 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2171 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2172 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2173 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2174 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2175 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2176 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2177 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2178 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2179 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2180 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2181 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2182 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2183
mbed_official 400:7fa56b1b9d45 2184 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 400:7fa56b1b9d45 2185 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2186 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2187 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2188 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2189 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2190 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2191 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2192 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2193 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2194 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2195 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2196 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2197 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2198 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2199 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2200 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2201 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2202 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2203 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2204 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2205 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2206 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2207 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2208 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2209 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2210 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2211 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2212 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2213 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2214 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2215 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2216 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2217
mbed_official 400:7fa56b1b9d45 2218 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 400:7fa56b1b9d45 2219 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2220 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2221 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2222 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2223 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2224 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2225 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2226 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2227 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2228 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2229 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2230 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2231 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2232 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2233 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2234 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2235 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2236 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2237 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2238 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2239 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2240 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2241 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2242 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2243 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2244 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2245 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2246 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2247 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2248 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2249 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2250 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2251
mbed_official 400:7fa56b1b9d45 2252 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 400:7fa56b1b9d45 2253 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2254 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2255 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2256 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2257 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2258 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2259 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2260 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2261 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2262 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2263 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2264 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2265 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2266 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2267 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2268 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2269 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2270 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2271 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2272 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2273 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2274 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2275 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2276 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2277 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2278 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2279 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2280 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2281 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2282 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2283 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2284 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2285
mbed_official 400:7fa56b1b9d45 2286 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 400:7fa56b1b9d45 2287 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2288 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2289 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2290 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2291 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2292 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2293 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2294 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2295 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2296 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2297 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2298 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2299 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2300 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2301 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2302 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2303 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2304 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2305 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2306 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2307 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2308 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2309 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2310 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2311 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2312 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2313 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2314 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2315 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2316 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2317 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2318 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2319
mbed_official 400:7fa56b1b9d45 2320 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 400:7fa56b1b9d45 2321 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2322 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2323 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2324 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2325 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2326 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2327 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2328 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2329 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2330 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2331 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2332 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2333 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2334 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2335 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2336 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2337 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2338 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2339 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2340 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2341 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2342 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2343 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2344 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2345 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2346 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2347 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2348 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2349 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2350 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2351 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2352 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2353
mbed_official 400:7fa56b1b9d45 2354 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 400:7fa56b1b9d45 2355 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2356 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2357 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2358 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2359 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2360 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2361 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2362 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2363 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2364 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2365 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2366 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2367 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2368 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2369 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2370 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2371 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2372 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2373 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2374 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2375 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2376 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2377 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2378 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2379 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2380 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2381 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2382 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2383 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2384 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2385 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2386 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2387
mbed_official 400:7fa56b1b9d45 2388 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 400:7fa56b1b9d45 2389 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2390 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2391 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2392 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2393 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2394 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2395 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2396 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2397 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2398 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2399 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2400 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2401 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2402 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2403 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2404 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2405 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2406 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2407 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2408 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2409 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2410 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2411 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2412 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2413 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2414 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2415 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2416 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2417 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2418 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2419 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2420 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2421
mbed_official 400:7fa56b1b9d45 2422 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 400:7fa56b1b9d45 2423 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2424 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2425 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2426 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2427 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2428 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2429 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2430 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2431 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2432 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2433 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2434 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2435 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2436 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2437 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2438 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2439 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2440 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2441 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2442 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2443 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2444 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2445 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2446 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2447 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2448 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2449 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2450 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2451 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2452 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2453 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2454 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2455
mbed_official 400:7fa56b1b9d45 2456 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 400:7fa56b1b9d45 2457 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2458 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2459 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2460 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2461 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2462 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2463 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2464 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2465 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2466 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2467 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2468 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2469 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2470 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2471 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2472 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2473 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2474 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2475 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2476 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2477 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2478 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2479 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2480 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2481 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2482 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2483 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2484 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2485 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2486 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2487 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2488 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2489
mbed_official 400:7fa56b1b9d45 2490 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 400:7fa56b1b9d45 2491 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2492 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2493 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2494 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2495 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2496 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2497 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2498 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2499 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2500 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2501 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2502 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2503 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2504 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2505 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2506 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2507 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2508 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2509 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2510 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2511 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2512 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2513 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2514 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2515 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2516 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2517 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2518 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2519 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2520 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2521 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2522 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2523
mbed_official 400:7fa56b1b9d45 2524 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 400:7fa56b1b9d45 2525 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2526 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2527 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2528 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2529 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2530 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2531 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2532 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2533 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2534 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2535 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2536 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2537 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2538 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2539 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2540 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2541 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2542 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2543 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2544 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2545 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2546 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2547 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2548 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2549 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2550 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2551 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2552 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2553 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2554 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2555 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2556 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2557
mbed_official 400:7fa56b1b9d45 2558 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 400:7fa56b1b9d45 2559 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2560 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2561 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2562 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2563 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2564 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2565 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2566 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2567 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2568 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2569 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2570 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2571 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2572 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2573 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2574 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2575 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2576 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2577 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2578 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2579 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2580 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2581 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2582 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2583 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2584 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2585 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2586 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2587 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2588 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2589 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2590 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2591
mbed_official 400:7fa56b1b9d45 2592 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 400:7fa56b1b9d45 2593 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2594 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2595 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2596 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2597 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2598 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2599 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2600 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2601 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2602 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2603 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2604 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2605 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2606 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2607 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2608 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2609 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2610 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2611 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2612 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2613 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2614 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2615 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2616 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2617 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2618 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2619 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2620 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2621 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2622 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2623 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2624 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2625
mbed_official 400:7fa56b1b9d45 2626 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 400:7fa56b1b9d45 2627 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2628 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2629 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2630 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2631 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2632 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2633 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2634 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2635 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2636 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2637 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2638 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2639 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2640 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2641 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2642 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2643 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2644 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2645 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2646 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2647 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2648 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2649 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2650 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2651 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2652 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2653 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2654 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2655 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2656 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2657 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2658 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2659
mbed_official 400:7fa56b1b9d45 2660 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 400:7fa56b1b9d45 2661 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2662 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2663 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2664 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2665 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2666 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2667 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2668 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2669 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2670 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2671 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2672 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2673 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2674 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2675 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2676 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2677 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2678 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2679 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2680 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2681 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2682 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2683 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2684 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2685 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2686 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2687 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2688 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2689 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2690 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2691 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2692 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2693
mbed_official 400:7fa56b1b9d45 2694 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 400:7fa56b1b9d45 2695 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2696 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2697 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2698 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2699 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2700 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2701 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2702 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2703 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2704 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2705 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2706 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2707 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2708 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2709 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2710 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2711 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2712 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2713 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2714 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2715 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2716 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2717 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2718 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2719 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2720 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2721 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2722 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2723 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2724 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2725 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2726 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2727
mbed_official 400:7fa56b1b9d45 2728 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 400:7fa56b1b9d45 2729 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 400:7fa56b1b9d45 2730 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 400:7fa56b1b9d45 2731 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 400:7fa56b1b9d45 2732 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 400:7fa56b1b9d45 2733 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 400:7fa56b1b9d45 2734 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 400:7fa56b1b9d45 2735 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 400:7fa56b1b9d45 2736 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 400:7fa56b1b9d45 2737 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 400:7fa56b1b9d45 2738 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 400:7fa56b1b9d45 2739 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 400:7fa56b1b9d45 2740 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 400:7fa56b1b9d45 2741 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 400:7fa56b1b9d45 2742 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 400:7fa56b1b9d45 2743 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 400:7fa56b1b9d45 2744 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 400:7fa56b1b9d45 2745 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 400:7fa56b1b9d45 2746 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 400:7fa56b1b9d45 2747 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 400:7fa56b1b9d45 2748 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 400:7fa56b1b9d45 2749 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 400:7fa56b1b9d45 2750 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 400:7fa56b1b9d45 2751 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 400:7fa56b1b9d45 2752 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 400:7fa56b1b9d45 2753 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 400:7fa56b1b9d45 2754 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 400:7fa56b1b9d45 2755 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 400:7fa56b1b9d45 2756 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 400:7fa56b1b9d45 2757 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 400:7fa56b1b9d45 2758 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 400:7fa56b1b9d45 2759 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 400:7fa56b1b9d45 2760 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 400:7fa56b1b9d45 2761
mbed_official 400:7fa56b1b9d45 2762 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 2763 /* */
mbed_official 400:7fa56b1b9d45 2764 /* CRC calculation unit */
mbed_official 400:7fa56b1b9d45 2765 /* */
mbed_official 400:7fa56b1b9d45 2766 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 2767 /******************* Bit definition for CRC_DR register *********************/
mbed_official 400:7fa56b1b9d45 2768 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 400:7fa56b1b9d45 2769
mbed_official 400:7fa56b1b9d45 2770
mbed_official 400:7fa56b1b9d45 2771 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 400:7fa56b1b9d45 2772 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 400:7fa56b1b9d45 2773
mbed_official 400:7fa56b1b9d45 2774
mbed_official 400:7fa56b1b9d45 2775 /******************** Bit definition for CRC_CR register ********************/
mbed_official 400:7fa56b1b9d45 2776 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
mbed_official 400:7fa56b1b9d45 2777
mbed_official 400:7fa56b1b9d45 2778
mbed_official 400:7fa56b1b9d45 2779 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 2780 /* */
mbed_official 400:7fa56b1b9d45 2781 /* Digital to Analog Converter */
mbed_official 400:7fa56b1b9d45 2782 /* */
mbed_official 400:7fa56b1b9d45 2783 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 2784 /******************** Bit definition for DAC_CR register ********************/
mbed_official 400:7fa56b1b9d45 2785 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
mbed_official 400:7fa56b1b9d45 2786 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
mbed_official 400:7fa56b1b9d45 2787 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
mbed_official 400:7fa56b1b9d45 2788
mbed_official 400:7fa56b1b9d45 2789 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 400:7fa56b1b9d45 2790 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 2791 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 2792 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 2793
mbed_official 400:7fa56b1b9d45 2794 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 400:7fa56b1b9d45 2795 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 2796 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 2797
mbed_official 400:7fa56b1b9d45 2798 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 400:7fa56b1b9d45 2799 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 2800 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 2801 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 2802 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 2803
mbed_official 400:7fa56b1b9d45 2804 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
mbed_official 400:7fa56b1b9d45 2805 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
mbed_official 400:7fa56b1b9d45 2806 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
mbed_official 400:7fa56b1b9d45 2807 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
mbed_official 400:7fa56b1b9d45 2808
mbed_official 400:7fa56b1b9d45 2809 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 400:7fa56b1b9d45 2810 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 2811 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 2812 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 2813
mbed_official 400:7fa56b1b9d45 2814 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 400:7fa56b1b9d45 2815 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 2816 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 2817
mbed_official 400:7fa56b1b9d45 2818 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 400:7fa56b1b9d45 2819 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 2820 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 2821 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 2822 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 2823
mbed_official 400:7fa56b1b9d45 2824 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
mbed_official 400:7fa56b1b9d45 2825
mbed_official 400:7fa56b1b9d45 2826 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 400:7fa56b1b9d45 2827 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
mbed_official 400:7fa56b1b9d45 2828 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
mbed_official 400:7fa56b1b9d45 2829
mbed_official 400:7fa56b1b9d45 2830 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 400:7fa56b1b9d45 2831 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 400:7fa56b1b9d45 2832
mbed_official 400:7fa56b1b9d45 2833 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 400:7fa56b1b9d45 2834 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 400:7fa56b1b9d45 2835
mbed_official 400:7fa56b1b9d45 2836 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 400:7fa56b1b9d45 2837 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 400:7fa56b1b9d45 2838
mbed_official 400:7fa56b1b9d45 2839 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 400:7fa56b1b9d45 2840 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 400:7fa56b1b9d45 2841
mbed_official 400:7fa56b1b9d45 2842 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 400:7fa56b1b9d45 2843 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 400:7fa56b1b9d45 2844
mbed_official 400:7fa56b1b9d45 2845 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 400:7fa56b1b9d45 2846 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 400:7fa56b1b9d45 2847
mbed_official 400:7fa56b1b9d45 2848 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 400:7fa56b1b9d45 2849 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 400:7fa56b1b9d45 2850 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 400:7fa56b1b9d45 2851
mbed_official 400:7fa56b1b9d45 2852 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 400:7fa56b1b9d45 2853 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 400:7fa56b1b9d45 2854 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 400:7fa56b1b9d45 2855
mbed_official 400:7fa56b1b9d45 2856 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 400:7fa56b1b9d45 2857 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 400:7fa56b1b9d45 2858 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 400:7fa56b1b9d45 2859
mbed_official 400:7fa56b1b9d45 2860 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 400:7fa56b1b9d45 2861 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
mbed_official 400:7fa56b1b9d45 2862
mbed_official 400:7fa56b1b9d45 2863 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 400:7fa56b1b9d45 2864 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
mbed_official 400:7fa56b1b9d45 2865
mbed_official 400:7fa56b1b9d45 2866 /******************** Bit definition for DAC_SR register ********************/
mbed_official 400:7fa56b1b9d45 2867 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
mbed_official 400:7fa56b1b9d45 2868 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
mbed_official 400:7fa56b1b9d45 2869
mbed_official 400:7fa56b1b9d45 2870 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 2871 /* */
mbed_official 400:7fa56b1b9d45 2872 /* Debug MCU */
mbed_official 400:7fa56b1b9d45 2873 /* */
mbed_official 400:7fa56b1b9d45 2874 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 2875
mbed_official 400:7fa56b1b9d45 2876 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 2877 /* */
mbed_official 400:7fa56b1b9d45 2878 /* DMA Controller */
mbed_official 400:7fa56b1b9d45 2879 /* */
mbed_official 400:7fa56b1b9d45 2880 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 2881 /******************** Bits definition for DMA_SxCR register *****************/
mbed_official 400:7fa56b1b9d45 2882 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
mbed_official 400:7fa56b1b9d45 2883 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 2884 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 2885 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 2886 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
mbed_official 400:7fa56b1b9d45 2887 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 2888 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 2889 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
mbed_official 400:7fa56b1b9d45 2890 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 2891 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 2892 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 2893 #define DMA_SxCR_CT ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 2894 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 2895 #define DMA_SxCR_PL ((uint32_t)0x00030000)
mbed_official 400:7fa56b1b9d45 2896 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 2897 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 2898 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 2899 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
mbed_official 400:7fa56b1b9d45 2900 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 2901 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 2902 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
mbed_official 400:7fa56b1b9d45 2903 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 2904 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 2905 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 2906 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 2907 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 2908 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
mbed_official 400:7fa56b1b9d45 2909 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 2910 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 2911 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 2912 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 2913 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 2914 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 2915 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 2916 #define DMA_SxCR_EN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 2917
mbed_official 400:7fa56b1b9d45 2918 /******************** Bits definition for DMA_SxCNDTR register **************/
mbed_official 400:7fa56b1b9d45 2919 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
mbed_official 400:7fa56b1b9d45 2920 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 2921 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 2922 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 2923 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 2924 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 2925 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 2926 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 2927 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 2928 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 2929 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 2930 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 2931 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 2932 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 2933 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 2934 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 2935 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 2936
mbed_official 400:7fa56b1b9d45 2937 /******************** Bits definition for DMA_SxFCR register ****************/
mbed_official 400:7fa56b1b9d45 2938 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 2939 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
mbed_official 400:7fa56b1b9d45 2940 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 2941 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 2942 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 2943 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 2944 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
mbed_official 400:7fa56b1b9d45 2945 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 2946 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 2947
mbed_official 400:7fa56b1b9d45 2948 /******************** Bits definition for DMA_LISR register *****************/
mbed_official 400:7fa56b1b9d45 2949 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 2950 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 2951 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 2952 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 2953 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 2954 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 2955 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 2956 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 2957 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 2958 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 2959 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 2960 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 2961 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 2962 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 2963 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 2964 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 2965 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 2966 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 2967 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 2968 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 2969
mbed_official 400:7fa56b1b9d45 2970 /******************** Bits definition for DMA_HISR register *****************/
mbed_official 400:7fa56b1b9d45 2971 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 2972 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 2973 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 2974 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 2975 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 2976 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 2977 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 2978 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 2979 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 2980 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 2981 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 2982 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 2983 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 2984 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 2985 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 2986 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 2987 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 2988 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 2989 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 2990 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 2991
mbed_official 400:7fa56b1b9d45 2992 /******************** Bits definition for DMA_LIFCR register ****************/
mbed_official 400:7fa56b1b9d45 2993 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 2994 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 2995 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 2996 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 2997 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 2998 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 2999 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 3000 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 3001 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 3002 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 3003 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 3004 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 3005 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 3006 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 3007 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 3008 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 3009 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 3010 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 3011 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 3012 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 3013
mbed_official 400:7fa56b1b9d45 3014 /******************** Bits definition for DMA_HIFCR register ****************/
mbed_official 400:7fa56b1b9d45 3015 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 3016 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 3017 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 3018 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 3019 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 3020 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 3021 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 3022 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 3023 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 3024 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 3025 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 3026 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 3027 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 3028 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 3029 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 3030 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 3031 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 3032 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 3033 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 3034 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 3035
mbed_official 400:7fa56b1b9d45 3036
mbed_official 400:7fa56b1b9d45 3037 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 3038 /* */
mbed_official 400:7fa56b1b9d45 3039 /* External Interrupt/Event Controller */
mbed_official 400:7fa56b1b9d45 3040 /* */
mbed_official 400:7fa56b1b9d45 3041 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 3042 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 400:7fa56b1b9d45 3043 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 400:7fa56b1b9d45 3044 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 400:7fa56b1b9d45 3045 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 400:7fa56b1b9d45 3046 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 400:7fa56b1b9d45 3047 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 400:7fa56b1b9d45 3048 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 400:7fa56b1b9d45 3049 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 400:7fa56b1b9d45 3050 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 400:7fa56b1b9d45 3051 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 400:7fa56b1b9d45 3052 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 400:7fa56b1b9d45 3053 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 400:7fa56b1b9d45 3054 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 400:7fa56b1b9d45 3055 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 400:7fa56b1b9d45 3056 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 400:7fa56b1b9d45 3057 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 400:7fa56b1b9d45 3058 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 400:7fa56b1b9d45 3059 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 400:7fa56b1b9d45 3060 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 400:7fa56b1b9d45 3061 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 400:7fa56b1b9d45 3062 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 532:fe11edbda85c 3063 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 532:fe11edbda85c 3064 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 532:fe11edbda85c 3065 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 400:7fa56b1b9d45 3066
mbed_official 400:7fa56b1b9d45 3067 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 400:7fa56b1b9d45 3068 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 400:7fa56b1b9d45 3069 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 400:7fa56b1b9d45 3070 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 400:7fa56b1b9d45 3071 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 400:7fa56b1b9d45 3072 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 400:7fa56b1b9d45 3073 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 400:7fa56b1b9d45 3074 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 400:7fa56b1b9d45 3075 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 400:7fa56b1b9d45 3076 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 400:7fa56b1b9d45 3077 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 400:7fa56b1b9d45 3078 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 400:7fa56b1b9d45 3079 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 400:7fa56b1b9d45 3080 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 400:7fa56b1b9d45 3081 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 400:7fa56b1b9d45 3082 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 400:7fa56b1b9d45 3083 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 400:7fa56b1b9d45 3084 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 400:7fa56b1b9d45 3085 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 400:7fa56b1b9d45 3086 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 400:7fa56b1b9d45 3087 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 532:fe11edbda85c 3088 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 532:fe11edbda85c 3089 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 532:fe11edbda85c 3090 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 400:7fa56b1b9d45 3091
mbed_official 400:7fa56b1b9d45 3092 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 400:7fa56b1b9d45 3093 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 400:7fa56b1b9d45 3094 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 400:7fa56b1b9d45 3095 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 400:7fa56b1b9d45 3096 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 400:7fa56b1b9d45 3097 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 400:7fa56b1b9d45 3098 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 400:7fa56b1b9d45 3099 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 400:7fa56b1b9d45 3100 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 400:7fa56b1b9d45 3101 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 400:7fa56b1b9d45 3102 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 400:7fa56b1b9d45 3103 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 400:7fa56b1b9d45 3104 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 400:7fa56b1b9d45 3105 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 400:7fa56b1b9d45 3106 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 400:7fa56b1b9d45 3107 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 400:7fa56b1b9d45 3108 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 400:7fa56b1b9d45 3109 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 400:7fa56b1b9d45 3110 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 400:7fa56b1b9d45 3111 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 400:7fa56b1b9d45 3112 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 532:fe11edbda85c 3113 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 532:fe11edbda85c 3114 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 532:fe11edbda85c 3115 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 400:7fa56b1b9d45 3116
mbed_official 400:7fa56b1b9d45 3117 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 400:7fa56b1b9d45 3118 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 400:7fa56b1b9d45 3119 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 400:7fa56b1b9d45 3120 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 400:7fa56b1b9d45 3121 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 400:7fa56b1b9d45 3122 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 400:7fa56b1b9d45 3123 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 400:7fa56b1b9d45 3124 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 400:7fa56b1b9d45 3125 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 400:7fa56b1b9d45 3126 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 400:7fa56b1b9d45 3127 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 400:7fa56b1b9d45 3128 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 400:7fa56b1b9d45 3129 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 400:7fa56b1b9d45 3130 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 400:7fa56b1b9d45 3131 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 400:7fa56b1b9d45 3132 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 400:7fa56b1b9d45 3133 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 400:7fa56b1b9d45 3134 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 400:7fa56b1b9d45 3135 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 400:7fa56b1b9d45 3136 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 400:7fa56b1b9d45 3137 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 532:fe11edbda85c 3138 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 532:fe11edbda85c 3139 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 532:fe11edbda85c 3140 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 400:7fa56b1b9d45 3141
mbed_official 400:7fa56b1b9d45 3142 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 400:7fa56b1b9d45 3143 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 400:7fa56b1b9d45 3144 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 400:7fa56b1b9d45 3145 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 400:7fa56b1b9d45 3146 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 400:7fa56b1b9d45 3147 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 400:7fa56b1b9d45 3148 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 400:7fa56b1b9d45 3149 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 400:7fa56b1b9d45 3150 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 400:7fa56b1b9d45 3151 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 400:7fa56b1b9d45 3152 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 400:7fa56b1b9d45 3153 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 400:7fa56b1b9d45 3154 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 400:7fa56b1b9d45 3155 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 400:7fa56b1b9d45 3156 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 400:7fa56b1b9d45 3157 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 400:7fa56b1b9d45 3158 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 400:7fa56b1b9d45 3159 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 400:7fa56b1b9d45 3160 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 400:7fa56b1b9d45 3161 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 400:7fa56b1b9d45 3162 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 532:fe11edbda85c 3163 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 532:fe11edbda85c 3164 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 532:fe11edbda85c 3165 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 400:7fa56b1b9d45 3166
mbed_official 400:7fa56b1b9d45 3167 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 400:7fa56b1b9d45 3168 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 400:7fa56b1b9d45 3169 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 400:7fa56b1b9d45 3170 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 400:7fa56b1b9d45 3171 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 400:7fa56b1b9d45 3172 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 400:7fa56b1b9d45 3173 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 400:7fa56b1b9d45 3174 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 400:7fa56b1b9d45 3175 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 400:7fa56b1b9d45 3176 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 400:7fa56b1b9d45 3177 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 400:7fa56b1b9d45 3178 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 400:7fa56b1b9d45 3179 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 400:7fa56b1b9d45 3180 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 400:7fa56b1b9d45 3181 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 400:7fa56b1b9d45 3182 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 400:7fa56b1b9d45 3183 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 400:7fa56b1b9d45 3184 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 400:7fa56b1b9d45 3185 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 400:7fa56b1b9d45 3186 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 400:7fa56b1b9d45 3187 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 532:fe11edbda85c 3188 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 532:fe11edbda85c 3189 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 532:fe11edbda85c 3190 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 400:7fa56b1b9d45 3191
mbed_official 400:7fa56b1b9d45 3192 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 3193 /* */
mbed_official 400:7fa56b1b9d45 3194 /* FLASH */
mbed_official 400:7fa56b1b9d45 3195 /* */
mbed_official 400:7fa56b1b9d45 3196 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 3197 /******************* Bits definition for FLASH_ACR register *****************/
mbed_official 400:7fa56b1b9d45 3198 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
mbed_official 400:7fa56b1b9d45 3199 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
mbed_official 400:7fa56b1b9d45 3200 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 3201 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 3202 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
mbed_official 400:7fa56b1b9d45 3203 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 3204 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
mbed_official 400:7fa56b1b9d45 3205 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
mbed_official 400:7fa56b1b9d45 3206 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
mbed_official 400:7fa56b1b9d45 3207
mbed_official 400:7fa56b1b9d45 3208 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 3209 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 3210 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 3211 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 3212 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 3213 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
mbed_official 400:7fa56b1b9d45 3214 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
mbed_official 400:7fa56b1b9d45 3215
mbed_official 400:7fa56b1b9d45 3216 /******************* Bits definition for FLASH_SR register ******************/
mbed_official 400:7fa56b1b9d45 3217 #define FLASH_SR_EOP ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 3218 #define FLASH_SR_SOP ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 3219 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 3220 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 3221 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 3222 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 3223 #define FLASH_SR_BSY ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 3224
mbed_official 400:7fa56b1b9d45 3225 /******************* Bits definition for FLASH_CR register ******************/
mbed_official 400:7fa56b1b9d45 3226 #define FLASH_CR_PG ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 3227 #define FLASH_CR_SER ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 3228 #define FLASH_CR_MER ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 3229 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
mbed_official 400:7fa56b1b9d45 3230 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 3231 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 3232 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 3233 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 3234 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 3235 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
mbed_official 400:7fa56b1b9d45 3236 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 3237 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 3238 #define FLASH_CR_STRT ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 3239 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 3240 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 3241
mbed_official 400:7fa56b1b9d45 3242 /******************* Bits definition for FLASH_OPTCR register ***************/
mbed_official 400:7fa56b1b9d45 3243 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 3244 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 3245 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 3246 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 3247 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
mbed_official 400:7fa56b1b9d45 3248
mbed_official 400:7fa56b1b9d45 3249 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 3250 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 3251 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 3252 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
mbed_official 400:7fa56b1b9d45 3253 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 3254 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 3255 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 3256 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 3257 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 3258 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 3259 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 3260 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 3261 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
mbed_official 400:7fa56b1b9d45 3262 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 3263 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 3264 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 3265 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 3266 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 3267 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 3268 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 3269 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 3270 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 3271 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 3272 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 3273 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 3274
mbed_official 400:7fa56b1b9d45 3275 /****************** Bits definition for FLASH_OPTCR1 register ***************/
mbed_official 400:7fa56b1b9d45 3276 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
mbed_official 400:7fa56b1b9d45 3277 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 3278 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 3279 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 3280 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 3281 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 3282 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 3283 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 3284 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 3285 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 3286 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 3287 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 3288 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 3289
mbed_official 400:7fa56b1b9d45 3290 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 3291 /* */
mbed_official 400:7fa56b1b9d45 3292 /* Flexible Static Memory Controller */
mbed_official 400:7fa56b1b9d45 3293 /* */
mbed_official 400:7fa56b1b9d45 3294 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 3295 /****************** Bit definition for FSMC_BCR1 register *******************/
mbed_official 400:7fa56b1b9d45 3296 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 400:7fa56b1b9d45 3297 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 400:7fa56b1b9d45 3298
mbed_official 400:7fa56b1b9d45 3299 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 400:7fa56b1b9d45 3300 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3301 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3302
mbed_official 400:7fa56b1b9d45 3303 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 400:7fa56b1b9d45 3304 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3305 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3306
mbed_official 400:7fa56b1b9d45 3307 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 400:7fa56b1b9d45 3308 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 400:7fa56b1b9d45 3309 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 400:7fa56b1b9d45 3310 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 400:7fa56b1b9d45 3311 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 400:7fa56b1b9d45 3312 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 400:7fa56b1b9d45 3313 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 400:7fa56b1b9d45 3314 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 400:7fa56b1b9d45 3315 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 400:7fa56b1b9d45 3316 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 400:7fa56b1b9d45 3317
mbed_official 400:7fa56b1b9d45 3318 /****************** Bit definition for FSMC_BCR2 register *******************/
mbed_official 400:7fa56b1b9d45 3319 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 400:7fa56b1b9d45 3320 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 400:7fa56b1b9d45 3321
mbed_official 400:7fa56b1b9d45 3322 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 400:7fa56b1b9d45 3323 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3324 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3325
mbed_official 400:7fa56b1b9d45 3326 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 400:7fa56b1b9d45 3327 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3328 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3329
mbed_official 400:7fa56b1b9d45 3330 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 400:7fa56b1b9d45 3331 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 400:7fa56b1b9d45 3332 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 400:7fa56b1b9d45 3333 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 400:7fa56b1b9d45 3334 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 400:7fa56b1b9d45 3335 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 400:7fa56b1b9d45 3336 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 400:7fa56b1b9d45 3337 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 400:7fa56b1b9d45 3338 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 400:7fa56b1b9d45 3339 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 400:7fa56b1b9d45 3340
mbed_official 400:7fa56b1b9d45 3341 /****************** Bit definition for FSMC_BCR3 register *******************/
mbed_official 400:7fa56b1b9d45 3342 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 400:7fa56b1b9d45 3343 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 400:7fa56b1b9d45 3344
mbed_official 400:7fa56b1b9d45 3345 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 400:7fa56b1b9d45 3346 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3347 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3348
mbed_official 400:7fa56b1b9d45 3349 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 400:7fa56b1b9d45 3350 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3351 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3352
mbed_official 400:7fa56b1b9d45 3353 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 400:7fa56b1b9d45 3354 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 400:7fa56b1b9d45 3355 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 400:7fa56b1b9d45 3356 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 400:7fa56b1b9d45 3357 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 400:7fa56b1b9d45 3358 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 400:7fa56b1b9d45 3359 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 400:7fa56b1b9d45 3360 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 400:7fa56b1b9d45 3361 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 400:7fa56b1b9d45 3362 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 400:7fa56b1b9d45 3363
mbed_official 400:7fa56b1b9d45 3364 /****************** Bit definition for FSMC_BCR4 register *******************/
mbed_official 400:7fa56b1b9d45 3365 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 400:7fa56b1b9d45 3366 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 400:7fa56b1b9d45 3367
mbed_official 400:7fa56b1b9d45 3368 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 400:7fa56b1b9d45 3369 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3370 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3371
mbed_official 400:7fa56b1b9d45 3372 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 400:7fa56b1b9d45 3373 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3374 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3375
mbed_official 400:7fa56b1b9d45 3376 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 400:7fa56b1b9d45 3377 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 400:7fa56b1b9d45 3378 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 400:7fa56b1b9d45 3379 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 400:7fa56b1b9d45 3380 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 400:7fa56b1b9d45 3381 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 400:7fa56b1b9d45 3382 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 400:7fa56b1b9d45 3383 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 400:7fa56b1b9d45 3384 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 400:7fa56b1b9d45 3385 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 400:7fa56b1b9d45 3386
mbed_official 400:7fa56b1b9d45 3387 /****************** Bit definition for FSMC_BTR1 register ******************/
mbed_official 400:7fa56b1b9d45 3388 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 400:7fa56b1b9d45 3389 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3390 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3391 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3392 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3393
mbed_official 400:7fa56b1b9d45 3394 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 400:7fa56b1b9d45 3395 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3396 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3397 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3398 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3399
mbed_official 613:bc40b8d2aec4 3400 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 400:7fa56b1b9d45 3401 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3402 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3403 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3404 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3405 #define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3406 #define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3407 #define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3408 #define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3409
mbed_official 400:7fa56b1b9d45 3410 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 400:7fa56b1b9d45 3411 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3412 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3413 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3414 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3415
mbed_official 400:7fa56b1b9d45 3416 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 400:7fa56b1b9d45 3417 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3418 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3419 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3420 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3421
mbed_official 400:7fa56b1b9d45 3422 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 400:7fa56b1b9d45 3423 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3424 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3425 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3426 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3427
mbed_official 400:7fa56b1b9d45 3428 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 400:7fa56b1b9d45 3429 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3430 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3431
mbed_official 400:7fa56b1b9d45 3432 /****************** Bit definition for FSMC_BTR2 register *******************/
mbed_official 400:7fa56b1b9d45 3433 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 400:7fa56b1b9d45 3434 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3435 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3436 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3437 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3438
mbed_official 400:7fa56b1b9d45 3439 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 400:7fa56b1b9d45 3440 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3441 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3442 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3443 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3444
mbed_official 613:bc40b8d2aec4 3445 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 400:7fa56b1b9d45 3446 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3447 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3448 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3449 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3450 #define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3451 #define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3452 #define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3453 #define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3454
mbed_official 400:7fa56b1b9d45 3455 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 400:7fa56b1b9d45 3456 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3457 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3458 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3459 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3460
mbed_official 400:7fa56b1b9d45 3461 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 400:7fa56b1b9d45 3462 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3463 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3464 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3465 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3466
mbed_official 400:7fa56b1b9d45 3467 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 400:7fa56b1b9d45 3468 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3469 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3470 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3471 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3472
mbed_official 400:7fa56b1b9d45 3473 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 400:7fa56b1b9d45 3474 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3475 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3476
mbed_official 400:7fa56b1b9d45 3477 /******************* Bit definition for FSMC_BTR3 register *******************/
mbed_official 400:7fa56b1b9d45 3478 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 400:7fa56b1b9d45 3479 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3480 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3481 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3482 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3483
mbed_official 400:7fa56b1b9d45 3484 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 400:7fa56b1b9d45 3485 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3486 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3487 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3488 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3489
mbed_official 613:bc40b8d2aec4 3490 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 400:7fa56b1b9d45 3491 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3492 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3493 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3494 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3495 #define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3496 #define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3497 #define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3498 #define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3499
mbed_official 400:7fa56b1b9d45 3500 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 400:7fa56b1b9d45 3501 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3502 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3503 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3504 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3505
mbed_official 400:7fa56b1b9d45 3506 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 400:7fa56b1b9d45 3507 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3508 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3509 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3510 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3511
mbed_official 400:7fa56b1b9d45 3512 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 400:7fa56b1b9d45 3513 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3514 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3515 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3516 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3517
mbed_official 400:7fa56b1b9d45 3518 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 400:7fa56b1b9d45 3519 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3520 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3521
mbed_official 400:7fa56b1b9d45 3522 /****************** Bit definition for FSMC_BTR4 register *******************/
mbed_official 400:7fa56b1b9d45 3523 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 400:7fa56b1b9d45 3524 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3525 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3526 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3527 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3528
mbed_official 400:7fa56b1b9d45 3529 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 400:7fa56b1b9d45 3530 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3531 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3532 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3533 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3534
mbed_official 613:bc40b8d2aec4 3535 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 400:7fa56b1b9d45 3536 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3537 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3538 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3539 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3540 #define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3541 #define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3542 #define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3543 #define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3544
mbed_official 400:7fa56b1b9d45 3545 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 400:7fa56b1b9d45 3546 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3547 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3548 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3549 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3550
mbed_official 400:7fa56b1b9d45 3551 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 400:7fa56b1b9d45 3552 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3553 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3554 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3555 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3556
mbed_official 400:7fa56b1b9d45 3557 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 400:7fa56b1b9d45 3558 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3559 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3560 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3561 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3562
mbed_official 400:7fa56b1b9d45 3563 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 400:7fa56b1b9d45 3564 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3565 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3566
mbed_official 400:7fa56b1b9d45 3567 /****************** Bit definition for FSMC_BWTR1 register ******************/
mbed_official 400:7fa56b1b9d45 3568 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 400:7fa56b1b9d45 3569 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3570 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3571 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3572 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3573
mbed_official 400:7fa56b1b9d45 3574 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 400:7fa56b1b9d45 3575 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3576 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3577 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3578 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3579
mbed_official 613:bc40b8d2aec4 3580 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 400:7fa56b1b9d45 3581 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3582 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3583 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3584 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3585 #define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3586 #define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3587 #define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3588 #define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3589
mbed_official 532:fe11edbda85c 3590 #define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 532:fe11edbda85c 3591 #define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 532:fe11edbda85c 3592 #define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 532:fe11edbda85c 3593 #define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 532:fe11edbda85c 3594 #define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 532:fe11edbda85c 3595
mbed_official 400:7fa56b1b9d45 3596 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 400:7fa56b1b9d45 3597 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3598 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3599 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3600 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3601
mbed_official 400:7fa56b1b9d45 3602 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 400:7fa56b1b9d45 3603 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3604 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3605 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3606 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3607
mbed_official 400:7fa56b1b9d45 3608 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 400:7fa56b1b9d45 3609 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3610 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3611
mbed_official 400:7fa56b1b9d45 3612 /****************** Bit definition for FSMC_BWTR2 register ******************/
mbed_official 400:7fa56b1b9d45 3613 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 400:7fa56b1b9d45 3614 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3615 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3616 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3617 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3618
mbed_official 400:7fa56b1b9d45 3619 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 400:7fa56b1b9d45 3620 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3621 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3622 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3623 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3624
mbed_official 613:bc40b8d2aec4 3625 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 400:7fa56b1b9d45 3626 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3627 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3628 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3629 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3630 #define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3631 #define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3632 #define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3633 #define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3634
mbed_official 532:fe11edbda85c 3635 #define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 532:fe11edbda85c 3636 #define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 532:fe11edbda85c 3637 #define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 532:fe11edbda85c 3638 #define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 532:fe11edbda85c 3639 #define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 532:fe11edbda85c 3640
mbed_official 400:7fa56b1b9d45 3641 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 400:7fa56b1b9d45 3642 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3643 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
mbed_official 400:7fa56b1b9d45 3644 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3645 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3646
mbed_official 400:7fa56b1b9d45 3647 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 400:7fa56b1b9d45 3648 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3649 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3650 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3651 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3652
mbed_official 400:7fa56b1b9d45 3653 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 400:7fa56b1b9d45 3654 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3655 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3656
mbed_official 400:7fa56b1b9d45 3657 /****************** Bit definition for FSMC_BWTR3 register ******************/
mbed_official 400:7fa56b1b9d45 3658 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 400:7fa56b1b9d45 3659 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3660 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3661 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3662 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3663
mbed_official 400:7fa56b1b9d45 3664 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 400:7fa56b1b9d45 3665 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3666 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3667 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3668 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3669
mbed_official 613:bc40b8d2aec4 3670 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 400:7fa56b1b9d45 3671 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3672 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3673 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3674 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3675 #define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3676 #define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3677 #define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3678 #define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3679
mbed_official 532:fe11edbda85c 3680 #define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 532:fe11edbda85c 3681 #define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 532:fe11edbda85c 3682 #define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 532:fe11edbda85c 3683 #define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 532:fe11edbda85c 3684 #define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 532:fe11edbda85c 3685
mbed_official 400:7fa56b1b9d45 3686 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 400:7fa56b1b9d45 3687 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3688 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3689 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3690 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3691
mbed_official 400:7fa56b1b9d45 3692 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 400:7fa56b1b9d45 3693 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3694 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3695 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3696 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3697
mbed_official 400:7fa56b1b9d45 3698 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 400:7fa56b1b9d45 3699 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3700 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3701
mbed_official 400:7fa56b1b9d45 3702 /****************** Bit definition for FSMC_BWTR4 register ******************/
mbed_official 400:7fa56b1b9d45 3703 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 400:7fa56b1b9d45 3704 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3705 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3706 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3707 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3708
mbed_official 400:7fa56b1b9d45 3709 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 400:7fa56b1b9d45 3710 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3711 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3712 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3713 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3714
mbed_official 400:7fa56b1b9d45 3715 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 400:7fa56b1b9d45 3716 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3717 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3718 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3719 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3720 #define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3721 #define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3722 #define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3723 #define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3724
mbed_official 532:fe11edbda85c 3725 #define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 532:fe11edbda85c 3726 #define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 532:fe11edbda85c 3727 #define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 532:fe11edbda85c 3728 #define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 532:fe11edbda85c 3729 #define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 532:fe11edbda85c 3730
mbed_official 400:7fa56b1b9d45 3731 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 400:7fa56b1b9d45 3732 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3733 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3734 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3735 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3736
mbed_official 400:7fa56b1b9d45 3737 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 400:7fa56b1b9d45 3738 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3739 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3740 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3741 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3742
mbed_official 400:7fa56b1b9d45 3743 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 400:7fa56b1b9d45 3744 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3745 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3746
mbed_official 400:7fa56b1b9d45 3747 /****************** Bit definition for FSMC_PCR2 register *******************/
mbed_official 400:7fa56b1b9d45 3748 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 400:7fa56b1b9d45 3749 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 400:7fa56b1b9d45 3750 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 400:7fa56b1b9d45 3751
mbed_official 400:7fa56b1b9d45 3752 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 400:7fa56b1b9d45 3753 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3754 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3755
mbed_official 400:7fa56b1b9d45 3756 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 400:7fa56b1b9d45 3757
mbed_official 400:7fa56b1b9d45 3758 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 400:7fa56b1b9d45 3759 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3760 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3761 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3762 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3763
mbed_official 400:7fa56b1b9d45 3764 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 400:7fa56b1b9d45 3765 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3766 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3767 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3768 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3769
mbed_official 400:7fa56b1b9d45 3770 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
mbed_official 400:7fa56b1b9d45 3771 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3772 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3773 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3774
mbed_official 400:7fa56b1b9d45 3775 /****************** Bit definition for FSMC_PCR3 register *******************/
mbed_official 400:7fa56b1b9d45 3776 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 400:7fa56b1b9d45 3777 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 400:7fa56b1b9d45 3778 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 400:7fa56b1b9d45 3779
mbed_official 400:7fa56b1b9d45 3780 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 400:7fa56b1b9d45 3781 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3782 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3783
mbed_official 400:7fa56b1b9d45 3784 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 400:7fa56b1b9d45 3785
mbed_official 400:7fa56b1b9d45 3786 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 400:7fa56b1b9d45 3787 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3788 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3789 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3790 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3791
mbed_official 400:7fa56b1b9d45 3792 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 400:7fa56b1b9d45 3793 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3794 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3795 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3796 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3797
mbed_official 400:7fa56b1b9d45 3798 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 400:7fa56b1b9d45 3799 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3800 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3801 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3802
mbed_official 400:7fa56b1b9d45 3803 /****************** Bit definition for FSMC_PCR4 register *******************/
mbed_official 400:7fa56b1b9d45 3804 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 400:7fa56b1b9d45 3805 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 400:7fa56b1b9d45 3806 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 400:7fa56b1b9d45 3807
mbed_official 400:7fa56b1b9d45 3808 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 400:7fa56b1b9d45 3809 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3810 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3811
mbed_official 400:7fa56b1b9d45 3812 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 400:7fa56b1b9d45 3813
mbed_official 400:7fa56b1b9d45 3814 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 400:7fa56b1b9d45 3815 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3816 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3817 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3818 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3819
mbed_official 400:7fa56b1b9d45 3820 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 400:7fa56b1b9d45 3821 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3822 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3823 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3824 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3825
mbed_official 400:7fa56b1b9d45 3826 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 400:7fa56b1b9d45 3827 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3828 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3829 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3830
mbed_official 400:7fa56b1b9d45 3831 /******************* Bit definition for FSMC_SR2 register *******************/
mbed_official 400:7fa56b1b9d45 3832 #define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 400:7fa56b1b9d45 3833 #define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 400:7fa56b1b9d45 3834 #define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 400:7fa56b1b9d45 3835 #define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 400:7fa56b1b9d45 3836 #define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 400:7fa56b1b9d45 3837 #define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 400:7fa56b1b9d45 3838 #define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 400:7fa56b1b9d45 3839
mbed_official 400:7fa56b1b9d45 3840 /******************* Bit definition for FSMC_SR3 register *******************/
mbed_official 400:7fa56b1b9d45 3841 #define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 400:7fa56b1b9d45 3842 #define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 400:7fa56b1b9d45 3843 #define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 400:7fa56b1b9d45 3844 #define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 400:7fa56b1b9d45 3845 #define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 400:7fa56b1b9d45 3846 #define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 400:7fa56b1b9d45 3847 #define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 400:7fa56b1b9d45 3848
mbed_official 400:7fa56b1b9d45 3849 /******************* Bit definition for FSMC_SR4 register *******************/
mbed_official 400:7fa56b1b9d45 3850 #define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 400:7fa56b1b9d45 3851 #define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 400:7fa56b1b9d45 3852 #define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 400:7fa56b1b9d45 3853 #define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 400:7fa56b1b9d45 3854 #define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 400:7fa56b1b9d45 3855 #define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 400:7fa56b1b9d45 3856 #define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 400:7fa56b1b9d45 3857
mbed_official 400:7fa56b1b9d45 3858 /****************** Bit definition for FSMC_PMEM2 register ******************/
mbed_official 400:7fa56b1b9d45 3859 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
mbed_official 400:7fa56b1b9d45 3860 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3861 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3862 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3863 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3864 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3865 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3866 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3867 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3868
mbed_official 400:7fa56b1b9d45 3869 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
mbed_official 400:7fa56b1b9d45 3870 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3871 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3872 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3873 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3874 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3875 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3876 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3877 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3878
mbed_official 400:7fa56b1b9d45 3879 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
mbed_official 400:7fa56b1b9d45 3880 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3881 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3882 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3883 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3884 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3885 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3886 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3887 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3888
mbed_official 400:7fa56b1b9d45 3889 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
mbed_official 400:7fa56b1b9d45 3890 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3891 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3892 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3893 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3894 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3895 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3896 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3897 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3898
mbed_official 400:7fa56b1b9d45 3899 /****************** Bit definition for FSMC_PMEM3 register ******************/
mbed_official 400:7fa56b1b9d45 3900 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
mbed_official 400:7fa56b1b9d45 3901 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3902 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3903 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3904 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3905 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3906 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3907 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3908 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3909
mbed_official 400:7fa56b1b9d45 3910 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
mbed_official 400:7fa56b1b9d45 3911 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3912 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3913 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3914 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3915 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3916 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3917 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3918 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3919
mbed_official 400:7fa56b1b9d45 3920 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
mbed_official 400:7fa56b1b9d45 3921 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3922 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3923 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3924 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3925 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3926 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3927 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3928 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3929
mbed_official 400:7fa56b1b9d45 3930 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
mbed_official 400:7fa56b1b9d45 3931 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3932 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3933 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3934 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3935 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3936 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3937 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3938 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3939
mbed_official 400:7fa56b1b9d45 3940 /****************** Bit definition for FSMC_PMEM4 register ******************/
mbed_official 400:7fa56b1b9d45 3941 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
mbed_official 400:7fa56b1b9d45 3942 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3943 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3944 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3945 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3946 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3947 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3948 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3949 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3950
mbed_official 400:7fa56b1b9d45 3951 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
mbed_official 400:7fa56b1b9d45 3952 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3953 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3954 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3955 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3956 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3957 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3958 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3959 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3960
mbed_official 400:7fa56b1b9d45 3961 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
mbed_official 400:7fa56b1b9d45 3962 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3963 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3964 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3965 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3966 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3967 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3968 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3969 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3970
mbed_official 400:7fa56b1b9d45 3971 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
mbed_official 400:7fa56b1b9d45 3972 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3973 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3974 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3975 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3976 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3977 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3978 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3979 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3980
mbed_official 400:7fa56b1b9d45 3981 /****************** Bit definition for FSMC_PATT2 register ******************/
mbed_official 400:7fa56b1b9d45 3982 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
mbed_official 400:7fa56b1b9d45 3983 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3984 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3985 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3986 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3987 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3988 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3989 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 3990 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 3991
mbed_official 400:7fa56b1b9d45 3992 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
mbed_official 400:7fa56b1b9d45 3993 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 3994 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 3995 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 3996 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 3997 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 3998 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 3999 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4000 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4001
mbed_official 400:7fa56b1b9d45 4002 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
mbed_official 400:7fa56b1b9d45 4003 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4004 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4005 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4006 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4007 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4008 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4009 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4010 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4011
mbed_official 400:7fa56b1b9d45 4012 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
mbed_official 400:7fa56b1b9d45 4013 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4014 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4015 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4016 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4017 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4018 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4019 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4020 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4021
mbed_official 400:7fa56b1b9d45 4022 /****************** Bit definition for FSMC_PATT3 register ******************/
mbed_official 400:7fa56b1b9d45 4023 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
mbed_official 400:7fa56b1b9d45 4024 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4025 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4026 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4027 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4028 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4029 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4030 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4031 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4032
mbed_official 400:7fa56b1b9d45 4033 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
mbed_official 400:7fa56b1b9d45 4034 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4035 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4036 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4037 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4038 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4039 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4040 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4041 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4042
mbed_official 400:7fa56b1b9d45 4043 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
mbed_official 400:7fa56b1b9d45 4044 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4045 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4046 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4047 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4048 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4049 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4050 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4051 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4052
mbed_official 400:7fa56b1b9d45 4053 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
mbed_official 400:7fa56b1b9d45 4054 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4055 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4056 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4057 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4058 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4059 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4060 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4061 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4062
mbed_official 400:7fa56b1b9d45 4063 /****************** Bit definition for FSMC_PATT4 register ******************/
mbed_official 400:7fa56b1b9d45 4064 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
mbed_official 400:7fa56b1b9d45 4065 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4066 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4067 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4068 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4069 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4070 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4071 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4072 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4073
mbed_official 400:7fa56b1b9d45 4074 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
mbed_official 400:7fa56b1b9d45 4075 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4076 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4077 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4078 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4079 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4080 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4081 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4082 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4083
mbed_official 400:7fa56b1b9d45 4084 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
mbed_official 400:7fa56b1b9d45 4085 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4086 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4087 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4088 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4089 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4090 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4091 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4092 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4093
mbed_official 400:7fa56b1b9d45 4094 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
mbed_official 400:7fa56b1b9d45 4095 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4096 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4097 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4098 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4099 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4100 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4101 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4102 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4103
mbed_official 400:7fa56b1b9d45 4104 /****************** Bit definition for FSMC_PIO4 register *******************/
mbed_official 400:7fa56b1b9d45 4105 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
mbed_official 400:7fa56b1b9d45 4106 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4107 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4108 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4109 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4110 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4111 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4112 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4113 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4114
mbed_official 400:7fa56b1b9d45 4115 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
mbed_official 400:7fa56b1b9d45 4116 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4117 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4118 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4119 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4120 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4121 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4122 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4123 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4124
mbed_official 400:7fa56b1b9d45 4125 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
mbed_official 400:7fa56b1b9d45 4126 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4127 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4128 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4129 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4130 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4131 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4132 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4133 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4134
mbed_official 400:7fa56b1b9d45 4135 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
mbed_official 400:7fa56b1b9d45 4136 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4137 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4138 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4139 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4140 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4141 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4142 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4143 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4144
mbed_official 400:7fa56b1b9d45 4145 /****************** Bit definition for FSMC_ECCR2 register ******************/
mbed_official 400:7fa56b1b9d45 4146 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 400:7fa56b1b9d45 4147
mbed_official 400:7fa56b1b9d45 4148 /****************** Bit definition for FSMC_ECCR3 register ******************/
mbed_official 400:7fa56b1b9d45 4149 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 400:7fa56b1b9d45 4150
mbed_official 400:7fa56b1b9d45 4151 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4152 /* */
mbed_official 400:7fa56b1b9d45 4153 /* General Purpose I/O */
mbed_official 400:7fa56b1b9d45 4154 /* */
mbed_official 400:7fa56b1b9d45 4155 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4156 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 400:7fa56b1b9d45 4157 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 400:7fa56b1b9d45 4158 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4159 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4160
mbed_official 400:7fa56b1b9d45 4161 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 400:7fa56b1b9d45 4162 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4163 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4164
mbed_official 400:7fa56b1b9d45 4165 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 400:7fa56b1b9d45 4166 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4167 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4168
mbed_official 400:7fa56b1b9d45 4169 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 400:7fa56b1b9d45 4170 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4171 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4172
mbed_official 400:7fa56b1b9d45 4173 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 400:7fa56b1b9d45 4174 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4175 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4176
mbed_official 400:7fa56b1b9d45 4177 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 400:7fa56b1b9d45 4178 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4179 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4180
mbed_official 400:7fa56b1b9d45 4181 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 400:7fa56b1b9d45 4182 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4183 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4184
mbed_official 400:7fa56b1b9d45 4185 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 400:7fa56b1b9d45 4186 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4187 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4188
mbed_official 400:7fa56b1b9d45 4189 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 400:7fa56b1b9d45 4190 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4191 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4192
mbed_official 400:7fa56b1b9d45 4193 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 400:7fa56b1b9d45 4194 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4195 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4196
mbed_official 400:7fa56b1b9d45 4197 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 400:7fa56b1b9d45 4198 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4199 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4200
mbed_official 400:7fa56b1b9d45 4201 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 400:7fa56b1b9d45 4202 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4203 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 4204
mbed_official 400:7fa56b1b9d45 4205 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 400:7fa56b1b9d45 4206 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 4207 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4208
mbed_official 400:7fa56b1b9d45 4209 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 400:7fa56b1b9d45 4210 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4211 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 4212
mbed_official 400:7fa56b1b9d45 4213 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 400:7fa56b1b9d45 4214 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 4215 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4216
mbed_official 400:7fa56b1b9d45 4217 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 400:7fa56b1b9d45 4218 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 4219 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 4220
mbed_official 400:7fa56b1b9d45 4221 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 400:7fa56b1b9d45 4222 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4223 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4224 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4225 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4226 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4227 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4228 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4229 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4230 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4231 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4232 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4233 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4234 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4235 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4236 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4237 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4238
mbed_official 400:7fa56b1b9d45 4239 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 400:7fa56b1b9d45 4240 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 400:7fa56b1b9d45 4241 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4242 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4243
mbed_official 400:7fa56b1b9d45 4244 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 400:7fa56b1b9d45 4245 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4246 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4247
mbed_official 400:7fa56b1b9d45 4248 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 400:7fa56b1b9d45 4249 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4250 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4251
mbed_official 400:7fa56b1b9d45 4252 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 400:7fa56b1b9d45 4253 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4254 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4255
mbed_official 400:7fa56b1b9d45 4256 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 400:7fa56b1b9d45 4257 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4258 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4259
mbed_official 400:7fa56b1b9d45 4260 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 400:7fa56b1b9d45 4261 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4262 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4263
mbed_official 400:7fa56b1b9d45 4264 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 400:7fa56b1b9d45 4265 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4266 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4267
mbed_official 400:7fa56b1b9d45 4268 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 400:7fa56b1b9d45 4269 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4270 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4271
mbed_official 400:7fa56b1b9d45 4272 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 400:7fa56b1b9d45 4273 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4274 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4275
mbed_official 400:7fa56b1b9d45 4276 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 400:7fa56b1b9d45 4277 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4278 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4279
mbed_official 400:7fa56b1b9d45 4280 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 400:7fa56b1b9d45 4281 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4282 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4283
mbed_official 400:7fa56b1b9d45 4284 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 400:7fa56b1b9d45 4285 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4286 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 4287
mbed_official 400:7fa56b1b9d45 4288 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 400:7fa56b1b9d45 4289 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 4290 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4291
mbed_official 400:7fa56b1b9d45 4292 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 400:7fa56b1b9d45 4293 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4294 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 4295
mbed_official 400:7fa56b1b9d45 4296 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 400:7fa56b1b9d45 4297 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 4298 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4299
mbed_official 400:7fa56b1b9d45 4300 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 400:7fa56b1b9d45 4301 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 4302 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 4303
mbed_official 400:7fa56b1b9d45 4304 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 400:7fa56b1b9d45 4305 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 400:7fa56b1b9d45 4306 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4307 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4308
mbed_official 400:7fa56b1b9d45 4309 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 400:7fa56b1b9d45 4310 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4311 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4312
mbed_official 400:7fa56b1b9d45 4313 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 400:7fa56b1b9d45 4314 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4315 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4316
mbed_official 400:7fa56b1b9d45 4317 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 400:7fa56b1b9d45 4318 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4319 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4320
mbed_official 400:7fa56b1b9d45 4321 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 400:7fa56b1b9d45 4322 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4323 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4324
mbed_official 400:7fa56b1b9d45 4325 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 400:7fa56b1b9d45 4326 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4327 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4328
mbed_official 400:7fa56b1b9d45 4329 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 400:7fa56b1b9d45 4330 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4331 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4332
mbed_official 400:7fa56b1b9d45 4333 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 400:7fa56b1b9d45 4334 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4335 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4336
mbed_official 400:7fa56b1b9d45 4337 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 400:7fa56b1b9d45 4338 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4339 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4340
mbed_official 400:7fa56b1b9d45 4341 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 400:7fa56b1b9d45 4342 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4343 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4344
mbed_official 400:7fa56b1b9d45 4345 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 400:7fa56b1b9d45 4346 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4347 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4348
mbed_official 400:7fa56b1b9d45 4349 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 400:7fa56b1b9d45 4350 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4351 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 4352
mbed_official 400:7fa56b1b9d45 4353 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 400:7fa56b1b9d45 4354 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 4355 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4356
mbed_official 400:7fa56b1b9d45 4357 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 400:7fa56b1b9d45 4358 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4359 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 4360
mbed_official 400:7fa56b1b9d45 4361 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 400:7fa56b1b9d45 4362 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 4363 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4364
mbed_official 400:7fa56b1b9d45 4365 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 400:7fa56b1b9d45 4366 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 4367 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 4368
mbed_official 400:7fa56b1b9d45 4369 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 400:7fa56b1b9d45 4370 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4371 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4372 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4373 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4374 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4375 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4376 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4377 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4378 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4379 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4380 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4381 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4382 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4383 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4384 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4385 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4386 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
mbed_official 400:7fa56b1b9d45 4387 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
mbed_official 400:7fa56b1b9d45 4388 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
mbed_official 400:7fa56b1b9d45 4389 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
mbed_official 400:7fa56b1b9d45 4390 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
mbed_official 400:7fa56b1b9d45 4391 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
mbed_official 400:7fa56b1b9d45 4392 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
mbed_official 400:7fa56b1b9d45 4393 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
mbed_official 400:7fa56b1b9d45 4394 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
mbed_official 400:7fa56b1b9d45 4395 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
mbed_official 400:7fa56b1b9d45 4396 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
mbed_official 400:7fa56b1b9d45 4397 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
mbed_official 400:7fa56b1b9d45 4398 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
mbed_official 400:7fa56b1b9d45 4399 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
mbed_official 400:7fa56b1b9d45 4400 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
mbed_official 400:7fa56b1b9d45 4401 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
mbed_official 400:7fa56b1b9d45 4402 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
mbed_official 400:7fa56b1b9d45 4403
mbed_official 400:7fa56b1b9d45 4404 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 400:7fa56b1b9d45 4405 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4406 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4407 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4408 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4409 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4410 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4411 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4412 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4413 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4414 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4415 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4416 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4417 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4418 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4419 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4420 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4421 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
mbed_official 400:7fa56b1b9d45 4422 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
mbed_official 400:7fa56b1b9d45 4423 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
mbed_official 400:7fa56b1b9d45 4424 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
mbed_official 400:7fa56b1b9d45 4425 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
mbed_official 400:7fa56b1b9d45 4426 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
mbed_official 400:7fa56b1b9d45 4427 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
mbed_official 400:7fa56b1b9d45 4428 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
mbed_official 400:7fa56b1b9d45 4429 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
mbed_official 400:7fa56b1b9d45 4430 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
mbed_official 400:7fa56b1b9d45 4431 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
mbed_official 400:7fa56b1b9d45 4432 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
mbed_official 400:7fa56b1b9d45 4433 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
mbed_official 400:7fa56b1b9d45 4434 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
mbed_official 400:7fa56b1b9d45 4435 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
mbed_official 400:7fa56b1b9d45 4436 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
mbed_official 400:7fa56b1b9d45 4437 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
mbed_official 400:7fa56b1b9d45 4438
mbed_official 400:7fa56b1b9d45 4439 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 400:7fa56b1b9d45 4440 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4441 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4442 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4443 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4444 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4445 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4446 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4447 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4448 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4449 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4450 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4451 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4452 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4453 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4454 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4455 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4456 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4457 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4458 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4459 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4460 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4461 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4462 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4463 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 4464 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 4465 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4466 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4467 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 4468 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 4469 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4470 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 4471 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 4472
mbed_official 400:7fa56b1b9d45 4473 /****************** Bit definition for GPIO_LCKR register *********************/
mbed_official 400:7fa56b1b9d45 4474 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4475 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4476 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4477 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4478 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4479 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4480 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4481 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4482 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4483 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4484 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4485 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4486 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4487 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4488 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4489 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4490 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4491
mbed_official 400:7fa56b1b9d45 4492 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4493 /* */
mbed_official 400:7fa56b1b9d45 4494 /* Inter-integrated Circuit Interface */
mbed_official 400:7fa56b1b9d45 4495 /* */
mbed_official 400:7fa56b1b9d45 4496 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4497 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 400:7fa56b1b9d45 4498 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
mbed_official 400:7fa56b1b9d45 4499 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
mbed_official 400:7fa56b1b9d45 4500 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
mbed_official 400:7fa56b1b9d45 4501 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
mbed_official 400:7fa56b1b9d45 4502 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
mbed_official 400:7fa56b1b9d45 4503 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
mbed_official 400:7fa56b1b9d45 4504 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
mbed_official 400:7fa56b1b9d45 4505 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
mbed_official 400:7fa56b1b9d45 4506 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
mbed_official 400:7fa56b1b9d45 4507 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
mbed_official 400:7fa56b1b9d45 4508 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
mbed_official 400:7fa56b1b9d45 4509 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
mbed_official 400:7fa56b1b9d45 4510 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
mbed_official 400:7fa56b1b9d45 4511 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
mbed_official 400:7fa56b1b9d45 4512
mbed_official 400:7fa56b1b9d45 4513 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 400:7fa56b1b9d45 4514 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 400:7fa56b1b9d45 4515 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4516 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4517 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4518 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4519 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4520 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4521
mbed_official 400:7fa56b1b9d45 4522 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
mbed_official 400:7fa56b1b9d45 4523 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
mbed_official 400:7fa56b1b9d45 4524 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
mbed_official 400:7fa56b1b9d45 4525 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
mbed_official 400:7fa56b1b9d45 4526 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
mbed_official 400:7fa56b1b9d45 4527
mbed_official 400:7fa56b1b9d45 4528 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 400:7fa56b1b9d45 4529 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
mbed_official 400:7fa56b1b9d45 4530 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
mbed_official 400:7fa56b1b9d45 4531
mbed_official 400:7fa56b1b9d45 4532 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4533 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4534 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4535 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4536 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4537 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4538 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4539 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4540 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
mbed_official 400:7fa56b1b9d45 4541 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
mbed_official 400:7fa56b1b9d45 4542
mbed_official 400:7fa56b1b9d45 4543 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
mbed_official 400:7fa56b1b9d45 4544
mbed_official 400:7fa56b1b9d45 4545 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 400:7fa56b1b9d45 4546 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
mbed_official 400:7fa56b1b9d45 4547 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
mbed_official 400:7fa56b1b9d45 4548
mbed_official 400:7fa56b1b9d45 4549 /******************** Bit definition for I2C_DR register ********************/
mbed_official 400:7fa56b1b9d45 4550 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
mbed_official 400:7fa56b1b9d45 4551
mbed_official 400:7fa56b1b9d45 4552 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 400:7fa56b1b9d45 4553 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
mbed_official 400:7fa56b1b9d45 4554 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
mbed_official 400:7fa56b1b9d45 4555 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
mbed_official 400:7fa56b1b9d45 4556 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
mbed_official 400:7fa56b1b9d45 4557 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
mbed_official 400:7fa56b1b9d45 4558 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
mbed_official 400:7fa56b1b9d45 4559 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
mbed_official 400:7fa56b1b9d45 4560 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
mbed_official 400:7fa56b1b9d45 4561 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
mbed_official 400:7fa56b1b9d45 4562 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
mbed_official 400:7fa56b1b9d45 4563 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
mbed_official 400:7fa56b1b9d45 4564 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
mbed_official 400:7fa56b1b9d45 4565 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
mbed_official 400:7fa56b1b9d45 4566 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
mbed_official 400:7fa56b1b9d45 4567
mbed_official 400:7fa56b1b9d45 4568 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 400:7fa56b1b9d45 4569 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
mbed_official 400:7fa56b1b9d45 4570 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
mbed_official 400:7fa56b1b9d45 4571 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
mbed_official 400:7fa56b1b9d45 4572 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
mbed_official 400:7fa56b1b9d45 4573 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
mbed_official 400:7fa56b1b9d45 4574 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
mbed_official 400:7fa56b1b9d45 4575 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
mbed_official 400:7fa56b1b9d45 4576 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
mbed_official 400:7fa56b1b9d45 4577
mbed_official 400:7fa56b1b9d45 4578 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 400:7fa56b1b9d45 4579 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 400:7fa56b1b9d45 4580 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
mbed_official 400:7fa56b1b9d45 4581 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
mbed_official 400:7fa56b1b9d45 4582
mbed_official 400:7fa56b1b9d45 4583 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 400:7fa56b1b9d45 4584 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 400:7fa56b1b9d45 4585
mbed_official 400:7fa56b1b9d45 4586 /****************** Bit definition for I2C_FLTR register *******************/
mbed_official 400:7fa56b1b9d45 4587 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
mbed_official 400:7fa56b1b9d45 4588 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
mbed_official 400:7fa56b1b9d45 4589
mbed_official 400:7fa56b1b9d45 4590 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4591 /* */
mbed_official 400:7fa56b1b9d45 4592 /* Independent WATCHDOG */
mbed_official 400:7fa56b1b9d45 4593 /* */
mbed_official 400:7fa56b1b9d45 4594 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4595 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 400:7fa56b1b9d45 4596 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
mbed_official 400:7fa56b1b9d45 4597
mbed_official 400:7fa56b1b9d45 4598 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 400:7fa56b1b9d45 4599 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
mbed_official 400:7fa56b1b9d45 4600 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4601 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4602 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4603
mbed_official 400:7fa56b1b9d45 4604 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 400:7fa56b1b9d45 4605 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
mbed_official 400:7fa56b1b9d45 4606
mbed_official 400:7fa56b1b9d45 4607 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 400:7fa56b1b9d45 4608 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
mbed_official 400:7fa56b1b9d45 4609 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
mbed_official 400:7fa56b1b9d45 4610
mbed_official 400:7fa56b1b9d45 4611
mbed_official 400:7fa56b1b9d45 4612 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4613 /* */
mbed_official 400:7fa56b1b9d45 4614 /* Power Control */
mbed_official 400:7fa56b1b9d45 4615 /* */
mbed_official 400:7fa56b1b9d45 4616 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4617 /******************** Bit definition for PWR_CR register ********************/
mbed_official 400:7fa56b1b9d45 4618 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
mbed_official 400:7fa56b1b9d45 4619 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 400:7fa56b1b9d45 4620 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 400:7fa56b1b9d45 4621 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 400:7fa56b1b9d45 4622 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 400:7fa56b1b9d45 4623
mbed_official 400:7fa56b1b9d45 4624 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 400:7fa56b1b9d45 4625 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 400:7fa56b1b9d45 4626 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 400:7fa56b1b9d45 4627 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 400:7fa56b1b9d45 4628
mbed_official 400:7fa56b1b9d45 4629 /*!< PVD level configuration */
mbed_official 400:7fa56b1b9d45 4630 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 400:7fa56b1b9d45 4631 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 400:7fa56b1b9d45 4632 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 400:7fa56b1b9d45 4633 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 400:7fa56b1b9d45 4634 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 400:7fa56b1b9d45 4635 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 400:7fa56b1b9d45 4636 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 400:7fa56b1b9d45 4637 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 400:7fa56b1b9d45 4638
mbed_official 532:fe11edbda85c 4639 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 532:fe11edbda85c 4640 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
mbed_official 532:fe11edbda85c 4641 #define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
mbed_official 400:7fa56b1b9d45 4642
mbed_official 400:7fa56b1b9d45 4643 /* Legacy define */
mbed_official 400:7fa56b1b9d45 4644 #define PWR_CR_PMODE PWR_CR_VOS
mbed_official 400:7fa56b1b9d45 4645
mbed_official 400:7fa56b1b9d45 4646 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 400:7fa56b1b9d45 4647 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 400:7fa56b1b9d45 4648 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 400:7fa56b1b9d45 4649 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 400:7fa56b1b9d45 4650 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
mbed_official 400:7fa56b1b9d45 4651 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
mbed_official 400:7fa56b1b9d45 4652 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
mbed_official 400:7fa56b1b9d45 4653 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
mbed_official 400:7fa56b1b9d45 4654
mbed_official 400:7fa56b1b9d45 4655 /* Legacy define */
mbed_official 400:7fa56b1b9d45 4656 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
mbed_official 400:7fa56b1b9d45 4657
mbed_official 400:7fa56b1b9d45 4658 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4659 /* */
mbed_official 400:7fa56b1b9d45 4660 /* Reset and Clock Control */
mbed_official 400:7fa56b1b9d45 4661 /* */
mbed_official 400:7fa56b1b9d45 4662 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 4663 /******************** Bit definition for RCC_CR register ********************/
mbed_official 400:7fa56b1b9d45 4664 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4665 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4666
mbed_official 400:7fa56b1b9d45 4667 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 400:7fa56b1b9d45 4668 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4669 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4670 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4671 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4672 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4673
mbed_official 400:7fa56b1b9d45 4674 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 400:7fa56b1b9d45 4675 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 4676 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 4677 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 4678 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 4679 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 4680 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 4681 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 4682 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 4683
mbed_official 400:7fa56b1b9d45 4684 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4685 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4686 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4687 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4688 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 4689 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4690 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4691 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 4692
mbed_official 400:7fa56b1b9d45 4693 /******************** Bit definition for RCC_PLLCFGR register ***************/
mbed_official 400:7fa56b1b9d45 4694 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
mbed_official 400:7fa56b1b9d45 4695 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4696 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4697 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4698 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4699 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4700 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4701
mbed_official 400:7fa56b1b9d45 4702 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
mbed_official 400:7fa56b1b9d45 4703 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4704 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4705 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4706 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4707 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4708 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4709 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4710 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4711 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4712
mbed_official 400:7fa56b1b9d45 4713 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
mbed_official 400:7fa56b1b9d45 4714 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4715 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4716
mbed_official 400:7fa56b1b9d45 4717 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4718 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4719 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
mbed_official 400:7fa56b1b9d45 4720
mbed_official 400:7fa56b1b9d45 4721 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
mbed_official 400:7fa56b1b9d45 4722 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 4723 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4724 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4725 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 4726
mbed_official 400:7fa56b1b9d45 4727 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 400:7fa56b1b9d45 4728 /*!< SW configuration */
mbed_official 400:7fa56b1b9d45 4729 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 400:7fa56b1b9d45 4730 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 400:7fa56b1b9d45 4731 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 400:7fa56b1b9d45 4732
mbed_official 400:7fa56b1b9d45 4733 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 400:7fa56b1b9d45 4734 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 400:7fa56b1b9d45 4735 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 400:7fa56b1b9d45 4736
mbed_official 400:7fa56b1b9d45 4737 /*!< SWS configuration */
mbed_official 400:7fa56b1b9d45 4738 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 400:7fa56b1b9d45 4739 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 400:7fa56b1b9d45 4740 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 400:7fa56b1b9d45 4741
mbed_official 400:7fa56b1b9d45 4742 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 400:7fa56b1b9d45 4743 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 400:7fa56b1b9d45 4744 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 400:7fa56b1b9d45 4745
mbed_official 400:7fa56b1b9d45 4746 /*!< HPRE configuration */
mbed_official 400:7fa56b1b9d45 4747 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 400:7fa56b1b9d45 4748 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 400:7fa56b1b9d45 4749 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 400:7fa56b1b9d45 4750 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 400:7fa56b1b9d45 4751 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 400:7fa56b1b9d45 4752
mbed_official 400:7fa56b1b9d45 4753 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 400:7fa56b1b9d45 4754 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 400:7fa56b1b9d45 4755 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 400:7fa56b1b9d45 4756 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 400:7fa56b1b9d45 4757 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 400:7fa56b1b9d45 4758 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 400:7fa56b1b9d45 4759 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 400:7fa56b1b9d45 4760 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 400:7fa56b1b9d45 4761 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 400:7fa56b1b9d45 4762
mbed_official 400:7fa56b1b9d45 4763 /*!< PPRE1 configuration */
mbed_official 400:7fa56b1b9d45 4764 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 400:7fa56b1b9d45 4765 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 400:7fa56b1b9d45 4766 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 400:7fa56b1b9d45 4767 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 400:7fa56b1b9d45 4768
mbed_official 400:7fa56b1b9d45 4769 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 400:7fa56b1b9d45 4770 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
mbed_official 400:7fa56b1b9d45 4771 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
mbed_official 400:7fa56b1b9d45 4772 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
mbed_official 400:7fa56b1b9d45 4773 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
mbed_official 400:7fa56b1b9d45 4774
mbed_official 400:7fa56b1b9d45 4775 /*!< PPRE2 configuration */
mbed_official 400:7fa56b1b9d45 4776 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 400:7fa56b1b9d45 4777 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 400:7fa56b1b9d45 4778 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 400:7fa56b1b9d45 4779 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 400:7fa56b1b9d45 4780
mbed_official 400:7fa56b1b9d45 4781 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 400:7fa56b1b9d45 4782 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
mbed_official 400:7fa56b1b9d45 4783 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
mbed_official 400:7fa56b1b9d45 4784 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
mbed_official 400:7fa56b1b9d45 4785 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
mbed_official 400:7fa56b1b9d45 4786
mbed_official 400:7fa56b1b9d45 4787 /*!< RTCPRE configuration */
mbed_official 400:7fa56b1b9d45 4788 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
mbed_official 400:7fa56b1b9d45 4789 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4790 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4791 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4792 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4793 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4794
mbed_official 400:7fa56b1b9d45 4795 /*!< MCO1 configuration */
mbed_official 400:7fa56b1b9d45 4796 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
mbed_official 400:7fa56b1b9d45 4797 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4798 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4799
mbed_official 400:7fa56b1b9d45 4800 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 4801
mbed_official 400:7fa56b1b9d45 4802 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
mbed_official 400:7fa56b1b9d45 4803 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 4804 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4805 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4806
mbed_official 400:7fa56b1b9d45 4807 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
mbed_official 400:7fa56b1b9d45 4808 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 4809 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 4810 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4811
mbed_official 400:7fa56b1b9d45 4812 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
mbed_official 400:7fa56b1b9d45 4813 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 4814 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 4815
mbed_official 400:7fa56b1b9d45 4816 /******************** Bit definition for RCC_CIR register *******************/
mbed_official 400:7fa56b1b9d45 4817 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4818 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4819 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4820 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4821 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4822 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4823
mbed_official 400:7fa56b1b9d45 4824 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4825 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4826 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4827 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4828 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4829 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4830 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 4831
mbed_official 400:7fa56b1b9d45 4832 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4833 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4834 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4835 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4836 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4837 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4838
mbed_official 400:7fa56b1b9d45 4839 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 4840
mbed_official 400:7fa56b1b9d45 4841 /******************** Bit definition for RCC_AHB1RSTR register **************/
mbed_official 400:7fa56b1b9d45 4842 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4843 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4844 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4845 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4846 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4847 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4848 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4849 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4850 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4851 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4852 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4853 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
mbed_official 532:fe11edbda85c 4854 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4855
mbed_official 400:7fa56b1b9d45 4856 /******************** Bit definition for RCC_AHB2RSTR register **************/
mbed_official 400:7fa56b1b9d45 4857 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4858 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4859
mbed_official 400:7fa56b1b9d45 4860 /******************** Bit definition for RCC_AHB3RSTR register **************/
mbed_official 400:7fa56b1b9d45 4861
mbed_official 400:7fa56b1b9d45 4862 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4863
mbed_official 400:7fa56b1b9d45 4864 /******************** Bit definition for RCC_APB1RSTR register **************/
mbed_official 400:7fa56b1b9d45 4865 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4866 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4867 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4868 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4869 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4870 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4871 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4872 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4873 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4874 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4875 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4876 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4877 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4878 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4879 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4880 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4881 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4882 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4883 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 4884 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4885 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4886 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 4887 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4888
mbed_official 400:7fa56b1b9d45 4889 /******************** Bit definition for RCC_APB2RSTR register **************/
mbed_official 400:7fa56b1b9d45 4890 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4891 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4892 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4893 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4894 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4895 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4896 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4897 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4898 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4899 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4900 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4901
mbed_official 400:7fa56b1b9d45 4902 /* Old SPI1RST bit definition, maintained for legacy purpose */
mbed_official 400:7fa56b1b9d45 4903 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
mbed_official 400:7fa56b1b9d45 4904
mbed_official 400:7fa56b1b9d45 4905 /******************** Bit definition for RCC_AHB1ENR register ***************/
mbed_official 400:7fa56b1b9d45 4906 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4907 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4908 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4909 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4910 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4911 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4912 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4913 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4914 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4915 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4916 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4917 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4918 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4919 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4920
mbed_official 400:7fa56b1b9d45 4921 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4922 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 4923
mbed_official 400:7fa56b1b9d45 4924 /******************** Bit definition for RCC_AHB2ENR register ***************/
mbed_official 400:7fa56b1b9d45 4925 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4926 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4927
mbed_official 400:7fa56b1b9d45 4928 /******************** Bit definition for RCC_AHB3ENR register ***************/
mbed_official 400:7fa56b1b9d45 4929
mbed_official 400:7fa56b1b9d45 4930 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4931
mbed_official 400:7fa56b1b9d45 4932 /******************** Bit definition for RCC_APB1ENR register ***************/
mbed_official 400:7fa56b1b9d45 4933 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4934 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4935 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4936 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4937 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4938 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4939 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4940 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4941 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4942 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4943 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4944 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4945 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4946 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4947 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 4948 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4949 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4950 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4951 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 4952 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 4953 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 4954 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 4955 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4956
mbed_official 400:7fa56b1b9d45 4957 /******************** Bit definition for RCC_APB2ENR register ***************/
mbed_official 400:7fa56b1b9d45 4958 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4959 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4960 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4961 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4962 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4963 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 4964 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 4965 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 4966 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4967 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 4968 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4969 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4970 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4971 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 4972 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4973
mbed_official 400:7fa56b1b9d45 4974 /******************** Bit definition for RCC_AHB1LPENR register *************/
mbed_official 400:7fa56b1b9d45 4975 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 4976 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 4977 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 4978 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 4979 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 4980 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 4981 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4982 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4983 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 4984 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 4985 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 4986 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 4987 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 4988 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 4989 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 4990 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 4991 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 4992 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 4993
mbed_official 400:7fa56b1b9d45 4994 /******************** Bit definition for RCC_AHB2LPENR register *************/
mbed_official 400:7fa56b1b9d45 4995 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 4996 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 4997
mbed_official 400:7fa56b1b9d45 4998 /******************** Bit definition for RCC_AHB3LPENR register *************/
mbed_official 400:7fa56b1b9d45 4999
mbed_official 400:7fa56b1b9d45 5000 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5001
mbed_official 400:7fa56b1b9d45 5002 /******************** Bit definition for RCC_APB1LPENR register *************/
mbed_official 400:7fa56b1b9d45 5003 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5004 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5005 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5006 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5007 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5008 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5009 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5010 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5011 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5012 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5013 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5014 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5015 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5016 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5017 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 5018 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 5019 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 5020 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 5021 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 5022 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 5023 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 5024 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 5025 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 5026
mbed_official 400:7fa56b1b9d45 5027 /******************** Bit definition for RCC_APB2LPENR register *************/
mbed_official 400:7fa56b1b9d45 5028 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5029 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5030 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5031 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5032 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5033 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5034 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5035 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5036 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5037 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5038 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5039 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5040 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5041
mbed_official 400:7fa56b1b9d45 5042 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 400:7fa56b1b9d45 5043 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5044 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5045 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5046
mbed_official 400:7fa56b1b9d45 5047 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
mbed_official 400:7fa56b1b9d45 5048 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5049 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5050
mbed_official 400:7fa56b1b9d45 5051 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5052 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5053
mbed_official 400:7fa56b1b9d45 5054 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 400:7fa56b1b9d45 5055 #define RCC_CSR_LSION ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5056 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5057 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 5058 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 5059 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 5060 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 5061 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 5062 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 5063 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 5064 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 5065
mbed_official 400:7fa56b1b9d45 5066 /******************** Bit definition for RCC_SSCGR register *****************/
mbed_official 400:7fa56b1b9d45 5067 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
mbed_official 400:7fa56b1b9d45 5068 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
mbed_official 400:7fa56b1b9d45 5069 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 5070 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 5071
mbed_official 400:7fa56b1b9d45 5072 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
mbed_official 400:7fa56b1b9d45 5073 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
mbed_official 400:7fa56b1b9d45 5074 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5075 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5076 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5077 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5078 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5079 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5080 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5081 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5082 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5083
mbed_official 400:7fa56b1b9d45 5084 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
mbed_official 400:7fa56b1b9d45 5085 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 5086 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 5087 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 5088
mbed_official 400:7fa56b1b9d45 5089 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5090 /* */
mbed_official 400:7fa56b1b9d45 5091 /* RNG */
mbed_official 400:7fa56b1b9d45 5092 /* */
mbed_official 400:7fa56b1b9d45 5093 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5094 /******************** Bits definition for RNG_CR register *******************/
mbed_official 400:7fa56b1b9d45 5095 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5096 #define RNG_CR_IE ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5097
mbed_official 400:7fa56b1b9d45 5098 /******************** Bits definition for RNG_SR register *******************/
mbed_official 400:7fa56b1b9d45 5099 #define RNG_SR_DRDY ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5100 #define RNG_SR_CECS ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5101 #define RNG_SR_SECS ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5102 #define RNG_SR_CEIS ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5103 #define RNG_SR_SEIS ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5104
mbed_official 400:7fa56b1b9d45 5105 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5106 /* */
mbed_official 400:7fa56b1b9d45 5107 /* Real-Time Clock (RTC) */
mbed_official 400:7fa56b1b9d45 5108 /* */
mbed_official 400:7fa56b1b9d45 5109 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5110 /******************** Bits definition for RTC_TR register *******************/
mbed_official 400:7fa56b1b9d45 5111 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 5112 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 400:7fa56b1b9d45 5113 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 5114 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 5115 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 400:7fa56b1b9d45 5116 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5117 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5118 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5119 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 5120 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 400:7fa56b1b9d45 5121 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5122 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5123 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5124 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 400:7fa56b1b9d45 5125 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5126 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5127 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5128 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5129 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 400:7fa56b1b9d45 5130 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5131 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5132 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5133 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 400:7fa56b1b9d45 5134 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5135 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5136 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5137 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5138
mbed_official 400:7fa56b1b9d45 5139 /******************** Bits definition for RTC_DR register *******************/
mbed_official 400:7fa56b1b9d45 5140 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 400:7fa56b1b9d45 5141 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 5142 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 5143 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 5144 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 5145 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 400:7fa56b1b9d45 5146 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5147 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5148 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5149 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 5150 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 400:7fa56b1b9d45 5151 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5152 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5153 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5154 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5155 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 400:7fa56b1b9d45 5156 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5157 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5158 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5159 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5160 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 400:7fa56b1b9d45 5161 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5162 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5163 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 400:7fa56b1b9d45 5164 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5165 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5166 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5167 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5168
mbed_official 400:7fa56b1b9d45 5169 /******************** Bits definition for RTC_CR register *******************/
mbed_official 400:7fa56b1b9d45 5170 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 5171 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 400:7fa56b1b9d45 5172 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 5173 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 5174 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 5175 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 5176 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5177 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5178 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5179 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5180 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5181 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5182 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5183 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5184 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5185 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5186 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5187 #define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5188 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5189 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5190 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5191 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5192 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 400:7fa56b1b9d45 5193 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5194 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5195 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5196
mbed_official 400:7fa56b1b9d45 5197 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 400:7fa56b1b9d45 5198 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5199 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5200 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5201 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5202 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5203 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5204 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5205 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5206 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5207 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5208 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5209 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5210 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5211 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5212 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5213 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5214
mbed_official 400:7fa56b1b9d45 5215 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 400:7fa56b1b9d45 5216 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 613:bc40b8d2aec4 5217 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 400:7fa56b1b9d45 5218
mbed_official 400:7fa56b1b9d45 5219 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 400:7fa56b1b9d45 5220 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 400:7fa56b1b9d45 5221
mbed_official 400:7fa56b1b9d45 5222 /******************** Bits definition for RTC_CALIBR register ***************/
mbed_official 400:7fa56b1b9d45 5223 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5224 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official 400:7fa56b1b9d45 5225
mbed_official 400:7fa56b1b9d45 5226 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 400:7fa56b1b9d45 5227 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 5228 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 5229 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 400:7fa56b1b9d45 5230 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 5231 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 5232 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 400:7fa56b1b9d45 5233 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 5234 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 5235 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 5236 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 5237 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 5238 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 5239 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 400:7fa56b1b9d45 5240 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 5241 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 5242 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 400:7fa56b1b9d45 5243 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5244 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5245 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5246 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 5247 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5248 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 400:7fa56b1b9d45 5249 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5250 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5251 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5252 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 400:7fa56b1b9d45 5253 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5254 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5255 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5256 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5257 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5258 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 400:7fa56b1b9d45 5259 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5260 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5261 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5262 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 400:7fa56b1b9d45 5263 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5264 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5265 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5266 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5267
mbed_official 400:7fa56b1b9d45 5268 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 400:7fa56b1b9d45 5269 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 5270 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 400:7fa56b1b9d45 5271 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 400:7fa56b1b9d45 5272 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 400:7fa56b1b9d45 5273 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 400:7fa56b1b9d45 5274 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 400:7fa56b1b9d45 5275 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 5276 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 5277 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 5278 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 5279 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 5280 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 5281 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 400:7fa56b1b9d45 5282 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 5283 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 5284 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 400:7fa56b1b9d45 5285 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5286 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5287 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5288 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 5289 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5290 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 400:7fa56b1b9d45 5291 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5292 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5293 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5294 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 400:7fa56b1b9d45 5295 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5296 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5297 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5298 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5299 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5300 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 400:7fa56b1b9d45 5301 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5302 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5303 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5304 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 400:7fa56b1b9d45 5305 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5306 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5307 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5308 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5309
mbed_official 400:7fa56b1b9d45 5310 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 400:7fa56b1b9d45 5311 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 400:7fa56b1b9d45 5312
mbed_official 400:7fa56b1b9d45 5313 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 400:7fa56b1b9d45 5314 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 400:7fa56b1b9d45 5315
mbed_official 400:7fa56b1b9d45 5316 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 400:7fa56b1b9d45 5317 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 400:7fa56b1b9d45 5318 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 400:7fa56b1b9d45 5319
mbed_official 400:7fa56b1b9d45 5320 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 400:7fa56b1b9d45 5321 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 5322 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 400:7fa56b1b9d45 5323 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 400:7fa56b1b9d45 5324 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 5325 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 400:7fa56b1b9d45 5326 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5327 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5328 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5329 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 400:7fa56b1b9d45 5330 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 400:7fa56b1b9d45 5331 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5332 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5333 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5334 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 400:7fa56b1b9d45 5335 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5336 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5337 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5338 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5339 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 400:7fa56b1b9d45 5340 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5341 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5342 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5343 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 400:7fa56b1b9d45 5344 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5345 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5346 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5347 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5348
mbed_official 400:7fa56b1b9d45 5349 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 400:7fa56b1b9d45 5350 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 400:7fa56b1b9d45 5351 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5352 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5353 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5354 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5355 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 400:7fa56b1b9d45 5356 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5357 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5358 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5359 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5360 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 400:7fa56b1b9d45 5361 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5362 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5363 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 400:7fa56b1b9d45 5364 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5365 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5366 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5367 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5368
mbed_official 400:7fa56b1b9d45 5369 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 400:7fa56b1b9d45 5370 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 400:7fa56b1b9d45 5371
mbed_official 400:7fa56b1b9d45 5372 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 400:7fa56b1b9d45 5373 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5374 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5375 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5376 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 400:7fa56b1b9d45 5377 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5378 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5379 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5380 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5381 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5382 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 5383 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 5384 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5385 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5386
mbed_official 400:7fa56b1b9d45 5387 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 400:7fa56b1b9d45 5388 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 5389 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 5390 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 5391 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 400:7fa56b1b9d45 5392 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 400:7fa56b1b9d45 5393 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 400:7fa56b1b9d45 5394 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 400:7fa56b1b9d45 5395 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 400:7fa56b1b9d45 5396 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 5397 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 5398 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 400:7fa56b1b9d45 5399 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 5400 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 400:7fa56b1b9d45 5401 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 5402 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 5403 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 5404 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 5405 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5406 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5407 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5408
mbed_official 400:7fa56b1b9d45 5409 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 400:7fa56b1b9d45 5410 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 400:7fa56b1b9d45 5411 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 5412 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 5413 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 5414 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 5415 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 400:7fa56b1b9d45 5416
mbed_official 400:7fa56b1b9d45 5417 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 400:7fa56b1b9d45 5418 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 400:7fa56b1b9d45 5419 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 400:7fa56b1b9d45 5420 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 5421 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 5422 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 400:7fa56b1b9d45 5423 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 400:7fa56b1b9d45 5424
mbed_official 400:7fa56b1b9d45 5425 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 400:7fa56b1b9d45 5426 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5427
mbed_official 400:7fa56b1b9d45 5428 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 400:7fa56b1b9d45 5429 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5430
mbed_official 400:7fa56b1b9d45 5431 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 400:7fa56b1b9d45 5432 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5433
mbed_official 400:7fa56b1b9d45 5434 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 400:7fa56b1b9d45 5435 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5436
mbed_official 400:7fa56b1b9d45 5437 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 400:7fa56b1b9d45 5438 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5439
mbed_official 400:7fa56b1b9d45 5440 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 400:7fa56b1b9d45 5441 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5442
mbed_official 400:7fa56b1b9d45 5443 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 400:7fa56b1b9d45 5444 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5445
mbed_official 400:7fa56b1b9d45 5446 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 400:7fa56b1b9d45 5447 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5448
mbed_official 400:7fa56b1b9d45 5449 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 400:7fa56b1b9d45 5450 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5451
mbed_official 400:7fa56b1b9d45 5452 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 400:7fa56b1b9d45 5453 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5454
mbed_official 400:7fa56b1b9d45 5455 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 400:7fa56b1b9d45 5456 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5457
mbed_official 400:7fa56b1b9d45 5458 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 400:7fa56b1b9d45 5459 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5460
mbed_official 400:7fa56b1b9d45 5461 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 400:7fa56b1b9d45 5462 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5463
mbed_official 400:7fa56b1b9d45 5464 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 400:7fa56b1b9d45 5465 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5466
mbed_official 400:7fa56b1b9d45 5467 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 400:7fa56b1b9d45 5468 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5469
mbed_official 400:7fa56b1b9d45 5470 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 400:7fa56b1b9d45 5471 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5472
mbed_official 400:7fa56b1b9d45 5473 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 400:7fa56b1b9d45 5474 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5475
mbed_official 400:7fa56b1b9d45 5476 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 400:7fa56b1b9d45 5477 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5478
mbed_official 400:7fa56b1b9d45 5479 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 400:7fa56b1b9d45 5480 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5481
mbed_official 400:7fa56b1b9d45 5482 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 400:7fa56b1b9d45 5483 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 400:7fa56b1b9d45 5484
mbed_official 400:7fa56b1b9d45 5485
mbed_official 400:7fa56b1b9d45 5486
mbed_official 400:7fa56b1b9d45 5487 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5488 /* */
mbed_official 400:7fa56b1b9d45 5489 /* SD host Interface */
mbed_official 400:7fa56b1b9d45 5490 /* */
mbed_official 400:7fa56b1b9d45 5491 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5492 /****************** Bit definition for SDIO_POWER register ******************/
mbed_official 400:7fa56b1b9d45 5493 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
mbed_official 400:7fa56b1b9d45 5494 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5495 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5496
mbed_official 400:7fa56b1b9d45 5497 /****************** Bit definition for SDIO_CLKCR register ******************/
mbed_official 400:7fa56b1b9d45 5498 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
mbed_official 400:7fa56b1b9d45 5499 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
mbed_official 400:7fa56b1b9d45 5500 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
mbed_official 400:7fa56b1b9d45 5501 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
mbed_official 400:7fa56b1b9d45 5502
mbed_official 400:7fa56b1b9d45 5503 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
mbed_official 400:7fa56b1b9d45 5504 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5505 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5506
mbed_official 400:7fa56b1b9d45 5507 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
mbed_official 400:7fa56b1b9d45 5508 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
mbed_official 400:7fa56b1b9d45 5509
mbed_official 400:7fa56b1b9d45 5510 /******************* Bit definition for SDIO_ARG register *******************/
mbed_official 400:7fa56b1b9d45 5511 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
mbed_official 400:7fa56b1b9d45 5512
mbed_official 400:7fa56b1b9d45 5513 /******************* Bit definition for SDIO_CMD register *******************/
mbed_official 400:7fa56b1b9d45 5514 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
mbed_official 400:7fa56b1b9d45 5515
mbed_official 400:7fa56b1b9d45 5516 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
mbed_official 400:7fa56b1b9d45 5517 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
mbed_official 400:7fa56b1b9d45 5518 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
mbed_official 400:7fa56b1b9d45 5519
mbed_official 400:7fa56b1b9d45 5520 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
mbed_official 400:7fa56b1b9d45 5521 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
mbed_official 400:7fa56b1b9d45 5522 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
mbed_official 400:7fa56b1b9d45 5523 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
mbed_official 400:7fa56b1b9d45 5524 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
mbed_official 400:7fa56b1b9d45 5525 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5526 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
mbed_official 400:7fa56b1b9d45 5527
mbed_official 400:7fa56b1b9d45 5528 /***************** Bit definition for SDIO_RESPCMD register *****************/
mbed_official 400:7fa56b1b9d45 5529 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
mbed_official 400:7fa56b1b9d45 5530
mbed_official 400:7fa56b1b9d45 5531 /****************** Bit definition for SDIO_RESP0 register ******************/
mbed_official 400:7fa56b1b9d45 5532 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 400:7fa56b1b9d45 5533
mbed_official 400:7fa56b1b9d45 5534 /****************** Bit definition for SDIO_RESP1 register ******************/
mbed_official 400:7fa56b1b9d45 5535 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 400:7fa56b1b9d45 5536
mbed_official 400:7fa56b1b9d45 5537 /****************** Bit definition for SDIO_RESP2 register ******************/
mbed_official 400:7fa56b1b9d45 5538 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 400:7fa56b1b9d45 5539
mbed_official 400:7fa56b1b9d45 5540 /****************** Bit definition for SDIO_RESP3 register ******************/
mbed_official 400:7fa56b1b9d45 5541 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 400:7fa56b1b9d45 5542
mbed_official 400:7fa56b1b9d45 5543 /****************** Bit definition for SDIO_RESP4 register ******************/
mbed_official 400:7fa56b1b9d45 5544 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 400:7fa56b1b9d45 5545
mbed_official 400:7fa56b1b9d45 5546 /****************** Bit definition for SDIO_DTIMER register *****************/
mbed_official 400:7fa56b1b9d45 5547 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
mbed_official 400:7fa56b1b9d45 5548
mbed_official 400:7fa56b1b9d45 5549 /****************** Bit definition for SDIO_DLEN register *******************/
mbed_official 400:7fa56b1b9d45 5550 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
mbed_official 400:7fa56b1b9d45 5551
mbed_official 400:7fa56b1b9d45 5552 /****************** Bit definition for SDIO_DCTRL register ******************/
mbed_official 400:7fa56b1b9d45 5553 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
mbed_official 400:7fa56b1b9d45 5554 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
mbed_official 400:7fa56b1b9d45 5555 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
mbed_official 400:7fa56b1b9d45 5556 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
mbed_official 400:7fa56b1b9d45 5557
mbed_official 400:7fa56b1b9d45 5558 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
mbed_official 400:7fa56b1b9d45 5559 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5560 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5561 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 5562 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 5563
mbed_official 400:7fa56b1b9d45 5564 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
mbed_official 400:7fa56b1b9d45 5565 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
mbed_official 400:7fa56b1b9d45 5566 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
mbed_official 400:7fa56b1b9d45 5567 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
mbed_official 400:7fa56b1b9d45 5568
mbed_official 400:7fa56b1b9d45 5569 /****************** Bit definition for SDIO_DCOUNT register *****************/
mbed_official 400:7fa56b1b9d45 5570 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
mbed_official 400:7fa56b1b9d45 5571
mbed_official 400:7fa56b1b9d45 5572 /****************** Bit definition for SDIO_STA register ********************/
mbed_official 400:7fa56b1b9d45 5573 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
mbed_official 400:7fa56b1b9d45 5574 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
mbed_official 400:7fa56b1b9d45 5575 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
mbed_official 400:7fa56b1b9d45 5576 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
mbed_official 400:7fa56b1b9d45 5577 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
mbed_official 400:7fa56b1b9d45 5578 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
mbed_official 400:7fa56b1b9d45 5579 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
mbed_official 400:7fa56b1b9d45 5580 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
mbed_official 400:7fa56b1b9d45 5581 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
mbed_official 400:7fa56b1b9d45 5582 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
mbed_official 400:7fa56b1b9d45 5583 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
mbed_official 400:7fa56b1b9d45 5584 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
mbed_official 400:7fa56b1b9d45 5585 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
mbed_official 400:7fa56b1b9d45 5586 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
mbed_official 400:7fa56b1b9d45 5587 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
mbed_official 400:7fa56b1b9d45 5588 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
mbed_official 400:7fa56b1b9d45 5589 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
mbed_official 400:7fa56b1b9d45 5590 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
mbed_official 400:7fa56b1b9d45 5591 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
mbed_official 400:7fa56b1b9d45 5592 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
mbed_official 400:7fa56b1b9d45 5593 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
mbed_official 400:7fa56b1b9d45 5594 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
mbed_official 400:7fa56b1b9d45 5595 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
mbed_official 400:7fa56b1b9d45 5596 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
mbed_official 400:7fa56b1b9d45 5597
mbed_official 400:7fa56b1b9d45 5598 /******************* Bit definition for SDIO_ICR register *******************/
mbed_official 400:7fa56b1b9d45 5599 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
mbed_official 400:7fa56b1b9d45 5600 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
mbed_official 400:7fa56b1b9d45 5601 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
mbed_official 400:7fa56b1b9d45 5602 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
mbed_official 400:7fa56b1b9d45 5603 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
mbed_official 400:7fa56b1b9d45 5604 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
mbed_official 400:7fa56b1b9d45 5605 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
mbed_official 400:7fa56b1b9d45 5606 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
mbed_official 400:7fa56b1b9d45 5607 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
mbed_official 400:7fa56b1b9d45 5608 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
mbed_official 400:7fa56b1b9d45 5609 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
mbed_official 400:7fa56b1b9d45 5610 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
mbed_official 400:7fa56b1b9d45 5611 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
mbed_official 400:7fa56b1b9d45 5612
mbed_official 400:7fa56b1b9d45 5613 /****************** Bit definition for SDIO_MASK register *******************/
mbed_official 400:7fa56b1b9d45 5614 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5615 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5616 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5617 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5618 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5619 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5620 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5621 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5622 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5623 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5624 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5625 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5626 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5627 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
mbed_official 400:7fa56b1b9d45 5628 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
mbed_official 400:7fa56b1b9d45 5629 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
mbed_official 400:7fa56b1b9d45 5630 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
mbed_official 400:7fa56b1b9d45 5631 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
mbed_official 400:7fa56b1b9d45 5632 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
mbed_official 400:7fa56b1b9d45 5633 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
mbed_official 400:7fa56b1b9d45 5634 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
mbed_official 400:7fa56b1b9d45 5635 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
mbed_official 400:7fa56b1b9d45 5636 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
mbed_official 400:7fa56b1b9d45 5637 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5638
mbed_official 400:7fa56b1b9d45 5639 /***************** Bit definition for SDIO_FIFOCNT register *****************/
mbed_official 400:7fa56b1b9d45 5640 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
mbed_official 400:7fa56b1b9d45 5641
mbed_official 400:7fa56b1b9d45 5642 /****************** Bit definition for SDIO_FIFO register *******************/
mbed_official 400:7fa56b1b9d45 5643 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
mbed_official 400:7fa56b1b9d45 5644
mbed_official 400:7fa56b1b9d45 5645 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5646 /* */
mbed_official 400:7fa56b1b9d45 5647 /* Serial Peripheral Interface */
mbed_official 400:7fa56b1b9d45 5648 /* */
mbed_official 400:7fa56b1b9d45 5649 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5650 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 400:7fa56b1b9d45 5651 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
mbed_official 400:7fa56b1b9d45 5652 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
mbed_official 400:7fa56b1b9d45 5653 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
mbed_official 400:7fa56b1b9d45 5654
mbed_official 400:7fa56b1b9d45 5655 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
mbed_official 400:7fa56b1b9d45 5656 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5657 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5658 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 5659
mbed_official 400:7fa56b1b9d45 5660 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
mbed_official 400:7fa56b1b9d45 5661 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
mbed_official 400:7fa56b1b9d45 5662 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
mbed_official 400:7fa56b1b9d45 5663 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
mbed_official 400:7fa56b1b9d45 5664 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
mbed_official 400:7fa56b1b9d45 5665 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
mbed_official 400:7fa56b1b9d45 5666 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
mbed_official 400:7fa56b1b9d45 5667 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
mbed_official 400:7fa56b1b9d45 5668 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
mbed_official 400:7fa56b1b9d45 5669 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
mbed_official 400:7fa56b1b9d45 5670
mbed_official 400:7fa56b1b9d45 5671 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 400:7fa56b1b9d45 5672 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
mbed_official 400:7fa56b1b9d45 5673 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
mbed_official 400:7fa56b1b9d45 5674 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
mbed_official 400:7fa56b1b9d45 5675 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
mbed_official 400:7fa56b1b9d45 5676 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5677 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5678 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
mbed_official 400:7fa56b1b9d45 5679
mbed_official 400:7fa56b1b9d45 5680 /******************** Bit definition for SPI_SR register ********************/
mbed_official 400:7fa56b1b9d45 5681 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
mbed_official 400:7fa56b1b9d45 5682 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
mbed_official 400:7fa56b1b9d45 5683 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
mbed_official 400:7fa56b1b9d45 5684 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
mbed_official 400:7fa56b1b9d45 5685 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
mbed_official 400:7fa56b1b9d45 5686 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
mbed_official 400:7fa56b1b9d45 5687 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
mbed_official 400:7fa56b1b9d45 5688 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
mbed_official 400:7fa56b1b9d45 5689 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
mbed_official 400:7fa56b1b9d45 5690
mbed_official 400:7fa56b1b9d45 5691 /******************** Bit definition for SPI_DR register ********************/
mbed_official 400:7fa56b1b9d45 5692 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
mbed_official 400:7fa56b1b9d45 5693
mbed_official 400:7fa56b1b9d45 5694 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 400:7fa56b1b9d45 5695 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
mbed_official 400:7fa56b1b9d45 5696
mbed_official 400:7fa56b1b9d45 5697 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 400:7fa56b1b9d45 5698 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
mbed_official 400:7fa56b1b9d45 5699
mbed_official 400:7fa56b1b9d45 5700 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 400:7fa56b1b9d45 5701 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
mbed_official 400:7fa56b1b9d45 5702
mbed_official 400:7fa56b1b9d45 5703 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 400:7fa56b1b9d45 5704 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 400:7fa56b1b9d45 5705
mbed_official 400:7fa56b1b9d45 5706 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 400:7fa56b1b9d45 5707 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5708 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5709
mbed_official 400:7fa56b1b9d45 5710 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 400:7fa56b1b9d45 5711
mbed_official 400:7fa56b1b9d45 5712 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 400:7fa56b1b9d45 5713 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5714 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5715
mbed_official 400:7fa56b1b9d45 5716 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 400:7fa56b1b9d45 5717
mbed_official 400:7fa56b1b9d45 5718 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 400:7fa56b1b9d45 5719 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5720 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5721
mbed_official 400:7fa56b1b9d45 5722 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 400:7fa56b1b9d45 5723 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 400:7fa56b1b9d45 5724
mbed_official 400:7fa56b1b9d45 5725 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 400:7fa56b1b9d45 5726 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 400:7fa56b1b9d45 5727 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 400:7fa56b1b9d45 5728 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 400:7fa56b1b9d45 5729
mbed_official 400:7fa56b1b9d45 5730 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5731 /* */
mbed_official 400:7fa56b1b9d45 5732 /* SYSCFG */
mbed_official 400:7fa56b1b9d45 5733 /* */
mbed_official 400:7fa56b1b9d45 5734 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5735 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
mbed_official 400:7fa56b1b9d45 5736 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
mbed_official 400:7fa56b1b9d45 5737 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 5738 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 5739 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 5740
mbed_official 400:7fa56b1b9d45 5741 /****************** Bit definition for SYSCFG_PMC register ******************/
mbed_official 400:7fa56b1b9d45 5742 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
mbed_official 400:7fa56b1b9d45 5743 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
mbed_official 400:7fa56b1b9d45 5744 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
mbed_official 400:7fa56b1b9d45 5745
mbed_official 400:7fa56b1b9d45 5746 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 400:7fa56b1b9d45 5747 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
mbed_official 400:7fa56b1b9d45 5748 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
mbed_official 400:7fa56b1b9d45 5749 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
mbed_official 400:7fa56b1b9d45 5750 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
mbed_official 400:7fa56b1b9d45 5751 /**
mbed_official 400:7fa56b1b9d45 5752 * @brief EXTI0 configuration
mbed_official 400:7fa56b1b9d45 5753 */
mbed_official 400:7fa56b1b9d45 5754 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
mbed_official 400:7fa56b1b9d45 5755 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
mbed_official 400:7fa56b1b9d45 5756 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
mbed_official 400:7fa56b1b9d45 5757 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
mbed_official 400:7fa56b1b9d45 5758 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
mbed_official 400:7fa56b1b9d45 5759 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
mbed_official 400:7fa56b1b9d45 5760 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
mbed_official 400:7fa56b1b9d45 5761 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
mbed_official 400:7fa56b1b9d45 5762 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
mbed_official 400:7fa56b1b9d45 5763
mbed_official 400:7fa56b1b9d45 5764 /**
mbed_official 400:7fa56b1b9d45 5765 * @brief EXTI1 configuration
mbed_official 400:7fa56b1b9d45 5766 */
mbed_official 400:7fa56b1b9d45 5767 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
mbed_official 400:7fa56b1b9d45 5768 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
mbed_official 400:7fa56b1b9d45 5769 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
mbed_official 400:7fa56b1b9d45 5770 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
mbed_official 400:7fa56b1b9d45 5771 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
mbed_official 400:7fa56b1b9d45 5772 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
mbed_official 400:7fa56b1b9d45 5773 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
mbed_official 400:7fa56b1b9d45 5774 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
mbed_official 400:7fa56b1b9d45 5775 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
mbed_official 400:7fa56b1b9d45 5776
mbed_official 400:7fa56b1b9d45 5777 /**
mbed_official 400:7fa56b1b9d45 5778 * @brief EXTI2 configuration
mbed_official 400:7fa56b1b9d45 5779 */
mbed_official 400:7fa56b1b9d45 5780 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
mbed_official 400:7fa56b1b9d45 5781 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
mbed_official 400:7fa56b1b9d45 5782 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
mbed_official 400:7fa56b1b9d45 5783 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
mbed_official 400:7fa56b1b9d45 5784 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
mbed_official 400:7fa56b1b9d45 5785 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
mbed_official 400:7fa56b1b9d45 5786 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
mbed_official 400:7fa56b1b9d45 5787 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
mbed_official 400:7fa56b1b9d45 5788 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
mbed_official 400:7fa56b1b9d45 5789
mbed_official 400:7fa56b1b9d45 5790 /**
mbed_official 400:7fa56b1b9d45 5791 * @brief EXTI3 configuration
mbed_official 400:7fa56b1b9d45 5792 */
mbed_official 400:7fa56b1b9d45 5793 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
mbed_official 400:7fa56b1b9d45 5794 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
mbed_official 400:7fa56b1b9d45 5795 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
mbed_official 400:7fa56b1b9d45 5796 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
mbed_official 400:7fa56b1b9d45 5797 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
mbed_official 400:7fa56b1b9d45 5798 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
mbed_official 400:7fa56b1b9d45 5799 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
mbed_official 400:7fa56b1b9d45 5800 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
mbed_official 400:7fa56b1b9d45 5801 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
mbed_official 400:7fa56b1b9d45 5802
mbed_official 400:7fa56b1b9d45 5803 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 400:7fa56b1b9d45 5804 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
mbed_official 400:7fa56b1b9d45 5805 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
mbed_official 400:7fa56b1b9d45 5806 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
mbed_official 400:7fa56b1b9d45 5807 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
mbed_official 400:7fa56b1b9d45 5808 /**
mbed_official 400:7fa56b1b9d45 5809 * @brief EXTI4 configuration
mbed_official 400:7fa56b1b9d45 5810 */
mbed_official 400:7fa56b1b9d45 5811 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
mbed_official 400:7fa56b1b9d45 5812 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
mbed_official 400:7fa56b1b9d45 5813 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
mbed_official 400:7fa56b1b9d45 5814 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
mbed_official 400:7fa56b1b9d45 5815 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
mbed_official 400:7fa56b1b9d45 5816 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
mbed_official 400:7fa56b1b9d45 5817 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
mbed_official 400:7fa56b1b9d45 5818 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
mbed_official 400:7fa56b1b9d45 5819 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
mbed_official 400:7fa56b1b9d45 5820
mbed_official 400:7fa56b1b9d45 5821 /**
mbed_official 400:7fa56b1b9d45 5822 * @brief EXTI5 configuration
mbed_official 400:7fa56b1b9d45 5823 */
mbed_official 400:7fa56b1b9d45 5824 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
mbed_official 400:7fa56b1b9d45 5825 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
mbed_official 400:7fa56b1b9d45 5826 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
mbed_official 400:7fa56b1b9d45 5827 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
mbed_official 400:7fa56b1b9d45 5828 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
mbed_official 400:7fa56b1b9d45 5829 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
mbed_official 400:7fa56b1b9d45 5830 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
mbed_official 400:7fa56b1b9d45 5831 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
mbed_official 400:7fa56b1b9d45 5832 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
mbed_official 400:7fa56b1b9d45 5833
mbed_official 400:7fa56b1b9d45 5834 /**
mbed_official 400:7fa56b1b9d45 5835 * @brief EXTI6 configuration
mbed_official 400:7fa56b1b9d45 5836 */
mbed_official 400:7fa56b1b9d45 5837 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
mbed_official 400:7fa56b1b9d45 5838 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
mbed_official 400:7fa56b1b9d45 5839 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
mbed_official 400:7fa56b1b9d45 5840 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
mbed_official 400:7fa56b1b9d45 5841 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
mbed_official 400:7fa56b1b9d45 5842 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
mbed_official 400:7fa56b1b9d45 5843 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
mbed_official 400:7fa56b1b9d45 5844 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
mbed_official 400:7fa56b1b9d45 5845 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
mbed_official 400:7fa56b1b9d45 5846
mbed_official 400:7fa56b1b9d45 5847 /**
mbed_official 400:7fa56b1b9d45 5848 * @brief EXTI7 configuration
mbed_official 400:7fa56b1b9d45 5849 */
mbed_official 400:7fa56b1b9d45 5850 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
mbed_official 400:7fa56b1b9d45 5851 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
mbed_official 400:7fa56b1b9d45 5852 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
mbed_official 400:7fa56b1b9d45 5853 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
mbed_official 400:7fa56b1b9d45 5854 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
mbed_official 400:7fa56b1b9d45 5855 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
mbed_official 400:7fa56b1b9d45 5856 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
mbed_official 400:7fa56b1b9d45 5857 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
mbed_official 400:7fa56b1b9d45 5858 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
mbed_official 400:7fa56b1b9d45 5859
mbed_official 400:7fa56b1b9d45 5860
mbed_official 400:7fa56b1b9d45 5861 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 400:7fa56b1b9d45 5862 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
mbed_official 400:7fa56b1b9d45 5863 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
mbed_official 400:7fa56b1b9d45 5864 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
mbed_official 400:7fa56b1b9d45 5865 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
mbed_official 400:7fa56b1b9d45 5866
mbed_official 400:7fa56b1b9d45 5867 /**
mbed_official 400:7fa56b1b9d45 5868 * @brief EXTI8 configuration
mbed_official 400:7fa56b1b9d45 5869 */
mbed_official 400:7fa56b1b9d45 5870 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
mbed_official 400:7fa56b1b9d45 5871 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
mbed_official 400:7fa56b1b9d45 5872 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
mbed_official 400:7fa56b1b9d45 5873 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
mbed_official 400:7fa56b1b9d45 5874 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
mbed_official 400:7fa56b1b9d45 5875 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
mbed_official 400:7fa56b1b9d45 5876 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
mbed_official 400:7fa56b1b9d45 5877 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
mbed_official 400:7fa56b1b9d45 5878 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
mbed_official 400:7fa56b1b9d45 5879
mbed_official 400:7fa56b1b9d45 5880 /**
mbed_official 400:7fa56b1b9d45 5881 * @brief EXTI9 configuration
mbed_official 400:7fa56b1b9d45 5882 */
mbed_official 400:7fa56b1b9d45 5883 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
mbed_official 400:7fa56b1b9d45 5884 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
mbed_official 400:7fa56b1b9d45 5885 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
mbed_official 400:7fa56b1b9d45 5886 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
mbed_official 400:7fa56b1b9d45 5887 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
mbed_official 400:7fa56b1b9d45 5888 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
mbed_official 400:7fa56b1b9d45 5889 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
mbed_official 400:7fa56b1b9d45 5890 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
mbed_official 400:7fa56b1b9d45 5891 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
mbed_official 400:7fa56b1b9d45 5892
mbed_official 400:7fa56b1b9d45 5893 /**
mbed_official 400:7fa56b1b9d45 5894 * @brief EXTI10 configuration
mbed_official 400:7fa56b1b9d45 5895 */
mbed_official 400:7fa56b1b9d45 5896 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
mbed_official 400:7fa56b1b9d45 5897 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
mbed_official 400:7fa56b1b9d45 5898 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
mbed_official 400:7fa56b1b9d45 5899 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
mbed_official 400:7fa56b1b9d45 5900 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
mbed_official 400:7fa56b1b9d45 5901 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
mbed_official 400:7fa56b1b9d45 5902 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
mbed_official 400:7fa56b1b9d45 5903 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
mbed_official 400:7fa56b1b9d45 5904 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
mbed_official 400:7fa56b1b9d45 5905
mbed_official 400:7fa56b1b9d45 5906 /**
mbed_official 400:7fa56b1b9d45 5907 * @brief EXTI11 configuration
mbed_official 400:7fa56b1b9d45 5908 */
mbed_official 400:7fa56b1b9d45 5909 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
mbed_official 400:7fa56b1b9d45 5910 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
mbed_official 400:7fa56b1b9d45 5911 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
mbed_official 400:7fa56b1b9d45 5912 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
mbed_official 400:7fa56b1b9d45 5913 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
mbed_official 400:7fa56b1b9d45 5914 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
mbed_official 400:7fa56b1b9d45 5915 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
mbed_official 400:7fa56b1b9d45 5916 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
mbed_official 400:7fa56b1b9d45 5917 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
mbed_official 400:7fa56b1b9d45 5918
mbed_official 400:7fa56b1b9d45 5919 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official 400:7fa56b1b9d45 5920 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
mbed_official 400:7fa56b1b9d45 5921 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
mbed_official 400:7fa56b1b9d45 5922 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
mbed_official 400:7fa56b1b9d45 5923 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
mbed_official 400:7fa56b1b9d45 5924 /**
mbed_official 400:7fa56b1b9d45 5925 * @brief EXTI12 configuration
mbed_official 400:7fa56b1b9d45 5926 */
mbed_official 400:7fa56b1b9d45 5927 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
mbed_official 400:7fa56b1b9d45 5928 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
mbed_official 400:7fa56b1b9d45 5929 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
mbed_official 400:7fa56b1b9d45 5930 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
mbed_official 400:7fa56b1b9d45 5931 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
mbed_official 400:7fa56b1b9d45 5932 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
mbed_official 400:7fa56b1b9d45 5933 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
mbed_official 400:7fa56b1b9d45 5934 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
mbed_official 400:7fa56b1b9d45 5935
mbed_official 400:7fa56b1b9d45 5936 /**
mbed_official 400:7fa56b1b9d45 5937 * @brief EXTI13 configuration
mbed_official 400:7fa56b1b9d45 5938 */
mbed_official 400:7fa56b1b9d45 5939 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
mbed_official 400:7fa56b1b9d45 5940 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
mbed_official 400:7fa56b1b9d45 5941 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
mbed_official 400:7fa56b1b9d45 5942 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
mbed_official 400:7fa56b1b9d45 5943 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
mbed_official 400:7fa56b1b9d45 5944 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
mbed_official 400:7fa56b1b9d45 5945 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
mbed_official 400:7fa56b1b9d45 5946 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
mbed_official 400:7fa56b1b9d45 5947
mbed_official 400:7fa56b1b9d45 5948 /**
mbed_official 400:7fa56b1b9d45 5949 * @brief EXTI14 configuration
mbed_official 400:7fa56b1b9d45 5950 */
mbed_official 400:7fa56b1b9d45 5951 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
mbed_official 400:7fa56b1b9d45 5952 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
mbed_official 400:7fa56b1b9d45 5953 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
mbed_official 400:7fa56b1b9d45 5954 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
mbed_official 400:7fa56b1b9d45 5955 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
mbed_official 400:7fa56b1b9d45 5956 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
mbed_official 400:7fa56b1b9d45 5957 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
mbed_official 400:7fa56b1b9d45 5958 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
mbed_official 400:7fa56b1b9d45 5959
mbed_official 400:7fa56b1b9d45 5960 /**
mbed_official 400:7fa56b1b9d45 5961 * @brief EXTI15 configuration
mbed_official 400:7fa56b1b9d45 5962 */
mbed_official 400:7fa56b1b9d45 5963 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
mbed_official 400:7fa56b1b9d45 5964 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
mbed_official 400:7fa56b1b9d45 5965 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
mbed_official 400:7fa56b1b9d45 5966 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
mbed_official 400:7fa56b1b9d45 5967 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
mbed_official 400:7fa56b1b9d45 5968 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
mbed_official 400:7fa56b1b9d45 5969 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
mbed_official 400:7fa56b1b9d45 5970 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
mbed_official 400:7fa56b1b9d45 5971
mbed_official 400:7fa56b1b9d45 5972 /****************** Bit definition for SYSCFG_CMPCR register ****************/
mbed_official 400:7fa56b1b9d45 5973 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
mbed_official 400:7fa56b1b9d45 5974 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
mbed_official 400:7fa56b1b9d45 5975
mbed_official 400:7fa56b1b9d45 5976 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5977 /* */
mbed_official 400:7fa56b1b9d45 5978 /* TIM */
mbed_official 400:7fa56b1b9d45 5979 /* */
mbed_official 400:7fa56b1b9d45 5980 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 5981 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 400:7fa56b1b9d45 5982 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
mbed_official 400:7fa56b1b9d45 5983 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
mbed_official 400:7fa56b1b9d45 5984 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
mbed_official 400:7fa56b1b9d45 5985 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
mbed_official 400:7fa56b1b9d45 5986 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
mbed_official 400:7fa56b1b9d45 5987
mbed_official 400:7fa56b1b9d45 5988 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 400:7fa56b1b9d45 5989 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5990 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5991
mbed_official 400:7fa56b1b9d45 5992 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 400:7fa56b1b9d45 5993
mbed_official 400:7fa56b1b9d45 5994 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 400:7fa56b1b9d45 5995 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 5996 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 5997
mbed_official 400:7fa56b1b9d45 5998 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 400:7fa56b1b9d45 5999 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
mbed_official 400:7fa56b1b9d45 6000 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
mbed_official 400:7fa56b1b9d45 6001 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
mbed_official 400:7fa56b1b9d45 6002
mbed_official 400:7fa56b1b9d45 6003 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 400:7fa56b1b9d45 6004 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6005 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6006 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6007
mbed_official 400:7fa56b1b9d45 6008 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
mbed_official 400:7fa56b1b9d45 6009 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 400:7fa56b1b9d45 6010 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 400:7fa56b1b9d45 6011 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 400:7fa56b1b9d45 6012 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 400:7fa56b1b9d45 6013 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 400:7fa56b1b9d45 6014 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 400:7fa56b1b9d45 6015 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 400:7fa56b1b9d45 6016
mbed_official 400:7fa56b1b9d45 6017 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 400:7fa56b1b9d45 6018 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 400:7fa56b1b9d45 6019 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6020 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6021 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6022
mbed_official 400:7fa56b1b9d45 6023 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 400:7fa56b1b9d45 6024 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6025 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6026 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6027
mbed_official 400:7fa56b1b9d45 6028 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
mbed_official 400:7fa56b1b9d45 6029
mbed_official 400:7fa56b1b9d45 6030 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 400:7fa56b1b9d45 6031 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6032 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6033 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6034 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6035
mbed_official 400:7fa56b1b9d45 6036 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 400:7fa56b1b9d45 6037 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6038 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6039
mbed_official 400:7fa56b1b9d45 6040 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
mbed_official 400:7fa56b1b9d45 6041 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
mbed_official 400:7fa56b1b9d45 6042
mbed_official 400:7fa56b1b9d45 6043 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 400:7fa56b1b9d45 6044 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
mbed_official 400:7fa56b1b9d45 6045 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 400:7fa56b1b9d45 6046 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 400:7fa56b1b9d45 6047 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 400:7fa56b1b9d45 6048 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 400:7fa56b1b9d45 6049 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
mbed_official 400:7fa56b1b9d45 6050 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 400:7fa56b1b9d45 6051 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
mbed_official 400:7fa56b1b9d45 6052 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
mbed_official 400:7fa56b1b9d45 6053 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 400:7fa56b1b9d45 6054 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 400:7fa56b1b9d45 6055 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 400:7fa56b1b9d45 6056 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 400:7fa56b1b9d45 6057 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
mbed_official 400:7fa56b1b9d45 6058 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 400:7fa56b1b9d45 6059
mbed_official 400:7fa56b1b9d45 6060 /******************** Bit definition for TIM_SR register ********************/
mbed_official 400:7fa56b1b9d45 6061 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
mbed_official 400:7fa56b1b9d45 6062 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 400:7fa56b1b9d45 6063 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 400:7fa56b1b9d45 6064 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 400:7fa56b1b9d45 6065 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 400:7fa56b1b9d45 6066 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
mbed_official 400:7fa56b1b9d45 6067 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 400:7fa56b1b9d45 6068 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
mbed_official 400:7fa56b1b9d45 6069 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 400:7fa56b1b9d45 6070 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 400:7fa56b1b9d45 6071 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 400:7fa56b1b9d45 6072 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 400:7fa56b1b9d45 6073
mbed_official 400:7fa56b1b9d45 6074 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 400:7fa56b1b9d45 6075 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
mbed_official 400:7fa56b1b9d45 6076 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
mbed_official 400:7fa56b1b9d45 6077 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
mbed_official 400:7fa56b1b9d45 6078 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
mbed_official 400:7fa56b1b9d45 6079 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
mbed_official 400:7fa56b1b9d45 6080 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
mbed_official 400:7fa56b1b9d45 6081 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
mbed_official 400:7fa56b1b9d45 6082 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
mbed_official 400:7fa56b1b9d45 6083
mbed_official 400:7fa56b1b9d45 6084 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 400:7fa56b1b9d45 6085 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 400:7fa56b1b9d45 6086 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6087 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6088
mbed_official 400:7fa56b1b9d45 6089 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
mbed_official 400:7fa56b1b9d45 6090 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
mbed_official 400:7fa56b1b9d45 6091
mbed_official 400:7fa56b1b9d45 6092 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 400:7fa56b1b9d45 6093 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6094 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6095 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6096
mbed_official 400:7fa56b1b9d45 6097 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
mbed_official 400:7fa56b1b9d45 6098
mbed_official 400:7fa56b1b9d45 6099 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 400:7fa56b1b9d45 6100 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6101 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6102
mbed_official 400:7fa56b1b9d45 6103 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
mbed_official 400:7fa56b1b9d45 6104 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
mbed_official 400:7fa56b1b9d45 6105
mbed_official 400:7fa56b1b9d45 6106 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 400:7fa56b1b9d45 6107 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6108 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6109 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6110
mbed_official 400:7fa56b1b9d45 6111 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
mbed_official 400:7fa56b1b9d45 6112
mbed_official 400:7fa56b1b9d45 6113 /*----------------------------------------------------------------------------*/
mbed_official 400:7fa56b1b9d45 6114
mbed_official 400:7fa56b1b9d45 6115 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 400:7fa56b1b9d45 6116 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6117 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6118
mbed_official 400:7fa56b1b9d45 6119 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 400:7fa56b1b9d45 6120 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6121 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6122 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6123 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6124
mbed_official 400:7fa56b1b9d45 6125 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 400:7fa56b1b9d45 6126 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6127 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6128
mbed_official 400:7fa56b1b9d45 6129 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 400:7fa56b1b9d45 6130 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6131 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6132 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6133 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6134
mbed_official 400:7fa56b1b9d45 6135 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 400:7fa56b1b9d45 6136 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 400:7fa56b1b9d45 6137 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6138 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6139
mbed_official 400:7fa56b1b9d45 6140 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
mbed_official 400:7fa56b1b9d45 6141 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
mbed_official 400:7fa56b1b9d45 6142
mbed_official 400:7fa56b1b9d45 6143 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 400:7fa56b1b9d45 6144 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6145 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6146 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6147
mbed_official 400:7fa56b1b9d45 6148 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
mbed_official 400:7fa56b1b9d45 6149
mbed_official 400:7fa56b1b9d45 6150 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 400:7fa56b1b9d45 6151 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6152 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6153
mbed_official 400:7fa56b1b9d45 6154 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
mbed_official 400:7fa56b1b9d45 6155 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
mbed_official 400:7fa56b1b9d45 6156
mbed_official 400:7fa56b1b9d45 6157 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 400:7fa56b1b9d45 6158 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6159 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6160 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6161
mbed_official 400:7fa56b1b9d45 6162 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 400:7fa56b1b9d45 6163
mbed_official 400:7fa56b1b9d45 6164 /*----------------------------------------------------------------------------*/
mbed_official 400:7fa56b1b9d45 6165
mbed_official 400:7fa56b1b9d45 6166 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 400:7fa56b1b9d45 6167 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6168 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6169
mbed_official 400:7fa56b1b9d45 6170 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 400:7fa56b1b9d45 6171 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6172 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6173 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6174 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6175
mbed_official 400:7fa56b1b9d45 6176 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 400:7fa56b1b9d45 6177 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6178 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6179
mbed_official 400:7fa56b1b9d45 6180 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 400:7fa56b1b9d45 6181 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6182 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6183 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6184 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6185
mbed_official 400:7fa56b1b9d45 6186 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 400:7fa56b1b9d45 6187 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
mbed_official 400:7fa56b1b9d45 6188 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
mbed_official 400:7fa56b1b9d45 6189 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 400:7fa56b1b9d45 6190 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 400:7fa56b1b9d45 6191 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
mbed_official 400:7fa56b1b9d45 6192 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
mbed_official 400:7fa56b1b9d45 6193 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 400:7fa56b1b9d45 6194 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 400:7fa56b1b9d45 6195 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
mbed_official 400:7fa56b1b9d45 6196 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
mbed_official 400:7fa56b1b9d45 6197 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 400:7fa56b1b9d45 6198 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 400:7fa56b1b9d45 6199 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
mbed_official 400:7fa56b1b9d45 6200 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
mbed_official 400:7fa56b1b9d45 6201 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 400:7fa56b1b9d45 6202
mbed_official 400:7fa56b1b9d45 6203 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 400:7fa56b1b9d45 6204 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
mbed_official 400:7fa56b1b9d45 6205
mbed_official 400:7fa56b1b9d45 6206 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 400:7fa56b1b9d45 6207 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
mbed_official 400:7fa56b1b9d45 6208
mbed_official 400:7fa56b1b9d45 6209 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 400:7fa56b1b9d45 6210 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 400:7fa56b1b9d45 6211
mbed_official 400:7fa56b1b9d45 6212 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 400:7fa56b1b9d45 6213 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
mbed_official 400:7fa56b1b9d45 6214
mbed_official 400:7fa56b1b9d45 6215 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 400:7fa56b1b9d45 6216 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 400:7fa56b1b9d45 6217
mbed_official 400:7fa56b1b9d45 6218 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 400:7fa56b1b9d45 6219 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 400:7fa56b1b9d45 6220
mbed_official 400:7fa56b1b9d45 6221 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 400:7fa56b1b9d45 6222 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 400:7fa56b1b9d45 6223
mbed_official 400:7fa56b1b9d45 6224 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 400:7fa56b1b9d45 6225 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 400:7fa56b1b9d45 6226
mbed_official 400:7fa56b1b9d45 6227 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 400:7fa56b1b9d45 6228 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 400:7fa56b1b9d45 6229 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6230 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6231 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6232 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6233 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6234 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6235 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6236 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 6237
mbed_official 400:7fa56b1b9d45 6238 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 400:7fa56b1b9d45 6239 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6240 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6241
mbed_official 400:7fa56b1b9d45 6242 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
mbed_official 400:7fa56b1b9d45 6243 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
mbed_official 400:7fa56b1b9d45 6244 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
mbed_official 400:7fa56b1b9d45 6245 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
mbed_official 400:7fa56b1b9d45 6246 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
mbed_official 400:7fa56b1b9d45 6247 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
mbed_official 400:7fa56b1b9d45 6248
mbed_official 400:7fa56b1b9d45 6249 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 400:7fa56b1b9d45 6250 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 400:7fa56b1b9d45 6251 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6252 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6253 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6254 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6255 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6256
mbed_official 400:7fa56b1b9d45 6257 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 400:7fa56b1b9d45 6258 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6259 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6260 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6261 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6262 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6263
mbed_official 400:7fa56b1b9d45 6264 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 400:7fa56b1b9d45 6265 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 400:7fa56b1b9d45 6266
mbed_official 400:7fa56b1b9d45 6267 /******************* Bit definition for TIM_OR register *********************/
mbed_official 400:7fa56b1b9d45 6268 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
mbed_official 400:7fa56b1b9d45 6269 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6270 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6271 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
mbed_official 400:7fa56b1b9d45 6272 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6273 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6274
mbed_official 400:7fa56b1b9d45 6275
mbed_official 400:7fa56b1b9d45 6276 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 6277 /* */
mbed_official 400:7fa56b1b9d45 6278 /* Universal Synchronous Asynchronous Receiver Transmitter */
mbed_official 400:7fa56b1b9d45 6279 /* */
mbed_official 400:7fa56b1b9d45 6280 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 6281 /******************* Bit definition for USART_SR register *******************/
mbed_official 400:7fa56b1b9d45 6282 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
mbed_official 400:7fa56b1b9d45 6283 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
mbed_official 400:7fa56b1b9d45 6284 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
mbed_official 400:7fa56b1b9d45 6285 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
mbed_official 400:7fa56b1b9d45 6286 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
mbed_official 400:7fa56b1b9d45 6287 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
mbed_official 400:7fa56b1b9d45 6288 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
mbed_official 400:7fa56b1b9d45 6289 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
mbed_official 400:7fa56b1b9d45 6290 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
mbed_official 400:7fa56b1b9d45 6291 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
mbed_official 400:7fa56b1b9d45 6292
mbed_official 400:7fa56b1b9d45 6293 /******************* Bit definition for USART_DR register *******************/
mbed_official 400:7fa56b1b9d45 6294 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
mbed_official 400:7fa56b1b9d45 6295
mbed_official 400:7fa56b1b9d45 6296 /****************** Bit definition for USART_BRR register *******************/
mbed_official 400:7fa56b1b9d45 6297 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
mbed_official 400:7fa56b1b9d45 6298 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
mbed_official 400:7fa56b1b9d45 6299
mbed_official 400:7fa56b1b9d45 6300 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 400:7fa56b1b9d45 6301 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
mbed_official 400:7fa56b1b9d45 6302 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
mbed_official 400:7fa56b1b9d45 6303 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
mbed_official 400:7fa56b1b9d45 6304 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
mbed_official 400:7fa56b1b9d45 6305 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
mbed_official 400:7fa56b1b9d45 6306 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
mbed_official 400:7fa56b1b9d45 6307 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
mbed_official 400:7fa56b1b9d45 6308 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
mbed_official 400:7fa56b1b9d45 6309 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
mbed_official 400:7fa56b1b9d45 6310 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
mbed_official 400:7fa56b1b9d45 6311 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
mbed_official 400:7fa56b1b9d45 6312 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
mbed_official 400:7fa56b1b9d45 6313 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
mbed_official 400:7fa56b1b9d45 6314 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
mbed_official 400:7fa56b1b9d45 6315 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
mbed_official 400:7fa56b1b9d45 6316
mbed_official 400:7fa56b1b9d45 6317 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 400:7fa56b1b9d45 6318 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
mbed_official 400:7fa56b1b9d45 6319 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
mbed_official 400:7fa56b1b9d45 6320 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
mbed_official 400:7fa56b1b9d45 6321 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
mbed_official 400:7fa56b1b9d45 6322 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
mbed_official 400:7fa56b1b9d45 6323 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
mbed_official 400:7fa56b1b9d45 6324 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
mbed_official 400:7fa56b1b9d45 6325
mbed_official 400:7fa56b1b9d45 6326 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
mbed_official 400:7fa56b1b9d45 6327 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6328 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6329
mbed_official 400:7fa56b1b9d45 6330 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
mbed_official 400:7fa56b1b9d45 6331
mbed_official 400:7fa56b1b9d45 6332 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 400:7fa56b1b9d45 6333 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
mbed_official 400:7fa56b1b9d45 6334 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
mbed_official 400:7fa56b1b9d45 6335 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
mbed_official 400:7fa56b1b9d45 6336 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
mbed_official 400:7fa56b1b9d45 6337 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
mbed_official 400:7fa56b1b9d45 6338 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
mbed_official 400:7fa56b1b9d45 6339 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
mbed_official 400:7fa56b1b9d45 6340 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
mbed_official 400:7fa56b1b9d45 6341 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
mbed_official 400:7fa56b1b9d45 6342 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
mbed_official 400:7fa56b1b9d45 6343 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
mbed_official 400:7fa56b1b9d45 6344 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
mbed_official 400:7fa56b1b9d45 6345
mbed_official 400:7fa56b1b9d45 6346 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 400:7fa56b1b9d45 6347 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
mbed_official 400:7fa56b1b9d45 6348 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6349 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6350 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6351 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6352 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6353 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6354 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6355 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 6356
mbed_official 400:7fa56b1b9d45 6357 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
mbed_official 400:7fa56b1b9d45 6358
mbed_official 400:7fa56b1b9d45 6359 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 6360 /* */
mbed_official 400:7fa56b1b9d45 6361 /* Window WATCHDOG */
mbed_official 400:7fa56b1b9d45 6362 /* */
mbed_official 400:7fa56b1b9d45 6363 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 6364 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 400:7fa56b1b9d45 6365 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 400:7fa56b1b9d45 6366 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6367 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6368 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6369 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6370 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6371 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6372 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6373
mbed_official 400:7fa56b1b9d45 6374 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 400:7fa56b1b9d45 6375
mbed_official 400:7fa56b1b9d45 6376 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 400:7fa56b1b9d45 6377 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 400:7fa56b1b9d45 6378 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6379 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6380 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6381 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6382 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6383 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6384 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6385
mbed_official 400:7fa56b1b9d45 6386 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 400:7fa56b1b9d45 6387 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6388 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6389
mbed_official 400:7fa56b1b9d45 6390 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 400:7fa56b1b9d45 6391
mbed_official 400:7fa56b1b9d45 6392 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 400:7fa56b1b9d45 6393 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 400:7fa56b1b9d45 6394
mbed_official 400:7fa56b1b9d45 6395
mbed_official 400:7fa56b1b9d45 6396 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 6397 /* */
mbed_official 400:7fa56b1b9d45 6398 /* DBG */
mbed_official 400:7fa56b1b9d45 6399 /* */
mbed_official 400:7fa56b1b9d45 6400 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 6401 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 400:7fa56b1b9d45 6402 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 400:7fa56b1b9d45 6403 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 400:7fa56b1b9d45 6404
mbed_official 400:7fa56b1b9d45 6405 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 400:7fa56b1b9d45 6406 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 6407 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 6408 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 6409 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 6410
mbed_official 400:7fa56b1b9d45 6411 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 400:7fa56b1b9d45 6412 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6413 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6414
mbed_official 400:7fa56b1b9d45 6415 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 400:7fa56b1b9d45 6416 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 6417 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 6418 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 400:7fa56b1b9d45 6419 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
mbed_official 400:7fa56b1b9d45 6420 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 400:7fa56b1b9d45 6421 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 400:7fa56b1b9d45 6422 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
mbed_official 400:7fa56b1b9d45 6423 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
mbed_official 400:7fa56b1b9d45 6424 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
mbed_official 400:7fa56b1b9d45 6425 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 400:7fa56b1b9d45 6426 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 400:7fa56b1b9d45 6427 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 400:7fa56b1b9d45 6428 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 400:7fa56b1b9d45 6429 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 400:7fa56b1b9d45 6430 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
mbed_official 400:7fa56b1b9d45 6431 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
mbed_official 400:7fa56b1b9d45 6432 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
mbed_official 400:7fa56b1b9d45 6433 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
mbed_official 400:7fa56b1b9d45 6434 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
mbed_official 400:7fa56b1b9d45 6435
mbed_official 400:7fa56b1b9d45 6436 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 400:7fa56b1b9d45 6437 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 400:7fa56b1b9d45 6438 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 400:7fa56b1b9d45 6439 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
mbed_official 400:7fa56b1b9d45 6440 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
mbed_official 400:7fa56b1b9d45 6441 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
mbed_official 400:7fa56b1b9d45 6442
mbed_official 400:7fa56b1b9d45 6443 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 6444 /* */
mbed_official 400:7fa56b1b9d45 6445 /* USB_OTG */
mbed_official 400:7fa56b1b9d45 6446 /* */
mbed_official 400:7fa56b1b9d45 6447 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 6448 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
mbed_official 400:7fa56b1b9d45 6449 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
mbed_official 400:7fa56b1b9d45 6450 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
mbed_official 400:7fa56b1b9d45 6451 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
mbed_official 400:7fa56b1b9d45 6452 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
mbed_official 400:7fa56b1b9d45 6453 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
mbed_official 400:7fa56b1b9d45 6454 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
mbed_official 400:7fa56b1b9d45 6455 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
mbed_official 400:7fa56b1b9d45 6456 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
mbed_official 400:7fa56b1b9d45 6457 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
mbed_official 400:7fa56b1b9d45 6458 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
mbed_official 400:7fa56b1b9d45 6459
mbed_official 400:7fa56b1b9d45 6460 /******************** Bit definition forUSB_OTG_HCFG register ********************/
mbed_official 400:7fa56b1b9d45 6461
mbed_official 400:7fa56b1b9d45 6462 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
mbed_official 400:7fa56b1b9d45 6463 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6464 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6465 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
mbed_official 400:7fa56b1b9d45 6466
mbed_official 400:7fa56b1b9d45 6467 /******************** Bit definition forUSB_OTG_DCFG register ********************/
mbed_official 400:7fa56b1b9d45 6468
mbed_official 400:7fa56b1b9d45 6469 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
mbed_official 400:7fa56b1b9d45 6470 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6471 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6472 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
mbed_official 400:7fa56b1b9d45 6473
mbed_official 400:7fa56b1b9d45 6474 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
mbed_official 400:7fa56b1b9d45 6475 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6476 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6477 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6478 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6479 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6480 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6481 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6482
mbed_official 400:7fa56b1b9d45 6483 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
mbed_official 400:7fa56b1b9d45 6484 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6485 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6486
mbed_official 400:7fa56b1b9d45 6487 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
mbed_official 400:7fa56b1b9d45 6488 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6489 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6490
mbed_official 400:7fa56b1b9d45 6491 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
mbed_official 400:7fa56b1b9d45 6492 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
mbed_official 400:7fa56b1b9d45 6493 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
mbed_official 400:7fa56b1b9d45 6494 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
mbed_official 400:7fa56b1b9d45 6495
mbed_official 400:7fa56b1b9d45 6496 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
mbed_official 400:7fa56b1b9d45 6497 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
mbed_official 400:7fa56b1b9d45 6498 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
mbed_official 400:7fa56b1b9d45 6499 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
mbed_official 400:7fa56b1b9d45 6500 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
mbed_official 400:7fa56b1b9d45 6501 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
mbed_official 400:7fa56b1b9d45 6502 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
mbed_official 400:7fa56b1b9d45 6503
mbed_official 400:7fa56b1b9d45 6504 /******************** Bit definition forUSB_OTG_DCTL register ********************/
mbed_official 400:7fa56b1b9d45 6505 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
mbed_official 400:7fa56b1b9d45 6506 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
mbed_official 400:7fa56b1b9d45 6507 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
mbed_official 400:7fa56b1b9d45 6508 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
mbed_official 400:7fa56b1b9d45 6509
mbed_official 400:7fa56b1b9d45 6510 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
mbed_official 400:7fa56b1b9d45 6511 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6512 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6513 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6514 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
mbed_official 400:7fa56b1b9d45 6515 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
mbed_official 400:7fa56b1b9d45 6516 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
mbed_official 400:7fa56b1b9d45 6517 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
mbed_official 400:7fa56b1b9d45 6518 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
mbed_official 400:7fa56b1b9d45 6519
mbed_official 400:7fa56b1b9d45 6520 /******************** Bit definition forUSB_OTG_HFIR register ********************/
mbed_official 400:7fa56b1b9d45 6521 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
mbed_official 400:7fa56b1b9d45 6522
mbed_official 400:7fa56b1b9d45 6523 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
mbed_official 400:7fa56b1b9d45 6524 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
mbed_official 400:7fa56b1b9d45 6525 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
mbed_official 400:7fa56b1b9d45 6526
mbed_official 400:7fa56b1b9d45 6527 /******************** Bit definition forUSB_OTG_DSTS register ********************/
mbed_official 400:7fa56b1b9d45 6528 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
mbed_official 400:7fa56b1b9d45 6529
mbed_official 400:7fa56b1b9d45 6530 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
mbed_official 400:7fa56b1b9d45 6531 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6532 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6533 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
mbed_official 400:7fa56b1b9d45 6534 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
mbed_official 400:7fa56b1b9d45 6535
mbed_official 400:7fa56b1b9d45 6536 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
mbed_official 400:7fa56b1b9d45 6537 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
mbed_official 400:7fa56b1b9d45 6538
mbed_official 400:7fa56b1b9d45 6539 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
mbed_official 400:7fa56b1b9d45 6540 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6541 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6542 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6543 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6544 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
mbed_official 400:7fa56b1b9d45 6545 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
mbed_official 400:7fa56b1b9d45 6546 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
mbed_official 400:7fa56b1b9d45 6547
mbed_official 400:7fa56b1b9d45 6548 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
mbed_official 400:7fa56b1b9d45 6549
mbed_official 400:7fa56b1b9d45 6550 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
mbed_official 400:7fa56b1b9d45 6551 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6552 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6553 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6554 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
mbed_official 400:7fa56b1b9d45 6555 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
mbed_official 400:7fa56b1b9d45 6556 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
mbed_official 400:7fa56b1b9d45 6557
mbed_official 400:7fa56b1b9d45 6558 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
mbed_official 400:7fa56b1b9d45 6559 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6560 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6561 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6562 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6563 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
mbed_official 400:7fa56b1b9d45 6564 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
mbed_official 400:7fa56b1b9d45 6565 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
mbed_official 400:7fa56b1b9d45 6566 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
mbed_official 400:7fa56b1b9d45 6567 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
mbed_official 400:7fa56b1b9d45 6568 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
mbed_official 400:7fa56b1b9d45 6569 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
mbed_official 400:7fa56b1b9d45 6570 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
mbed_official 400:7fa56b1b9d45 6571 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
mbed_official 400:7fa56b1b9d45 6572 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
mbed_official 400:7fa56b1b9d45 6573 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
mbed_official 400:7fa56b1b9d45 6574 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
mbed_official 400:7fa56b1b9d45 6575 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
mbed_official 400:7fa56b1b9d45 6576
mbed_official 400:7fa56b1b9d45 6577 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
mbed_official 400:7fa56b1b9d45 6578 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
mbed_official 400:7fa56b1b9d45 6579 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
mbed_official 400:7fa56b1b9d45 6580 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
mbed_official 400:7fa56b1b9d45 6581 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
mbed_official 400:7fa56b1b9d45 6582 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
mbed_official 400:7fa56b1b9d45 6583
mbed_official 400:7fa56b1b9d45 6584 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
mbed_official 400:7fa56b1b9d45 6585 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6586 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6587 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6588 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6589 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6590 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
mbed_official 400:7fa56b1b9d45 6591 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
mbed_official 400:7fa56b1b9d45 6592
mbed_official 400:7fa56b1b9d45 6593 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
mbed_official 400:7fa56b1b9d45 6594 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 400:7fa56b1b9d45 6595 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 400:7fa56b1b9d45 6596 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 400:7fa56b1b9d45 6597 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 400:7fa56b1b9d45 6598 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 400:7fa56b1b9d45 6599 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 400:7fa56b1b9d45 6600 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 400:7fa56b1b9d45 6601 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 400:7fa56b1b9d45 6602
mbed_official 400:7fa56b1b9d45 6603 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
mbed_official 400:7fa56b1b9d45 6604 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
mbed_official 400:7fa56b1b9d45 6605
mbed_official 400:7fa56b1b9d45 6606 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
mbed_official 400:7fa56b1b9d45 6607 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6608 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6609 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6610 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6611 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6612 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6613 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6614 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 6615
mbed_official 400:7fa56b1b9d45 6616 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
mbed_official 400:7fa56b1b9d45 6617 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6618 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6619 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6620 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6621 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6622 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6623 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6624 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 6625
mbed_official 400:7fa56b1b9d45 6626 /******************** Bit definition forUSB_OTG_HAINT register ********************/
mbed_official 400:7fa56b1b9d45 6627 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
mbed_official 400:7fa56b1b9d45 6628
mbed_official 400:7fa56b1b9d45 6629 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
mbed_official 400:7fa56b1b9d45 6630 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 400:7fa56b1b9d45 6631 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 400:7fa56b1b9d45 6632 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
mbed_official 400:7fa56b1b9d45 6633 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
mbed_official 400:7fa56b1b9d45 6634 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
mbed_official 400:7fa56b1b9d45 6635 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 400:7fa56b1b9d45 6636 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 400:7fa56b1b9d45 6637
mbed_official 400:7fa56b1b9d45 6638 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
mbed_official 400:7fa56b1b9d45 6639 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
mbed_official 400:7fa56b1b9d45 6640 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
mbed_official 400:7fa56b1b9d45 6641 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
mbed_official 400:7fa56b1b9d45 6642 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
mbed_official 400:7fa56b1b9d45 6643 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
mbed_official 400:7fa56b1b9d45 6644 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
mbed_official 400:7fa56b1b9d45 6645 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
mbed_official 400:7fa56b1b9d45 6646 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
mbed_official 400:7fa56b1b9d45 6647 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
mbed_official 400:7fa56b1b9d45 6648 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
mbed_official 400:7fa56b1b9d45 6649 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
mbed_official 400:7fa56b1b9d45 6650 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
mbed_official 400:7fa56b1b9d45 6651 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
mbed_official 400:7fa56b1b9d45 6652 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
mbed_official 400:7fa56b1b9d45 6653 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
mbed_official 400:7fa56b1b9d45 6654 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
mbed_official 400:7fa56b1b9d45 6655 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
mbed_official 400:7fa56b1b9d45 6656 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
mbed_official 400:7fa56b1b9d45 6657 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
mbed_official 400:7fa56b1b9d45 6658 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
mbed_official 400:7fa56b1b9d45 6659 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
mbed_official 400:7fa56b1b9d45 6660 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
mbed_official 400:7fa56b1b9d45 6661 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
mbed_official 400:7fa56b1b9d45 6662 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
mbed_official 400:7fa56b1b9d45 6663 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
mbed_official 400:7fa56b1b9d45 6664 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
mbed_official 400:7fa56b1b9d45 6665
mbed_official 400:7fa56b1b9d45 6666 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
mbed_official 400:7fa56b1b9d45 6667 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
mbed_official 400:7fa56b1b9d45 6668 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
mbed_official 400:7fa56b1b9d45 6669 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
mbed_official 400:7fa56b1b9d45 6670 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
mbed_official 400:7fa56b1b9d45 6671 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
mbed_official 400:7fa56b1b9d45 6672 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
mbed_official 400:7fa56b1b9d45 6673 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
mbed_official 400:7fa56b1b9d45 6674 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
mbed_official 400:7fa56b1b9d45 6675 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
mbed_official 400:7fa56b1b9d45 6676 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
mbed_official 400:7fa56b1b9d45 6677 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
mbed_official 400:7fa56b1b9d45 6678 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
mbed_official 400:7fa56b1b9d45 6679 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
mbed_official 400:7fa56b1b9d45 6680 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
mbed_official 400:7fa56b1b9d45 6681 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
mbed_official 400:7fa56b1b9d45 6682 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
mbed_official 400:7fa56b1b9d45 6683 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
mbed_official 400:7fa56b1b9d45 6684 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
mbed_official 400:7fa56b1b9d45 6685 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
mbed_official 400:7fa56b1b9d45 6686 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
mbed_official 400:7fa56b1b9d45 6687 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
mbed_official 400:7fa56b1b9d45 6688 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
mbed_official 400:7fa56b1b9d45 6689 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
mbed_official 400:7fa56b1b9d45 6690 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
mbed_official 400:7fa56b1b9d45 6691 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
mbed_official 400:7fa56b1b9d45 6692 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
mbed_official 400:7fa56b1b9d45 6693
mbed_official 400:7fa56b1b9d45 6694 /******************** Bit definition forUSB_OTG_DAINT register ********************/
mbed_official 400:7fa56b1b9d45 6695 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
mbed_official 400:7fa56b1b9d45 6696 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
mbed_official 400:7fa56b1b9d45 6697
mbed_official 400:7fa56b1b9d45 6698 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
mbed_official 400:7fa56b1b9d45 6699 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
mbed_official 400:7fa56b1b9d45 6700
mbed_official 400:7fa56b1b9d45 6701 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
mbed_official 400:7fa56b1b9d45 6702 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
mbed_official 400:7fa56b1b9d45 6703 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
mbed_official 400:7fa56b1b9d45 6704 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
mbed_official 400:7fa56b1b9d45 6705 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
mbed_official 400:7fa56b1b9d45 6706
mbed_official 400:7fa56b1b9d45 6707 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
mbed_official 400:7fa56b1b9d45 6708 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
mbed_official 400:7fa56b1b9d45 6709 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
mbed_official 400:7fa56b1b9d45 6710
mbed_official 400:7fa56b1b9d45 6711 /******************** Bit definition for OTG register ********************/
mbed_official 400:7fa56b1b9d45 6712
mbed_official 400:7fa56b1b9d45 6713 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 400:7fa56b1b9d45 6714 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6715 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6716 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6717 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6718 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 400:7fa56b1b9d45 6719
mbed_official 400:7fa56b1b9d45 6720 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 400:7fa56b1b9d45 6721 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6722 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6723
mbed_official 400:7fa56b1b9d45 6724 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 400:7fa56b1b9d45 6725 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6726 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6727 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6728 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6729
mbed_official 400:7fa56b1b9d45 6730 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 400:7fa56b1b9d45 6731 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6732 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6733 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6734 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6735
mbed_official 400:7fa56b1b9d45 6736 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 400:7fa56b1b9d45 6737 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6738 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6739 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6740 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6741
mbed_official 400:7fa56b1b9d45 6742 /******************** Bit definition for OTG register ********************/
mbed_official 400:7fa56b1b9d45 6743
mbed_official 400:7fa56b1b9d45 6744 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 400:7fa56b1b9d45 6745 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6746 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6747 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6748 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6749 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 400:7fa56b1b9d45 6750
mbed_official 400:7fa56b1b9d45 6751 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 400:7fa56b1b9d45 6752 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6753 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6754
mbed_official 400:7fa56b1b9d45 6755 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 400:7fa56b1b9d45 6756 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6757 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6758 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6759 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6760
mbed_official 400:7fa56b1b9d45 6761 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 400:7fa56b1b9d45 6762 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6763 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6764 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6765 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6766
mbed_official 400:7fa56b1b9d45 6767 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 400:7fa56b1b9d45 6768 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6769 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6770 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6771 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6772
mbed_official 400:7fa56b1b9d45 6773 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
mbed_official 400:7fa56b1b9d45 6774 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
mbed_official 400:7fa56b1b9d45 6775
mbed_official 400:7fa56b1b9d45 6776 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
mbed_official 400:7fa56b1b9d45 6777 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
mbed_official 400:7fa56b1b9d45 6778
mbed_official 400:7fa56b1b9d45 6779 /******************** Bit definition for OTG register ********************/
mbed_official 400:7fa56b1b9d45 6780 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
mbed_official 400:7fa56b1b9d45 6781 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
mbed_official 400:7fa56b1b9d45 6782 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
mbed_official 400:7fa56b1b9d45 6783 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
mbed_official 400:7fa56b1b9d45 6784
mbed_official 400:7fa56b1b9d45 6785 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
mbed_official 400:7fa56b1b9d45 6786 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
mbed_official 400:7fa56b1b9d45 6787
mbed_official 400:7fa56b1b9d45 6788 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
mbed_official 400:7fa56b1b9d45 6789 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
mbed_official 400:7fa56b1b9d45 6790
mbed_official 400:7fa56b1b9d45 6791 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
mbed_official 400:7fa56b1b9d45 6792 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6793 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6794 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6795 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6796 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6797 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6798 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6799 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 6800
mbed_official 400:7fa56b1b9d45 6801 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
mbed_official 400:7fa56b1b9d45 6802 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6803 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6804 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6805 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6806 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6807 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6808 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6809
mbed_official 400:7fa56b1b9d45 6810 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
mbed_official 400:7fa56b1b9d45 6811 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
mbed_official 400:7fa56b1b9d45 6812 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
mbed_official 400:7fa56b1b9d45 6813
mbed_official 400:7fa56b1b9d45 6814 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
mbed_official 400:7fa56b1b9d45 6815 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6816 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6817 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6818 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6819 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6820 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6821 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6822 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 6823 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
mbed_official 400:7fa56b1b9d45 6824 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
mbed_official 400:7fa56b1b9d45 6825
mbed_official 400:7fa56b1b9d45 6826 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
mbed_official 400:7fa56b1b9d45 6827 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6828 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6829 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6830 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6831 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6832 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6833 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6834 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
mbed_official 400:7fa56b1b9d45 6835 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
mbed_official 400:7fa56b1b9d45 6836 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
mbed_official 400:7fa56b1b9d45 6837
mbed_official 400:7fa56b1b9d45 6838 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
mbed_official 400:7fa56b1b9d45 6839 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
mbed_official 400:7fa56b1b9d45 6840
mbed_official 400:7fa56b1b9d45 6841 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
mbed_official 400:7fa56b1b9d45 6842 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
mbed_official 400:7fa56b1b9d45 6843 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
mbed_official 400:7fa56b1b9d45 6844
mbed_official 400:7fa56b1b9d45 6845 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
mbed_official 400:7fa56b1b9d45 6846 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
mbed_official 400:7fa56b1b9d45 6847 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
mbed_official 400:7fa56b1b9d45 6848 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
mbed_official 400:7fa56b1b9d45 6849 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
mbed_official 400:7fa56b1b9d45 6850 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
mbed_official 400:7fa56b1b9d45 6851 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
mbed_official 400:7fa56b1b9d45 6852
mbed_official 400:7fa56b1b9d45 6853 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
mbed_official 400:7fa56b1b9d45 6854 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
mbed_official 400:7fa56b1b9d45 6855 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
mbed_official 400:7fa56b1b9d45 6856
mbed_official 400:7fa56b1b9d45 6857 /******************** Bit definition forUSB_OTG_CID register ********************/
mbed_official 400:7fa56b1b9d45 6858 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
mbed_official 400:7fa56b1b9d45 6859
mbed_official 400:7fa56b1b9d45 6860 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
mbed_official 400:7fa56b1b9d45 6861 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 400:7fa56b1b9d45 6862 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 400:7fa56b1b9d45 6863 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 400:7fa56b1b9d45 6864 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 400:7fa56b1b9d45 6865 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 400:7fa56b1b9d45 6866 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 400:7fa56b1b9d45 6867 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 400:7fa56b1b9d45 6868 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 400:7fa56b1b9d45 6869 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 400:7fa56b1b9d45 6870
mbed_official 400:7fa56b1b9d45 6871 /******************** Bit definition forUSB_OTG_HPRT register ********************/
mbed_official 400:7fa56b1b9d45 6872 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
mbed_official 400:7fa56b1b9d45 6873 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
mbed_official 400:7fa56b1b9d45 6874 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
mbed_official 400:7fa56b1b9d45 6875 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
mbed_official 400:7fa56b1b9d45 6876 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
mbed_official 400:7fa56b1b9d45 6877 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
mbed_official 400:7fa56b1b9d45 6878 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
mbed_official 400:7fa56b1b9d45 6879 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
mbed_official 400:7fa56b1b9d45 6880 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
mbed_official 400:7fa56b1b9d45 6881
mbed_official 400:7fa56b1b9d45 6882 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
mbed_official 400:7fa56b1b9d45 6883 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6884 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6885 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
mbed_official 400:7fa56b1b9d45 6886
mbed_official 400:7fa56b1b9d45 6887 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
mbed_official 400:7fa56b1b9d45 6888 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6889 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6890 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6891 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6892
mbed_official 400:7fa56b1b9d45 6893 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
mbed_official 400:7fa56b1b9d45 6894 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6895 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6896
mbed_official 400:7fa56b1b9d45 6897 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
mbed_official 400:7fa56b1b9d45 6898 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 400:7fa56b1b9d45 6899 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 400:7fa56b1b9d45 6900 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
mbed_official 400:7fa56b1b9d45 6901 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 400:7fa56b1b9d45 6902 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 400:7fa56b1b9d45 6903 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 400:7fa56b1b9d45 6904 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 400:7fa56b1b9d45 6905 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 400:7fa56b1b9d45 6906 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
mbed_official 400:7fa56b1b9d45 6907 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 400:7fa56b1b9d45 6908 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
mbed_official 400:7fa56b1b9d45 6909
mbed_official 400:7fa56b1b9d45 6910 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
mbed_official 400:7fa56b1b9d45 6911 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
mbed_official 400:7fa56b1b9d45 6912 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
mbed_official 400:7fa56b1b9d45 6913
mbed_official 400:7fa56b1b9d45 6914 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
mbed_official 400:7fa56b1b9d45 6915 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 400:7fa56b1b9d45 6916 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 400:7fa56b1b9d45 6917 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
mbed_official 400:7fa56b1b9d45 6918 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 400:7fa56b1b9d45 6919
mbed_official 400:7fa56b1b9d45 6920 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 400:7fa56b1b9d45 6921 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6922 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6923 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 400:7fa56b1b9d45 6924
mbed_official 400:7fa56b1b9d45 6925 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
mbed_official 400:7fa56b1b9d45 6926 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6927 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6928 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6929 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6930 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 400:7fa56b1b9d45 6931 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 400:7fa56b1b9d45 6932 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 400:7fa56b1b9d45 6933 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 400:7fa56b1b9d45 6934 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 400:7fa56b1b9d45 6935 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 400:7fa56b1b9d45 6936
mbed_official 400:7fa56b1b9d45 6937 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
mbed_official 400:7fa56b1b9d45 6938 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 400:7fa56b1b9d45 6939
mbed_official 400:7fa56b1b9d45 6940 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
mbed_official 400:7fa56b1b9d45 6941 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6942 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6943 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6944 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6945 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
mbed_official 400:7fa56b1b9d45 6946 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
mbed_official 400:7fa56b1b9d45 6947
mbed_official 400:7fa56b1b9d45 6948 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 400:7fa56b1b9d45 6949 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6950 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6951
mbed_official 400:7fa56b1b9d45 6952 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
mbed_official 400:7fa56b1b9d45 6953 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6954 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6955
mbed_official 400:7fa56b1b9d45 6956 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
mbed_official 400:7fa56b1b9d45 6957 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6958 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6959 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6960 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6961 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6962 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6963 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6964 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
mbed_official 400:7fa56b1b9d45 6965 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
mbed_official 400:7fa56b1b9d45 6966 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
mbed_official 400:7fa56b1b9d45 6967
mbed_official 400:7fa56b1b9d45 6968 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
mbed_official 400:7fa56b1b9d45 6969
mbed_official 400:7fa56b1b9d45 6970 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
mbed_official 400:7fa56b1b9d45 6971 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6972 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6973 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6974 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6975 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6976 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6977 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6978
mbed_official 400:7fa56b1b9d45 6979 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
mbed_official 400:7fa56b1b9d45 6980 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6981 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6982 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 400:7fa56b1b9d45 6983 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 400:7fa56b1b9d45 6984 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 400:7fa56b1b9d45 6985 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 400:7fa56b1b9d45 6986 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
mbed_official 400:7fa56b1b9d45 6987
mbed_official 400:7fa56b1b9d45 6988 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
mbed_official 400:7fa56b1b9d45 6989 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 6990 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 6991 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
mbed_official 400:7fa56b1b9d45 6992 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
mbed_official 400:7fa56b1b9d45 6993
mbed_official 400:7fa56b1b9d45 6994 /******************** Bit definition forUSB_OTG_HCINT register ********************/
mbed_official 400:7fa56b1b9d45 6995 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
mbed_official 400:7fa56b1b9d45 6996 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
mbed_official 400:7fa56b1b9d45 6997 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 400:7fa56b1b9d45 6998 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
mbed_official 400:7fa56b1b9d45 6999 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
mbed_official 400:7fa56b1b9d45 7000 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
mbed_official 400:7fa56b1b9d45 7001 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
mbed_official 400:7fa56b1b9d45 7002 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
mbed_official 400:7fa56b1b9d45 7003 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
mbed_official 400:7fa56b1b9d45 7004 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
mbed_official 400:7fa56b1b9d45 7005 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
mbed_official 400:7fa56b1b9d45 7006
mbed_official 400:7fa56b1b9d45 7007 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
mbed_official 400:7fa56b1b9d45 7008 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 400:7fa56b1b9d45 7009 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 400:7fa56b1b9d45 7010 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
mbed_official 400:7fa56b1b9d45 7011 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
mbed_official 400:7fa56b1b9d45 7012 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
mbed_official 400:7fa56b1b9d45 7013 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
mbed_official 400:7fa56b1b9d45 7014 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
mbed_official 400:7fa56b1b9d45 7015 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
mbed_official 400:7fa56b1b9d45 7016 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
mbed_official 400:7fa56b1b9d45 7017 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
mbed_official 400:7fa56b1b9d45 7018 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
mbed_official 400:7fa56b1b9d45 7019
mbed_official 400:7fa56b1b9d45 7020 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
mbed_official 400:7fa56b1b9d45 7021 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
mbed_official 400:7fa56b1b9d45 7022 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
mbed_official 400:7fa56b1b9d45 7023 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 400:7fa56b1b9d45 7024 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
mbed_official 400:7fa56b1b9d45 7025 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
mbed_official 400:7fa56b1b9d45 7026 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
mbed_official 400:7fa56b1b9d45 7027 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
mbed_official 400:7fa56b1b9d45 7028 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
mbed_official 400:7fa56b1b9d45 7029 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
mbed_official 400:7fa56b1b9d45 7030 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
mbed_official 400:7fa56b1b9d45 7031 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
mbed_official 400:7fa56b1b9d45 7032
mbed_official 400:7fa56b1b9d45 7033 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
mbed_official 400:7fa56b1b9d45 7034
mbed_official 400:7fa56b1b9d45 7035 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 400:7fa56b1b9d45 7036 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 400:7fa56b1b9d45 7037 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
mbed_official 400:7fa56b1b9d45 7038 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
mbed_official 400:7fa56b1b9d45 7039 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 400:7fa56b1b9d45 7040 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 400:7fa56b1b9d45 7041 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
mbed_official 400:7fa56b1b9d45 7042 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
mbed_official 400:7fa56b1b9d45 7043 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 7044 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 7045
mbed_official 400:7fa56b1b9d45 7046 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
mbed_official 400:7fa56b1b9d45 7047 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 400:7fa56b1b9d45 7048
mbed_official 400:7fa56b1b9d45 7049 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
mbed_official 400:7fa56b1b9d45 7050 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 400:7fa56b1b9d45 7051
mbed_official 400:7fa56b1b9d45 7052 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
mbed_official 400:7fa56b1b9d45 7053 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
mbed_official 400:7fa56b1b9d45 7054
mbed_official 400:7fa56b1b9d45 7055 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
mbed_official 400:7fa56b1b9d45 7056 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
mbed_official 400:7fa56b1b9d45 7057 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
mbed_official 400:7fa56b1b9d45 7058
mbed_official 400:7fa56b1b9d45 7059 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
mbed_official 400:7fa56b1b9d45 7060
mbed_official 400:7fa56b1b9d45 7061 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 7062 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 400:7fa56b1b9d45 7063 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 400:7fa56b1b9d45 7064 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 400:7fa56b1b9d45 7065 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 400:7fa56b1b9d45 7066 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 400:7fa56b1b9d45 7067 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 7068 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 7069 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
mbed_official 400:7fa56b1b9d45 7070 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 400:7fa56b1b9d45 7071 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 400:7fa56b1b9d45 7072 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 400:7fa56b1b9d45 7073 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 400:7fa56b1b9d45 7074 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 400:7fa56b1b9d45 7075
mbed_official 400:7fa56b1b9d45 7076 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
mbed_official 400:7fa56b1b9d45 7077 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 400:7fa56b1b9d45 7078 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 400:7fa56b1b9d45 7079 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
mbed_official 400:7fa56b1b9d45 7080 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
mbed_official 400:7fa56b1b9d45 7081 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
mbed_official 400:7fa56b1b9d45 7082 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
mbed_official 400:7fa56b1b9d45 7083
mbed_official 400:7fa56b1b9d45 7084 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
mbed_official 400:7fa56b1b9d45 7085
mbed_official 400:7fa56b1b9d45 7086 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 400:7fa56b1b9d45 7087 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 400:7fa56b1b9d45 7088
mbed_official 400:7fa56b1b9d45 7089 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
mbed_official 400:7fa56b1b9d45 7090 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 7091 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 7092
mbed_official 400:7fa56b1b9d45 7093 /******************** Bit definition for PCGCCTL register ********************/
mbed_official 400:7fa56b1b9d45 7094 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
mbed_official 400:7fa56b1b9d45 7095 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 400:7fa56b1b9d45 7096 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 400:7fa56b1b9d45 7097
mbed_official 400:7fa56b1b9d45 7098 /**
mbed_official 400:7fa56b1b9d45 7099 * @}
mbed_official 400:7fa56b1b9d45 7100 */
mbed_official 400:7fa56b1b9d45 7101
mbed_official 400:7fa56b1b9d45 7102 /**
mbed_official 400:7fa56b1b9d45 7103 * @}
mbed_official 400:7fa56b1b9d45 7104 */
mbed_official 400:7fa56b1b9d45 7105
mbed_official 400:7fa56b1b9d45 7106 /** @addtogroup Exported_macros
mbed_official 400:7fa56b1b9d45 7107 * @{
mbed_official 400:7fa56b1b9d45 7108 */
mbed_official 400:7fa56b1b9d45 7109
mbed_official 400:7fa56b1b9d45 7110 /******************************* ADC Instances ********************************/
mbed_official 400:7fa56b1b9d45 7111 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 400:7fa56b1b9d45 7112 ((INSTANCE) == ADC2) || \
mbed_official 400:7fa56b1b9d45 7113 ((INSTANCE) == ADC3))
mbed_official 400:7fa56b1b9d45 7114
mbed_official 400:7fa56b1b9d45 7115 /******************************* CAN Instances ********************************/
mbed_official 400:7fa56b1b9d45 7116 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
mbed_official 400:7fa56b1b9d45 7117 ((INSTANCE) == CAN2))
mbed_official 400:7fa56b1b9d45 7118
mbed_official 400:7fa56b1b9d45 7119 /******************************* CRC Instances ********************************/
mbed_official 400:7fa56b1b9d45 7120 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 400:7fa56b1b9d45 7121
mbed_official 400:7fa56b1b9d45 7122 /******************************* DAC Instances ********************************/
mbed_official 400:7fa56b1b9d45 7123 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 400:7fa56b1b9d45 7124
mbed_official 400:7fa56b1b9d45 7125 /******************************** DMA Instances *******************************/
mbed_official 400:7fa56b1b9d45 7126 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
mbed_official 400:7fa56b1b9d45 7127 ((INSTANCE) == DMA1_Stream1) || \
mbed_official 400:7fa56b1b9d45 7128 ((INSTANCE) == DMA1_Stream2) || \
mbed_official 400:7fa56b1b9d45 7129 ((INSTANCE) == DMA1_Stream3) || \
mbed_official 400:7fa56b1b9d45 7130 ((INSTANCE) == DMA1_Stream4) || \
mbed_official 400:7fa56b1b9d45 7131 ((INSTANCE) == DMA1_Stream5) || \
mbed_official 400:7fa56b1b9d45 7132 ((INSTANCE) == DMA1_Stream6) || \
mbed_official 400:7fa56b1b9d45 7133 ((INSTANCE) == DMA1_Stream7) || \
mbed_official 400:7fa56b1b9d45 7134 ((INSTANCE) == DMA2_Stream0) || \
mbed_official 400:7fa56b1b9d45 7135 ((INSTANCE) == DMA2_Stream1) || \
mbed_official 400:7fa56b1b9d45 7136 ((INSTANCE) == DMA2_Stream2) || \
mbed_official 400:7fa56b1b9d45 7137 ((INSTANCE) == DMA2_Stream3) || \
mbed_official 400:7fa56b1b9d45 7138 ((INSTANCE) == DMA2_Stream4) || \
mbed_official 400:7fa56b1b9d45 7139 ((INSTANCE) == DMA2_Stream5) || \
mbed_official 400:7fa56b1b9d45 7140 ((INSTANCE) == DMA2_Stream6) || \
mbed_official 400:7fa56b1b9d45 7141 ((INSTANCE) == DMA2_Stream7))
mbed_official 400:7fa56b1b9d45 7142
mbed_official 400:7fa56b1b9d45 7143 /******************************* GPIO Instances *******************************/
mbed_official 400:7fa56b1b9d45 7144 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 400:7fa56b1b9d45 7145 ((INSTANCE) == GPIOB) || \
mbed_official 400:7fa56b1b9d45 7146 ((INSTANCE) == GPIOC) || \
mbed_official 400:7fa56b1b9d45 7147 ((INSTANCE) == GPIOD) || \
mbed_official 400:7fa56b1b9d45 7148 ((INSTANCE) == GPIOE) || \
mbed_official 400:7fa56b1b9d45 7149 ((INSTANCE) == GPIOF) || \
mbed_official 400:7fa56b1b9d45 7150 ((INSTANCE) == GPIOG) || \
mbed_official 400:7fa56b1b9d45 7151 ((INSTANCE) == GPIOH) || \
mbed_official 400:7fa56b1b9d45 7152 ((INSTANCE) == GPIOI))
mbed_official 400:7fa56b1b9d45 7153
mbed_official 400:7fa56b1b9d45 7154 /******************************** I2C Instances *******************************/
mbed_official 400:7fa56b1b9d45 7155 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 400:7fa56b1b9d45 7156 ((INSTANCE) == I2C2) || \
mbed_official 400:7fa56b1b9d45 7157 ((INSTANCE) == I2C3))
mbed_official 400:7fa56b1b9d45 7158
mbed_official 400:7fa56b1b9d45 7159 /******************************** I2S Instances *******************************/
mbed_official 532:fe11edbda85c 7160 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
mbed_official 400:7fa56b1b9d45 7161 ((INSTANCE) == SPI3))
mbed_official 400:7fa56b1b9d45 7162
mbed_official 400:7fa56b1b9d45 7163 /*************************** I2S Extended Instances ***************************/
mbed_official 532:fe11edbda85c 7164 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
mbed_official 532:fe11edbda85c 7165 ((INSTANCE) == SPI3) || \
mbed_official 532:fe11edbda85c 7166 ((INSTANCE) == I2S2ext) || \
mbed_official 532:fe11edbda85c 7167 ((INSTANCE) == I2S3ext))
mbed_official 400:7fa56b1b9d45 7168
mbed_official 400:7fa56b1b9d45 7169 /******************************* RNG Instances ********************************/
mbed_official 400:7fa56b1b9d45 7170 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
mbed_official 400:7fa56b1b9d45 7171
mbed_official 400:7fa56b1b9d45 7172 /****************************** RTC Instances *********************************/
mbed_official 400:7fa56b1b9d45 7173 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 400:7fa56b1b9d45 7174
mbed_official 400:7fa56b1b9d45 7175 /******************************** SPI Instances *******************************/
mbed_official 400:7fa56b1b9d45 7176 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 400:7fa56b1b9d45 7177 ((INSTANCE) == SPI2) || \
mbed_official 400:7fa56b1b9d45 7178 ((INSTANCE) == SPI3))
mbed_official 400:7fa56b1b9d45 7179
mbed_official 400:7fa56b1b9d45 7180 /*************************** SPI Extended Instances ***************************/
mbed_official 400:7fa56b1b9d45 7181 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 400:7fa56b1b9d45 7182 ((INSTANCE) == SPI2) || \
mbed_official 400:7fa56b1b9d45 7183 ((INSTANCE) == SPI3) || \
mbed_official 400:7fa56b1b9d45 7184 ((INSTANCE) == I2S2ext) || \
mbed_official 400:7fa56b1b9d45 7185 ((INSTANCE) == I2S3ext))
mbed_official 400:7fa56b1b9d45 7186
mbed_official 400:7fa56b1b9d45 7187 /****************** TIM Instances : All supported instances *******************/
mbed_official 400:7fa56b1b9d45 7188 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7189 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7190 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7191 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7192 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7193 ((INSTANCE) == TIM6) || \
mbed_official 400:7fa56b1b9d45 7194 ((INSTANCE) == TIM7) || \
mbed_official 400:7fa56b1b9d45 7195 ((INSTANCE) == TIM8) || \
mbed_official 400:7fa56b1b9d45 7196 ((INSTANCE) == TIM9) || \
mbed_official 400:7fa56b1b9d45 7197 ((INSTANCE) == TIM10) || \
mbed_official 400:7fa56b1b9d45 7198 ((INSTANCE) == TIM11) || \
mbed_official 400:7fa56b1b9d45 7199 ((INSTANCE) == TIM12) || \
mbed_official 400:7fa56b1b9d45 7200 ((INSTANCE) == TIM13) || \
mbed_official 400:7fa56b1b9d45 7201 ((INSTANCE) == TIM14))
mbed_official 400:7fa56b1b9d45 7202
mbed_official 400:7fa56b1b9d45 7203 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 400:7fa56b1b9d45 7204 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7205 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7206 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7207 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7208 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7209 ((INSTANCE) == TIM8) || \
mbed_official 400:7fa56b1b9d45 7210 ((INSTANCE) == TIM9) || \
mbed_official 400:7fa56b1b9d45 7211 ((INSTANCE) == TIM10) || \
mbed_official 400:7fa56b1b9d45 7212 ((INSTANCE) == TIM11) || \
mbed_official 400:7fa56b1b9d45 7213 ((INSTANCE) == TIM12) || \
mbed_official 400:7fa56b1b9d45 7214 ((INSTANCE) == TIM13) || \
mbed_official 400:7fa56b1b9d45 7215 ((INSTANCE) == TIM14))
mbed_official 400:7fa56b1b9d45 7216
mbed_official 400:7fa56b1b9d45 7217 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 400:7fa56b1b9d45 7218 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7219 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7220 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7221 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7222 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7223 ((INSTANCE) == TIM8) || \
mbed_official 400:7fa56b1b9d45 7224 ((INSTANCE) == TIM9) || \
mbed_official 400:7fa56b1b9d45 7225 ((INSTANCE) == TIM12))
mbed_official 400:7fa56b1b9d45 7226
mbed_official 400:7fa56b1b9d45 7227 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 400:7fa56b1b9d45 7228 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7229 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7230 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7231 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7232 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7233 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7234
mbed_official 400:7fa56b1b9d45 7235 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 400:7fa56b1b9d45 7236 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7237 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7238 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7239 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7240 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7241 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7242
mbed_official 400:7fa56b1b9d45 7243 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 400:7fa56b1b9d45 7244 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7245 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7246
mbed_official 400:7fa56b1b9d45 7247 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 400:7fa56b1b9d45 7248 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7249 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7250 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7251 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7252 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7253 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7254
mbed_official 400:7fa56b1b9d45 7255 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 400:7fa56b1b9d45 7256 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7257 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7258 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7259 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7260 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7261 ((INSTANCE) == TIM6) || \
mbed_official 400:7fa56b1b9d45 7262 ((INSTANCE) == TIM7) || \
mbed_official 400:7fa56b1b9d45 7263 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7264
mbed_official 400:7fa56b1b9d45 7265 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 400:7fa56b1b9d45 7266 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7267 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7268 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7269 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7270 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7271 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7272
mbed_official 400:7fa56b1b9d45 7273 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 400:7fa56b1b9d45 7274 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7275 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7276 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7277 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7278 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7279 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7280
mbed_official 400:7fa56b1b9d45 7281 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 400:7fa56b1b9d45 7282 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7283 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7284 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7285 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7286 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7287 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7288
mbed_official 400:7fa56b1b9d45 7289 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 400:7fa56b1b9d45 7290 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7291 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7292 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7293 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7294 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7295 ((INSTANCE) == TIM6) || \
mbed_official 400:7fa56b1b9d45 7296 ((INSTANCE) == TIM7) || \
mbed_official 400:7fa56b1b9d45 7297 ((INSTANCE) == TIM8) || \
mbed_official 400:7fa56b1b9d45 7298 ((INSTANCE) == TIM9) || \
mbed_official 400:7fa56b1b9d45 7299 ((INSTANCE) == TIM12))
mbed_official 400:7fa56b1b9d45 7300
mbed_official 400:7fa56b1b9d45 7301 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 400:7fa56b1b9d45 7302 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7303 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7304 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7305 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7306 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7307 ((INSTANCE) == TIM8) || \
mbed_official 400:7fa56b1b9d45 7308 ((INSTANCE) == TIM9) || \
mbed_official 400:7fa56b1b9d45 7309 ((INSTANCE) == TIM12))
mbed_official 400:7fa56b1b9d45 7310
mbed_official 400:7fa56b1b9d45 7311 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 400:7fa56b1b9d45 7312 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7313 ((INSTANCE) == TIM5))
mbed_official 400:7fa56b1b9d45 7314
mbed_official 400:7fa56b1b9d45 7315 /***************** TIM Instances : external trigger input availabe ************/
mbed_official 400:7fa56b1b9d45 7316 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 400:7fa56b1b9d45 7317 ((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7318 ((INSTANCE) == TIM3) || \
mbed_official 400:7fa56b1b9d45 7319 ((INSTANCE) == TIM4) || \
mbed_official 400:7fa56b1b9d45 7320 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7321 ((INSTANCE) == TIM8))
mbed_official 400:7fa56b1b9d45 7322
mbed_official 400:7fa56b1b9d45 7323 /****************** TIM Instances : remapping capability **********************/
mbed_official 400:7fa56b1b9d45 7324 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 400:7fa56b1b9d45 7325 ((INSTANCE) == TIM5) || \
mbed_official 400:7fa56b1b9d45 7326 ((INSTANCE) == TIM11))
mbed_official 400:7fa56b1b9d45 7327
mbed_official 400:7fa56b1b9d45 7328 /******************* TIM Instances : output(s) available **********************/
mbed_official 400:7fa56b1b9d45 7329 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 400:7fa56b1b9d45 7330 ((((INSTANCE) == TIM1) && \
mbed_official 400:7fa56b1b9d45 7331 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7332 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 400:7fa56b1b9d45 7333 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 400:7fa56b1b9d45 7334 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 400:7fa56b1b9d45 7335 || \
mbed_official 400:7fa56b1b9d45 7336 (((INSTANCE) == TIM2) && \
mbed_official 400:7fa56b1b9d45 7337 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7338 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 400:7fa56b1b9d45 7339 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 400:7fa56b1b9d45 7340 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 400:7fa56b1b9d45 7341 || \
mbed_official 400:7fa56b1b9d45 7342 (((INSTANCE) == TIM3) && \
mbed_official 400:7fa56b1b9d45 7343 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7344 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 400:7fa56b1b9d45 7345 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 400:7fa56b1b9d45 7346 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 400:7fa56b1b9d45 7347 || \
mbed_official 400:7fa56b1b9d45 7348 (((INSTANCE) == TIM4) && \
mbed_official 400:7fa56b1b9d45 7349 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7350 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 400:7fa56b1b9d45 7351 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 400:7fa56b1b9d45 7352 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 400:7fa56b1b9d45 7353 || \
mbed_official 400:7fa56b1b9d45 7354 (((INSTANCE) == TIM5) && \
mbed_official 400:7fa56b1b9d45 7355 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7356 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 400:7fa56b1b9d45 7357 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 400:7fa56b1b9d45 7358 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 400:7fa56b1b9d45 7359 || \
mbed_official 400:7fa56b1b9d45 7360 (((INSTANCE) == TIM8) && \
mbed_official 400:7fa56b1b9d45 7361 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7362 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 400:7fa56b1b9d45 7363 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 400:7fa56b1b9d45 7364 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 400:7fa56b1b9d45 7365 || \
mbed_official 400:7fa56b1b9d45 7366 (((INSTANCE) == TIM9) && \
mbed_official 400:7fa56b1b9d45 7367 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7368 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 400:7fa56b1b9d45 7369 || \
mbed_official 400:7fa56b1b9d45 7370 (((INSTANCE) == TIM10) && \
mbed_official 400:7fa56b1b9d45 7371 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 400:7fa56b1b9d45 7372 || \
mbed_official 400:7fa56b1b9d45 7373 (((INSTANCE) == TIM11) && \
mbed_official 400:7fa56b1b9d45 7374 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 400:7fa56b1b9d45 7375 || \
mbed_official 400:7fa56b1b9d45 7376 (((INSTANCE) == TIM12) && \
mbed_official 400:7fa56b1b9d45 7377 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7378 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 400:7fa56b1b9d45 7379 || \
mbed_official 400:7fa56b1b9d45 7380 (((INSTANCE) == TIM13) && \
mbed_official 400:7fa56b1b9d45 7381 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 400:7fa56b1b9d45 7382 || \
mbed_official 400:7fa56b1b9d45 7383 (((INSTANCE) == TIM14) && \
mbed_official 400:7fa56b1b9d45 7384 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 400:7fa56b1b9d45 7385
mbed_official 400:7fa56b1b9d45 7386 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 400:7fa56b1b9d45 7387 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 400:7fa56b1b9d45 7388 ((((INSTANCE) == TIM1) && \
mbed_official 400:7fa56b1b9d45 7389 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7390 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 400:7fa56b1b9d45 7391 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 400:7fa56b1b9d45 7392 || \
mbed_official 400:7fa56b1b9d45 7393 (((INSTANCE) == TIM8) && \
mbed_official 400:7fa56b1b9d45 7394 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 400:7fa56b1b9d45 7395 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 400:7fa56b1b9d45 7396 ((CHANNEL) == TIM_CHANNEL_3))))
mbed_official 400:7fa56b1b9d45 7397
mbed_official 400:7fa56b1b9d45 7398 /******************** USART Instances : Synchronous mode **********************/
mbed_official 400:7fa56b1b9d45 7399 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 400:7fa56b1b9d45 7400 ((INSTANCE) == USART2) || \
mbed_official 400:7fa56b1b9d45 7401 ((INSTANCE) == USART3) || \
mbed_official 400:7fa56b1b9d45 7402 ((INSTANCE) == USART6))
mbed_official 400:7fa56b1b9d45 7403
mbed_official 400:7fa56b1b9d45 7404 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 400:7fa56b1b9d45 7405 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 400:7fa56b1b9d45 7406 ((INSTANCE) == USART2) || \
mbed_official 400:7fa56b1b9d45 7407 ((INSTANCE) == USART3) || \
mbed_official 400:7fa56b1b9d45 7408 ((INSTANCE) == UART4) || \
mbed_official 400:7fa56b1b9d45 7409 ((INSTANCE) == UART5) || \
mbed_official 400:7fa56b1b9d45 7410 ((INSTANCE) == USART6))
mbed_official 400:7fa56b1b9d45 7411
mbed_official 400:7fa56b1b9d45 7412 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 400:7fa56b1b9d45 7413 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 400:7fa56b1b9d45 7414 ((INSTANCE) == USART2) || \
mbed_official 400:7fa56b1b9d45 7415 ((INSTANCE) == USART3) || \
mbed_official 400:7fa56b1b9d45 7416 ((INSTANCE) == USART6))
mbed_official 400:7fa56b1b9d45 7417
mbed_official 400:7fa56b1b9d45 7418 /********************* UART Instances : Smard card mode ***********************/
mbed_official 400:7fa56b1b9d45 7419 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 400:7fa56b1b9d45 7420 ((INSTANCE) == USART2) || \
mbed_official 400:7fa56b1b9d45 7421 ((INSTANCE) == USART3) || \
mbed_official 400:7fa56b1b9d45 7422 ((INSTANCE) == USART6))
mbed_official 400:7fa56b1b9d45 7423
mbed_official 400:7fa56b1b9d45 7424 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 400:7fa56b1b9d45 7425 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 400:7fa56b1b9d45 7426 ((INSTANCE) == USART2) || \
mbed_official 400:7fa56b1b9d45 7427 ((INSTANCE) == USART3) || \
mbed_official 400:7fa56b1b9d45 7428 ((INSTANCE) == UART4) || \
mbed_official 400:7fa56b1b9d45 7429 ((INSTANCE) == UART5) || \
mbed_official 400:7fa56b1b9d45 7430 ((INSTANCE) == USART6))
mbed_official 400:7fa56b1b9d45 7431
mbed_official 400:7fa56b1b9d45 7432 /****************************** IWDG Instances ********************************/
mbed_official 400:7fa56b1b9d45 7433 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 400:7fa56b1b9d45 7434
mbed_official 400:7fa56b1b9d45 7435 /****************************** WWDG Instances ********************************/
mbed_official 400:7fa56b1b9d45 7436 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 400:7fa56b1b9d45 7437
mbed_official 532:fe11edbda85c 7438 /****************************** SDIO Instances ********************************/
mbed_official 532:fe11edbda85c 7439 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
mbed_official 532:fe11edbda85c 7440
mbed_official 532:fe11edbda85c 7441 /****************************** USB Exported Constants ************************/
mbed_official 532:fe11edbda85c 7442 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
mbed_official 532:fe11edbda85c 7443 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
mbed_official 532:fe11edbda85c 7444 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
mbed_official 532:fe11edbda85c 7445 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
mbed_official 532:fe11edbda85c 7446
mbed_official 532:fe11edbda85c 7447 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
mbed_official 532:fe11edbda85c 7448 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
mbed_official 532:fe11edbda85c 7449 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
mbed_official 532:fe11edbda85c 7450 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
mbed_official 532:fe11edbda85c 7451
mbed_official 400:7fa56b1b9d45 7452 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 7453 /* For a painless codes migration between the STM32F4xx device product */
mbed_official 400:7fa56b1b9d45 7454 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 400:7fa56b1b9d45 7455 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 400:7fa56b1b9d45 7456 /* No need to update developed interrupt code when moving across */
mbed_official 400:7fa56b1b9d45 7457 /* product lines within the same STM32F4 Family */
mbed_official 400:7fa56b1b9d45 7458 /******************************************************************************/
mbed_official 400:7fa56b1b9d45 7459
mbed_official 400:7fa56b1b9d45 7460 /* Aliases for __IRQn */
mbed_official 400:7fa56b1b9d45 7461 #define FMC_IRQn FSMC_IRQn
mbed_official 400:7fa56b1b9d45 7462
mbed_official 400:7fa56b1b9d45 7463 /* Aliases for __IRQHandler */
mbed_official 400:7fa56b1b9d45 7464 #define FMC_IRQHandler FSMC_IRQHandler
mbed_official 400:7fa56b1b9d45 7465
mbed_official 400:7fa56b1b9d45 7466 /**
mbed_official 400:7fa56b1b9d45 7467 * @}
mbed_official 400:7fa56b1b9d45 7468 */
mbed_official 400:7fa56b1b9d45 7469
mbed_official 400:7fa56b1b9d45 7470 /**
mbed_official 400:7fa56b1b9d45 7471 * @}
mbed_official 400:7fa56b1b9d45 7472 */
mbed_official 400:7fa56b1b9d45 7473
mbed_official 400:7fa56b1b9d45 7474 /**
mbed_official 400:7fa56b1b9d45 7475 * @}
mbed_official 400:7fa56b1b9d45 7476 */
mbed_official 400:7fa56b1b9d45 7477
mbed_official 400:7fa56b1b9d45 7478 #ifdef __cplusplus
mbed_official 400:7fa56b1b9d45 7479 }
mbed_official 400:7fa56b1b9d45 7480 #endif /* __cplusplus */
mbed_official 400:7fa56b1b9d45 7481
mbed_official 400:7fa56b1b9d45 7482 #endif /* __STM32F405xx_H */
mbed_official 400:7fa56b1b9d45 7483
mbed_official 400:7fa56b1b9d45 7484
mbed_official 400:7fa56b1b9d45 7485
mbed_official 400:7fa56b1b9d45 7486 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/