Flotsam
Modified version of the mbed library for use with the Nucleo boards.
Dependents: EEPROMWrite Full-Project
Fork of
mbed-src
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h@613:bc40b8d2aec4, 2015-08-20 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Aug 20 10:45:13 2015 +0100
- Revision:
- 613:bc40b8d2aec4
- Parent:
- 532:fe11edbda85c
Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade
Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/
Nordic: update application start address in GCC linker script
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f429xx.h |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 613:bc40b8d2aec4 | 5 | * @version V2.3.2 |
| mbed_official | 613:bc40b8d2aec4 | 6 | * @date 26-June-2015 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File. |
| mbed_official | 340:28d1f895c6fe | 8 | * |
| mbed_official | 340:28d1f895c6fe | 9 | * This file contains: |
| mbed_official | 340:28d1f895c6fe | 10 | * - Data structures and the address mapping for all peripherals |
| mbed_official | 340:28d1f895c6fe | 11 | * - Peripheral's registers declarations and bits definition |
| mbed_official | 340:28d1f895c6fe | 12 | * - Macros to access peripherals registers hardware |
| mbed_official | 340:28d1f895c6fe | 13 | * |
| mbed_official | 340:28d1f895c6fe | 14 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 15 | * @attention |
| mbed_official | 340:28d1f895c6fe | 16 | * |
| mbed_official | 532:fe11edbda85c | 17 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 18 | * |
| mbed_official | 340:28d1f895c6fe | 19 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 20 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 21 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 22 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 23 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 24 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 25 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 26 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 27 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 28 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 29 | * |
| mbed_official | 340:28d1f895c6fe | 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 33 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 36 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 38 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 40 | * |
| mbed_official | 340:28d1f895c6fe | 41 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 42 | */ |
| mbed_official | 340:28d1f895c6fe | 43 | |
| mbed_official | 340:28d1f895c6fe | 44 | /** @addtogroup CMSIS_Device |
| mbed_official | 340:28d1f895c6fe | 45 | * @{ |
| mbed_official | 340:28d1f895c6fe | 46 | */ |
| mbed_official | 340:28d1f895c6fe | 47 | |
| mbed_official | 340:28d1f895c6fe | 48 | /** @addtogroup stm32f429xx |
| mbed_official | 340:28d1f895c6fe | 49 | * @{ |
| mbed_official | 340:28d1f895c6fe | 50 | */ |
| mbed_official | 340:28d1f895c6fe | 51 | |
| mbed_official | 340:28d1f895c6fe | 52 | #ifndef __STM32F429xx_H |
| mbed_official | 340:28d1f895c6fe | 53 | #define __STM32F429xx_H |
| mbed_official | 340:28d1f895c6fe | 54 | |
| mbed_official | 340:28d1f895c6fe | 55 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 56 | extern "C" { |
| mbed_official | 340:28d1f895c6fe | 57 | #endif /* __cplusplus */ |
| mbed_official | 340:28d1f895c6fe | 58 | |
| mbed_official | 340:28d1f895c6fe | 59 | /** @addtogroup Configuration_section_for_CMSIS |
| mbed_official | 340:28d1f895c6fe | 60 | * @{ |
| mbed_official | 340:28d1f895c6fe | 61 | */ |
| mbed_official | 340:28d1f895c6fe | 62 | |
| mbed_official | 340:28d1f895c6fe | 63 | /** |
| mbed_official | 340:28d1f895c6fe | 64 | * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
| mbed_official | 340:28d1f895c6fe | 65 | */ |
| mbed_official | 340:28d1f895c6fe | 66 | #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ |
| mbed_official | 340:28d1f895c6fe | 67 | #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ |
| mbed_official | 340:28d1f895c6fe | 68 | #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ |
| mbed_official | 340:28d1f895c6fe | 69 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| mbed_official | 340:28d1f895c6fe | 70 | #define __FPU_PRESENT 1 /*!< FPU present */ |
| mbed_official | 340:28d1f895c6fe | 71 | |
| mbed_official | 340:28d1f895c6fe | 72 | /** |
| mbed_official | 340:28d1f895c6fe | 73 | * @} |
| mbed_official | 340:28d1f895c6fe | 74 | */ |
| mbed_official | 340:28d1f895c6fe | 75 | |
| mbed_official | 340:28d1f895c6fe | 76 | /** @addtogroup Peripheral_interrupt_number_definition |
| mbed_official | 340:28d1f895c6fe | 77 | * @{ |
| mbed_official | 340:28d1f895c6fe | 78 | */ |
| mbed_official | 340:28d1f895c6fe | 79 | |
| mbed_official | 340:28d1f895c6fe | 80 | /** |
| mbed_official | 340:28d1f895c6fe | 81 | * @brief STM32F4XX Interrupt Number Definition, according to the selected device |
| mbed_official | 340:28d1f895c6fe | 82 | * in @ref Library_configuration_section |
| mbed_official | 340:28d1f895c6fe | 83 | */ |
| mbed_official | 340:28d1f895c6fe | 84 | typedef enum |
| mbed_official | 340:28d1f895c6fe | 85 | { |
| mbed_official | 340:28d1f895c6fe | 86 | /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 87 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 88 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 89 | BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 90 | UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 91 | SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 92 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 93 | PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 94 | SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 95 | /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 96 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 97 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 98 | TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
| mbed_official | 340:28d1f895c6fe | 99 | RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ |
| mbed_official | 340:28d1f895c6fe | 100 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 101 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 102 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 103 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 104 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 105 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 106 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 107 | DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 108 | DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 109 | DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 110 | DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 111 | DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 112 | DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 113 | DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 114 | ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ |
| mbed_official | 340:28d1f895c6fe | 115 | CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 116 | CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 117 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 118 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 119 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 340:28d1f895c6fe | 120 | TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 121 | TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 122 | TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 123 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 124 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 125 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 126 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 127 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 128 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 129 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 130 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 131 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 132 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 133 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 134 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 135 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 136 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 340:28d1f895c6fe | 137 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 138 | OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ |
| mbed_official | 340:28d1f895c6fe | 139 | TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 140 | TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 141 | TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 142 | TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 143 | DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 144 | FMC_IRQn = 48, /*!< FMC global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 145 | SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 146 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 147 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 148 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 149 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 150 | TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ |
| mbed_official | 340:28d1f895c6fe | 151 | TIM7_IRQn = 55, /*!< TIM7 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 152 | DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 153 | DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 154 | DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 155 | DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 156 | DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 157 | ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 158 | ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 159 | CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 160 | CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 161 | CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 162 | CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 163 | OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 164 | DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 165 | DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 166 | DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 167 | USART6_IRQn = 71, /*!< USART6 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 168 | I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ |
| mbed_official | 340:28d1f895c6fe | 169 | I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ |
| mbed_official | 340:28d1f895c6fe | 170 | OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 171 | OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 172 | OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ |
| mbed_official | 340:28d1f895c6fe | 173 | OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 174 | DCMI_IRQn = 78, /*!< DCMI global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 175 | HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 176 | FPU_IRQn = 81, /*!< FPU global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 177 | UART7_IRQn = 82, /*!< UART7 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 178 | UART8_IRQn = 83, /*!< UART8 global interrupt */ |
| mbed_official | 340:28d1f895c6fe | 179 | SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 180 | SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 181 | SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 182 | SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 183 | LTDC_IRQn = 88, /*!< LTDC global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 184 | LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 185 | DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 186 | } IRQn_Type; |
| mbed_official | 340:28d1f895c6fe | 187 | |
| mbed_official | 340:28d1f895c6fe | 188 | /** |
| mbed_official | 340:28d1f895c6fe | 189 | * @} |
| mbed_official | 340:28d1f895c6fe | 190 | */ |
| mbed_official | 340:28d1f895c6fe | 191 | |
| mbed_official | 340:28d1f895c6fe | 192 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
| mbed_official | 340:28d1f895c6fe | 193 | #include "system_stm32f4xx.h" |
| mbed_official | 340:28d1f895c6fe | 194 | #include <stdint.h> |
| mbed_official | 340:28d1f895c6fe | 195 | |
| mbed_official | 340:28d1f895c6fe | 196 | /** @addtogroup Peripheral_registers_structures |
| mbed_official | 340:28d1f895c6fe | 197 | * @{ |
| mbed_official | 340:28d1f895c6fe | 198 | */ |
| mbed_official | 340:28d1f895c6fe | 199 | |
| mbed_official | 340:28d1f895c6fe | 200 | /** |
| mbed_official | 340:28d1f895c6fe | 201 | * @brief Analog to Digital Converter |
| mbed_official | 340:28d1f895c6fe | 202 | */ |
| mbed_official | 340:28d1f895c6fe | 203 | |
| mbed_official | 340:28d1f895c6fe | 204 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 205 | { |
| mbed_official | 340:28d1f895c6fe | 206 | __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 207 | __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 208 | __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 209 | __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 210 | __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 211 | __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 212 | __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 213 | __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 214 | __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 215 | __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 216 | __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ |
| mbed_official | 340:28d1f895c6fe | 217 | __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ |
| mbed_official | 340:28d1f895c6fe | 218 | __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ |
| mbed_official | 340:28d1f895c6fe | 219 | __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ |
| mbed_official | 340:28d1f895c6fe | 220 | __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ |
| mbed_official | 340:28d1f895c6fe | 221 | __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ |
| mbed_official | 340:28d1f895c6fe | 222 | __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ |
| mbed_official | 340:28d1f895c6fe | 223 | __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ |
| mbed_official | 340:28d1f895c6fe | 224 | __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ |
| mbed_official | 340:28d1f895c6fe | 225 | __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ |
| mbed_official | 340:28d1f895c6fe | 226 | } ADC_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 227 | |
| mbed_official | 340:28d1f895c6fe | 228 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 229 | { |
| mbed_official | 340:28d1f895c6fe | 230 | __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ |
| mbed_official | 340:28d1f895c6fe | 231 | __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ |
| mbed_official | 340:28d1f895c6fe | 232 | __IO uint32_t CDR; /*!< ADC common regular data register for dual |
| mbed_official | 340:28d1f895c6fe | 233 | AND triple modes, Address offset: ADC1 base address + 0x308 */ |
| mbed_official | 340:28d1f895c6fe | 234 | } ADC_Common_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 235 | |
| mbed_official | 340:28d1f895c6fe | 236 | |
| mbed_official | 340:28d1f895c6fe | 237 | /** |
| mbed_official | 340:28d1f895c6fe | 238 | * @brief Controller Area Network TxMailBox |
| mbed_official | 340:28d1f895c6fe | 239 | */ |
| mbed_official | 340:28d1f895c6fe | 240 | |
| mbed_official | 340:28d1f895c6fe | 241 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 242 | { |
| mbed_official | 340:28d1f895c6fe | 243 | __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| mbed_official | 340:28d1f895c6fe | 244 | __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| mbed_official | 340:28d1f895c6fe | 245 | __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| mbed_official | 340:28d1f895c6fe | 246 | __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| mbed_official | 340:28d1f895c6fe | 247 | } CAN_TxMailBox_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 248 | |
| mbed_official | 340:28d1f895c6fe | 249 | /** |
| mbed_official | 340:28d1f895c6fe | 250 | * @brief Controller Area Network FIFOMailBox |
| mbed_official | 340:28d1f895c6fe | 251 | */ |
| mbed_official | 340:28d1f895c6fe | 252 | |
| mbed_official | 340:28d1f895c6fe | 253 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 254 | { |
| mbed_official | 340:28d1f895c6fe | 255 | __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| mbed_official | 340:28d1f895c6fe | 256 | __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| mbed_official | 340:28d1f895c6fe | 257 | __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| mbed_official | 340:28d1f895c6fe | 258 | __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| mbed_official | 340:28d1f895c6fe | 259 | } CAN_FIFOMailBox_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 260 | |
| mbed_official | 340:28d1f895c6fe | 261 | /** |
| mbed_official | 340:28d1f895c6fe | 262 | * @brief Controller Area Network FilterRegister |
| mbed_official | 340:28d1f895c6fe | 263 | */ |
| mbed_official | 340:28d1f895c6fe | 264 | |
| mbed_official | 340:28d1f895c6fe | 265 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 266 | { |
| mbed_official | 340:28d1f895c6fe | 267 | __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| mbed_official | 340:28d1f895c6fe | 268 | __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| mbed_official | 340:28d1f895c6fe | 269 | } CAN_FilterRegister_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 270 | |
| mbed_official | 340:28d1f895c6fe | 271 | /** |
| mbed_official | 340:28d1f895c6fe | 272 | * @brief Controller Area Network |
| mbed_official | 340:28d1f895c6fe | 273 | */ |
| mbed_official | 340:28d1f895c6fe | 274 | |
| mbed_official | 340:28d1f895c6fe | 275 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 276 | { |
| mbed_official | 340:28d1f895c6fe | 277 | __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 278 | __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 279 | __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 280 | __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 281 | __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 282 | __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 283 | __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 284 | __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 285 | uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| mbed_official | 340:28d1f895c6fe | 286 | CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| mbed_official | 340:28d1f895c6fe | 287 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| mbed_official | 340:28d1f895c6fe | 288 | uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| mbed_official | 340:28d1f895c6fe | 289 | __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| mbed_official | 340:28d1f895c6fe | 290 | __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| mbed_official | 340:28d1f895c6fe | 291 | uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| mbed_official | 340:28d1f895c6fe | 292 | __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| mbed_official | 340:28d1f895c6fe | 293 | uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| mbed_official | 340:28d1f895c6fe | 294 | __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| mbed_official | 340:28d1f895c6fe | 295 | uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| mbed_official | 340:28d1f895c6fe | 296 | __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| mbed_official | 340:28d1f895c6fe | 297 | uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| mbed_official | 340:28d1f895c6fe | 298 | CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
| mbed_official | 340:28d1f895c6fe | 299 | } CAN_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 300 | |
| mbed_official | 340:28d1f895c6fe | 301 | /** |
| mbed_official | 340:28d1f895c6fe | 302 | * @brief CRC calculation unit |
| mbed_official | 340:28d1f895c6fe | 303 | */ |
| mbed_official | 340:28d1f895c6fe | 304 | |
| mbed_official | 340:28d1f895c6fe | 305 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 306 | { |
| mbed_official | 340:28d1f895c6fe | 307 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 308 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 309 | uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| mbed_official | 340:28d1f895c6fe | 310 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| mbed_official | 340:28d1f895c6fe | 311 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 312 | } CRC_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 313 | |
| mbed_official | 340:28d1f895c6fe | 314 | /** |
| mbed_official | 340:28d1f895c6fe | 315 | * @brief Digital to Analog Converter |
| mbed_official | 340:28d1f895c6fe | 316 | */ |
| mbed_official | 340:28d1f895c6fe | 317 | |
| mbed_official | 340:28d1f895c6fe | 318 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 319 | { |
| mbed_official | 340:28d1f895c6fe | 320 | __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 321 | __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 322 | __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 323 | __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 324 | __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 325 | __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 326 | __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 327 | __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 328 | __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 329 | __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 330 | __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
| mbed_official | 340:28d1f895c6fe | 331 | __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
| mbed_official | 340:28d1f895c6fe | 332 | __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
| mbed_official | 340:28d1f895c6fe | 333 | __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
| mbed_official | 340:28d1f895c6fe | 334 | } DAC_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 335 | |
| mbed_official | 340:28d1f895c6fe | 336 | /** |
| mbed_official | 340:28d1f895c6fe | 337 | * @brief Debug MCU |
| mbed_official | 340:28d1f895c6fe | 338 | */ |
| mbed_official | 340:28d1f895c6fe | 339 | |
| mbed_official | 340:28d1f895c6fe | 340 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 341 | { |
| mbed_official | 340:28d1f895c6fe | 342 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 343 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 344 | __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 345 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 346 | }DBGMCU_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 347 | |
| mbed_official | 340:28d1f895c6fe | 348 | /** |
| mbed_official | 340:28d1f895c6fe | 349 | * @brief DCMI |
| mbed_official | 340:28d1f895c6fe | 350 | */ |
| mbed_official | 340:28d1f895c6fe | 351 | |
| mbed_official | 340:28d1f895c6fe | 352 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 353 | { |
| mbed_official | 340:28d1f895c6fe | 354 | __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 355 | __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 356 | __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 357 | __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 358 | __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 359 | __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 360 | __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 361 | __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 362 | __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 363 | __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 364 | __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ |
| mbed_official | 340:28d1f895c6fe | 365 | } DCMI_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 366 | |
| mbed_official | 340:28d1f895c6fe | 367 | /** |
| mbed_official | 340:28d1f895c6fe | 368 | * @brief DMA Controller |
| mbed_official | 340:28d1f895c6fe | 369 | */ |
| mbed_official | 340:28d1f895c6fe | 370 | |
| mbed_official | 340:28d1f895c6fe | 371 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 372 | { |
| mbed_official | 340:28d1f895c6fe | 373 | __IO uint32_t CR; /*!< DMA stream x configuration register */ |
| mbed_official | 340:28d1f895c6fe | 374 | __IO uint32_t NDTR; /*!< DMA stream x number of data register */ |
| mbed_official | 340:28d1f895c6fe | 375 | __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ |
| mbed_official | 340:28d1f895c6fe | 376 | __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ |
| mbed_official | 340:28d1f895c6fe | 377 | __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ |
| mbed_official | 340:28d1f895c6fe | 378 | __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ |
| mbed_official | 340:28d1f895c6fe | 379 | } DMA_Stream_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 380 | |
| mbed_official | 340:28d1f895c6fe | 381 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 382 | { |
| mbed_official | 340:28d1f895c6fe | 383 | __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 384 | __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 385 | __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 386 | __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 387 | } DMA_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 388 | |
| mbed_official | 340:28d1f895c6fe | 389 | /** |
| mbed_official | 340:28d1f895c6fe | 390 | * @brief DMA2D Controller |
| mbed_official | 340:28d1f895c6fe | 391 | */ |
| mbed_official | 340:28d1f895c6fe | 392 | |
| mbed_official | 340:28d1f895c6fe | 393 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 394 | { |
| mbed_official | 340:28d1f895c6fe | 395 | __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 396 | __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 397 | __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 398 | __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 399 | __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 400 | __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 401 | __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 402 | __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 403 | __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 404 | __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 405 | __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ |
| mbed_official | 340:28d1f895c6fe | 406 | __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ |
| mbed_official | 340:28d1f895c6fe | 407 | __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ |
| mbed_official | 340:28d1f895c6fe | 408 | __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ |
| mbed_official | 340:28d1f895c6fe | 409 | __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ |
| mbed_official | 340:28d1f895c6fe | 410 | __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ |
| mbed_official | 340:28d1f895c6fe | 411 | __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ |
| mbed_official | 340:28d1f895c6fe | 412 | __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ |
| mbed_official | 340:28d1f895c6fe | 413 | __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ |
| mbed_official | 340:28d1f895c6fe | 414 | __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ |
| mbed_official | 340:28d1f895c6fe | 415 | uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ |
| mbed_official | 340:28d1f895c6fe | 416 | __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ |
| mbed_official | 340:28d1f895c6fe | 417 | __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ |
| mbed_official | 340:28d1f895c6fe | 418 | } DMA2D_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 419 | |
| mbed_official | 340:28d1f895c6fe | 420 | /** |
| mbed_official | 340:28d1f895c6fe | 421 | * @brief Ethernet MAC |
| mbed_official | 340:28d1f895c6fe | 422 | */ |
| mbed_official | 340:28d1f895c6fe | 423 | |
| mbed_official | 340:28d1f895c6fe | 424 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 425 | { |
| mbed_official | 340:28d1f895c6fe | 426 | __IO uint32_t MACCR; |
| mbed_official | 340:28d1f895c6fe | 427 | __IO uint32_t MACFFR; |
| mbed_official | 340:28d1f895c6fe | 428 | __IO uint32_t MACHTHR; |
| mbed_official | 340:28d1f895c6fe | 429 | __IO uint32_t MACHTLR; |
| mbed_official | 340:28d1f895c6fe | 430 | __IO uint32_t MACMIIAR; |
| mbed_official | 340:28d1f895c6fe | 431 | __IO uint32_t MACMIIDR; |
| mbed_official | 340:28d1f895c6fe | 432 | __IO uint32_t MACFCR; |
| mbed_official | 340:28d1f895c6fe | 433 | __IO uint32_t MACVLANTR; /* 8 */ |
| mbed_official | 340:28d1f895c6fe | 434 | uint32_t RESERVED0[2]; |
| mbed_official | 340:28d1f895c6fe | 435 | __IO uint32_t MACRWUFFR; /* 11 */ |
| mbed_official | 340:28d1f895c6fe | 436 | __IO uint32_t MACPMTCSR; |
| mbed_official | 340:28d1f895c6fe | 437 | uint32_t RESERVED1[2]; |
| mbed_official | 340:28d1f895c6fe | 438 | __IO uint32_t MACSR; /* 15 */ |
| mbed_official | 340:28d1f895c6fe | 439 | __IO uint32_t MACIMR; |
| mbed_official | 340:28d1f895c6fe | 440 | __IO uint32_t MACA0HR; |
| mbed_official | 340:28d1f895c6fe | 441 | __IO uint32_t MACA0LR; |
| mbed_official | 340:28d1f895c6fe | 442 | __IO uint32_t MACA1HR; |
| mbed_official | 340:28d1f895c6fe | 443 | __IO uint32_t MACA1LR; |
| mbed_official | 340:28d1f895c6fe | 444 | __IO uint32_t MACA2HR; |
| mbed_official | 340:28d1f895c6fe | 445 | __IO uint32_t MACA2LR; |
| mbed_official | 340:28d1f895c6fe | 446 | __IO uint32_t MACA3HR; |
| mbed_official | 340:28d1f895c6fe | 447 | __IO uint32_t MACA3LR; /* 24 */ |
| mbed_official | 340:28d1f895c6fe | 448 | uint32_t RESERVED2[40]; |
| mbed_official | 340:28d1f895c6fe | 449 | __IO uint32_t MMCCR; /* 65 */ |
| mbed_official | 340:28d1f895c6fe | 450 | __IO uint32_t MMCRIR; |
| mbed_official | 340:28d1f895c6fe | 451 | __IO uint32_t MMCTIR; |
| mbed_official | 340:28d1f895c6fe | 452 | __IO uint32_t MMCRIMR; |
| mbed_official | 340:28d1f895c6fe | 453 | __IO uint32_t MMCTIMR; /* 69 */ |
| mbed_official | 340:28d1f895c6fe | 454 | uint32_t RESERVED3[14]; |
| mbed_official | 340:28d1f895c6fe | 455 | __IO uint32_t MMCTGFSCCR; /* 84 */ |
| mbed_official | 340:28d1f895c6fe | 456 | __IO uint32_t MMCTGFMSCCR; |
| mbed_official | 340:28d1f895c6fe | 457 | uint32_t RESERVED4[5]; |
| mbed_official | 340:28d1f895c6fe | 458 | __IO uint32_t MMCTGFCR; |
| mbed_official | 340:28d1f895c6fe | 459 | uint32_t RESERVED5[10]; |
| mbed_official | 340:28d1f895c6fe | 460 | __IO uint32_t MMCRFCECR; |
| mbed_official | 340:28d1f895c6fe | 461 | __IO uint32_t MMCRFAECR; |
| mbed_official | 340:28d1f895c6fe | 462 | uint32_t RESERVED6[10]; |
| mbed_official | 340:28d1f895c6fe | 463 | __IO uint32_t MMCRGUFCR; |
| mbed_official | 340:28d1f895c6fe | 464 | uint32_t RESERVED7[334]; |
| mbed_official | 340:28d1f895c6fe | 465 | __IO uint32_t PTPTSCR; |
| mbed_official | 340:28d1f895c6fe | 466 | __IO uint32_t PTPSSIR; |
| mbed_official | 340:28d1f895c6fe | 467 | __IO uint32_t PTPTSHR; |
| mbed_official | 340:28d1f895c6fe | 468 | __IO uint32_t PTPTSLR; |
| mbed_official | 340:28d1f895c6fe | 469 | __IO uint32_t PTPTSHUR; |
| mbed_official | 340:28d1f895c6fe | 470 | __IO uint32_t PTPTSLUR; |
| mbed_official | 340:28d1f895c6fe | 471 | __IO uint32_t PTPTSAR; |
| mbed_official | 340:28d1f895c6fe | 472 | __IO uint32_t PTPTTHR; |
| mbed_official | 340:28d1f895c6fe | 473 | __IO uint32_t PTPTTLR; |
| mbed_official | 340:28d1f895c6fe | 474 | __IO uint32_t RESERVED8; |
| mbed_official | 340:28d1f895c6fe | 475 | __IO uint32_t PTPTSSR; |
| mbed_official | 340:28d1f895c6fe | 476 | uint32_t RESERVED9[565]; |
| mbed_official | 340:28d1f895c6fe | 477 | __IO uint32_t DMABMR; |
| mbed_official | 340:28d1f895c6fe | 478 | __IO uint32_t DMATPDR; |
| mbed_official | 340:28d1f895c6fe | 479 | __IO uint32_t DMARPDR; |
| mbed_official | 340:28d1f895c6fe | 480 | __IO uint32_t DMARDLAR; |
| mbed_official | 340:28d1f895c6fe | 481 | __IO uint32_t DMATDLAR; |
| mbed_official | 340:28d1f895c6fe | 482 | __IO uint32_t DMASR; |
| mbed_official | 340:28d1f895c6fe | 483 | __IO uint32_t DMAOMR; |
| mbed_official | 340:28d1f895c6fe | 484 | __IO uint32_t DMAIER; |
| mbed_official | 340:28d1f895c6fe | 485 | __IO uint32_t DMAMFBOCR; |
| mbed_official | 340:28d1f895c6fe | 486 | __IO uint32_t DMARSWTR; |
| mbed_official | 340:28d1f895c6fe | 487 | uint32_t RESERVED10[8]; |
| mbed_official | 340:28d1f895c6fe | 488 | __IO uint32_t DMACHTDR; |
| mbed_official | 340:28d1f895c6fe | 489 | __IO uint32_t DMACHRDR; |
| mbed_official | 340:28d1f895c6fe | 490 | __IO uint32_t DMACHTBAR; |
| mbed_official | 340:28d1f895c6fe | 491 | __IO uint32_t DMACHRBAR; |
| mbed_official | 340:28d1f895c6fe | 492 | } ETH_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 493 | |
| mbed_official | 340:28d1f895c6fe | 494 | /** |
| mbed_official | 340:28d1f895c6fe | 495 | * @brief External Interrupt/Event Controller |
| mbed_official | 340:28d1f895c6fe | 496 | */ |
| mbed_official | 340:28d1f895c6fe | 497 | |
| mbed_official | 340:28d1f895c6fe | 498 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 499 | { |
| mbed_official | 340:28d1f895c6fe | 500 | __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 501 | __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 502 | __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 503 | __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 504 | __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 505 | __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 506 | } EXTI_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 507 | |
| mbed_official | 340:28d1f895c6fe | 508 | /** |
| mbed_official | 340:28d1f895c6fe | 509 | * @brief FLASH Registers |
| mbed_official | 340:28d1f895c6fe | 510 | */ |
| mbed_official | 340:28d1f895c6fe | 511 | |
| mbed_official | 340:28d1f895c6fe | 512 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 513 | { |
| mbed_official | 340:28d1f895c6fe | 514 | __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 515 | __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 516 | __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 517 | __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 518 | __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 519 | __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 520 | __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 521 | } FLASH_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 522 | |
| mbed_official | 340:28d1f895c6fe | 523 | /** |
| mbed_official | 340:28d1f895c6fe | 524 | * @brief Flexible Memory Controller |
| mbed_official | 340:28d1f895c6fe | 525 | */ |
| mbed_official | 340:28d1f895c6fe | 526 | |
| mbed_official | 340:28d1f895c6fe | 527 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 528 | { |
| mbed_official | 340:28d1f895c6fe | 529 | __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
| mbed_official | 340:28d1f895c6fe | 530 | } FMC_Bank1_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 531 | |
| mbed_official | 340:28d1f895c6fe | 532 | /** |
| mbed_official | 340:28d1f895c6fe | 533 | * @brief Flexible Memory Controller Bank1E |
| mbed_official | 340:28d1f895c6fe | 534 | */ |
| mbed_official | 340:28d1f895c6fe | 535 | |
| mbed_official | 340:28d1f895c6fe | 536 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 537 | { |
| mbed_official | 340:28d1f895c6fe | 538 | __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
| mbed_official | 340:28d1f895c6fe | 539 | } FMC_Bank1E_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 540 | |
| mbed_official | 340:28d1f895c6fe | 541 | /** |
| mbed_official | 340:28d1f895c6fe | 542 | * @brief Flexible Memory Controller Bank2 |
| mbed_official | 340:28d1f895c6fe | 543 | */ |
| mbed_official | 340:28d1f895c6fe | 544 | |
| mbed_official | 340:28d1f895c6fe | 545 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 546 | { |
| mbed_official | 340:28d1f895c6fe | 547 | __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ |
| mbed_official | 340:28d1f895c6fe | 548 | __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ |
| mbed_official | 340:28d1f895c6fe | 549 | __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ |
| mbed_official | 340:28d1f895c6fe | 550 | __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ |
| mbed_official | 340:28d1f895c6fe | 551 | uint32_t RESERVED0; /*!< Reserved, 0x70 */ |
| mbed_official | 340:28d1f895c6fe | 552 | __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ |
| mbed_official | 340:28d1f895c6fe | 553 | uint32_t RESERVED1; /*!< Reserved, 0x78 */ |
| mbed_official | 340:28d1f895c6fe | 554 | uint32_t RESERVED2; /*!< Reserved, 0x7C */ |
| mbed_official | 340:28d1f895c6fe | 555 | __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ |
| mbed_official | 340:28d1f895c6fe | 556 | __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ |
| mbed_official | 340:28d1f895c6fe | 557 | __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ |
| mbed_official | 340:28d1f895c6fe | 558 | __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ |
| mbed_official | 340:28d1f895c6fe | 559 | uint32_t RESERVED3; /*!< Reserved, 0x90 */ |
| mbed_official | 340:28d1f895c6fe | 560 | __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ |
| mbed_official | 340:28d1f895c6fe | 561 | } FMC_Bank2_3_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 562 | |
| mbed_official | 340:28d1f895c6fe | 563 | /** |
| mbed_official | 340:28d1f895c6fe | 564 | * @brief Flexible Memory Controller Bank4 |
| mbed_official | 340:28d1f895c6fe | 565 | */ |
| mbed_official | 340:28d1f895c6fe | 566 | |
| mbed_official | 340:28d1f895c6fe | 567 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 568 | { |
| mbed_official | 340:28d1f895c6fe | 569 | __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ |
| mbed_official | 340:28d1f895c6fe | 570 | __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ |
| mbed_official | 340:28d1f895c6fe | 571 | __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ |
| mbed_official | 340:28d1f895c6fe | 572 | __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ |
| mbed_official | 340:28d1f895c6fe | 573 | __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ |
| mbed_official | 340:28d1f895c6fe | 574 | } FMC_Bank4_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 575 | |
| mbed_official | 340:28d1f895c6fe | 576 | /** |
| mbed_official | 340:28d1f895c6fe | 577 | * @brief Flexible Memory Controller Bank5_6 |
| mbed_official | 340:28d1f895c6fe | 578 | */ |
| mbed_official | 340:28d1f895c6fe | 579 | |
| mbed_official | 340:28d1f895c6fe | 580 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 581 | { |
| mbed_official | 340:28d1f895c6fe | 582 | __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ |
| mbed_official | 340:28d1f895c6fe | 583 | __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ |
| mbed_official | 340:28d1f895c6fe | 584 | __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ |
| mbed_official | 340:28d1f895c6fe | 585 | __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ |
| mbed_official | 340:28d1f895c6fe | 586 | __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ |
| mbed_official | 340:28d1f895c6fe | 587 | } FMC_Bank5_6_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 588 | |
| mbed_official | 340:28d1f895c6fe | 589 | /** |
| mbed_official | 340:28d1f895c6fe | 590 | * @brief General Purpose I/O |
| mbed_official | 340:28d1f895c6fe | 591 | */ |
| mbed_official | 340:28d1f895c6fe | 592 | |
| mbed_official | 340:28d1f895c6fe | 593 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 594 | { |
| mbed_official | 340:28d1f895c6fe | 595 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 596 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 597 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 598 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 599 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 600 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| mbed_official | 532:fe11edbda85c | 601 | __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 602 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 603 | __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| mbed_official | 340:28d1f895c6fe | 604 | } GPIO_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 605 | |
| mbed_official | 340:28d1f895c6fe | 606 | /** |
| mbed_official | 340:28d1f895c6fe | 607 | * @brief System configuration controller |
| mbed_official | 340:28d1f895c6fe | 608 | */ |
| mbed_official | 340:28d1f895c6fe | 609 | |
| mbed_official | 340:28d1f895c6fe | 610 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 611 | { |
| mbed_official | 340:28d1f895c6fe | 612 | __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 613 | __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 614 | __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ |
| mbed_official | 340:28d1f895c6fe | 615 | uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ |
| mbed_official | 340:28d1f895c6fe | 616 | __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 617 | } SYSCFG_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 618 | |
| mbed_official | 340:28d1f895c6fe | 619 | /** |
| mbed_official | 340:28d1f895c6fe | 620 | * @brief Inter-integrated Circuit Interface |
| mbed_official | 340:28d1f895c6fe | 621 | */ |
| mbed_official | 340:28d1f895c6fe | 622 | |
| mbed_official | 340:28d1f895c6fe | 623 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 624 | { |
| mbed_official | 340:28d1f895c6fe | 625 | __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 626 | __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 627 | __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 628 | __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 629 | __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 630 | __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 631 | __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 632 | __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 633 | __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 634 | __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 635 | } I2C_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 636 | |
| mbed_official | 340:28d1f895c6fe | 637 | /** |
| mbed_official | 340:28d1f895c6fe | 638 | * @brief Independent WATCHDOG |
| mbed_official | 340:28d1f895c6fe | 639 | */ |
| mbed_official | 340:28d1f895c6fe | 640 | |
| mbed_official | 340:28d1f895c6fe | 641 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 642 | { |
| mbed_official | 340:28d1f895c6fe | 643 | __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 644 | __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 645 | __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 646 | __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 647 | } IWDG_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 648 | |
| mbed_official | 340:28d1f895c6fe | 649 | /** |
| mbed_official | 340:28d1f895c6fe | 650 | * @brief LCD-TFT Display Controller |
| mbed_official | 340:28d1f895c6fe | 651 | */ |
| mbed_official | 340:28d1f895c6fe | 652 | |
| mbed_official | 340:28d1f895c6fe | 653 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 654 | { |
| mbed_official | 340:28d1f895c6fe | 655 | uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ |
| mbed_official | 340:28d1f895c6fe | 656 | __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 657 | __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 658 | __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 659 | __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 660 | __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 661 | uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ |
| mbed_official | 340:28d1f895c6fe | 662 | __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 663 | uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ |
| mbed_official | 340:28d1f895c6fe | 664 | __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ |
| mbed_official | 340:28d1f895c6fe | 665 | uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ |
| mbed_official | 340:28d1f895c6fe | 666 | __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ |
| mbed_official | 340:28d1f895c6fe | 667 | __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ |
| mbed_official | 340:28d1f895c6fe | 668 | __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ |
| mbed_official | 340:28d1f895c6fe | 669 | __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ |
| mbed_official | 340:28d1f895c6fe | 670 | __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ |
| mbed_official | 340:28d1f895c6fe | 671 | __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ |
| mbed_official | 340:28d1f895c6fe | 672 | } LTDC_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 673 | |
| mbed_official | 340:28d1f895c6fe | 674 | /** |
| mbed_official | 340:28d1f895c6fe | 675 | * @brief LCD-TFT Display layer x Controller |
| mbed_official | 340:28d1f895c6fe | 676 | */ |
| mbed_official | 340:28d1f895c6fe | 677 | |
| mbed_official | 340:28d1f895c6fe | 678 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 679 | { |
| mbed_official | 340:28d1f895c6fe | 680 | __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ |
| mbed_official | 340:28d1f895c6fe | 681 | __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ |
| mbed_official | 340:28d1f895c6fe | 682 | __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ |
| mbed_official | 340:28d1f895c6fe | 683 | __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ |
| mbed_official | 340:28d1f895c6fe | 684 | __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ |
| mbed_official | 340:28d1f895c6fe | 685 | __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ |
| mbed_official | 340:28d1f895c6fe | 686 | __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ |
| mbed_official | 340:28d1f895c6fe | 687 | __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ |
| mbed_official | 340:28d1f895c6fe | 688 | uint32_t RESERVED0[2]; /*!< Reserved */ |
| mbed_official | 340:28d1f895c6fe | 689 | __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ |
| mbed_official | 340:28d1f895c6fe | 690 | __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ |
| mbed_official | 340:28d1f895c6fe | 691 | __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ |
| mbed_official | 340:28d1f895c6fe | 692 | uint32_t RESERVED1[3]; /*!< Reserved */ |
| mbed_official | 340:28d1f895c6fe | 693 | __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ |
| mbed_official | 340:28d1f895c6fe | 694 | |
| mbed_official | 340:28d1f895c6fe | 695 | } LTDC_Layer_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 696 | |
| mbed_official | 340:28d1f895c6fe | 697 | /** |
| mbed_official | 340:28d1f895c6fe | 698 | * @brief Power Control |
| mbed_official | 340:28d1f895c6fe | 699 | */ |
| mbed_official | 340:28d1f895c6fe | 700 | |
| mbed_official | 340:28d1f895c6fe | 701 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 702 | { |
| mbed_official | 340:28d1f895c6fe | 703 | __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 704 | __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 705 | } PWR_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 706 | |
| mbed_official | 340:28d1f895c6fe | 707 | /** |
| mbed_official | 340:28d1f895c6fe | 708 | * @brief Reset and Clock Control |
| mbed_official | 340:28d1f895c6fe | 709 | */ |
| mbed_official | 340:28d1f895c6fe | 710 | |
| mbed_official | 340:28d1f895c6fe | 711 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 712 | { |
| mbed_official | 340:28d1f895c6fe | 713 | __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 714 | __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 715 | __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 716 | __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 717 | __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 718 | __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 719 | __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 720 | uint32_t RESERVED0; /*!< Reserved, 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 721 | __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 722 | __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 723 | uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ |
| mbed_official | 340:28d1f895c6fe | 724 | __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ |
| mbed_official | 340:28d1f895c6fe | 725 | __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ |
| mbed_official | 340:28d1f895c6fe | 726 | __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ |
| mbed_official | 340:28d1f895c6fe | 727 | uint32_t RESERVED2; /*!< Reserved, 0x3C */ |
| mbed_official | 340:28d1f895c6fe | 728 | __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ |
| mbed_official | 340:28d1f895c6fe | 729 | __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ |
| mbed_official | 340:28d1f895c6fe | 730 | uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ |
| mbed_official | 340:28d1f895c6fe | 731 | __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ |
| mbed_official | 340:28d1f895c6fe | 732 | __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ |
| mbed_official | 340:28d1f895c6fe | 733 | __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ |
| mbed_official | 340:28d1f895c6fe | 734 | uint32_t RESERVED4; /*!< Reserved, 0x5C */ |
| mbed_official | 340:28d1f895c6fe | 735 | __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ |
| mbed_official | 340:28d1f895c6fe | 736 | __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ |
| mbed_official | 340:28d1f895c6fe | 737 | uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ |
| mbed_official | 340:28d1f895c6fe | 738 | __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ |
| mbed_official | 340:28d1f895c6fe | 739 | __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ |
| mbed_official | 340:28d1f895c6fe | 740 | uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ |
| mbed_official | 340:28d1f895c6fe | 741 | __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ |
| mbed_official | 340:28d1f895c6fe | 742 | __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ |
| mbed_official | 340:28d1f895c6fe | 743 | __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ |
| mbed_official | 340:28d1f895c6fe | 744 | __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ |
| mbed_official | 340:28d1f895c6fe | 745 | |
| mbed_official | 340:28d1f895c6fe | 746 | } RCC_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 747 | |
| mbed_official | 340:28d1f895c6fe | 748 | /** |
| mbed_official | 340:28d1f895c6fe | 749 | * @brief Real-Time Clock |
| mbed_official | 340:28d1f895c6fe | 750 | */ |
| mbed_official | 340:28d1f895c6fe | 751 | |
| mbed_official | 340:28d1f895c6fe | 752 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 753 | { |
| mbed_official | 340:28d1f895c6fe | 754 | __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 755 | __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 756 | __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 757 | __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 758 | __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 759 | __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 760 | __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 761 | __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 762 | __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 763 | __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 764 | __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| mbed_official | 340:28d1f895c6fe | 765 | __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| mbed_official | 340:28d1f895c6fe | 766 | __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| mbed_official | 340:28d1f895c6fe | 767 | __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| mbed_official | 340:28d1f895c6fe | 768 | __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| mbed_official | 340:28d1f895c6fe | 769 | __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| mbed_official | 340:28d1f895c6fe | 770 | __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ |
| mbed_official | 340:28d1f895c6fe | 771 | __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| mbed_official | 340:28d1f895c6fe | 772 | __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| mbed_official | 340:28d1f895c6fe | 773 | uint32_t RESERVED7; /*!< Reserved, 0x4C */ |
| mbed_official | 340:28d1f895c6fe | 774 | __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ |
| mbed_official | 340:28d1f895c6fe | 775 | __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| mbed_official | 340:28d1f895c6fe | 776 | __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| mbed_official | 340:28d1f895c6fe | 777 | __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| mbed_official | 340:28d1f895c6fe | 778 | __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| mbed_official | 340:28d1f895c6fe | 779 | __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
| mbed_official | 340:28d1f895c6fe | 780 | __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
| mbed_official | 340:28d1f895c6fe | 781 | __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
| mbed_official | 340:28d1f895c6fe | 782 | __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
| mbed_official | 340:28d1f895c6fe | 783 | __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
| mbed_official | 340:28d1f895c6fe | 784 | __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
| mbed_official | 340:28d1f895c6fe | 785 | __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
| mbed_official | 340:28d1f895c6fe | 786 | __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
| mbed_official | 340:28d1f895c6fe | 787 | __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
| mbed_official | 340:28d1f895c6fe | 788 | __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
| mbed_official | 340:28d1f895c6fe | 789 | __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
| mbed_official | 340:28d1f895c6fe | 790 | __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ |
| mbed_official | 340:28d1f895c6fe | 791 | __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ |
| mbed_official | 340:28d1f895c6fe | 792 | __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ |
| mbed_official | 340:28d1f895c6fe | 793 | __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ |
| mbed_official | 340:28d1f895c6fe | 794 | } RTC_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 795 | |
| mbed_official | 340:28d1f895c6fe | 796 | /** |
| mbed_official | 340:28d1f895c6fe | 797 | * @brief Serial Audio Interface |
| mbed_official | 340:28d1f895c6fe | 798 | */ |
| mbed_official | 340:28d1f895c6fe | 799 | |
| mbed_official | 340:28d1f895c6fe | 800 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 801 | { |
| mbed_official | 340:28d1f895c6fe | 802 | __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 803 | } SAI_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 804 | |
| mbed_official | 340:28d1f895c6fe | 805 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 806 | { |
| mbed_official | 340:28d1f895c6fe | 807 | __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 808 | __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 809 | __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 810 | __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 811 | __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 812 | __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 813 | __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 814 | __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 815 | } SAI_Block_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 816 | |
| mbed_official | 340:28d1f895c6fe | 817 | /** |
| mbed_official | 340:28d1f895c6fe | 818 | * @brief SD host Interface |
| mbed_official | 340:28d1f895c6fe | 819 | */ |
| mbed_official | 340:28d1f895c6fe | 820 | |
| mbed_official | 340:28d1f895c6fe | 821 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 822 | { |
| mbed_official | 340:28d1f895c6fe | 823 | __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 824 | __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 825 | __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 826 | __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 827 | __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 828 | __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 829 | __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 830 | __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 831 | __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 832 | __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 833 | __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ |
| mbed_official | 340:28d1f895c6fe | 834 | __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ |
| mbed_official | 340:28d1f895c6fe | 835 | __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ |
| mbed_official | 340:28d1f895c6fe | 836 | __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ |
| mbed_official | 340:28d1f895c6fe | 837 | __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ |
| mbed_official | 340:28d1f895c6fe | 838 | __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ |
| mbed_official | 340:28d1f895c6fe | 839 | uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ |
| mbed_official | 340:28d1f895c6fe | 840 | __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ |
| mbed_official | 340:28d1f895c6fe | 841 | uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ |
| mbed_official | 340:28d1f895c6fe | 842 | __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ |
| mbed_official | 340:28d1f895c6fe | 843 | } SDIO_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 844 | |
| mbed_official | 340:28d1f895c6fe | 845 | /** |
| mbed_official | 340:28d1f895c6fe | 846 | * @brief Serial Peripheral Interface |
| mbed_official | 340:28d1f895c6fe | 847 | */ |
| mbed_official | 340:28d1f895c6fe | 848 | |
| mbed_official | 340:28d1f895c6fe | 849 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 850 | { |
| mbed_official | 340:28d1f895c6fe | 851 | __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 852 | __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 853 | __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 854 | __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 855 | __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 856 | __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 857 | __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 858 | __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 859 | __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 860 | } SPI_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 861 | |
| mbed_official | 340:28d1f895c6fe | 862 | /** |
| mbed_official | 340:28d1f895c6fe | 863 | * @brief TIM |
| mbed_official | 340:28d1f895c6fe | 864 | */ |
| mbed_official | 340:28d1f895c6fe | 865 | |
| mbed_official | 340:28d1f895c6fe | 866 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 867 | { |
| mbed_official | 340:28d1f895c6fe | 868 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 869 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 870 | __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 871 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 872 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 873 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 874 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 875 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| mbed_official | 340:28d1f895c6fe | 876 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| mbed_official | 340:28d1f895c6fe | 877 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| mbed_official | 340:28d1f895c6fe | 878 | __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| mbed_official | 340:28d1f895c6fe | 879 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| mbed_official | 340:28d1f895c6fe | 880 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| mbed_official | 340:28d1f895c6fe | 881 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| mbed_official | 340:28d1f895c6fe | 882 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| mbed_official | 340:28d1f895c6fe | 883 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| mbed_official | 340:28d1f895c6fe | 884 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| mbed_official | 340:28d1f895c6fe | 885 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| mbed_official | 340:28d1f895c6fe | 886 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| mbed_official | 340:28d1f895c6fe | 887 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| mbed_official | 340:28d1f895c6fe | 888 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| mbed_official | 340:28d1f895c6fe | 889 | } TIM_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 890 | |
| mbed_official | 340:28d1f895c6fe | 891 | /** |
| mbed_official | 340:28d1f895c6fe | 892 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| mbed_official | 340:28d1f895c6fe | 893 | */ |
| mbed_official | 340:28d1f895c6fe | 894 | |
| mbed_official | 340:28d1f895c6fe | 895 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 896 | { |
| mbed_official | 340:28d1f895c6fe | 897 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 898 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 899 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 900 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
| mbed_official | 340:28d1f895c6fe | 901 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
| mbed_official | 340:28d1f895c6fe | 902 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
| mbed_official | 340:28d1f895c6fe | 903 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
| mbed_official | 340:28d1f895c6fe | 904 | } USART_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 905 | |
| mbed_official | 340:28d1f895c6fe | 906 | /** |
| mbed_official | 340:28d1f895c6fe | 907 | * @brief Window WATCHDOG |
| mbed_official | 340:28d1f895c6fe | 908 | */ |
| mbed_official | 340:28d1f895c6fe | 909 | |
| mbed_official | 340:28d1f895c6fe | 910 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 911 | { |
| mbed_official | 340:28d1f895c6fe | 912 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 913 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 914 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 915 | } WWDG_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 916 | |
| mbed_official | 340:28d1f895c6fe | 917 | |
| mbed_official | 340:28d1f895c6fe | 918 | /** |
| mbed_official | 340:28d1f895c6fe | 919 | * @brief RNG |
| mbed_official | 340:28d1f895c6fe | 920 | */ |
| mbed_official | 340:28d1f895c6fe | 921 | |
| mbed_official | 340:28d1f895c6fe | 922 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 923 | { |
| mbed_official | 340:28d1f895c6fe | 924 | __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ |
| mbed_official | 340:28d1f895c6fe | 925 | __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ |
| mbed_official | 340:28d1f895c6fe | 926 | __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ |
| mbed_official | 340:28d1f895c6fe | 927 | } RNG_TypeDef; |
| mbed_official | 340:28d1f895c6fe | 928 | |
| mbed_official | 340:28d1f895c6fe | 929 | |
| mbed_official | 340:28d1f895c6fe | 930 | /** |
| mbed_official | 340:28d1f895c6fe | 931 | * @brief __USB_OTG_Core_register |
| mbed_official | 340:28d1f895c6fe | 932 | */ |
| mbed_official | 340:28d1f895c6fe | 933 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 934 | { |
| mbed_official | 340:28d1f895c6fe | 935 | __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ |
| mbed_official | 340:28d1f895c6fe | 936 | __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ |
| mbed_official | 340:28d1f895c6fe | 937 | __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ |
| mbed_official | 340:28d1f895c6fe | 938 | __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ |
| mbed_official | 340:28d1f895c6fe | 939 | __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ |
| mbed_official | 340:28d1f895c6fe | 940 | __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ |
| mbed_official | 340:28d1f895c6fe | 941 | __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ |
| mbed_official | 340:28d1f895c6fe | 942 | __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ |
| mbed_official | 340:28d1f895c6fe | 943 | __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ |
| mbed_official | 340:28d1f895c6fe | 944 | __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */ |
| mbed_official | 340:28d1f895c6fe | 945 | __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ |
| mbed_official | 340:28d1f895c6fe | 946 | __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ |
| mbed_official | 340:28d1f895c6fe | 947 | uint32_t Reserved30[2]; /* Reserved 030h*/ |
| mbed_official | 340:28d1f895c6fe | 948 | __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ |
| mbed_official | 340:28d1f895c6fe | 949 | __IO uint32_t CID; /* User ID Register 03Ch*/ |
| mbed_official | 340:28d1f895c6fe | 950 | uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ |
| mbed_official | 340:28d1f895c6fe | 951 | __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ |
| mbed_official | 340:28d1f895c6fe | 952 | __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */ |
| mbed_official | 340:28d1f895c6fe | 953 | } |
| mbed_official | 340:28d1f895c6fe | 954 | USB_OTG_GlobalTypeDef; |
| mbed_official | 340:28d1f895c6fe | 955 | |
| mbed_official | 340:28d1f895c6fe | 956 | |
| mbed_official | 340:28d1f895c6fe | 957 | /** |
| mbed_official | 340:28d1f895c6fe | 958 | * @brief __device_Registers |
| mbed_official | 340:28d1f895c6fe | 959 | */ |
| mbed_official | 340:28d1f895c6fe | 960 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 961 | { |
| mbed_official | 340:28d1f895c6fe | 962 | __IO uint32_t DCFG; /* dev Configuration Register 800h*/ |
| mbed_official | 340:28d1f895c6fe | 963 | __IO uint32_t DCTL; /* dev Control Register 804h*/ |
| mbed_official | 340:28d1f895c6fe | 964 | __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ |
| mbed_official | 340:28d1f895c6fe | 965 | uint32_t Reserved0C; /* Reserved 80Ch*/ |
| mbed_official | 340:28d1f895c6fe | 966 | __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ |
| mbed_official | 340:28d1f895c6fe | 967 | __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ |
| mbed_official | 340:28d1f895c6fe | 968 | __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ |
| mbed_official | 340:28d1f895c6fe | 969 | __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ |
| mbed_official | 340:28d1f895c6fe | 970 | uint32_t Reserved20; /* Reserved 820h*/ |
| mbed_official | 340:28d1f895c6fe | 971 | uint32_t Reserved9; /* Reserved 824h*/ |
| mbed_official | 340:28d1f895c6fe | 972 | __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ |
| mbed_official | 340:28d1f895c6fe | 973 | __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ |
| mbed_official | 340:28d1f895c6fe | 974 | __IO uint32_t DTHRCTL; /* dev thr 830h*/ |
| mbed_official | 340:28d1f895c6fe | 975 | __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ |
| mbed_official | 340:28d1f895c6fe | 976 | __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ |
| mbed_official | 340:28d1f895c6fe | 977 | __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ |
| mbed_official | 340:28d1f895c6fe | 978 | uint32_t Reserved40; /* dedicated EP mask 840h*/ |
| mbed_official | 340:28d1f895c6fe | 979 | __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ |
| mbed_official | 340:28d1f895c6fe | 980 | uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ |
| mbed_official | 340:28d1f895c6fe | 981 | __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ |
| mbed_official | 340:28d1f895c6fe | 982 | } |
| mbed_official | 340:28d1f895c6fe | 983 | USB_OTG_DeviceTypeDef; |
| mbed_official | 340:28d1f895c6fe | 984 | |
| mbed_official | 340:28d1f895c6fe | 985 | |
| mbed_official | 340:28d1f895c6fe | 986 | /** |
| mbed_official | 340:28d1f895c6fe | 987 | * @brief __IN_Endpoint-Specific_Register |
| mbed_official | 340:28d1f895c6fe | 988 | */ |
| mbed_official | 340:28d1f895c6fe | 989 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 990 | { |
| mbed_official | 340:28d1f895c6fe | 991 | __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ |
| mbed_official | 340:28d1f895c6fe | 992 | uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ |
| mbed_official | 340:28d1f895c6fe | 993 | __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ |
| mbed_official | 340:28d1f895c6fe | 994 | uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ |
| mbed_official | 340:28d1f895c6fe | 995 | __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ |
| mbed_official | 340:28d1f895c6fe | 996 | __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ |
| mbed_official | 340:28d1f895c6fe | 997 | __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ |
| mbed_official | 340:28d1f895c6fe | 998 | uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ |
| mbed_official | 340:28d1f895c6fe | 999 | } |
| mbed_official | 340:28d1f895c6fe | 1000 | USB_OTG_INEndpointTypeDef; |
| mbed_official | 340:28d1f895c6fe | 1001 | |
| mbed_official | 340:28d1f895c6fe | 1002 | |
| mbed_official | 340:28d1f895c6fe | 1003 | /** |
| mbed_official | 340:28d1f895c6fe | 1004 | * @brief __OUT_Endpoint-Specific_Registers |
| mbed_official | 340:28d1f895c6fe | 1005 | */ |
| mbed_official | 340:28d1f895c6fe | 1006 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 1007 | { |
| mbed_official | 340:28d1f895c6fe | 1008 | __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ |
| mbed_official | 340:28d1f895c6fe | 1009 | uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ |
| mbed_official | 340:28d1f895c6fe | 1010 | __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ |
| mbed_official | 340:28d1f895c6fe | 1011 | uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ |
| mbed_official | 340:28d1f895c6fe | 1012 | __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ |
| mbed_official | 340:28d1f895c6fe | 1013 | __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ |
| mbed_official | 340:28d1f895c6fe | 1014 | uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ |
| mbed_official | 340:28d1f895c6fe | 1015 | } |
| mbed_official | 340:28d1f895c6fe | 1016 | USB_OTG_OUTEndpointTypeDef; |
| mbed_official | 340:28d1f895c6fe | 1017 | |
| mbed_official | 340:28d1f895c6fe | 1018 | |
| mbed_official | 340:28d1f895c6fe | 1019 | /** |
| mbed_official | 340:28d1f895c6fe | 1020 | * @brief __Host_Mode_Register_Structures |
| mbed_official | 340:28d1f895c6fe | 1021 | */ |
| mbed_official | 340:28d1f895c6fe | 1022 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 1023 | { |
| mbed_official | 340:28d1f895c6fe | 1024 | __IO uint32_t HCFG; /* Host Configuration Register 400h*/ |
| mbed_official | 340:28d1f895c6fe | 1025 | __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ |
| mbed_official | 340:28d1f895c6fe | 1026 | __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ |
| mbed_official | 340:28d1f895c6fe | 1027 | uint32_t Reserved40C; /* Reserved 40Ch*/ |
| mbed_official | 340:28d1f895c6fe | 1028 | __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ |
| mbed_official | 340:28d1f895c6fe | 1029 | __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ |
| mbed_official | 340:28d1f895c6fe | 1030 | __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ |
| mbed_official | 340:28d1f895c6fe | 1031 | } |
| mbed_official | 340:28d1f895c6fe | 1032 | USB_OTG_HostTypeDef; |
| mbed_official | 340:28d1f895c6fe | 1033 | |
| mbed_official | 340:28d1f895c6fe | 1034 | /** |
| mbed_official | 340:28d1f895c6fe | 1035 | * @brief __Host_Channel_Specific_Registers |
| mbed_official | 340:28d1f895c6fe | 1036 | */ |
| mbed_official | 340:28d1f895c6fe | 1037 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 1038 | { |
| mbed_official | 340:28d1f895c6fe | 1039 | __IO uint32_t HCCHAR; |
| mbed_official | 340:28d1f895c6fe | 1040 | __IO uint32_t HCSPLT; |
| mbed_official | 340:28d1f895c6fe | 1041 | __IO uint32_t HCINT; |
| mbed_official | 340:28d1f895c6fe | 1042 | __IO uint32_t HCINTMSK; |
| mbed_official | 340:28d1f895c6fe | 1043 | __IO uint32_t HCTSIZ; |
| mbed_official | 340:28d1f895c6fe | 1044 | __IO uint32_t HCDMA; |
| mbed_official | 340:28d1f895c6fe | 1045 | uint32_t Reserved[2]; |
| mbed_official | 340:28d1f895c6fe | 1046 | } |
| mbed_official | 340:28d1f895c6fe | 1047 | USB_OTG_HostChannelTypeDef; |
| mbed_official | 340:28d1f895c6fe | 1048 | /** |
| mbed_official | 340:28d1f895c6fe | 1049 | * @} |
| mbed_official | 340:28d1f895c6fe | 1050 | */ |
| mbed_official | 340:28d1f895c6fe | 1051 | |
| mbed_official | 340:28d1f895c6fe | 1052 | /** @addtogroup Peripheral_memory_map |
| mbed_official | 340:28d1f895c6fe | 1053 | * @{ |
| mbed_official | 340:28d1f895c6fe | 1054 | */ |
| mbed_official | 340:28d1f895c6fe | 1055 | #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region */ |
| mbed_official | 340:28d1f895c6fe | 1056 | #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ |
| mbed_official | 340:28d1f895c6fe | 1057 | #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ |
| mbed_official | 340:28d1f895c6fe | 1058 | #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ |
| mbed_official | 340:28d1f895c6fe | 1059 | #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ |
| mbed_official | 340:28d1f895c6fe | 1060 | #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
| mbed_official | 340:28d1f895c6fe | 1061 | #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ |
| mbed_official | 340:28d1f895c6fe | 1062 | #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ |
| mbed_official | 340:28d1f895c6fe | 1063 | #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ |
| mbed_official | 613:bc40b8d2aec4 | 1064 | #define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ |
| mbed_official | 613:bc40b8d2aec4 | 1065 | #define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ |
| mbed_official | 340:28d1f895c6fe | 1066 | #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
| mbed_official | 613:bc40b8d2aec4 | 1067 | #define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ |
| mbed_official | 340:28d1f895c6fe | 1068 | #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */ |
| mbed_official | 340:28d1f895c6fe | 1069 | #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ |
| mbed_official | 340:28d1f895c6fe | 1070 | |
| mbed_official | 340:28d1f895c6fe | 1071 | /* Legacy defines */ |
| mbed_official | 340:28d1f895c6fe | 1072 | #define SRAM_BASE SRAM1_BASE |
| mbed_official | 340:28d1f895c6fe | 1073 | #define SRAM_BB_BASE SRAM1_BB_BASE |
| mbed_official | 340:28d1f895c6fe | 1074 | |
| mbed_official | 340:28d1f895c6fe | 1075 | |
| mbed_official | 340:28d1f895c6fe | 1076 | /*!< Peripheral memory map */ |
| mbed_official | 340:28d1f895c6fe | 1077 | #define APB1PERIPH_BASE PERIPH_BASE |
| mbed_official | 340:28d1f895c6fe | 1078 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) |
| mbed_official | 340:28d1f895c6fe | 1079 | #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) |
| mbed_official | 340:28d1f895c6fe | 1080 | #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) |
| mbed_official | 340:28d1f895c6fe | 1081 | |
| mbed_official | 340:28d1f895c6fe | 1082 | /*!< APB1 peripherals */ |
| mbed_official | 340:28d1f895c6fe | 1083 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| mbed_official | 340:28d1f895c6fe | 1084 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| mbed_official | 340:28d1f895c6fe | 1085 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| mbed_official | 340:28d1f895c6fe | 1086 | #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| mbed_official | 340:28d1f895c6fe | 1087 | #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| mbed_official | 340:28d1f895c6fe | 1088 | #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| mbed_official | 340:28d1f895c6fe | 1089 | #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| mbed_official | 340:28d1f895c6fe | 1090 | #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| mbed_official | 340:28d1f895c6fe | 1091 | #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| mbed_official | 340:28d1f895c6fe | 1092 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| mbed_official | 340:28d1f895c6fe | 1093 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| mbed_official | 340:28d1f895c6fe | 1094 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| mbed_official | 340:28d1f895c6fe | 1095 | #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) |
| mbed_official | 340:28d1f895c6fe | 1096 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| mbed_official | 340:28d1f895c6fe | 1097 | #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| mbed_official | 340:28d1f895c6fe | 1098 | #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) |
| mbed_official | 340:28d1f895c6fe | 1099 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| mbed_official | 340:28d1f895c6fe | 1100 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| mbed_official | 340:28d1f895c6fe | 1101 | #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| mbed_official | 340:28d1f895c6fe | 1102 | #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| mbed_official | 340:28d1f895c6fe | 1103 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| mbed_official | 340:28d1f895c6fe | 1104 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| mbed_official | 340:28d1f895c6fe | 1105 | #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) |
| mbed_official | 340:28d1f895c6fe | 1106 | #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| mbed_official | 340:28d1f895c6fe | 1107 | #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| mbed_official | 340:28d1f895c6fe | 1108 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| mbed_official | 340:28d1f895c6fe | 1109 | #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| mbed_official | 340:28d1f895c6fe | 1110 | #define UART7_BASE (APB1PERIPH_BASE + 0x7800) |
| mbed_official | 340:28d1f895c6fe | 1111 | #define UART8_BASE (APB1PERIPH_BASE + 0x7C00) |
| mbed_official | 340:28d1f895c6fe | 1112 | |
| mbed_official | 340:28d1f895c6fe | 1113 | /*!< APB2 peripherals */ |
| mbed_official | 340:28d1f895c6fe | 1114 | #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) |
| mbed_official | 340:28d1f895c6fe | 1115 | #define TIM8_BASE (APB2PERIPH_BASE + 0x0400) |
| mbed_official | 340:28d1f895c6fe | 1116 | #define USART1_BASE (APB2PERIPH_BASE + 0x1000) |
| mbed_official | 340:28d1f895c6fe | 1117 | #define USART6_BASE (APB2PERIPH_BASE + 0x1400) |
| mbed_official | 340:28d1f895c6fe | 1118 | #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) |
| mbed_official | 340:28d1f895c6fe | 1119 | #define ADC2_BASE (APB2PERIPH_BASE + 0x2100) |
| mbed_official | 340:28d1f895c6fe | 1120 | #define ADC3_BASE (APB2PERIPH_BASE + 0x2200) |
| mbed_official | 340:28d1f895c6fe | 1121 | #define ADC_BASE (APB2PERIPH_BASE + 0x2300) |
| mbed_official | 340:28d1f895c6fe | 1122 | #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) |
| mbed_official | 340:28d1f895c6fe | 1123 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| mbed_official | 340:28d1f895c6fe | 1124 | #define SPI4_BASE (APB2PERIPH_BASE + 0x3400) |
| mbed_official | 340:28d1f895c6fe | 1125 | #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) |
| mbed_official | 340:28d1f895c6fe | 1126 | #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) |
| mbed_official | 340:28d1f895c6fe | 1127 | #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) |
| mbed_official | 340:28d1f895c6fe | 1128 | #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) |
| mbed_official | 340:28d1f895c6fe | 1129 | #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) |
| mbed_official | 340:28d1f895c6fe | 1130 | #define SPI5_BASE (APB2PERIPH_BASE + 0x5000) |
| mbed_official | 340:28d1f895c6fe | 1131 | #define SPI6_BASE (APB2PERIPH_BASE + 0x5400) |
| mbed_official | 340:28d1f895c6fe | 1132 | #define SAI1_BASE (APB2PERIPH_BASE + 0x5800) |
| mbed_official | 340:28d1f895c6fe | 1133 | #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) |
| mbed_official | 340:28d1f895c6fe | 1134 | #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) |
| mbed_official | 340:28d1f895c6fe | 1135 | #define LTDC_BASE (APB2PERIPH_BASE + 0x6800) |
| mbed_official | 340:28d1f895c6fe | 1136 | #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) |
| mbed_official | 340:28d1f895c6fe | 1137 | #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) |
| mbed_official | 340:28d1f895c6fe | 1138 | |
| mbed_official | 340:28d1f895c6fe | 1139 | /*!< AHB1 peripherals */ |
| mbed_official | 340:28d1f895c6fe | 1140 | #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) |
| mbed_official | 340:28d1f895c6fe | 1141 | #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) |
| mbed_official | 340:28d1f895c6fe | 1142 | #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) |
| mbed_official | 340:28d1f895c6fe | 1143 | #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) |
| mbed_official | 340:28d1f895c6fe | 1144 | #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) |
| mbed_official | 340:28d1f895c6fe | 1145 | #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) |
| mbed_official | 340:28d1f895c6fe | 1146 | #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) |
| mbed_official | 340:28d1f895c6fe | 1147 | #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) |
| mbed_official | 340:28d1f895c6fe | 1148 | #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) |
| mbed_official | 340:28d1f895c6fe | 1149 | #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) |
| mbed_official | 340:28d1f895c6fe | 1150 | #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) |
| mbed_official | 340:28d1f895c6fe | 1151 | #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) |
| mbed_official | 340:28d1f895c6fe | 1152 | #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) |
| mbed_official | 340:28d1f895c6fe | 1153 | #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) |
| mbed_official | 340:28d1f895c6fe | 1154 | #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) |
| mbed_official | 340:28d1f895c6fe | 1155 | #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) |
| mbed_official | 340:28d1f895c6fe | 1156 | #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) |
| mbed_official | 340:28d1f895c6fe | 1157 | #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) |
| mbed_official | 340:28d1f895c6fe | 1158 | #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) |
| mbed_official | 340:28d1f895c6fe | 1159 | #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) |
| mbed_official | 340:28d1f895c6fe | 1160 | #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) |
| mbed_official | 340:28d1f895c6fe | 1161 | #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) |
| mbed_official | 340:28d1f895c6fe | 1162 | #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) |
| mbed_official | 340:28d1f895c6fe | 1163 | #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) |
| mbed_official | 340:28d1f895c6fe | 1164 | #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) |
| mbed_official | 340:28d1f895c6fe | 1165 | #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) |
| mbed_official | 340:28d1f895c6fe | 1166 | #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) |
| mbed_official | 340:28d1f895c6fe | 1167 | #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) |
| mbed_official | 340:28d1f895c6fe | 1168 | #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) |
| mbed_official | 340:28d1f895c6fe | 1169 | #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) |
| mbed_official | 340:28d1f895c6fe | 1170 | #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) |
| mbed_official | 340:28d1f895c6fe | 1171 | #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) |
| mbed_official | 340:28d1f895c6fe | 1172 | #define ETH_BASE (AHB1PERIPH_BASE + 0x8000) |
| mbed_official | 340:28d1f895c6fe | 1173 | #define ETH_MAC_BASE (ETH_BASE) |
| mbed_official | 340:28d1f895c6fe | 1174 | #define ETH_MMC_BASE (ETH_BASE + 0x0100) |
| mbed_official | 340:28d1f895c6fe | 1175 | #define ETH_PTP_BASE (ETH_BASE + 0x0700) |
| mbed_official | 340:28d1f895c6fe | 1176 | #define ETH_DMA_BASE (ETH_BASE + 0x1000) |
| mbed_official | 340:28d1f895c6fe | 1177 | #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) |
| mbed_official | 340:28d1f895c6fe | 1178 | |
| mbed_official | 340:28d1f895c6fe | 1179 | /*!< AHB2 peripherals */ |
| mbed_official | 340:28d1f895c6fe | 1180 | #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) |
| mbed_official | 340:28d1f895c6fe | 1181 | #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) |
| mbed_official | 340:28d1f895c6fe | 1182 | |
| mbed_official | 340:28d1f895c6fe | 1183 | /*!< FMC Bankx registers base address */ |
| mbed_official | 340:28d1f895c6fe | 1184 | #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) |
| mbed_official | 340:28d1f895c6fe | 1185 | #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) |
| mbed_official | 340:28d1f895c6fe | 1186 | #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060) |
| mbed_official | 340:28d1f895c6fe | 1187 | #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) |
| mbed_official | 340:28d1f895c6fe | 1188 | #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) |
| mbed_official | 340:28d1f895c6fe | 1189 | |
| mbed_official | 340:28d1f895c6fe | 1190 | /* Debug MCU registers base address */ |
| mbed_official | 340:28d1f895c6fe | 1191 | #define DBGMCU_BASE ((uint32_t )0xE0042000) |
| mbed_official | 340:28d1f895c6fe | 1192 | |
| mbed_official | 340:28d1f895c6fe | 1193 | /*!< USB registers base address */ |
| mbed_official | 340:28d1f895c6fe | 1194 | #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) |
| mbed_official | 340:28d1f895c6fe | 1195 | #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) |
| mbed_official | 340:28d1f895c6fe | 1196 | |
| mbed_official | 340:28d1f895c6fe | 1197 | #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) |
| mbed_official | 340:28d1f895c6fe | 1198 | #define USB_OTG_DEVICE_BASE ((uint32_t )0x800) |
| mbed_official | 340:28d1f895c6fe | 1199 | #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) |
| mbed_official | 340:28d1f895c6fe | 1200 | #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) |
| mbed_official | 340:28d1f895c6fe | 1201 | #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) |
| mbed_official | 340:28d1f895c6fe | 1202 | #define USB_OTG_HOST_BASE ((uint32_t )0x400) |
| mbed_official | 340:28d1f895c6fe | 1203 | #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) |
| mbed_official | 340:28d1f895c6fe | 1204 | #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) |
| mbed_official | 340:28d1f895c6fe | 1205 | #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) |
| mbed_official | 340:28d1f895c6fe | 1206 | #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) |
| mbed_official | 340:28d1f895c6fe | 1207 | #define USB_OTG_FIFO_BASE ((uint32_t )0x1000) |
| mbed_official | 340:28d1f895c6fe | 1208 | #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) |
| mbed_official | 340:28d1f895c6fe | 1209 | |
| mbed_official | 340:28d1f895c6fe | 1210 | /** |
| mbed_official | 340:28d1f895c6fe | 1211 | * @} |
| mbed_official | 340:28d1f895c6fe | 1212 | */ |
| mbed_official | 340:28d1f895c6fe | 1213 | |
| mbed_official | 340:28d1f895c6fe | 1214 | /** @addtogroup Peripheral_declaration |
| mbed_official | 340:28d1f895c6fe | 1215 | * @{ |
| mbed_official | 340:28d1f895c6fe | 1216 | */ |
| mbed_official | 340:28d1f895c6fe | 1217 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1218 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| mbed_official | 340:28d1f895c6fe | 1219 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| mbed_official | 340:28d1f895c6fe | 1220 | #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
| mbed_official | 340:28d1f895c6fe | 1221 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| mbed_official | 340:28d1f895c6fe | 1222 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| mbed_official | 340:28d1f895c6fe | 1223 | #define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
| mbed_official | 340:28d1f895c6fe | 1224 | #define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
| mbed_official | 340:28d1f895c6fe | 1225 | #define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
| mbed_official | 340:28d1f895c6fe | 1226 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
| mbed_official | 340:28d1f895c6fe | 1227 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| mbed_official | 340:28d1f895c6fe | 1228 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| mbed_official | 340:28d1f895c6fe | 1229 | #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) |
| mbed_official | 340:28d1f895c6fe | 1230 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1231 | #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| mbed_official | 340:28d1f895c6fe | 1232 | #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) |
| mbed_official | 340:28d1f895c6fe | 1233 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1234 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
| mbed_official | 340:28d1f895c6fe | 1235 | #define UART4 ((USART_TypeDef *) UART4_BASE) |
| mbed_official | 340:28d1f895c6fe | 1236 | #define UART5 ((USART_TypeDef *) UART5_BASE) |
| mbed_official | 340:28d1f895c6fe | 1237 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1238 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1239 | #define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
| mbed_official | 340:28d1f895c6fe | 1240 | #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1241 | #define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1242 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
| mbed_official | 340:28d1f895c6fe | 1243 | #define DAC ((DAC_TypeDef *) DAC_BASE) |
| mbed_official | 340:28d1f895c6fe | 1244 | #define UART7 ((USART_TypeDef *) UART7_BASE) |
| mbed_official | 340:28d1f895c6fe | 1245 | #define UART8 ((USART_TypeDef *) UART8_BASE) |
| mbed_official | 340:28d1f895c6fe | 1246 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1247 | #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
| mbed_official | 340:28d1f895c6fe | 1248 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1249 | #define USART6 ((USART_TypeDef *) USART6_BASE) |
| mbed_official | 340:28d1f895c6fe | 1250 | #define ADC ((ADC_Common_TypeDef *) ADC_BASE) |
| mbed_official | 340:28d1f895c6fe | 1251 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1252 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1253 | #define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
| mbed_official | 340:28d1f895c6fe | 1254 | #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
| mbed_official | 340:28d1f895c6fe | 1255 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1256 | #define SPI4 ((SPI_TypeDef *) SPI4_BASE) |
| mbed_official | 340:28d1f895c6fe | 1257 | #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| mbed_official | 340:28d1f895c6fe | 1258 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| mbed_official | 340:28d1f895c6fe | 1259 | #define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
| mbed_official | 340:28d1f895c6fe | 1260 | #define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
| mbed_official | 340:28d1f895c6fe | 1261 | #define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
| mbed_official | 340:28d1f895c6fe | 1262 | #define SPI5 ((SPI_TypeDef *) SPI5_BASE) |
| mbed_official | 340:28d1f895c6fe | 1263 | #define SPI6 ((SPI_TypeDef *) SPI6_BASE) |
| mbed_official | 340:28d1f895c6fe | 1264 | #define SAI1 ((SAI_TypeDef *) SAI1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1265 | #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
| mbed_official | 340:28d1f895c6fe | 1266 | #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
| mbed_official | 340:28d1f895c6fe | 1267 | #define LTDC ((LTDC_TypeDef *)LTDC_BASE) |
| mbed_official | 340:28d1f895c6fe | 1268 | #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1269 | #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1270 | |
| mbed_official | 340:28d1f895c6fe | 1271 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| mbed_official | 340:28d1f895c6fe | 1272 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| mbed_official | 340:28d1f895c6fe | 1273 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| mbed_official | 340:28d1f895c6fe | 1274 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| mbed_official | 340:28d1f895c6fe | 1275 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| mbed_official | 340:28d1f895c6fe | 1276 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| mbed_official | 340:28d1f895c6fe | 1277 | #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
| mbed_official | 340:28d1f895c6fe | 1278 | #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
| mbed_official | 340:28d1f895c6fe | 1279 | #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
| mbed_official | 340:28d1f895c6fe | 1280 | #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) |
| mbed_official | 340:28d1f895c6fe | 1281 | #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) |
| mbed_official | 340:28d1f895c6fe | 1282 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
| mbed_official | 340:28d1f895c6fe | 1283 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
| mbed_official | 340:28d1f895c6fe | 1284 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| mbed_official | 340:28d1f895c6fe | 1285 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1286 | #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) |
| mbed_official | 340:28d1f895c6fe | 1287 | #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1288 | #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1289 | #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) |
| mbed_official | 340:28d1f895c6fe | 1290 | #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) |
| mbed_official | 340:28d1f895c6fe | 1291 | #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) |
| mbed_official | 340:28d1f895c6fe | 1292 | #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) |
| mbed_official | 340:28d1f895c6fe | 1293 | #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) |
| mbed_official | 340:28d1f895c6fe | 1294 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1295 | #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) |
| mbed_official | 340:28d1f895c6fe | 1296 | #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) |
| mbed_official | 340:28d1f895c6fe | 1297 | #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) |
| mbed_official | 340:28d1f895c6fe | 1298 | #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) |
| mbed_official | 340:28d1f895c6fe | 1299 | #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) |
| mbed_official | 340:28d1f895c6fe | 1300 | #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) |
| mbed_official | 340:28d1f895c6fe | 1301 | #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) |
| mbed_official | 340:28d1f895c6fe | 1302 | #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) |
| mbed_official | 340:28d1f895c6fe | 1303 | #define ETH ((ETH_TypeDef *) ETH_BASE) |
| mbed_official | 340:28d1f895c6fe | 1304 | #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) |
| mbed_official | 340:28d1f895c6fe | 1305 | #define DCMI ((DCMI_TypeDef *) DCMI_BASE) |
| mbed_official | 340:28d1f895c6fe | 1306 | #define RNG ((RNG_TypeDef *) RNG_BASE) |
| mbed_official | 340:28d1f895c6fe | 1307 | #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) |
| mbed_official | 340:28d1f895c6fe | 1308 | #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) |
| mbed_official | 340:28d1f895c6fe | 1309 | #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE) |
| mbed_official | 340:28d1f895c6fe | 1310 | #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) |
| mbed_official | 340:28d1f895c6fe | 1311 | #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) |
| mbed_official | 340:28d1f895c6fe | 1312 | |
| mbed_official | 340:28d1f895c6fe | 1313 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| mbed_official | 340:28d1f895c6fe | 1314 | |
| mbed_official | 340:28d1f895c6fe | 1315 | #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
| mbed_official | 340:28d1f895c6fe | 1316 | #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) |
| mbed_official | 340:28d1f895c6fe | 1317 | |
| mbed_official | 340:28d1f895c6fe | 1318 | /** |
| mbed_official | 340:28d1f895c6fe | 1319 | * @} |
| mbed_official | 340:28d1f895c6fe | 1320 | */ |
| mbed_official | 340:28d1f895c6fe | 1321 | |
| mbed_official | 340:28d1f895c6fe | 1322 | /** @addtogroup Exported_constants |
| mbed_official | 340:28d1f895c6fe | 1323 | * @{ |
| mbed_official | 340:28d1f895c6fe | 1324 | */ |
| mbed_official | 340:28d1f895c6fe | 1325 | |
| mbed_official | 340:28d1f895c6fe | 1326 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| mbed_official | 340:28d1f895c6fe | 1327 | * @{ |
| mbed_official | 340:28d1f895c6fe | 1328 | */ |
| mbed_official | 340:28d1f895c6fe | 1329 | |
| mbed_official | 340:28d1f895c6fe | 1330 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 1331 | /* Peripheral Registers_Bits_Definition */ |
| mbed_official | 340:28d1f895c6fe | 1332 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 1333 | |
| mbed_official | 340:28d1f895c6fe | 1334 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 1335 | /* */ |
| mbed_official | 340:28d1f895c6fe | 1336 | /* Analog to Digital Converter */ |
| mbed_official | 340:28d1f895c6fe | 1337 | /* */ |
| mbed_official | 340:28d1f895c6fe | 1338 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 1339 | /******************** Bit definition for ADC_SR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1340 | #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */ |
| mbed_official | 340:28d1f895c6fe | 1341 | #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */ |
| mbed_official | 340:28d1f895c6fe | 1342 | #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */ |
| mbed_official | 340:28d1f895c6fe | 1343 | #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */ |
| mbed_official | 340:28d1f895c6fe | 1344 | #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */ |
| mbed_official | 340:28d1f895c6fe | 1345 | #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */ |
| mbed_official | 340:28d1f895c6fe | 1346 | |
| mbed_official | 340:28d1f895c6fe | 1347 | /******************* Bit definition for ADC_CR1 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1348 | #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
| mbed_official | 340:28d1f895c6fe | 1349 | #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1350 | #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1351 | #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1352 | #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1353 | #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1354 | #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */ |
| mbed_official | 340:28d1f895c6fe | 1355 | #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 1356 | #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */ |
| mbed_official | 340:28d1f895c6fe | 1357 | #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */ |
| mbed_official | 340:28d1f895c6fe | 1358 | #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */ |
| mbed_official | 340:28d1f895c6fe | 1359 | #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */ |
| mbed_official | 340:28d1f895c6fe | 1360 | #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */ |
| mbed_official | 340:28d1f895c6fe | 1361 | #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */ |
| mbed_official | 340:28d1f895c6fe | 1362 | #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
| mbed_official | 340:28d1f895c6fe | 1363 | #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1364 | #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1365 | #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1366 | #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */ |
| mbed_official | 340:28d1f895c6fe | 1367 | #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */ |
| mbed_official | 340:28d1f895c6fe | 1368 | #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */ |
| mbed_official | 340:28d1f895c6fe | 1369 | #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1370 | #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1371 | #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 1372 | |
| mbed_official | 340:28d1f895c6fe | 1373 | /******************* Bit definition for ADC_CR2 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1374 | #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */ |
| mbed_official | 340:28d1f895c6fe | 1375 | #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */ |
| mbed_official | 340:28d1f895c6fe | 1376 | #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */ |
| mbed_official | 340:28d1f895c6fe | 1377 | #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */ |
| mbed_official | 340:28d1f895c6fe | 1378 | #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */ |
| mbed_official | 340:28d1f895c6fe | 1379 | #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */ |
| mbed_official | 340:28d1f895c6fe | 1380 | #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */ |
| mbed_official | 340:28d1f895c6fe | 1381 | #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1382 | #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1383 | #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1384 | #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1385 | #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ |
| mbed_official | 340:28d1f895c6fe | 1386 | #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1387 | #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1388 | #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */ |
| mbed_official | 340:28d1f895c6fe | 1389 | #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ |
| mbed_official | 340:28d1f895c6fe | 1390 | #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1391 | #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1392 | #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1393 | #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1394 | #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ |
| mbed_official | 340:28d1f895c6fe | 1395 | #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1396 | #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1397 | #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */ |
| mbed_official | 340:28d1f895c6fe | 1398 | |
| mbed_official | 340:28d1f895c6fe | 1399 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1400 | #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1401 | #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1402 | #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1403 | #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1404 | #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1405 | #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1406 | #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1407 | #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1408 | #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1409 | #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1410 | #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1411 | #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1412 | #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1413 | #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1414 | #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1415 | #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1416 | #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1417 | #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1418 | #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1419 | #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1420 | #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1421 | #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1422 | #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1423 | #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1424 | #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1425 | #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1426 | #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1427 | #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1428 | #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1429 | #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1430 | #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1431 | #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1432 | #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1433 | #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1434 | #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1435 | #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1436 | |
| mbed_official | 340:28d1f895c6fe | 1437 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1438 | #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1439 | #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1440 | #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1441 | #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1442 | #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1443 | #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1444 | #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1445 | #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1446 | #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1447 | #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1448 | #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1449 | #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1450 | #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1451 | #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1452 | #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1453 | #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1454 | #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1455 | #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1456 | #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1457 | #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1458 | #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1459 | #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1460 | #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1461 | #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1462 | #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1463 | #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1464 | #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1465 | #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1466 | #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1467 | #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1468 | #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1469 | #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1470 | #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1471 | #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1472 | #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1473 | #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1474 | #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ |
| mbed_official | 340:28d1f895c6fe | 1475 | #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1476 | #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1477 | #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1478 | |
| mbed_official | 340:28d1f895c6fe | 1479 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1480 | #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 1481 | |
| mbed_official | 340:28d1f895c6fe | 1482 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1483 | #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 1484 | |
| mbed_official | 340:28d1f895c6fe | 1485 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1486 | #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 1487 | |
| mbed_official | 340:28d1f895c6fe | 1488 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1489 | #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 1490 | |
| mbed_official | 340:28d1f895c6fe | 1491 | /******************* Bit definition for ADC_HTR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1492 | #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */ |
| mbed_official | 340:28d1f895c6fe | 1493 | |
| mbed_official | 340:28d1f895c6fe | 1494 | /******************* Bit definition for ADC_LTR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1495 | #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */ |
| mbed_official | 340:28d1f895c6fe | 1496 | |
| mbed_official | 340:28d1f895c6fe | 1497 | /******************* Bit definition for ADC_SQR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1498 | #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1499 | #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1500 | #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1501 | #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1502 | #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1503 | #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1504 | #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1505 | #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1506 | #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1507 | #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1508 | #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1509 | #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1510 | #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1511 | #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1512 | #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1513 | #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1514 | #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1515 | #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1516 | #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1517 | #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1518 | #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1519 | #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1520 | #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1521 | #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1522 | #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */ |
| mbed_official | 340:28d1f895c6fe | 1523 | #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1524 | #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1525 | #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1526 | #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1527 | |
| mbed_official | 340:28d1f895c6fe | 1528 | /******************* Bit definition for ADC_SQR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1529 | #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1530 | #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1531 | #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1532 | #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1533 | #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1534 | #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1535 | #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1536 | #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1537 | #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1538 | #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1539 | #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1540 | #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1541 | #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1542 | #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1543 | #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1544 | #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1545 | #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1546 | #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1547 | #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1548 | #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1549 | #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1550 | #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1551 | #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1552 | #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1553 | #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1554 | #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1555 | #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1556 | #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1557 | #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1558 | #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1559 | #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1560 | #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1561 | #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1562 | #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1563 | #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1564 | #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1565 | |
| mbed_official | 340:28d1f895c6fe | 1566 | /******************* Bit definition for ADC_SQR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1567 | #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1568 | #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1569 | #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1570 | #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1571 | #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1572 | #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1573 | #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1574 | #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1575 | #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1576 | #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1577 | #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1578 | #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1579 | #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1580 | #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1581 | #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1582 | #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1583 | #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1584 | #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1585 | #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1586 | #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1587 | #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1588 | #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1589 | #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1590 | #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1591 | #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1592 | #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1593 | #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1594 | #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1595 | #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1596 | #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1597 | #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1598 | #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1599 | #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1600 | #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1601 | #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1602 | #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1603 | |
| mbed_official | 340:28d1f895c6fe | 1604 | /******************* Bit definition for ADC_JSQR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1605 | #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1606 | #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1607 | #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1608 | #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1609 | #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1610 | #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1611 | #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1612 | #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1613 | #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1614 | #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1615 | #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1616 | #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1617 | #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1618 | #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1619 | #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1620 | #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1621 | #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1622 | #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1623 | #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ |
| mbed_official | 340:28d1f895c6fe | 1624 | #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1625 | #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1626 | #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1627 | #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1628 | #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1629 | #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */ |
| mbed_official | 340:28d1f895c6fe | 1630 | #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1631 | #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1632 | |
| mbed_official | 340:28d1f895c6fe | 1633 | /******************* Bit definition for ADC_JDR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1634 | #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */ |
| mbed_official | 340:28d1f895c6fe | 1635 | |
| mbed_official | 340:28d1f895c6fe | 1636 | /******************* Bit definition for ADC_JDR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1637 | #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */ |
| mbed_official | 340:28d1f895c6fe | 1638 | |
| mbed_official | 340:28d1f895c6fe | 1639 | /******************* Bit definition for ADC_JDR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1640 | #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */ |
| mbed_official | 340:28d1f895c6fe | 1641 | |
| mbed_official | 340:28d1f895c6fe | 1642 | /******************* Bit definition for ADC_JDR4 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1643 | #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */ |
| mbed_official | 340:28d1f895c6fe | 1644 | |
| mbed_official | 340:28d1f895c6fe | 1645 | /******************** Bit definition for ADC_DR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1646 | #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */ |
| mbed_official | 340:28d1f895c6fe | 1647 | #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */ |
| mbed_official | 340:28d1f895c6fe | 1648 | |
| mbed_official | 340:28d1f895c6fe | 1649 | /******************* Bit definition for ADC_CSR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1650 | #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */ |
| mbed_official | 340:28d1f895c6fe | 1651 | #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */ |
| mbed_official | 340:28d1f895c6fe | 1652 | #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */ |
| mbed_official | 340:28d1f895c6fe | 1653 | #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */ |
| mbed_official | 340:28d1f895c6fe | 1654 | #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */ |
| mbed_official | 340:28d1f895c6fe | 1655 | #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */ |
| mbed_official | 340:28d1f895c6fe | 1656 | #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */ |
| mbed_official | 340:28d1f895c6fe | 1657 | #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */ |
| mbed_official | 340:28d1f895c6fe | 1658 | #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */ |
| mbed_official | 340:28d1f895c6fe | 1659 | #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */ |
| mbed_official | 340:28d1f895c6fe | 1660 | #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */ |
| mbed_official | 340:28d1f895c6fe | 1661 | #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */ |
| mbed_official | 340:28d1f895c6fe | 1662 | #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */ |
| mbed_official | 340:28d1f895c6fe | 1663 | #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */ |
| mbed_official | 340:28d1f895c6fe | 1664 | #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */ |
| mbed_official | 340:28d1f895c6fe | 1665 | #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */ |
| mbed_official | 340:28d1f895c6fe | 1666 | #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */ |
| mbed_official | 340:28d1f895c6fe | 1667 | #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */ |
| mbed_official | 340:28d1f895c6fe | 1668 | |
| mbed_official | 340:28d1f895c6fe | 1669 | /******************* Bit definition for ADC_CCR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1670 | #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ |
| mbed_official | 340:28d1f895c6fe | 1671 | #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1672 | #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1673 | #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1674 | #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1675 | #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 1676 | #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ |
| mbed_official | 340:28d1f895c6fe | 1677 | #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1678 | #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1679 | #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1680 | #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1681 | #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */ |
| mbed_official | 340:28d1f895c6fe | 1682 | #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ |
| mbed_official | 340:28d1f895c6fe | 1683 | #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1684 | #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1685 | #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 1686 | #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1687 | #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1688 | #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */ |
| mbed_official | 340:28d1f895c6fe | 1689 | #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */ |
| mbed_official | 340:28d1f895c6fe | 1690 | |
| mbed_official | 340:28d1f895c6fe | 1691 | /******************* Bit definition for ADC_CDR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1692 | #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */ |
| mbed_official | 340:28d1f895c6fe | 1693 | #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */ |
| mbed_official | 340:28d1f895c6fe | 1694 | |
| mbed_official | 340:28d1f895c6fe | 1695 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 1696 | /* */ |
| mbed_official | 340:28d1f895c6fe | 1697 | /* Controller Area Network */ |
| mbed_official | 340:28d1f895c6fe | 1698 | /* */ |
| mbed_official | 340:28d1f895c6fe | 1699 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 1700 | /*!<CAN control and status registers */ |
| mbed_official | 340:28d1f895c6fe | 1701 | /******************* Bit definition for CAN_MCR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1702 | #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */ |
| mbed_official | 340:28d1f895c6fe | 1703 | #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */ |
| mbed_official | 340:28d1f895c6fe | 1704 | #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */ |
| mbed_official | 340:28d1f895c6fe | 1705 | #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */ |
| mbed_official | 340:28d1f895c6fe | 1706 | #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */ |
| mbed_official | 340:28d1f895c6fe | 1707 | #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */ |
| mbed_official | 340:28d1f895c6fe | 1708 | #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */ |
| mbed_official | 340:28d1f895c6fe | 1709 | #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */ |
| mbed_official | 340:28d1f895c6fe | 1710 | #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */ |
| mbed_official | 340:28d1f895c6fe | 1711 | #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */ |
| mbed_official | 340:28d1f895c6fe | 1712 | /******************* Bit definition for CAN_MSR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1713 | #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */ |
| mbed_official | 340:28d1f895c6fe | 1714 | #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */ |
| mbed_official | 340:28d1f895c6fe | 1715 | #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 1716 | #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 1717 | #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 1718 | #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */ |
| mbed_official | 340:28d1f895c6fe | 1719 | #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */ |
| mbed_official | 340:28d1f895c6fe | 1720 | #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */ |
| mbed_official | 340:28d1f895c6fe | 1721 | #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */ |
| mbed_official | 340:28d1f895c6fe | 1722 | |
| mbed_official | 340:28d1f895c6fe | 1723 | /******************* Bit definition for CAN_TSR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1724 | #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ |
| mbed_official | 340:28d1f895c6fe | 1725 | #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ |
| mbed_official | 340:28d1f895c6fe | 1726 | #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ |
| mbed_official | 340:28d1f895c6fe | 1727 | #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ |
| mbed_official | 340:28d1f895c6fe | 1728 | #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ |
| mbed_official | 340:28d1f895c6fe | 1729 | #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ |
| mbed_official | 340:28d1f895c6fe | 1730 | #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ |
| mbed_official | 340:28d1f895c6fe | 1731 | #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ |
| mbed_official | 340:28d1f895c6fe | 1732 | #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ |
| mbed_official | 340:28d1f895c6fe | 1733 | #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ |
| mbed_official | 340:28d1f895c6fe | 1734 | #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ |
| mbed_official | 340:28d1f895c6fe | 1735 | #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ |
| mbed_official | 340:28d1f895c6fe | 1736 | #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ |
| mbed_official | 340:28d1f895c6fe | 1737 | #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ |
| mbed_official | 340:28d1f895c6fe | 1738 | #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ |
| mbed_official | 340:28d1f895c6fe | 1739 | #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ |
| mbed_official | 340:28d1f895c6fe | 1740 | |
| mbed_official | 340:28d1f895c6fe | 1741 | #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ |
| mbed_official | 340:28d1f895c6fe | 1742 | #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ |
| mbed_official | 340:28d1f895c6fe | 1743 | #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ |
| mbed_official | 340:28d1f895c6fe | 1744 | #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ |
| mbed_official | 340:28d1f895c6fe | 1745 | |
| mbed_official | 340:28d1f895c6fe | 1746 | #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ |
| mbed_official | 340:28d1f895c6fe | 1747 | #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ |
| mbed_official | 340:28d1f895c6fe | 1748 | #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ |
| mbed_official | 340:28d1f895c6fe | 1749 | #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ |
| mbed_official | 340:28d1f895c6fe | 1750 | |
| mbed_official | 340:28d1f895c6fe | 1751 | /******************* Bit definition for CAN_RF0R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1752 | #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */ |
| mbed_official | 340:28d1f895c6fe | 1753 | #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */ |
| mbed_official | 340:28d1f895c6fe | 1754 | #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */ |
| mbed_official | 340:28d1f895c6fe | 1755 | #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */ |
| mbed_official | 340:28d1f895c6fe | 1756 | |
| mbed_official | 340:28d1f895c6fe | 1757 | /******************* Bit definition for CAN_RF1R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1758 | #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */ |
| mbed_official | 340:28d1f895c6fe | 1759 | #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */ |
| mbed_official | 340:28d1f895c6fe | 1760 | #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */ |
| mbed_official | 340:28d1f895c6fe | 1761 | #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */ |
| mbed_official | 340:28d1f895c6fe | 1762 | |
| mbed_official | 340:28d1f895c6fe | 1763 | /******************** Bit definition for CAN_IER register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1764 | #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1765 | #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1766 | #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1767 | #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1768 | #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1769 | #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1770 | #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1771 | #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1772 | #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1773 | #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1774 | #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1775 | #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1776 | #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1777 | #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 1778 | #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 1779 | #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 1780 | #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 1781 | #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 1782 | #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 1783 | |
| mbed_official | 340:28d1f895c6fe | 1784 | |
| mbed_official | 340:28d1f895c6fe | 1785 | /******************** Bit definition for CAN_ESR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1786 | #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ |
| mbed_official | 340:28d1f895c6fe | 1787 | #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ |
| mbed_official | 340:28d1f895c6fe | 1788 | #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ |
| mbed_official | 340:28d1f895c6fe | 1789 | |
| mbed_official | 340:28d1f895c6fe | 1790 | #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ |
| mbed_official | 340:28d1f895c6fe | 1791 | #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1792 | #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1793 | #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1794 | |
| mbed_official | 340:28d1f895c6fe | 1795 | #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
| mbed_official | 340:28d1f895c6fe | 1796 | #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ |
| mbed_official | 340:28d1f895c6fe | 1797 | |
| mbed_official | 340:28d1f895c6fe | 1798 | /******************* Bit definition for CAN_BTR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1799 | #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ |
| mbed_official | 340:28d1f895c6fe | 1800 | #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ |
| mbed_official | 340:28d1f895c6fe | 1801 | #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1802 | #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1803 | #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1804 | #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 1805 | #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ |
| mbed_official | 340:28d1f895c6fe | 1806 | #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1807 | #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1808 | #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 1809 | #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ |
| mbed_official | 340:28d1f895c6fe | 1810 | #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 1811 | #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 1812 | #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ |
| mbed_official | 340:28d1f895c6fe | 1813 | #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ |
| mbed_official | 340:28d1f895c6fe | 1814 | |
| mbed_official | 340:28d1f895c6fe | 1815 | |
| mbed_official | 340:28d1f895c6fe | 1816 | /*!<Mailbox registers */ |
| mbed_official | 340:28d1f895c6fe | 1817 | /****************** Bit definition for CAN_TI0R register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1818 | #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
| mbed_official | 340:28d1f895c6fe | 1819 | #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 340:28d1f895c6fe | 1820 | #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 340:28d1f895c6fe | 1821 | #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
| mbed_official | 340:28d1f895c6fe | 1822 | #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 340:28d1f895c6fe | 1823 | |
| mbed_official | 340:28d1f895c6fe | 1824 | /****************** Bit definition for CAN_TDT0R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1825 | #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 340:28d1f895c6fe | 1826 | #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
| mbed_official | 340:28d1f895c6fe | 1827 | #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 340:28d1f895c6fe | 1828 | |
| mbed_official | 340:28d1f895c6fe | 1829 | /****************** Bit definition for CAN_TDL0R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1830 | #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 340:28d1f895c6fe | 1831 | #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 340:28d1f895c6fe | 1832 | #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 340:28d1f895c6fe | 1833 | #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 340:28d1f895c6fe | 1834 | |
| mbed_official | 340:28d1f895c6fe | 1835 | /****************** Bit definition for CAN_TDH0R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1836 | #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 340:28d1f895c6fe | 1837 | #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 340:28d1f895c6fe | 1838 | #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 340:28d1f895c6fe | 1839 | #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 340:28d1f895c6fe | 1840 | |
| mbed_official | 340:28d1f895c6fe | 1841 | /******************* Bit definition for CAN_TI1R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1842 | #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
| mbed_official | 340:28d1f895c6fe | 1843 | #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 340:28d1f895c6fe | 1844 | #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 340:28d1f895c6fe | 1845 | #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
| mbed_official | 340:28d1f895c6fe | 1846 | #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 340:28d1f895c6fe | 1847 | |
| mbed_official | 340:28d1f895c6fe | 1848 | /******************* Bit definition for CAN_TDT1R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1849 | #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 340:28d1f895c6fe | 1850 | #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
| mbed_official | 340:28d1f895c6fe | 1851 | #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 340:28d1f895c6fe | 1852 | |
| mbed_official | 340:28d1f895c6fe | 1853 | /******************* Bit definition for CAN_TDL1R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1854 | #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 340:28d1f895c6fe | 1855 | #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 340:28d1f895c6fe | 1856 | #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 340:28d1f895c6fe | 1857 | #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 340:28d1f895c6fe | 1858 | |
| mbed_official | 340:28d1f895c6fe | 1859 | /******************* Bit definition for CAN_TDH1R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1860 | #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 340:28d1f895c6fe | 1861 | #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 340:28d1f895c6fe | 1862 | #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 340:28d1f895c6fe | 1863 | #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 340:28d1f895c6fe | 1864 | |
| mbed_official | 340:28d1f895c6fe | 1865 | /******************* Bit definition for CAN_TI2R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1866 | #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
| mbed_official | 340:28d1f895c6fe | 1867 | #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 340:28d1f895c6fe | 1868 | #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 340:28d1f895c6fe | 1869 | #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
| mbed_official | 340:28d1f895c6fe | 1870 | #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 340:28d1f895c6fe | 1871 | |
| mbed_official | 340:28d1f895c6fe | 1872 | /******************* Bit definition for CAN_TDT2R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1873 | #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 340:28d1f895c6fe | 1874 | #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
| mbed_official | 340:28d1f895c6fe | 1875 | #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 340:28d1f895c6fe | 1876 | |
| mbed_official | 340:28d1f895c6fe | 1877 | /******************* Bit definition for CAN_TDL2R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1878 | #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 340:28d1f895c6fe | 1879 | #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 340:28d1f895c6fe | 1880 | #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 340:28d1f895c6fe | 1881 | #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 340:28d1f895c6fe | 1882 | |
| mbed_official | 340:28d1f895c6fe | 1883 | /******************* Bit definition for CAN_TDH2R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1884 | #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 340:28d1f895c6fe | 1885 | #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 340:28d1f895c6fe | 1886 | #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 340:28d1f895c6fe | 1887 | #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 340:28d1f895c6fe | 1888 | |
| mbed_official | 340:28d1f895c6fe | 1889 | /******************* Bit definition for CAN_RI0R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1890 | #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 340:28d1f895c6fe | 1891 | #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 340:28d1f895c6fe | 1892 | #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
| mbed_official | 340:28d1f895c6fe | 1893 | #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 340:28d1f895c6fe | 1894 | |
| mbed_official | 340:28d1f895c6fe | 1895 | /******************* Bit definition for CAN_RDT0R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1896 | #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 340:28d1f895c6fe | 1897 | #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
| mbed_official | 340:28d1f895c6fe | 1898 | #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 340:28d1f895c6fe | 1899 | |
| mbed_official | 340:28d1f895c6fe | 1900 | /******************* Bit definition for CAN_RDL0R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1901 | #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 340:28d1f895c6fe | 1902 | #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 340:28d1f895c6fe | 1903 | #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 340:28d1f895c6fe | 1904 | #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 340:28d1f895c6fe | 1905 | |
| mbed_official | 340:28d1f895c6fe | 1906 | /******************* Bit definition for CAN_RDH0R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1907 | #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 340:28d1f895c6fe | 1908 | #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 340:28d1f895c6fe | 1909 | #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 340:28d1f895c6fe | 1910 | #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 340:28d1f895c6fe | 1911 | |
| mbed_official | 340:28d1f895c6fe | 1912 | /******************* Bit definition for CAN_RI1R register *******************/ |
| mbed_official | 340:28d1f895c6fe | 1913 | #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 340:28d1f895c6fe | 1914 | #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 340:28d1f895c6fe | 1915 | #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
| mbed_official | 340:28d1f895c6fe | 1916 | #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 340:28d1f895c6fe | 1917 | |
| mbed_official | 340:28d1f895c6fe | 1918 | /******************* Bit definition for CAN_RDT1R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1919 | #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 340:28d1f895c6fe | 1920 | #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
| mbed_official | 340:28d1f895c6fe | 1921 | #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 340:28d1f895c6fe | 1922 | |
| mbed_official | 340:28d1f895c6fe | 1923 | /******************* Bit definition for CAN_RDL1R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1924 | #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 340:28d1f895c6fe | 1925 | #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 340:28d1f895c6fe | 1926 | #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 340:28d1f895c6fe | 1927 | #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 340:28d1f895c6fe | 1928 | |
| mbed_official | 340:28d1f895c6fe | 1929 | /******************* Bit definition for CAN_RDH1R register ******************/ |
| mbed_official | 340:28d1f895c6fe | 1930 | #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 340:28d1f895c6fe | 1931 | #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 340:28d1f895c6fe | 1932 | #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 340:28d1f895c6fe | 1933 | #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 340:28d1f895c6fe | 1934 | |
| mbed_official | 340:28d1f895c6fe | 1935 | /*!<CAN filter registers */ |
| mbed_official | 340:28d1f895c6fe | 1936 | /******************* Bit definition for CAN_FMR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 1937 | #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */ |
| mbed_official | 340:28d1f895c6fe | 1938 | #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */ |
| mbed_official | 340:28d1f895c6fe | 1939 | |
| mbed_official | 340:28d1f895c6fe | 1940 | /******************* Bit definition for CAN_FM1R register *******************/ |
| mbed_official | 532:fe11edbda85c | 1941 | #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */ |
| mbed_official | 532:fe11edbda85c | 1942 | #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */ |
| mbed_official | 532:fe11edbda85c | 1943 | #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */ |
| mbed_official | 532:fe11edbda85c | 1944 | #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */ |
| mbed_official | 532:fe11edbda85c | 1945 | #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */ |
| mbed_official | 532:fe11edbda85c | 1946 | #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */ |
| mbed_official | 532:fe11edbda85c | 1947 | #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */ |
| mbed_official | 532:fe11edbda85c | 1948 | #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */ |
| mbed_official | 532:fe11edbda85c | 1949 | #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */ |
| mbed_official | 532:fe11edbda85c | 1950 | #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */ |
| mbed_official | 532:fe11edbda85c | 1951 | #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */ |
| mbed_official | 532:fe11edbda85c | 1952 | #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */ |
| mbed_official | 532:fe11edbda85c | 1953 | #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */ |
| mbed_official | 532:fe11edbda85c | 1954 | #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */ |
| mbed_official | 532:fe11edbda85c | 1955 | #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */ |
| mbed_official | 532:fe11edbda85c | 1956 | #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */ |
| mbed_official | 532:fe11edbda85c | 1957 | #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */ |
| mbed_official | 532:fe11edbda85c | 1958 | #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */ |
| mbed_official | 532:fe11edbda85c | 1959 | #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */ |
| mbed_official | 532:fe11edbda85c | 1960 | #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */ |
| mbed_official | 532:fe11edbda85c | 1961 | #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */ |
| mbed_official | 532:fe11edbda85c | 1962 | #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */ |
| mbed_official | 532:fe11edbda85c | 1963 | #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */ |
| mbed_official | 532:fe11edbda85c | 1964 | #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */ |
| mbed_official | 532:fe11edbda85c | 1965 | #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */ |
| mbed_official | 532:fe11edbda85c | 1966 | #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */ |
| mbed_official | 532:fe11edbda85c | 1967 | #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */ |
| mbed_official | 532:fe11edbda85c | 1968 | #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */ |
| mbed_official | 532:fe11edbda85c | 1969 | #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 1970 | |
| mbed_official | 340:28d1f895c6fe | 1971 | /******************* Bit definition for CAN_FS1R register *******************/ |
| mbed_official | 532:fe11edbda85c | 1972 | #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */ |
| mbed_official | 532:fe11edbda85c | 1973 | #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */ |
| mbed_official | 532:fe11edbda85c | 1974 | #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */ |
| mbed_official | 532:fe11edbda85c | 1975 | #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */ |
| mbed_official | 532:fe11edbda85c | 1976 | #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */ |
| mbed_official | 532:fe11edbda85c | 1977 | #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */ |
| mbed_official | 532:fe11edbda85c | 1978 | #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */ |
| mbed_official | 532:fe11edbda85c | 1979 | #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */ |
| mbed_official | 532:fe11edbda85c | 1980 | #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */ |
| mbed_official | 532:fe11edbda85c | 1981 | #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */ |
| mbed_official | 532:fe11edbda85c | 1982 | #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */ |
| mbed_official | 532:fe11edbda85c | 1983 | #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */ |
| mbed_official | 532:fe11edbda85c | 1984 | #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */ |
| mbed_official | 532:fe11edbda85c | 1985 | #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */ |
| mbed_official | 532:fe11edbda85c | 1986 | #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */ |
| mbed_official | 532:fe11edbda85c | 1987 | #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */ |
| mbed_official | 532:fe11edbda85c | 1988 | #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */ |
| mbed_official | 532:fe11edbda85c | 1989 | #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */ |
| mbed_official | 532:fe11edbda85c | 1990 | #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */ |
| mbed_official | 532:fe11edbda85c | 1991 | #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */ |
| mbed_official | 532:fe11edbda85c | 1992 | #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */ |
| mbed_official | 532:fe11edbda85c | 1993 | #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */ |
| mbed_official | 532:fe11edbda85c | 1994 | #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */ |
| mbed_official | 532:fe11edbda85c | 1995 | #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */ |
| mbed_official | 532:fe11edbda85c | 1996 | #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */ |
| mbed_official | 532:fe11edbda85c | 1997 | #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */ |
| mbed_official | 532:fe11edbda85c | 1998 | #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */ |
| mbed_official | 532:fe11edbda85c | 1999 | #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */ |
| mbed_official | 532:fe11edbda85c | 2000 | #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2001 | |
| mbed_official | 340:28d1f895c6fe | 2002 | /****************** Bit definition for CAN_FFA1R register *******************/ |
| mbed_official | 532:fe11edbda85c | 2003 | #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */ |
| mbed_official | 532:fe11edbda85c | 2004 | #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */ |
| mbed_official | 532:fe11edbda85c | 2005 | #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */ |
| mbed_official | 532:fe11edbda85c | 2006 | #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */ |
| mbed_official | 532:fe11edbda85c | 2007 | #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */ |
| mbed_official | 532:fe11edbda85c | 2008 | #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */ |
| mbed_official | 532:fe11edbda85c | 2009 | #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */ |
| mbed_official | 532:fe11edbda85c | 2010 | #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */ |
| mbed_official | 532:fe11edbda85c | 2011 | #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */ |
| mbed_official | 532:fe11edbda85c | 2012 | #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */ |
| mbed_official | 532:fe11edbda85c | 2013 | #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */ |
| mbed_official | 532:fe11edbda85c | 2014 | #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */ |
| mbed_official | 532:fe11edbda85c | 2015 | #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */ |
| mbed_official | 532:fe11edbda85c | 2016 | #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */ |
| mbed_official | 532:fe11edbda85c | 2017 | #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */ |
| mbed_official | 532:fe11edbda85c | 2018 | #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */ |
| mbed_official | 532:fe11edbda85c | 2019 | #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */ |
| mbed_official | 532:fe11edbda85c | 2020 | #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */ |
| mbed_official | 532:fe11edbda85c | 2021 | #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */ |
| mbed_official | 532:fe11edbda85c | 2022 | #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */ |
| mbed_official | 532:fe11edbda85c | 2023 | #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */ |
| mbed_official | 532:fe11edbda85c | 2024 | #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */ |
| mbed_official | 532:fe11edbda85c | 2025 | #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */ |
| mbed_official | 532:fe11edbda85c | 2026 | #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */ |
| mbed_official | 532:fe11edbda85c | 2027 | #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */ |
| mbed_official | 532:fe11edbda85c | 2028 | #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */ |
| mbed_official | 532:fe11edbda85c | 2029 | #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */ |
| mbed_official | 532:fe11edbda85c | 2030 | #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */ |
| mbed_official | 532:fe11edbda85c | 2031 | #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2032 | |
| mbed_official | 340:28d1f895c6fe | 2033 | /******************* Bit definition for CAN_FA1R register *******************/ |
| mbed_official | 532:fe11edbda85c | 2034 | #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */ |
| mbed_official | 532:fe11edbda85c | 2035 | #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */ |
| mbed_official | 532:fe11edbda85c | 2036 | #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */ |
| mbed_official | 532:fe11edbda85c | 2037 | #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */ |
| mbed_official | 532:fe11edbda85c | 2038 | #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */ |
| mbed_official | 532:fe11edbda85c | 2039 | #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */ |
| mbed_official | 532:fe11edbda85c | 2040 | #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */ |
| mbed_official | 532:fe11edbda85c | 2041 | #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */ |
| mbed_official | 532:fe11edbda85c | 2042 | #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */ |
| mbed_official | 532:fe11edbda85c | 2043 | #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */ |
| mbed_official | 532:fe11edbda85c | 2044 | #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */ |
| mbed_official | 532:fe11edbda85c | 2045 | #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */ |
| mbed_official | 532:fe11edbda85c | 2046 | #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */ |
| mbed_official | 532:fe11edbda85c | 2047 | #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */ |
| mbed_official | 532:fe11edbda85c | 2048 | #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */ |
| mbed_official | 532:fe11edbda85c | 2049 | #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */ |
| mbed_official | 532:fe11edbda85c | 2050 | #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */ |
| mbed_official | 532:fe11edbda85c | 2051 | #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */ |
| mbed_official | 532:fe11edbda85c | 2052 | #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */ |
| mbed_official | 532:fe11edbda85c | 2053 | #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */ |
| mbed_official | 532:fe11edbda85c | 2054 | #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */ |
| mbed_official | 532:fe11edbda85c | 2055 | #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */ |
| mbed_official | 532:fe11edbda85c | 2056 | #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */ |
| mbed_official | 532:fe11edbda85c | 2057 | #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */ |
| mbed_official | 532:fe11edbda85c | 2058 | #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */ |
| mbed_official | 532:fe11edbda85c | 2059 | #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */ |
| mbed_official | 532:fe11edbda85c | 2060 | #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */ |
| mbed_official | 532:fe11edbda85c | 2061 | #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */ |
| mbed_official | 532:fe11edbda85c | 2062 | #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2063 | |
| mbed_official | 340:28d1f895c6fe | 2064 | /******************* Bit definition for CAN_F0R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2065 | #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2066 | #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2067 | #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2068 | #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2069 | #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2070 | #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2071 | #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2072 | #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2073 | #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2074 | #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2075 | #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2076 | #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2077 | #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2078 | #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2079 | #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2080 | #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2081 | #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2082 | #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2083 | #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2084 | #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2085 | #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2086 | #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2087 | #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2088 | #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2089 | #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2090 | #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2091 | #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2092 | #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2093 | #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2094 | #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2095 | #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2096 | #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2097 | |
| mbed_official | 340:28d1f895c6fe | 2098 | /******************* Bit definition for CAN_F1R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2099 | #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2100 | #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2101 | #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2102 | #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2103 | #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2104 | #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2105 | #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2106 | #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2107 | #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2108 | #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2109 | #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2110 | #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2111 | #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2112 | #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2113 | #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2114 | #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2115 | #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2116 | #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2117 | #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2118 | #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2119 | #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2120 | #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2121 | #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2122 | #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2123 | #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2124 | #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2125 | #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2126 | #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2127 | #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2128 | #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2129 | #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2130 | #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2131 | |
| mbed_official | 340:28d1f895c6fe | 2132 | /******************* Bit definition for CAN_F2R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2133 | #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2134 | #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2135 | #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2136 | #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2137 | #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2138 | #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2139 | #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2140 | #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2141 | #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2142 | #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2143 | #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2144 | #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2145 | #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2146 | #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2147 | #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2148 | #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2149 | #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2150 | #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2151 | #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2152 | #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2153 | #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2154 | #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2155 | #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2156 | #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2157 | #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2158 | #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2159 | #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2160 | #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2161 | #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2162 | #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2163 | #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2164 | #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2165 | |
| mbed_official | 340:28d1f895c6fe | 2166 | /******************* Bit definition for CAN_F3R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2167 | #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2168 | #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2169 | #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2170 | #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2171 | #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2172 | #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2173 | #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2174 | #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2175 | #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2176 | #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2177 | #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2178 | #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2179 | #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2180 | #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2181 | #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2182 | #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2183 | #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2184 | #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2185 | #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2186 | #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2187 | #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2188 | #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2189 | #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2190 | #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2191 | #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2192 | #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2193 | #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2194 | #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2195 | #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2196 | #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2197 | #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2198 | #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2199 | |
| mbed_official | 340:28d1f895c6fe | 2200 | /******************* Bit definition for CAN_F4R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2201 | #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2202 | #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2203 | #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2204 | #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2205 | #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2206 | #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2207 | #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2208 | #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2209 | #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2210 | #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2211 | #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2212 | #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2213 | #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2214 | #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2215 | #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2216 | #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2217 | #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2218 | #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2219 | #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2220 | #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2221 | #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2222 | #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2223 | #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2224 | #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2225 | #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2226 | #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2227 | #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2228 | #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2229 | #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2230 | #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2231 | #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2232 | #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2233 | |
| mbed_official | 340:28d1f895c6fe | 2234 | /******************* Bit definition for CAN_F5R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2235 | #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2236 | #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2237 | #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2238 | #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2239 | #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2240 | #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2241 | #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2242 | #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2243 | #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2244 | #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2245 | #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2246 | #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2247 | #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2248 | #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2249 | #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2250 | #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2251 | #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2252 | #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2253 | #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2254 | #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2255 | #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2256 | #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2257 | #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2258 | #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2259 | #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2260 | #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2261 | #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2262 | #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2263 | #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2264 | #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2265 | #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2266 | #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2267 | |
| mbed_official | 340:28d1f895c6fe | 2268 | /******************* Bit definition for CAN_F6R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2269 | #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2270 | #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2271 | #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2272 | #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2273 | #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2274 | #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2275 | #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2276 | #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2277 | #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2278 | #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2279 | #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2280 | #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2281 | #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2282 | #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2283 | #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2284 | #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2285 | #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2286 | #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2287 | #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2288 | #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2289 | #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2290 | #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2291 | #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2292 | #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2293 | #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2294 | #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2295 | #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2296 | #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2297 | #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2298 | #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2299 | #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2300 | #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2301 | |
| mbed_official | 340:28d1f895c6fe | 2302 | /******************* Bit definition for CAN_F7R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2303 | #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2304 | #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2305 | #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2306 | #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2307 | #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2308 | #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2309 | #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2310 | #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2311 | #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2312 | #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2313 | #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2314 | #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2315 | #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2316 | #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2317 | #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2318 | #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2319 | #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2320 | #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2321 | #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2322 | #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2323 | #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2324 | #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2325 | #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2326 | #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2327 | #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2328 | #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2329 | #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2330 | #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2331 | #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2332 | #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2333 | #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2334 | #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2335 | |
| mbed_official | 340:28d1f895c6fe | 2336 | /******************* Bit definition for CAN_F8R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2337 | #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2338 | #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2339 | #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2340 | #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2341 | #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2342 | #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2343 | #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2344 | #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2345 | #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2346 | #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2347 | #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2348 | #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2349 | #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2350 | #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2351 | #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2352 | #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2353 | #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2354 | #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2355 | #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2356 | #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2357 | #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2358 | #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2359 | #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2360 | #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2361 | #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2362 | #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2363 | #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2364 | #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2365 | #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2366 | #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2367 | #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2368 | #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2369 | |
| mbed_official | 340:28d1f895c6fe | 2370 | /******************* Bit definition for CAN_F9R1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2371 | #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2372 | #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2373 | #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2374 | #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2375 | #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2376 | #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2377 | #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2378 | #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2379 | #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2380 | #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2381 | #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2382 | #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2383 | #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2384 | #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2385 | #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2386 | #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2387 | #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2388 | #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2389 | #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2390 | #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2391 | #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2392 | #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2393 | #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2394 | #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2395 | #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2396 | #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2397 | #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2398 | #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2399 | #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2400 | #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2401 | #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2402 | #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2403 | |
| mbed_official | 340:28d1f895c6fe | 2404 | /******************* Bit definition for CAN_F10R1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 2405 | #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2406 | #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2407 | #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2408 | #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2409 | #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2410 | #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2411 | #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2412 | #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2413 | #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2414 | #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2415 | #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2416 | #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2417 | #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2418 | #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2419 | #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2420 | #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2421 | #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2422 | #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2423 | #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2424 | #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2425 | #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2426 | #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2427 | #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2428 | #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2429 | #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2430 | #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2431 | #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2432 | #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2433 | #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2434 | #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2435 | #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2436 | #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2437 | |
| mbed_official | 340:28d1f895c6fe | 2438 | /******************* Bit definition for CAN_F11R1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 2439 | #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2440 | #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2441 | #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2442 | #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2443 | #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2444 | #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2445 | #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2446 | #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2447 | #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2448 | #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2449 | #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2450 | #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2451 | #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2452 | #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2453 | #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2454 | #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2455 | #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2456 | #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2457 | #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2458 | #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2459 | #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2460 | #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2461 | #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2462 | #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2463 | #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2464 | #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2465 | #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2466 | #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2467 | #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2468 | #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2469 | #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2470 | #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2471 | |
| mbed_official | 340:28d1f895c6fe | 2472 | /******************* Bit definition for CAN_F12R1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 2473 | #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2474 | #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2475 | #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2476 | #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2477 | #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2478 | #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2479 | #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2480 | #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2481 | #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2482 | #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2483 | #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2484 | #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2485 | #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2486 | #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2487 | #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2488 | #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2489 | #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2490 | #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2491 | #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2492 | #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2493 | #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2494 | #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2495 | #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2496 | #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2497 | #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2498 | #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2499 | #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2500 | #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2501 | #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2502 | #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2503 | #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2504 | #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2505 | |
| mbed_official | 340:28d1f895c6fe | 2506 | /******************* Bit definition for CAN_F13R1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 2507 | #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2508 | #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2509 | #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2510 | #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2511 | #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2512 | #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2513 | #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2514 | #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2515 | #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2516 | #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2517 | #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2518 | #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2519 | #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2520 | #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2521 | #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2522 | #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2523 | #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2524 | #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2525 | #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2526 | #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2527 | #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2528 | #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2529 | #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2530 | #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2531 | #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2532 | #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2533 | #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2534 | #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2535 | #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2536 | #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2537 | #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2538 | #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2539 | |
| mbed_official | 340:28d1f895c6fe | 2540 | /******************* Bit definition for CAN_F0R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2541 | #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2542 | #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2543 | #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2544 | #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2545 | #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2546 | #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2547 | #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2548 | #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2549 | #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2550 | #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2551 | #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2552 | #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2553 | #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2554 | #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2555 | #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2556 | #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2557 | #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2558 | #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2559 | #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2560 | #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2561 | #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2562 | #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2563 | #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2564 | #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2565 | #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2566 | #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2567 | #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2568 | #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2569 | #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2570 | #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2571 | #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2572 | #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2573 | |
| mbed_official | 340:28d1f895c6fe | 2574 | /******************* Bit definition for CAN_F1R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2575 | #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2576 | #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2577 | #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2578 | #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2579 | #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2580 | #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2581 | #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2582 | #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2583 | #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2584 | #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2585 | #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2586 | #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2587 | #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2588 | #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2589 | #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2590 | #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2591 | #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2592 | #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2593 | #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2594 | #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2595 | #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2596 | #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2597 | #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2598 | #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2599 | #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2600 | #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2601 | #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2602 | #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2603 | #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2604 | #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2605 | #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2606 | #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2607 | |
| mbed_official | 340:28d1f895c6fe | 2608 | /******************* Bit definition for CAN_F2R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2609 | #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2610 | #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2611 | #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2612 | #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2613 | #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2614 | #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2615 | #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2616 | #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2617 | #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2618 | #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2619 | #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2620 | #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2621 | #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2622 | #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2623 | #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2624 | #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2625 | #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2626 | #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2627 | #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2628 | #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2629 | #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2630 | #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2631 | #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2632 | #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2633 | #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2634 | #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2635 | #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2636 | #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2637 | #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2638 | #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2639 | #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2640 | #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2641 | |
| mbed_official | 340:28d1f895c6fe | 2642 | /******************* Bit definition for CAN_F3R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2643 | #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2644 | #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2645 | #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2646 | #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2647 | #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2648 | #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2649 | #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2650 | #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2651 | #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2652 | #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2653 | #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2654 | #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2655 | #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2656 | #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2657 | #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2658 | #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2659 | #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2660 | #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2661 | #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2662 | #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2663 | #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2664 | #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2665 | #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2666 | #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2667 | #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2668 | #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2669 | #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2670 | #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2671 | #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2672 | #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2673 | #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2674 | #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2675 | |
| mbed_official | 340:28d1f895c6fe | 2676 | /******************* Bit definition for CAN_F4R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2677 | #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2678 | #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2679 | #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2680 | #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2681 | #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2682 | #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2683 | #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2684 | #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2685 | #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2686 | #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2687 | #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2688 | #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2689 | #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2690 | #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2691 | #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2692 | #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2693 | #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2694 | #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2695 | #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2696 | #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2697 | #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2698 | #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2699 | #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2700 | #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2701 | #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2702 | #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2703 | #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2704 | #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2705 | #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2706 | #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2707 | #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2708 | #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2709 | |
| mbed_official | 340:28d1f895c6fe | 2710 | /******************* Bit definition for CAN_F5R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2711 | #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2712 | #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2713 | #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2714 | #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2715 | #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2716 | #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2717 | #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2718 | #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2719 | #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2720 | #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2721 | #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2722 | #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2723 | #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2724 | #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2725 | #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2726 | #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2727 | #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2728 | #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2729 | #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2730 | #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2731 | #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2732 | #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2733 | #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2734 | #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2735 | #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2736 | #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2737 | #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2738 | #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2739 | #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2740 | #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2741 | #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2742 | #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2743 | |
| mbed_official | 340:28d1f895c6fe | 2744 | /******************* Bit definition for CAN_F6R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2745 | #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2746 | #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2747 | #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2748 | #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2749 | #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2750 | #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2751 | #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2752 | #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2753 | #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2754 | #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2755 | #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2756 | #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2757 | #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2758 | #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2759 | #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2760 | #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2761 | #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2762 | #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2763 | #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2764 | #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2765 | #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2766 | #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2767 | #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2768 | #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2769 | #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2770 | #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2771 | #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2772 | #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2773 | #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2774 | #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2775 | #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2776 | #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2777 | |
| mbed_official | 340:28d1f895c6fe | 2778 | /******************* Bit definition for CAN_F7R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2779 | #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2780 | #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2781 | #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2782 | #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2783 | #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2784 | #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2785 | #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2786 | #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2787 | #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2788 | #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2789 | #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2790 | #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2791 | #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2792 | #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2793 | #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2794 | #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2795 | #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2796 | #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2797 | #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2798 | #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2799 | #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2800 | #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2801 | #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2802 | #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2803 | #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2804 | #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2805 | #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2806 | #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2807 | #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2808 | #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2809 | #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2810 | #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2811 | |
| mbed_official | 340:28d1f895c6fe | 2812 | /******************* Bit definition for CAN_F8R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2813 | #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2814 | #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2815 | #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2816 | #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2817 | #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2818 | #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2819 | #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2820 | #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2821 | #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2822 | #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2823 | #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2824 | #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2825 | #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2826 | #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2827 | #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2828 | #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2829 | #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2830 | #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2831 | #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2832 | #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2833 | #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2834 | #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2835 | #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2836 | #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2837 | #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2838 | #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2839 | #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2840 | #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2841 | #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2842 | #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2843 | #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2844 | #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2845 | |
| mbed_official | 340:28d1f895c6fe | 2846 | /******************* Bit definition for CAN_F9R2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 2847 | #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2848 | #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2849 | #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2850 | #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2851 | #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2852 | #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2853 | #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2854 | #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2855 | #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2856 | #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2857 | #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2858 | #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2859 | #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2860 | #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2861 | #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2862 | #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2863 | #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2864 | #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2865 | #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2866 | #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2867 | #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2868 | #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2869 | #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2870 | #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2871 | #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2872 | #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2873 | #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2874 | #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2875 | #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2876 | #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2877 | #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2878 | #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2879 | |
| mbed_official | 340:28d1f895c6fe | 2880 | /******************* Bit definition for CAN_F10R2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 2881 | #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2882 | #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2883 | #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2884 | #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2885 | #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2886 | #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2887 | #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2888 | #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2889 | #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2890 | #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2891 | #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2892 | #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2893 | #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2894 | #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2895 | #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2896 | #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2897 | #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2898 | #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2899 | #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2900 | #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2901 | #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2902 | #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2903 | #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2904 | #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2905 | #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2906 | #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2907 | #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2908 | #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2909 | #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2910 | #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2911 | #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2912 | #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2913 | |
| mbed_official | 340:28d1f895c6fe | 2914 | /******************* Bit definition for CAN_F11R2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 2915 | #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2916 | #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2917 | #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2918 | #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2919 | #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2920 | #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2921 | #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2922 | #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2923 | #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2924 | #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2925 | #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2926 | #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2927 | #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2928 | #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2929 | #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2930 | #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2931 | #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2932 | #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2933 | #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2934 | #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2935 | #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2936 | #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2937 | #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2938 | #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2939 | #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2940 | #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2941 | #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2942 | #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2943 | #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2944 | #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2945 | #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2946 | #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2947 | |
| mbed_official | 340:28d1f895c6fe | 2948 | /******************* Bit definition for CAN_F12R2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 2949 | #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2950 | #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2951 | #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2952 | #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2953 | #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2954 | #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2955 | #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2956 | #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2957 | #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2958 | #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2959 | #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2960 | #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2961 | #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2962 | #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2963 | #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2964 | #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2965 | #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 2966 | #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 2967 | #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 2968 | #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 2969 | #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 2970 | #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 2971 | #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 2972 | #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 2973 | #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 2974 | #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 2975 | #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 2976 | #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 2977 | #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 2978 | #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 2979 | #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 2980 | #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 2981 | |
| mbed_official | 340:28d1f895c6fe | 2982 | /******************* Bit definition for CAN_F13R2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 2983 | #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 2984 | #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 2985 | #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 2986 | #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 2987 | #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 2988 | #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 2989 | #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 2990 | #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 2991 | #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 2992 | #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 2993 | #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 340:28d1f895c6fe | 2994 | #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 340:28d1f895c6fe | 2995 | #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 340:28d1f895c6fe | 2996 | #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 340:28d1f895c6fe | 2997 | #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 340:28d1f895c6fe | 2998 | #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 340:28d1f895c6fe | 2999 | #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 340:28d1f895c6fe | 3000 | #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 340:28d1f895c6fe | 3001 | #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 340:28d1f895c6fe | 3002 | #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 340:28d1f895c6fe | 3003 | #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 340:28d1f895c6fe | 3004 | #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 340:28d1f895c6fe | 3005 | #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 340:28d1f895c6fe | 3006 | #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 340:28d1f895c6fe | 3007 | #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 340:28d1f895c6fe | 3008 | #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 340:28d1f895c6fe | 3009 | #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 340:28d1f895c6fe | 3010 | #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 340:28d1f895c6fe | 3011 | #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 340:28d1f895c6fe | 3012 | #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 340:28d1f895c6fe | 3013 | #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 340:28d1f895c6fe | 3014 | #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 340:28d1f895c6fe | 3015 | |
| mbed_official | 340:28d1f895c6fe | 3016 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3017 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3018 | /* CRC calculation unit */ |
| mbed_official | 340:28d1f895c6fe | 3019 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3020 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3021 | /******************* Bit definition for CRC_DR register *********************/ |
| mbed_official | 340:28d1f895c6fe | 3022 | #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
| mbed_official | 340:28d1f895c6fe | 3023 | |
| mbed_official | 340:28d1f895c6fe | 3024 | |
| mbed_official | 340:28d1f895c6fe | 3025 | /******************* Bit definition for CRC_IDR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 3026 | #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
| mbed_official | 340:28d1f895c6fe | 3027 | |
| mbed_official | 340:28d1f895c6fe | 3028 | |
| mbed_official | 340:28d1f895c6fe | 3029 | /******************** Bit definition for CRC_CR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 3030 | #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */ |
| mbed_official | 340:28d1f895c6fe | 3031 | |
| mbed_official | 340:28d1f895c6fe | 3032 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3033 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3034 | /* Digital to Analog Converter */ |
| mbed_official | 340:28d1f895c6fe | 3035 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3036 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3037 | /******************** Bit definition for DAC_CR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 3038 | #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */ |
| mbed_official | 340:28d1f895c6fe | 3039 | #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */ |
| mbed_official | 340:28d1f895c6fe | 3040 | #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */ |
| mbed_official | 340:28d1f895c6fe | 3041 | |
| mbed_official | 340:28d1f895c6fe | 3042 | #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ |
| mbed_official | 340:28d1f895c6fe | 3043 | #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3044 | #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3045 | #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3046 | |
| mbed_official | 340:28d1f895c6fe | 3047 | #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
| mbed_official | 340:28d1f895c6fe | 3048 | #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3049 | #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3050 | |
| mbed_official | 340:28d1f895c6fe | 3051 | #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
| mbed_official | 340:28d1f895c6fe | 3052 | #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3053 | #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3054 | #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3055 | #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3056 | |
| mbed_official | 340:28d1f895c6fe | 3057 | #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */ |
| mbed_official | 340:28d1f895c6fe | 3058 | #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */ |
| mbed_official | 340:28d1f895c6fe | 3059 | #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */ |
| mbed_official | 340:28d1f895c6fe | 3060 | #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */ |
| mbed_official | 340:28d1f895c6fe | 3061 | |
| mbed_official | 340:28d1f895c6fe | 3062 | #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ |
| mbed_official | 340:28d1f895c6fe | 3063 | #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3064 | #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3065 | #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3066 | |
| mbed_official | 340:28d1f895c6fe | 3067 | #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
| mbed_official | 340:28d1f895c6fe | 3068 | #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3069 | #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3070 | |
| mbed_official | 340:28d1f895c6fe | 3071 | #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
| mbed_official | 340:28d1f895c6fe | 3072 | #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3073 | #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3074 | #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3075 | #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3076 | |
| mbed_official | 340:28d1f895c6fe | 3077 | #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */ |
| mbed_official | 340:28d1f895c6fe | 3078 | |
| mbed_official | 340:28d1f895c6fe | 3079 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3080 | #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */ |
| mbed_official | 340:28d1f895c6fe | 3081 | #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */ |
| mbed_official | 340:28d1f895c6fe | 3082 | |
| mbed_official | 340:28d1f895c6fe | 3083 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3084 | #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3085 | |
| mbed_official | 340:28d1f895c6fe | 3086 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3087 | #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3088 | |
| mbed_official | 340:28d1f895c6fe | 3089 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3090 | #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3091 | |
| mbed_official | 340:28d1f895c6fe | 3092 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3093 | #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3094 | |
| mbed_official | 340:28d1f895c6fe | 3095 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3096 | #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3097 | |
| mbed_official | 340:28d1f895c6fe | 3098 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3099 | #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3100 | |
| mbed_official | 340:28d1f895c6fe | 3101 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3102 | #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3103 | #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3104 | |
| mbed_official | 340:28d1f895c6fe | 3105 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3106 | #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3107 | #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3108 | |
| mbed_official | 340:28d1f895c6fe | 3109 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3110 | #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3111 | #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */ |
| mbed_official | 340:28d1f895c6fe | 3112 | |
| mbed_official | 340:28d1f895c6fe | 3113 | /******************* Bit definition for DAC_DOR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3114 | #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */ |
| mbed_official | 340:28d1f895c6fe | 3115 | |
| mbed_official | 340:28d1f895c6fe | 3116 | /******************* Bit definition for DAC_DOR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3117 | #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */ |
| mbed_official | 340:28d1f895c6fe | 3118 | |
| mbed_official | 340:28d1f895c6fe | 3119 | /******************** Bit definition for DAC_SR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 3120 | #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */ |
| mbed_official | 340:28d1f895c6fe | 3121 | #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */ |
| mbed_official | 340:28d1f895c6fe | 3122 | |
| mbed_official | 340:28d1f895c6fe | 3123 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3124 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3125 | /* Debug MCU */ |
| mbed_official | 340:28d1f895c6fe | 3126 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3127 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3128 | |
| mbed_official | 340:28d1f895c6fe | 3129 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3130 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3131 | /* DCMI */ |
| mbed_official | 340:28d1f895c6fe | 3132 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3133 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3134 | /******************** Bits definition for DCMI_CR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3135 | #define DCMI_CR_CAPTURE ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3136 | #define DCMI_CR_CM ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3137 | #define DCMI_CR_CROP ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3138 | #define DCMI_CR_JPEG ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3139 | #define DCMI_CR_ESS ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3140 | #define DCMI_CR_PCKPOL ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3141 | #define DCMI_CR_HSPOL ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3142 | #define DCMI_CR_VSPOL ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 3143 | #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3144 | #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3145 | #define DCMI_CR_EDM_0 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3146 | #define DCMI_CR_EDM_1 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3147 | #define DCMI_CR_CRE ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 3148 | #define DCMI_CR_ENABLE ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 3149 | |
| mbed_official | 340:28d1f895c6fe | 3150 | /******************** Bits definition for DCMI_SR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3151 | #define DCMI_SR_HSYNC ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3152 | #define DCMI_SR_VSYNC ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3153 | #define DCMI_SR_FNE ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3154 | |
| mbed_official | 340:28d1f895c6fe | 3155 | /******************** Bits definition for DCMI_RISR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3156 | #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3157 | #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3158 | #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3159 | #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3160 | #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3161 | |
| mbed_official | 340:28d1f895c6fe | 3162 | /******************** Bits definition for DCMI_IER register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3163 | #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3164 | #define DCMI_IER_OVF_IE ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3165 | #define DCMI_IER_ERR_IE ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3166 | #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3167 | #define DCMI_IER_LINE_IE ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3168 | |
| mbed_official | 340:28d1f895c6fe | 3169 | /******************** Bits definition for DCMI_MISR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3170 | #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3171 | #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3172 | #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3173 | #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3174 | #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3175 | |
| mbed_official | 340:28d1f895c6fe | 3176 | /******************** Bits definition for DCMI_ICR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3177 | #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3178 | #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3179 | #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3180 | #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3181 | #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3182 | |
| mbed_official | 340:28d1f895c6fe | 3183 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3184 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3185 | /* DMA Controller */ |
| mbed_official | 340:28d1f895c6fe | 3186 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3187 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3188 | /******************** Bits definition for DMA_SxCR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3189 | #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000) |
| mbed_official | 340:28d1f895c6fe | 3190 | #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 3191 | #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 3192 | #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 3193 | #define DMA_SxCR_MBURST ((uint32_t)0x01800000) |
| mbed_official | 340:28d1f895c6fe | 3194 | #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 3195 | #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 3196 | #define DMA_SxCR_PBURST ((uint32_t)0x00600000) |
| mbed_official | 340:28d1f895c6fe | 3197 | #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 3198 | #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 3199 | #define DMA_SxCR_ACK ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 3200 | #define DMA_SxCR_CT ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 3201 | #define DMA_SxCR_DBM ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 3202 | #define DMA_SxCR_PL ((uint32_t)0x00030000) |
| mbed_official | 340:28d1f895c6fe | 3203 | #define DMA_SxCR_PL_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3204 | #define DMA_SxCR_PL_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 3205 | #define DMA_SxCR_PINCOS ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 3206 | #define DMA_SxCR_MSIZE ((uint32_t)0x00006000) |
| mbed_official | 340:28d1f895c6fe | 3207 | #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 3208 | #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 3209 | #define DMA_SxCR_PSIZE ((uint32_t)0x00001800) |
| mbed_official | 340:28d1f895c6fe | 3210 | #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3211 | #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 3212 | #define DMA_SxCR_MINC ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3213 | #define DMA_SxCR_PINC ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3214 | #define DMA_SxCR_CIRC ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3215 | #define DMA_SxCR_DIR ((uint32_t)0x000000C0) |
| mbed_official | 340:28d1f895c6fe | 3216 | #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3217 | #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 3218 | #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3219 | #define DMA_SxCR_TCIE ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3220 | #define DMA_SxCR_HTIE ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3221 | #define DMA_SxCR_TEIE ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3222 | #define DMA_SxCR_DMEIE ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3223 | #define DMA_SxCR_EN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3224 | |
| mbed_official | 340:28d1f895c6fe | 3225 | /******************** Bits definition for DMA_SxCNDTR register **************/ |
| mbed_official | 340:28d1f895c6fe | 3226 | #define DMA_SxNDT ((uint32_t)0x0000FFFF) |
| mbed_official | 340:28d1f895c6fe | 3227 | #define DMA_SxNDT_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3228 | #define DMA_SxNDT_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3229 | #define DMA_SxNDT_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3230 | #define DMA_SxNDT_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3231 | #define DMA_SxNDT_4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3232 | #define DMA_SxNDT_5 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3233 | #define DMA_SxNDT_6 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3234 | #define DMA_SxNDT_7 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 3235 | #define DMA_SxNDT_8 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3236 | #define DMA_SxNDT_9 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3237 | #define DMA_SxNDT_10 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3238 | #define DMA_SxNDT_11 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3239 | #define DMA_SxNDT_12 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 3240 | #define DMA_SxNDT_13 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 3241 | #define DMA_SxNDT_14 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 3242 | #define DMA_SxNDT_15 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 3243 | |
| mbed_official | 340:28d1f895c6fe | 3244 | /******************** Bits definition for DMA_SxFCR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3245 | #define DMA_SxFCR_FEIE ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 3246 | #define DMA_SxFCR_FS ((uint32_t)0x00000038) |
| mbed_official | 340:28d1f895c6fe | 3247 | #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3248 | #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3249 | #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3250 | #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3251 | #define DMA_SxFCR_FTH ((uint32_t)0x00000003) |
| mbed_official | 340:28d1f895c6fe | 3252 | #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3253 | #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3254 | |
| mbed_official | 340:28d1f895c6fe | 3255 | /******************** Bits definition for DMA_LISR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3256 | #define DMA_LISR_TCIF3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 3257 | #define DMA_LISR_HTIF3 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 3258 | #define DMA_LISR_TEIF3 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 3259 | #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 3260 | #define DMA_LISR_FEIF3 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 3261 | #define DMA_LISR_TCIF2 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 3262 | #define DMA_LISR_HTIF2 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 3263 | #define DMA_LISR_TEIF2 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 3264 | #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 3265 | #define DMA_LISR_FEIF2 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3266 | #define DMA_LISR_TCIF1 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3267 | #define DMA_LISR_HTIF1 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3268 | #define DMA_LISR_TEIF1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3269 | #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3270 | #define DMA_LISR_FEIF1 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3271 | #define DMA_LISR_TCIF0 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3272 | #define DMA_LISR_HTIF0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3273 | #define DMA_LISR_TEIF0 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3274 | #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3275 | #define DMA_LISR_FEIF0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3276 | |
| mbed_official | 340:28d1f895c6fe | 3277 | /******************** Bits definition for DMA_HISR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3278 | #define DMA_HISR_TCIF7 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 3279 | #define DMA_HISR_HTIF7 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 3280 | #define DMA_HISR_TEIF7 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 3281 | #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 3282 | #define DMA_HISR_FEIF7 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 3283 | #define DMA_HISR_TCIF6 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 3284 | #define DMA_HISR_HTIF6 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 3285 | #define DMA_HISR_TEIF6 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 3286 | #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 3287 | #define DMA_HISR_FEIF6 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3288 | #define DMA_HISR_TCIF5 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3289 | #define DMA_HISR_HTIF5 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3290 | #define DMA_HISR_TEIF5 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3291 | #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3292 | #define DMA_HISR_FEIF5 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3293 | #define DMA_HISR_TCIF4 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3294 | #define DMA_HISR_HTIF4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3295 | #define DMA_HISR_TEIF4 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3296 | #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3297 | #define DMA_HISR_FEIF4 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3298 | |
| mbed_official | 340:28d1f895c6fe | 3299 | /******************** Bits definition for DMA_LIFCR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3300 | #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 3301 | #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 3302 | #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 3303 | #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 3304 | #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 3305 | #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 3306 | #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 3307 | #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 3308 | #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 3309 | #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3310 | #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3311 | #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3312 | #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3313 | #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3314 | #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3315 | #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3316 | #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3317 | #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3318 | #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3319 | #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3320 | |
| mbed_official | 340:28d1f895c6fe | 3321 | /******************** Bits definition for DMA_HIFCR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3322 | #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 3323 | #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 3324 | #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 3325 | #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 3326 | #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 3327 | #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 3328 | #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 3329 | #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 3330 | #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 3331 | #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3332 | #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3333 | #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3334 | #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3335 | #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3336 | #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3337 | #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3338 | #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3339 | #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3340 | #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3341 | #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3342 | |
| mbed_official | 340:28d1f895c6fe | 3343 | |
| mbed_official | 340:28d1f895c6fe | 3344 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3345 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3346 | /* AHB Master DMA2D Controller (DMA2D) */ |
| mbed_official | 340:28d1f895c6fe | 3347 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3348 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3349 | |
| mbed_official | 340:28d1f895c6fe | 3350 | /******************** Bit definition for DMA2D_CR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3351 | |
| mbed_official | 340:28d1f895c6fe | 3352 | #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */ |
| mbed_official | 340:28d1f895c6fe | 3353 | #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */ |
| mbed_official | 340:28d1f895c6fe | 3354 | #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */ |
| mbed_official | 340:28d1f895c6fe | 3355 | #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 3356 | #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 3357 | #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 3358 | #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 3359 | #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 3360 | #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 3361 | #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */ |
| mbed_official | 340:28d1f895c6fe | 3362 | |
| mbed_official | 340:28d1f895c6fe | 3363 | /******************** Bit definition for DMA2D_ISR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3364 | |
| mbed_official | 340:28d1f895c6fe | 3365 | #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3366 | #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3367 | #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3368 | #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3369 | #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3370 | #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3371 | |
| mbed_official | 340:28d1f895c6fe | 3372 | /******************** Bit definition for DMA2D_IFSR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3373 | |
| mbed_official | 340:28d1f895c6fe | 3374 | #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3375 | #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3376 | #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3377 | #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3378 | #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3379 | #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 3380 | |
| mbed_official | 340:28d1f895c6fe | 3381 | /******************** Bit definition for DMA2D_FGMAR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 3382 | |
| mbed_official | 340:28d1f895c6fe | 3383 | #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 340:28d1f895c6fe | 3384 | |
| mbed_official | 340:28d1f895c6fe | 3385 | /******************** Bit definition for DMA2D_FGOR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3386 | |
| mbed_official | 340:28d1f895c6fe | 3387 | #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */ |
| mbed_official | 340:28d1f895c6fe | 3388 | |
| mbed_official | 340:28d1f895c6fe | 3389 | /******************** Bit definition for DMA2D_BGMAR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 3390 | |
| mbed_official | 340:28d1f895c6fe | 3391 | #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 340:28d1f895c6fe | 3392 | |
| mbed_official | 340:28d1f895c6fe | 3393 | /******************** Bit definition for DMA2D_BGOR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3394 | |
| mbed_official | 340:28d1f895c6fe | 3395 | #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */ |
| mbed_official | 340:28d1f895c6fe | 3396 | |
| mbed_official | 340:28d1f895c6fe | 3397 | /******************** Bit definition for DMA2D_FGPFCCR register *************/ |
| mbed_official | 340:28d1f895c6fe | 3398 | |
| mbed_official | 340:28d1f895c6fe | 3399 | #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */ |
| mbed_official | 340:28d1f895c6fe | 3400 | #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */ |
| mbed_official | 340:28d1f895c6fe | 3401 | #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */ |
| mbed_official | 340:28d1f895c6fe | 3402 | #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */ |
| mbed_official | 340:28d1f895c6fe | 3403 | #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */ |
| mbed_official | 340:28d1f895c6fe | 3404 | #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */ |
| mbed_official | 340:28d1f895c6fe | 3405 | |
| mbed_official | 340:28d1f895c6fe | 3406 | /******************** Bit definition for DMA2D_FGCOLR register **************/ |
| mbed_official | 340:28d1f895c6fe | 3407 | |
| mbed_official | 340:28d1f895c6fe | 3408 | #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */ |
| mbed_official | 340:28d1f895c6fe | 3409 | #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */ |
| mbed_official | 340:28d1f895c6fe | 3410 | #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */ |
| mbed_official | 340:28d1f895c6fe | 3411 | |
| mbed_official | 340:28d1f895c6fe | 3412 | /******************** Bit definition for DMA2D_BGPFCCR register *************/ |
| mbed_official | 340:28d1f895c6fe | 3413 | |
| mbed_official | 340:28d1f895c6fe | 3414 | #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */ |
| mbed_official | 340:28d1f895c6fe | 3415 | #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */ |
| mbed_official | 340:28d1f895c6fe | 3416 | #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */ |
| mbed_official | 340:28d1f895c6fe | 3417 | #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */ |
| mbed_official | 340:28d1f895c6fe | 3418 | #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */ |
| mbed_official | 340:28d1f895c6fe | 3419 | #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */ |
| mbed_official | 340:28d1f895c6fe | 3420 | |
| mbed_official | 340:28d1f895c6fe | 3421 | /******************** Bit definition for DMA2D_BGCOLR register **************/ |
| mbed_official | 340:28d1f895c6fe | 3422 | |
| mbed_official | 340:28d1f895c6fe | 3423 | #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */ |
| mbed_official | 340:28d1f895c6fe | 3424 | #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */ |
| mbed_official | 340:28d1f895c6fe | 3425 | #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */ |
| mbed_official | 340:28d1f895c6fe | 3426 | |
| mbed_official | 340:28d1f895c6fe | 3427 | /******************** Bit definition for DMA2D_FGCMAR register **************/ |
| mbed_official | 340:28d1f895c6fe | 3428 | |
| mbed_official | 340:28d1f895c6fe | 3429 | #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 340:28d1f895c6fe | 3430 | |
| mbed_official | 340:28d1f895c6fe | 3431 | /******************** Bit definition for DMA2D_BGCMAR register **************/ |
| mbed_official | 340:28d1f895c6fe | 3432 | |
| mbed_official | 340:28d1f895c6fe | 3433 | #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 340:28d1f895c6fe | 3434 | |
| mbed_official | 340:28d1f895c6fe | 3435 | /******************** Bit definition for DMA2D_OPFCCR register **************/ |
| mbed_official | 340:28d1f895c6fe | 3436 | |
| mbed_official | 340:28d1f895c6fe | 3437 | #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */ |
| mbed_official | 340:28d1f895c6fe | 3438 | |
| mbed_official | 340:28d1f895c6fe | 3439 | /******************** Bit definition for DMA2D_OCOLR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 3440 | |
| mbed_official | 340:28d1f895c6fe | 3441 | /*!<Mode_ARGB8888/RGB888 */ |
| mbed_official | 340:28d1f895c6fe | 3442 | |
| mbed_official | 340:28d1f895c6fe | 3443 | #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */ |
| mbed_official | 340:28d1f895c6fe | 3444 | #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */ |
| mbed_official | 340:28d1f895c6fe | 3445 | #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */ |
| mbed_official | 340:28d1f895c6fe | 3446 | #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */ |
| mbed_official | 340:28d1f895c6fe | 3447 | |
| mbed_official | 340:28d1f895c6fe | 3448 | /*!<Mode_RGB565 */ |
| mbed_official | 340:28d1f895c6fe | 3449 | #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */ |
| mbed_official | 340:28d1f895c6fe | 3450 | #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */ |
| mbed_official | 340:28d1f895c6fe | 3451 | #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */ |
| mbed_official | 340:28d1f895c6fe | 3452 | |
| mbed_official | 340:28d1f895c6fe | 3453 | /*!<Mode_ARGB1555 */ |
| mbed_official | 340:28d1f895c6fe | 3454 | #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */ |
| mbed_official | 340:28d1f895c6fe | 3455 | #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */ |
| mbed_official | 340:28d1f895c6fe | 3456 | #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */ |
| mbed_official | 340:28d1f895c6fe | 3457 | #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */ |
| mbed_official | 340:28d1f895c6fe | 3458 | |
| mbed_official | 340:28d1f895c6fe | 3459 | /*!<Mode_ARGB4444 */ |
| mbed_official | 340:28d1f895c6fe | 3460 | #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */ |
| mbed_official | 340:28d1f895c6fe | 3461 | #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */ |
| mbed_official | 340:28d1f895c6fe | 3462 | #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */ |
| mbed_official | 340:28d1f895c6fe | 3463 | #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */ |
| mbed_official | 340:28d1f895c6fe | 3464 | |
| mbed_official | 340:28d1f895c6fe | 3465 | /******************** Bit definition for DMA2D_OMAR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 3466 | |
| mbed_official | 340:28d1f895c6fe | 3467 | #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 340:28d1f895c6fe | 3468 | |
| mbed_official | 340:28d1f895c6fe | 3469 | /******************** Bit definition for DMA2D_OOR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3470 | |
| mbed_official | 340:28d1f895c6fe | 3471 | #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */ |
| mbed_official | 340:28d1f895c6fe | 3472 | |
| mbed_official | 340:28d1f895c6fe | 3473 | /******************** Bit definition for DMA2D_NLR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3474 | |
| mbed_official | 340:28d1f895c6fe | 3475 | #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */ |
| mbed_official | 340:28d1f895c6fe | 3476 | #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */ |
| mbed_official | 340:28d1f895c6fe | 3477 | |
| mbed_official | 340:28d1f895c6fe | 3478 | /******************** Bit definition for DMA2D_LWR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3479 | |
| mbed_official | 340:28d1f895c6fe | 3480 | #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */ |
| mbed_official | 340:28d1f895c6fe | 3481 | |
| mbed_official | 340:28d1f895c6fe | 3482 | /******************** Bit definition for DMA2D_AMTCR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 3483 | |
| mbed_official | 340:28d1f895c6fe | 3484 | #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */ |
| mbed_official | 340:28d1f895c6fe | 3485 | #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */ |
| mbed_official | 340:28d1f895c6fe | 3486 | |
| mbed_official | 340:28d1f895c6fe | 3487 | |
| mbed_official | 340:28d1f895c6fe | 3488 | /******************** Bit definition for DMA2D_FGCLUT register **************/ |
| mbed_official | 340:28d1f895c6fe | 3489 | |
| mbed_official | 340:28d1f895c6fe | 3490 | /******************** Bit definition for DMA2D_BGCLUT register **************/ |
| mbed_official | 340:28d1f895c6fe | 3491 | |
| mbed_official | 340:28d1f895c6fe | 3492 | |
| mbed_official | 340:28d1f895c6fe | 3493 | |
| mbed_official | 340:28d1f895c6fe | 3494 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3495 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3496 | /* External Interrupt/Event Controller */ |
| mbed_official | 340:28d1f895c6fe | 3497 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3498 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3499 | /******************* Bit definition for EXTI_IMR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3500 | #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
| mbed_official | 340:28d1f895c6fe | 3501 | #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
| mbed_official | 340:28d1f895c6fe | 3502 | #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
| mbed_official | 340:28d1f895c6fe | 3503 | #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
| mbed_official | 340:28d1f895c6fe | 3504 | #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
| mbed_official | 340:28d1f895c6fe | 3505 | #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
| mbed_official | 340:28d1f895c6fe | 3506 | #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
| mbed_official | 340:28d1f895c6fe | 3507 | #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
| mbed_official | 340:28d1f895c6fe | 3508 | #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
| mbed_official | 340:28d1f895c6fe | 3509 | #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
| mbed_official | 340:28d1f895c6fe | 3510 | #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
| mbed_official | 340:28d1f895c6fe | 3511 | #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
| mbed_official | 340:28d1f895c6fe | 3512 | #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
| mbed_official | 340:28d1f895c6fe | 3513 | #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
| mbed_official | 340:28d1f895c6fe | 3514 | #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
| mbed_official | 340:28d1f895c6fe | 3515 | #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
| mbed_official | 340:28d1f895c6fe | 3516 | #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
| mbed_official | 340:28d1f895c6fe | 3517 | #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
| mbed_official | 340:28d1f895c6fe | 3518 | #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
| mbed_official | 340:28d1f895c6fe | 3519 | #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
| mbed_official | 532:fe11edbda85c | 3520 | #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ |
| mbed_official | 532:fe11edbda85c | 3521 | #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ |
| mbed_official | 532:fe11edbda85c | 3522 | #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ |
| mbed_official | 340:28d1f895c6fe | 3523 | |
| mbed_official | 340:28d1f895c6fe | 3524 | /******************* Bit definition for EXTI_EMR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3525 | #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
| mbed_official | 340:28d1f895c6fe | 3526 | #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
| mbed_official | 340:28d1f895c6fe | 3527 | #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
| mbed_official | 340:28d1f895c6fe | 3528 | #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
| mbed_official | 340:28d1f895c6fe | 3529 | #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
| mbed_official | 340:28d1f895c6fe | 3530 | #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
| mbed_official | 340:28d1f895c6fe | 3531 | #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
| mbed_official | 340:28d1f895c6fe | 3532 | #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
| mbed_official | 340:28d1f895c6fe | 3533 | #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
| mbed_official | 340:28d1f895c6fe | 3534 | #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
| mbed_official | 340:28d1f895c6fe | 3535 | #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
| mbed_official | 340:28d1f895c6fe | 3536 | #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
| mbed_official | 340:28d1f895c6fe | 3537 | #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
| mbed_official | 340:28d1f895c6fe | 3538 | #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
| mbed_official | 340:28d1f895c6fe | 3539 | #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
| mbed_official | 340:28d1f895c6fe | 3540 | #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
| mbed_official | 340:28d1f895c6fe | 3541 | #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
| mbed_official | 340:28d1f895c6fe | 3542 | #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
| mbed_official | 340:28d1f895c6fe | 3543 | #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
| mbed_official | 340:28d1f895c6fe | 3544 | #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
| mbed_official | 532:fe11edbda85c | 3545 | #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ |
| mbed_official | 532:fe11edbda85c | 3546 | #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ |
| mbed_official | 532:fe11edbda85c | 3547 | #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ |
| mbed_official | 340:28d1f895c6fe | 3548 | |
| mbed_official | 340:28d1f895c6fe | 3549 | /****************** Bit definition for EXTI_RTSR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3550 | #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
| mbed_official | 340:28d1f895c6fe | 3551 | #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
| mbed_official | 340:28d1f895c6fe | 3552 | #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
| mbed_official | 340:28d1f895c6fe | 3553 | #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
| mbed_official | 340:28d1f895c6fe | 3554 | #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
| mbed_official | 340:28d1f895c6fe | 3555 | #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
| mbed_official | 340:28d1f895c6fe | 3556 | #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
| mbed_official | 340:28d1f895c6fe | 3557 | #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
| mbed_official | 340:28d1f895c6fe | 3558 | #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
| mbed_official | 340:28d1f895c6fe | 3559 | #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
| mbed_official | 340:28d1f895c6fe | 3560 | #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
| mbed_official | 340:28d1f895c6fe | 3561 | #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
| mbed_official | 340:28d1f895c6fe | 3562 | #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
| mbed_official | 340:28d1f895c6fe | 3563 | #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
| mbed_official | 340:28d1f895c6fe | 3564 | #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
| mbed_official | 340:28d1f895c6fe | 3565 | #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
| mbed_official | 340:28d1f895c6fe | 3566 | #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
| mbed_official | 340:28d1f895c6fe | 3567 | #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
| mbed_official | 340:28d1f895c6fe | 3568 | #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
| mbed_official | 340:28d1f895c6fe | 3569 | #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
| mbed_official | 532:fe11edbda85c | 3570 | #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ |
| mbed_official | 532:fe11edbda85c | 3571 | #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ |
| mbed_official | 532:fe11edbda85c | 3572 | #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ |
| mbed_official | 340:28d1f895c6fe | 3573 | |
| mbed_official | 340:28d1f895c6fe | 3574 | /****************** Bit definition for EXTI_FTSR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3575 | #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
| mbed_official | 340:28d1f895c6fe | 3576 | #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
| mbed_official | 340:28d1f895c6fe | 3577 | #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
| mbed_official | 340:28d1f895c6fe | 3578 | #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
| mbed_official | 340:28d1f895c6fe | 3579 | #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
| mbed_official | 340:28d1f895c6fe | 3580 | #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
| mbed_official | 340:28d1f895c6fe | 3581 | #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
| mbed_official | 340:28d1f895c6fe | 3582 | #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
| mbed_official | 340:28d1f895c6fe | 3583 | #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
| mbed_official | 340:28d1f895c6fe | 3584 | #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
| mbed_official | 340:28d1f895c6fe | 3585 | #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
| mbed_official | 340:28d1f895c6fe | 3586 | #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
| mbed_official | 340:28d1f895c6fe | 3587 | #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
| mbed_official | 340:28d1f895c6fe | 3588 | #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
| mbed_official | 340:28d1f895c6fe | 3589 | #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
| mbed_official | 340:28d1f895c6fe | 3590 | #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
| mbed_official | 340:28d1f895c6fe | 3591 | #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
| mbed_official | 340:28d1f895c6fe | 3592 | #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
| mbed_official | 340:28d1f895c6fe | 3593 | #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
| mbed_official | 340:28d1f895c6fe | 3594 | #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
| mbed_official | 532:fe11edbda85c | 3595 | #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ |
| mbed_official | 532:fe11edbda85c | 3596 | #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ |
| mbed_official | 532:fe11edbda85c | 3597 | #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ |
| mbed_official | 340:28d1f895c6fe | 3598 | |
| mbed_official | 340:28d1f895c6fe | 3599 | /****************** Bit definition for EXTI_SWIER register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3600 | #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
| mbed_official | 340:28d1f895c6fe | 3601 | #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
| mbed_official | 340:28d1f895c6fe | 3602 | #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
| mbed_official | 340:28d1f895c6fe | 3603 | #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
| mbed_official | 340:28d1f895c6fe | 3604 | #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
| mbed_official | 340:28d1f895c6fe | 3605 | #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
| mbed_official | 340:28d1f895c6fe | 3606 | #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
| mbed_official | 340:28d1f895c6fe | 3607 | #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
| mbed_official | 340:28d1f895c6fe | 3608 | #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
| mbed_official | 340:28d1f895c6fe | 3609 | #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
| mbed_official | 340:28d1f895c6fe | 3610 | #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
| mbed_official | 340:28d1f895c6fe | 3611 | #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
| mbed_official | 340:28d1f895c6fe | 3612 | #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
| mbed_official | 340:28d1f895c6fe | 3613 | #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
| mbed_official | 340:28d1f895c6fe | 3614 | #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
| mbed_official | 340:28d1f895c6fe | 3615 | #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
| mbed_official | 340:28d1f895c6fe | 3616 | #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
| mbed_official | 340:28d1f895c6fe | 3617 | #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
| mbed_official | 340:28d1f895c6fe | 3618 | #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
| mbed_official | 340:28d1f895c6fe | 3619 | #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
| mbed_official | 532:fe11edbda85c | 3620 | #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ |
| mbed_official | 532:fe11edbda85c | 3621 | #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ |
| mbed_official | 532:fe11edbda85c | 3622 | #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ |
| mbed_official | 340:28d1f895c6fe | 3623 | |
| mbed_official | 340:28d1f895c6fe | 3624 | /******************* Bit definition for EXTI_PR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 3625 | #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
| mbed_official | 340:28d1f895c6fe | 3626 | #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
| mbed_official | 340:28d1f895c6fe | 3627 | #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
| mbed_official | 340:28d1f895c6fe | 3628 | #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
| mbed_official | 340:28d1f895c6fe | 3629 | #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
| mbed_official | 340:28d1f895c6fe | 3630 | #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
| mbed_official | 340:28d1f895c6fe | 3631 | #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
| mbed_official | 340:28d1f895c6fe | 3632 | #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
| mbed_official | 340:28d1f895c6fe | 3633 | #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
| mbed_official | 340:28d1f895c6fe | 3634 | #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
| mbed_official | 340:28d1f895c6fe | 3635 | #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
| mbed_official | 340:28d1f895c6fe | 3636 | #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
| mbed_official | 340:28d1f895c6fe | 3637 | #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
| mbed_official | 340:28d1f895c6fe | 3638 | #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
| mbed_official | 340:28d1f895c6fe | 3639 | #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
| mbed_official | 340:28d1f895c6fe | 3640 | #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
| mbed_official | 340:28d1f895c6fe | 3641 | #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
| mbed_official | 340:28d1f895c6fe | 3642 | #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
| mbed_official | 340:28d1f895c6fe | 3643 | #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
| mbed_official | 340:28d1f895c6fe | 3644 | #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
| mbed_official | 532:fe11edbda85c | 3645 | #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ |
| mbed_official | 532:fe11edbda85c | 3646 | #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ |
| mbed_official | 532:fe11edbda85c | 3647 | #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ |
| mbed_official | 340:28d1f895c6fe | 3648 | |
| mbed_official | 340:28d1f895c6fe | 3649 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3650 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3651 | /* FLASH */ |
| mbed_official | 340:28d1f895c6fe | 3652 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3653 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3654 | /******************* Bits definition for FLASH_ACR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 3655 | #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 3656 | #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 3657 | #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3658 | #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3659 | #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) |
| mbed_official | 340:28d1f895c6fe | 3660 | #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3661 | #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) |
| mbed_official | 340:28d1f895c6fe | 3662 | #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) |
| mbed_official | 340:28d1f895c6fe | 3663 | #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) |
| mbed_official | 340:28d1f895c6fe | 3664 | #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3665 | #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009) |
| mbed_official | 340:28d1f895c6fe | 3666 | #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A) |
| mbed_official | 340:28d1f895c6fe | 3667 | #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B) |
| mbed_official | 340:28d1f895c6fe | 3668 | #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C) |
| mbed_official | 340:28d1f895c6fe | 3669 | #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D) |
| mbed_official | 340:28d1f895c6fe | 3670 | #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E) |
| mbed_official | 340:28d1f895c6fe | 3671 | #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 3672 | #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3673 | #define FLASH_ACR_ICEN ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3674 | #define FLASH_ACR_DCEN ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3675 | #define FLASH_ACR_ICRST ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3676 | #define FLASH_ACR_DCRST ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 3677 | #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) |
| mbed_official | 340:28d1f895c6fe | 3678 | #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) |
| mbed_official | 340:28d1f895c6fe | 3679 | |
| mbed_official | 340:28d1f895c6fe | 3680 | /******************* Bits definition for FLASH_SR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3681 | #define FLASH_SR_EOP ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3682 | #define FLASH_SR_SOP ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3683 | #define FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3684 | #define FLASH_SR_PGAERR ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3685 | #define FLASH_SR_PGPERR ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3686 | #define FLASH_SR_PGSERR ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 3687 | #define FLASH_SR_BSY ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3688 | |
| mbed_official | 340:28d1f895c6fe | 3689 | /******************* Bits definition for FLASH_CR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3690 | #define FLASH_CR_PG ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3691 | #define FLASH_CR_SER ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3692 | #define FLASH_CR_MER ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3693 | #define FLASH_CR_MER1 FLASH_CR_MER |
| mbed_official | 340:28d1f895c6fe | 3694 | #define FLASH_CR_SNB ((uint32_t)0x000000F8) |
| mbed_official | 340:28d1f895c6fe | 3695 | #define FLASH_CR_SNB_0 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3696 | #define FLASH_CR_SNB_1 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3697 | #define FLASH_CR_SNB_2 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3698 | #define FLASH_CR_SNB_3 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3699 | #define FLASH_CR_SNB_4 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 3700 | #define FLASH_CR_PSIZE ((uint32_t)0x00000300) |
| mbed_official | 340:28d1f895c6fe | 3701 | #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3702 | #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3703 | #define FLASH_CR_MER2 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 3704 | #define FLASH_CR_STRT ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3705 | #define FLASH_CR_EOPIE ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 3706 | #define FLASH_CR_LOCK ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 3707 | |
| mbed_official | 340:28d1f895c6fe | 3708 | /******************* Bits definition for FLASH_OPTCR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 3709 | #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 3710 | #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 3711 | #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 3712 | #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 3713 | #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) |
| mbed_official | 340:28d1f895c6fe | 3714 | #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 3715 | #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 3716 | #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 3717 | #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 3718 | #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00) |
| mbed_official | 340:28d1f895c6fe | 3719 | #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 3720 | #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 3721 | #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 3722 | #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 3723 | #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 3724 | #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 3725 | #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 3726 | #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 3727 | #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000) |
| mbed_official | 340:28d1f895c6fe | 3728 | #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3729 | #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 3730 | #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 3731 | #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 3732 | #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 3733 | #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 3734 | #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 3735 | #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 3736 | #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 3737 | #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 3738 | #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 3739 | #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 3740 | #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 3741 | #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 3742 | |
| mbed_official | 340:28d1f895c6fe | 3743 | /****************** Bits definition for FLASH_OPTCR1 register ***************/ |
| mbed_official | 340:28d1f895c6fe | 3744 | #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000) |
| mbed_official | 340:28d1f895c6fe | 3745 | #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 3746 | #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 3747 | #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 3748 | #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 3749 | #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 3750 | #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 3751 | #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 3752 | #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 3753 | #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 3754 | #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 3755 | #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 3756 | #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 3757 | |
| mbed_official | 340:28d1f895c6fe | 3758 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3759 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3760 | /* Flexible Memory Controller */ |
| mbed_official | 340:28d1f895c6fe | 3761 | /* */ |
| mbed_official | 340:28d1f895c6fe | 3762 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 3763 | /****************** Bit definition for FMC_BCR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3764 | #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3765 | #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3766 | |
| mbed_official | 340:28d1f895c6fe | 3767 | #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
| mbed_official | 340:28d1f895c6fe | 3768 | #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3769 | #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3770 | |
| mbed_official | 340:28d1f895c6fe | 3771 | #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 340:28d1f895c6fe | 3772 | #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3773 | #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3774 | |
| mbed_official | 340:28d1f895c6fe | 3775 | #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
| mbed_official | 340:28d1f895c6fe | 3776 | #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3777 | #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
| mbed_official | 340:28d1f895c6fe | 3778 | #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
| mbed_official | 340:28d1f895c6fe | 3779 | #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
| mbed_official | 340:28d1f895c6fe | 3780 | #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3781 | #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3782 | #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
| mbed_official | 340:28d1f895c6fe | 3783 | #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
| mbed_official | 340:28d1f895c6fe | 3784 | #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
| mbed_official | 340:28d1f895c6fe | 3785 | #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */ |
| mbed_official | 340:28d1f895c6fe | 3786 | |
| mbed_official | 340:28d1f895c6fe | 3787 | /****************** Bit definition for FMC_BCR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3788 | #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3789 | #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3790 | |
| mbed_official | 340:28d1f895c6fe | 3791 | #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
| mbed_official | 340:28d1f895c6fe | 3792 | #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3793 | #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3794 | |
| mbed_official | 340:28d1f895c6fe | 3795 | #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 340:28d1f895c6fe | 3796 | #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3797 | #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3798 | |
| mbed_official | 340:28d1f895c6fe | 3799 | #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
| mbed_official | 340:28d1f895c6fe | 3800 | #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3801 | #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
| mbed_official | 340:28d1f895c6fe | 3802 | #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
| mbed_official | 340:28d1f895c6fe | 3803 | #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
| mbed_official | 340:28d1f895c6fe | 3804 | #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3805 | #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3806 | #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
| mbed_official | 340:28d1f895c6fe | 3807 | #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
| mbed_official | 340:28d1f895c6fe | 3808 | #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
| mbed_official | 340:28d1f895c6fe | 3809 | |
| mbed_official | 340:28d1f895c6fe | 3810 | /****************** Bit definition for FMC_BCR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3811 | #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3812 | #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3813 | |
| mbed_official | 340:28d1f895c6fe | 3814 | #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
| mbed_official | 340:28d1f895c6fe | 3815 | #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3816 | #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3817 | |
| mbed_official | 340:28d1f895c6fe | 3818 | #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 340:28d1f895c6fe | 3819 | #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3820 | #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3821 | |
| mbed_official | 340:28d1f895c6fe | 3822 | #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
| mbed_official | 340:28d1f895c6fe | 3823 | #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3824 | #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
| mbed_official | 340:28d1f895c6fe | 3825 | #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
| mbed_official | 340:28d1f895c6fe | 3826 | #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
| mbed_official | 340:28d1f895c6fe | 3827 | #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3828 | #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3829 | #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
| mbed_official | 340:28d1f895c6fe | 3830 | #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
| mbed_official | 340:28d1f895c6fe | 3831 | #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
| mbed_official | 340:28d1f895c6fe | 3832 | |
| mbed_official | 340:28d1f895c6fe | 3833 | /****************** Bit definition for FMC_BCR4 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3834 | #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3835 | #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3836 | |
| mbed_official | 340:28d1f895c6fe | 3837 | #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
| mbed_official | 340:28d1f895c6fe | 3838 | #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3839 | #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3840 | |
| mbed_official | 340:28d1f895c6fe | 3841 | #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 340:28d1f895c6fe | 3842 | #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3843 | #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3844 | |
| mbed_official | 340:28d1f895c6fe | 3845 | #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
| mbed_official | 340:28d1f895c6fe | 3846 | #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3847 | #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
| mbed_official | 340:28d1f895c6fe | 3848 | #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
| mbed_official | 340:28d1f895c6fe | 3849 | #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
| mbed_official | 340:28d1f895c6fe | 3850 | #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3851 | #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
| mbed_official | 340:28d1f895c6fe | 3852 | #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
| mbed_official | 340:28d1f895c6fe | 3853 | #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
| mbed_official | 340:28d1f895c6fe | 3854 | #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
| mbed_official | 340:28d1f895c6fe | 3855 | |
| mbed_official | 340:28d1f895c6fe | 3856 | /****************** Bit definition for FMC_BTR1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 3857 | #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3858 | #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3859 | #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3860 | #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3861 | #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3862 | |
| mbed_official | 340:28d1f895c6fe | 3863 | #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3864 | #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3865 | #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3866 | #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3867 | #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3868 | |
| mbed_official | 340:28d1f895c6fe | 3869 | #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3870 | #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3871 | #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3872 | #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3873 | #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3874 | #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 3875 | #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 3876 | #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 3877 | #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 3878 | |
| mbed_official | 340:28d1f895c6fe | 3879 | #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3880 | #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3881 | #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3882 | #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3883 | #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3884 | |
| mbed_official | 340:28d1f895c6fe | 3885 | #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 340:28d1f895c6fe | 3886 | #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3887 | #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3888 | #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3889 | #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3890 | |
| mbed_official | 340:28d1f895c6fe | 3891 | #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 340:28d1f895c6fe | 3892 | #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3893 | #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3894 | #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3895 | #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3896 | |
| mbed_official | 340:28d1f895c6fe | 3897 | #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 340:28d1f895c6fe | 3898 | #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3899 | #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3900 | |
| mbed_official | 340:28d1f895c6fe | 3901 | /****************** Bit definition for FMC_BTR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3902 | #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3903 | #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3904 | #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3905 | #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3906 | #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3907 | |
| mbed_official | 340:28d1f895c6fe | 3908 | #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3909 | #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3910 | #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3911 | #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3912 | #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3913 | |
| mbed_official | 340:28d1f895c6fe | 3914 | #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3915 | #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3916 | #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3917 | #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3918 | #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3919 | #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 3920 | #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 3921 | #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 3922 | #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 3923 | |
| mbed_official | 340:28d1f895c6fe | 3924 | #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3925 | #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3926 | #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3927 | #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3928 | #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3929 | |
| mbed_official | 340:28d1f895c6fe | 3930 | #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 340:28d1f895c6fe | 3931 | #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3932 | #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3933 | #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3934 | #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3935 | |
| mbed_official | 340:28d1f895c6fe | 3936 | #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 340:28d1f895c6fe | 3937 | #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3938 | #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3939 | #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3940 | #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3941 | |
| mbed_official | 340:28d1f895c6fe | 3942 | #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 340:28d1f895c6fe | 3943 | #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3944 | #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3945 | |
| mbed_official | 340:28d1f895c6fe | 3946 | /******************* Bit definition for FMC_BTR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3947 | #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3948 | #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3949 | #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3950 | #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3951 | #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3952 | |
| mbed_official | 340:28d1f895c6fe | 3953 | #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3954 | #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3955 | #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3956 | #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3957 | #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3958 | |
| mbed_official | 340:28d1f895c6fe | 3959 | #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3960 | #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3961 | #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3962 | #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3963 | #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3964 | #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 3965 | #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 3966 | #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 3967 | #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 3968 | |
| mbed_official | 340:28d1f895c6fe | 3969 | #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3970 | #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3971 | #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3972 | #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3973 | #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3974 | |
| mbed_official | 340:28d1f895c6fe | 3975 | #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 340:28d1f895c6fe | 3976 | #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3977 | #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3978 | #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3979 | #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3980 | |
| mbed_official | 340:28d1f895c6fe | 3981 | #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 340:28d1f895c6fe | 3982 | #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3983 | #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3984 | #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3985 | #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3986 | |
| mbed_official | 340:28d1f895c6fe | 3987 | #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 340:28d1f895c6fe | 3988 | #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3989 | #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3990 | |
| mbed_official | 340:28d1f895c6fe | 3991 | /****************** Bit definition for FMC_BTR4 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 3992 | #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3993 | #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 3994 | #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 3995 | #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 3996 | #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 3997 | |
| mbed_official | 340:28d1f895c6fe | 3998 | #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 3999 | #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4000 | #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4001 | #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4002 | #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4003 | |
| mbed_official | 340:28d1f895c6fe | 4004 | #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4005 | #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4006 | #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4007 | #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4008 | #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4009 | #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4010 | #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4011 | #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4012 | #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4013 | |
| mbed_official | 340:28d1f895c6fe | 4014 | #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4015 | #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4016 | #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4017 | #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4018 | #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4019 | |
| mbed_official | 340:28d1f895c6fe | 4020 | #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 340:28d1f895c6fe | 4021 | #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4022 | #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4023 | #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4024 | #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4025 | |
| mbed_official | 340:28d1f895c6fe | 4026 | #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 340:28d1f895c6fe | 4027 | #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4028 | #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4029 | #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4030 | #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4031 | |
| mbed_official | 340:28d1f895c6fe | 4032 | #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 340:28d1f895c6fe | 4033 | #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4034 | #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4035 | |
| mbed_official | 340:28d1f895c6fe | 4036 | /****************** Bit definition for FMC_BWTR1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4037 | #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4038 | #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4039 | #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4040 | #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4041 | #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4042 | |
| mbed_official | 340:28d1f895c6fe | 4043 | #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4044 | #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4045 | #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4046 | #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4047 | #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4048 | |
| mbed_official | 340:28d1f895c6fe | 4049 | #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4050 | #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4051 | #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4052 | #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4053 | #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4054 | #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4055 | #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4056 | #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4057 | #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4058 | |
| mbed_official | 532:fe11edbda85c | 4059 | #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ |
| mbed_official | 532:fe11edbda85c | 4060 | #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 532:fe11edbda85c | 4061 | #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 532:fe11edbda85c | 4062 | #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 532:fe11edbda85c | 4063 | #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 532:fe11edbda85c | 4064 | |
| mbed_official | 340:28d1f895c6fe | 4065 | #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 340:28d1f895c6fe | 4066 | #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4067 | #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4068 | #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4069 | #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4070 | |
| mbed_official | 340:28d1f895c6fe | 4071 | #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 340:28d1f895c6fe | 4072 | #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4073 | #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4074 | #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4075 | #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4076 | |
| mbed_official | 340:28d1f895c6fe | 4077 | #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 340:28d1f895c6fe | 4078 | #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4079 | #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4080 | |
| mbed_official | 340:28d1f895c6fe | 4081 | /****************** Bit definition for FMC_BWTR2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4082 | #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4083 | #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4084 | #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4085 | #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4086 | #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4087 | |
| mbed_official | 340:28d1f895c6fe | 4088 | #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4089 | #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4090 | #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4091 | #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4092 | #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4093 | |
| mbed_official | 340:28d1f895c6fe | 4094 | #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4095 | #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4096 | #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4097 | #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4098 | #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4099 | #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4100 | #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4101 | #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4102 | #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4103 | |
| mbed_official | 532:fe11edbda85c | 4104 | #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ |
| mbed_official | 532:fe11edbda85c | 4105 | #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 532:fe11edbda85c | 4106 | #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 532:fe11edbda85c | 4107 | #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 532:fe11edbda85c | 4108 | #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 532:fe11edbda85c | 4109 | |
| mbed_official | 340:28d1f895c6fe | 4110 | #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 340:28d1f895c6fe | 4111 | #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4112 | #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ |
| mbed_official | 340:28d1f895c6fe | 4113 | #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4114 | #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4115 | |
| mbed_official | 340:28d1f895c6fe | 4116 | #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 340:28d1f895c6fe | 4117 | #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4118 | #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4119 | #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4120 | #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4121 | |
| mbed_official | 340:28d1f895c6fe | 4122 | #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 340:28d1f895c6fe | 4123 | #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4124 | #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4125 | |
| mbed_official | 340:28d1f895c6fe | 4126 | /****************** Bit definition for FMC_BWTR3 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4127 | #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4128 | #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4129 | #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4130 | #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4131 | #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4132 | |
| mbed_official | 340:28d1f895c6fe | 4133 | #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4134 | #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4135 | #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4136 | #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4137 | #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4138 | |
| mbed_official | 340:28d1f895c6fe | 4139 | #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4140 | #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4141 | #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4142 | #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4143 | #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4144 | #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4145 | #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4146 | #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4147 | #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4148 | |
| mbed_official | 532:fe11edbda85c | 4149 | #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ |
| mbed_official | 532:fe11edbda85c | 4150 | #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 532:fe11edbda85c | 4151 | #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 532:fe11edbda85c | 4152 | #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 532:fe11edbda85c | 4153 | #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 532:fe11edbda85c | 4154 | |
| mbed_official | 340:28d1f895c6fe | 4155 | #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 340:28d1f895c6fe | 4156 | #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4157 | #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4158 | #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4159 | #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4160 | |
| mbed_official | 340:28d1f895c6fe | 4161 | #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 340:28d1f895c6fe | 4162 | #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4163 | #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4164 | #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4165 | #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4166 | |
| mbed_official | 340:28d1f895c6fe | 4167 | #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 340:28d1f895c6fe | 4168 | #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4169 | #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4170 | |
| mbed_official | 340:28d1f895c6fe | 4171 | /****************** Bit definition for FMC_BWTR4 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4172 | #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4173 | #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4174 | #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4175 | #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4176 | #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4177 | |
| mbed_official | 340:28d1f895c6fe | 4178 | #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4179 | #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4180 | #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4181 | #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4182 | #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4183 | |
| mbed_official | 340:28d1f895c6fe | 4184 | #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 340:28d1f895c6fe | 4185 | #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4186 | #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4187 | #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4188 | #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4189 | #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4190 | #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4191 | #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4192 | #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4193 | |
| mbed_official | 532:fe11edbda85c | 4194 | #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ |
| mbed_official | 532:fe11edbda85c | 4195 | #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 532:fe11edbda85c | 4196 | #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 532:fe11edbda85c | 4197 | #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 532:fe11edbda85c | 4198 | #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 532:fe11edbda85c | 4199 | |
| mbed_official | 340:28d1f895c6fe | 4200 | #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 340:28d1f895c6fe | 4201 | #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4202 | #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4203 | #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4204 | #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4205 | |
| mbed_official | 340:28d1f895c6fe | 4206 | #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 340:28d1f895c6fe | 4207 | #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4208 | #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4209 | #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4210 | #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4211 | |
| mbed_official | 340:28d1f895c6fe | 4212 | #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 340:28d1f895c6fe | 4213 | #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4214 | #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4215 | |
| mbed_official | 340:28d1f895c6fe | 4216 | /****************** Bit definition for FMC_PCR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 4217 | #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4218 | #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4219 | #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
| mbed_official | 340:28d1f895c6fe | 4220 | |
| mbed_official | 340:28d1f895c6fe | 4221 | #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
| mbed_official | 340:28d1f895c6fe | 4222 | #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4223 | #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4224 | |
| mbed_official | 340:28d1f895c6fe | 4225 | #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4226 | |
| mbed_official | 340:28d1f895c6fe | 4227 | #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
| mbed_official | 340:28d1f895c6fe | 4228 | #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4229 | #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4230 | #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4231 | #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4232 | |
| mbed_official | 340:28d1f895c6fe | 4233 | #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
| mbed_official | 340:28d1f895c6fe | 4234 | #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4235 | #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4236 | #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4237 | #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4238 | |
| mbed_official | 340:28d1f895c6fe | 4239 | #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */ |
| mbed_official | 340:28d1f895c6fe | 4240 | #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4241 | #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4242 | #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4243 | |
| mbed_official | 340:28d1f895c6fe | 4244 | /****************** Bit definition for FMC_PCR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 4245 | #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4246 | #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4247 | #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
| mbed_official | 340:28d1f895c6fe | 4248 | |
| mbed_official | 340:28d1f895c6fe | 4249 | #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
| mbed_official | 340:28d1f895c6fe | 4250 | #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4251 | #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4252 | |
| mbed_official | 340:28d1f895c6fe | 4253 | #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4254 | |
| mbed_official | 340:28d1f895c6fe | 4255 | #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
| mbed_official | 340:28d1f895c6fe | 4256 | #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4257 | #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4258 | #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4259 | #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4260 | |
| mbed_official | 340:28d1f895c6fe | 4261 | #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
| mbed_official | 340:28d1f895c6fe | 4262 | #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4263 | #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4264 | #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4265 | #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4266 | |
| mbed_official | 340:28d1f895c6fe | 4267 | #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ |
| mbed_official | 340:28d1f895c6fe | 4268 | #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4269 | #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4270 | #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4271 | |
| mbed_official | 340:28d1f895c6fe | 4272 | /****************** Bit definition for FMC_PCR4 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 4273 | #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4274 | #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4275 | #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
| mbed_official | 340:28d1f895c6fe | 4276 | |
| mbed_official | 340:28d1f895c6fe | 4277 | #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
| mbed_official | 340:28d1f895c6fe | 4278 | #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4279 | #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4280 | |
| mbed_official | 340:28d1f895c6fe | 4281 | #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4282 | |
| mbed_official | 340:28d1f895c6fe | 4283 | #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
| mbed_official | 340:28d1f895c6fe | 4284 | #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4285 | #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4286 | #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4287 | #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4288 | |
| mbed_official | 340:28d1f895c6fe | 4289 | #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
| mbed_official | 340:28d1f895c6fe | 4290 | #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4291 | #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4292 | #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4293 | #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4294 | |
| mbed_official | 340:28d1f895c6fe | 4295 | #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ |
| mbed_official | 340:28d1f895c6fe | 4296 | #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4297 | #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4298 | #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4299 | |
| mbed_official | 340:28d1f895c6fe | 4300 | /******************* Bit definition for FMC_SR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 4301 | #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ |
| mbed_official | 340:28d1f895c6fe | 4302 | #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ |
| mbed_official | 340:28d1f895c6fe | 4303 | #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ |
| mbed_official | 340:28d1f895c6fe | 4304 | #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4305 | #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4306 | #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4307 | #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ |
| mbed_official | 340:28d1f895c6fe | 4308 | |
| mbed_official | 340:28d1f895c6fe | 4309 | /******************* Bit definition for FMC_SR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 4310 | #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ |
| mbed_official | 340:28d1f895c6fe | 4311 | #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ |
| mbed_official | 340:28d1f895c6fe | 4312 | #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ |
| mbed_official | 340:28d1f895c6fe | 4313 | #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4314 | #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4315 | #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4316 | #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ |
| mbed_official | 340:28d1f895c6fe | 4317 | |
| mbed_official | 340:28d1f895c6fe | 4318 | /******************* Bit definition for FMC_SR4 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 4319 | #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ |
| mbed_official | 340:28d1f895c6fe | 4320 | #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ |
| mbed_official | 340:28d1f895c6fe | 4321 | #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ |
| mbed_official | 340:28d1f895c6fe | 4322 | #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4323 | #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4324 | #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 4325 | #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ |
| mbed_official | 340:28d1f895c6fe | 4326 | |
| mbed_official | 340:28d1f895c6fe | 4327 | /****************** Bit definition for FMC_PMEM2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4328 | #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ |
| mbed_official | 340:28d1f895c6fe | 4329 | #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4330 | #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4331 | #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4332 | #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4333 | #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4334 | #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4335 | #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4336 | #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4337 | |
| mbed_official | 340:28d1f895c6fe | 4338 | #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ |
| mbed_official | 340:28d1f895c6fe | 4339 | #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4340 | #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4341 | #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4342 | #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4343 | #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4344 | #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4345 | #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4346 | #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4347 | |
| mbed_official | 340:28d1f895c6fe | 4348 | #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ |
| mbed_official | 340:28d1f895c6fe | 4349 | #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4350 | #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4351 | #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4352 | #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4353 | #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4354 | #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4355 | #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4356 | #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4357 | |
| mbed_official | 340:28d1f895c6fe | 4358 | #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ |
| mbed_official | 340:28d1f895c6fe | 4359 | #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4360 | #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4361 | #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4362 | #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4363 | #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4364 | #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4365 | #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4366 | #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4367 | |
| mbed_official | 340:28d1f895c6fe | 4368 | /****************** Bit definition for FMC_PMEM3 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4369 | #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */ |
| mbed_official | 340:28d1f895c6fe | 4370 | #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4371 | #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4372 | #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4373 | #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4374 | #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4375 | #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4376 | #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4377 | #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4378 | |
| mbed_official | 340:28d1f895c6fe | 4379 | #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */ |
| mbed_official | 340:28d1f895c6fe | 4380 | #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4381 | #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4382 | #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4383 | #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4384 | #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4385 | #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4386 | #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4387 | #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4388 | |
| mbed_official | 340:28d1f895c6fe | 4389 | #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */ |
| mbed_official | 340:28d1f895c6fe | 4390 | #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4391 | #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4392 | #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4393 | #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4394 | #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4395 | #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4396 | #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4397 | #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4398 | |
| mbed_official | 340:28d1f895c6fe | 4399 | #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ |
| mbed_official | 340:28d1f895c6fe | 4400 | #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4401 | #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4402 | #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4403 | #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4404 | #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4405 | #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4406 | #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4407 | #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4408 | |
| mbed_official | 340:28d1f895c6fe | 4409 | /****************** Bit definition for FMC_PMEM4 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4410 | #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */ |
| mbed_official | 340:28d1f895c6fe | 4411 | #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4412 | #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4413 | #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4414 | #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4415 | #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4416 | #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4417 | #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4418 | #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4419 | |
| mbed_official | 340:28d1f895c6fe | 4420 | #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */ |
| mbed_official | 340:28d1f895c6fe | 4421 | #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4422 | #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4423 | #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4424 | #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4425 | #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4426 | #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4427 | #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4428 | #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4429 | |
| mbed_official | 340:28d1f895c6fe | 4430 | #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */ |
| mbed_official | 340:28d1f895c6fe | 4431 | #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4432 | #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4433 | #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4434 | #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4435 | #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4436 | #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4437 | #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4438 | #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4439 | |
| mbed_official | 340:28d1f895c6fe | 4440 | #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ |
| mbed_official | 340:28d1f895c6fe | 4441 | #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4442 | #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4443 | #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4444 | #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4445 | #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4446 | #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4447 | #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4448 | #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4449 | |
| mbed_official | 340:28d1f895c6fe | 4450 | /****************** Bit definition for FMC_PATT2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4451 | #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ |
| mbed_official | 340:28d1f895c6fe | 4452 | #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4453 | #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4454 | #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4455 | #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4456 | #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4457 | #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4458 | #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4459 | #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4460 | |
| mbed_official | 340:28d1f895c6fe | 4461 | #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ |
| mbed_official | 340:28d1f895c6fe | 4462 | #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4463 | #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4464 | #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4465 | #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4466 | #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4467 | #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4468 | #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4469 | #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4470 | |
| mbed_official | 340:28d1f895c6fe | 4471 | #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ |
| mbed_official | 340:28d1f895c6fe | 4472 | #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4473 | #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4474 | #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4475 | #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4476 | #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4477 | #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4478 | #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4479 | #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4480 | |
| mbed_official | 340:28d1f895c6fe | 4481 | #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ |
| mbed_official | 340:28d1f895c6fe | 4482 | #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4483 | #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4484 | #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4485 | #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4486 | #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4487 | #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4488 | #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4489 | #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4490 | |
| mbed_official | 340:28d1f895c6fe | 4491 | /****************** Bit definition for FMC_PATT3 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4492 | #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */ |
| mbed_official | 340:28d1f895c6fe | 4493 | #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4494 | #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4495 | #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4496 | #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4497 | #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4498 | #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4499 | #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4500 | #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4501 | |
| mbed_official | 340:28d1f895c6fe | 4502 | #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ |
| mbed_official | 340:28d1f895c6fe | 4503 | #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4504 | #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4505 | #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4506 | #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4507 | #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4508 | #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4509 | #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4510 | #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4511 | |
| mbed_official | 340:28d1f895c6fe | 4512 | #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ |
| mbed_official | 340:28d1f895c6fe | 4513 | #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4514 | #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4515 | #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4516 | #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4517 | #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4518 | #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4519 | #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4520 | #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4521 | |
| mbed_official | 340:28d1f895c6fe | 4522 | #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ |
| mbed_official | 340:28d1f895c6fe | 4523 | #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4524 | #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4525 | #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4526 | #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4527 | #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4528 | #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4529 | #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4530 | #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4531 | |
| mbed_official | 340:28d1f895c6fe | 4532 | /****************** Bit definition for FMC_PATT4 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4533 | #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */ |
| mbed_official | 340:28d1f895c6fe | 4534 | #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4535 | #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4536 | #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4537 | #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4538 | #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4539 | #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4540 | #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4541 | #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4542 | |
| mbed_official | 340:28d1f895c6fe | 4543 | #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ |
| mbed_official | 340:28d1f895c6fe | 4544 | #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4545 | #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4546 | #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4547 | #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4548 | #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4549 | #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4550 | #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4551 | #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4552 | |
| mbed_official | 340:28d1f895c6fe | 4553 | #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ |
| mbed_official | 340:28d1f895c6fe | 4554 | #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4555 | #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4556 | #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4557 | #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4558 | #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4559 | #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4560 | #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4561 | #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4562 | |
| mbed_official | 340:28d1f895c6fe | 4563 | #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ |
| mbed_official | 340:28d1f895c6fe | 4564 | #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4565 | #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4566 | #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4567 | #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4568 | #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4569 | #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4570 | #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4571 | #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4572 | |
| mbed_official | 340:28d1f895c6fe | 4573 | /****************** Bit definition for FMC_PIO4 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 4574 | #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */ |
| mbed_official | 340:28d1f895c6fe | 4575 | #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4576 | #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4577 | #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4578 | #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4579 | #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4580 | #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4581 | #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4582 | #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4583 | |
| mbed_official | 340:28d1f895c6fe | 4584 | #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */ |
| mbed_official | 340:28d1f895c6fe | 4585 | #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4586 | #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4587 | #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4588 | #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4589 | #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4590 | #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4591 | #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4592 | #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4593 | |
| mbed_official | 340:28d1f895c6fe | 4594 | #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */ |
| mbed_official | 340:28d1f895c6fe | 4595 | #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4596 | #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4597 | #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4598 | #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4599 | #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4600 | #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4601 | #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4602 | #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4603 | |
| mbed_official | 340:28d1f895c6fe | 4604 | #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ |
| mbed_official | 340:28d1f895c6fe | 4605 | #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4606 | #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4607 | #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4608 | #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4609 | #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 4610 | #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 4611 | #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 4612 | #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 4613 | |
| mbed_official | 340:28d1f895c6fe | 4614 | /****************** Bit definition for FMC_ECCR2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4615 | #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
| mbed_official | 340:28d1f895c6fe | 4616 | |
| mbed_official | 340:28d1f895c6fe | 4617 | /****************** Bit definition for FMC_ECCR3 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4618 | #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
| mbed_official | 340:28d1f895c6fe | 4619 | |
| mbed_official | 340:28d1f895c6fe | 4620 | /****************** Bit definition for FMC_SDCR1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4621 | #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */ |
| mbed_official | 340:28d1f895c6fe | 4622 | #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4623 | #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4624 | |
| mbed_official | 340:28d1f895c6fe | 4625 | #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */ |
| mbed_official | 340:28d1f895c6fe | 4626 | #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4627 | #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4628 | |
| mbed_official | 340:28d1f895c6fe | 4629 | #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */ |
| mbed_official | 340:28d1f895c6fe | 4630 | #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4631 | #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4632 | |
| mbed_official | 340:28d1f895c6fe | 4633 | #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */ |
| mbed_official | 340:28d1f895c6fe | 4634 | |
| mbed_official | 340:28d1f895c6fe | 4635 | #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */ |
| mbed_official | 340:28d1f895c6fe | 4636 | #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4637 | #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4638 | |
| mbed_official | 340:28d1f895c6fe | 4639 | #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */ |
| mbed_official | 340:28d1f895c6fe | 4640 | |
| mbed_official | 340:28d1f895c6fe | 4641 | #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */ |
| mbed_official | 340:28d1f895c6fe | 4642 | #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4643 | #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4644 | |
| mbed_official | 340:28d1f895c6fe | 4645 | #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */ |
| mbed_official | 340:28d1f895c6fe | 4646 | |
| mbed_official | 340:28d1f895c6fe | 4647 | #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */ |
| mbed_official | 340:28d1f895c6fe | 4648 | #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4649 | #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4650 | |
| mbed_official | 340:28d1f895c6fe | 4651 | /****************** Bit definition for FMC_SDCR2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4652 | #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */ |
| mbed_official | 340:28d1f895c6fe | 4653 | #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4654 | #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4655 | |
| mbed_official | 340:28d1f895c6fe | 4656 | #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */ |
| mbed_official | 340:28d1f895c6fe | 4657 | #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4658 | #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4659 | |
| mbed_official | 340:28d1f895c6fe | 4660 | #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */ |
| mbed_official | 340:28d1f895c6fe | 4661 | #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4662 | #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4663 | |
| mbed_official | 340:28d1f895c6fe | 4664 | #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */ |
| mbed_official | 340:28d1f895c6fe | 4665 | |
| mbed_official | 340:28d1f895c6fe | 4666 | #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */ |
| mbed_official | 340:28d1f895c6fe | 4667 | #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4668 | #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4669 | |
| mbed_official | 340:28d1f895c6fe | 4670 | #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */ |
| mbed_official | 340:28d1f895c6fe | 4671 | |
| mbed_official | 340:28d1f895c6fe | 4672 | #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */ |
| mbed_official | 340:28d1f895c6fe | 4673 | #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4674 | #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4675 | |
| mbed_official | 340:28d1f895c6fe | 4676 | #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */ |
| mbed_official | 340:28d1f895c6fe | 4677 | |
| mbed_official | 340:28d1f895c6fe | 4678 | #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */ |
| mbed_official | 340:28d1f895c6fe | 4679 | #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4680 | #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4681 | |
| mbed_official | 340:28d1f895c6fe | 4682 | /****************** Bit definition for FMC_SDTR1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4683 | #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */ |
| mbed_official | 340:28d1f895c6fe | 4684 | #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4685 | #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4686 | #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4687 | #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4688 | |
| mbed_official | 340:28d1f895c6fe | 4689 | #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */ |
| mbed_official | 340:28d1f895c6fe | 4690 | #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4691 | #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4692 | #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4693 | #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4694 | |
| mbed_official | 340:28d1f895c6fe | 4695 | #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */ |
| mbed_official | 340:28d1f895c6fe | 4696 | #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4697 | #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4698 | #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4699 | #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4700 | |
| mbed_official | 340:28d1f895c6fe | 4701 | #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */ |
| mbed_official | 340:28d1f895c6fe | 4702 | #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4703 | #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4704 | #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4705 | |
| mbed_official | 340:28d1f895c6fe | 4706 | #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */ |
| mbed_official | 340:28d1f895c6fe | 4707 | #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4708 | #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4709 | #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4710 | |
| mbed_official | 340:28d1f895c6fe | 4711 | #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */ |
| mbed_official | 340:28d1f895c6fe | 4712 | #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4713 | #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4714 | #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4715 | |
| mbed_official | 340:28d1f895c6fe | 4716 | #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */ |
| mbed_official | 340:28d1f895c6fe | 4717 | #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4718 | #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4719 | #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4720 | |
| mbed_official | 340:28d1f895c6fe | 4721 | /****************** Bit definition for FMC_SDTR2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4722 | #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */ |
| mbed_official | 340:28d1f895c6fe | 4723 | #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4724 | #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4725 | #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4726 | #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4727 | |
| mbed_official | 340:28d1f895c6fe | 4728 | #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */ |
| mbed_official | 340:28d1f895c6fe | 4729 | #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4730 | #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4731 | #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4732 | #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4733 | |
| mbed_official | 340:28d1f895c6fe | 4734 | #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */ |
| mbed_official | 340:28d1f895c6fe | 4735 | #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4736 | #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4737 | #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4738 | #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4739 | |
| mbed_official | 340:28d1f895c6fe | 4740 | #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */ |
| mbed_official | 340:28d1f895c6fe | 4741 | #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4742 | #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4743 | #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4744 | |
| mbed_official | 340:28d1f895c6fe | 4745 | #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */ |
| mbed_official | 340:28d1f895c6fe | 4746 | #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4747 | #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4748 | #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4749 | |
| mbed_official | 340:28d1f895c6fe | 4750 | #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */ |
| mbed_official | 340:28d1f895c6fe | 4751 | #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4752 | #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4753 | #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4754 | |
| mbed_official | 340:28d1f895c6fe | 4755 | #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */ |
| mbed_official | 340:28d1f895c6fe | 4756 | #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4757 | #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4758 | #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4759 | |
| mbed_official | 340:28d1f895c6fe | 4760 | /****************** Bit definition for FMC_SDCMR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4761 | #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */ |
| mbed_official | 340:28d1f895c6fe | 4762 | #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4763 | #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 532:fe11edbda85c | 4764 | #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4765 | |
| mbed_official | 340:28d1f895c6fe | 4766 | #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */ |
| mbed_official | 340:28d1f895c6fe | 4767 | |
| mbed_official | 340:28d1f895c6fe | 4768 | #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */ |
| mbed_official | 340:28d1f895c6fe | 4769 | |
| mbed_official | 340:28d1f895c6fe | 4770 | #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */ |
| mbed_official | 340:28d1f895c6fe | 4771 | #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4772 | #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4773 | #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 4774 | #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 4775 | |
| mbed_official | 340:28d1f895c6fe | 4776 | #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */ |
| mbed_official | 340:28d1f895c6fe | 4777 | |
| mbed_official | 340:28d1f895c6fe | 4778 | /****************** Bit definition for FMC_SDRTR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4779 | #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */ |
| mbed_official | 340:28d1f895c6fe | 4780 | |
| mbed_official | 340:28d1f895c6fe | 4781 | #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */ |
| mbed_official | 340:28d1f895c6fe | 4782 | |
| mbed_official | 340:28d1f895c6fe | 4783 | #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */ |
| mbed_official | 340:28d1f895c6fe | 4784 | |
| mbed_official | 340:28d1f895c6fe | 4785 | /****************** Bit definition for FMC_SDSR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 4786 | #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */ |
| mbed_official | 340:28d1f895c6fe | 4787 | |
| mbed_official | 340:28d1f895c6fe | 4788 | #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */ |
| mbed_official | 340:28d1f895c6fe | 4789 | #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4790 | #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4791 | |
| mbed_official | 340:28d1f895c6fe | 4792 | #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */ |
| mbed_official | 340:28d1f895c6fe | 4793 | #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 4794 | #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 4795 | #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */ |
| mbed_official | 340:28d1f895c6fe | 4796 | |
| mbed_official | 340:28d1f895c6fe | 4797 | |
| mbed_official | 340:28d1f895c6fe | 4798 | |
| mbed_official | 340:28d1f895c6fe | 4799 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 4800 | /* */ |
| mbed_official | 340:28d1f895c6fe | 4801 | /* General Purpose I/O */ |
| mbed_official | 340:28d1f895c6fe | 4802 | /* */ |
| mbed_official | 340:28d1f895c6fe | 4803 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 4804 | /****************** Bits definition for GPIO_MODER register *****************/ |
| mbed_official | 340:28d1f895c6fe | 4805 | #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| mbed_official | 340:28d1f895c6fe | 4806 | #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 4807 | #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 4808 | |
| mbed_official | 340:28d1f895c6fe | 4809 | #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| mbed_official | 340:28d1f895c6fe | 4810 | #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 4811 | #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 4812 | |
| mbed_official | 340:28d1f895c6fe | 4813 | #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| mbed_official | 340:28d1f895c6fe | 4814 | #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 4815 | #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 4816 | |
| mbed_official | 340:28d1f895c6fe | 4817 | #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| mbed_official | 340:28d1f895c6fe | 4818 | #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 4819 | #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 4820 | |
| mbed_official | 340:28d1f895c6fe | 4821 | #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| mbed_official | 340:28d1f895c6fe | 4822 | #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 4823 | #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 4824 | |
| mbed_official | 340:28d1f895c6fe | 4825 | #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| mbed_official | 340:28d1f895c6fe | 4826 | #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 4827 | #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 4828 | |
| mbed_official | 340:28d1f895c6fe | 4829 | #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| mbed_official | 340:28d1f895c6fe | 4830 | #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 4831 | #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 4832 | |
| mbed_official | 340:28d1f895c6fe | 4833 | #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| mbed_official | 340:28d1f895c6fe | 4834 | #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 4835 | #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 4836 | |
| mbed_official | 340:28d1f895c6fe | 4837 | #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| mbed_official | 340:28d1f895c6fe | 4838 | #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 4839 | #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 4840 | |
| mbed_official | 340:28d1f895c6fe | 4841 | #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| mbed_official | 340:28d1f895c6fe | 4842 | #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 4843 | #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 4844 | |
| mbed_official | 340:28d1f895c6fe | 4845 | #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| mbed_official | 340:28d1f895c6fe | 4846 | #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 4847 | #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 4848 | |
| mbed_official | 340:28d1f895c6fe | 4849 | #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| mbed_official | 340:28d1f895c6fe | 4850 | #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 4851 | #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 4852 | |
| mbed_official | 340:28d1f895c6fe | 4853 | #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| mbed_official | 340:28d1f895c6fe | 4854 | #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 4855 | #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 4856 | |
| mbed_official | 340:28d1f895c6fe | 4857 | #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| mbed_official | 340:28d1f895c6fe | 4858 | #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 4859 | #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 4860 | |
| mbed_official | 340:28d1f895c6fe | 4861 | #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| mbed_official | 340:28d1f895c6fe | 4862 | #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 4863 | #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 4864 | |
| mbed_official | 340:28d1f895c6fe | 4865 | #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| mbed_official | 340:28d1f895c6fe | 4866 | #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 4867 | #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 4868 | |
| mbed_official | 340:28d1f895c6fe | 4869 | /****************** Bits definition for GPIO_OTYPER register ****************/ |
| mbed_official | 340:28d1f895c6fe | 4870 | #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 4871 | #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 4872 | #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 4873 | #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 4874 | #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 4875 | #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 4876 | #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 4877 | #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 4878 | #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 4879 | #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 4880 | #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 4881 | #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 4882 | #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 4883 | #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 4884 | #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 4885 | #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 4886 | |
| mbed_official | 340:28d1f895c6fe | 4887 | /****************** Bits definition for GPIO_OSPEEDR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 4888 | #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| mbed_official | 340:28d1f895c6fe | 4889 | #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 4890 | #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 4891 | |
| mbed_official | 340:28d1f895c6fe | 4892 | #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| mbed_official | 340:28d1f895c6fe | 4893 | #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 4894 | #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 4895 | |
| mbed_official | 340:28d1f895c6fe | 4896 | #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| mbed_official | 340:28d1f895c6fe | 4897 | #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 4898 | #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 4899 | |
| mbed_official | 340:28d1f895c6fe | 4900 | #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| mbed_official | 340:28d1f895c6fe | 4901 | #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 4902 | #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 4903 | |
| mbed_official | 340:28d1f895c6fe | 4904 | #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| mbed_official | 340:28d1f895c6fe | 4905 | #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 4906 | #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 4907 | |
| mbed_official | 340:28d1f895c6fe | 4908 | #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| mbed_official | 340:28d1f895c6fe | 4909 | #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 4910 | #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 4911 | |
| mbed_official | 340:28d1f895c6fe | 4912 | #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| mbed_official | 340:28d1f895c6fe | 4913 | #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 4914 | #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 4915 | |
| mbed_official | 340:28d1f895c6fe | 4916 | #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| mbed_official | 340:28d1f895c6fe | 4917 | #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 4918 | #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 4919 | |
| mbed_official | 340:28d1f895c6fe | 4920 | #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| mbed_official | 340:28d1f895c6fe | 4921 | #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 4922 | #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 4923 | |
| mbed_official | 340:28d1f895c6fe | 4924 | #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| mbed_official | 340:28d1f895c6fe | 4925 | #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 4926 | #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 4927 | |
| mbed_official | 340:28d1f895c6fe | 4928 | #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| mbed_official | 340:28d1f895c6fe | 4929 | #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 4930 | #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 4931 | |
| mbed_official | 340:28d1f895c6fe | 4932 | #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| mbed_official | 340:28d1f895c6fe | 4933 | #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 4934 | #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 4935 | |
| mbed_official | 340:28d1f895c6fe | 4936 | #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| mbed_official | 340:28d1f895c6fe | 4937 | #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 4938 | #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 4939 | |
| mbed_official | 340:28d1f895c6fe | 4940 | #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| mbed_official | 340:28d1f895c6fe | 4941 | #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 4942 | #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 4943 | |
| mbed_official | 340:28d1f895c6fe | 4944 | #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| mbed_official | 340:28d1f895c6fe | 4945 | #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 4946 | #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 4947 | |
| mbed_official | 340:28d1f895c6fe | 4948 | #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| mbed_official | 340:28d1f895c6fe | 4949 | #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 4950 | #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 4951 | |
| mbed_official | 340:28d1f895c6fe | 4952 | /****************** Bits definition for GPIO_PUPDR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 4953 | #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| mbed_official | 340:28d1f895c6fe | 4954 | #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 4955 | #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 4956 | |
| mbed_official | 340:28d1f895c6fe | 4957 | #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| mbed_official | 340:28d1f895c6fe | 4958 | #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 4959 | #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 4960 | |
| mbed_official | 340:28d1f895c6fe | 4961 | #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| mbed_official | 340:28d1f895c6fe | 4962 | #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 4963 | #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 4964 | |
| mbed_official | 340:28d1f895c6fe | 4965 | #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| mbed_official | 340:28d1f895c6fe | 4966 | #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 4967 | #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 4968 | |
| mbed_official | 340:28d1f895c6fe | 4969 | #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| mbed_official | 340:28d1f895c6fe | 4970 | #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 4971 | #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 4972 | |
| mbed_official | 340:28d1f895c6fe | 4973 | #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| mbed_official | 340:28d1f895c6fe | 4974 | #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 4975 | #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 4976 | |
| mbed_official | 340:28d1f895c6fe | 4977 | #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| mbed_official | 340:28d1f895c6fe | 4978 | #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 4979 | #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 4980 | |
| mbed_official | 340:28d1f895c6fe | 4981 | #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| mbed_official | 340:28d1f895c6fe | 4982 | #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 4983 | #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 4984 | |
| mbed_official | 340:28d1f895c6fe | 4985 | #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| mbed_official | 340:28d1f895c6fe | 4986 | #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 4987 | #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 4988 | |
| mbed_official | 340:28d1f895c6fe | 4989 | #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| mbed_official | 340:28d1f895c6fe | 4990 | #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 4991 | #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 4992 | |
| mbed_official | 340:28d1f895c6fe | 4993 | #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| mbed_official | 340:28d1f895c6fe | 4994 | #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 4995 | #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 4996 | |
| mbed_official | 340:28d1f895c6fe | 4997 | #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| mbed_official | 340:28d1f895c6fe | 4998 | #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 4999 | #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5000 | |
| mbed_official | 340:28d1f895c6fe | 5001 | #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| mbed_official | 340:28d1f895c6fe | 5002 | #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5003 | #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5004 | |
| mbed_official | 340:28d1f895c6fe | 5005 | #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| mbed_official | 340:28d1f895c6fe | 5006 | #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5007 | #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5008 | |
| mbed_official | 340:28d1f895c6fe | 5009 | #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| mbed_official | 340:28d1f895c6fe | 5010 | #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5011 | #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5012 | |
| mbed_official | 340:28d1f895c6fe | 5013 | #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| mbed_official | 340:28d1f895c6fe | 5014 | #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5015 | #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 5016 | |
| mbed_official | 340:28d1f895c6fe | 5017 | /****************** Bits definition for GPIO_IDR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5018 | #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5019 | #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5020 | #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5021 | #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5022 | #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5023 | #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5024 | #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5025 | #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5026 | #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5027 | #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5028 | #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5029 | #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5030 | #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5031 | #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5032 | #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5033 | #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5034 | /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ |
| mbed_official | 340:28d1f895c6fe | 5035 | #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
| mbed_official | 340:28d1f895c6fe | 5036 | #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
| mbed_official | 340:28d1f895c6fe | 5037 | #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
| mbed_official | 340:28d1f895c6fe | 5038 | #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
| mbed_official | 340:28d1f895c6fe | 5039 | #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
| mbed_official | 340:28d1f895c6fe | 5040 | #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
| mbed_official | 340:28d1f895c6fe | 5041 | #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
| mbed_official | 340:28d1f895c6fe | 5042 | #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
| mbed_official | 340:28d1f895c6fe | 5043 | #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
| mbed_official | 340:28d1f895c6fe | 5044 | #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
| mbed_official | 340:28d1f895c6fe | 5045 | #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
| mbed_official | 340:28d1f895c6fe | 5046 | #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
| mbed_official | 340:28d1f895c6fe | 5047 | #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
| mbed_official | 340:28d1f895c6fe | 5048 | #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
| mbed_official | 340:28d1f895c6fe | 5049 | #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
| mbed_official | 340:28d1f895c6fe | 5050 | #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
| mbed_official | 340:28d1f895c6fe | 5051 | |
| mbed_official | 340:28d1f895c6fe | 5052 | /****************** Bits definition for GPIO_ODR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5053 | #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5054 | #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5055 | #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5056 | #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5057 | #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5058 | #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5059 | #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5060 | #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5061 | #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5062 | #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5063 | #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5064 | #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5065 | #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5066 | #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5067 | #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5068 | #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5069 | /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ |
| mbed_official | 340:28d1f895c6fe | 5070 | #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
| mbed_official | 340:28d1f895c6fe | 5071 | #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
| mbed_official | 340:28d1f895c6fe | 5072 | #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
| mbed_official | 340:28d1f895c6fe | 5073 | #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
| mbed_official | 340:28d1f895c6fe | 5074 | #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
| mbed_official | 340:28d1f895c6fe | 5075 | #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
| mbed_official | 340:28d1f895c6fe | 5076 | #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
| mbed_official | 340:28d1f895c6fe | 5077 | #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
| mbed_official | 340:28d1f895c6fe | 5078 | #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
| mbed_official | 340:28d1f895c6fe | 5079 | #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
| mbed_official | 340:28d1f895c6fe | 5080 | #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
| mbed_official | 340:28d1f895c6fe | 5081 | #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
| mbed_official | 340:28d1f895c6fe | 5082 | #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
| mbed_official | 340:28d1f895c6fe | 5083 | #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
| mbed_official | 340:28d1f895c6fe | 5084 | #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
| mbed_official | 340:28d1f895c6fe | 5085 | #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
| mbed_official | 340:28d1f895c6fe | 5086 | |
| mbed_official | 340:28d1f895c6fe | 5087 | /****************** Bits definition for GPIO_BSRR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 5088 | #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5089 | #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5090 | #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5091 | #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5092 | #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5093 | #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5094 | #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5095 | #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5096 | #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5097 | #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5098 | #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5099 | #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5100 | #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5101 | #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5102 | #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5103 | #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5104 | #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5105 | #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5106 | #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5107 | #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 5108 | #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5109 | #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5110 | #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5111 | #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5112 | #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5113 | #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5114 | #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5115 | #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5116 | #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5117 | #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5118 | #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5119 | #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 5120 | |
| mbed_official | 340:28d1f895c6fe | 5121 | /****************** Bit definition for GPIO_LCKR register *********************/ |
| mbed_official | 340:28d1f895c6fe | 5122 | #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5123 | #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5124 | #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5125 | #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5126 | #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5127 | #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5128 | #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5129 | #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5130 | #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5131 | #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5132 | #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5133 | #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5134 | #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5135 | #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5136 | #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5137 | #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5138 | #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5139 | |
| mbed_official | 340:28d1f895c6fe | 5140 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5141 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5142 | /* Inter-integrated Circuit Interface */ |
| mbed_official | 340:28d1f895c6fe | 5143 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5144 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5145 | /******************* Bit definition for I2C_CR1 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5146 | #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */ |
| mbed_official | 340:28d1f895c6fe | 5147 | #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */ |
| mbed_official | 340:28d1f895c6fe | 5148 | #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */ |
| mbed_official | 340:28d1f895c6fe | 5149 | #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */ |
| mbed_official | 340:28d1f895c6fe | 5150 | #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */ |
| mbed_official | 340:28d1f895c6fe | 5151 | #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */ |
| mbed_official | 340:28d1f895c6fe | 5152 | #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */ |
| mbed_official | 340:28d1f895c6fe | 5153 | #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */ |
| mbed_official | 340:28d1f895c6fe | 5154 | #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */ |
| mbed_official | 340:28d1f895c6fe | 5155 | #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */ |
| mbed_official | 340:28d1f895c6fe | 5156 | #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */ |
| mbed_official | 340:28d1f895c6fe | 5157 | #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */ |
| mbed_official | 340:28d1f895c6fe | 5158 | #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */ |
| mbed_official | 340:28d1f895c6fe | 5159 | #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */ |
| mbed_official | 340:28d1f895c6fe | 5160 | |
| mbed_official | 340:28d1f895c6fe | 5161 | /******************* Bit definition for I2C_CR2 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5162 | #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ |
| mbed_official | 340:28d1f895c6fe | 5163 | #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5164 | #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5165 | #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5166 | #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 5167 | #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 5168 | #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 5169 | |
| mbed_official | 340:28d1f895c6fe | 5170 | #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 5171 | #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 5172 | #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 5173 | #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */ |
| mbed_official | 340:28d1f895c6fe | 5174 | #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */ |
| mbed_official | 340:28d1f895c6fe | 5175 | |
| mbed_official | 340:28d1f895c6fe | 5176 | /******************* Bit definition for I2C_OAR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5177 | #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */ |
| mbed_official | 340:28d1f895c6fe | 5178 | #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */ |
| mbed_official | 340:28d1f895c6fe | 5179 | |
| mbed_official | 340:28d1f895c6fe | 5180 | #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5181 | #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5182 | #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5183 | #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 5184 | #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 5185 | #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 5186 | #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 5187 | #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 5188 | #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 5189 | #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */ |
| mbed_official | 340:28d1f895c6fe | 5190 | |
| mbed_official | 340:28d1f895c6fe | 5191 | #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */ |
| mbed_official | 340:28d1f895c6fe | 5192 | |
| mbed_official | 340:28d1f895c6fe | 5193 | /******************* Bit definition for I2C_OAR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5194 | #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */ |
| mbed_official | 340:28d1f895c6fe | 5195 | #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */ |
| mbed_official | 340:28d1f895c6fe | 5196 | |
| mbed_official | 340:28d1f895c6fe | 5197 | /******************** Bit definition for I2C_DR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5198 | #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */ |
| mbed_official | 340:28d1f895c6fe | 5199 | |
| mbed_official | 340:28d1f895c6fe | 5200 | /******************* Bit definition for I2C_SR1 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5201 | #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */ |
| mbed_official | 340:28d1f895c6fe | 5202 | #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */ |
| mbed_official | 340:28d1f895c6fe | 5203 | #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */ |
| mbed_official | 340:28d1f895c6fe | 5204 | #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */ |
| mbed_official | 340:28d1f895c6fe | 5205 | #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */ |
| mbed_official | 340:28d1f895c6fe | 5206 | #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */ |
| mbed_official | 340:28d1f895c6fe | 5207 | #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */ |
| mbed_official | 340:28d1f895c6fe | 5208 | #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */ |
| mbed_official | 340:28d1f895c6fe | 5209 | #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */ |
| mbed_official | 340:28d1f895c6fe | 5210 | #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */ |
| mbed_official | 340:28d1f895c6fe | 5211 | #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */ |
| mbed_official | 340:28d1f895c6fe | 5212 | #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */ |
| mbed_official | 340:28d1f895c6fe | 5213 | #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */ |
| mbed_official | 340:28d1f895c6fe | 5214 | #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */ |
| mbed_official | 340:28d1f895c6fe | 5215 | |
| mbed_official | 340:28d1f895c6fe | 5216 | /******************* Bit definition for I2C_SR2 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5217 | #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */ |
| mbed_official | 340:28d1f895c6fe | 5218 | #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */ |
| mbed_official | 340:28d1f895c6fe | 5219 | #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */ |
| mbed_official | 340:28d1f895c6fe | 5220 | #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */ |
| mbed_official | 340:28d1f895c6fe | 5221 | #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */ |
| mbed_official | 340:28d1f895c6fe | 5222 | #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */ |
| mbed_official | 340:28d1f895c6fe | 5223 | #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */ |
| mbed_official | 340:28d1f895c6fe | 5224 | #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */ |
| mbed_official | 340:28d1f895c6fe | 5225 | |
| mbed_official | 340:28d1f895c6fe | 5226 | /******************* Bit definition for I2C_CCR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5227 | #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */ |
| mbed_official | 340:28d1f895c6fe | 5228 | #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */ |
| mbed_official | 340:28d1f895c6fe | 5229 | #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */ |
| mbed_official | 340:28d1f895c6fe | 5230 | |
| mbed_official | 340:28d1f895c6fe | 5231 | /****************** Bit definition for I2C_TRISE register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5232 | #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ |
| mbed_official | 340:28d1f895c6fe | 5233 | |
| mbed_official | 340:28d1f895c6fe | 5234 | /****************** Bit definition for I2C_FLTR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5235 | #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */ |
| mbed_official | 340:28d1f895c6fe | 5236 | #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */ |
| mbed_official | 340:28d1f895c6fe | 5237 | |
| mbed_official | 340:28d1f895c6fe | 5238 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5239 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5240 | /* Independent WATCHDOG */ |
| mbed_official | 340:28d1f895c6fe | 5241 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5242 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5243 | /******************* Bit definition for IWDG_KR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5244 | #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */ |
| mbed_official | 340:28d1f895c6fe | 5245 | |
| mbed_official | 340:28d1f895c6fe | 5246 | /******************* Bit definition for IWDG_PR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5247 | #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */ |
| mbed_official | 340:28d1f895c6fe | 5248 | #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5249 | #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5250 | #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5251 | |
| mbed_official | 340:28d1f895c6fe | 5252 | /******************* Bit definition for IWDG_RLR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5253 | #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */ |
| mbed_official | 340:28d1f895c6fe | 5254 | |
| mbed_official | 340:28d1f895c6fe | 5255 | /******************* Bit definition for IWDG_SR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5256 | #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */ |
| mbed_official | 340:28d1f895c6fe | 5257 | #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */ |
| mbed_official | 340:28d1f895c6fe | 5258 | |
| mbed_official | 340:28d1f895c6fe | 5259 | |
| mbed_official | 340:28d1f895c6fe | 5260 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5261 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5262 | /* LCD-TFT Display Controller (LTDC) */ |
| mbed_official | 340:28d1f895c6fe | 5263 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5264 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5265 | |
| mbed_official | 340:28d1f895c6fe | 5266 | /******************** Bit definition for LTDC_SSCR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5267 | |
| mbed_official | 340:28d1f895c6fe | 5268 | #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */ |
| mbed_official | 340:28d1f895c6fe | 5269 | #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */ |
| mbed_official | 340:28d1f895c6fe | 5270 | |
| mbed_official | 340:28d1f895c6fe | 5271 | /******************** Bit definition for LTDC_BPCR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5272 | |
| mbed_official | 340:28d1f895c6fe | 5273 | #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */ |
| mbed_official | 340:28d1f895c6fe | 5274 | #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */ |
| mbed_official | 340:28d1f895c6fe | 5275 | |
| mbed_official | 340:28d1f895c6fe | 5276 | /******************** Bit definition for LTDC_AWCR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5277 | |
| mbed_official | 340:28d1f895c6fe | 5278 | #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */ |
| mbed_official | 340:28d1f895c6fe | 5279 | #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */ |
| mbed_official | 340:28d1f895c6fe | 5280 | |
| mbed_official | 340:28d1f895c6fe | 5281 | /******************** Bit definition for LTDC_TWCR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5282 | |
| mbed_official | 340:28d1f895c6fe | 5283 | #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */ |
| mbed_official | 340:28d1f895c6fe | 5284 | #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */ |
| mbed_official | 340:28d1f895c6fe | 5285 | |
| mbed_official | 340:28d1f895c6fe | 5286 | /******************** Bit definition for LTDC_GCR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 5287 | |
| mbed_official | 340:28d1f895c6fe | 5288 | #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */ |
| mbed_official | 340:28d1f895c6fe | 5289 | #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */ |
| mbed_official | 340:28d1f895c6fe | 5290 | #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */ |
| mbed_official | 340:28d1f895c6fe | 5291 | #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */ |
| mbed_official | 340:28d1f895c6fe | 5292 | #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */ |
| mbed_official | 340:28d1f895c6fe | 5293 | #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */ |
| mbed_official | 340:28d1f895c6fe | 5294 | #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */ |
| mbed_official | 340:28d1f895c6fe | 5295 | #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */ |
| mbed_official | 340:28d1f895c6fe | 5296 | #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */ |
| mbed_official | 340:28d1f895c6fe | 5297 | |
| mbed_official | 340:28d1f895c6fe | 5298 | /******************** Bit definition for LTDC_SRCR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5299 | |
| mbed_official | 340:28d1f895c6fe | 5300 | #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */ |
| mbed_official | 340:28d1f895c6fe | 5301 | #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */ |
| mbed_official | 340:28d1f895c6fe | 5302 | |
| mbed_official | 340:28d1f895c6fe | 5303 | /******************** Bit definition for LTDC_BCCR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5304 | |
| mbed_official | 340:28d1f895c6fe | 5305 | #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */ |
| mbed_official | 340:28d1f895c6fe | 5306 | #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */ |
| mbed_official | 340:28d1f895c6fe | 5307 | #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */ |
| mbed_official | 340:28d1f895c6fe | 5308 | |
| mbed_official | 340:28d1f895c6fe | 5309 | /******************** Bit definition for LTDC_IER register ******************/ |
| mbed_official | 340:28d1f895c6fe | 5310 | |
| mbed_official | 340:28d1f895c6fe | 5311 | #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 5312 | #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 5313 | #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 5314 | #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 5315 | |
| mbed_official | 340:28d1f895c6fe | 5316 | /******************** Bit definition for LTDC_ISR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 5317 | |
| mbed_official | 340:28d1f895c6fe | 5318 | #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 5319 | #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 5320 | #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 5321 | #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 5322 | |
| mbed_official | 340:28d1f895c6fe | 5323 | /******************** Bit definition for LTDC_ICR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 5324 | |
| mbed_official | 340:28d1f895c6fe | 5325 | #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 5326 | #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 5327 | #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 5328 | #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 5329 | |
| mbed_official | 340:28d1f895c6fe | 5330 | /******************** Bit definition for LTDC_LIPCR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 5331 | |
| mbed_official | 340:28d1f895c6fe | 5332 | #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */ |
| mbed_official | 340:28d1f895c6fe | 5333 | |
| mbed_official | 340:28d1f895c6fe | 5334 | /******************** Bit definition for LTDC_CPSR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5335 | |
| mbed_official | 340:28d1f895c6fe | 5336 | #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */ |
| mbed_official | 340:28d1f895c6fe | 5337 | #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */ |
| mbed_official | 340:28d1f895c6fe | 5338 | |
| mbed_official | 340:28d1f895c6fe | 5339 | /******************** Bit definition for LTDC_CDSR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5340 | |
| mbed_official | 340:28d1f895c6fe | 5341 | #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */ |
| mbed_official | 340:28d1f895c6fe | 5342 | #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */ |
| mbed_official | 340:28d1f895c6fe | 5343 | #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */ |
| mbed_official | 340:28d1f895c6fe | 5344 | #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */ |
| mbed_official | 340:28d1f895c6fe | 5345 | |
| mbed_official | 340:28d1f895c6fe | 5346 | /******************** Bit definition for LTDC_LxCR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5347 | |
| mbed_official | 340:28d1f895c6fe | 5348 | #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */ |
| mbed_official | 340:28d1f895c6fe | 5349 | #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */ |
| mbed_official | 340:28d1f895c6fe | 5350 | #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */ |
| mbed_official | 340:28d1f895c6fe | 5351 | |
| mbed_official | 340:28d1f895c6fe | 5352 | /******************** Bit definition for LTDC_LxWHPCR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5353 | |
| mbed_official | 340:28d1f895c6fe | 5354 | #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */ |
| mbed_official | 340:28d1f895c6fe | 5355 | #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */ |
| mbed_official | 340:28d1f895c6fe | 5356 | |
| mbed_official | 340:28d1f895c6fe | 5357 | /******************** Bit definition for LTDC_LxWVPCR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5358 | |
| mbed_official | 340:28d1f895c6fe | 5359 | #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */ |
| mbed_official | 340:28d1f895c6fe | 5360 | #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */ |
| mbed_official | 340:28d1f895c6fe | 5361 | |
| mbed_official | 340:28d1f895c6fe | 5362 | /******************** Bit definition for LTDC_LxCKCR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5363 | |
| mbed_official | 340:28d1f895c6fe | 5364 | #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */ |
| mbed_official | 340:28d1f895c6fe | 5365 | #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */ |
| mbed_official | 340:28d1f895c6fe | 5366 | #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */ |
| mbed_official | 340:28d1f895c6fe | 5367 | |
| mbed_official | 340:28d1f895c6fe | 5368 | /******************** Bit definition for LTDC_LxPFCR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5369 | |
| mbed_official | 340:28d1f895c6fe | 5370 | #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */ |
| mbed_official | 340:28d1f895c6fe | 5371 | |
| mbed_official | 340:28d1f895c6fe | 5372 | /******************** Bit definition for LTDC_LxCACR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5373 | |
| mbed_official | 340:28d1f895c6fe | 5374 | #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */ |
| mbed_official | 340:28d1f895c6fe | 5375 | |
| mbed_official | 340:28d1f895c6fe | 5376 | /******************** Bit definition for LTDC_LxDCCR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5377 | |
| mbed_official | 340:28d1f895c6fe | 5378 | #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */ |
| mbed_official | 340:28d1f895c6fe | 5379 | #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */ |
| mbed_official | 340:28d1f895c6fe | 5380 | #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */ |
| mbed_official | 340:28d1f895c6fe | 5381 | #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */ |
| mbed_official | 340:28d1f895c6fe | 5382 | |
| mbed_official | 340:28d1f895c6fe | 5383 | /******************** Bit definition for LTDC_LxBFCR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5384 | |
| mbed_official | 340:28d1f895c6fe | 5385 | #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */ |
| mbed_official | 340:28d1f895c6fe | 5386 | #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */ |
| mbed_official | 340:28d1f895c6fe | 5387 | |
| mbed_official | 340:28d1f895c6fe | 5388 | /******************** Bit definition for LTDC_LxCFBAR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5389 | |
| mbed_official | 340:28d1f895c6fe | 5390 | #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */ |
| mbed_official | 340:28d1f895c6fe | 5391 | |
| mbed_official | 340:28d1f895c6fe | 5392 | /******************** Bit definition for LTDC_LxCFBLR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5393 | |
| mbed_official | 340:28d1f895c6fe | 5394 | #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */ |
| mbed_official | 340:28d1f895c6fe | 5395 | #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */ |
| mbed_official | 340:28d1f895c6fe | 5396 | |
| mbed_official | 340:28d1f895c6fe | 5397 | /******************** Bit definition for LTDC_LxCFBLNR register *************/ |
| mbed_official | 340:28d1f895c6fe | 5398 | |
| mbed_official | 340:28d1f895c6fe | 5399 | #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */ |
| mbed_official | 340:28d1f895c6fe | 5400 | |
| mbed_official | 340:28d1f895c6fe | 5401 | /******************** Bit definition for LTDC_LxCLUTWR register *************/ |
| mbed_official | 340:28d1f895c6fe | 5402 | |
| mbed_official | 340:28d1f895c6fe | 5403 | #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */ |
| mbed_official | 340:28d1f895c6fe | 5404 | #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */ |
| mbed_official | 340:28d1f895c6fe | 5405 | #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */ |
| mbed_official | 340:28d1f895c6fe | 5406 | #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */ |
| mbed_official | 340:28d1f895c6fe | 5407 | |
| mbed_official | 340:28d1f895c6fe | 5408 | |
| mbed_official | 340:28d1f895c6fe | 5409 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5410 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5411 | /* Power Control */ |
| mbed_official | 340:28d1f895c6fe | 5412 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5413 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5414 | /******************** Bit definition for PWR_CR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5415 | #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */ |
| mbed_official | 340:28d1f895c6fe | 5416 | #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */ |
| mbed_official | 340:28d1f895c6fe | 5417 | #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */ |
| mbed_official | 340:28d1f895c6fe | 5418 | #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */ |
| mbed_official | 340:28d1f895c6fe | 5419 | #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */ |
| mbed_official | 340:28d1f895c6fe | 5420 | |
| mbed_official | 340:28d1f895c6fe | 5421 | #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */ |
| mbed_official | 340:28d1f895c6fe | 5422 | #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5423 | #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5424 | #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5425 | |
| mbed_official | 340:28d1f895c6fe | 5426 | /*!< PVD level configuration */ |
| mbed_official | 340:28d1f895c6fe | 5427 | #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */ |
| mbed_official | 340:28d1f895c6fe | 5428 | #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */ |
| mbed_official | 340:28d1f895c6fe | 5429 | #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */ |
| mbed_official | 340:28d1f895c6fe | 5430 | #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */ |
| mbed_official | 340:28d1f895c6fe | 5431 | #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */ |
| mbed_official | 340:28d1f895c6fe | 5432 | #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */ |
| mbed_official | 340:28d1f895c6fe | 5433 | #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */ |
| mbed_official | 340:28d1f895c6fe | 5434 | #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */ |
| mbed_official | 340:28d1f895c6fe | 5435 | #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ |
| mbed_official | 340:28d1f895c6fe | 5436 | #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */ |
| mbed_official | 340:28d1f895c6fe | 5437 | #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */ |
| mbed_official | 340:28d1f895c6fe | 5438 | #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */ |
| mbed_official | 340:28d1f895c6fe | 5439 | #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */ |
| mbed_official | 340:28d1f895c6fe | 5440 | #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ |
| mbed_official | 340:28d1f895c6fe | 5441 | #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5442 | #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5443 | #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */ |
| mbed_official | 340:28d1f895c6fe | 5444 | #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */ |
| mbed_official | 340:28d1f895c6fe | 5445 | #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */ |
| mbed_official | 340:28d1f895c6fe | 5446 | #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5447 | #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5448 | |
| mbed_official | 340:28d1f895c6fe | 5449 | /* Legacy define */ |
| mbed_official | 340:28d1f895c6fe | 5450 | #define PWR_CR_PMODE PWR_CR_VOS |
| mbed_official | 340:28d1f895c6fe | 5451 | #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */ |
| mbed_official | 340:28d1f895c6fe | 5452 | #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */ |
| mbed_official | 340:28d1f895c6fe | 5453 | |
| mbed_official | 340:28d1f895c6fe | 5454 | /******************* Bit definition for PWR_CSR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5455 | #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ |
| mbed_official | 340:28d1f895c6fe | 5456 | #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ |
| mbed_official | 340:28d1f895c6fe | 5457 | #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */ |
| mbed_official | 340:28d1f895c6fe | 5458 | #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */ |
| mbed_official | 340:28d1f895c6fe | 5459 | #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */ |
| mbed_official | 340:28d1f895c6fe | 5460 | #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */ |
| mbed_official | 340:28d1f895c6fe | 5461 | #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */ |
| mbed_official | 340:28d1f895c6fe | 5462 | #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */ |
| mbed_official | 340:28d1f895c6fe | 5463 | #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */ |
| mbed_official | 340:28d1f895c6fe | 5464 | #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */ |
| mbed_official | 340:28d1f895c6fe | 5465 | |
| mbed_official | 340:28d1f895c6fe | 5466 | /* Legacy define */ |
| mbed_official | 340:28d1f895c6fe | 5467 | #define PWR_CSR_REGRDY PWR_CSR_VOSRDY |
| mbed_official | 340:28d1f895c6fe | 5468 | |
| mbed_official | 340:28d1f895c6fe | 5469 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5470 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5471 | /* Reset and Clock Control */ |
| mbed_official | 340:28d1f895c6fe | 5472 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5473 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5474 | /******************** Bit definition for RCC_CR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 5475 | #define RCC_CR_HSION ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5476 | #define RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5477 | |
| mbed_official | 340:28d1f895c6fe | 5478 | #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| mbed_official | 340:28d1f895c6fe | 5479 | #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5480 | #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5481 | #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5482 | #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 5483 | #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 5484 | |
| mbed_official | 340:28d1f895c6fe | 5485 | #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| mbed_official | 340:28d1f895c6fe | 5486 | #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5487 | #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5488 | #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5489 | #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 5490 | #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 5491 | #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 5492 | #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 5493 | #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 5494 | |
| mbed_official | 340:28d1f895c6fe | 5495 | #define RCC_CR_HSEON ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5496 | #define RCC_CR_HSERDY ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5497 | #define RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5498 | #define RCC_CR_CSSON ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 5499 | #define RCC_CR_PLLON ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5500 | #define RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5501 | #define RCC_CR_PLLI2SON ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5502 | #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5503 | #define RCC_CR_PLLSAION ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5504 | #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5505 | |
| mbed_official | 340:28d1f895c6fe | 5506 | /******************** Bit definition for RCC_PLLCFGR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5507 | #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) |
| mbed_official | 340:28d1f895c6fe | 5508 | #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5509 | #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5510 | #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5511 | #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5512 | #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5513 | #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5514 | |
| mbed_official | 340:28d1f895c6fe | 5515 | #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) |
| mbed_official | 340:28d1f895c6fe | 5516 | #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5517 | #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5518 | #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5519 | #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5520 | #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5521 | #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5522 | #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5523 | #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5524 | #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5525 | |
| mbed_official | 340:28d1f895c6fe | 5526 | #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) |
| mbed_official | 340:28d1f895c6fe | 5527 | #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5528 | #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5529 | |
| mbed_official | 340:28d1f895c6fe | 5530 | #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5531 | #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5532 | #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 5533 | |
| mbed_official | 340:28d1f895c6fe | 5534 | #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) |
| mbed_official | 340:28d1f895c6fe | 5535 | #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5536 | #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5537 | #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5538 | #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5539 | |
| mbed_official | 340:28d1f895c6fe | 5540 | /******************** Bit definition for RCC_CFGR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 5541 | /*!< SW configuration */ |
| mbed_official | 340:28d1f895c6fe | 5542 | #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
| mbed_official | 340:28d1f895c6fe | 5543 | #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5544 | #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5545 | |
| mbed_official | 340:28d1f895c6fe | 5546 | #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
| mbed_official | 340:28d1f895c6fe | 5547 | #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
| mbed_official | 340:28d1f895c6fe | 5548 | #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
| mbed_official | 340:28d1f895c6fe | 5549 | |
| mbed_official | 340:28d1f895c6fe | 5550 | /*!< SWS configuration */ |
| mbed_official | 340:28d1f895c6fe | 5551 | #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
| mbed_official | 340:28d1f895c6fe | 5552 | #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5553 | #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5554 | |
| mbed_official | 340:28d1f895c6fe | 5555 | #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
| mbed_official | 340:28d1f895c6fe | 5556 | #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
| mbed_official | 340:28d1f895c6fe | 5557 | #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
| mbed_official | 340:28d1f895c6fe | 5558 | |
| mbed_official | 340:28d1f895c6fe | 5559 | /*!< HPRE configuration */ |
| mbed_official | 340:28d1f895c6fe | 5560 | #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 5561 | #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5562 | #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5563 | #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5564 | #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 5565 | |
| mbed_official | 340:28d1f895c6fe | 5566 | #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
| mbed_official | 340:28d1f895c6fe | 5567 | #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
| mbed_official | 340:28d1f895c6fe | 5568 | #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
| mbed_official | 340:28d1f895c6fe | 5569 | #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
| mbed_official | 340:28d1f895c6fe | 5570 | #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
| mbed_official | 340:28d1f895c6fe | 5571 | #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
| mbed_official | 340:28d1f895c6fe | 5572 | #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
| mbed_official | 340:28d1f895c6fe | 5573 | #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
| mbed_official | 340:28d1f895c6fe | 5574 | #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
| mbed_official | 340:28d1f895c6fe | 5575 | |
| mbed_official | 340:28d1f895c6fe | 5576 | /*!< PPRE1 configuration */ |
| mbed_official | 340:28d1f895c6fe | 5577 | #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 5578 | #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5579 | #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5580 | #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5581 | |
| mbed_official | 340:28d1f895c6fe | 5582 | #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
| mbed_official | 340:28d1f895c6fe | 5583 | #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */ |
| mbed_official | 340:28d1f895c6fe | 5584 | #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */ |
| mbed_official | 340:28d1f895c6fe | 5585 | #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */ |
| mbed_official | 340:28d1f895c6fe | 5586 | #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */ |
| mbed_official | 340:28d1f895c6fe | 5587 | |
| mbed_official | 340:28d1f895c6fe | 5588 | /*!< PPRE2 configuration */ |
| mbed_official | 340:28d1f895c6fe | 5589 | #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 5590 | #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 5591 | #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 5592 | #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 5593 | |
| mbed_official | 340:28d1f895c6fe | 5594 | #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
| mbed_official | 340:28d1f895c6fe | 5595 | #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */ |
| mbed_official | 340:28d1f895c6fe | 5596 | #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */ |
| mbed_official | 340:28d1f895c6fe | 5597 | #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */ |
| mbed_official | 340:28d1f895c6fe | 5598 | #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */ |
| mbed_official | 340:28d1f895c6fe | 5599 | |
| mbed_official | 340:28d1f895c6fe | 5600 | /*!< RTCPRE configuration */ |
| mbed_official | 340:28d1f895c6fe | 5601 | #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) |
| mbed_official | 340:28d1f895c6fe | 5602 | #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5603 | #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5604 | #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5605 | #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 5606 | #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5607 | |
| mbed_official | 340:28d1f895c6fe | 5608 | /*!< MCO1 configuration */ |
| mbed_official | 340:28d1f895c6fe | 5609 | #define RCC_CFGR_MCO1 ((uint32_t)0x00600000) |
| mbed_official | 340:28d1f895c6fe | 5610 | #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5611 | #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5612 | |
| mbed_official | 340:28d1f895c6fe | 5613 | #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5614 | |
| mbed_official | 340:28d1f895c6fe | 5615 | #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) |
| mbed_official | 340:28d1f895c6fe | 5616 | #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5617 | #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5618 | #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5619 | |
| mbed_official | 340:28d1f895c6fe | 5620 | #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) |
| mbed_official | 340:28d1f895c6fe | 5621 | #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5622 | #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5623 | #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5624 | |
| mbed_official | 340:28d1f895c6fe | 5625 | #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000) |
| mbed_official | 340:28d1f895c6fe | 5626 | #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5627 | #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 5628 | |
| mbed_official | 340:28d1f895c6fe | 5629 | /******************** Bit definition for RCC_CIR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5630 | #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5631 | #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5632 | #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5633 | #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5634 | #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5635 | #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5636 | #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5637 | #define RCC_CIR_CSSF ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5638 | #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5639 | #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5640 | #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5641 | #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5642 | #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5643 | #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5644 | #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5645 | #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5646 | #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5647 | #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5648 | #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 5649 | #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5650 | #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5651 | #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5652 | #define RCC_CIR_CSSC ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5653 | |
| mbed_official | 340:28d1f895c6fe | 5654 | /******************** Bit definition for RCC_AHB1RSTR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5655 | #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5656 | #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5657 | #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5658 | #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5659 | #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5660 | #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5661 | #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5662 | #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5663 | #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5664 | #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5665 | #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5666 | #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5667 | #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5668 | #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5669 | #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5670 | #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) |
| mbed_official | 532:fe11edbda85c | 5671 | #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5672 | |
| mbed_official | 340:28d1f895c6fe | 5673 | /******************** Bit definition for RCC_AHB2RSTR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5674 | #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5675 | #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5676 | #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5677 | |
| mbed_official | 340:28d1f895c6fe | 5678 | /******************** Bit definition for RCC_AHB3RSTR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5679 | #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5680 | |
| mbed_official | 340:28d1f895c6fe | 5681 | /******************** Bit definition for RCC_APB1RSTR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5682 | #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5683 | #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5684 | #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5685 | #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5686 | #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5687 | #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5688 | #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5689 | #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5690 | #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5691 | #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5692 | #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5693 | #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5694 | #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5695 | #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5696 | #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 5697 | #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5698 | #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5699 | #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5700 | #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5701 | #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5702 | #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5703 | #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5704 | #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5705 | #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5706 | #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 5707 | |
| mbed_official | 340:28d1f895c6fe | 5708 | /******************** Bit definition for RCC_APB2RSTR register **************/ |
| mbed_official | 340:28d1f895c6fe | 5709 | #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5710 | #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5711 | #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5712 | #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5713 | #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5714 | #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5715 | #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5716 | #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5717 | #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5718 | #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5719 | #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5720 | #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5721 | #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5722 | #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5723 | #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5724 | #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5725 | |
| mbed_official | 340:28d1f895c6fe | 5726 | /* Old SPI1RST bit definition, maintained for legacy purpose */ |
| mbed_official | 340:28d1f895c6fe | 5727 | #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
| mbed_official | 340:28d1f895c6fe | 5728 | |
| mbed_official | 340:28d1f895c6fe | 5729 | /******************** Bit definition for RCC_AHB1ENR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5730 | #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5731 | #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5732 | #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5733 | #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5734 | #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5735 | #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5736 | #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5737 | #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5738 | #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5739 | #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5740 | #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5741 | |
| mbed_official | 340:28d1f895c6fe | 5742 | #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5743 | #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5744 | #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5745 | #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5746 | #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5747 | #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5748 | |
| mbed_official | 340:28d1f895c6fe | 5749 | #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5750 | #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5751 | #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5752 | #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5753 | #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5754 | #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5755 | |
| mbed_official | 340:28d1f895c6fe | 5756 | /******************** Bit definition for RCC_AHB2ENR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5757 | #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5758 | #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5759 | #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5760 | |
| mbed_official | 340:28d1f895c6fe | 5761 | /******************** Bit definition for RCC_AHB3ENR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5762 | #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5763 | |
| mbed_official | 340:28d1f895c6fe | 5764 | /******************** Bit definition for RCC_APB1ENR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5765 | #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5766 | #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5767 | #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5768 | #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5769 | #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5770 | #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5771 | #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5772 | #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5773 | #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5774 | #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5775 | #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5776 | #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5777 | #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5778 | #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5779 | #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 5780 | #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5781 | #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5782 | #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5783 | #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5784 | #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5785 | #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5786 | #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5787 | #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5788 | #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5789 | #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 5790 | |
| mbed_official | 340:28d1f895c6fe | 5791 | /******************** Bit definition for RCC_APB2ENR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5792 | #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5793 | #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5794 | #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5795 | #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5796 | #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5797 | #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5798 | #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5799 | #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5800 | #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5801 | #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5802 | #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5803 | #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5804 | #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5805 | #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5806 | #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5807 | #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5808 | #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5809 | #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5810 | |
| mbed_official | 340:28d1f895c6fe | 5811 | /******************** Bit definition for RCC_AHB1LPENR register *************/ |
| mbed_official | 340:28d1f895c6fe | 5812 | #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5813 | #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5814 | #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5815 | #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5816 | #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5817 | #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5818 | #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5819 | #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5820 | #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5821 | #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5822 | #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5823 | |
| mbed_official | 340:28d1f895c6fe | 5824 | #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5825 | #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5826 | #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5827 | #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5828 | #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5829 | #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 5830 | #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5831 | #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5832 | #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5833 | |
| mbed_official | 340:28d1f895c6fe | 5834 | #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5835 | #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5836 | #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5837 | #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5838 | #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5839 | #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5840 | |
| mbed_official | 340:28d1f895c6fe | 5841 | /******************** Bit definition for RCC_AHB2LPENR register *************/ |
| mbed_official | 340:28d1f895c6fe | 5842 | #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5843 | #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5844 | #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5845 | |
| mbed_official | 340:28d1f895c6fe | 5846 | /******************** Bit definition for RCC_AHB3LPENR register *************/ |
| mbed_official | 340:28d1f895c6fe | 5847 | #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5848 | |
| mbed_official | 340:28d1f895c6fe | 5849 | /******************** Bit definition for RCC_APB1LPENR register *************/ |
| mbed_official | 340:28d1f895c6fe | 5850 | #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5851 | #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5852 | #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5853 | #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5854 | #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5855 | #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5856 | #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5857 | #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5858 | #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5859 | #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5860 | #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5861 | #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5862 | #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5863 | #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5864 | #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 5865 | #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5866 | #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5867 | #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5868 | #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5869 | #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5870 | #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5871 | #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5872 | #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5873 | #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5874 | #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 5875 | |
| mbed_official | 340:28d1f895c6fe | 5876 | /******************** Bit definition for RCC_APB2LPENR register *************/ |
| mbed_official | 340:28d1f895c6fe | 5877 | #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5878 | #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5879 | #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 5880 | #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 5881 | #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5882 | #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5883 | #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5884 | #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5885 | #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5886 | #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5887 | #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5888 | #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5889 | #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 5890 | #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 5891 | #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 5892 | #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5893 | #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 5894 | #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5895 | |
| mbed_official | 340:28d1f895c6fe | 5896 | /******************** Bit definition for RCC_BDCR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 5897 | #define RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5898 | #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5899 | #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5900 | |
| mbed_official | 340:28d1f895c6fe | 5901 | #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| mbed_official | 340:28d1f895c6fe | 5902 | #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5903 | #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5904 | |
| mbed_official | 340:28d1f895c6fe | 5905 | #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 5906 | #define RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 5907 | |
| mbed_official | 340:28d1f895c6fe | 5908 | /******************** Bit definition for RCC_CSR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5909 | #define RCC_CSR_LSION ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5910 | #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5911 | #define RCC_CSR_RMVF ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5912 | #define RCC_CSR_BORRSTF ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5913 | #define RCC_CSR_PADRSTF ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5914 | #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5915 | #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5916 | #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5917 | #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5918 | #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 5919 | |
| mbed_official | 340:28d1f895c6fe | 5920 | /******************** Bit definition for RCC_SSCGR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 5921 | #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) |
| mbed_official | 340:28d1f895c6fe | 5922 | #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) |
| mbed_official | 340:28d1f895c6fe | 5923 | #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5924 | #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 5925 | |
| mbed_official | 340:28d1f895c6fe | 5926 | /******************** Bit definition for RCC_PLLI2SCFGR register ************/ |
| mbed_official | 340:28d1f895c6fe | 5927 | #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) |
| mbed_official | 340:28d1f895c6fe | 5928 | #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5929 | #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5930 | #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5931 | #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5932 | #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5933 | #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5934 | #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5935 | #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5936 | #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5937 | |
| mbed_official | 340:28d1f895c6fe | 5938 | #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000) |
| mbed_official | 340:28d1f895c6fe | 5939 | #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5940 | #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5941 | #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5942 | #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5943 | |
| mbed_official | 340:28d1f895c6fe | 5944 | #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) |
| mbed_official | 340:28d1f895c6fe | 5945 | #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5946 | #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5947 | #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5948 | |
| mbed_official | 340:28d1f895c6fe | 5949 | |
| mbed_official | 340:28d1f895c6fe | 5950 | /******************** Bit definition for RCC_PLLSAICFGR register ************/ |
| mbed_official | 340:28d1f895c6fe | 5951 | #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0) |
| mbed_official | 340:28d1f895c6fe | 5952 | #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 5953 | #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 5954 | #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 5955 | #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 5956 | #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 5957 | #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 5958 | #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 5959 | #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 5960 | #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 5961 | |
| mbed_official | 340:28d1f895c6fe | 5962 | #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000) |
| mbed_official | 340:28d1f895c6fe | 5963 | #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5964 | #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 5965 | #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 5966 | #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 5967 | |
| mbed_official | 340:28d1f895c6fe | 5968 | #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000) |
| mbed_official | 340:28d1f895c6fe | 5969 | #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 5970 | #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 5971 | #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 5972 | |
| mbed_official | 340:28d1f895c6fe | 5973 | /******************** Bit definition for RCC_DCKCFGR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 5974 | #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F) |
| mbed_official | 340:28d1f895c6fe | 5975 | #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00) |
| mbed_official | 340:28d1f895c6fe | 5976 | #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000) |
| mbed_official | 340:28d1f895c6fe | 5977 | #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000) |
| mbed_official | 532:fe11edbda85c | 5978 | #define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000) |
| mbed_official | 532:fe11edbda85c | 5979 | #define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 5980 | #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000) |
| mbed_official | 532:fe11edbda85c | 5981 | #define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000) |
| mbed_official | 532:fe11edbda85c | 5982 | #define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 5983 | #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 5984 | |
| mbed_official | 340:28d1f895c6fe | 5985 | |
| mbed_official | 340:28d1f895c6fe | 5986 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5987 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5988 | /* RNG */ |
| mbed_official | 340:28d1f895c6fe | 5989 | /* */ |
| mbed_official | 340:28d1f895c6fe | 5990 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 5991 | /******************** Bits definition for RNG_CR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5992 | #define RNG_CR_RNGEN ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5993 | #define RNG_CR_IE ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 5994 | |
| mbed_official | 340:28d1f895c6fe | 5995 | /******************** Bits definition for RNG_SR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 5996 | #define RNG_SR_DRDY ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 5997 | #define RNG_SR_CECS ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 5998 | #define RNG_SR_SECS ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 5999 | #define RNG_SR_CEIS ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6000 | #define RNG_SR_SEIS ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 6001 | |
| mbed_official | 340:28d1f895c6fe | 6002 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6003 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6004 | /* Real-Time Clock (RTC) */ |
| mbed_official | 340:28d1f895c6fe | 6005 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6006 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6007 | /******************** Bits definition for RTC_TR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6008 | #define RTC_TR_PM ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 6009 | #define RTC_TR_HT ((uint32_t)0x00300000) |
| mbed_official | 340:28d1f895c6fe | 6010 | #define RTC_TR_HT_0 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 6011 | #define RTC_TR_HT_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 6012 | #define RTC_TR_HU ((uint32_t)0x000F0000) |
| mbed_official | 340:28d1f895c6fe | 6013 | #define RTC_TR_HU_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 6014 | #define RTC_TR_HU_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 6015 | #define RTC_TR_HU_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 6016 | #define RTC_TR_HU_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 6017 | #define RTC_TR_MNT ((uint32_t)0x00007000) |
| mbed_official | 340:28d1f895c6fe | 6018 | #define RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6019 | #define RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6020 | #define RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6021 | #define RTC_TR_MNU ((uint32_t)0x00000F00) |
| mbed_official | 340:28d1f895c6fe | 6022 | #define RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6023 | #define RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6024 | #define RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6025 | #define RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6026 | #define RTC_TR_ST ((uint32_t)0x00000070) |
| mbed_official | 340:28d1f895c6fe | 6027 | #define RTC_TR_ST_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6028 | #define RTC_TR_ST_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6029 | #define RTC_TR_ST_2 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 6030 | #define RTC_TR_SU ((uint32_t)0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 6031 | #define RTC_TR_SU_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6032 | #define RTC_TR_SU_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6033 | #define RTC_TR_SU_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6034 | #define RTC_TR_SU_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6035 | |
| mbed_official | 340:28d1f895c6fe | 6036 | /******************** Bits definition for RTC_DR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6037 | #define RTC_DR_YT ((uint32_t)0x00F00000) |
| mbed_official | 340:28d1f895c6fe | 6038 | #define RTC_DR_YT_0 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 6039 | #define RTC_DR_YT_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 6040 | #define RTC_DR_YT_2 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 6041 | #define RTC_DR_YT_3 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 6042 | #define RTC_DR_YU ((uint32_t)0x000F0000) |
| mbed_official | 340:28d1f895c6fe | 6043 | #define RTC_DR_YU_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 6044 | #define RTC_DR_YU_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 6045 | #define RTC_DR_YU_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 6046 | #define RTC_DR_YU_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 6047 | #define RTC_DR_WDU ((uint32_t)0x0000E000) |
| mbed_official | 340:28d1f895c6fe | 6048 | #define RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6049 | #define RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6050 | #define RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 6051 | #define RTC_DR_MT ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6052 | #define RTC_DR_MU ((uint32_t)0x00000F00) |
| mbed_official | 340:28d1f895c6fe | 6053 | #define RTC_DR_MU_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6054 | #define RTC_DR_MU_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6055 | #define RTC_DR_MU_2 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6056 | #define RTC_DR_MU_3 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6057 | #define RTC_DR_DT ((uint32_t)0x00000030) |
| mbed_official | 340:28d1f895c6fe | 6058 | #define RTC_DR_DT_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6059 | #define RTC_DR_DT_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6060 | #define RTC_DR_DU ((uint32_t)0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 6061 | #define RTC_DR_DU_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6062 | #define RTC_DR_DU_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6063 | #define RTC_DR_DU_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6064 | #define RTC_DR_DU_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6065 | |
| mbed_official | 340:28d1f895c6fe | 6066 | /******************** Bits definition for RTC_CR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6067 | #define RTC_CR_COE ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 6068 | #define RTC_CR_OSEL ((uint32_t)0x00600000) |
| mbed_official | 340:28d1f895c6fe | 6069 | #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 6070 | #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 6071 | #define RTC_CR_POL ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 6072 | #define RTC_CR_COSEL ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 6073 | #define RTC_CR_BCK ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 6074 | #define RTC_CR_SUB1H ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 6075 | #define RTC_CR_ADD1H ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 6076 | #define RTC_CR_TSIE ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 6077 | #define RTC_CR_WUTIE ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6078 | #define RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6079 | #define RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6080 | #define RTC_CR_TSE ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6081 | #define RTC_CR_WUTE ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6082 | #define RTC_CR_ALRBE ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6083 | #define RTC_CR_ALRAE ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6084 | #define RTC_CR_DCE ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 6085 | #define RTC_CR_FMT ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 6086 | #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6087 | #define RTC_CR_REFCKON ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6088 | #define RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6089 | #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| mbed_official | 340:28d1f895c6fe | 6090 | #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6091 | #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6092 | #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6093 | |
| mbed_official | 340:28d1f895c6fe | 6094 | /******************** Bits definition for RTC_ISR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6095 | #define RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 6096 | #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6097 | #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6098 | #define RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6099 | #define RTC_ISR_TSF ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6100 | #define RTC_ISR_WUTF ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6101 | #define RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6102 | #define RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6103 | #define RTC_ISR_INIT ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 6104 | #define RTC_ISR_INITF ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 6105 | #define RTC_ISR_RSF ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6106 | #define RTC_ISR_INITS ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6107 | #define RTC_ISR_SHPF ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6108 | #define RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6109 | #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6110 | #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6111 | |
| mbed_official | 340:28d1f895c6fe | 6112 | /******************** Bits definition for RTC_PRER register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6113 | #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| mbed_official | 613:bc40b8d2aec4 | 6114 | #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) |
| mbed_official | 340:28d1f895c6fe | 6115 | |
| mbed_official | 340:28d1f895c6fe | 6116 | /******************** Bits definition for RTC_WUTR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6117 | #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| mbed_official | 340:28d1f895c6fe | 6118 | |
| mbed_official | 340:28d1f895c6fe | 6119 | /******************** Bits definition for RTC_CALIBR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6120 | #define RTC_CALIBR_DCS ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 6121 | #define RTC_CALIBR_DC ((uint32_t)0x0000001F) |
| mbed_official | 340:28d1f895c6fe | 6122 | |
| mbed_official | 340:28d1f895c6fe | 6123 | /******************** Bits definition for RTC_ALRMAR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6124 | #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 6125 | #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 6126 | #define RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| mbed_official | 340:28d1f895c6fe | 6127 | #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 6128 | #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 6129 | #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| mbed_official | 340:28d1f895c6fe | 6130 | #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 6131 | #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 6132 | #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 6133 | #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 6134 | #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 6135 | #define RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 6136 | #define RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| mbed_official | 340:28d1f895c6fe | 6137 | #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 6138 | #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 6139 | #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| mbed_official | 340:28d1f895c6fe | 6140 | #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 6141 | #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 6142 | #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 6143 | #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 6144 | #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 6145 | #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| mbed_official | 340:28d1f895c6fe | 6146 | #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6147 | #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6148 | #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6149 | #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| mbed_official | 340:28d1f895c6fe | 6150 | #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6151 | #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6152 | #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6153 | #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6154 | #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 6155 | #define RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| mbed_official | 340:28d1f895c6fe | 6156 | #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6157 | #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6158 | #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 6159 | #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 6160 | #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6161 | #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6162 | #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6163 | #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6164 | |
| mbed_official | 340:28d1f895c6fe | 6165 | /******************** Bits definition for RTC_ALRMBR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6166 | #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 6167 | #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| mbed_official | 340:28d1f895c6fe | 6168 | #define RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| mbed_official | 340:28d1f895c6fe | 6169 | #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| mbed_official | 340:28d1f895c6fe | 6170 | #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| mbed_official | 340:28d1f895c6fe | 6171 | #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| mbed_official | 340:28d1f895c6fe | 6172 | #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 6173 | #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 6174 | #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 6175 | #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 6176 | #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 6177 | #define RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 6178 | #define RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| mbed_official | 340:28d1f895c6fe | 6179 | #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 6180 | #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 6181 | #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| mbed_official | 340:28d1f895c6fe | 6182 | #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 6183 | #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 6184 | #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 6185 | #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 6186 | #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 6187 | #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| mbed_official | 340:28d1f895c6fe | 6188 | #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6189 | #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6190 | #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6191 | #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| mbed_official | 340:28d1f895c6fe | 6192 | #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6193 | #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6194 | #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6195 | #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6196 | #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 6197 | #define RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| mbed_official | 340:28d1f895c6fe | 6198 | #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6199 | #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6200 | #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 6201 | #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 6202 | #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6203 | #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6204 | #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6205 | #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6206 | |
| mbed_official | 340:28d1f895c6fe | 6207 | /******************** Bits definition for RTC_WPR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6208 | #define RTC_WPR_KEY ((uint32_t)0x000000FF) |
| mbed_official | 340:28d1f895c6fe | 6209 | |
| mbed_official | 340:28d1f895c6fe | 6210 | /******************** Bits definition for RTC_SSR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6211 | #define RTC_SSR_SS ((uint32_t)0x0000FFFF) |
| mbed_official | 340:28d1f895c6fe | 6212 | |
| mbed_official | 340:28d1f895c6fe | 6213 | /******************** Bits definition for RTC_SHIFTR register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6214 | #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| mbed_official | 340:28d1f895c6fe | 6215 | #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| mbed_official | 340:28d1f895c6fe | 6216 | |
| mbed_official | 340:28d1f895c6fe | 6217 | /******************** Bits definition for RTC_TSTR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6218 | #define RTC_TSTR_PM ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 6219 | #define RTC_TSTR_HT ((uint32_t)0x00300000) |
| mbed_official | 340:28d1f895c6fe | 6220 | #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| mbed_official | 340:28d1f895c6fe | 6221 | #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 6222 | #define RTC_TSTR_HU ((uint32_t)0x000F0000) |
| mbed_official | 340:28d1f895c6fe | 6223 | #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 6224 | #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 6225 | #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 6226 | #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| mbed_official | 340:28d1f895c6fe | 6227 | #define RTC_TSTR_MNT ((uint32_t)0x00007000) |
| mbed_official | 340:28d1f895c6fe | 6228 | #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6229 | #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6230 | #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6231 | #define RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| mbed_official | 340:28d1f895c6fe | 6232 | #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6233 | #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6234 | #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6235 | #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6236 | #define RTC_TSTR_ST ((uint32_t)0x00000070) |
| mbed_official | 340:28d1f895c6fe | 6237 | #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6238 | #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6239 | #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 6240 | #define RTC_TSTR_SU ((uint32_t)0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 6241 | #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6242 | #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6243 | #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6244 | #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6245 | |
| mbed_official | 340:28d1f895c6fe | 6246 | /******************** Bits definition for RTC_TSDR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6247 | #define RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| mbed_official | 340:28d1f895c6fe | 6248 | #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6249 | #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6250 | #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 6251 | #define RTC_TSDR_MT ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6252 | #define RTC_TSDR_MU ((uint32_t)0x00000F00) |
| mbed_official | 340:28d1f895c6fe | 6253 | #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6254 | #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6255 | #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6256 | #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6257 | #define RTC_TSDR_DT ((uint32_t)0x00000030) |
| mbed_official | 340:28d1f895c6fe | 6258 | #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6259 | #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6260 | #define RTC_TSDR_DU ((uint32_t)0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 6261 | #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6262 | #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6263 | #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6264 | #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6265 | |
| mbed_official | 340:28d1f895c6fe | 6266 | /******************** Bits definition for RTC_TSSSR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6267 | #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
| mbed_official | 340:28d1f895c6fe | 6268 | |
| mbed_official | 340:28d1f895c6fe | 6269 | /******************** Bits definition for RTC_CAL register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6270 | #define RTC_CALR_CALP ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 6271 | #define RTC_CALR_CALW8 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6272 | #define RTC_CALR_CALW16 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6273 | #define RTC_CALR_CALM ((uint32_t)0x000001FF) |
| mbed_official | 340:28d1f895c6fe | 6274 | #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6275 | #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6276 | #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6277 | #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6278 | #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6279 | #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 6280 | #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 6281 | #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 6282 | #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6283 | |
| mbed_official | 340:28d1f895c6fe | 6284 | /******************** Bits definition for RTC_TAFCR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6285 | #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 6286 | #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 6287 | #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 6288 | #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
| mbed_official | 340:28d1f895c6fe | 6289 | #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
| mbed_official | 340:28d1f895c6fe | 6290 | #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| mbed_official | 340:28d1f895c6fe | 6291 | #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| mbed_official | 340:28d1f895c6fe | 6292 | #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
| mbed_official | 340:28d1f895c6fe | 6293 | #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 6294 | #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 6295 | #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
| mbed_official | 340:28d1f895c6fe | 6296 | #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 6297 | #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| mbed_official | 340:28d1f895c6fe | 6298 | #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 6299 | #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 6300 | #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 6301 | #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 6302 | #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6303 | #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6304 | #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6305 | |
| mbed_official | 340:28d1f895c6fe | 6306 | /******************** Bits definition for RTC_ALRMASSR register *************/ |
| mbed_official | 340:28d1f895c6fe | 6307 | #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| mbed_official | 340:28d1f895c6fe | 6308 | #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 6309 | #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 6310 | #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 6311 | #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 6312 | #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| mbed_official | 340:28d1f895c6fe | 6313 | |
| mbed_official | 340:28d1f895c6fe | 6314 | /******************** Bits definition for RTC_ALRMBSSR register *************/ |
| mbed_official | 340:28d1f895c6fe | 6315 | #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
| mbed_official | 340:28d1f895c6fe | 6316 | #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
| mbed_official | 340:28d1f895c6fe | 6317 | #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 6318 | #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 6319 | #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
| mbed_official | 340:28d1f895c6fe | 6320 | #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
| mbed_official | 340:28d1f895c6fe | 6321 | |
| mbed_official | 340:28d1f895c6fe | 6322 | /******************** Bits definition for RTC_BKP0R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6323 | #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6324 | |
| mbed_official | 340:28d1f895c6fe | 6325 | /******************** Bits definition for RTC_BKP1R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6326 | #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6327 | |
| mbed_official | 340:28d1f895c6fe | 6328 | /******************** Bits definition for RTC_BKP2R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6329 | #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6330 | |
| mbed_official | 340:28d1f895c6fe | 6331 | /******************** Bits definition for RTC_BKP3R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6332 | #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6333 | |
| mbed_official | 340:28d1f895c6fe | 6334 | /******************** Bits definition for RTC_BKP4R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6335 | #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6336 | |
| mbed_official | 340:28d1f895c6fe | 6337 | /******************** Bits definition for RTC_BKP5R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6338 | #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6339 | |
| mbed_official | 340:28d1f895c6fe | 6340 | /******************** Bits definition for RTC_BKP6R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6341 | #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6342 | |
| mbed_official | 340:28d1f895c6fe | 6343 | /******************** Bits definition for RTC_BKP7R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6344 | #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6345 | |
| mbed_official | 340:28d1f895c6fe | 6346 | /******************** Bits definition for RTC_BKP8R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6347 | #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6348 | |
| mbed_official | 340:28d1f895c6fe | 6349 | /******************** Bits definition for RTC_BKP9R register ****************/ |
| mbed_official | 340:28d1f895c6fe | 6350 | #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6351 | |
| mbed_official | 340:28d1f895c6fe | 6352 | /******************** Bits definition for RTC_BKP10R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6353 | #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6354 | |
| mbed_official | 340:28d1f895c6fe | 6355 | /******************** Bits definition for RTC_BKP11R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6356 | #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6357 | |
| mbed_official | 340:28d1f895c6fe | 6358 | /******************** Bits definition for RTC_BKP12R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6359 | #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6360 | |
| mbed_official | 340:28d1f895c6fe | 6361 | /******************** Bits definition for RTC_BKP13R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6362 | #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6363 | |
| mbed_official | 340:28d1f895c6fe | 6364 | /******************** Bits definition for RTC_BKP14R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6365 | #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6366 | |
| mbed_official | 340:28d1f895c6fe | 6367 | /******************** Bits definition for RTC_BKP15R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6368 | #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6369 | |
| mbed_official | 340:28d1f895c6fe | 6370 | /******************** Bits definition for RTC_BKP16R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6371 | #define RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6372 | |
| mbed_official | 340:28d1f895c6fe | 6373 | /******************** Bits definition for RTC_BKP17R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6374 | #define RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6375 | |
| mbed_official | 340:28d1f895c6fe | 6376 | /******************** Bits definition for RTC_BKP18R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6377 | #define RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6378 | |
| mbed_official | 340:28d1f895c6fe | 6379 | /******************** Bits definition for RTC_BKP19R register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6380 | #define RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6381 | |
| mbed_official | 340:28d1f895c6fe | 6382 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6383 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6384 | /* Serial Audio Interface */ |
| mbed_official | 340:28d1f895c6fe | 6385 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6386 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6387 | /******************** Bit definition for SAI_GCR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6388 | #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ |
| mbed_official | 340:28d1f895c6fe | 6389 | #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6390 | #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6391 | |
| mbed_official | 340:28d1f895c6fe | 6392 | #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ |
| mbed_official | 340:28d1f895c6fe | 6393 | #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6394 | #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6395 | |
| mbed_official | 340:28d1f895c6fe | 6396 | /******************* Bit definition for SAI_xCR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6397 | #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */ |
| mbed_official | 340:28d1f895c6fe | 6398 | #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6399 | #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6400 | |
| mbed_official | 340:28d1f895c6fe | 6401 | #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */ |
| mbed_official | 340:28d1f895c6fe | 6402 | #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6403 | #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6404 | |
| mbed_official | 340:28d1f895c6fe | 6405 | #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */ |
| mbed_official | 340:28d1f895c6fe | 6406 | #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6407 | #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6408 | #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6409 | |
| mbed_official | 340:28d1f895c6fe | 6410 | #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */ |
| mbed_official | 340:28d1f895c6fe | 6411 | #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */ |
| mbed_official | 340:28d1f895c6fe | 6412 | |
| mbed_official | 340:28d1f895c6fe | 6413 | #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */ |
| mbed_official | 340:28d1f895c6fe | 6414 | #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6415 | #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6416 | |
| mbed_official | 340:28d1f895c6fe | 6417 | #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */ |
| mbed_official | 340:28d1f895c6fe | 6418 | #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */ |
| mbed_official | 340:28d1f895c6fe | 6419 | #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */ |
| mbed_official | 340:28d1f895c6fe | 6420 | #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */ |
| mbed_official | 340:28d1f895c6fe | 6421 | #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */ |
| mbed_official | 340:28d1f895c6fe | 6422 | |
| mbed_official | 532:fe11edbda85c | 6423 | #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */ |
| mbed_official | 532:fe11edbda85c | 6424 | #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 532:fe11edbda85c | 6425 | #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 532:fe11edbda85c | 6426 | #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 532:fe11edbda85c | 6427 | #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 6428 | |
| mbed_official | 340:28d1f895c6fe | 6429 | /******************* Bit definition for SAI_xCR2 register *******************/ |
| mbed_official | 532:fe11edbda85c | 6430 | #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */ |
| mbed_official | 340:28d1f895c6fe | 6431 | #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6432 | #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 532:fe11edbda85c | 6433 | #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6434 | |
| mbed_official | 340:28d1f895c6fe | 6435 | #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */ |
| mbed_official | 340:28d1f895c6fe | 6436 | #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */ |
| mbed_official | 340:28d1f895c6fe | 6437 | #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */ |
| mbed_official | 340:28d1f895c6fe | 6438 | #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */ |
| mbed_official | 340:28d1f895c6fe | 6439 | |
| mbed_official | 340:28d1f895c6fe | 6440 | #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */ |
| mbed_official | 340:28d1f895c6fe | 6441 | #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6442 | #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6443 | #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6444 | #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 6445 | #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 6446 | #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 6447 | |
| mbed_official | 340:28d1f895c6fe | 6448 | #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */ |
| mbed_official | 340:28d1f895c6fe | 6449 | |
| mbed_official | 340:28d1f895c6fe | 6450 | #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */ |
| mbed_official | 340:28d1f895c6fe | 6451 | #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6452 | #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6453 | |
| mbed_official | 340:28d1f895c6fe | 6454 | /****************** Bit definition for SAI_xFRCR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6455 | #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */ |
| mbed_official | 340:28d1f895c6fe | 6456 | #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6457 | #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6458 | #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6459 | #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 6460 | #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 6461 | #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 6462 | #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 6463 | #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 6464 | |
| mbed_official | 340:28d1f895c6fe | 6465 | #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */ |
| mbed_official | 340:28d1f895c6fe | 6466 | #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6467 | #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6468 | #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6469 | #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 6470 | #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 6471 | #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 6472 | #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 6473 | |
| mbed_official | 340:28d1f895c6fe | 6474 | #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */ |
| mbed_official | 340:28d1f895c6fe | 6475 | #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */ |
| mbed_official | 340:28d1f895c6fe | 6476 | #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */ |
| mbed_official | 340:28d1f895c6fe | 6477 | |
| mbed_official | 340:28d1f895c6fe | 6478 | /****************** Bit definition for SAI_xSLOTR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6479 | #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */ |
| mbed_official | 340:28d1f895c6fe | 6480 | #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6481 | #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6482 | #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6483 | #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 6484 | #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 6485 | |
| mbed_official | 340:28d1f895c6fe | 6486 | #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */ |
| mbed_official | 340:28d1f895c6fe | 6487 | #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6488 | #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6489 | |
| mbed_official | 340:28d1f895c6fe | 6490 | #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */ |
| mbed_official | 340:28d1f895c6fe | 6491 | #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6492 | #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6493 | #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6494 | #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 6495 | |
| mbed_official | 340:28d1f895c6fe | 6496 | #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */ |
| mbed_official | 340:28d1f895c6fe | 6497 | |
| mbed_official | 340:28d1f895c6fe | 6498 | /******************* Bit definition for SAI_xIMR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6499 | #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 6500 | #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 6501 | #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 6502 | #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 6503 | #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 6504 | #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 6505 | #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 6506 | |
| mbed_official | 340:28d1f895c6fe | 6507 | /******************** Bit definition for SAI_xSR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6508 | #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */ |
| mbed_official | 340:28d1f895c6fe | 6509 | #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */ |
| mbed_official | 340:28d1f895c6fe | 6510 | #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */ |
| mbed_official | 340:28d1f895c6fe | 6511 | #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */ |
| mbed_official | 340:28d1f895c6fe | 6512 | #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */ |
| mbed_official | 340:28d1f895c6fe | 6513 | #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */ |
| mbed_official | 340:28d1f895c6fe | 6514 | #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */ |
| mbed_official | 340:28d1f895c6fe | 6515 | |
| mbed_official | 340:28d1f895c6fe | 6516 | #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */ |
| mbed_official | 340:28d1f895c6fe | 6517 | #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6518 | #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 613:bc40b8d2aec4 | 6519 | #define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6520 | |
| mbed_official | 340:28d1f895c6fe | 6521 | /****************** Bit definition for SAI_xCLRFR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6522 | #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */ |
| mbed_official | 340:28d1f895c6fe | 6523 | #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */ |
| mbed_official | 340:28d1f895c6fe | 6524 | #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */ |
| mbed_official | 340:28d1f895c6fe | 6525 | #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */ |
| mbed_official | 340:28d1f895c6fe | 6526 | #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */ |
| mbed_official | 340:28d1f895c6fe | 6527 | #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */ |
| mbed_official | 340:28d1f895c6fe | 6528 | #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */ |
| mbed_official | 340:28d1f895c6fe | 6529 | |
| mbed_official | 340:28d1f895c6fe | 6530 | /****************** Bit definition for SAI_xDR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6531 | #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) |
| mbed_official | 340:28d1f895c6fe | 6532 | |
| mbed_official | 340:28d1f895c6fe | 6533 | |
| mbed_official | 340:28d1f895c6fe | 6534 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6535 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6536 | /* SD host Interface */ |
| mbed_official | 340:28d1f895c6fe | 6537 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6538 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6539 | /****************** Bit definition for SDIO_POWER register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6540 | #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */ |
| mbed_official | 340:28d1f895c6fe | 6541 | #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6542 | #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6543 | |
| mbed_official | 340:28d1f895c6fe | 6544 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6545 | #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */ |
| mbed_official | 340:28d1f895c6fe | 6546 | #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */ |
| mbed_official | 340:28d1f895c6fe | 6547 | #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */ |
| mbed_official | 340:28d1f895c6fe | 6548 | #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */ |
| mbed_official | 340:28d1f895c6fe | 6549 | |
| mbed_official | 340:28d1f895c6fe | 6550 | #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
| mbed_official | 340:28d1f895c6fe | 6551 | #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6552 | #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6553 | |
| mbed_official | 340:28d1f895c6fe | 6554 | #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */ |
| mbed_official | 340:28d1f895c6fe | 6555 | #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */ |
| mbed_official | 340:28d1f895c6fe | 6556 | |
| mbed_official | 340:28d1f895c6fe | 6557 | /******************* Bit definition for SDIO_ARG register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6558 | #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */ |
| mbed_official | 340:28d1f895c6fe | 6559 | |
| mbed_official | 340:28d1f895c6fe | 6560 | /******************* Bit definition for SDIO_CMD register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6561 | #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */ |
| mbed_official | 340:28d1f895c6fe | 6562 | |
| mbed_official | 340:28d1f895c6fe | 6563 | #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */ |
| mbed_official | 340:28d1f895c6fe | 6564 | #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6565 | #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6566 | |
| mbed_official | 340:28d1f895c6fe | 6567 | #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */ |
| mbed_official | 340:28d1f895c6fe | 6568 | #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
| mbed_official | 340:28d1f895c6fe | 6569 | #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */ |
| mbed_official | 340:28d1f895c6fe | 6570 | #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */ |
| mbed_official | 340:28d1f895c6fe | 6571 | #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */ |
| mbed_official | 340:28d1f895c6fe | 6572 | #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6573 | #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */ |
| mbed_official | 340:28d1f895c6fe | 6574 | |
| mbed_official | 340:28d1f895c6fe | 6575 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6576 | #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */ |
| mbed_official | 340:28d1f895c6fe | 6577 | |
| mbed_official | 340:28d1f895c6fe | 6578 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6579 | #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 340:28d1f895c6fe | 6580 | |
| mbed_official | 340:28d1f895c6fe | 6581 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6582 | #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 340:28d1f895c6fe | 6583 | |
| mbed_official | 340:28d1f895c6fe | 6584 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6585 | #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 340:28d1f895c6fe | 6586 | |
| mbed_official | 340:28d1f895c6fe | 6587 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6588 | #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 340:28d1f895c6fe | 6589 | |
| mbed_official | 340:28d1f895c6fe | 6590 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6591 | #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 340:28d1f895c6fe | 6592 | |
| mbed_official | 340:28d1f895c6fe | 6593 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6594 | #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */ |
| mbed_official | 340:28d1f895c6fe | 6595 | |
| mbed_official | 340:28d1f895c6fe | 6596 | /****************** Bit definition for SDIO_DLEN register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6597 | #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */ |
| mbed_official | 340:28d1f895c6fe | 6598 | |
| mbed_official | 340:28d1f895c6fe | 6599 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6600 | #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */ |
| mbed_official | 340:28d1f895c6fe | 6601 | #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */ |
| mbed_official | 340:28d1f895c6fe | 6602 | #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */ |
| mbed_official | 340:28d1f895c6fe | 6603 | #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */ |
| mbed_official | 340:28d1f895c6fe | 6604 | |
| mbed_official | 340:28d1f895c6fe | 6605 | #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */ |
| mbed_official | 340:28d1f895c6fe | 6606 | #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6607 | #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6608 | #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6609 | #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 6610 | |
| mbed_official | 340:28d1f895c6fe | 6611 | #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */ |
| mbed_official | 340:28d1f895c6fe | 6612 | #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */ |
| mbed_official | 340:28d1f895c6fe | 6613 | #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */ |
| mbed_official | 340:28d1f895c6fe | 6614 | #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */ |
| mbed_official | 340:28d1f895c6fe | 6615 | |
| mbed_official | 340:28d1f895c6fe | 6616 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6617 | #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */ |
| mbed_official | 340:28d1f895c6fe | 6618 | |
| mbed_official | 340:28d1f895c6fe | 6619 | /****************** Bit definition for SDIO_STA register ********************/ |
| mbed_official | 340:28d1f895c6fe | 6620 | #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */ |
| mbed_official | 340:28d1f895c6fe | 6621 | #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */ |
| mbed_official | 340:28d1f895c6fe | 6622 | #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */ |
| mbed_official | 340:28d1f895c6fe | 6623 | #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */ |
| mbed_official | 340:28d1f895c6fe | 6624 | #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */ |
| mbed_official | 340:28d1f895c6fe | 6625 | #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */ |
| mbed_official | 340:28d1f895c6fe | 6626 | #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */ |
| mbed_official | 340:28d1f895c6fe | 6627 | #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */ |
| mbed_official | 340:28d1f895c6fe | 6628 | #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */ |
| mbed_official | 340:28d1f895c6fe | 6629 | #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */ |
| mbed_official | 340:28d1f895c6fe | 6630 | #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */ |
| mbed_official | 340:28d1f895c6fe | 6631 | #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */ |
| mbed_official | 340:28d1f895c6fe | 6632 | #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */ |
| mbed_official | 340:28d1f895c6fe | 6633 | #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */ |
| mbed_official | 340:28d1f895c6fe | 6634 | #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
| mbed_official | 340:28d1f895c6fe | 6635 | #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
| mbed_official | 340:28d1f895c6fe | 6636 | #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */ |
| mbed_official | 340:28d1f895c6fe | 6637 | #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */ |
| mbed_official | 340:28d1f895c6fe | 6638 | #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */ |
| mbed_official | 340:28d1f895c6fe | 6639 | #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */ |
| mbed_official | 340:28d1f895c6fe | 6640 | #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */ |
| mbed_official | 340:28d1f895c6fe | 6641 | #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */ |
| mbed_official | 340:28d1f895c6fe | 6642 | #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */ |
| mbed_official | 340:28d1f895c6fe | 6643 | #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */ |
| mbed_official | 340:28d1f895c6fe | 6644 | |
| mbed_official | 340:28d1f895c6fe | 6645 | /******************* Bit definition for SDIO_ICR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6646 | #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6647 | #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6648 | #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6649 | #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6650 | #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6651 | #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6652 | #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6653 | #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6654 | #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6655 | #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6656 | #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6657 | #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6658 | #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */ |
| mbed_official | 340:28d1f895c6fe | 6659 | |
| mbed_official | 340:28d1f895c6fe | 6660 | /****************** Bit definition for SDIO_MASK register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6661 | #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6662 | #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6663 | #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6664 | #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6665 | #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6666 | #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6667 | #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6668 | #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6669 | #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6670 | #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6671 | #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6672 | #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6673 | #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6674 | #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */ |
| mbed_official | 340:28d1f895c6fe | 6675 | #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6676 | #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6677 | #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6678 | #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6679 | #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6680 | #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6681 | #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6682 | #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6683 | #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6684 | #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6685 | |
| mbed_official | 340:28d1f895c6fe | 6686 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6687 | #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */ |
| mbed_official | 340:28d1f895c6fe | 6688 | |
| mbed_official | 340:28d1f895c6fe | 6689 | /****************** Bit definition for SDIO_FIFO register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6690 | #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */ |
| mbed_official | 340:28d1f895c6fe | 6691 | |
| mbed_official | 340:28d1f895c6fe | 6692 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6693 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6694 | /* Serial Peripheral Interface */ |
| mbed_official | 340:28d1f895c6fe | 6695 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6696 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6697 | /******************* Bit definition for SPI_CR1 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 6698 | #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */ |
| mbed_official | 340:28d1f895c6fe | 6699 | #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */ |
| mbed_official | 340:28d1f895c6fe | 6700 | #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */ |
| mbed_official | 340:28d1f895c6fe | 6701 | |
| mbed_official | 340:28d1f895c6fe | 6702 | #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */ |
| mbed_official | 340:28d1f895c6fe | 6703 | #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6704 | #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6705 | #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 6706 | |
| mbed_official | 340:28d1f895c6fe | 6707 | #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */ |
| mbed_official | 340:28d1f895c6fe | 6708 | #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */ |
| mbed_official | 340:28d1f895c6fe | 6709 | #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */ |
| mbed_official | 340:28d1f895c6fe | 6710 | #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */ |
| mbed_official | 340:28d1f895c6fe | 6711 | #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */ |
| mbed_official | 340:28d1f895c6fe | 6712 | #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */ |
| mbed_official | 340:28d1f895c6fe | 6713 | #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */ |
| mbed_official | 340:28d1f895c6fe | 6714 | #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */ |
| mbed_official | 340:28d1f895c6fe | 6715 | #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */ |
| mbed_official | 340:28d1f895c6fe | 6716 | #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */ |
| mbed_official | 340:28d1f895c6fe | 6717 | |
| mbed_official | 340:28d1f895c6fe | 6718 | /******************* Bit definition for SPI_CR2 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 6719 | #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */ |
| mbed_official | 340:28d1f895c6fe | 6720 | #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */ |
| mbed_official | 340:28d1f895c6fe | 6721 | #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */ |
| mbed_official | 340:28d1f895c6fe | 6722 | #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */ |
| mbed_official | 340:28d1f895c6fe | 6723 | #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6724 | #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6725 | #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 6726 | |
| mbed_official | 340:28d1f895c6fe | 6727 | /******************** Bit definition for SPI_SR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 6728 | #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */ |
| mbed_official | 340:28d1f895c6fe | 6729 | #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */ |
| mbed_official | 340:28d1f895c6fe | 6730 | #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */ |
| mbed_official | 340:28d1f895c6fe | 6731 | #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */ |
| mbed_official | 340:28d1f895c6fe | 6732 | #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */ |
| mbed_official | 340:28d1f895c6fe | 6733 | #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */ |
| mbed_official | 340:28d1f895c6fe | 6734 | #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */ |
| mbed_official | 340:28d1f895c6fe | 6735 | #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */ |
| mbed_official | 340:28d1f895c6fe | 6736 | #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */ |
| mbed_official | 340:28d1f895c6fe | 6737 | |
| mbed_official | 340:28d1f895c6fe | 6738 | /******************** Bit definition for SPI_DR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 6739 | #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */ |
| mbed_official | 340:28d1f895c6fe | 6740 | |
| mbed_official | 340:28d1f895c6fe | 6741 | /******************* Bit definition for SPI_CRCPR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6742 | #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */ |
| mbed_official | 340:28d1f895c6fe | 6743 | |
| mbed_official | 340:28d1f895c6fe | 6744 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6745 | #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */ |
| mbed_official | 340:28d1f895c6fe | 6746 | |
| mbed_official | 340:28d1f895c6fe | 6747 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6748 | #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */ |
| mbed_official | 340:28d1f895c6fe | 6749 | |
| mbed_official | 340:28d1f895c6fe | 6750 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 6751 | #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */ |
| mbed_official | 340:28d1f895c6fe | 6752 | |
| mbed_official | 340:28d1f895c6fe | 6753 | #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ |
| mbed_official | 340:28d1f895c6fe | 6754 | #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6755 | #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6756 | |
| mbed_official | 340:28d1f895c6fe | 6757 | #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */ |
| mbed_official | 340:28d1f895c6fe | 6758 | |
| mbed_official | 340:28d1f895c6fe | 6759 | #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ |
| mbed_official | 340:28d1f895c6fe | 6760 | #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6761 | #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6762 | |
| mbed_official | 340:28d1f895c6fe | 6763 | #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */ |
| mbed_official | 340:28d1f895c6fe | 6764 | |
| mbed_official | 340:28d1f895c6fe | 6765 | #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ |
| mbed_official | 340:28d1f895c6fe | 6766 | #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 6767 | #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 6768 | |
| mbed_official | 340:28d1f895c6fe | 6769 | #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */ |
| mbed_official | 340:28d1f895c6fe | 6770 | #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */ |
| mbed_official | 340:28d1f895c6fe | 6771 | |
| mbed_official | 340:28d1f895c6fe | 6772 | /****************** Bit definition for SPI_I2SPR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 6773 | #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */ |
| mbed_official | 340:28d1f895c6fe | 6774 | #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */ |
| mbed_official | 340:28d1f895c6fe | 6775 | #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */ |
| mbed_official | 340:28d1f895c6fe | 6776 | |
| mbed_official | 340:28d1f895c6fe | 6777 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6778 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6779 | /* SYSCFG */ |
| mbed_official | 340:28d1f895c6fe | 6780 | /* */ |
| mbed_official | 340:28d1f895c6fe | 6781 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 6782 | /****************** Bit definition for SYSCFG_MEMRMP register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6783 | #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */ |
| mbed_official | 340:28d1f895c6fe | 6784 | #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 6785 | #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 6786 | #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 6787 | |
| mbed_official | 340:28d1f895c6fe | 6788 | #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */ |
| mbed_official | 340:28d1f895c6fe | 6789 | #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */ |
| mbed_official | 340:28d1f895c6fe | 6790 | |
| mbed_official | 340:28d1f895c6fe | 6791 | /****************** Bit definition for SYSCFG_PMC register ******************/ |
| mbed_official | 340:28d1f895c6fe | 6792 | #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */ |
| mbed_official | 340:28d1f895c6fe | 6793 | #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */ |
| mbed_official | 340:28d1f895c6fe | 6794 | #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */ |
| mbed_official | 340:28d1f895c6fe | 6795 | #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */ |
| mbed_official | 340:28d1f895c6fe | 6796 | |
| mbed_official | 340:28d1f895c6fe | 6797 | #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */ |
| mbed_official | 340:28d1f895c6fe | 6798 | /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */ |
| mbed_official | 340:28d1f895c6fe | 6799 | #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
| mbed_official | 340:28d1f895c6fe | 6800 | |
| mbed_official | 340:28d1f895c6fe | 6801 | /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6802 | #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6803 | #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6804 | #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6805 | #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6806 | /** |
| mbed_official | 340:28d1f895c6fe | 6807 | * @brief EXTI0 configuration |
| mbed_official | 340:28d1f895c6fe | 6808 | */ |
| mbed_official | 340:28d1f895c6fe | 6809 | #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6810 | #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6811 | #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6812 | #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6813 | #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6814 | #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6815 | #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6816 | #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6817 | #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6818 | #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6819 | #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */ |
| mbed_official | 340:28d1f895c6fe | 6820 | |
| mbed_official | 340:28d1f895c6fe | 6821 | /** |
| mbed_official | 340:28d1f895c6fe | 6822 | * @brief EXTI1 configuration |
| mbed_official | 340:28d1f895c6fe | 6823 | */ |
| mbed_official | 340:28d1f895c6fe | 6824 | #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6825 | #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6826 | #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6827 | #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6828 | #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6829 | #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6830 | #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6831 | #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6832 | #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6833 | #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6834 | #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */ |
| mbed_official | 340:28d1f895c6fe | 6835 | |
| mbed_official | 340:28d1f895c6fe | 6836 | |
| mbed_official | 340:28d1f895c6fe | 6837 | /** |
| mbed_official | 340:28d1f895c6fe | 6838 | * @brief EXTI2 configuration |
| mbed_official | 340:28d1f895c6fe | 6839 | */ |
| mbed_official | 340:28d1f895c6fe | 6840 | #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6841 | #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6842 | #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6843 | #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6844 | #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6845 | #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6846 | #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6847 | #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6848 | #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6849 | #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6850 | #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */ |
| mbed_official | 340:28d1f895c6fe | 6851 | |
| mbed_official | 340:28d1f895c6fe | 6852 | |
| mbed_official | 340:28d1f895c6fe | 6853 | /** |
| mbed_official | 340:28d1f895c6fe | 6854 | * @brief EXTI3 configuration |
| mbed_official | 340:28d1f895c6fe | 6855 | */ |
| mbed_official | 340:28d1f895c6fe | 6856 | #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6857 | #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6858 | #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6859 | #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6860 | #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6861 | #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6862 | #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6863 | #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6864 | #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6865 | #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6866 | #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */ |
| mbed_official | 340:28d1f895c6fe | 6867 | |
| mbed_official | 340:28d1f895c6fe | 6868 | |
| mbed_official | 340:28d1f895c6fe | 6869 | /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6870 | #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6871 | #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6872 | #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6873 | #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6874 | /** |
| mbed_official | 340:28d1f895c6fe | 6875 | * @brief EXTI4 configuration |
| mbed_official | 340:28d1f895c6fe | 6876 | */ |
| mbed_official | 340:28d1f895c6fe | 6877 | #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6878 | #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6879 | #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6880 | #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6881 | #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6882 | #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6883 | #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6884 | #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6885 | #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6886 | #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6887 | #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */ |
| mbed_official | 340:28d1f895c6fe | 6888 | |
| mbed_official | 340:28d1f895c6fe | 6889 | /** |
| mbed_official | 340:28d1f895c6fe | 6890 | * @brief EXTI5 configuration |
| mbed_official | 340:28d1f895c6fe | 6891 | */ |
| mbed_official | 340:28d1f895c6fe | 6892 | #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6893 | #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6894 | #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6895 | #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6896 | #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6897 | #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6898 | #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6899 | #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6900 | #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6901 | #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6902 | #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */ |
| mbed_official | 340:28d1f895c6fe | 6903 | |
| mbed_official | 340:28d1f895c6fe | 6904 | /** |
| mbed_official | 340:28d1f895c6fe | 6905 | * @brief EXTI6 configuration |
| mbed_official | 340:28d1f895c6fe | 6906 | */ |
| mbed_official | 340:28d1f895c6fe | 6907 | #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6908 | #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6909 | #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6910 | #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6911 | #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6912 | #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6913 | #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6914 | #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6915 | #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6916 | #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6917 | #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */ |
| mbed_official | 340:28d1f895c6fe | 6918 | |
| mbed_official | 340:28d1f895c6fe | 6919 | |
| mbed_official | 340:28d1f895c6fe | 6920 | /** |
| mbed_official | 340:28d1f895c6fe | 6921 | * @brief EXTI7 configuration |
| mbed_official | 340:28d1f895c6fe | 6922 | */ |
| mbed_official | 340:28d1f895c6fe | 6923 | #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6924 | #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6925 | #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6926 | #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6927 | #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6928 | #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6929 | #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6930 | #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6931 | #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6932 | #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6933 | #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */ |
| mbed_official | 340:28d1f895c6fe | 6934 | |
| mbed_official | 340:28d1f895c6fe | 6935 | /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ |
| mbed_official | 340:28d1f895c6fe | 6936 | #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6937 | #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6938 | #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6939 | #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */ |
| mbed_official | 340:28d1f895c6fe | 6940 | |
| mbed_official | 340:28d1f895c6fe | 6941 | /** |
| mbed_official | 340:28d1f895c6fe | 6942 | * @brief EXTI8 configuration |
| mbed_official | 340:28d1f895c6fe | 6943 | */ |
| mbed_official | 340:28d1f895c6fe | 6944 | #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6945 | #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6946 | #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6947 | #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6948 | #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6949 | #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6950 | #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6951 | #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6952 | #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6953 | #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */ |
| mbed_official | 340:28d1f895c6fe | 6954 | |
| mbed_official | 340:28d1f895c6fe | 6955 | /** |
| mbed_official | 340:28d1f895c6fe | 6956 | * @brief EXTI9 configuration |
| mbed_official | 340:28d1f895c6fe | 6957 | */ |
| mbed_official | 340:28d1f895c6fe | 6958 | #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6959 | #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6960 | #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6961 | #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6962 | #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6963 | #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6964 | #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6965 | #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6966 | #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6967 | #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */ |
| mbed_official | 340:28d1f895c6fe | 6968 | |
| mbed_official | 340:28d1f895c6fe | 6969 | |
| mbed_official | 340:28d1f895c6fe | 6970 | /** |
| mbed_official | 340:28d1f895c6fe | 6971 | * @brief EXTI10 configuration |
| mbed_official | 340:28d1f895c6fe | 6972 | */ |
| mbed_official | 340:28d1f895c6fe | 6973 | #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6974 | #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6975 | #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6976 | #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6977 | #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6978 | #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6979 | #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6980 | #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6981 | #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6982 | #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */ |
| mbed_official | 340:28d1f895c6fe | 6983 | |
| mbed_official | 340:28d1f895c6fe | 6984 | |
| mbed_official | 340:28d1f895c6fe | 6985 | /** |
| mbed_official | 340:28d1f895c6fe | 6986 | * @brief EXTI11 configuration |
| mbed_official | 340:28d1f895c6fe | 6987 | */ |
| mbed_official | 340:28d1f895c6fe | 6988 | #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6989 | #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6990 | #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6991 | #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6992 | #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6993 | #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6994 | #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6995 | #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6996 | #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6997 | #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */ |
| mbed_official | 340:28d1f895c6fe | 6998 | |
| mbed_official | 340:28d1f895c6fe | 6999 | |
| mbed_official | 340:28d1f895c6fe | 7000 | /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ |
| mbed_official | 340:28d1f895c6fe | 7001 | #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */ |
| mbed_official | 340:28d1f895c6fe | 7002 | #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */ |
| mbed_official | 340:28d1f895c6fe | 7003 | #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */ |
| mbed_official | 340:28d1f895c6fe | 7004 | #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */ |
| mbed_official | 340:28d1f895c6fe | 7005 | /** |
| mbed_official | 340:28d1f895c6fe | 7006 | * @brief EXTI12 configuration |
| mbed_official | 340:28d1f895c6fe | 7007 | */ |
| mbed_official | 340:28d1f895c6fe | 7008 | #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7009 | #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7010 | #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7011 | #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7012 | #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7013 | #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7014 | #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7015 | #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7016 | #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7017 | #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */ |
| mbed_official | 340:28d1f895c6fe | 7018 | |
| mbed_official | 340:28d1f895c6fe | 7019 | |
| mbed_official | 340:28d1f895c6fe | 7020 | /** |
| mbed_official | 340:28d1f895c6fe | 7021 | * @brief EXTI13 configuration |
| mbed_official | 340:28d1f895c6fe | 7022 | */ |
| mbed_official | 340:28d1f895c6fe | 7023 | #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7024 | #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7025 | #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7026 | #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7027 | #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7028 | #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7029 | #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7030 | #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7031 | #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7032 | #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */ |
| mbed_official | 340:28d1f895c6fe | 7033 | |
| mbed_official | 340:28d1f895c6fe | 7034 | |
| mbed_official | 340:28d1f895c6fe | 7035 | /** |
| mbed_official | 340:28d1f895c6fe | 7036 | * @brief EXTI14 configuration |
| mbed_official | 340:28d1f895c6fe | 7037 | */ |
| mbed_official | 340:28d1f895c6fe | 7038 | #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7039 | #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7040 | #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7041 | #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7042 | #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7043 | #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7044 | #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7045 | #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7046 | #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7047 | #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */ |
| mbed_official | 340:28d1f895c6fe | 7048 | |
| mbed_official | 340:28d1f895c6fe | 7049 | |
| mbed_official | 340:28d1f895c6fe | 7050 | /** |
| mbed_official | 340:28d1f895c6fe | 7051 | * @brief EXTI15 configuration |
| mbed_official | 340:28d1f895c6fe | 7052 | */ |
| mbed_official | 340:28d1f895c6fe | 7053 | #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7054 | #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7055 | #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7056 | #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7057 | #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7058 | #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7059 | #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7060 | #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7061 | #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7062 | #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */ |
| mbed_official | 340:28d1f895c6fe | 7063 | |
| mbed_official | 340:28d1f895c6fe | 7064 | /****************** Bit definition for SYSCFG_CMPCR register ****************/ |
| mbed_official | 340:28d1f895c6fe | 7065 | #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */ |
| mbed_official | 340:28d1f895c6fe | 7066 | #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */ |
| mbed_official | 340:28d1f895c6fe | 7067 | |
| mbed_official | 340:28d1f895c6fe | 7068 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7069 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7070 | /* TIM */ |
| mbed_official | 340:28d1f895c6fe | 7071 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7072 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7073 | /******************* Bit definition for TIM_CR1 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7074 | #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */ |
| mbed_official | 340:28d1f895c6fe | 7075 | #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */ |
| mbed_official | 340:28d1f895c6fe | 7076 | #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */ |
| mbed_official | 340:28d1f895c6fe | 7077 | #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */ |
| mbed_official | 340:28d1f895c6fe | 7078 | #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */ |
| mbed_official | 340:28d1f895c6fe | 7079 | |
| mbed_official | 340:28d1f895c6fe | 7080 | #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
| mbed_official | 340:28d1f895c6fe | 7081 | #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7082 | #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7083 | |
| mbed_official | 340:28d1f895c6fe | 7084 | #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */ |
| mbed_official | 340:28d1f895c6fe | 7085 | |
| mbed_official | 340:28d1f895c6fe | 7086 | #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */ |
| mbed_official | 340:28d1f895c6fe | 7087 | #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7088 | #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7089 | |
| mbed_official | 340:28d1f895c6fe | 7090 | /******************* Bit definition for TIM_CR2 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7091 | #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */ |
| mbed_official | 340:28d1f895c6fe | 7092 | #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */ |
| mbed_official | 340:28d1f895c6fe | 7093 | #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */ |
| mbed_official | 340:28d1f895c6fe | 7094 | |
| mbed_official | 340:28d1f895c6fe | 7095 | #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
| mbed_official | 340:28d1f895c6fe | 7096 | #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7097 | #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7098 | #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7099 | |
| mbed_official | 340:28d1f895c6fe | 7100 | #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */ |
| mbed_official | 340:28d1f895c6fe | 7101 | #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ |
| mbed_official | 340:28d1f895c6fe | 7102 | #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ |
| mbed_official | 340:28d1f895c6fe | 7103 | #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ |
| mbed_official | 340:28d1f895c6fe | 7104 | #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ |
| mbed_official | 340:28d1f895c6fe | 7105 | #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ |
| mbed_official | 340:28d1f895c6fe | 7106 | #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ |
| mbed_official | 340:28d1f895c6fe | 7107 | #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ |
| mbed_official | 340:28d1f895c6fe | 7108 | |
| mbed_official | 340:28d1f895c6fe | 7109 | /******************* Bit definition for TIM_SMCR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7110 | #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ |
| mbed_official | 340:28d1f895c6fe | 7111 | #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7112 | #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7113 | #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7114 | |
| mbed_official | 340:28d1f895c6fe | 7115 | #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ |
| mbed_official | 340:28d1f895c6fe | 7116 | #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7117 | #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7118 | #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7119 | |
| mbed_official | 340:28d1f895c6fe | 7120 | #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */ |
| mbed_official | 340:28d1f895c6fe | 7121 | |
| mbed_official | 340:28d1f895c6fe | 7122 | #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ |
| mbed_official | 340:28d1f895c6fe | 7123 | #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7124 | #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7125 | #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7126 | #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7127 | |
| mbed_official | 340:28d1f895c6fe | 7128 | #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 7129 | #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7130 | #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7131 | |
| mbed_official | 340:28d1f895c6fe | 7132 | #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */ |
| mbed_official | 340:28d1f895c6fe | 7133 | #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */ |
| mbed_official | 340:28d1f895c6fe | 7134 | |
| mbed_official | 340:28d1f895c6fe | 7135 | /******************* Bit definition for TIM_DIER register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7136 | #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7137 | #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7138 | #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7139 | #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7140 | #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7141 | #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7142 | #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7143 | #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7144 | #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */ |
| mbed_official | 340:28d1f895c6fe | 7145 | #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ |
| mbed_official | 340:28d1f895c6fe | 7146 | #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ |
| mbed_official | 340:28d1f895c6fe | 7147 | #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ |
| mbed_official | 340:28d1f895c6fe | 7148 | #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ |
| mbed_official | 340:28d1f895c6fe | 7149 | #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */ |
| mbed_official | 340:28d1f895c6fe | 7150 | #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */ |
| mbed_official | 340:28d1f895c6fe | 7151 | |
| mbed_official | 340:28d1f895c6fe | 7152 | /******************** Bit definition for TIM_SR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7153 | #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7154 | #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7155 | #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7156 | #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7157 | #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7158 | #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7159 | #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7160 | #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7161 | #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ |
| mbed_official | 340:28d1f895c6fe | 7162 | #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ |
| mbed_official | 340:28d1f895c6fe | 7163 | #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ |
| mbed_official | 340:28d1f895c6fe | 7164 | #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ |
| mbed_official | 340:28d1f895c6fe | 7165 | |
| mbed_official | 340:28d1f895c6fe | 7166 | /******************* Bit definition for TIM_EGR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7167 | #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */ |
| mbed_official | 340:28d1f895c6fe | 7168 | #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */ |
| mbed_official | 340:28d1f895c6fe | 7169 | #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */ |
| mbed_official | 340:28d1f895c6fe | 7170 | #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */ |
| mbed_official | 340:28d1f895c6fe | 7171 | #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */ |
| mbed_official | 340:28d1f895c6fe | 7172 | #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */ |
| mbed_official | 340:28d1f895c6fe | 7173 | #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */ |
| mbed_official | 340:28d1f895c6fe | 7174 | #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */ |
| mbed_official | 340:28d1f895c6fe | 7175 | |
| mbed_official | 340:28d1f895c6fe | 7176 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7177 | #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| mbed_official | 340:28d1f895c6fe | 7178 | #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7179 | #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7180 | |
| mbed_official | 340:28d1f895c6fe | 7181 | #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */ |
| mbed_official | 340:28d1f895c6fe | 7182 | #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */ |
| mbed_official | 340:28d1f895c6fe | 7183 | |
| mbed_official | 340:28d1f895c6fe | 7184 | #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
| mbed_official | 340:28d1f895c6fe | 7185 | #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7186 | #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7187 | #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7188 | |
| mbed_official | 340:28d1f895c6fe | 7189 | #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */ |
| mbed_official | 340:28d1f895c6fe | 7190 | |
| mbed_official | 340:28d1f895c6fe | 7191 | #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| mbed_official | 340:28d1f895c6fe | 7192 | #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7193 | #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7194 | |
| mbed_official | 340:28d1f895c6fe | 7195 | #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */ |
| mbed_official | 340:28d1f895c6fe | 7196 | #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */ |
| mbed_official | 340:28d1f895c6fe | 7197 | |
| mbed_official | 340:28d1f895c6fe | 7198 | #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
| mbed_official | 340:28d1f895c6fe | 7199 | #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7200 | #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7201 | #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7202 | |
| mbed_official | 340:28d1f895c6fe | 7203 | #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */ |
| mbed_official | 340:28d1f895c6fe | 7204 | |
| mbed_official | 340:28d1f895c6fe | 7205 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 7206 | |
| mbed_official | 340:28d1f895c6fe | 7207 | #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 7208 | #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7209 | #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7210 | |
| mbed_official | 340:28d1f895c6fe | 7211 | #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
| mbed_official | 340:28d1f895c6fe | 7212 | #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7213 | #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7214 | #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7215 | #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7216 | |
| mbed_official | 340:28d1f895c6fe | 7217 | #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 7218 | #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7219 | #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7220 | |
| mbed_official | 340:28d1f895c6fe | 7221 | #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
| mbed_official | 340:28d1f895c6fe | 7222 | #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7223 | #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7224 | #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7225 | #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7226 | |
| mbed_official | 340:28d1f895c6fe | 7227 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7228 | #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| mbed_official | 340:28d1f895c6fe | 7229 | #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7230 | #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7231 | |
| mbed_official | 340:28d1f895c6fe | 7232 | #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */ |
| mbed_official | 340:28d1f895c6fe | 7233 | #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */ |
| mbed_official | 340:28d1f895c6fe | 7234 | |
| mbed_official | 340:28d1f895c6fe | 7235 | #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
| mbed_official | 340:28d1f895c6fe | 7236 | #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7237 | #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7238 | #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7239 | |
| mbed_official | 340:28d1f895c6fe | 7240 | #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */ |
| mbed_official | 340:28d1f895c6fe | 7241 | |
| mbed_official | 340:28d1f895c6fe | 7242 | #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| mbed_official | 340:28d1f895c6fe | 7243 | #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7244 | #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7245 | |
| mbed_official | 340:28d1f895c6fe | 7246 | #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */ |
| mbed_official | 340:28d1f895c6fe | 7247 | #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */ |
| mbed_official | 340:28d1f895c6fe | 7248 | |
| mbed_official | 340:28d1f895c6fe | 7249 | #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
| mbed_official | 340:28d1f895c6fe | 7250 | #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7251 | #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7252 | #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7253 | |
| mbed_official | 340:28d1f895c6fe | 7254 | #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */ |
| mbed_official | 340:28d1f895c6fe | 7255 | |
| mbed_official | 340:28d1f895c6fe | 7256 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 7257 | |
| mbed_official | 340:28d1f895c6fe | 7258 | #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 7259 | #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7260 | #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7261 | |
| mbed_official | 340:28d1f895c6fe | 7262 | #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
| mbed_official | 340:28d1f895c6fe | 7263 | #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7264 | #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7265 | #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7266 | #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7267 | |
| mbed_official | 340:28d1f895c6fe | 7268 | #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| mbed_official | 340:28d1f895c6fe | 7269 | #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7270 | #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7271 | |
| mbed_official | 340:28d1f895c6fe | 7272 | #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
| mbed_official | 340:28d1f895c6fe | 7273 | #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7274 | #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7275 | #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7276 | #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7277 | |
| mbed_official | 340:28d1f895c6fe | 7278 | /******************* Bit definition for TIM_CCER register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7279 | #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */ |
| mbed_official | 340:28d1f895c6fe | 7280 | #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7281 | #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ |
| mbed_official | 340:28d1f895c6fe | 7282 | #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7283 | #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */ |
| mbed_official | 340:28d1f895c6fe | 7284 | #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7285 | #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ |
| mbed_official | 340:28d1f895c6fe | 7286 | #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7287 | #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */ |
| mbed_official | 340:28d1f895c6fe | 7288 | #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7289 | #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ |
| mbed_official | 340:28d1f895c6fe | 7290 | #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7291 | #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */ |
| mbed_official | 340:28d1f895c6fe | 7292 | #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7293 | #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7294 | |
| mbed_official | 340:28d1f895c6fe | 7295 | /******************* Bit definition for TIM_CNT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7296 | #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */ |
| mbed_official | 340:28d1f895c6fe | 7297 | |
| mbed_official | 340:28d1f895c6fe | 7298 | /******************* Bit definition for TIM_PSC register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7299 | #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */ |
| mbed_official | 340:28d1f895c6fe | 7300 | |
| mbed_official | 340:28d1f895c6fe | 7301 | /******************* Bit definition for TIM_ARR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7302 | #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */ |
| mbed_official | 340:28d1f895c6fe | 7303 | |
| mbed_official | 340:28d1f895c6fe | 7304 | /******************* Bit definition for TIM_RCR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7305 | #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */ |
| mbed_official | 340:28d1f895c6fe | 7306 | |
| mbed_official | 340:28d1f895c6fe | 7307 | /******************* Bit definition for TIM_CCR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7308 | #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */ |
| mbed_official | 340:28d1f895c6fe | 7309 | |
| mbed_official | 340:28d1f895c6fe | 7310 | /******************* Bit definition for TIM_CCR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7311 | #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */ |
| mbed_official | 340:28d1f895c6fe | 7312 | |
| mbed_official | 340:28d1f895c6fe | 7313 | /******************* Bit definition for TIM_CCR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7314 | #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */ |
| mbed_official | 340:28d1f895c6fe | 7315 | |
| mbed_official | 340:28d1f895c6fe | 7316 | /******************* Bit definition for TIM_CCR4 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7317 | #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */ |
| mbed_official | 340:28d1f895c6fe | 7318 | |
| mbed_official | 340:28d1f895c6fe | 7319 | /******************* Bit definition for TIM_BDTR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7320 | #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
| mbed_official | 340:28d1f895c6fe | 7321 | #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7322 | #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7323 | #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7324 | #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7325 | #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 7326 | #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 7327 | #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 7328 | #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 7329 | |
| mbed_official | 340:28d1f895c6fe | 7330 | #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
| mbed_official | 340:28d1f895c6fe | 7331 | #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7332 | #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7333 | |
| mbed_official | 340:28d1f895c6fe | 7334 | #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */ |
| mbed_official | 340:28d1f895c6fe | 7335 | #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */ |
| mbed_official | 340:28d1f895c6fe | 7336 | #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */ |
| mbed_official | 340:28d1f895c6fe | 7337 | #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7338 | #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */ |
| mbed_official | 340:28d1f895c6fe | 7339 | #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */ |
| mbed_official | 340:28d1f895c6fe | 7340 | |
| mbed_official | 340:28d1f895c6fe | 7341 | /******************* Bit definition for TIM_DCR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7342 | #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
| mbed_official | 340:28d1f895c6fe | 7343 | #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7344 | #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7345 | #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7346 | #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7347 | #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 7348 | |
| mbed_official | 340:28d1f895c6fe | 7349 | #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
| mbed_official | 340:28d1f895c6fe | 7350 | #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7351 | #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7352 | #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7353 | #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7354 | #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 7355 | |
| mbed_official | 340:28d1f895c6fe | 7356 | /******************* Bit definition for TIM_DMAR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7357 | #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */ |
| mbed_official | 340:28d1f895c6fe | 7358 | |
| mbed_official | 340:28d1f895c6fe | 7359 | /******************* Bit definition for TIM_OR register *********************/ |
| mbed_official | 340:28d1f895c6fe | 7360 | #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */ |
| mbed_official | 340:28d1f895c6fe | 7361 | #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7362 | #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7363 | #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */ |
| mbed_official | 340:28d1f895c6fe | 7364 | #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7365 | #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7366 | |
| mbed_official | 340:28d1f895c6fe | 7367 | |
| mbed_official | 340:28d1f895c6fe | 7368 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7369 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7370 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
| mbed_official | 340:28d1f895c6fe | 7371 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7372 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7373 | /******************* Bit definition for USART_SR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7374 | #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */ |
| mbed_official | 340:28d1f895c6fe | 7375 | #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */ |
| mbed_official | 340:28d1f895c6fe | 7376 | #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */ |
| mbed_official | 340:28d1f895c6fe | 7377 | #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */ |
| mbed_official | 340:28d1f895c6fe | 7378 | #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */ |
| mbed_official | 340:28d1f895c6fe | 7379 | #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */ |
| mbed_official | 340:28d1f895c6fe | 7380 | #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */ |
| mbed_official | 340:28d1f895c6fe | 7381 | #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */ |
| mbed_official | 340:28d1f895c6fe | 7382 | #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */ |
| mbed_official | 340:28d1f895c6fe | 7383 | #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */ |
| mbed_official | 340:28d1f895c6fe | 7384 | |
| mbed_official | 340:28d1f895c6fe | 7385 | /******************* Bit definition for USART_DR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7386 | #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */ |
| mbed_official | 340:28d1f895c6fe | 7387 | |
| mbed_official | 340:28d1f895c6fe | 7388 | /****************** Bit definition for USART_BRR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7389 | #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */ |
| mbed_official | 340:28d1f895c6fe | 7390 | #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */ |
| mbed_official | 340:28d1f895c6fe | 7391 | |
| mbed_official | 340:28d1f895c6fe | 7392 | /****************** Bit definition for USART_CR1 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7393 | #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */ |
| mbed_official | 340:28d1f895c6fe | 7394 | #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */ |
| mbed_official | 340:28d1f895c6fe | 7395 | #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */ |
| mbed_official | 340:28d1f895c6fe | 7396 | #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */ |
| mbed_official | 340:28d1f895c6fe | 7397 | #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 7398 | #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 7399 | #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 7400 | #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 7401 | #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 7402 | #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */ |
| mbed_official | 340:28d1f895c6fe | 7403 | #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */ |
| mbed_official | 340:28d1f895c6fe | 7404 | #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */ |
| mbed_official | 340:28d1f895c6fe | 7405 | #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */ |
| mbed_official | 340:28d1f895c6fe | 7406 | #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */ |
| mbed_official | 340:28d1f895c6fe | 7407 | #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */ |
| mbed_official | 340:28d1f895c6fe | 7408 | |
| mbed_official | 340:28d1f895c6fe | 7409 | /****************** Bit definition for USART_CR2 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7410 | #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */ |
| mbed_official | 340:28d1f895c6fe | 7411 | #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */ |
| mbed_official | 340:28d1f895c6fe | 7412 | #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 7413 | #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */ |
| mbed_official | 340:28d1f895c6fe | 7414 | #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */ |
| mbed_official | 340:28d1f895c6fe | 7415 | #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */ |
| mbed_official | 340:28d1f895c6fe | 7416 | #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */ |
| mbed_official | 340:28d1f895c6fe | 7417 | |
| mbed_official | 340:28d1f895c6fe | 7418 | #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */ |
| mbed_official | 340:28d1f895c6fe | 7419 | #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7420 | #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7421 | |
| mbed_official | 340:28d1f895c6fe | 7422 | #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */ |
| mbed_official | 340:28d1f895c6fe | 7423 | |
| mbed_official | 340:28d1f895c6fe | 7424 | /****************** Bit definition for USART_CR3 register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7425 | #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 7426 | #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */ |
| mbed_official | 340:28d1f895c6fe | 7427 | #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */ |
| mbed_official | 340:28d1f895c6fe | 7428 | #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */ |
| mbed_official | 340:28d1f895c6fe | 7429 | #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */ |
| mbed_official | 340:28d1f895c6fe | 7430 | #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */ |
| mbed_official | 340:28d1f895c6fe | 7431 | #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */ |
| mbed_official | 340:28d1f895c6fe | 7432 | #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */ |
| mbed_official | 340:28d1f895c6fe | 7433 | #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */ |
| mbed_official | 340:28d1f895c6fe | 7434 | #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */ |
| mbed_official | 340:28d1f895c6fe | 7435 | #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */ |
| mbed_official | 340:28d1f895c6fe | 7436 | #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */ |
| mbed_official | 340:28d1f895c6fe | 7437 | |
| mbed_official | 340:28d1f895c6fe | 7438 | /****************** Bit definition for USART_GTPR register ******************/ |
| mbed_official | 340:28d1f895c6fe | 7439 | #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */ |
| mbed_official | 340:28d1f895c6fe | 7440 | #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7441 | #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7442 | #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7443 | #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7444 | #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 7445 | #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 7446 | #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 7447 | #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 7448 | |
| mbed_official | 340:28d1f895c6fe | 7449 | #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */ |
| mbed_official | 340:28d1f895c6fe | 7450 | |
| mbed_official | 340:28d1f895c6fe | 7451 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7452 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7453 | /* Window WATCHDOG */ |
| mbed_official | 340:28d1f895c6fe | 7454 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7455 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7456 | /******************* Bit definition for WWDG_CR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7457 | #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
| mbed_official | 340:28d1f895c6fe | 7458 | #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7459 | #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7460 | #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7461 | #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7462 | #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 7463 | #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 7464 | #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 7465 | |
| mbed_official | 340:28d1f895c6fe | 7466 | #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */ |
| mbed_official | 340:28d1f895c6fe | 7467 | |
| mbed_official | 340:28d1f895c6fe | 7468 | /******************* Bit definition for WWDG_CFR register *******************/ |
| mbed_official | 340:28d1f895c6fe | 7469 | #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ |
| mbed_official | 340:28d1f895c6fe | 7470 | #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7471 | #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7472 | #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 7473 | #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 7474 | #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 7475 | #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 7476 | #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 7477 | |
| mbed_official | 340:28d1f895c6fe | 7478 | #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ |
| mbed_official | 340:28d1f895c6fe | 7479 | #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7480 | #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7481 | |
| mbed_official | 340:28d1f895c6fe | 7482 | #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 7483 | |
| mbed_official | 340:28d1f895c6fe | 7484 | /******************* Bit definition for WWDG_SR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7485 | #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */ |
| mbed_official | 340:28d1f895c6fe | 7486 | |
| mbed_official | 340:28d1f895c6fe | 7487 | |
| mbed_official | 340:28d1f895c6fe | 7488 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7489 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7490 | /* DBG */ |
| mbed_official | 340:28d1f895c6fe | 7491 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7492 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7493 | /******************** Bit definition for DBGMCU_IDCODE register *************/ |
| mbed_official | 340:28d1f895c6fe | 7494 | #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| mbed_official | 340:28d1f895c6fe | 7495 | #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| mbed_official | 340:28d1f895c6fe | 7496 | |
| mbed_official | 340:28d1f895c6fe | 7497 | /******************** Bit definition for DBGMCU_CR register *****************/ |
| mbed_official | 340:28d1f895c6fe | 7498 | #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 7499 | #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 7500 | #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 7501 | #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 7502 | |
| mbed_official | 340:28d1f895c6fe | 7503 | #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| mbed_official | 340:28d1f895c6fe | 7504 | #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7505 | #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7506 | |
| mbed_official | 340:28d1f895c6fe | 7507 | /******************** Bit definition for DBGMCU_APB1_FZ register ************/ |
| mbed_official | 340:28d1f895c6fe | 7508 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 7509 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 7510 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| mbed_official | 340:28d1f895c6fe | 7511 | #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 7512 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 7513 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 7514 | #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) |
| mbed_official | 340:28d1f895c6fe | 7515 | #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) |
| mbed_official | 340:28d1f895c6fe | 7516 | #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
| mbed_official | 340:28d1f895c6fe | 7517 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| mbed_official | 340:28d1f895c6fe | 7518 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| mbed_official | 340:28d1f895c6fe | 7519 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| mbed_official | 340:28d1f895c6fe | 7520 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| mbed_official | 340:28d1f895c6fe | 7521 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
| mbed_official | 340:28d1f895c6fe | 7522 | #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) |
| mbed_official | 340:28d1f895c6fe | 7523 | #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
| mbed_official | 340:28d1f895c6fe | 7524 | #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) |
| mbed_official | 340:28d1f895c6fe | 7525 | /* Old IWDGSTOP bit definition, maintained for legacy purpose */ |
| mbed_official | 340:28d1f895c6fe | 7526 | #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
| mbed_official | 340:28d1f895c6fe | 7527 | |
| mbed_official | 340:28d1f895c6fe | 7528 | /******************** Bit definition for DBGMCU_APB2_FZ register ************/ |
| mbed_official | 340:28d1f895c6fe | 7529 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 7530 | #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 7531 | #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) |
| mbed_official | 340:28d1f895c6fe | 7532 | #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) |
| mbed_official | 340:28d1f895c6fe | 7533 | #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 7534 | |
| mbed_official | 340:28d1f895c6fe | 7535 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7536 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7537 | /* Ethernet MAC Registers bits definitions */ |
| mbed_official | 340:28d1f895c6fe | 7538 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7539 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7540 | /* Bit definition for Ethernet MAC Control Register register */ |
| mbed_official | 340:28d1f895c6fe | 7541 | #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
| mbed_official | 340:28d1f895c6fe | 7542 | #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
| mbed_official | 340:28d1f895c6fe | 7543 | #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
| mbed_official | 340:28d1f895c6fe | 7544 | #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
| mbed_official | 340:28d1f895c6fe | 7545 | #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
| mbed_official | 340:28d1f895c6fe | 7546 | #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
| mbed_official | 340:28d1f895c6fe | 7547 | #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
| mbed_official | 340:28d1f895c6fe | 7548 | #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
| mbed_official | 340:28d1f895c6fe | 7549 | #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
| mbed_official | 340:28d1f895c6fe | 7550 | #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
| mbed_official | 340:28d1f895c6fe | 7551 | #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
| mbed_official | 340:28d1f895c6fe | 7552 | #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
| mbed_official | 340:28d1f895c6fe | 7553 | #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
| mbed_official | 340:28d1f895c6fe | 7554 | #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
| mbed_official | 340:28d1f895c6fe | 7555 | #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
| mbed_official | 340:28d1f895c6fe | 7556 | #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
| mbed_official | 340:28d1f895c6fe | 7557 | #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
| mbed_official | 340:28d1f895c6fe | 7558 | #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
| mbed_official | 340:28d1f895c6fe | 7559 | #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
| mbed_official | 340:28d1f895c6fe | 7560 | #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling |
| mbed_official | 340:28d1f895c6fe | 7561 | a transmission attempt during retries after a collision: 0 =< r <2^k */ |
| mbed_official | 340:28d1f895c6fe | 7562 | #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
| mbed_official | 340:28d1f895c6fe | 7563 | #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
| mbed_official | 340:28d1f895c6fe | 7564 | #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
| mbed_official | 340:28d1f895c6fe | 7565 | #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
| mbed_official | 340:28d1f895c6fe | 7566 | #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
| mbed_official | 340:28d1f895c6fe | 7567 | #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
| mbed_official | 340:28d1f895c6fe | 7568 | #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
| mbed_official | 340:28d1f895c6fe | 7569 | |
| mbed_official | 340:28d1f895c6fe | 7570 | /* Bit definition for Ethernet MAC Frame Filter Register */ |
| mbed_official | 340:28d1f895c6fe | 7571 | #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
| mbed_official | 340:28d1f895c6fe | 7572 | #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
| mbed_official | 340:28d1f895c6fe | 7573 | #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
| mbed_official | 340:28d1f895c6fe | 7574 | #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
| mbed_official | 340:28d1f895c6fe | 7575 | #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
| mbed_official | 340:28d1f895c6fe | 7576 | #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
| mbed_official | 340:28d1f895c6fe | 7577 | #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| mbed_official | 340:28d1f895c6fe | 7578 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
| mbed_official | 340:28d1f895c6fe | 7579 | #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
| mbed_official | 340:28d1f895c6fe | 7580 | #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
| mbed_official | 340:28d1f895c6fe | 7581 | #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
| mbed_official | 340:28d1f895c6fe | 7582 | #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
| mbed_official | 340:28d1f895c6fe | 7583 | #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
| mbed_official | 340:28d1f895c6fe | 7584 | #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
| mbed_official | 340:28d1f895c6fe | 7585 | |
| mbed_official | 340:28d1f895c6fe | 7586 | /* Bit definition for Ethernet MAC Hash Table High Register */ |
| mbed_official | 340:28d1f895c6fe | 7587 | #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
| mbed_official | 340:28d1f895c6fe | 7588 | |
| mbed_official | 340:28d1f895c6fe | 7589 | /* Bit definition for Ethernet MAC Hash Table Low Register */ |
| mbed_official | 340:28d1f895c6fe | 7590 | #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
| mbed_official | 340:28d1f895c6fe | 7591 | |
| mbed_official | 340:28d1f895c6fe | 7592 | /* Bit definition for Ethernet MAC MII Address Register */ |
| mbed_official | 340:28d1f895c6fe | 7593 | #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
| mbed_official | 340:28d1f895c6fe | 7594 | #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
| mbed_official | 340:28d1f895c6fe | 7595 | #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
| mbed_official | 340:28d1f895c6fe | 7596 | #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
| mbed_official | 340:28d1f895c6fe | 7597 | #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
| mbed_official | 340:28d1f895c6fe | 7598 | #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| mbed_official | 340:28d1f895c6fe | 7599 | #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| mbed_official | 340:28d1f895c6fe | 7600 | #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
| mbed_official | 340:28d1f895c6fe | 7601 | #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
| mbed_official | 340:28d1f895c6fe | 7602 | #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
| mbed_official | 340:28d1f895c6fe | 7603 | |
| mbed_official | 340:28d1f895c6fe | 7604 | /* Bit definition for Ethernet MAC MII Data Register */ |
| mbed_official | 340:28d1f895c6fe | 7605 | #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
| mbed_official | 340:28d1f895c6fe | 7606 | |
| mbed_official | 340:28d1f895c6fe | 7607 | /* Bit definition for Ethernet MAC Flow Control Register */ |
| mbed_official | 340:28d1f895c6fe | 7608 | #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
| mbed_official | 340:28d1f895c6fe | 7609 | #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
| mbed_official | 340:28d1f895c6fe | 7610 | #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
| mbed_official | 340:28d1f895c6fe | 7611 | #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
| mbed_official | 340:28d1f895c6fe | 7612 | #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
| mbed_official | 340:28d1f895c6fe | 7613 | #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
| mbed_official | 340:28d1f895c6fe | 7614 | #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
| mbed_official | 340:28d1f895c6fe | 7615 | #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
| mbed_official | 340:28d1f895c6fe | 7616 | #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
| mbed_official | 340:28d1f895c6fe | 7617 | #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
| mbed_official | 340:28d1f895c6fe | 7618 | #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
| mbed_official | 340:28d1f895c6fe | 7619 | |
| mbed_official | 340:28d1f895c6fe | 7620 | /* Bit definition for Ethernet MAC VLAN Tag Register */ |
| mbed_official | 340:28d1f895c6fe | 7621 | #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
| mbed_official | 340:28d1f895c6fe | 7622 | #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
| mbed_official | 340:28d1f895c6fe | 7623 | |
| mbed_official | 340:28d1f895c6fe | 7624 | /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ |
| mbed_official | 340:28d1f895c6fe | 7625 | #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
| mbed_official | 340:28d1f895c6fe | 7626 | /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. |
| mbed_official | 340:28d1f895c6fe | 7627 | Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ |
| mbed_official | 340:28d1f895c6fe | 7628 | /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask |
| mbed_official | 340:28d1f895c6fe | 7629 | Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask |
| mbed_official | 340:28d1f895c6fe | 7630 | Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask |
| mbed_official | 340:28d1f895c6fe | 7631 | Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask |
| mbed_official | 340:28d1f895c6fe | 7632 | Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - |
| mbed_official | 340:28d1f895c6fe | 7633 | RSVD - Filter1 Command - RSVD - Filter0 Command |
| mbed_official | 340:28d1f895c6fe | 7634 | Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset |
| mbed_official | 340:28d1f895c6fe | 7635 | Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 |
| mbed_official | 340:28d1f895c6fe | 7636 | Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ |
| mbed_official | 340:28d1f895c6fe | 7637 | |
| mbed_official | 340:28d1f895c6fe | 7638 | /* Bit definition for Ethernet MAC PMT Control and Status Register */ |
| mbed_official | 340:28d1f895c6fe | 7639 | #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
| mbed_official | 340:28d1f895c6fe | 7640 | #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
| mbed_official | 340:28d1f895c6fe | 7641 | #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
| mbed_official | 340:28d1f895c6fe | 7642 | #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
| mbed_official | 340:28d1f895c6fe | 7643 | #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
| mbed_official | 340:28d1f895c6fe | 7644 | #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
| mbed_official | 340:28d1f895c6fe | 7645 | #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
| mbed_official | 340:28d1f895c6fe | 7646 | |
| mbed_official | 340:28d1f895c6fe | 7647 | /* Bit definition for Ethernet MAC Status Register */ |
| mbed_official | 340:28d1f895c6fe | 7648 | #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
| mbed_official | 340:28d1f895c6fe | 7649 | #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
| mbed_official | 340:28d1f895c6fe | 7650 | #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
| mbed_official | 340:28d1f895c6fe | 7651 | #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
| mbed_official | 340:28d1f895c6fe | 7652 | #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
| mbed_official | 340:28d1f895c6fe | 7653 | |
| mbed_official | 340:28d1f895c6fe | 7654 | /* Bit definition for Ethernet MAC Interrupt Mask Register */ |
| mbed_official | 340:28d1f895c6fe | 7655 | #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 7656 | #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 7657 | |
| mbed_official | 340:28d1f895c6fe | 7658 | /* Bit definition for Ethernet MAC Address0 High Register */ |
| mbed_official | 340:28d1f895c6fe | 7659 | #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
| mbed_official | 340:28d1f895c6fe | 7660 | |
| mbed_official | 340:28d1f895c6fe | 7661 | /* Bit definition for Ethernet MAC Address0 Low Register */ |
| mbed_official | 340:28d1f895c6fe | 7662 | #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
| mbed_official | 340:28d1f895c6fe | 7663 | |
| mbed_official | 340:28d1f895c6fe | 7664 | /* Bit definition for Ethernet MAC Address1 High Register */ |
| mbed_official | 340:28d1f895c6fe | 7665 | #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| mbed_official | 340:28d1f895c6fe | 7666 | #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
| mbed_official | 340:28d1f895c6fe | 7667 | #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| mbed_official | 340:28d1f895c6fe | 7668 | #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| mbed_official | 340:28d1f895c6fe | 7669 | #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| mbed_official | 340:28d1f895c6fe | 7670 | #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| mbed_official | 340:28d1f895c6fe | 7671 | #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| mbed_official | 340:28d1f895c6fe | 7672 | #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| mbed_official | 340:28d1f895c6fe | 7673 | #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
| mbed_official | 340:28d1f895c6fe | 7674 | #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| mbed_official | 340:28d1f895c6fe | 7675 | |
| mbed_official | 340:28d1f895c6fe | 7676 | /* Bit definition for Ethernet MAC Address1 Low Register */ |
| mbed_official | 340:28d1f895c6fe | 7677 | #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
| mbed_official | 340:28d1f895c6fe | 7678 | |
| mbed_official | 340:28d1f895c6fe | 7679 | /* Bit definition for Ethernet MAC Address2 High Register */ |
| mbed_official | 340:28d1f895c6fe | 7680 | #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| mbed_official | 340:28d1f895c6fe | 7681 | #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
| mbed_official | 340:28d1f895c6fe | 7682 | #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| mbed_official | 340:28d1f895c6fe | 7683 | #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| mbed_official | 340:28d1f895c6fe | 7684 | #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| mbed_official | 340:28d1f895c6fe | 7685 | #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| mbed_official | 340:28d1f895c6fe | 7686 | #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| mbed_official | 340:28d1f895c6fe | 7687 | #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| mbed_official | 340:28d1f895c6fe | 7688 | #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| mbed_official | 340:28d1f895c6fe | 7689 | #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| mbed_official | 340:28d1f895c6fe | 7690 | |
| mbed_official | 340:28d1f895c6fe | 7691 | /* Bit definition for Ethernet MAC Address2 Low Register */ |
| mbed_official | 340:28d1f895c6fe | 7692 | #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
| mbed_official | 340:28d1f895c6fe | 7693 | |
| mbed_official | 340:28d1f895c6fe | 7694 | /* Bit definition for Ethernet MAC Address3 High Register */ |
| mbed_official | 340:28d1f895c6fe | 7695 | #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| mbed_official | 340:28d1f895c6fe | 7696 | #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
| mbed_official | 340:28d1f895c6fe | 7697 | #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| mbed_official | 340:28d1f895c6fe | 7698 | #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| mbed_official | 340:28d1f895c6fe | 7699 | #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| mbed_official | 340:28d1f895c6fe | 7700 | #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| mbed_official | 340:28d1f895c6fe | 7701 | #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| mbed_official | 340:28d1f895c6fe | 7702 | #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| mbed_official | 340:28d1f895c6fe | 7703 | #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| mbed_official | 340:28d1f895c6fe | 7704 | #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
| mbed_official | 340:28d1f895c6fe | 7705 | |
| mbed_official | 340:28d1f895c6fe | 7706 | /* Bit definition for Ethernet MAC Address3 Low Register */ |
| mbed_official | 340:28d1f895c6fe | 7707 | #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
| mbed_official | 340:28d1f895c6fe | 7708 | |
| mbed_official | 340:28d1f895c6fe | 7709 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7710 | /* Ethernet MMC Registers bits definition */ |
| mbed_official | 340:28d1f895c6fe | 7711 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7712 | |
| mbed_official | 340:28d1f895c6fe | 7713 | /* Bit definition for Ethernet MMC Contol Register */ |
| mbed_official | 340:28d1f895c6fe | 7714 | #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */ |
| mbed_official | 340:28d1f895c6fe | 7715 | #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */ |
| mbed_official | 340:28d1f895c6fe | 7716 | #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
| mbed_official | 340:28d1f895c6fe | 7717 | #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
| mbed_official | 340:28d1f895c6fe | 7718 | #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
| mbed_official | 340:28d1f895c6fe | 7719 | #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
| mbed_official | 340:28d1f895c6fe | 7720 | |
| mbed_official | 340:28d1f895c6fe | 7721 | /* Bit definition for Ethernet MMC Receive Interrupt Register */ |
| mbed_official | 340:28d1f895c6fe | 7722 | #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7723 | #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7724 | #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7725 | |
| mbed_official | 340:28d1f895c6fe | 7726 | /* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
| mbed_official | 340:28d1f895c6fe | 7727 | #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7728 | #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7729 | #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7730 | |
| mbed_official | 340:28d1f895c6fe | 7731 | /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
| mbed_official | 340:28d1f895c6fe | 7732 | #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7733 | #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7734 | #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7735 | |
| mbed_official | 340:28d1f895c6fe | 7736 | /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
| mbed_official | 340:28d1f895c6fe | 7737 | #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7738 | #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7739 | #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| mbed_official | 340:28d1f895c6fe | 7740 | |
| mbed_official | 340:28d1f895c6fe | 7741 | /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ |
| mbed_official | 340:28d1f895c6fe | 7742 | #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| mbed_official | 340:28d1f895c6fe | 7743 | |
| mbed_official | 340:28d1f895c6fe | 7744 | /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ |
| mbed_official | 340:28d1f895c6fe | 7745 | #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| mbed_official | 340:28d1f895c6fe | 7746 | |
| mbed_official | 340:28d1f895c6fe | 7747 | /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ |
| mbed_official | 340:28d1f895c6fe | 7748 | #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
| mbed_official | 340:28d1f895c6fe | 7749 | |
| mbed_official | 340:28d1f895c6fe | 7750 | /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ |
| mbed_official | 340:28d1f895c6fe | 7751 | #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
| mbed_official | 340:28d1f895c6fe | 7752 | |
| mbed_official | 340:28d1f895c6fe | 7753 | /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ |
| mbed_official | 340:28d1f895c6fe | 7754 | #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
| mbed_official | 340:28d1f895c6fe | 7755 | |
| mbed_official | 340:28d1f895c6fe | 7756 | /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ |
| mbed_official | 340:28d1f895c6fe | 7757 | #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
| mbed_official | 340:28d1f895c6fe | 7758 | |
| mbed_official | 340:28d1f895c6fe | 7759 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7760 | /* Ethernet PTP Registers bits definition */ |
| mbed_official | 340:28d1f895c6fe | 7761 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7762 | |
| mbed_official | 340:28d1f895c6fe | 7763 | /* Bit definition for Ethernet PTP Time Stamp Contol Register */ |
| mbed_official | 340:28d1f895c6fe | 7764 | #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ |
| mbed_official | 340:28d1f895c6fe | 7765 | #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ |
| mbed_official | 340:28d1f895c6fe | 7766 | #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ |
| mbed_official | 340:28d1f895c6fe | 7767 | #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ |
| mbed_official | 340:28d1f895c6fe | 7768 | #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ |
| mbed_official | 340:28d1f895c6fe | 7769 | #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ |
| mbed_official | 340:28d1f895c6fe | 7770 | #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ |
| mbed_official | 340:28d1f895c6fe | 7771 | #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ |
| mbed_official | 340:28d1f895c6fe | 7772 | #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ |
| mbed_official | 340:28d1f895c6fe | 7773 | |
| mbed_official | 340:28d1f895c6fe | 7774 | #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
| mbed_official | 340:28d1f895c6fe | 7775 | #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
| mbed_official | 340:28d1f895c6fe | 7776 | #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
| mbed_official | 340:28d1f895c6fe | 7777 | #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
| mbed_official | 340:28d1f895c6fe | 7778 | #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
| mbed_official | 340:28d1f895c6fe | 7779 | #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
| mbed_official | 340:28d1f895c6fe | 7780 | |
| mbed_official | 340:28d1f895c6fe | 7781 | /* Bit definition for Ethernet PTP Sub-Second Increment Register */ |
| mbed_official | 340:28d1f895c6fe | 7782 | #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
| mbed_official | 340:28d1f895c6fe | 7783 | |
| mbed_official | 340:28d1f895c6fe | 7784 | /* Bit definition for Ethernet PTP Time Stamp High Register */ |
| mbed_official | 340:28d1f895c6fe | 7785 | #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
| mbed_official | 340:28d1f895c6fe | 7786 | |
| mbed_official | 340:28d1f895c6fe | 7787 | /* Bit definition for Ethernet PTP Time Stamp Low Register */ |
| mbed_official | 340:28d1f895c6fe | 7788 | #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
| mbed_official | 340:28d1f895c6fe | 7789 | #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
| mbed_official | 340:28d1f895c6fe | 7790 | |
| mbed_official | 340:28d1f895c6fe | 7791 | /* Bit definition for Ethernet PTP Time Stamp High Update Register */ |
| mbed_official | 340:28d1f895c6fe | 7792 | #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
| mbed_official | 340:28d1f895c6fe | 7793 | |
| mbed_official | 340:28d1f895c6fe | 7794 | /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ |
| mbed_official | 340:28d1f895c6fe | 7795 | #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
| mbed_official | 340:28d1f895c6fe | 7796 | #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
| mbed_official | 340:28d1f895c6fe | 7797 | |
| mbed_official | 340:28d1f895c6fe | 7798 | /* Bit definition for Ethernet PTP Time Stamp Addend Register */ |
| mbed_official | 340:28d1f895c6fe | 7799 | #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
| mbed_official | 340:28d1f895c6fe | 7800 | |
| mbed_official | 340:28d1f895c6fe | 7801 | /* Bit definition for Ethernet PTP Target Time High Register */ |
| mbed_official | 340:28d1f895c6fe | 7802 | #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
| mbed_official | 340:28d1f895c6fe | 7803 | |
| mbed_official | 340:28d1f895c6fe | 7804 | /* Bit definition for Ethernet PTP Target Time Low Register */ |
| mbed_official | 340:28d1f895c6fe | 7805 | #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
| mbed_official | 340:28d1f895c6fe | 7806 | |
| mbed_official | 340:28d1f895c6fe | 7807 | /* Bit definition for Ethernet PTP Time Stamp Status Register */ |
| mbed_official | 340:28d1f895c6fe | 7808 | #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ |
| mbed_official | 340:28d1f895c6fe | 7809 | #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ |
| mbed_official | 340:28d1f895c6fe | 7810 | |
| mbed_official | 340:28d1f895c6fe | 7811 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7812 | /* Ethernet DMA Registers bits definition */ |
| mbed_official | 340:28d1f895c6fe | 7813 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7814 | |
| mbed_official | 340:28d1f895c6fe | 7815 | /* Bit definition for Ethernet DMA Bus Mode Register */ |
| mbed_official | 340:28d1f895c6fe | 7816 | #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
| mbed_official | 340:28d1f895c6fe | 7817 | #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
| mbed_official | 340:28d1f895c6fe | 7818 | #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
| mbed_official | 340:28d1f895c6fe | 7819 | #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
| mbed_official | 340:28d1f895c6fe | 7820 | #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| mbed_official | 340:28d1f895c6fe | 7821 | #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| mbed_official | 340:28d1f895c6fe | 7822 | #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| mbed_official | 340:28d1f895c6fe | 7823 | #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| mbed_official | 340:28d1f895c6fe | 7824 | #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| mbed_official | 340:28d1f895c6fe | 7825 | #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| mbed_official | 340:28d1f895c6fe | 7826 | #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| mbed_official | 340:28d1f895c6fe | 7827 | #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| mbed_official | 340:28d1f895c6fe | 7828 | #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| mbed_official | 340:28d1f895c6fe | 7829 | #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| mbed_official | 340:28d1f895c6fe | 7830 | #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| mbed_official | 340:28d1f895c6fe | 7831 | #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| mbed_official | 340:28d1f895c6fe | 7832 | #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
| mbed_official | 340:28d1f895c6fe | 7833 | #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| mbed_official | 340:28d1f895c6fe | 7834 | #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
| mbed_official | 340:28d1f895c6fe | 7835 | #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
| mbed_official | 340:28d1f895c6fe | 7836 | #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
| mbed_official | 340:28d1f895c6fe | 7837 | #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| mbed_official | 340:28d1f895c6fe | 7838 | #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
| mbed_official | 340:28d1f895c6fe | 7839 | #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| mbed_official | 340:28d1f895c6fe | 7840 | #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| mbed_official | 340:28d1f895c6fe | 7841 | #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| mbed_official | 340:28d1f895c6fe | 7842 | #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| mbed_official | 340:28d1f895c6fe | 7843 | #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| mbed_official | 340:28d1f895c6fe | 7844 | #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| mbed_official | 340:28d1f895c6fe | 7845 | #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| mbed_official | 340:28d1f895c6fe | 7846 | #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| mbed_official | 340:28d1f895c6fe | 7847 | #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| mbed_official | 340:28d1f895c6fe | 7848 | #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| mbed_official | 340:28d1f895c6fe | 7849 | #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| mbed_official | 340:28d1f895c6fe | 7850 | #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| mbed_official | 340:28d1f895c6fe | 7851 | #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ |
| mbed_official | 340:28d1f895c6fe | 7852 | #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
| mbed_official | 340:28d1f895c6fe | 7853 | #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
| mbed_official | 340:28d1f895c6fe | 7854 | #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
| mbed_official | 340:28d1f895c6fe | 7855 | |
| mbed_official | 340:28d1f895c6fe | 7856 | /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ |
| mbed_official | 340:28d1f895c6fe | 7857 | #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
| mbed_official | 340:28d1f895c6fe | 7858 | |
| mbed_official | 340:28d1f895c6fe | 7859 | /* Bit definition for Ethernet DMA Receive Poll Demand Register */ |
| mbed_official | 340:28d1f895c6fe | 7860 | #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
| mbed_official | 340:28d1f895c6fe | 7861 | |
| mbed_official | 340:28d1f895c6fe | 7862 | /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ |
| mbed_official | 340:28d1f895c6fe | 7863 | #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
| mbed_official | 340:28d1f895c6fe | 7864 | |
| mbed_official | 340:28d1f895c6fe | 7865 | /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ |
| mbed_official | 340:28d1f895c6fe | 7866 | #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
| mbed_official | 340:28d1f895c6fe | 7867 | |
| mbed_official | 340:28d1f895c6fe | 7868 | /* Bit definition for Ethernet DMA Status Register */ |
| mbed_official | 340:28d1f895c6fe | 7869 | #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
| mbed_official | 340:28d1f895c6fe | 7870 | #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
| mbed_official | 340:28d1f895c6fe | 7871 | #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
| mbed_official | 340:28d1f895c6fe | 7872 | #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
| mbed_official | 340:28d1f895c6fe | 7873 | /* combination with EBS[2:0] for GetFlagStatus function */ |
| mbed_official | 340:28d1f895c6fe | 7874 | #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
| mbed_official | 340:28d1f895c6fe | 7875 | #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
| mbed_official | 340:28d1f895c6fe | 7876 | #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| mbed_official | 340:28d1f895c6fe | 7877 | #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
| mbed_official | 340:28d1f895c6fe | 7878 | #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
| mbed_official | 340:28d1f895c6fe | 7879 | #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
| mbed_official | 340:28d1f895c6fe | 7880 | #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
| mbed_official | 340:28d1f895c6fe | 7881 | #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
| mbed_official | 340:28d1f895c6fe | 7882 | #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
| mbed_official | 340:28d1f895c6fe | 7883 | #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
| mbed_official | 340:28d1f895c6fe | 7884 | #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
| mbed_official | 340:28d1f895c6fe | 7885 | #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
| mbed_official | 340:28d1f895c6fe | 7886 | #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
| mbed_official | 340:28d1f895c6fe | 7887 | #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
| mbed_official | 340:28d1f895c6fe | 7888 | #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
| mbed_official | 340:28d1f895c6fe | 7889 | #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
| mbed_official | 340:28d1f895c6fe | 7890 | #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
| mbed_official | 340:28d1f895c6fe | 7891 | #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
| mbed_official | 340:28d1f895c6fe | 7892 | #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
| mbed_official | 340:28d1f895c6fe | 7893 | #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
| mbed_official | 340:28d1f895c6fe | 7894 | #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
| mbed_official | 340:28d1f895c6fe | 7895 | #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
| mbed_official | 340:28d1f895c6fe | 7896 | #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
| mbed_official | 340:28d1f895c6fe | 7897 | #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
| mbed_official | 340:28d1f895c6fe | 7898 | #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
| mbed_official | 340:28d1f895c6fe | 7899 | #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
| mbed_official | 340:28d1f895c6fe | 7900 | #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
| mbed_official | 340:28d1f895c6fe | 7901 | #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
| mbed_official | 340:28d1f895c6fe | 7902 | #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
| mbed_official | 340:28d1f895c6fe | 7903 | #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
| mbed_official | 340:28d1f895c6fe | 7904 | #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
| mbed_official | 340:28d1f895c6fe | 7905 | #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
| mbed_official | 340:28d1f895c6fe | 7906 | |
| mbed_official | 340:28d1f895c6fe | 7907 | /* Bit definition for Ethernet DMA Operation Mode Register */ |
| mbed_official | 340:28d1f895c6fe | 7908 | #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
| mbed_official | 340:28d1f895c6fe | 7909 | #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
| mbed_official | 340:28d1f895c6fe | 7910 | #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
| mbed_official | 340:28d1f895c6fe | 7911 | #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
| mbed_official | 340:28d1f895c6fe | 7912 | #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
| mbed_official | 340:28d1f895c6fe | 7913 | #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
| mbed_official | 340:28d1f895c6fe | 7914 | #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7915 | #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7916 | #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7917 | #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7918 | #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7919 | #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7920 | #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7921 | #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7922 | #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
| mbed_official | 340:28d1f895c6fe | 7923 | #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
| mbed_official | 340:28d1f895c6fe | 7924 | #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
| mbed_official | 340:28d1f895c6fe | 7925 | #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
| mbed_official | 340:28d1f895c6fe | 7926 | #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7927 | #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7928 | #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7929 | #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| mbed_official | 340:28d1f895c6fe | 7930 | #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
| mbed_official | 340:28d1f895c6fe | 7931 | #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
| mbed_official | 340:28d1f895c6fe | 7932 | |
| mbed_official | 340:28d1f895c6fe | 7933 | /* Bit definition for Ethernet DMA Interrupt Enable Register */ |
| mbed_official | 340:28d1f895c6fe | 7934 | #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
| mbed_official | 340:28d1f895c6fe | 7935 | #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
| mbed_official | 340:28d1f895c6fe | 7936 | #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7937 | #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7938 | #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7939 | #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7940 | #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7941 | #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7942 | #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7943 | #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7944 | #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7945 | #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7946 | #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7947 | #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7948 | #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
| mbed_official | 340:28d1f895c6fe | 7949 | |
| mbed_official | 340:28d1f895c6fe | 7950 | /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ |
| mbed_official | 340:28d1f895c6fe | 7951 | #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
| mbed_official | 340:28d1f895c6fe | 7952 | #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
| mbed_official | 340:28d1f895c6fe | 7953 | #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
| mbed_official | 340:28d1f895c6fe | 7954 | #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
| mbed_official | 340:28d1f895c6fe | 7955 | |
| mbed_official | 340:28d1f895c6fe | 7956 | /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ |
| mbed_official | 340:28d1f895c6fe | 7957 | #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
| mbed_official | 340:28d1f895c6fe | 7958 | |
| mbed_official | 340:28d1f895c6fe | 7959 | /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ |
| mbed_official | 340:28d1f895c6fe | 7960 | #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
| mbed_official | 340:28d1f895c6fe | 7961 | |
| mbed_official | 340:28d1f895c6fe | 7962 | /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ |
| mbed_official | 340:28d1f895c6fe | 7963 | #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
| mbed_official | 340:28d1f895c6fe | 7964 | |
| mbed_official | 340:28d1f895c6fe | 7965 | /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ |
| mbed_official | 340:28d1f895c6fe | 7966 | #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
| mbed_official | 340:28d1f895c6fe | 7967 | |
| mbed_official | 340:28d1f895c6fe | 7968 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7969 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7970 | /* USB_OTG */ |
| mbed_official | 340:28d1f895c6fe | 7971 | /* */ |
| mbed_official | 340:28d1f895c6fe | 7972 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 7973 | /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7974 | #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */ |
| mbed_official | 340:28d1f895c6fe | 7975 | #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */ |
| mbed_official | 340:28d1f895c6fe | 7976 | #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */ |
| mbed_official | 340:28d1f895c6fe | 7977 | #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */ |
| mbed_official | 340:28d1f895c6fe | 7978 | #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */ |
| mbed_official | 340:28d1f895c6fe | 7979 | #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */ |
| mbed_official | 340:28d1f895c6fe | 7980 | #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */ |
| mbed_official | 340:28d1f895c6fe | 7981 | #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */ |
| mbed_official | 340:28d1f895c6fe | 7982 | #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */ |
| mbed_official | 340:28d1f895c6fe | 7983 | #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */ |
| mbed_official | 340:28d1f895c6fe | 7984 | |
| mbed_official | 340:28d1f895c6fe | 7985 | /******************** Bit definition forUSB_OTG_HCFG register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7986 | |
| mbed_official | 340:28d1f895c6fe | 7987 | #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */ |
| mbed_official | 340:28d1f895c6fe | 7988 | #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7989 | #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7990 | #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */ |
| mbed_official | 340:28d1f895c6fe | 7991 | |
| mbed_official | 340:28d1f895c6fe | 7992 | /******************** Bit definition forUSB_OTG_DCFG register ********************/ |
| mbed_official | 340:28d1f895c6fe | 7993 | |
| mbed_official | 340:28d1f895c6fe | 7994 | #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */ |
| mbed_official | 340:28d1f895c6fe | 7995 | #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 7996 | #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 7997 | #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */ |
| mbed_official | 340:28d1f895c6fe | 7998 | |
| mbed_official | 340:28d1f895c6fe | 7999 | #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */ |
| mbed_official | 340:28d1f895c6fe | 8000 | #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8001 | #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8002 | #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8003 | #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8004 | #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8005 | #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8006 | #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8007 | |
| mbed_official | 340:28d1f895c6fe | 8008 | #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */ |
| mbed_official | 340:28d1f895c6fe | 8009 | #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8010 | #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8011 | |
| mbed_official | 340:28d1f895c6fe | 8012 | #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */ |
| mbed_official | 340:28d1f895c6fe | 8013 | #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8014 | #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8015 | |
| mbed_official | 340:28d1f895c6fe | 8016 | /******************** Bit definition forUSB_OTG_PCGCR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8017 | #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */ |
| mbed_official | 340:28d1f895c6fe | 8018 | #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */ |
| mbed_official | 340:28d1f895c6fe | 8019 | #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */ |
| mbed_official | 340:28d1f895c6fe | 8020 | |
| mbed_official | 340:28d1f895c6fe | 8021 | /******************** Bit definition forUSB_OTG_GOTGINT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8022 | #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */ |
| mbed_official | 340:28d1f895c6fe | 8023 | #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */ |
| mbed_official | 340:28d1f895c6fe | 8024 | #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */ |
| mbed_official | 340:28d1f895c6fe | 8025 | #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */ |
| mbed_official | 340:28d1f895c6fe | 8026 | #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */ |
| mbed_official | 340:28d1f895c6fe | 8027 | #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */ |
| mbed_official | 340:28d1f895c6fe | 8028 | |
| mbed_official | 340:28d1f895c6fe | 8029 | /******************** Bit definition forUSB_OTG_DCTL register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8030 | #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */ |
| mbed_official | 340:28d1f895c6fe | 8031 | #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */ |
| mbed_official | 340:28d1f895c6fe | 8032 | #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */ |
| mbed_official | 340:28d1f895c6fe | 8033 | #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */ |
| mbed_official | 340:28d1f895c6fe | 8034 | |
| mbed_official | 340:28d1f895c6fe | 8035 | #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */ |
| mbed_official | 340:28d1f895c6fe | 8036 | #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8037 | #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8038 | #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8039 | #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */ |
| mbed_official | 340:28d1f895c6fe | 8040 | #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */ |
| mbed_official | 340:28d1f895c6fe | 8041 | #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */ |
| mbed_official | 340:28d1f895c6fe | 8042 | #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */ |
| mbed_official | 340:28d1f895c6fe | 8043 | #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */ |
| mbed_official | 340:28d1f895c6fe | 8044 | |
| mbed_official | 340:28d1f895c6fe | 8045 | /******************** Bit definition forUSB_OTG_HFIR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8046 | #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */ |
| mbed_official | 340:28d1f895c6fe | 8047 | |
| mbed_official | 340:28d1f895c6fe | 8048 | /******************** Bit definition forUSB_OTG_HFNUM register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8049 | #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */ |
| mbed_official | 340:28d1f895c6fe | 8050 | #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */ |
| mbed_official | 340:28d1f895c6fe | 8051 | |
| mbed_official | 340:28d1f895c6fe | 8052 | /******************** Bit definition forUSB_OTG_DSTS register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8053 | #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */ |
| mbed_official | 340:28d1f895c6fe | 8054 | |
| mbed_official | 340:28d1f895c6fe | 8055 | #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */ |
| mbed_official | 340:28d1f895c6fe | 8056 | #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8057 | #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8058 | #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */ |
| mbed_official | 340:28d1f895c6fe | 8059 | #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */ |
| mbed_official | 340:28d1f895c6fe | 8060 | |
| mbed_official | 340:28d1f895c6fe | 8061 | /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8062 | #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8063 | |
| mbed_official | 340:28d1f895c6fe | 8064 | #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */ |
| mbed_official | 340:28d1f895c6fe | 8065 | #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8066 | #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8067 | #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8068 | #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8069 | #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */ |
| mbed_official | 340:28d1f895c6fe | 8070 | #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */ |
| mbed_official | 340:28d1f895c6fe | 8071 | #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */ |
| mbed_official | 340:28d1f895c6fe | 8072 | |
| mbed_official | 340:28d1f895c6fe | 8073 | /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8074 | |
| mbed_official | 340:28d1f895c6fe | 8075 | #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */ |
| mbed_official | 340:28d1f895c6fe | 8076 | #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8077 | #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8078 | #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8079 | #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ |
| mbed_official | 340:28d1f895c6fe | 8080 | #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */ |
| mbed_official | 340:28d1f895c6fe | 8081 | #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */ |
| mbed_official | 340:28d1f895c6fe | 8082 | |
| mbed_official | 340:28d1f895c6fe | 8083 | #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */ |
| mbed_official | 340:28d1f895c6fe | 8084 | #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8085 | #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8086 | #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8087 | #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8088 | #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */ |
| mbed_official | 340:28d1f895c6fe | 8089 | #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */ |
| mbed_official | 340:28d1f895c6fe | 8090 | #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */ |
| mbed_official | 340:28d1f895c6fe | 8091 | #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */ |
| mbed_official | 340:28d1f895c6fe | 8092 | #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */ |
| mbed_official | 340:28d1f895c6fe | 8093 | #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */ |
| mbed_official | 340:28d1f895c6fe | 8094 | #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */ |
| mbed_official | 340:28d1f895c6fe | 8095 | #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */ |
| mbed_official | 340:28d1f895c6fe | 8096 | #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */ |
| mbed_official | 340:28d1f895c6fe | 8097 | #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */ |
| mbed_official | 340:28d1f895c6fe | 8098 | #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */ |
| mbed_official | 340:28d1f895c6fe | 8099 | #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */ |
| mbed_official | 340:28d1f895c6fe | 8100 | #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */ |
| mbed_official | 340:28d1f895c6fe | 8101 | |
| mbed_official | 340:28d1f895c6fe | 8102 | /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8103 | #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */ |
| mbed_official | 340:28d1f895c6fe | 8104 | #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */ |
| mbed_official | 340:28d1f895c6fe | 8105 | #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */ |
| mbed_official | 340:28d1f895c6fe | 8106 | #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */ |
| mbed_official | 340:28d1f895c6fe | 8107 | #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */ |
| mbed_official | 340:28d1f895c6fe | 8108 | |
| mbed_official | 340:28d1f895c6fe | 8109 | #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */ |
| mbed_official | 340:28d1f895c6fe | 8110 | #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8111 | #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8112 | #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8113 | #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8114 | #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8115 | #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */ |
| mbed_official | 340:28d1f895c6fe | 8116 | #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */ |
| mbed_official | 340:28d1f895c6fe | 8117 | |
| mbed_official | 340:28d1f895c6fe | 8118 | /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8119 | #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8120 | #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8121 | #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */ |
| mbed_official | 340:28d1f895c6fe | 8122 | #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ |
| mbed_official | 340:28d1f895c6fe | 8123 | #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ |
| mbed_official | 340:28d1f895c6fe | 8124 | #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ |
| mbed_official | 340:28d1f895c6fe | 8125 | #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */ |
| mbed_official | 340:28d1f895c6fe | 8126 | #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8127 | |
| mbed_official | 340:28d1f895c6fe | 8128 | /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8129 | #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */ |
| mbed_official | 340:28d1f895c6fe | 8130 | |
| mbed_official | 340:28d1f895c6fe | 8131 | #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */ |
| mbed_official | 340:28d1f895c6fe | 8132 | #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8133 | #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8134 | #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8135 | #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8136 | #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8137 | #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8138 | #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8139 | #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 8140 | |
| mbed_official | 340:28d1f895c6fe | 8141 | #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */ |
| mbed_official | 340:28d1f895c6fe | 8142 | #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8143 | #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8144 | #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8145 | #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8146 | #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8147 | #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8148 | #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8149 | #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 8150 | |
| mbed_official | 340:28d1f895c6fe | 8151 | /******************** Bit definition forUSB_OTG_HAINT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8152 | #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */ |
| mbed_official | 340:28d1f895c6fe | 8153 | |
| mbed_official | 340:28d1f895c6fe | 8154 | /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8155 | #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8156 | #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8157 | #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */ |
| mbed_official | 340:28d1f895c6fe | 8158 | #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */ |
| mbed_official | 340:28d1f895c6fe | 8159 | #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */ |
| mbed_official | 340:28d1f895c6fe | 8160 | #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */ |
| mbed_official | 340:28d1f895c6fe | 8161 | #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8162 | |
| mbed_official | 340:28d1f895c6fe | 8163 | /******************** Bit definition forUSB_OTG_GINTSTS register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8164 | #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */ |
| mbed_official | 340:28d1f895c6fe | 8165 | #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8166 | #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8167 | #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */ |
| mbed_official | 340:28d1f895c6fe | 8168 | #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */ |
| mbed_official | 340:28d1f895c6fe | 8169 | #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */ |
| mbed_official | 340:28d1f895c6fe | 8170 | #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */ |
| mbed_official | 340:28d1f895c6fe | 8171 | #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */ |
| mbed_official | 340:28d1f895c6fe | 8172 | #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */ |
| mbed_official | 340:28d1f895c6fe | 8173 | #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */ |
| mbed_official | 340:28d1f895c6fe | 8174 | #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */ |
| mbed_official | 340:28d1f895c6fe | 8175 | #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */ |
| mbed_official | 340:28d1f895c6fe | 8176 | #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8177 | #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8178 | #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8179 | #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8180 | #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */ |
| mbed_official | 340:28d1f895c6fe | 8181 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */ |
| mbed_official | 340:28d1f895c6fe | 8182 | #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */ |
| mbed_official | 340:28d1f895c6fe | 8183 | #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8184 | #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8185 | #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */ |
| mbed_official | 340:28d1f895c6fe | 8186 | #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */ |
| mbed_official | 340:28d1f895c6fe | 8187 | #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8188 | #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8189 | #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8190 | |
| mbed_official | 340:28d1f895c6fe | 8191 | /******************** Bit definition forUSB_OTG_GINTMSK register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8192 | #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8193 | #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8194 | #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */ |
| mbed_official | 340:28d1f895c6fe | 8195 | #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */ |
| mbed_official | 340:28d1f895c6fe | 8196 | #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */ |
| mbed_official | 340:28d1f895c6fe | 8197 | #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */ |
| mbed_official | 340:28d1f895c6fe | 8198 | #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */ |
| mbed_official | 340:28d1f895c6fe | 8199 | #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */ |
| mbed_official | 340:28d1f895c6fe | 8200 | #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */ |
| mbed_official | 340:28d1f895c6fe | 8201 | #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */ |
| mbed_official | 340:28d1f895c6fe | 8202 | #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */ |
| mbed_official | 340:28d1f895c6fe | 8203 | #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8204 | #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8205 | #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8206 | #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8207 | #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8208 | #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */ |
| mbed_official | 340:28d1f895c6fe | 8209 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */ |
| mbed_official | 340:28d1f895c6fe | 8210 | #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */ |
| mbed_official | 340:28d1f895c6fe | 8211 | #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8212 | #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8213 | #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */ |
| mbed_official | 340:28d1f895c6fe | 8214 | #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */ |
| mbed_official | 340:28d1f895c6fe | 8215 | #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8216 | #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8217 | #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8218 | |
| mbed_official | 340:28d1f895c6fe | 8219 | /******************** Bit definition forUSB_OTG_DAINT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8220 | #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */ |
| mbed_official | 340:28d1f895c6fe | 8221 | #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */ |
| mbed_official | 340:28d1f895c6fe | 8222 | |
| mbed_official | 340:28d1f895c6fe | 8223 | /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8224 | #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8225 | |
| mbed_official | 340:28d1f895c6fe | 8226 | /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8227 | #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */ |
| mbed_official | 340:28d1f895c6fe | 8228 | #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */ |
| mbed_official | 340:28d1f895c6fe | 8229 | #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */ |
| mbed_official | 340:28d1f895c6fe | 8230 | #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */ |
| mbed_official | 340:28d1f895c6fe | 8231 | |
| mbed_official | 340:28d1f895c6fe | 8232 | /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8233 | #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */ |
| mbed_official | 340:28d1f895c6fe | 8234 | #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */ |
| mbed_official | 340:28d1f895c6fe | 8235 | |
| mbed_official | 340:28d1f895c6fe | 8236 | /******************** Bit definition for OTG register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8237 | |
| mbed_official | 340:28d1f895c6fe | 8238 | #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */ |
| mbed_official | 340:28d1f895c6fe | 8239 | #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8240 | #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8241 | #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8242 | #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8243 | #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */ |
| mbed_official | 340:28d1f895c6fe | 8244 | |
| mbed_official | 340:28d1f895c6fe | 8245 | #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */ |
| mbed_official | 340:28d1f895c6fe | 8246 | #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8247 | #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8248 | |
| mbed_official | 340:28d1f895c6fe | 8249 | #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */ |
| mbed_official | 340:28d1f895c6fe | 8250 | #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8251 | #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8252 | #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8253 | #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8254 | |
| mbed_official | 340:28d1f895c6fe | 8255 | #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */ |
| mbed_official | 340:28d1f895c6fe | 8256 | #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8257 | #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8258 | #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8259 | #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8260 | |
| mbed_official | 340:28d1f895c6fe | 8261 | #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */ |
| mbed_official | 340:28d1f895c6fe | 8262 | #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8263 | #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8264 | #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8265 | #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8266 | |
| mbed_official | 340:28d1f895c6fe | 8267 | /******************** Bit definition for OTG register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8268 | |
| mbed_official | 340:28d1f895c6fe | 8269 | #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */ |
| mbed_official | 340:28d1f895c6fe | 8270 | #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8271 | #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8272 | #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8273 | #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8274 | #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */ |
| mbed_official | 340:28d1f895c6fe | 8275 | |
| mbed_official | 340:28d1f895c6fe | 8276 | #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */ |
| mbed_official | 340:28d1f895c6fe | 8277 | #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8278 | #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8279 | |
| mbed_official | 340:28d1f895c6fe | 8280 | #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */ |
| mbed_official | 340:28d1f895c6fe | 8281 | #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8282 | #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8283 | #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8284 | #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8285 | |
| mbed_official | 340:28d1f895c6fe | 8286 | #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */ |
| mbed_official | 340:28d1f895c6fe | 8287 | #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8288 | #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8289 | #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8290 | #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8291 | |
| mbed_official | 340:28d1f895c6fe | 8292 | #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */ |
| mbed_official | 340:28d1f895c6fe | 8293 | #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8294 | #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8295 | #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8296 | #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8297 | |
| mbed_official | 340:28d1f895c6fe | 8298 | /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8299 | #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */ |
| mbed_official | 340:28d1f895c6fe | 8300 | |
| mbed_official | 340:28d1f895c6fe | 8301 | /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8302 | #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */ |
| mbed_official | 340:28d1f895c6fe | 8303 | |
| mbed_official | 340:28d1f895c6fe | 8304 | /******************** Bit definition for OTG register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8305 | #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */ |
| mbed_official | 340:28d1f895c6fe | 8306 | #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */ |
| mbed_official | 340:28d1f895c6fe | 8307 | #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */ |
| mbed_official | 340:28d1f895c6fe | 8308 | #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */ |
| mbed_official | 340:28d1f895c6fe | 8309 | |
| mbed_official | 340:28d1f895c6fe | 8310 | /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8311 | #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */ |
| mbed_official | 340:28d1f895c6fe | 8312 | |
| mbed_official | 340:28d1f895c6fe | 8313 | /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8314 | #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */ |
| mbed_official | 340:28d1f895c6fe | 8315 | |
| mbed_official | 340:28d1f895c6fe | 8316 | #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */ |
| mbed_official | 340:28d1f895c6fe | 8317 | #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8318 | #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8319 | #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8320 | #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8321 | #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8322 | #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8323 | #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8324 | #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 8325 | |
| mbed_official | 340:28d1f895c6fe | 8326 | #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */ |
| mbed_official | 340:28d1f895c6fe | 8327 | #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8328 | #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8329 | #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8330 | #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8331 | #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8332 | #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8333 | #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8334 | |
| mbed_official | 340:28d1f895c6fe | 8335 | /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8336 | #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */ |
| mbed_official | 340:28d1f895c6fe | 8337 | #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */ |
| mbed_official | 340:28d1f895c6fe | 8338 | |
| mbed_official | 340:28d1f895c6fe | 8339 | #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */ |
| mbed_official | 340:28d1f895c6fe | 8340 | #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8341 | #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8342 | #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8343 | #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8344 | #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8345 | #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8346 | #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8347 | #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 8348 | #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 8349 | #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */ |
| mbed_official | 340:28d1f895c6fe | 8350 | |
| mbed_official | 340:28d1f895c6fe | 8351 | #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */ |
| mbed_official | 340:28d1f895c6fe | 8352 | #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8353 | #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8354 | #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8355 | #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8356 | #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8357 | #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8358 | #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8359 | #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */ |
| mbed_official | 340:28d1f895c6fe | 8360 | #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */ |
| mbed_official | 340:28d1f895c6fe | 8361 | #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */ |
| mbed_official | 340:28d1f895c6fe | 8362 | |
| mbed_official | 340:28d1f895c6fe | 8363 | /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8364 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */ |
| mbed_official | 340:28d1f895c6fe | 8365 | |
| mbed_official | 340:28d1f895c6fe | 8366 | /******************** Bit definition forUSB_OTG_DEACHINT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8367 | #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */ |
| mbed_official | 340:28d1f895c6fe | 8368 | #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */ |
| mbed_official | 340:28d1f895c6fe | 8369 | |
| mbed_official | 340:28d1f895c6fe | 8370 | /******************** Bit definition forUSB_OTG_GCCFG register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8371 | #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */ |
| mbed_official | 340:28d1f895c6fe | 8372 | #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */ |
| mbed_official | 340:28d1f895c6fe | 8373 | #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */ |
| mbed_official | 340:28d1f895c6fe | 8374 | #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */ |
| mbed_official | 340:28d1f895c6fe | 8375 | #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */ |
| mbed_official | 340:28d1f895c6fe | 8376 | #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */ |
| mbed_official | 340:28d1f895c6fe | 8377 | |
| mbed_official | 340:28d1f895c6fe | 8378 | /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8379 | #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */ |
| mbed_official | 340:28d1f895c6fe | 8380 | #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */ |
| mbed_official | 340:28d1f895c6fe | 8381 | |
| mbed_official | 340:28d1f895c6fe | 8382 | /******************** Bit definition forUSB_OTG_CID register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8383 | #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */ |
| mbed_official | 340:28d1f895c6fe | 8384 | |
| mbed_official | 340:28d1f895c6fe | 8385 | /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8386 | #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8387 | #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8388 | #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */ |
| mbed_official | 340:28d1f895c6fe | 8389 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ |
| mbed_official | 340:28d1f895c6fe | 8390 | #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ |
| mbed_official | 340:28d1f895c6fe | 8391 | #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ |
| mbed_official | 340:28d1f895c6fe | 8392 | #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */ |
| mbed_official | 340:28d1f895c6fe | 8393 | #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8394 | #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8395 | |
| mbed_official | 340:28d1f895c6fe | 8396 | /******************** Bit definition forUSB_OTG_HPRT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8397 | #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */ |
| mbed_official | 340:28d1f895c6fe | 8398 | #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */ |
| mbed_official | 340:28d1f895c6fe | 8399 | #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */ |
| mbed_official | 340:28d1f895c6fe | 8400 | #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */ |
| mbed_official | 340:28d1f895c6fe | 8401 | #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */ |
| mbed_official | 340:28d1f895c6fe | 8402 | #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */ |
| mbed_official | 340:28d1f895c6fe | 8403 | #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */ |
| mbed_official | 340:28d1f895c6fe | 8404 | #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */ |
| mbed_official | 340:28d1f895c6fe | 8405 | #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */ |
| mbed_official | 340:28d1f895c6fe | 8406 | |
| mbed_official | 340:28d1f895c6fe | 8407 | #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */ |
| mbed_official | 340:28d1f895c6fe | 8408 | #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8409 | #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8410 | #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */ |
| mbed_official | 340:28d1f895c6fe | 8411 | |
| mbed_official | 340:28d1f895c6fe | 8412 | #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */ |
| mbed_official | 340:28d1f895c6fe | 8413 | #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8414 | #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8415 | #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8416 | #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8417 | |
| mbed_official | 340:28d1f895c6fe | 8418 | #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */ |
| mbed_official | 340:28d1f895c6fe | 8419 | #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8420 | #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8421 | |
| mbed_official | 340:28d1f895c6fe | 8422 | /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8423 | #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8424 | #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8425 | #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */ |
| mbed_official | 340:28d1f895c6fe | 8426 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ |
| mbed_official | 340:28d1f895c6fe | 8427 | #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ |
| mbed_official | 340:28d1f895c6fe | 8428 | #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ |
| mbed_official | 340:28d1f895c6fe | 8429 | #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */ |
| mbed_official | 340:28d1f895c6fe | 8430 | #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8431 | #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8432 | #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8433 | #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8434 | |
| mbed_official | 340:28d1f895c6fe | 8435 | /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8436 | #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */ |
| mbed_official | 340:28d1f895c6fe | 8437 | #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */ |
| mbed_official | 340:28d1f895c6fe | 8438 | |
| mbed_official | 340:28d1f895c6fe | 8439 | /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8440 | #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ |
| mbed_official | 340:28d1f895c6fe | 8441 | #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */ |
| mbed_official | 340:28d1f895c6fe | 8442 | #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */ |
| mbed_official | 340:28d1f895c6fe | 8443 | #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */ |
| mbed_official | 340:28d1f895c6fe | 8444 | |
| mbed_official | 340:28d1f895c6fe | 8445 | #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ |
| mbed_official | 340:28d1f895c6fe | 8446 | #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8447 | #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8448 | #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */ |
| mbed_official | 340:28d1f895c6fe | 8449 | |
| mbed_official | 340:28d1f895c6fe | 8450 | #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */ |
| mbed_official | 340:28d1f895c6fe | 8451 | #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8452 | #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8453 | #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8454 | #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8455 | #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */ |
| mbed_official | 340:28d1f895c6fe | 8456 | #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */ |
| mbed_official | 340:28d1f895c6fe | 8457 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */ |
| mbed_official | 340:28d1f895c6fe | 8458 | #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */ |
| mbed_official | 340:28d1f895c6fe | 8459 | #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */ |
| mbed_official | 340:28d1f895c6fe | 8460 | #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */ |
| mbed_official | 340:28d1f895c6fe | 8461 | |
| mbed_official | 340:28d1f895c6fe | 8462 | /******************** Bit definition forUSB_OTG_HCCHAR register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8463 | #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ |
| mbed_official | 340:28d1f895c6fe | 8464 | |
| mbed_official | 340:28d1f895c6fe | 8465 | #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */ |
| mbed_official | 340:28d1f895c6fe | 8466 | #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8467 | #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8468 | #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8469 | #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8470 | #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */ |
| mbed_official | 340:28d1f895c6fe | 8471 | #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */ |
| mbed_official | 340:28d1f895c6fe | 8472 | |
| mbed_official | 340:28d1f895c6fe | 8473 | #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ |
| mbed_official | 340:28d1f895c6fe | 8474 | #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8475 | #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8476 | |
| mbed_official | 340:28d1f895c6fe | 8477 | #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */ |
| mbed_official | 340:28d1f895c6fe | 8478 | #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8479 | #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8480 | |
| mbed_official | 340:28d1f895c6fe | 8481 | #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */ |
| mbed_official | 340:28d1f895c6fe | 8482 | #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8483 | #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8484 | #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8485 | #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8486 | #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8487 | #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8488 | #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8489 | #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */ |
| mbed_official | 340:28d1f895c6fe | 8490 | #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */ |
| mbed_official | 340:28d1f895c6fe | 8491 | #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */ |
| mbed_official | 340:28d1f895c6fe | 8492 | |
| mbed_official | 340:28d1f895c6fe | 8493 | /******************** Bit definition forUSB_OTG_HCSPLT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8494 | |
| mbed_official | 340:28d1f895c6fe | 8495 | #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */ |
| mbed_official | 340:28d1f895c6fe | 8496 | #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8497 | #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8498 | #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8499 | #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8500 | #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8501 | #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8502 | #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8503 | |
| mbed_official | 340:28d1f895c6fe | 8504 | #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */ |
| mbed_official | 340:28d1f895c6fe | 8505 | #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8506 | #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8507 | #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */ |
| mbed_official | 340:28d1f895c6fe | 8508 | #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */ |
| mbed_official | 340:28d1f895c6fe | 8509 | #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */ |
| mbed_official | 340:28d1f895c6fe | 8510 | #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */ |
| mbed_official | 340:28d1f895c6fe | 8511 | #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */ |
| mbed_official | 340:28d1f895c6fe | 8512 | |
| mbed_official | 340:28d1f895c6fe | 8513 | #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */ |
| mbed_official | 340:28d1f895c6fe | 8514 | #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8515 | #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8516 | #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */ |
| mbed_official | 340:28d1f895c6fe | 8517 | #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */ |
| mbed_official | 340:28d1f895c6fe | 8518 | |
| mbed_official | 340:28d1f895c6fe | 8519 | /******************** Bit definition forUSB_OTG_HCINT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8520 | #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */ |
| mbed_official | 340:28d1f895c6fe | 8521 | #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */ |
| mbed_official | 340:28d1f895c6fe | 8522 | #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */ |
| mbed_official | 340:28d1f895c6fe | 8523 | #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8524 | #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8525 | #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8526 | #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8527 | #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */ |
| mbed_official | 340:28d1f895c6fe | 8528 | #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */ |
| mbed_official | 340:28d1f895c6fe | 8529 | #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */ |
| mbed_official | 340:28d1f895c6fe | 8530 | #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */ |
| mbed_official | 340:28d1f895c6fe | 8531 | |
| mbed_official | 340:28d1f895c6fe | 8532 | /******************** Bit definition forUSB_OTG_DIEPINT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8533 | #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8534 | #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8535 | #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */ |
| mbed_official | 340:28d1f895c6fe | 8536 | #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */ |
| mbed_official | 340:28d1f895c6fe | 8537 | #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */ |
| mbed_official | 340:28d1f895c6fe | 8538 | #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */ |
| mbed_official | 340:28d1f895c6fe | 8539 | #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */ |
| mbed_official | 340:28d1f895c6fe | 8540 | #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8541 | #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */ |
| mbed_official | 340:28d1f895c6fe | 8542 | #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8543 | #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8544 | |
| mbed_official | 340:28d1f895c6fe | 8545 | /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8546 | #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */ |
| mbed_official | 340:28d1f895c6fe | 8547 | #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */ |
| mbed_official | 340:28d1f895c6fe | 8548 | #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */ |
| mbed_official | 340:28d1f895c6fe | 8549 | #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8550 | #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8551 | #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8552 | #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */ |
| mbed_official | 340:28d1f895c6fe | 8553 | #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */ |
| mbed_official | 340:28d1f895c6fe | 8554 | #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */ |
| mbed_official | 340:28d1f895c6fe | 8555 | #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */ |
| mbed_official | 340:28d1f895c6fe | 8556 | #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */ |
| mbed_official | 340:28d1f895c6fe | 8557 | |
| mbed_official | 340:28d1f895c6fe | 8558 | /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8559 | |
| mbed_official | 340:28d1f895c6fe | 8560 | #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ |
| mbed_official | 340:28d1f895c6fe | 8561 | #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ |
| mbed_official | 340:28d1f895c6fe | 8562 | #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */ |
| mbed_official | 340:28d1f895c6fe | 8563 | /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8564 | #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ |
| mbed_official | 340:28d1f895c6fe | 8565 | #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ |
| mbed_official | 340:28d1f895c6fe | 8566 | #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */ |
| mbed_official | 340:28d1f895c6fe | 8567 | #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */ |
| mbed_official | 340:28d1f895c6fe | 8568 | #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8569 | #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8570 | |
| mbed_official | 340:28d1f895c6fe | 8571 | /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8572 | #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */ |
| mbed_official | 340:28d1f895c6fe | 8573 | |
| mbed_official | 340:28d1f895c6fe | 8574 | /******************** Bit definition forUSB_OTG_HCDMA register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8575 | #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */ |
| mbed_official | 340:28d1f895c6fe | 8576 | |
| mbed_official | 340:28d1f895c6fe | 8577 | /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8578 | #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */ |
| mbed_official | 340:28d1f895c6fe | 8579 | |
| mbed_official | 340:28d1f895c6fe | 8580 | /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8581 | #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */ |
| mbed_official | 340:28d1f895c6fe | 8582 | #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */ |
| mbed_official | 340:28d1f895c6fe | 8583 | |
| mbed_official | 340:28d1f895c6fe | 8584 | /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8585 | |
| mbed_official | 340:28d1f895c6fe | 8586 | #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8587 | #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */ |
| mbed_official | 340:28d1f895c6fe | 8588 | #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */ |
| mbed_official | 340:28d1f895c6fe | 8589 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */ |
| mbed_official | 340:28d1f895c6fe | 8590 | #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */ |
| mbed_official | 340:28d1f895c6fe | 8591 | #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ |
| mbed_official | 340:28d1f895c6fe | 8592 | #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8593 | #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8594 | #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */ |
| mbed_official | 340:28d1f895c6fe | 8595 | #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */ |
| mbed_official | 340:28d1f895c6fe | 8596 | #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */ |
| mbed_official | 340:28d1f895c6fe | 8597 | #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */ |
| mbed_official | 340:28d1f895c6fe | 8598 | #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */ |
| mbed_official | 340:28d1f895c6fe | 8599 | #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */ |
| mbed_official | 340:28d1f895c6fe | 8600 | |
| mbed_official | 340:28d1f895c6fe | 8601 | /******************** Bit definition forUSB_OTG_DOEPINT register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8602 | #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8603 | #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8604 | #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */ |
| mbed_official | 340:28d1f895c6fe | 8605 | #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */ |
| mbed_official | 340:28d1f895c6fe | 8606 | #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */ |
| mbed_official | 340:28d1f895c6fe | 8607 | #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */ |
| mbed_official | 340:28d1f895c6fe | 8608 | |
| mbed_official | 340:28d1f895c6fe | 8609 | /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8610 | |
| mbed_official | 340:28d1f895c6fe | 8611 | #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ |
| mbed_official | 340:28d1f895c6fe | 8612 | #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ |
| mbed_official | 340:28d1f895c6fe | 8613 | |
| mbed_official | 340:28d1f895c6fe | 8614 | #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */ |
| mbed_official | 340:28d1f895c6fe | 8615 | #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8616 | #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8617 | |
| mbed_official | 340:28d1f895c6fe | 8618 | /******************** Bit definition for PCGCCTL register ********************/ |
| mbed_official | 340:28d1f895c6fe | 8619 | #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */ |
| mbed_official | 340:28d1f895c6fe | 8620 | #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 340:28d1f895c6fe | 8621 | #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 340:28d1f895c6fe | 8622 | |
| mbed_official | 340:28d1f895c6fe | 8623 | |
| mbed_official | 340:28d1f895c6fe | 8624 | /** |
| mbed_official | 340:28d1f895c6fe | 8625 | * @} |
| mbed_official | 340:28d1f895c6fe | 8626 | */ |
| mbed_official | 340:28d1f895c6fe | 8627 | |
| mbed_official | 340:28d1f895c6fe | 8628 | /** |
| mbed_official | 340:28d1f895c6fe | 8629 | * @} |
| mbed_official | 340:28d1f895c6fe | 8630 | */ |
| mbed_official | 340:28d1f895c6fe | 8631 | |
| mbed_official | 340:28d1f895c6fe | 8632 | /** @addtogroup Exported_macros |
| mbed_official | 340:28d1f895c6fe | 8633 | * @{ |
| mbed_official | 340:28d1f895c6fe | 8634 | */ |
| mbed_official | 340:28d1f895c6fe | 8635 | |
| mbed_official | 340:28d1f895c6fe | 8636 | /******************************* ADC Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8637 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
| mbed_official | 340:28d1f895c6fe | 8638 | ((INSTANCE) == ADC2) || \ |
| mbed_official | 340:28d1f895c6fe | 8639 | ((INSTANCE) == ADC3)) |
| mbed_official | 340:28d1f895c6fe | 8640 | |
| mbed_official | 340:28d1f895c6fe | 8641 | /******************************* CAN Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8642 | #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \ |
| mbed_official | 340:28d1f895c6fe | 8643 | ((INSTANCE) == CAN2)) |
| mbed_official | 340:28d1f895c6fe | 8644 | |
| mbed_official | 340:28d1f895c6fe | 8645 | /******************************* CRC Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8646 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| mbed_official | 340:28d1f895c6fe | 8647 | |
| mbed_official | 340:28d1f895c6fe | 8648 | /******************************* DAC Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8649 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) |
| mbed_official | 340:28d1f895c6fe | 8650 | |
| mbed_official | 340:28d1f895c6fe | 8651 | /******************************* DCMI Instances *******************************/ |
| mbed_official | 340:28d1f895c6fe | 8652 | #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI) |
| mbed_official | 340:28d1f895c6fe | 8653 | |
| mbed_official | 340:28d1f895c6fe | 8654 | /******************************* DMA2D Instances *******************************/ |
| mbed_official | 340:28d1f895c6fe | 8655 | #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D) |
| mbed_official | 340:28d1f895c6fe | 8656 | |
| mbed_official | 340:28d1f895c6fe | 8657 | /******************************** DMA Instances *******************************/ |
| mbed_official | 340:28d1f895c6fe | 8658 | #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \ |
| mbed_official | 340:28d1f895c6fe | 8659 | ((INSTANCE) == DMA1_Stream1) || \ |
| mbed_official | 340:28d1f895c6fe | 8660 | ((INSTANCE) == DMA1_Stream2) || \ |
| mbed_official | 340:28d1f895c6fe | 8661 | ((INSTANCE) == DMA1_Stream3) || \ |
| mbed_official | 340:28d1f895c6fe | 8662 | ((INSTANCE) == DMA1_Stream4) || \ |
| mbed_official | 340:28d1f895c6fe | 8663 | ((INSTANCE) == DMA1_Stream5) || \ |
| mbed_official | 340:28d1f895c6fe | 8664 | ((INSTANCE) == DMA1_Stream6) || \ |
| mbed_official | 340:28d1f895c6fe | 8665 | ((INSTANCE) == DMA1_Stream7) || \ |
| mbed_official | 340:28d1f895c6fe | 8666 | ((INSTANCE) == DMA2_Stream0) || \ |
| mbed_official | 340:28d1f895c6fe | 8667 | ((INSTANCE) == DMA2_Stream1) || \ |
| mbed_official | 340:28d1f895c6fe | 8668 | ((INSTANCE) == DMA2_Stream2) || \ |
| mbed_official | 340:28d1f895c6fe | 8669 | ((INSTANCE) == DMA2_Stream3) || \ |
| mbed_official | 340:28d1f895c6fe | 8670 | ((INSTANCE) == DMA2_Stream4) || \ |
| mbed_official | 340:28d1f895c6fe | 8671 | ((INSTANCE) == DMA2_Stream5) || \ |
| mbed_official | 340:28d1f895c6fe | 8672 | ((INSTANCE) == DMA2_Stream6) || \ |
| mbed_official | 340:28d1f895c6fe | 8673 | ((INSTANCE) == DMA2_Stream7)) |
| mbed_official | 340:28d1f895c6fe | 8674 | |
| mbed_official | 340:28d1f895c6fe | 8675 | /******************************* GPIO Instances *******************************/ |
| mbed_official | 340:28d1f895c6fe | 8676 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| mbed_official | 340:28d1f895c6fe | 8677 | ((INSTANCE) == GPIOB) || \ |
| mbed_official | 340:28d1f895c6fe | 8678 | ((INSTANCE) == GPIOC) || \ |
| mbed_official | 340:28d1f895c6fe | 8679 | ((INSTANCE) == GPIOD) || \ |
| mbed_official | 340:28d1f895c6fe | 8680 | ((INSTANCE) == GPIOE) || \ |
| mbed_official | 340:28d1f895c6fe | 8681 | ((INSTANCE) == GPIOF) || \ |
| mbed_official | 340:28d1f895c6fe | 8682 | ((INSTANCE) == GPIOG) || \ |
| mbed_official | 340:28d1f895c6fe | 8683 | ((INSTANCE) == GPIOH) || \ |
| mbed_official | 340:28d1f895c6fe | 8684 | ((INSTANCE) == GPIOI) || \ |
| mbed_official | 340:28d1f895c6fe | 8685 | ((INSTANCE) == GPIOJ) || \ |
| mbed_official | 340:28d1f895c6fe | 8686 | ((INSTANCE) == GPIOK)) |
| mbed_official | 340:28d1f895c6fe | 8687 | |
| mbed_official | 340:28d1f895c6fe | 8688 | /******************************** I2C Instances *******************************/ |
| mbed_official | 340:28d1f895c6fe | 8689 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| mbed_official | 340:28d1f895c6fe | 8690 | ((INSTANCE) == I2C2) || \ |
| mbed_official | 340:28d1f895c6fe | 8691 | ((INSTANCE) == I2C3)) |
| mbed_official | 340:28d1f895c6fe | 8692 | |
| mbed_official | 340:28d1f895c6fe | 8693 | /******************************** I2S Instances *******************************/ |
| mbed_official | 532:fe11edbda85c | 8694 | #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ |
| mbed_official | 532:fe11edbda85c | 8695 | ((INSTANCE) == SPI3)) |
| mbed_official | 340:28d1f895c6fe | 8696 | |
| mbed_official | 340:28d1f895c6fe | 8697 | /*************************** I2S Extended Instances ***************************/ |
| mbed_official | 532:fe11edbda85c | 8698 | #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ |
| mbed_official | 532:fe11edbda85c | 8699 | ((INSTANCE) == SPI3) || \ |
| mbed_official | 532:fe11edbda85c | 8700 | ((INSTANCE) == I2S2ext) || \ |
| mbed_official | 532:fe11edbda85c | 8701 | ((INSTANCE) == I2S3ext)) |
| mbed_official | 340:28d1f895c6fe | 8702 | |
| mbed_official | 340:28d1f895c6fe | 8703 | /****************************** LTDC Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8704 | #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| mbed_official | 340:28d1f895c6fe | 8705 | |
| mbed_official | 340:28d1f895c6fe | 8706 | /******************************* RNG Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8707 | #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| mbed_official | 340:28d1f895c6fe | 8708 | |
| mbed_official | 340:28d1f895c6fe | 8709 | /****************************** RTC Instances *********************************/ |
| mbed_official | 340:28d1f895c6fe | 8710 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| mbed_official | 340:28d1f895c6fe | 8711 | |
| mbed_official | 340:28d1f895c6fe | 8712 | /******************************* SAI Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8713 | #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \ |
| mbed_official | 340:28d1f895c6fe | 8714 | ((PERIPH) == SAI1_Block_B)) |
| mbed_official | 340:28d1f895c6fe | 8715 | |
| mbed_official | 340:28d1f895c6fe | 8716 | /******************************** SPI Instances *******************************/ |
| mbed_official | 340:28d1f895c6fe | 8717 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
| mbed_official | 340:28d1f895c6fe | 8718 | ((INSTANCE) == SPI2) || \ |
| mbed_official | 340:28d1f895c6fe | 8719 | ((INSTANCE) == SPI3) || \ |
| mbed_official | 340:28d1f895c6fe | 8720 | ((INSTANCE) == SPI4) || \ |
| mbed_official | 340:28d1f895c6fe | 8721 | ((INSTANCE) == SPI5) || \ |
| mbed_official | 340:28d1f895c6fe | 8722 | ((INSTANCE) == SPI6)) |
| mbed_official | 340:28d1f895c6fe | 8723 | |
| mbed_official | 340:28d1f895c6fe | 8724 | /*************************** SPI Extended Instances ***************************/ |
| mbed_official | 340:28d1f895c6fe | 8725 | #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \ |
| mbed_official | 340:28d1f895c6fe | 8726 | ((INSTANCE) == SPI2) || \ |
| mbed_official | 340:28d1f895c6fe | 8727 | ((INSTANCE) == SPI3) || \ |
| mbed_official | 340:28d1f895c6fe | 8728 | ((INSTANCE) == SPI4) || \ |
| mbed_official | 340:28d1f895c6fe | 8729 | ((INSTANCE) == SPI5) || \ |
| mbed_official | 340:28d1f895c6fe | 8730 | ((INSTANCE) == SPI6) || \ |
| mbed_official | 340:28d1f895c6fe | 8731 | ((INSTANCE) == I2S2ext) || \ |
| mbed_official | 340:28d1f895c6fe | 8732 | ((INSTANCE) == I2S3ext)) |
| mbed_official | 340:28d1f895c6fe | 8733 | |
| mbed_official | 340:28d1f895c6fe | 8734 | /****************** TIM Instances : All supported instances *******************/ |
| mbed_official | 340:28d1f895c6fe | 8735 | #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8736 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8737 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8738 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8739 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8740 | ((INSTANCE) == TIM6) || \ |
| mbed_official | 340:28d1f895c6fe | 8741 | ((INSTANCE) == TIM7) || \ |
| mbed_official | 340:28d1f895c6fe | 8742 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 340:28d1f895c6fe | 8743 | ((INSTANCE) == TIM9) || \ |
| mbed_official | 340:28d1f895c6fe | 8744 | ((INSTANCE) == TIM10) || \ |
| mbed_official | 340:28d1f895c6fe | 8745 | ((INSTANCE) == TIM11) || \ |
| mbed_official | 340:28d1f895c6fe | 8746 | ((INSTANCE) == TIM12) || \ |
| mbed_official | 340:28d1f895c6fe | 8747 | ((INSTANCE) == TIM13) || \ |
| mbed_official | 340:28d1f895c6fe | 8748 | ((INSTANCE) == TIM14)) |
| mbed_official | 340:28d1f895c6fe | 8749 | |
| mbed_official | 340:28d1f895c6fe | 8750 | /************* TIM Instances : at least 1 capture/compare channel *************/ |
| mbed_official | 340:28d1f895c6fe | 8751 | #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8752 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8753 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8754 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8755 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8756 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 340:28d1f895c6fe | 8757 | ((INSTANCE) == TIM9) || \ |
| mbed_official | 340:28d1f895c6fe | 8758 | ((INSTANCE) == TIM10) || \ |
| mbed_official | 340:28d1f895c6fe | 8759 | ((INSTANCE) == TIM11) || \ |
| mbed_official | 340:28d1f895c6fe | 8760 | ((INSTANCE) == TIM12) || \ |
| mbed_official | 340:28d1f895c6fe | 8761 | ((INSTANCE) == TIM13) || \ |
| mbed_official | 340:28d1f895c6fe | 8762 | ((INSTANCE) == TIM14)) |
| mbed_official | 340:28d1f895c6fe | 8763 | |
| mbed_official | 340:28d1f895c6fe | 8764 | /************ TIM Instances : at least 2 capture/compare channels *************/ |
| mbed_official | 340:28d1f895c6fe | 8765 | #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8766 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8767 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8768 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8769 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8770 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 340:28d1f895c6fe | 8771 | ((INSTANCE) == TIM9) || \ |
| mbed_official | 340:28d1f895c6fe | 8772 | ((INSTANCE) == TIM12)) |
| mbed_official | 340:28d1f895c6fe | 8773 | |
| mbed_official | 340:28d1f895c6fe | 8774 | /************ TIM Instances : at least 3 capture/compare channels *************/ |
| mbed_official | 340:28d1f895c6fe | 8775 | #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8776 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8777 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8778 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8779 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8780 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8781 | |
| mbed_official | 340:28d1f895c6fe | 8782 | /************ TIM Instances : at least 4 capture/compare channels *************/ |
| mbed_official | 340:28d1f895c6fe | 8783 | #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8784 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8785 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8786 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8787 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8788 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8789 | |
| mbed_official | 340:28d1f895c6fe | 8790 | /******************** TIM Instances : Advanced-control timers *****************/ |
| mbed_official | 340:28d1f895c6fe | 8791 | #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8792 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8793 | |
| mbed_official | 340:28d1f895c6fe | 8794 | /******************* TIM Instances : Timer input XOR function *****************/ |
| mbed_official | 340:28d1f895c6fe | 8795 | #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8796 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8797 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8798 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8799 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8800 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8801 | |
| mbed_official | 340:28d1f895c6fe | 8802 | /****************** TIM Instances : DMA requests generation (UDE) *************/ |
| mbed_official | 340:28d1f895c6fe | 8803 | #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8804 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8805 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8806 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8807 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8808 | ((INSTANCE) == TIM6) || \ |
| mbed_official | 340:28d1f895c6fe | 8809 | ((INSTANCE) == TIM7) || \ |
| mbed_official | 340:28d1f895c6fe | 8810 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8811 | |
| mbed_official | 340:28d1f895c6fe | 8812 | /************ TIM Instances : DMA requests generation (CCxDE) *****************/ |
| mbed_official | 340:28d1f895c6fe | 8813 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8814 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8815 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8816 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8817 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8818 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8819 | |
| mbed_official | 340:28d1f895c6fe | 8820 | /************ TIM Instances : DMA requests generation (COMDE) *****************/ |
| mbed_official | 340:28d1f895c6fe | 8821 | #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8822 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8823 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8824 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8825 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8826 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8827 | |
| mbed_official | 340:28d1f895c6fe | 8828 | /******************** TIM Instances : DMA burst feature ***********************/ |
| mbed_official | 340:28d1f895c6fe | 8829 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8830 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8831 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8832 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8833 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8834 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8835 | |
| mbed_official | 340:28d1f895c6fe | 8836 | /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/ |
| mbed_official | 340:28d1f895c6fe | 8837 | #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8838 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8839 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8840 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8841 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8842 | ((INSTANCE) == TIM6) || \ |
| mbed_official | 340:28d1f895c6fe | 8843 | ((INSTANCE) == TIM7) || \ |
| mbed_official | 340:28d1f895c6fe | 8844 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 340:28d1f895c6fe | 8845 | ((INSTANCE) == TIM9) || \ |
| mbed_official | 340:28d1f895c6fe | 8846 | ((INSTANCE) == TIM12)) |
| mbed_official | 340:28d1f895c6fe | 8847 | |
| mbed_official | 340:28d1f895c6fe | 8848 | /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ |
| mbed_official | 340:28d1f895c6fe | 8849 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8850 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8851 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8852 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8853 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8854 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 340:28d1f895c6fe | 8855 | ((INSTANCE) == TIM9) || \ |
| mbed_official | 340:28d1f895c6fe | 8856 | ((INSTANCE) == TIM12)) |
| mbed_official | 340:28d1f895c6fe | 8857 | |
| mbed_official | 340:28d1f895c6fe | 8858 | /********************** TIM Instances : 32 bit Counter ************************/ |
| mbed_official | 340:28d1f895c6fe | 8859 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8860 | ((INSTANCE) == TIM5)) |
| mbed_official | 340:28d1f895c6fe | 8861 | |
| mbed_official | 340:28d1f895c6fe | 8862 | /***************** TIM Instances : external trigger input availabe ************/ |
| mbed_official | 340:28d1f895c6fe | 8863 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 340:28d1f895c6fe | 8864 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8865 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 340:28d1f895c6fe | 8866 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 340:28d1f895c6fe | 8867 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8868 | ((INSTANCE) == TIM8)) |
| mbed_official | 340:28d1f895c6fe | 8869 | |
| mbed_official | 340:28d1f895c6fe | 8870 | /****************** TIM Instances : remapping capability **********************/ |
| mbed_official | 340:28d1f895c6fe | 8871 | #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
| mbed_official | 340:28d1f895c6fe | 8872 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 340:28d1f895c6fe | 8873 | ((INSTANCE) == TIM11)) |
| mbed_official | 340:28d1f895c6fe | 8874 | |
| mbed_official | 340:28d1f895c6fe | 8875 | /******************* TIM Instances : output(s) available **********************/ |
| mbed_official | 340:28d1f895c6fe | 8876 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
| mbed_official | 340:28d1f895c6fe | 8877 | ((((INSTANCE) == TIM1) && \ |
| mbed_official | 340:28d1f895c6fe | 8878 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8879 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 8880 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 340:28d1f895c6fe | 8881 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 340:28d1f895c6fe | 8882 | || \ |
| mbed_official | 340:28d1f895c6fe | 8883 | (((INSTANCE) == TIM2) && \ |
| mbed_official | 340:28d1f895c6fe | 8884 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8885 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 8886 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 340:28d1f895c6fe | 8887 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 340:28d1f895c6fe | 8888 | || \ |
| mbed_official | 340:28d1f895c6fe | 8889 | (((INSTANCE) == TIM3) && \ |
| mbed_official | 340:28d1f895c6fe | 8890 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8891 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 8892 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 340:28d1f895c6fe | 8893 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 340:28d1f895c6fe | 8894 | || \ |
| mbed_official | 340:28d1f895c6fe | 8895 | (((INSTANCE) == TIM4) && \ |
| mbed_official | 340:28d1f895c6fe | 8896 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8897 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 8898 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 340:28d1f895c6fe | 8899 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 340:28d1f895c6fe | 8900 | || \ |
| mbed_official | 340:28d1f895c6fe | 8901 | (((INSTANCE) == TIM5) && \ |
| mbed_official | 340:28d1f895c6fe | 8902 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8903 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 8904 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 340:28d1f895c6fe | 8905 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 340:28d1f895c6fe | 8906 | || \ |
| mbed_official | 340:28d1f895c6fe | 8907 | (((INSTANCE) == TIM8) && \ |
| mbed_official | 340:28d1f895c6fe | 8908 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8909 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 8910 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 340:28d1f895c6fe | 8911 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 340:28d1f895c6fe | 8912 | || \ |
| mbed_official | 340:28d1f895c6fe | 8913 | (((INSTANCE) == TIM9) && \ |
| mbed_official | 340:28d1f895c6fe | 8914 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8915 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
| mbed_official | 340:28d1f895c6fe | 8916 | || \ |
| mbed_official | 340:28d1f895c6fe | 8917 | (((INSTANCE) == TIM10) && \ |
| mbed_official | 340:28d1f895c6fe | 8918 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| mbed_official | 340:28d1f895c6fe | 8919 | || \ |
| mbed_official | 340:28d1f895c6fe | 8920 | (((INSTANCE) == TIM11) && \ |
| mbed_official | 340:28d1f895c6fe | 8921 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| mbed_official | 340:28d1f895c6fe | 8922 | || \ |
| mbed_official | 340:28d1f895c6fe | 8923 | (((INSTANCE) == TIM12) && \ |
| mbed_official | 340:28d1f895c6fe | 8924 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8925 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
| mbed_official | 340:28d1f895c6fe | 8926 | || \ |
| mbed_official | 340:28d1f895c6fe | 8927 | (((INSTANCE) == TIM13) && \ |
| mbed_official | 340:28d1f895c6fe | 8928 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| mbed_official | 340:28d1f895c6fe | 8929 | || \ |
| mbed_official | 340:28d1f895c6fe | 8930 | (((INSTANCE) == TIM14) && \ |
| mbed_official | 340:28d1f895c6fe | 8931 | (((CHANNEL) == TIM_CHANNEL_1)))) |
| mbed_official | 340:28d1f895c6fe | 8932 | |
| mbed_official | 340:28d1f895c6fe | 8933 | /************ TIM Instances : complementary output(s) available ***************/ |
| mbed_official | 340:28d1f895c6fe | 8934 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
| mbed_official | 340:28d1f895c6fe | 8935 | ((((INSTANCE) == TIM1) && \ |
| mbed_official | 340:28d1f895c6fe | 8936 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8937 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 8938 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
| mbed_official | 340:28d1f895c6fe | 8939 | || \ |
| mbed_official | 340:28d1f895c6fe | 8940 | (((INSTANCE) == TIM8) && \ |
| mbed_official | 340:28d1f895c6fe | 8941 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 8942 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 8943 | ((CHANNEL) == TIM_CHANNEL_3)))) |
| mbed_official | 340:28d1f895c6fe | 8944 | |
| mbed_official | 340:28d1f895c6fe | 8945 | /******************** USART Instances : Synchronous mode **********************/ |
| mbed_official | 340:28d1f895c6fe | 8946 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 340:28d1f895c6fe | 8947 | ((INSTANCE) == USART2) || \ |
| mbed_official | 340:28d1f895c6fe | 8948 | ((INSTANCE) == USART3) || \ |
| mbed_official | 340:28d1f895c6fe | 8949 | ((INSTANCE) == USART6)) |
| mbed_official | 340:28d1f895c6fe | 8950 | |
| mbed_official | 340:28d1f895c6fe | 8951 | /******************** UART Instances : Asynchronous mode **********************/ |
| mbed_official | 340:28d1f895c6fe | 8952 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 340:28d1f895c6fe | 8953 | ((INSTANCE) == USART2) || \ |
| mbed_official | 340:28d1f895c6fe | 8954 | ((INSTANCE) == USART3) || \ |
| mbed_official | 340:28d1f895c6fe | 8955 | ((INSTANCE) == UART4) || \ |
| mbed_official | 340:28d1f895c6fe | 8956 | ((INSTANCE) == UART5) || \ |
| mbed_official | 340:28d1f895c6fe | 8957 | ((INSTANCE) == USART6) || \ |
| mbed_official | 340:28d1f895c6fe | 8958 | ((INSTANCE) == UART7) || \ |
| mbed_official | 340:28d1f895c6fe | 8959 | ((INSTANCE) == UART8)) |
| mbed_official | 340:28d1f895c6fe | 8960 | |
| mbed_official | 340:28d1f895c6fe | 8961 | /****************** UART Instances : Hardware Flow control ********************/ |
| mbed_official | 340:28d1f895c6fe | 8962 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 340:28d1f895c6fe | 8963 | ((INSTANCE) == USART2) || \ |
| mbed_official | 340:28d1f895c6fe | 8964 | ((INSTANCE) == USART3) || \ |
| mbed_official | 340:28d1f895c6fe | 8965 | ((INSTANCE) == USART6)) |
| mbed_official | 340:28d1f895c6fe | 8966 | |
| mbed_official | 340:28d1f895c6fe | 8967 | /********************* UART Instances : Smard card mode ***********************/ |
| mbed_official | 340:28d1f895c6fe | 8968 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 340:28d1f895c6fe | 8969 | ((INSTANCE) == USART2) || \ |
| mbed_official | 340:28d1f895c6fe | 8970 | ((INSTANCE) == USART3) || \ |
| mbed_official | 340:28d1f895c6fe | 8971 | ((INSTANCE) == USART6)) |
| mbed_official | 340:28d1f895c6fe | 8972 | |
| mbed_official | 340:28d1f895c6fe | 8973 | /*********************** UART Instances : IRDA mode ***************************/ |
| mbed_official | 340:28d1f895c6fe | 8974 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 340:28d1f895c6fe | 8975 | ((INSTANCE) == USART2) || \ |
| mbed_official | 340:28d1f895c6fe | 8976 | ((INSTANCE) == USART3) || \ |
| mbed_official | 340:28d1f895c6fe | 8977 | ((INSTANCE) == UART4) || \ |
| mbed_official | 340:28d1f895c6fe | 8978 | ((INSTANCE) == UART5) || \ |
| mbed_official | 340:28d1f895c6fe | 8979 | ((INSTANCE) == USART6) || \ |
| mbed_official | 340:28d1f895c6fe | 8980 | ((INSTANCE) == UART7) || \ |
| mbed_official | 340:28d1f895c6fe | 8981 | ((INSTANCE) == UART8)) |
| mbed_official | 340:28d1f895c6fe | 8982 | |
| mbed_official | 340:28d1f895c6fe | 8983 | /****************************** IWDG Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8984 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
| mbed_official | 340:28d1f895c6fe | 8985 | |
| mbed_official | 340:28d1f895c6fe | 8986 | /****************************** WWDG Instances ********************************/ |
| mbed_official | 340:28d1f895c6fe | 8987 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
| mbed_official | 340:28d1f895c6fe | 8988 | |
| mbed_official | 532:fe11edbda85c | 8989 | /****************************** SDIO Instances ********************************/ |
| mbed_official | 532:fe11edbda85c | 8990 | #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) |
| mbed_official | 532:fe11edbda85c | 8991 | |
| mbed_official | 532:fe11edbda85c | 8992 | /****************************** USB Exported Constants ************************/ |
| mbed_official | 532:fe11edbda85c | 8993 | #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8 |
| mbed_official | 532:fe11edbda85c | 8994 | #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */ |
| mbed_official | 532:fe11edbda85c | 8995 | #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */ |
| mbed_official | 532:fe11edbda85c | 8996 | #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */ |
| mbed_official | 532:fe11edbda85c | 8997 | |
| mbed_official | 532:fe11edbda85c | 8998 | #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12 |
| mbed_official | 532:fe11edbda85c | 8999 | #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */ |
| mbed_official | 532:fe11edbda85c | 9000 | #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */ |
| mbed_official | 532:fe11edbda85c | 9001 | #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */ |
| mbed_official | 532:fe11edbda85c | 9002 | |
| mbed_official | 340:28d1f895c6fe | 9003 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 9004 | /* For a painless codes migration between the STM32F4xx device product */ |
| mbed_official | 340:28d1f895c6fe | 9005 | /* lines, the aliases defined below are put in place to overcome the */ |
| mbed_official | 340:28d1f895c6fe | 9006 | /* differences in the interrupt handlers and IRQn definitions. */ |
| mbed_official | 340:28d1f895c6fe | 9007 | /* No need to update developed interrupt code when moving across */ |
| mbed_official | 340:28d1f895c6fe | 9008 | /* product lines within the same STM32F4 Family */ |
| mbed_official | 340:28d1f895c6fe | 9009 | /******************************************************************************/ |
| mbed_official | 340:28d1f895c6fe | 9010 | |
| mbed_official | 340:28d1f895c6fe | 9011 | /* Aliases for __IRQn */ |
| mbed_official | 340:28d1f895c6fe | 9012 | #define FSMC_IRQn FMC_IRQn |
| mbed_official | 340:28d1f895c6fe | 9013 | |
| mbed_official | 340:28d1f895c6fe | 9014 | /* Aliases for __IRQHandler */ |
| mbed_official | 340:28d1f895c6fe | 9015 | #define FSMC_IRQHandler FMC_IRQHandler |
| mbed_official | 340:28d1f895c6fe | 9016 | |
| mbed_official | 340:28d1f895c6fe | 9017 | /** |
| mbed_official | 340:28d1f895c6fe | 9018 | * @} |
| mbed_official | 340:28d1f895c6fe | 9019 | */ |
| mbed_official | 340:28d1f895c6fe | 9020 | |
| mbed_official | 340:28d1f895c6fe | 9021 | /** |
| mbed_official | 340:28d1f895c6fe | 9022 | * @} |
| mbed_official | 340:28d1f895c6fe | 9023 | */ |
| mbed_official | 340:28d1f895c6fe | 9024 | |
| mbed_official | 340:28d1f895c6fe | 9025 | /** |
| mbed_official | 340:28d1f895c6fe | 9026 | * @} |
| mbed_official | 340:28d1f895c6fe | 9027 | */ |
| mbed_official | 340:28d1f895c6fe | 9028 | |
| mbed_official | 340:28d1f895c6fe | 9029 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 9030 | } |
| mbed_official | 340:28d1f895c6fe | 9031 | #endif /* __cplusplus */ |
| mbed_official | 340:28d1f895c6fe | 9032 | |
| mbed_official | 340:28d1f895c6fe | 9033 | #endif /* __STM32F429xx_H */ |
| mbed_official | 340:28d1f895c6fe | 9034 | |
| mbed_official | 340:28d1f895c6fe | 9035 | |
| mbed_official | 340:28d1f895c6fe | 9036 | |
| mbed_official | 340:28d1f895c6fe | 9037 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |