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Modified version of the mbed library for use with the Nucleo boards.

Dependents: EEPROMWrite Full-Project

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h@630:825f75ca301e, 2015-09-28 (annotated)

Committer:: mbed_official
Date:: Mon Sep 28 10:45:10 2015 +0100
Revision:: 630:825f75ca301e
Parent:: 441:d2c15dda23c1

Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10

Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/

NUCLEO_F031K6 : Add new target

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_rcc.h
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	630:825f75ca301e	5	* @version V1.3.0
mbed_official	630:825f75ca301e	6	* @date 26-June-2015
mbed_official	340:28d1f895c6fe	7	* @brief Header file of RCC HAL module.
mbed_official	340:28d1f895c6fe	8	******************************************************************************
mbed_official	340:28d1f895c6fe	9	* @attention
mbed_official	340:28d1f895c6fe	10	*
mbed_official	630:825f75ca301e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	12	*
mbed_official	340:28d1f895c6fe	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	14	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	16	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	19	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	21	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	22	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	23	*
mbed_official	340:28d1f895c6fe	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	34	*
mbed_official	340:28d1f895c6fe	35	******************************************************************************
mbed_official	630:825f75ca301e	36	*/
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	340:28d1f895c6fe	39	#ifndef __STM32F0xx_HAL_RCC_H
mbed_official	340:28d1f895c6fe	40	#define __STM32F0xx_HAL_RCC_H
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	43	extern "C" {
mbed_official	340:28d1f895c6fe	44	#endif
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	47	#include "stm32f0xx_hal_def.h"
mbed_official	340:28d1f895c6fe	48
mbed_official	340:28d1f895c6fe	49	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	50	* @{
mbed_official	340:28d1f895c6fe	51	*/
mbed_official	340:28d1f895c6fe	52
mbed_official	340:28d1f895c6fe	53	/** @addtogroup RCC
mbed_official	340:28d1f895c6fe	54	* @{
mbed_official	630:825f75ca301e	55	*/
mbed_official	630:825f75ca301e	56
mbed_official	630:825f75ca301e	57	/** @addtogroup RCC_Private_Constants
mbed_official	630:825f75ca301e	58	* @{
mbed_official	630:825f75ca301e	59	*/
mbed_official	630:825f75ca301e	60
mbed_official	630:825f75ca301e	61	/** @defgroup RCC_Timeout RCC Timeout
mbed_official	630:825f75ca301e	62	* @{
mbed_official	630:825f75ca301e	63	*/
mbed_official	630:825f75ca301e	64
mbed_official	630:825f75ca301e	65	/* Disable Backup domain write protection state change timeout */
mbed_official	630:825f75ca301e	66	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	630:825f75ca301e	67	/* LSE state change timeout */
mbed_official	630:825f75ca301e	68	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
mbed_official	630:825f75ca301e	69	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	630:825f75ca301e	70	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	630:825f75ca301e	71	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	630:825f75ca301e	72	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	630:825f75ca301e	73	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	630:825f75ca301e	74	#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	630:825f75ca301e	75	#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	630:825f75ca301e	76
mbed_official	630:825f75ca301e	77	/**
mbed_official	630:825f75ca301e	78	* @}
mbed_official	630:825f75ca301e	79	*/
mbed_official	630:825f75ca301e	80
mbed_official	630:825f75ca301e	81	/** @defgroup RCC_Register_Offset Register offsets
mbed_official	630:825f75ca301e	82	* @{
mbed_official	630:825f75ca301e	83	*/
mbed_official	630:825f75ca301e	84	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	630:825f75ca301e	85	#define RCC_CR_OFFSET 0x00
mbed_official	630:825f75ca301e	86	#define RCC_CFGR_OFFSET 0x04
mbed_official	630:825f75ca301e	87	#define RCC_CIR_OFFSET 0x08
mbed_official	630:825f75ca301e	88	#define RCC_BDCR_OFFSET 0x20
mbed_official	630:825f75ca301e	89	#define RCC_CSR_OFFSET 0x24
mbed_official	630:825f75ca301e	90
mbed_official	630:825f75ca301e	91	/**
mbed_official	630:825f75ca301e	92	* @}
mbed_official	340:28d1f895c6fe	93	*/
mbed_official	340:28d1f895c6fe	94
mbed_official	630:825f75ca301e	95
mbed_official	630:825f75ca301e	96	/* CR register byte 2 (Bits[23:16]) base address */
mbed_official	630:825f75ca301e	97	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
mbed_official	630:825f75ca301e	98
mbed_official	630:825f75ca301e	99	/* CIR register byte 1 (Bits[15:8]) base address */
mbed_official	630:825f75ca301e	100	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
mbed_official	630:825f75ca301e	101
mbed_official	630:825f75ca301e	102	/* CIR register byte 2 (Bits[23:16]) base address */
mbed_official	630:825f75ca301e	103	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
mbed_official	630:825f75ca301e	104
mbed_official	630:825f75ca301e	105	/* Defines used for Flags */
mbed_official	630:825f75ca301e	106	#define CR_REG_INDEX ((uint8_t)1)
mbed_official	630:825f75ca301e	107	#define CR2_REG_INDEX 2
mbed_official	630:825f75ca301e	108	#define BDCR_REG_INDEX 3
mbed_official	630:825f75ca301e	109	#define CSR_REG_INDEX 4
mbed_official	630:825f75ca301e	110
mbed_official	630:825f75ca301e	111	/* Flags in the CFGR register */
mbed_official	630:825f75ca301e	112	#define RCC_CFGR_PLLMUL_BITNUMBER 18
mbed_official	630:825f75ca301e	113	#define RCC_CFGR_HPRE_BITNUMBER 4
mbed_official	630:825f75ca301e	114	#define RCC_CFGR_PPRE_BITNUMBER 8
mbed_official	630:825f75ca301e	115	/* Flags in the CFGR2 register */
mbed_official	630:825f75ca301e	116	#define RCC_CFGR2_PREDIV_BITNUMBER 0
mbed_official	630:825f75ca301e	117	/* Flags in the CR register */
mbed_official	630:825f75ca301e	118	#define RCC_CR_HSIRDY_BitNumber 1
mbed_official	630:825f75ca301e	119	#define RCC_CR_HSERDY_BitNumber 17
mbed_official	630:825f75ca301e	120	#define RCC_CR_PLLRDY_BitNumber 25
mbed_official	630:825f75ca301e	121	/* Flags in the CR2 register */
mbed_official	630:825f75ca301e	122	#define RCC_CR2_HSI14RDY_BitNumber 1
mbed_official	630:825f75ca301e	123	#define RCC_CR2_HSI48RDY_BitNumber 16
mbed_official	630:825f75ca301e	124	/* Flags in the BDCR register */
mbed_official	630:825f75ca301e	125	#define RCC_BDCR_LSERDY_BitNumber 1
mbed_official	630:825f75ca301e	126	/* Flags in the CSR register */
mbed_official	630:825f75ca301e	127	#define RCC_CSR_LSIRDY_BitNumber 1
mbed_official	630:825f75ca301e	128	#define RCC_CSR_V18PWRRSTF_BitNumber 23
mbed_official	630:825f75ca301e	129	#define RCC_CSR_RMVF_BitNumber 24
mbed_official	630:825f75ca301e	130	#define RCC_CSR_OBLRSTF_BitNumber 25
mbed_official	630:825f75ca301e	131	#define RCC_CSR_PINRSTF_BitNumber 26
mbed_official	630:825f75ca301e	132	#define RCC_CSR_PORRSTF_BitNumber 27
mbed_official	630:825f75ca301e	133	#define RCC_CSR_SFTRSTF_BitNumber 28
mbed_official	630:825f75ca301e	134	#define RCC_CSR_IWDGRSTF_BitNumber 29
mbed_official	630:825f75ca301e	135	#define RCC_CSR_WWDGRSTF_BitNumber 30
mbed_official	630:825f75ca301e	136	#define RCC_CSR_LPWRRSTF_BitNumber 31
mbed_official	630:825f75ca301e	137	/* Flags in the HSITRIM register */
mbed_official	630:825f75ca301e	138	#define RCC_CR_HSITRIM_BitNumber 3
mbed_official	630:825f75ca301e	139	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	630:825f75ca301e	140
mbed_official	630:825f75ca301e	141	/**
mbed_official	630:825f75ca301e	142	* @}
mbed_official	630:825f75ca301e	143	*/
mbed_official	630:825f75ca301e	144
mbed_official	630:825f75ca301e	145	/** @addtogroup RCC_Private_Macros
mbed_official	630:825f75ca301e	146	* @{
mbed_official	630:825f75ca301e	147	*/
mbed_official	630:825f75ca301e	148
mbed_official	630:825f75ca301e	149	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
mbed_official	630:825f75ca301e	150	((__HSE__) == RCC_HSE_BYPASS))
mbed_official	630:825f75ca301e	151	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
mbed_official	630:825f75ca301e	152	((__LSE__) == RCC_LSE_BYPASS))
mbed_official	630:825f75ca301e	153	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
mbed_official	630:825f75ca301e	154	#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) \|\| ((__HSI14__) == RCC_HSI14_ON) \|\| ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
mbed_official	630:825f75ca301e	155	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
mbed_official	630:825f75ca301e	156	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
mbed_official	630:825f75ca301e	157	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
mbed_official	630:825f75ca301e	158	((__PLL__) == RCC_PLL_ON))
mbed_official	630:825f75ca301e	159	#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) \|\| ((__PREDIV__) == RCC_PREDIV_DIV2) \|\| \
mbed_official	630:825f75ca301e	160	((__PREDIV__) == RCC_PREDIV_DIV3) \|\| ((__PREDIV__) == RCC_PREDIV_DIV4) \|\| \
mbed_official	630:825f75ca301e	161	((__PREDIV__) == RCC_PREDIV_DIV5) \|\| ((__PREDIV__) == RCC_PREDIV_DIV6) \|\| \
mbed_official	630:825f75ca301e	162	((__PREDIV__) == RCC_PREDIV_DIV7) \|\| ((__PREDIV__) == RCC_PREDIV_DIV8) \|\| \
mbed_official	630:825f75ca301e	163	((__PREDIV__) == RCC_PREDIV_DIV9) \|\| ((__PREDIV__) == RCC_PREDIV_DIV10) \|\| \
mbed_official	630:825f75ca301e	164	((__PREDIV__) == RCC_PREDIV_DIV11) \|\| ((__PREDIV__) == RCC_PREDIV_DIV12) \|\| \
mbed_official	630:825f75ca301e	165	((__PREDIV__) == RCC_PREDIV_DIV13) \|\| ((__PREDIV__) == RCC_PREDIV_DIV14) \|\| \
mbed_official	630:825f75ca301e	166	((__PREDIV__) == RCC_PREDIV_DIV15) \|\| ((__PREDIV__) == RCC_PREDIV_DIV16))
mbed_official	630:825f75ca301e	167	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
mbed_official	630:825f75ca301e	168	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
mbed_official	630:825f75ca301e	169	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
mbed_official	630:825f75ca301e	170	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
mbed_official	630:825f75ca301e	171	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
mbed_official	630:825f75ca301e	172	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
mbed_official	630:825f75ca301e	173	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
mbed_official	630:825f75ca301e	174	((__MUL__) == RCC_PLL_MUL16))
mbed_official	630:825f75ca301e	175	#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
mbed_official	630:825f75ca301e	176	(((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
mbed_official	630:825f75ca301e	177	(((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
mbed_official	630:825f75ca301e	178	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	630:825f75ca301e	179	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	630:825f75ca301e	180	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	630:825f75ca301e	181	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	630:825f75ca301e	182	((__HCLK__) == RCC_SYSCLK_DIV512))
mbed_official	630:825f75ca301e	183	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
mbed_official	630:825f75ca301e	184	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
mbed_official	630:825f75ca301e	185	((__PCLK__) == RCC_HCLK_DIV16))
mbed_official	630:825f75ca301e	186	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
mbed_official	630:825f75ca301e	187	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
mbed_official	630:825f75ca301e	188	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
mbed_official	630:825f75ca301e	189	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
mbed_official	630:825f75ca301e	190	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
mbed_official	630:825f75ca301e	191	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
mbed_official	630:825f75ca301e	192	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	630:825f75ca301e	193	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	630:825f75ca301e	194	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
mbed_official	630:825f75ca301e	195	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	196	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
mbed_official	630:825f75ca301e	197
mbed_official	630:825f75ca301e	198	/**
mbed_official	630:825f75ca301e	199	* @}
mbed_official	630:825f75ca301e	200	*/
mbed_official	630:825f75ca301e	201
mbed_official	630:825f75ca301e	202	/* Exported types ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	203
mbed_official	340:28d1f895c6fe	204	/** @defgroup RCC_Exported_Types RCC Exported Types
mbed_official	340:28d1f895c6fe	205	* @{
mbed_official	340:28d1f895c6fe	206	*/
mbed_official	340:28d1f895c6fe	207
mbed_official	630:825f75ca301e	208	/**
mbed_official	630:825f75ca301e	209	* @brief RCC PLL configuration structure definition
mbed_official	340:28d1f895c6fe	210	*/
mbed_official	340:28d1f895c6fe	211	typedef struct
mbed_official	340:28d1f895c6fe	212	{
mbed_official	630:825f75ca301e	213	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	630:825f75ca301e	214	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	340:28d1f895c6fe	215
mbed_official	630:825f75ca301e	216	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
mbed_official	630:825f75ca301e	217	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	340:28d1f895c6fe	218
mbed_official	630:825f75ca301e	219	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
mbed_official	630:825f75ca301e	220	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
mbed_official	630:825f75ca301e	221
mbed_official	630:825f75ca301e	222	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
mbed_official	630:825f75ca301e	223	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
mbed_official	340:28d1f895c6fe	224
mbed_official	630:825f75ca301e	225	} RCC_PLLInitTypeDef;
mbed_official	630:825f75ca301e	226
mbed_official	630:825f75ca301e	227	/**
mbed_official	630:825f75ca301e	228	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	340:28d1f895c6fe	229	*/
mbed_official	340:28d1f895c6fe	230	typedef struct
mbed_official	340:28d1f895c6fe	231	{
mbed_official	630:825f75ca301e	232	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	630:825f75ca301e	233	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	340:28d1f895c6fe	234
mbed_official	630:825f75ca301e	235	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	630:825f75ca301e	236	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	630:825f75ca301e	237
mbed_official	630:825f75ca301e	238	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	630:825f75ca301e	239	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	630:825f75ca301e	240
mbed_official	630:825f75ca301e	241	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	630:825f75ca301e	242	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	340:28d1f895c6fe	243
mbed_official	630:825f75ca301e	244	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	630:825f75ca301e	245	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	630:825f75ca301e	246
mbed_official	340:28d1f895c6fe	247	uint32_t HSI14State; /*!< The new state of the HSI14.
mbed_official	340:28d1f895c6fe	248	This parameter can be a value of @ref RCC_HSI14_Config */
mbed_official	340:28d1f895c6fe	249
mbed_official	340:28d1f895c6fe	250	uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
mbed_official	340:28d1f895c6fe	251	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	340:28d1f895c6fe	252
mbed_official	441:d2c15dda23c1	253	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
mbed_official	340:28d1f895c6fe	254	This parameter can be a value of @ref RCCEx_HSI48_Config */
mbed_official	340:28d1f895c6fe	255
mbed_official	630:825f75ca301e	256	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	630:825f75ca301e	257	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	340:28d1f895c6fe	258
mbed_official	630:825f75ca301e	259	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	340:28d1f895c6fe	260
mbed_official	630:825f75ca301e	261	} RCC_OscInitTypeDef;
mbed_official	630:825f75ca301e	262
mbed_official	340:28d1f895c6fe	263
mbed_official	630:825f75ca301e	264	/**
mbed_official	630:825f75ca301e	265	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	340:28d1f895c6fe	266	*/
mbed_official	340:28d1f895c6fe	267	typedef struct
mbed_official	340:28d1f895c6fe	268	{
mbed_official	630:825f75ca301e	269	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	630:825f75ca301e	270	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	630:825f75ca301e	271
mbed_official	630:825f75ca301e	272	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	630:825f75ca301e	273	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	340:28d1f895c6fe	274
mbed_official	630:825f75ca301e	275	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	630:825f75ca301e	276	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	630:825f75ca301e	277
mbed_official	630:825f75ca301e	278	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	630:825f75ca301e	279	This parameter can be a value of @ref RCC_APB1_Clock_Source */
mbed_official	630:825f75ca301e	280
mbed_official	630:825f75ca301e	281	} RCC_ClkInitTypeDef;
mbed_official	340:28d1f895c6fe	282
mbed_official	340:28d1f895c6fe	283	/**
mbed_official	340:28d1f895c6fe	284	* @}
mbed_official	340:28d1f895c6fe	285	*/
mbed_official	630:825f75ca301e	286
mbed_official	340:28d1f895c6fe	287	/* Exported constants --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	288	/** @defgroup RCC_Exported_Constants RCC Exported Constants
mbed_official	340:28d1f895c6fe	289	* @{
mbed_official	340:28d1f895c6fe	290	*/
mbed_official	340:28d1f895c6fe	291
mbed_official	630:825f75ca301e	292	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
mbed_official	340:28d1f895c6fe	293	* @{
mbed_official	340:28d1f895c6fe	294	*/
mbed_official	340:28d1f895c6fe	295
mbed_official	630:825f75ca301e	296	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /!< HSE clock selected as PLL entry clock source /
mbed_official	340:28d1f895c6fe	297
mbed_official	340:28d1f895c6fe	298	/**
mbed_official	340:28d1f895c6fe	299	* @}
mbed_official	630:825f75ca301e	300	*/
mbed_official	340:28d1f895c6fe	301
mbed_official	630:825f75ca301e	302	/** @defgroup RCC_Oscillator_Type Oscillator Type
mbed_official	340:28d1f895c6fe	303	* @{
mbed_official	340:28d1f895c6fe	304	*/
mbed_official	340:28d1f895c6fe	305	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	306	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	307	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	308	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	340:28d1f895c6fe	309	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	340:28d1f895c6fe	310	#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
mbed_official	340:28d1f895c6fe	311	/**
mbed_official	340:28d1f895c6fe	312	* @}
mbed_official	340:28d1f895c6fe	313	*/
mbed_official	340:28d1f895c6fe	314
mbed_official	630:825f75ca301e	315	/** @defgroup RCC_HSE_Config HSE Config
mbed_official	340:28d1f895c6fe	316	* @{
mbed_official	340:28d1f895c6fe	317	*/
mbed_official	630:825f75ca301e	318	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
mbed_official	630:825f75ca301e	319	#define RCC_HSE_ON ((uint32_t)0x00000001) /!< HSE clock activation /
mbed_official	630:825f75ca301e	320	#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for HSE clock /
mbed_official	340:28d1f895c6fe	321	/**
mbed_official	340:28d1f895c6fe	322	* @}
mbed_official	340:28d1f895c6fe	323	*/
mbed_official	340:28d1f895c6fe	324
mbed_official	630:825f75ca301e	325	/** @defgroup RCC_LSE_Config LSE Config
mbed_official	340:28d1f895c6fe	326	* @{
mbed_official	340:28d1f895c6fe	327	*/
mbed_official	630:825f75ca301e	328	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
mbed_official	630:825f75ca301e	329	#define RCC_LSE_ON ((uint32_t)0x00000001) /!< LSE clock activation /
mbed_official	630:825f75ca301e	330	#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for LSE clock /
mbed_official	340:28d1f895c6fe	331
mbed_official	340:28d1f895c6fe	332	/**
mbed_official	340:28d1f895c6fe	333	* @}
mbed_official	340:28d1f895c6fe	334	*/
mbed_official	340:28d1f895c6fe	335
mbed_official	630:825f75ca301e	336	/** @defgroup RCC_HSI_Config HSI Config
mbed_official	340:28d1f895c6fe	337	* @{
mbed_official	340:28d1f895c6fe	338	*/
mbed_official	630:825f75ca301e	339	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
mbed_official	630:825f75ca301e	340	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
mbed_official	340:28d1f895c6fe	341
mbed_official	630:825f75ca301e	342	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
mbed_official	340:28d1f895c6fe	343
mbed_official	340:28d1f895c6fe	344	/**
mbed_official	340:28d1f895c6fe	345	* @}
mbed_official	340:28d1f895c6fe	346	*/
mbed_official	630:825f75ca301e	347
mbed_official	340:28d1f895c6fe	348	/** @defgroup RCC_HSI14_Config RCC HSI14 Config
mbed_official	340:28d1f895c6fe	349	* @{
mbed_official	340:28d1f895c6fe	350	*/
mbed_official	340:28d1f895c6fe	351	#define RCC_HSI14_OFF ((uint32_t)0x00)
mbed_official	340:28d1f895c6fe	352	#define RCC_HSI14_ON RCC_CR2_HSI14ON
mbed_official	340:28d1f895c6fe	353	#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
mbed_official	340:28d1f895c6fe	354
mbed_official	630:825f75ca301e	355	#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
mbed_official	630:825f75ca301e	356	/**
mbed_official	630:825f75ca301e	357	* @}
mbed_official	630:825f75ca301e	358	*/
mbed_official	630:825f75ca301e	359
mbed_official	630:825f75ca301e	360
mbed_official	630:825f75ca301e	361	/** @defgroup RCC_LSI_Config LSI Config
mbed_official	630:825f75ca301e	362	* @{
mbed_official	630:825f75ca301e	363	*/
mbed_official	630:825f75ca301e	364	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
mbed_official	630:825f75ca301e	365	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
mbed_official	630:825f75ca301e	366
mbed_official	630:825f75ca301e	367	/**
mbed_official	630:825f75ca301e	368	* @}
mbed_official	630:825f75ca301e	369	*/
mbed_official	340:28d1f895c6fe	370
mbed_official	630:825f75ca301e	371	/** @defgroup RCC_PLL_Config PLL Config
mbed_official	630:825f75ca301e	372	* @{
mbed_official	630:825f75ca301e	373	*/
mbed_official	630:825f75ca301e	374	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
mbed_official	630:825f75ca301e	375	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
mbed_official	630:825f75ca301e	376	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
mbed_official	630:825f75ca301e	377
mbed_official	630:825f75ca301e	378	/**
mbed_official	630:825f75ca301e	379	* @}
mbed_official	630:825f75ca301e	380	*/
mbed_official	630:825f75ca301e	381
mbed_official	630:825f75ca301e	382	/** @defgroup RCC_System_Clock_Type System Clock Type
mbed_official	630:825f75ca301e	383	* @{
mbed_official	630:825f75ca301e	384	*/
mbed_official	630:825f75ca301e	385	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
mbed_official	630:825f75ca301e	386	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
mbed_official	630:825f75ca301e	387	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
mbed_official	630:825f75ca301e	388
mbed_official	340:28d1f895c6fe	389	/**
mbed_official	340:28d1f895c6fe	390	* @}
mbed_official	340:28d1f895c6fe	391	*/
mbed_official	340:28d1f895c6fe	392
mbed_official	630:825f75ca301e	393	/** @defgroup RCC_System_Clock_Source System Clock Source
mbed_official	340:28d1f895c6fe	394	* @{
mbed_official	340:28d1f895c6fe	395	*/
mbed_official	630:825f75ca301e	396	#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) /!< HSI selected as system clock /
mbed_official	630:825f75ca301e	397	#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) /!< HSE selected as system clock /
mbed_official	630:825f75ca301e	398	#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) /!< PLL selected as system clock /
mbed_official	630:825f75ca301e	399
mbed_official	630:825f75ca301e	400	/**
mbed_official	630:825f75ca301e	401	* @}
mbed_official	630:825f75ca301e	402	*/
mbed_official	340:28d1f895c6fe	403
mbed_official	630:825f75ca301e	404	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
mbed_official	630:825f75ca301e	405	* @{
mbed_official	630:825f75ca301e	406	*/
mbed_official	630:825f75ca301e	407	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
mbed_official	630:825f75ca301e	408	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
mbed_official	630:825f75ca301e	409	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
mbed_official	630:825f75ca301e	410
mbed_official	340:28d1f895c6fe	411	/**
mbed_official	340:28d1f895c6fe	412	* @}
mbed_official	340:28d1f895c6fe	413	*/
mbed_official	630:825f75ca301e	414
mbed_official	630:825f75ca301e	415	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
mbed_official	630:825f75ca301e	416	* @{
mbed_official	630:825f75ca301e	417	*/
mbed_official	630:825f75ca301e	418	#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
mbed_official	630:825f75ca301e	419	#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
mbed_official	630:825f75ca301e	420	#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
mbed_official	630:825f75ca301e	421	#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
mbed_official	630:825f75ca301e	422	#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
mbed_official	630:825f75ca301e	423	#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
mbed_official	630:825f75ca301e	424	#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
mbed_official	630:825f75ca301e	425	#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
mbed_official	630:825f75ca301e	426	#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
mbed_official	340:28d1f895c6fe	427
mbed_official	630:825f75ca301e	428	/**
mbed_official	630:825f75ca301e	429	* @}
mbed_official	630:825f75ca301e	430	*/
mbed_official	630:825f75ca301e	431
mbed_official	630:825f75ca301e	432	/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
mbed_official	340:28d1f895c6fe	433	* @{
mbed_official	340:28d1f895c6fe	434	*/
mbed_official	630:825f75ca301e	435	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
mbed_official	630:825f75ca301e	436	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
mbed_official	630:825f75ca301e	437	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
mbed_official	630:825f75ca301e	438	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
mbed_official	630:825f75ca301e	439	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
mbed_official	340:28d1f895c6fe	440
mbed_official	340:28d1f895c6fe	441	/**
mbed_official	340:28d1f895c6fe	442	* @}
mbed_official	630:825f75ca301e	443	*/
mbed_official	630:825f75ca301e	444
mbed_official	630:825f75ca301e	445	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
mbed_official	630:825f75ca301e	446	* @{
mbed_official	340:28d1f895c6fe	447	*/
mbed_official	630:825f75ca301e	448	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /!< No clock /
mbed_official	630:825f75ca301e	449	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_BDCR_RTCSEL_LSE) /!< LSE oscillator clock used as RTC clock /
mbed_official	630:825f75ca301e	450	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_BDCR_RTCSEL_LSI) /!< LSI oscillator clock used as RTC clock /
mbed_official	630:825f75ca301e	451	#define RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)RCC_BDCR_RTCSEL_HSE) /!< HSE oscillator clock divided by 32 used as RTC clock /
mbed_official	630:825f75ca301e	452	/**
mbed_official	630:825f75ca301e	453	* @}
mbed_official	630:825f75ca301e	454	*/
mbed_official	340:28d1f895c6fe	455
mbed_official	340:28d1f895c6fe	456	/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
mbed_official	340:28d1f895c6fe	457	* @{
mbed_official	340:28d1f895c6fe	458	*/
mbed_official	340:28d1f895c6fe	459	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
mbed_official	340:28d1f895c6fe	460	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
mbed_official	340:28d1f895c6fe	461	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
mbed_official	340:28d1f895c6fe	462	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
mbed_official	340:28d1f895c6fe	463	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
mbed_official	340:28d1f895c6fe	464	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
mbed_official	340:28d1f895c6fe	465	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
mbed_official	340:28d1f895c6fe	466	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
mbed_official	340:28d1f895c6fe	467	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
mbed_official	340:28d1f895c6fe	468	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
mbed_official	340:28d1f895c6fe	469	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
mbed_official	340:28d1f895c6fe	470	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
mbed_official	340:28d1f895c6fe	471	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
mbed_official	340:28d1f895c6fe	472	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
mbed_official	340:28d1f895c6fe	473	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
mbed_official	340:28d1f895c6fe	474	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
mbed_official	340:28d1f895c6fe	475
mbed_official	340:28d1f895c6fe	476	/**
mbed_official	340:28d1f895c6fe	477	* @}
mbed_official	340:28d1f895c6fe	478	*/
mbed_official	630:825f75ca301e	479
mbed_official	340:28d1f895c6fe	480	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
mbed_official	340:28d1f895c6fe	481	* @{
mbed_official	340:28d1f895c6fe	482	*/
mbed_official	340:28d1f895c6fe	483	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
mbed_official	340:28d1f895c6fe	484	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
mbed_official	340:28d1f895c6fe	485	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
mbed_official	340:28d1f895c6fe	486	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
mbed_official	340:28d1f895c6fe	487	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
mbed_official	340:28d1f895c6fe	488	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
mbed_official	340:28d1f895c6fe	489	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
mbed_official	340:28d1f895c6fe	490	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
mbed_official	340:28d1f895c6fe	491	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
mbed_official	340:28d1f895c6fe	492	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
mbed_official	340:28d1f895c6fe	493	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
mbed_official	340:28d1f895c6fe	494	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
mbed_official	340:28d1f895c6fe	495	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
mbed_official	340:28d1f895c6fe	496	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
mbed_official	340:28d1f895c6fe	497	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
mbed_official	340:28d1f895c6fe	498
mbed_official	340:28d1f895c6fe	499	/**
mbed_official	340:28d1f895c6fe	500	* @}
mbed_official	340:28d1f895c6fe	501	*/
mbed_official	340:28d1f895c6fe	502
mbed_official	340:28d1f895c6fe	503	/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
mbed_official	340:28d1f895c6fe	504	* @{
mbed_official	340:28d1f895c6fe	505	*/
mbed_official	340:28d1f895c6fe	506	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
mbed_official	340:28d1f895c6fe	507	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	340:28d1f895c6fe	508	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	340:28d1f895c6fe	509	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	340:28d1f895c6fe	510
mbed_official	340:28d1f895c6fe	511	/**
mbed_official	340:28d1f895c6fe	512	* @}
mbed_official	340:28d1f895c6fe	513	*/
mbed_official	340:28d1f895c6fe	514
mbed_official	340:28d1f895c6fe	515	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
mbed_official	340:28d1f895c6fe	516	* @{
mbed_official	340:28d1f895c6fe	517	*/
mbed_official	340:28d1f895c6fe	518	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
mbed_official	340:28d1f895c6fe	519	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
mbed_official	340:28d1f895c6fe	520
mbed_official	340:28d1f895c6fe	521	/**
mbed_official	340:28d1f895c6fe	522	* @}
mbed_official	340:28d1f895c6fe	523	*/
mbed_official	630:825f75ca301e	524	/** @defgroup RCC_MCO_Index MCO Index
mbed_official	340:28d1f895c6fe	525	* @{
mbed_official	340:28d1f895c6fe	526	*/
mbed_official	630:825f75ca301e	527	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	630:825f75ca301e	528	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
mbed_official	340:28d1f895c6fe	529
mbed_official	340:28d1f895c6fe	530	/**
mbed_official	340:28d1f895c6fe	531	* @}
mbed_official	340:28d1f895c6fe	532	*/
mbed_official	340:28d1f895c6fe	533
mbed_official	340:28d1f895c6fe	534	/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
mbed_official	340:28d1f895c6fe	535	* @{
mbed_official	340:28d1f895c6fe	536	*/
mbed_official	340:28d1f895c6fe	537	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
mbed_official	340:28d1f895c6fe	538	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
mbed_official	340:28d1f895c6fe	539	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
mbed_official	340:28d1f895c6fe	540	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
mbed_official	340:28d1f895c6fe	541	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
mbed_official	340:28d1f895c6fe	542	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
mbed_official	340:28d1f895c6fe	543	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
mbed_official	340:28d1f895c6fe	544	#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
mbed_official	630:825f75ca301e	545
mbed_official	340:28d1f895c6fe	546	/**
mbed_official	340:28d1f895c6fe	547	* @}
mbed_official	340:28d1f895c6fe	548	*/
mbed_official	630:825f75ca301e	549
mbed_official	630:825f75ca301e	550	/** @defgroup RCC_Interrupt Interrupts
mbed_official	340:28d1f895c6fe	551	* @{
mbed_official	340:28d1f895c6fe	552	*/
mbed_official	630:825f75ca301e	553	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
mbed_official	630:825f75ca301e	554	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
mbed_official	630:825f75ca301e	555	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
mbed_official	630:825f75ca301e	556	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
mbed_official	630:825f75ca301e	557	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
mbed_official	630:825f75ca301e	558	#define RCC_IT_HSI14 ((uint8_t)RCC_CIR_HSI14RDYF) /!< HSI14 Ready Interrupt flag /
mbed_official	630:825f75ca301e	559	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
mbed_official	340:28d1f895c6fe	560	/**
mbed_official	340:28d1f895c6fe	561	* @}
mbed_official	340:28d1f895c6fe	562	*/
mbed_official	340:28d1f895c6fe	563
mbed_official	630:825f75ca301e	564	/** @defgroup RCC_Flag Flags
mbed_official	630:825f75ca301e	565	* Elements values convention: XXXYYYYYb
mbed_official	340:28d1f895c6fe	566	* - YYYYY : Flag position in the register
mbed_official	630:825f75ca301e	567	* - XXX : Register index
mbed_official	630:825f75ca301e	568	* - 001: CR register
mbed_official	630:825f75ca301e	569	* - 010: CR2 register
mbed_official	630:825f75ca301e	570	* - 011: BDCR register
mbed_official	630:825f75ca301e	571	* - 0100: CSR register
mbed_official	340:28d1f895c6fe	572	* @{
mbed_official	340:28d1f895c6fe	573	*/
mbed_official	340:28d1f895c6fe	574	/* Flags in the CR register */
mbed_official	340:28d1f895c6fe	575	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSIRDY_BitNumber))
mbed_official	340:28d1f895c6fe	576	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSERDY_BitNumber))
mbed_official	340:28d1f895c6fe	577	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_PLLRDY_BitNumber))
mbed_official	340:28d1f895c6fe	578
mbed_official	340:28d1f895c6fe	579	/* Flags in the CR2 register */
mbed_official	340:28d1f895c6fe	580	#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI14RDY_BitNumber))
mbed_official	340:28d1f895c6fe	581
mbed_official	340:28d1f895c6fe	582
mbed_official	340:28d1f895c6fe	583	/* Flags in the CSR register */
mbed_official	340:28d1f895c6fe	584	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
mbed_official	340:28d1f895c6fe	585	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
mbed_official	340:28d1f895c6fe	586	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_RMVF_BitNumber))
mbed_official	340:28d1f895c6fe	587	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_OBLRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	588	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PINRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	589	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PORRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	590	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_SFTRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	591	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_IWDGRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	592	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_WWDGRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	593	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LPWRRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	594
mbed_official	630:825f75ca301e	595	/* Flags in the BDCR register */
mbed_official	630:825f75ca301e	596	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| RCC_BDCR_LSERDY_BitNumber))
mbed_official	340:28d1f895c6fe	597
mbed_official	340:28d1f895c6fe	598	/**
mbed_official	340:28d1f895c6fe	599	* @}
mbed_official	630:825f75ca301e	600	*/
mbed_official	340:28d1f895c6fe	601
mbed_official	340:28d1f895c6fe	602	/**
mbed_official	340:28d1f895c6fe	603	* @}
mbed_official	630:825f75ca301e	604	*/
mbed_official	340:28d1f895c6fe	605
mbed_official	340:28d1f895c6fe	606	/* Exported macro ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	607
mbed_official	340:28d1f895c6fe	608	/** @defgroup RCC_Exported_Macros RCC Exported Macros
mbed_official	630:825f75ca301e	609	* @{
mbed_official	630:825f75ca301e	610	*/
mbed_official	340:28d1f895c6fe	611
mbed_official	340:28d1f895c6fe	612	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
mbed_official	340:28d1f895c6fe	613	* @brief Enable or disable the AHB peripheral clock.
mbed_official	340:28d1f895c6fe	614	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	615	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	616	* using it.
mbed_official	340:28d1f895c6fe	617	* @{
mbed_official	340:28d1f895c6fe	618	*/
mbed_official	630:825f75ca301e	619	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	620	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	621	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
mbed_official	630:825f75ca301e	622	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	623	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
mbed_official	630:825f75ca301e	624	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	625	} while(0)
mbed_official	630:825f75ca301e	626	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	627	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	628	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
mbed_official	630:825f75ca301e	629	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	630	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
mbed_official	630:825f75ca301e	631	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	632	} while(0)
mbed_official	630:825f75ca301e	633	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	634	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	635	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
mbed_official	630:825f75ca301e	636	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	637	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
mbed_official	630:825f75ca301e	638	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	639	} while(0)
mbed_official	630:825f75ca301e	640	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	641	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	642	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
mbed_official	630:825f75ca301e	643	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	644	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
mbed_official	630:825f75ca301e	645	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	646	} while(0)
mbed_official	630:825f75ca301e	647	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	648	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	649	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
mbed_official	630:825f75ca301e	650	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	651	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
mbed_official	630:825f75ca301e	652	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	653	} while(0)
mbed_official	630:825f75ca301e	654	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	655	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	656	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
mbed_official	630:825f75ca301e	657	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	658	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
mbed_official	630:825f75ca301e	659	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	660	} while(0)
mbed_official	630:825f75ca301e	661	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	662	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	663	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
mbed_official	630:825f75ca301e	664	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	665	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
mbed_official	630:825f75ca301e	666	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	667	} while(0)
mbed_official	630:825f75ca301e	668	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	669	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	670	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
mbed_official	630:825f75ca301e	671	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	672	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
mbed_official	630:825f75ca301e	673	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	674	} while(0)
mbed_official	340:28d1f895c6fe	675
mbed_official	630:825f75ca301e	676	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
mbed_official	630:825f75ca301e	677	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
mbed_official	630:825f75ca301e	678	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
mbed_official	630:825f75ca301e	679	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
mbed_official	630:825f75ca301e	680	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
mbed_official	630:825f75ca301e	681	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
mbed_official	630:825f75ca301e	682	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
mbed_official	630:825f75ca301e	683	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
mbed_official	340:28d1f895c6fe	684	/**
mbed_official	340:28d1f895c6fe	685	* @}
mbed_official	340:28d1f895c6fe	686	*/
mbed_official	340:28d1f895c6fe	687
mbed_official	630:825f75ca301e	688	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
mbed_official	630:825f75ca301e	689	* @brief Get the enable or disable status of the AHB peripheral clock.
mbed_official	630:825f75ca301e	690	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	630:825f75ca301e	691	* is disabled and the application software has to enable this clock before
mbed_official	630:825f75ca301e	692	* using it.
mbed_official	630:825f75ca301e	693	* @{
mbed_official	630:825f75ca301e	694	*/
mbed_official	630:825f75ca301e	695	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
mbed_official	630:825f75ca301e	696	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
mbed_official	630:825f75ca301e	697	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
mbed_official	630:825f75ca301e	698	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
mbed_official	630:825f75ca301e	699	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
mbed_official	630:825f75ca301e	700	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
mbed_official	630:825f75ca301e	701	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
mbed_official	630:825f75ca301e	702	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
mbed_official	630:825f75ca301e	703	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
mbed_official	630:825f75ca301e	704	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
mbed_official	630:825f75ca301e	705	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
mbed_official	630:825f75ca301e	706	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
mbed_official	630:825f75ca301e	707	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
mbed_official	630:825f75ca301e	708	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
mbed_official	630:825f75ca301e	709	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
mbed_official	630:825f75ca301e	710	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
mbed_official	630:825f75ca301e	711	/**
mbed_official	630:825f75ca301e	712	* @}
mbed_official	630:825f75ca301e	713	*/
mbed_official	630:825f75ca301e	714
mbed_official	340:28d1f895c6fe	715	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
mbed_official	340:28d1f895c6fe	716	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	340:28d1f895c6fe	717	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	718	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	719	* using it.
mbed_official	340:28d1f895c6fe	720	* @{
mbed_official	340:28d1f895c6fe	721	*/
mbed_official	630:825f75ca301e	722	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	723	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	724	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official	630:825f75ca301e	725	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	726	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official	630:825f75ca301e	727	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	728	} while(0)
mbed_official	630:825f75ca301e	729	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	730	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	731	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	630:825f75ca301e	732	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	733	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	630:825f75ca301e	734	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	735	} while(0)
mbed_official	630:825f75ca301e	736	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	737	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	738	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
mbed_official	630:825f75ca301e	739	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	740	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
mbed_official	630:825f75ca301e	741	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	742	} while(0)
mbed_official	630:825f75ca301e	743	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	744	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	745	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official	630:825f75ca301e	746	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	747	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official	630:825f75ca301e	748	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	749	} while(0)
mbed_official	630:825f75ca301e	750	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	751	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	752	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
mbed_official	630:825f75ca301e	753	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	754	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
mbed_official	630:825f75ca301e	755	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	756	} while(0)
mbed_official	340:28d1f895c6fe	757
mbed_official	630:825f75ca301e	758	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	630:825f75ca301e	759	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	630:825f75ca301e	760	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official	630:825f75ca301e	761	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official	630:825f75ca301e	762	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
mbed_official	340:28d1f895c6fe	763	/**
mbed_official	340:28d1f895c6fe	764	* @}
mbed_official	340:28d1f895c6fe	765	*/
mbed_official	630:825f75ca301e	766
mbed_official	630:825f75ca301e	767	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
mbed_official	630:825f75ca301e	768	* @brief Get the enable or disable status of the APB1 peripheral clock.
mbed_official	630:825f75ca301e	769	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	630:825f75ca301e	770	* is disabled and the application software has to enable this clock before
mbed_official	630:825f75ca301e	771	* using it.
mbed_official	630:825f75ca301e	772	* @{
mbed_official	630:825f75ca301e	773	*/
mbed_official	630:825f75ca301e	774	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
mbed_official	630:825f75ca301e	775	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
mbed_official	630:825f75ca301e	776	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
mbed_official	630:825f75ca301e	777	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
mbed_official	630:825f75ca301e	778	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
mbed_official	630:825f75ca301e	779	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
mbed_official	630:825f75ca301e	780	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
mbed_official	630:825f75ca301e	781	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
mbed_official	630:825f75ca301e	782	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
mbed_official	630:825f75ca301e	783	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
mbed_official	630:825f75ca301e	784	/**
mbed_official	630:825f75ca301e	785	* @}
mbed_official	630:825f75ca301e	786	*/
mbed_official	630:825f75ca301e	787
mbed_official	340:28d1f895c6fe	788
mbed_official	340:28d1f895c6fe	789	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
mbed_official	340:28d1f895c6fe	790	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	340:28d1f895c6fe	791	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	792	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	793	* using it.
mbed_official	340:28d1f895c6fe	794	* @{
mbed_official	340:28d1f895c6fe	795	*/
mbed_official	630:825f75ca301e	796	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	797	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	798	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
mbed_official	630:825f75ca301e	799	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	800	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
mbed_official	630:825f75ca301e	801	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	802	} while(0)
mbed_official	630:825f75ca301e	803	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	804	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	805	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official	630:825f75ca301e	806	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	807	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official	630:825f75ca301e	808	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	809	} while(0)
mbed_official	630:825f75ca301e	810	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	811	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	812	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official	630:825f75ca301e	813	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	814	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official	630:825f75ca301e	815	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	816	} while(0)
mbed_official	630:825f75ca301e	817	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	818	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	819	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official	630:825f75ca301e	820	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	821	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official	630:825f75ca301e	822	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	823	} while(0)
mbed_official	630:825f75ca301e	824	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	825	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	826	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
mbed_official	630:825f75ca301e	827	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	828	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
mbed_official	630:825f75ca301e	829	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	830	} while(0)
mbed_official	630:825f75ca301e	831	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	832	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	833	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
mbed_official	630:825f75ca301e	834	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	835	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
mbed_official	630:825f75ca301e	836	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	837	} while(0)
mbed_official	630:825f75ca301e	838	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	839	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	840	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official	630:825f75ca301e	841	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	842	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official	630:825f75ca301e	843	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	844	} while(0)
mbed_official	630:825f75ca301e	845	#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	846	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	847	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
mbed_official	630:825f75ca301e	848	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	849	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
mbed_official	630:825f75ca301e	850	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	851	} while(0)
mbed_official	340:28d1f895c6fe	852
mbed_official	630:825f75ca301e	853	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
mbed_official	630:825f75ca301e	854	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	630:825f75ca301e	855	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official	630:825f75ca301e	856	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	630:825f75ca301e	857	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
mbed_official	630:825f75ca301e	858	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
mbed_official	630:825f75ca301e	859	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official	630:825f75ca301e	860	#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
mbed_official	340:28d1f895c6fe	861	/**
mbed_official	340:28d1f895c6fe	862	* @}
mbed_official	340:28d1f895c6fe	863	*/
mbed_official	340:28d1f895c6fe	864
mbed_official	630:825f75ca301e	865	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
mbed_official	630:825f75ca301e	866	* @brief Get the enable or disable status of the APB2 peripheral clock.
mbed_official	630:825f75ca301e	867	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	630:825f75ca301e	868	* is disabled and the application software has to enable this clock before
mbed_official	630:825f75ca301e	869	* using it.
mbed_official	630:825f75ca301e	870	* @{
mbed_official	630:825f75ca301e	871	*/
mbed_official	630:825f75ca301e	872	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
mbed_official	630:825f75ca301e	873	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
mbed_official	630:825f75ca301e	874	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
mbed_official	630:825f75ca301e	875	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
mbed_official	630:825f75ca301e	876	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
mbed_official	630:825f75ca301e	877	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
mbed_official	630:825f75ca301e	878	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
mbed_official	630:825f75ca301e	879	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
mbed_official	630:825f75ca301e	880	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
mbed_official	630:825f75ca301e	881	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
mbed_official	630:825f75ca301e	882	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
mbed_official	630:825f75ca301e	883	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
mbed_official	630:825f75ca301e	884	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
mbed_official	630:825f75ca301e	885	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
mbed_official	630:825f75ca301e	886	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
mbed_official	630:825f75ca301e	887	#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
mbed_official	630:825f75ca301e	888	/**
mbed_official	630:825f75ca301e	889	* @}
mbed_official	630:825f75ca301e	890	*/
mbed_official	630:825f75ca301e	891
mbed_official	340:28d1f895c6fe	892	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
mbed_official	340:28d1f895c6fe	893	* @brief Force or release AHB peripheral reset.
mbed_official	340:28d1f895c6fe	894	* @{
mbed_official	340:28d1f895c6fe	895	*/
mbed_official	630:825f75ca301e	896	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
mbed_official	630:825f75ca301e	897	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
mbed_official	630:825f75ca301e	898	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
mbed_official	630:825f75ca301e	899	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
mbed_official	630:825f75ca301e	900	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
mbed_official	340:28d1f895c6fe	901
mbed_official	630:825f75ca301e	902	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
mbed_official	630:825f75ca301e	903	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
mbed_official	630:825f75ca301e	904	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
mbed_official	630:825f75ca301e	905	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
mbed_official	630:825f75ca301e	906	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
mbed_official	340:28d1f895c6fe	907	/**
mbed_official	340:28d1f895c6fe	908	* @}
mbed_official	340:28d1f895c6fe	909	*/
mbed_official	340:28d1f895c6fe	910
mbed_official	340:28d1f895c6fe	911	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
mbed_official	340:28d1f895c6fe	912	* @brief Force or release APB1 peripheral reset.
mbed_official	340:28d1f895c6fe	913	* @{
mbed_official	340:28d1f895c6fe	914	*/
mbed_official	630:825f75ca301e	915	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	630:825f75ca301e	916	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	630:825f75ca301e	917	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	630:825f75ca301e	918	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	630:825f75ca301e	919	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	630:825f75ca301e	920	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	340:28d1f895c6fe	921
mbed_official	630:825f75ca301e	922	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	630:825f75ca301e	923	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	630:825f75ca301e	924	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	630:825f75ca301e	925	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
mbed_official	630:825f75ca301e	926	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official	630:825f75ca301e	927	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
mbed_official	340:28d1f895c6fe	928	/**
mbed_official	340:28d1f895c6fe	929	* @}
mbed_official	340:28d1f895c6fe	930	*/
mbed_official	340:28d1f895c6fe	931
mbed_official	340:28d1f895c6fe	932	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
mbed_official	340:28d1f895c6fe	933	* @brief Force or release APB2 peripheral reset.
mbed_official	340:28d1f895c6fe	934	* @{
mbed_official	340:28d1f895c6fe	935	*/
mbed_official	630:825f75ca301e	936	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	630:825f75ca301e	937	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	630:825f75ca301e	938	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
mbed_official	630:825f75ca301e	939	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
mbed_official	630:825f75ca301e	940	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	630:825f75ca301e	941	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
mbed_official	630:825f75ca301e	942	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
mbed_official	630:825f75ca301e	943	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
mbed_official	630:825f75ca301e	944	#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
mbed_official	340:28d1f895c6fe	945
mbed_official	630:825f75ca301e	946	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	630:825f75ca301e	947	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
mbed_official	630:825f75ca301e	948	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
mbed_official	630:825f75ca301e	949	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official	630:825f75ca301e	950	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	630:825f75ca301e	951	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official	630:825f75ca301e	952	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
mbed_official	630:825f75ca301e	953	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
mbed_official	630:825f75ca301e	954	#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
mbed_official	630:825f75ca301e	955	/**
mbed_official	630:825f75ca301e	956	* @}
mbed_official	630:825f75ca301e	957	*/
mbed_official	630:825f75ca301e	958	/** @defgroup RCC_HSI_Configuration HSI Configuration
mbed_official	630:825f75ca301e	959	* @{
mbed_official	630:825f75ca301e	960	*/
mbed_official	630:825f75ca301e	961
mbed_official	630:825f75ca301e	962	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	630:825f75ca301e	963	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	630:825f75ca301e	964	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	630:825f75ca301e	965	* you have to select another source of the system clock then stop the HSI.
mbed_official	630:825f75ca301e	966	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	630:825f75ca301e	967	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	630:825f75ca301e	968	* system clock source.
mbed_official	630:825f75ca301e	969	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	630:825f75ca301e	970	* clock cycles.
mbed_official	630:825f75ca301e	971	*/
mbed_official	630:825f75ca301e	972	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	630:825f75ca301e	973	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	630:825f75ca301e	974
mbed_official	630:825f75ca301e	975	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	630:825f75ca301e	976	* @note The calibration is used to compensate for the variations in voltage
mbed_official	630:825f75ca301e	977	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	630:825f75ca301e	978	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
mbed_official	630:825f75ca301e	979	* (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	630:825f75ca301e	980	* This parameter must be a number between 0 and 0x1F.
mbed_official	630:825f75ca301e	981	*/
mbed_official	630:825f75ca301e	982	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
mbed_official	630:825f75ca301e	983	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
mbed_official	630:825f75ca301e	984
mbed_official	340:28d1f895c6fe	985	/**
mbed_official	340:28d1f895c6fe	986	* @}
mbed_official	340:28d1f895c6fe	987	*/
mbed_official	340:28d1f895c6fe	988
mbed_official	630:825f75ca301e	989	/** @defgroup RCC_LSI_Configuration LSI Configuration
mbed_official	340:28d1f895c6fe	990	* @{
mbed_official	340:28d1f895c6fe	991	*/
mbed_official	340:28d1f895c6fe	992
mbed_official	630:825f75ca301e	993	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	630:825f75ca301e	994	* @note After enabling the LSI, the application software should wait on
mbed_official	630:825f75ca301e	995	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	630:825f75ca301e	996	* be used to clock the IWDG and/or the RTC.
mbed_official	630:825f75ca301e	997	* @note LSI can not be disabled if the IWDG is running.
mbed_official	630:825f75ca301e	998	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	630:825f75ca301e	999	* clock cycles.
mbed_official	630:825f75ca301e	1000	*/
mbed_official	630:825f75ca301e	1001	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	630:825f75ca301e	1002	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	630:825f75ca301e	1003
mbed_official	340:28d1f895c6fe	1004	/**
mbed_official	340:28d1f895c6fe	1005	* @}
mbed_official	340:28d1f895c6fe	1006	*/
mbed_official	340:28d1f895c6fe	1007
mbed_official	630:825f75ca301e	1008	/** @defgroup RCC_HSE_Configuration HSE Configuration
mbed_official	340:28d1f895c6fe	1009	* @{
mbed_official	340:28d1f895c6fe	1010	*/
mbed_official	340:28d1f895c6fe	1011
mbed_official	340:28d1f895c6fe	1012	/**
mbed_official	340:28d1f895c6fe	1013	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	630:825f75ca301e	1014	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
mbed_official	630:825f75ca301e	1015	* supported by this macro. User should request a transition to HSE Off
mbed_official	630:825f75ca301e	1016	* first and then HSE On or HSE Bypass.
mbed_official	340:28d1f895c6fe	1017	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	340:28d1f895c6fe	1018	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	340:28d1f895c6fe	1019	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	340:28d1f895c6fe	1020	* @note HSE state can not be changed if it is used directly or through the
mbed_official	340:28d1f895c6fe	1021	* PLL as system clock. In this case, you have to select another source
mbed_official	340:28d1f895c6fe	1022	* of the system clock then change the HSE state (ex. disable it).
mbed_official	340:28d1f895c6fe	1023	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	1024	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
mbed_official	340:28d1f895c6fe	1025	* was previously enabled you have to enable it again after calling this
mbed_official	340:28d1f895c6fe	1026	* function.
mbed_official	340:28d1f895c6fe	1027	* @param __STATE__: specifies the new state of the HSE.
mbed_official	340:28d1f895c6fe	1028	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1029	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	340:28d1f895c6fe	1030	* 6 HSE oscillator clock cycles.
mbed_official	340:28d1f895c6fe	1031	* @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official	340:28d1f895c6fe	1032	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
mbed_official	340:28d1f895c6fe	1033	*/
mbed_official	630:825f75ca301e	1034	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
mbed_official	630:825f75ca301e	1035	do{ \
mbed_official	630:825f75ca301e	1036	if ((__STATE__) == RCC_HSE_ON) \
mbed_official	630:825f75ca301e	1037	{ \
mbed_official	630:825f75ca301e	1038	SET_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	630:825f75ca301e	1039	} \
mbed_official	630:825f75ca301e	1040	else if ((__STATE__) == RCC_HSE_OFF) \
mbed_official	630:825f75ca301e	1041	{ \
mbed_official	630:825f75ca301e	1042	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	630:825f75ca301e	1043	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	630:825f75ca301e	1044	} \
mbed_official	630:825f75ca301e	1045	else if ((__STATE__) == RCC_HSE_BYPASS) \
mbed_official	630:825f75ca301e	1046	{ \
mbed_official	630:825f75ca301e	1047	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	630:825f75ca301e	1048	SET_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	630:825f75ca301e	1049	} \
mbed_official	630:825f75ca301e	1050	else \
mbed_official	630:825f75ca301e	1051	{ \
mbed_official	630:825f75ca301e	1052	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	630:825f75ca301e	1053	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	630:825f75ca301e	1054	} \
mbed_official	630:825f75ca301e	1055	}while(0)
mbed_official	340:28d1f895c6fe	1056
mbed_official	340:28d1f895c6fe	1057	/**
mbed_official	340:28d1f895c6fe	1058	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
mbed_official	340:28d1f895c6fe	1059	* @note Predivision factor can not be changed if PLL is used as system clock
mbed_official	340:28d1f895c6fe	1060	* In this case, you have to select another source of the system clock, disable the PLL and
mbed_official	340:28d1f895c6fe	1061	* then change the HSE predivision factor.
mbed_official	630:825f75ca301e	1062	* @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
mbed_official	340:28d1f895c6fe	1063	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
mbed_official	340:28d1f895c6fe	1064	*/
mbed_official	630:825f75ca301e	1065	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
mbed_official	630:825f75ca301e	1066	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
mbed_official	630:825f75ca301e	1067
mbed_official	340:28d1f895c6fe	1068	/**
mbed_official	340:28d1f895c6fe	1069	* @}
mbed_official	340:28d1f895c6fe	1070	*/
mbed_official	340:28d1f895c6fe	1071
mbed_official	630:825f75ca301e	1072	/** @defgroup RCC_LSE_Configuration LSE Configuration
mbed_official	340:28d1f895c6fe	1073	* @{
mbed_official	630:825f75ca301e	1074	*/
mbed_official	630:825f75ca301e	1075
mbed_official	340:28d1f895c6fe	1076	/**
mbed_official	340:28d1f895c6fe	1077	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	630:825f75ca301e	1078	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
mbed_official	340:28d1f895c6fe	1079	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	630:825f75ca301e	1080	* this domain after reset, you have to enable write access using
mbed_official	340:28d1f895c6fe	1081	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	630:825f75ca301e	1082	* (to be done once after reset).
mbed_official	340:28d1f895c6fe	1083	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	340:28d1f895c6fe	1084	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	340:28d1f895c6fe	1085	* is stable and can be used to clock the RTC.
mbed_official	340:28d1f895c6fe	1086	* @param __STATE__: specifies the new state of the LSE.
mbed_official	340:28d1f895c6fe	1087	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1088	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	340:28d1f895c6fe	1089	* 6 LSE oscillator clock cycles.
mbed_official	630:825f75ca301e	1090	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official	630:825f75ca301e	1091	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official	340:28d1f895c6fe	1092	*/
mbed_official	630:825f75ca301e	1093	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
mbed_official	630:825f75ca301e	1094	do{ \
mbed_official	630:825f75ca301e	1095	if ((__STATE__) == RCC_LSE_ON) \
mbed_official	630:825f75ca301e	1096	{ \
mbed_official	630:825f75ca301e	1097	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	630:825f75ca301e	1098	} \
mbed_official	630:825f75ca301e	1099	else if ((__STATE__) == RCC_LSE_OFF) \
mbed_official	630:825f75ca301e	1100	{ \
mbed_official	630:825f75ca301e	1101	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	630:825f75ca301e	1102	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	630:825f75ca301e	1103	} \
mbed_official	630:825f75ca301e	1104	else if ((__STATE__) == RCC_LSE_BYPASS) \
mbed_official	630:825f75ca301e	1105	{ \
mbed_official	630:825f75ca301e	1106	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	630:825f75ca301e	1107	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	630:825f75ca301e	1108	} \
mbed_official	630:825f75ca301e	1109	else \
mbed_official	630:825f75ca301e	1110	{ \
mbed_official	630:825f75ca301e	1111	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	630:825f75ca301e	1112	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	630:825f75ca301e	1113	} \
mbed_official	630:825f75ca301e	1114	}while(0)
mbed_official	630:825f75ca301e	1115
mbed_official	340:28d1f895c6fe	1116	/**
mbed_official	340:28d1f895c6fe	1117	* @}
mbed_official	340:28d1f895c6fe	1118	*/
mbed_official	340:28d1f895c6fe	1119
mbed_official	340:28d1f895c6fe	1120	/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
mbed_official	340:28d1f895c6fe	1121	* @{
mbed_official	340:28d1f895c6fe	1122	*/
mbed_official	340:28d1f895c6fe	1123
mbed_official	340:28d1f895c6fe	1124	/** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
mbed_official	340:28d1f895c6fe	1125	* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	1126	* @note HSI14 can not be stopped if it is used as system clock source. In this case,
mbed_official	340:28d1f895c6fe	1127	* you have to select another source of the system clock then stop the HSI14.
mbed_official	340:28d1f895c6fe	1128	* @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
mbed_official	340:28d1f895c6fe	1129	* should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
mbed_official	340:28d1f895c6fe	1130	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
mbed_official	340:28d1f895c6fe	1131	* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
mbed_official	340:28d1f895c6fe	1132	* clock cycles.
mbed_official	340:28d1f895c6fe	1133	*/
mbed_official	340:28d1f895c6fe	1134	#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
mbed_official	340:28d1f895c6fe	1135	#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
mbed_official	340:28d1f895c6fe	1136
mbed_official	340:28d1f895c6fe	1137	/** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
mbed_official	340:28d1f895c6fe	1138	*/
mbed_official	340:28d1f895c6fe	1139	#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
mbed_official	340:28d1f895c6fe	1140	#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
mbed_official	340:28d1f895c6fe	1141
mbed_official	340:28d1f895c6fe	1142	/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
mbed_official	340:28d1f895c6fe	1143	* @note The calibration is used to compensate for the variations in voltage
mbed_official	340:28d1f895c6fe	1144	* and temperature that influence the frequency of the internal HSI14 RC.
mbed_official	340:28d1f895c6fe	1145	* @param __HSI14CalibrationValue__: specifies the calibration trimming value
mbed_official	340:28d1f895c6fe	1146	* (default is RCC_HSI14CALIBRATION_DEFAULT).
mbed_official	340:28d1f895c6fe	1147	* This parameter must be a number between 0 and 0x1F.
mbed_official	340:28d1f895c6fe	1148	*/
mbed_official	340:28d1f895c6fe	1149	#define RCC_CR2_HSI14TRIM_BitNumber 3
mbed_official	340:28d1f895c6fe	1150	#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
mbed_official	340:28d1f895c6fe	1151	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
mbed_official	340:28d1f895c6fe	1152	/**
mbed_official	340:28d1f895c6fe	1153	* @}
mbed_official	340:28d1f895c6fe	1154	*/
mbed_official	340:28d1f895c6fe	1155
mbed_official	340:28d1f895c6fe	1156	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
mbed_official	340:28d1f895c6fe	1157	* @{
mbed_official	340:28d1f895c6fe	1158	*/
mbed_official	340:28d1f895c6fe	1159
mbed_official	340:28d1f895c6fe	1160	/** @brief Macro to configure the USART1 clock (USART1CLK).
mbed_official	340:28d1f895c6fe	1161	* @param __USART1CLKSource__: specifies the USART1 clock source.
mbed_official	340:28d1f895c6fe	1162	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1163	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
mbed_official	340:28d1f895c6fe	1164	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
mbed_official	340:28d1f895c6fe	1165	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
mbed_official	340:28d1f895c6fe	1166	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official	340:28d1f895c6fe	1167	*/
mbed_official	340:28d1f895c6fe	1168	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
mbed_official	340:28d1f895c6fe	1169	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
mbed_official	340:28d1f895c6fe	1170
mbed_official	340:28d1f895c6fe	1171	/** @brief Macro to get the USART1 clock source.
mbed_official	340:28d1f895c6fe	1172	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1173	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
mbed_official	340:28d1f895c6fe	1174	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
mbed_official	340:28d1f895c6fe	1175	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
mbed_official	340:28d1f895c6fe	1176	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official	340:28d1f895c6fe	1177	*/
mbed_official	340:28d1f895c6fe	1178	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
mbed_official	340:28d1f895c6fe	1179	/**
mbed_official	340:28d1f895c6fe	1180	* @}
mbed_official	340:28d1f895c6fe	1181	*/
mbed_official	340:28d1f895c6fe	1182
mbed_official	340:28d1f895c6fe	1183	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
mbed_official	340:28d1f895c6fe	1184	* @{
mbed_official	340:28d1f895c6fe	1185	*/
mbed_official	340:28d1f895c6fe	1186
mbed_official	340:28d1f895c6fe	1187	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
mbed_official	340:28d1f895c6fe	1188	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
mbed_official	340:28d1f895c6fe	1189	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1190	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
mbed_official	340:28d1f895c6fe	1191	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official	340:28d1f895c6fe	1192	*/
mbed_official	340:28d1f895c6fe	1193	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
mbed_official	340:28d1f895c6fe	1194	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
mbed_official	340:28d1f895c6fe	1195
mbed_official	340:28d1f895c6fe	1196	/** @brief Macro to get the I2C1 clock source.
mbed_official	340:28d1f895c6fe	1197	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1198	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
mbed_official	340:28d1f895c6fe	1199	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official	340:28d1f895c6fe	1200	*/
mbed_official	340:28d1f895c6fe	1201	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
mbed_official	340:28d1f895c6fe	1202	/**
mbed_official	340:28d1f895c6fe	1203	* @}
mbed_official	340:28d1f895c6fe	1204	*/
mbed_official	340:28d1f895c6fe	1205
mbed_official	630:825f75ca301e	1206
mbed_official	630:825f75ca301e	1207	/** @defgroup RCC_PLL_Configuration PLL Configuration
mbed_official	630:825f75ca301e	1208	* @{
mbed_official	630:825f75ca301e	1209	*/
mbed_official	630:825f75ca301e	1210
mbed_official	630:825f75ca301e	1211	/** @brief Macros to enable the main PLL.
mbed_official	630:825f75ca301e	1212	* @note After enabling the main PLL, the application software should wait on
mbed_official	630:825f75ca301e	1213	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	630:825f75ca301e	1214	* be used as system clock source.
mbed_official	630:825f75ca301e	1215	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	630:825f75ca301e	1216	*/
mbed_official	630:825f75ca301e	1217	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	630:825f75ca301e	1218
mbed_official	630:825f75ca301e	1219	/** @brief Macros to disable the main PLL.
mbed_official	630:825f75ca301e	1220	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	630:825f75ca301e	1221	*/
mbed_official	630:825f75ca301e	1222	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	630:825f75ca301e	1223
mbed_official	630:825f75ca301e	1224	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
mbed_official	630:825f75ca301e	1225	* @note This function must be used only when the main PLL is disabled.
mbed_official	630:825f75ca301e	1226	*
mbed_official	630:825f75ca301e	1227	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
mbed_official	630:825f75ca301e	1228	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1229	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	630:825f75ca301e	1230	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	630:825f75ca301e	1231	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
mbed_official	630:825f75ca301e	1232	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1233	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
mbed_official	630:825f75ca301e	1234	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
mbed_official	630:825f75ca301e	1235	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
mbed_official	630:825f75ca301e	1236	*
mbed_official	630:825f75ca301e	1237	*/
mbed_official	630:825f75ca301e	1238	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
mbed_official	630:825f75ca301e	1239	do { \
mbed_official	630:825f75ca301e	1240	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
mbed_official	630:825f75ca301e	1241	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSOURCE__))); \
mbed_official	630:825f75ca301e	1242	} while(0)
mbed_official	630:825f75ca301e	1243
mbed_official	630:825f75ca301e	1244	/** @brief Get oscillator clock selected as PLL input clock
mbed_official	630:825f75ca301e	1245	* @retval The clock source used for PLL entry. The returned value can be one
mbed_official	630:825f75ca301e	1246	* of the following:
mbed_official	630:825f75ca301e	1247	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
mbed_official	630:825f75ca301e	1248	*/
mbed_official	630:825f75ca301e	1249	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
mbed_official	630:825f75ca301e	1250
mbed_official	630:825f75ca301e	1251	/**
mbed_official	630:825f75ca301e	1252	* @}
mbed_official	630:825f75ca301e	1253	*/
mbed_official	630:825f75ca301e	1254
mbed_official	630:825f75ca301e	1255	/** @defgroup RCC_Get_Clock_source Get Clock source
mbed_official	630:825f75ca301e	1256	* @{
mbed_official	630:825f75ca301e	1257	*/
mbed_official	630:825f75ca301e	1258
mbed_official	630:825f75ca301e	1259	/**
mbed_official	630:825f75ca301e	1260	* @brief Macro to configure the system clock source.
mbed_official	630:825f75ca301e	1261	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
mbed_official	630:825f75ca301e	1262	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1263	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
mbed_official	630:825f75ca301e	1264	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
mbed_official	630:825f75ca301e	1265	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
mbed_official	630:825f75ca301e	1266	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
mbed_official	630:825f75ca301e	1267	*/
mbed_official	630:825f75ca301e	1268	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
mbed_official	630:825f75ca301e	1269	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
mbed_official	630:825f75ca301e	1270
mbed_official	630:825f75ca301e	1271	/** @brief Macro to get the clock source used as system clock.
mbed_official	630:825f75ca301e	1272	* @retval The clock source used as system clock. The returned value can be one
mbed_official	630:825f75ca301e	1273	* of the following:
mbed_official	630:825f75ca301e	1274	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
mbed_official	630:825f75ca301e	1275	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
mbed_official	630:825f75ca301e	1276	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
mbed_official	630:825f75ca301e	1277	*/
mbed_official	630:825f75ca301e	1278	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
mbed_official	630:825f75ca301e	1279
mbed_official	630:825f75ca301e	1280	/**
mbed_official	630:825f75ca301e	1281	* @}
mbed_official	630:825f75ca301e	1282	*/
mbed_official	630:825f75ca301e	1283
mbed_official	340:28d1f895c6fe	1284	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
mbed_official	340:28d1f895c6fe	1285	* @{
mbed_official	340:28d1f895c6fe	1286	*/
mbed_official	340:28d1f895c6fe	1287
mbed_official	630:825f75ca301e	1288	/** @brief Macro to configures the RTC clock (RTCCLK).
mbed_official	340:28d1f895c6fe	1289	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	340:28d1f895c6fe	1290	* access is denied to this domain after reset, you have to enable write
mbed_official	340:28d1f895c6fe	1291	* access using the Power Backup Access macro before to configure
mbed_official	630:825f75ca301e	1292	* the RTC clock source (to be done once after reset).
mbed_official	630:825f75ca301e	1293	* @note Once the RTC clock is configured it can't be changed unless the
mbed_official	630:825f75ca301e	1294	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
mbed_official	340:28d1f895c6fe	1295	* a Power On Reset (POR).
mbed_official	340:28d1f895c6fe	1296	*
mbed_official	630:825f75ca301e	1297	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
mbed_official	630:825f75ca301e	1298	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1299	* @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
mbed_official	630:825f75ca301e	1300	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	630:825f75ca301e	1301	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	630:825f75ca301e	1302	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
mbed_official	630:825f75ca301e	1303	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	340:28d1f895c6fe	1304	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	340:28d1f895c6fe	1305	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
mbed_official	340:28d1f895c6fe	1306	* the RTC cannot be used in STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	1307	* @note The system must always be configured so as to get a PCLK frequency greater than or
mbed_official	340:28d1f895c6fe	1308	* equal to the RTCCLK frequency for a proper operation of the RTC.
mbed_official	340:28d1f895c6fe	1309	*/
mbed_official	630:825f75ca301e	1310	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
mbed_official	630:825f75ca301e	1311
mbed_official	630:825f75ca301e	1312	/** @brief macros to get the RTC clock source.
mbed_official	340:28d1f895c6fe	1313	* @retval The clock source can be one of the following values:
mbed_official	630:825f75ca301e	1314	* @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
mbed_official	340:28d1f895c6fe	1315	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	340:28d1f895c6fe	1316	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	630:825f75ca301e	1317	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
mbed_official	340:28d1f895c6fe	1318	*/
mbed_official	630:825f75ca301e	1319	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
mbed_official	630:825f75ca301e	1320
mbed_official	630:825f75ca301e	1321	/** @brief Macros to enable the the RTC clock.
mbed_official	630:825f75ca301e	1322	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	340:28d1f895c6fe	1323	*/
mbed_official	630:825f75ca301e	1324	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
mbed_official	340:28d1f895c6fe	1325
mbed_official	630:825f75ca301e	1326	/** @brief Macros to disable the the RTC clock.
mbed_official	630:825f75ca301e	1327	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	340:28d1f895c6fe	1328	*/
mbed_official	630:825f75ca301e	1329	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
mbed_official	630:825f75ca301e	1330
mbed_official	630:825f75ca301e	1331	/** @brief Macros to force the Backup domain reset.
mbed_official	630:825f75ca301e	1332	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	630:825f75ca301e	1333	* and the RTC clock source selection in RCC_BDCR register.
mbed_official	630:825f75ca301e	1334	*/
mbed_official	630:825f75ca301e	1335	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
mbed_official	630:825f75ca301e	1336
mbed_official	630:825f75ca301e	1337	/** @brief Macros to release the Backup domain reset.
mbed_official	630:825f75ca301e	1338	*/
mbed_official	630:825f75ca301e	1339	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
mbed_official	630:825f75ca301e	1340
mbed_official	340:28d1f895c6fe	1341	/**
mbed_official	340:28d1f895c6fe	1342	* @}
mbed_official	340:28d1f895c6fe	1343	*/
mbed_official	340:28d1f895c6fe	1344
mbed_official	630:825f75ca301e	1345	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
mbed_official	340:28d1f895c6fe	1346	* @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	340:28d1f895c6fe	1347	* @{
mbed_official	340:28d1f895c6fe	1348	*/
mbed_official	340:28d1f895c6fe	1349
mbed_official	630:825f75ca301e	1350	/** @brief Enable RCC interrupt.
mbed_official	340:28d1f895c6fe	1351	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	630:825f75ca301e	1352	* This parameter can be any combination of the following values:
mbed_official	630:825f75ca301e	1353	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	630:825f75ca301e	1354	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	630:825f75ca301e	1355	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	630:825f75ca301e	1356	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	630:825f75ca301e	1357	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	340:28d1f895c6fe	1358	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
mbed_official	340:28d1f895c6fe	1359	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
mbed_official	340:28d1f895c6fe	1360	*/
mbed_official	630:825f75ca301e	1361	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1362
mbed_official	630:825f75ca301e	1363	/** @brief Disable RCC interrupt.
mbed_official	340:28d1f895c6fe	1364	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	630:825f75ca301e	1365	* This parameter can be any combination of the following values:
mbed_official	630:825f75ca301e	1366	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	630:825f75ca301e	1367	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	630:825f75ca301e	1368	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	630:825f75ca301e	1369	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	630:825f75ca301e	1370	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	630:825f75ca301e	1371	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
mbed_official	630:825f75ca301e	1372	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
mbed_official	630:825f75ca301e	1373	*/
mbed_official	630:825f75ca301e	1374	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
mbed_official	630:825f75ca301e	1375
mbed_official	630:825f75ca301e	1376	/** @brief Clear the RCC's interrupt pending bits.
mbed_official	630:825f75ca301e	1377	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	630:825f75ca301e	1378	* This parameter can be any combination of the following values:
mbed_official	630:825f75ca301e	1379	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	630:825f75ca301e	1380	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	630:825f75ca301e	1381	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	630:825f75ca301e	1382	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	630:825f75ca301e	1383	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	630:825f75ca301e	1384	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	340:28d1f895c6fe	1385	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
mbed_official	340:28d1f895c6fe	1386	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
mbed_official	340:28d1f895c6fe	1387	*/
mbed_official	630:825f75ca301e	1388	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1389
mbed_official	630:825f75ca301e	1390	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	630:825f75ca301e	1391	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	630:825f75ca301e	1392	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1393	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	630:825f75ca301e	1394	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	630:825f75ca301e	1395	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	630:825f75ca301e	1396	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	630:825f75ca301e	1397	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	630:825f75ca301e	1398	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	630:825f75ca301e	1399	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
mbed_official	630:825f75ca301e	1400	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
mbed_official	630:825f75ca301e	1401	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	340:28d1f895c6fe	1402	*/
mbed_official	630:825f75ca301e	1403	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1404
mbed_official	630:825f75ca301e	1405	/** @brief Set RMVF bit to clear the reset flags.
mbed_official	630:825f75ca301e	1406	* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
mbed_official	630:825f75ca301e	1407	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
mbed_official	340:28d1f895c6fe	1408	*/
mbed_official	630:825f75ca301e	1409	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	340:28d1f895c6fe	1410
mbed_official	340:28d1f895c6fe	1411	/** @brief Check RCC flag is set or not.
mbed_official	340:28d1f895c6fe	1412	* @param __FLAG__: specifies the flag to check.
mbed_official	630:825f75ca301e	1413	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1414	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
mbed_official	630:825f75ca301e	1415	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
mbed_official	630:825f75ca301e	1416	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
mbed_official	340:28d1f895c6fe	1417	* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
mbed_official	340:28d1f895c6fe	1418	* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
mbed_official	630:825f75ca301e	1419	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
mbed_official	630:825f75ca301e	1420	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
mbed_official	340:28d1f895c6fe	1421	* @arg RCC_FLAG_OBLRST: Option Byte Load reset
mbed_official	630:825f75ca301e	1422	* @arg RCC_FLAG_PINRST: Pin reset.
mbed_official	630:825f75ca301e	1423	* @arg RCC_FLAG_PORRST: POR/PDR reset.
mbed_official	630:825f75ca301e	1424	* @arg RCC_FLAG_SFTRST: Software reset.
mbed_official	630:825f75ca301e	1425	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
mbed_official	630:825f75ca301e	1426	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
mbed_official	630:825f75ca301e	1427	* @arg RCC_FLAG_LPWRRST: Low Power reset.
mbed_official	340:28d1f895c6fe	1428	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	340:28d1f895c6fe	1429	*/
mbed_official	340:28d1f895c6fe	1430	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
mbed_official	340:28d1f895c6fe	1431	(((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
mbed_official	340:28d1f895c6fe	1432	(((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
mbed_official	340:28d1f895c6fe	1433	RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
mbed_official	340:28d1f895c6fe	1434
mbed_official	630:825f75ca301e	1435	/**
mbed_official	630:825f75ca301e	1436	* @}
mbed_official	630:825f75ca301e	1437	*/
mbed_official	340:28d1f895c6fe	1438
mbed_official	340:28d1f895c6fe	1439	/**
mbed_official	340:28d1f895c6fe	1440	* @}
mbed_official	630:825f75ca301e	1441	*/
mbed_official	340:28d1f895c6fe	1442
mbed_official	340:28d1f895c6fe	1443	/* Include RCC HAL Extension module */
mbed_official	340:28d1f895c6fe	1444	#include "stm32f0xx_hal_rcc_ex.h"
mbed_official	340:28d1f895c6fe	1445
mbed_official	340:28d1f895c6fe	1446	/* Exported functions --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1447	/** @addtogroup RCC_Exported_Functions
mbed_official	340:28d1f895c6fe	1448	* @{
mbed_official	340:28d1f895c6fe	1449	*/
mbed_official	340:28d1f895c6fe	1450
mbed_official	340:28d1f895c6fe	1451	/** @addtogroup RCC_Exported_Functions_Group1
mbed_official	340:28d1f895c6fe	1452	* @{
mbed_official	340:28d1f895c6fe	1453	*/
mbed_official	340:28d1f895c6fe	1454
mbed_official	630:825f75ca301e	1455	/* Initialization and de-initialization functions ******************************/
mbed_official	630:825f75ca301e	1456	void HAL_RCC_DeInit(void);
mbed_official	630:825f75ca301e	1457	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	630:825f75ca301e	1458	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	340:28d1f895c6fe	1459
mbed_official	340:28d1f895c6fe	1460	/**
mbed_official	340:28d1f895c6fe	1461	* @}
mbed_official	340:28d1f895c6fe	1462	*/
mbed_official	340:28d1f895c6fe	1463
mbed_official	340:28d1f895c6fe	1464	/** @addtogroup RCC_Exported_Functions_Group2
mbed_official	340:28d1f895c6fe	1465	* @{
mbed_official	340:28d1f895c6fe	1466	*/
mbed_official	630:825f75ca301e	1467
mbed_official	630:825f75ca301e	1468	/* Peripheral Control functions ************************************************/
mbed_official	630:825f75ca301e	1469	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	630:825f75ca301e	1470	void HAL_RCC_EnableCSS(void);
mbed_official	630:825f75ca301e	1471	void HAL_RCC_DisableCSS(void);
mbed_official	630:825f75ca301e	1472	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	630:825f75ca301e	1473	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	630:825f75ca301e	1474	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	630:825f75ca301e	1475	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	630:825f75ca301e	1476	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	340:28d1f895c6fe	1477
mbed_official	340:28d1f895c6fe	1478	/* CSS NMI IRQ handler */
mbed_official	630:825f75ca301e	1479	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	340:28d1f895c6fe	1480
mbed_official	340:28d1f895c6fe	1481	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	630:825f75ca301e	1482	void HAL_RCC_CSSCallback(void);
mbed_official	340:28d1f895c6fe	1483
mbed_official	340:28d1f895c6fe	1484	/**
mbed_official	340:28d1f895c6fe	1485	* @}
mbed_official	340:28d1f895c6fe	1486	*/
mbed_official	340:28d1f895c6fe	1487
mbed_official	340:28d1f895c6fe	1488	/**
mbed_official	340:28d1f895c6fe	1489	* @}
mbed_official	630:825f75ca301e	1490	*/
mbed_official	630:825f75ca301e	1491
mbed_official	630:825f75ca301e	1492	/**
mbed_official	630:825f75ca301e	1493	* @}
mbed_official	630:825f75ca301e	1494	*/
mbed_official	340:28d1f895c6fe	1495
mbed_official	340:28d1f895c6fe	1496	/**
mbed_official	340:28d1f895c6fe	1497	* @}
mbed_official	340:28d1f895c6fe	1498	*/
mbed_official	630:825f75ca301e	1499
mbed_official	340:28d1f895c6fe	1500	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	1501	}
mbed_official	340:28d1f895c6fe	1502	#endif
mbed_official	340:28d1f895c6fe	1503
mbed_official	340:28d1f895c6fe	1504	#endif /* __STM32F0xx_HAL_RCC_H */
mbed_official	340:28d1f895c6fe	1505
mbed_official	340:28d1f895c6fe	1506	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	340:28d1f895c6fe	1507

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Type:	Library
Created:	02 Nov 2015
Imports:	14
Forks:	0
Commits:	637
Dependents:	2
Dependencies:	0
Followers:	5

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h@630:825f75ca301e, 2015-09-28 (annotated)

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