Modified version of the mbed library for use with the Nucleo boards.
Dependents: EEPROMWrite Full-Project
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c@630:825f75ca301e, 2015-09-28 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Sep 28 10:45:10 2015 +0100
- Revision:
- 630:825f75ca301e
- Parent:
- 441:d2c15dda23c1
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10
Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/
NUCLEO_F031K6 : Add new target
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 340:28d1f895c6fe | 1 | /** |
mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_pwr.c |
mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
mbed_official | 630:825f75ca301e | 5 | * @version V1.3.0 |
mbed_official | 630:825f75ca301e | 6 | * @date 26-June-2015 |
mbed_official | 340:28d1f895c6fe | 7 | * @brief PWR HAL module driver. |
mbed_official | 340:28d1f895c6fe | 8 | * This file provides firmware functions to manage the following |
mbed_official | 340:28d1f895c6fe | 9 | * functionalities of the Power Controller (PWR) peripheral: |
mbed_official | 340:28d1f895c6fe | 10 | * + Initialization/de-initialization function |
mbed_official | 340:28d1f895c6fe | 11 | * + Peripheral Control function |
mbed_official | 340:28d1f895c6fe | 12 | * |
mbed_official | 340:28d1f895c6fe | 13 | @verbatim |
mbed_official | 340:28d1f895c6fe | 14 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 15 | * @attention |
mbed_official | 340:28d1f895c6fe | 16 | * |
mbed_official | 630:825f75ca301e | 17 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
mbed_official | 340:28d1f895c6fe | 18 | * |
mbed_official | 340:28d1f895c6fe | 19 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 340:28d1f895c6fe | 20 | * are permitted provided that the following conditions are met: |
mbed_official | 340:28d1f895c6fe | 21 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 340:28d1f895c6fe | 22 | * this list of conditions and the following disclaimer. |
mbed_official | 340:28d1f895c6fe | 23 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 340:28d1f895c6fe | 24 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 340:28d1f895c6fe | 25 | * and/or other materials provided with the distribution. |
mbed_official | 340:28d1f895c6fe | 26 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 340:28d1f895c6fe | 27 | * may be used to endorse or promote products derived from this software |
mbed_official | 340:28d1f895c6fe | 28 | * without specific prior written permission. |
mbed_official | 340:28d1f895c6fe | 29 | * |
mbed_official | 340:28d1f895c6fe | 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 340:28d1f895c6fe | 31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 340:28d1f895c6fe | 32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 340:28d1f895c6fe | 33 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 340:28d1f895c6fe | 34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 340:28d1f895c6fe | 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 340:28d1f895c6fe | 36 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 340:28d1f895c6fe | 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 340:28d1f895c6fe | 38 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 340:28d1f895c6fe | 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 340:28d1f895c6fe | 40 | * |
mbed_official | 340:28d1f895c6fe | 41 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 42 | */ |
mbed_official | 340:28d1f895c6fe | 43 | |
mbed_official | 340:28d1f895c6fe | 44 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 45 | #include "stm32f0xx_hal.h" |
mbed_official | 340:28d1f895c6fe | 46 | |
mbed_official | 340:28d1f895c6fe | 47 | /** @addtogroup STM32F0xx_HAL_Driver |
mbed_official | 340:28d1f895c6fe | 48 | * @{ |
mbed_official | 340:28d1f895c6fe | 49 | */ |
mbed_official | 340:28d1f895c6fe | 50 | |
mbed_official | 630:825f75ca301e | 51 | /** @defgroup PWR PWR |
mbed_official | 340:28d1f895c6fe | 52 | * @brief PWR HAL module driver |
mbed_official | 340:28d1f895c6fe | 53 | * @{ |
mbed_official | 340:28d1f895c6fe | 54 | */ |
mbed_official | 340:28d1f895c6fe | 55 | |
mbed_official | 340:28d1f895c6fe | 56 | #ifdef HAL_PWR_MODULE_ENABLED |
mbed_official | 340:28d1f895c6fe | 57 | |
mbed_official | 340:28d1f895c6fe | 58 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 59 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 60 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 61 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 62 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 63 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 64 | |
mbed_official | 340:28d1f895c6fe | 65 | /** @defgroup PWR_Exported_Functions PWR Exported Functions |
mbed_official | 340:28d1f895c6fe | 66 | * @{ |
mbed_official | 340:28d1f895c6fe | 67 | */ |
mbed_official | 340:28d1f895c6fe | 68 | |
mbed_official | 340:28d1f895c6fe | 69 | /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
mbed_official | 340:28d1f895c6fe | 70 | * @brief Initialization and de-initialization functions |
mbed_official | 340:28d1f895c6fe | 71 | * |
mbed_official | 340:28d1f895c6fe | 72 | @verbatim |
mbed_official | 340:28d1f895c6fe | 73 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 74 | ##### Initialization and de-initialization functions ##### |
mbed_official | 340:28d1f895c6fe | 75 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 76 | [..] |
mbed_official | 340:28d1f895c6fe | 77 | After reset, the backup domain (RTC registers, RTC backup data |
mbed_official | 340:28d1f895c6fe | 78 | registers) is protected against possible unwanted |
mbed_official | 340:28d1f895c6fe | 79 | write accesses. |
mbed_official | 340:28d1f895c6fe | 80 | To enable access to the RTC Domain and RTC registers, proceed as follows: |
mbed_official | 340:28d1f895c6fe | 81 | (+) Enable the Power Controller (PWR) APB1 interface clock using the |
mbed_official | 630:825f75ca301e | 82 | __HAL_RCC_PWR_CLK_ENABLE() macro. |
mbed_official | 340:28d1f895c6fe | 83 | (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
mbed_official | 340:28d1f895c6fe | 84 | |
mbed_official | 340:28d1f895c6fe | 85 | @endverbatim |
mbed_official | 340:28d1f895c6fe | 86 | * @{ |
mbed_official | 340:28d1f895c6fe | 87 | */ |
mbed_official | 340:28d1f895c6fe | 88 | |
mbed_official | 340:28d1f895c6fe | 89 | /** |
mbed_official | 340:28d1f895c6fe | 90 | * @brief Deinitializes the PWR peripheral registers to their default reset values. |
mbed_official | 340:28d1f895c6fe | 91 | * @retval None |
mbed_official | 340:28d1f895c6fe | 92 | */ |
mbed_official | 340:28d1f895c6fe | 93 | void HAL_PWR_DeInit(void) |
mbed_official | 340:28d1f895c6fe | 94 | { |
mbed_official | 630:825f75ca301e | 95 | __HAL_RCC_PWR_FORCE_RESET(); |
mbed_official | 630:825f75ca301e | 96 | __HAL_RCC_PWR_RELEASE_RESET(); |
mbed_official | 340:28d1f895c6fe | 97 | } |
mbed_official | 340:28d1f895c6fe | 98 | |
mbed_official | 340:28d1f895c6fe | 99 | /** |
mbed_official | 340:28d1f895c6fe | 100 | * @brief Enables access to the backup domain (RTC registers, RTC |
mbed_official | 630:825f75ca301e | 101 | * backup data registers when present). |
mbed_official | 340:28d1f895c6fe | 102 | * @note If the HSE divided by 32 is used as the RTC clock, the |
mbed_official | 340:28d1f895c6fe | 103 | * Backup Domain Access should be kept enabled. |
mbed_official | 340:28d1f895c6fe | 104 | * @retval None |
mbed_official | 340:28d1f895c6fe | 105 | */ |
mbed_official | 340:28d1f895c6fe | 106 | void HAL_PWR_EnableBkUpAccess(void) |
mbed_official | 340:28d1f895c6fe | 107 | { |
mbed_official | 340:28d1f895c6fe | 108 | PWR->CR |= (uint32_t)PWR_CR_DBP; |
mbed_official | 340:28d1f895c6fe | 109 | } |
mbed_official | 340:28d1f895c6fe | 110 | |
mbed_official | 340:28d1f895c6fe | 111 | /** |
mbed_official | 340:28d1f895c6fe | 112 | * @brief Disables access to the backup domain (RTC registers, RTC |
mbed_official | 630:825f75ca301e | 113 | * backup data registers when present). |
mbed_official | 340:28d1f895c6fe | 114 | * @note If the HSE divided by 32 is used as the RTC clock, the |
mbed_official | 340:28d1f895c6fe | 115 | * Backup Domain Access should be kept enabled. |
mbed_official | 340:28d1f895c6fe | 116 | * @retval None |
mbed_official | 340:28d1f895c6fe | 117 | */ |
mbed_official | 340:28d1f895c6fe | 118 | void HAL_PWR_DisableBkUpAccess(void) |
mbed_official | 340:28d1f895c6fe | 119 | { |
mbed_official | 340:28d1f895c6fe | 120 | PWR->CR &= ~((uint32_t)PWR_CR_DBP); |
mbed_official | 340:28d1f895c6fe | 121 | } |
mbed_official | 340:28d1f895c6fe | 122 | |
mbed_official | 340:28d1f895c6fe | 123 | /** |
mbed_official | 340:28d1f895c6fe | 124 | * @} |
mbed_official | 340:28d1f895c6fe | 125 | */ |
mbed_official | 340:28d1f895c6fe | 126 | |
mbed_official | 340:28d1f895c6fe | 127 | /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions |
mbed_official | 340:28d1f895c6fe | 128 | * @brief Low Power modes configuration functions |
mbed_official | 340:28d1f895c6fe | 129 | * |
mbed_official | 340:28d1f895c6fe | 130 | @verbatim |
mbed_official | 340:28d1f895c6fe | 131 | |
mbed_official | 340:28d1f895c6fe | 132 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 133 | ##### Peripheral Control functions ##### |
mbed_official | 340:28d1f895c6fe | 134 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 135 | |
mbed_official | 340:28d1f895c6fe | 136 | *** WakeUp pin configuration *** |
mbed_official | 340:28d1f895c6fe | 137 | ================================ |
mbed_official | 340:28d1f895c6fe | 138 | [..] |
mbed_official | 340:28d1f895c6fe | 139 | (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is |
mbed_official | 340:28d1f895c6fe | 140 | forced in input pull down configuration and is active on rising edges. |
mbed_official | 340:28d1f895c6fe | 141 | (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. |
mbed_official | 340:28d1f895c6fe | 142 | (++)WakeUp Pin 1 on PA.00. |
mbed_official | 340:28d1f895c6fe | 143 | (++)WakeUp Pin 2 on PC.13. |
mbed_official | 340:28d1f895c6fe | 144 | (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) |
mbed_official | 340:28d1f895c6fe | 145 | (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) |
mbed_official | 340:28d1f895c6fe | 146 | (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) |
mbed_official | 340:28d1f895c6fe | 147 | (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) |
mbed_official | 340:28d1f895c6fe | 148 | (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) |
mbed_official | 340:28d1f895c6fe | 149 | (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) |
mbed_official | 340:28d1f895c6fe | 150 | |
mbed_official | 340:28d1f895c6fe | 151 | *** Low Power modes configuration *** |
mbed_official | 340:28d1f895c6fe | 152 | ===================================== |
mbed_official | 340:28d1f895c6fe | 153 | [..] |
mbed_official | 340:28d1f895c6fe | 154 | The devices feature 3 low-power modes: |
mbed_official | 340:28d1f895c6fe | 155 | (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. |
mbed_official | 340:28d1f895c6fe | 156 | (+) Stop mode: all clocks are stopped, regulator running, regulator |
mbed_official | 340:28d1f895c6fe | 157 | in low power mode |
mbed_official | 340:28d1f895c6fe | 158 | (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). |
mbed_official | 340:28d1f895c6fe | 159 | |
mbed_official | 340:28d1f895c6fe | 160 | *** Sleep mode *** |
mbed_official | 340:28d1f895c6fe | 161 | ================== |
mbed_official | 340:28d1f895c6fe | 162 | [..] |
mbed_official | 340:28d1f895c6fe | 163 | (+) Entry: |
mbed_official | 340:28d1f895c6fe | 164 | The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
mbed_official | 340:28d1f895c6fe | 165 | functions with |
mbed_official | 340:28d1f895c6fe | 166 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
mbed_official | 340:28d1f895c6fe | 167 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
mbed_official | 340:28d1f895c6fe | 168 | |
mbed_official | 340:28d1f895c6fe | 169 | (+) Exit: |
mbed_official | 340:28d1f895c6fe | 170 | (++) Any peripheral interrupt acknowledged by the nested vectored interrupt |
mbed_official | 340:28d1f895c6fe | 171 | controller (NVIC) can wake up the device from Sleep mode. |
mbed_official | 340:28d1f895c6fe | 172 | |
mbed_official | 340:28d1f895c6fe | 173 | *** Stop mode *** |
mbed_official | 340:28d1f895c6fe | 174 | ================= |
mbed_official | 340:28d1f895c6fe | 175 | [..] |
mbed_official | 340:28d1f895c6fe | 176 | In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, |
mbed_official | 340:28d1f895c6fe | 177 | and the HSE RC oscillators are disabled. Internal SRAM and register contents |
mbed_official | 340:28d1f895c6fe | 178 | are preserved. |
mbed_official | 340:28d1f895c6fe | 179 | The voltage regulator can be configured either in normal or low-power mode. |
mbed_official | 340:28d1f895c6fe | 180 | To minimize the consumption. |
mbed_official | 340:28d1f895c6fe | 181 | |
mbed_official | 340:28d1f895c6fe | 182 | (+) Entry: |
mbed_official | 340:28d1f895c6fe | 183 | The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) |
mbed_official | 340:28d1f895c6fe | 184 | function with: |
mbed_official | 340:28d1f895c6fe | 185 | (++) Main regulator ON. |
mbed_official | 340:28d1f895c6fe | 186 | (++) Low Power regulator ON. |
mbed_official | 340:28d1f895c6fe | 187 | (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction |
mbed_official | 340:28d1f895c6fe | 188 | (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction |
mbed_official | 340:28d1f895c6fe | 189 | (+) Exit: |
mbed_official | 340:28d1f895c6fe | 190 | (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. |
mbed_official | 340:28d1f895c6fe | 191 | (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, |
mbed_official | 340:28d1f895c6fe | 192 | when programmed in wakeup mode (the peripheral must be |
mbed_official | 340:28d1f895c6fe | 193 | programmed in wakeup mode and the corresponding interrupt vector |
mbed_official | 340:28d1f895c6fe | 194 | must be enabled in the NVIC) |
mbed_official | 340:28d1f895c6fe | 195 | |
mbed_official | 340:28d1f895c6fe | 196 | *** Standby mode *** |
mbed_official | 340:28d1f895c6fe | 197 | ==================== |
mbed_official | 340:28d1f895c6fe | 198 | [..] |
mbed_official | 340:28d1f895c6fe | 199 | The Standby mode allows to achieve the lowest power consumption. It is based |
mbed_official | 340:28d1f895c6fe | 200 | on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. |
mbed_official | 340:28d1f895c6fe | 201 | The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and |
mbed_official | 340:28d1f895c6fe | 202 | the HSE oscillator are also switched off. SRAM and register contents are lost |
mbed_official | 340:28d1f895c6fe | 203 | except for the RTC registers, RTC backup registers and Standby circuitry. |
mbed_official | 340:28d1f895c6fe | 204 | The voltage regulator is OFF. |
mbed_official | 340:28d1f895c6fe | 205 | |
mbed_official | 340:28d1f895c6fe | 206 | (+) Entry: |
mbed_official | 340:28d1f895c6fe | 207 | (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
mbed_official | 340:28d1f895c6fe | 208 | (+) Exit: |
mbed_official | 340:28d1f895c6fe | 209 | (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, |
mbed_official | 340:28d1f895c6fe | 210 | tamper event, time-stamp event, external reset in NRST pin, IWDG reset. |
mbed_official | 340:28d1f895c6fe | 211 | |
mbed_official | 340:28d1f895c6fe | 212 | *** Auto-wakeup (AWU) from low-power mode *** |
mbed_official | 340:28d1f895c6fe | 213 | ============================================= |
mbed_official | 340:28d1f895c6fe | 214 | [..] |
mbed_official | 340:28d1f895c6fe | 215 | The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC |
mbed_official | 340:28d1f895c6fe | 216 | Wakeup event, a tamper event, a time-stamp event, or a comparator event, |
mbed_official | 340:28d1f895c6fe | 217 | without depending on an external interrupt (Auto-wakeup mode). |
mbed_official | 340:28d1f895c6fe | 218 | |
mbed_official | 340:28d1f895c6fe | 219 | (+) RTC auto-wakeup (AWU) from the Stop and Standby modes |
mbed_official | 340:28d1f895c6fe | 220 | |
mbed_official | 340:28d1f895c6fe | 221 | (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to |
mbed_official | 340:28d1f895c6fe | 222 | configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. |
mbed_official | 340:28d1f895c6fe | 223 | |
mbed_official | 340:28d1f895c6fe | 224 | (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it |
mbed_official | 340:28d1f895c6fe | 225 | is necessary to configure the RTC to detect the tamper or time stamp event using the |
mbed_official | 340:28d1f895c6fe | 226 | HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. |
mbed_official | 340:28d1f895c6fe | 227 | |
mbed_official | 340:28d1f895c6fe | 228 | (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to |
mbed_official | 340:28d1f895c6fe | 229 | configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. |
mbed_official | 340:28d1f895c6fe | 230 | |
mbed_official | 340:28d1f895c6fe | 231 | (+) Comparator auto-wakeup (AWU) from the Stop mode |
mbed_official | 340:28d1f895c6fe | 232 | |
mbed_official | 340:28d1f895c6fe | 233 | (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: |
mbed_official | 340:28d1f895c6fe | 234 | (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) |
mbed_official | 340:28d1f895c6fe | 235 | to be sensitive to to the selected edges (falling, rising or falling |
mbed_official | 340:28d1f895c6fe | 236 | and rising) (Interrupt or Event modes) using the EXTI_Init() function. |
mbed_official | 340:28d1f895c6fe | 237 | (+++) Configure the comparator to generate the event. |
mbed_official | 340:28d1f895c6fe | 238 | @endverbatim |
mbed_official | 340:28d1f895c6fe | 239 | * @{ |
mbed_official | 340:28d1f895c6fe | 240 | */ |
mbed_official | 340:28d1f895c6fe | 241 | |
mbed_official | 340:28d1f895c6fe | 242 | /** |
mbed_official | 340:28d1f895c6fe | 243 | * @brief Enables the WakeUp PINx functionality. |
mbed_official | 340:28d1f895c6fe | 244 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
mbed_official | 340:28d1f895c6fe | 245 | * This parameter can be value of : |
mbed_official | 340:28d1f895c6fe | 246 | * @ref PWREx_WakeUp_Pins |
mbed_official | 340:28d1f895c6fe | 247 | * @retval None |
mbed_official | 340:28d1f895c6fe | 248 | */ |
mbed_official | 340:28d1f895c6fe | 249 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
mbed_official | 340:28d1f895c6fe | 250 | { |
mbed_official | 340:28d1f895c6fe | 251 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 252 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
mbed_official | 340:28d1f895c6fe | 253 | PWR->CSR |= (PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx); |
mbed_official | 340:28d1f895c6fe | 254 | } |
mbed_official | 340:28d1f895c6fe | 255 | |
mbed_official | 340:28d1f895c6fe | 256 | /** |
mbed_official | 340:28d1f895c6fe | 257 | * @brief Disables the WakeUp PINx functionality. |
mbed_official | 340:28d1f895c6fe | 258 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
mbed_official | 340:28d1f895c6fe | 259 | * This parameter can be values of : |
mbed_official | 340:28d1f895c6fe | 260 | * @ref PWREx_WakeUp_Pins |
mbed_official | 340:28d1f895c6fe | 261 | * @retval None |
mbed_official | 340:28d1f895c6fe | 262 | */ |
mbed_official | 340:28d1f895c6fe | 263 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
mbed_official | 340:28d1f895c6fe | 264 | { |
mbed_official | 340:28d1f895c6fe | 265 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 266 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
mbed_official | 340:28d1f895c6fe | 267 | PWR->CSR &= ~(PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx); |
mbed_official | 340:28d1f895c6fe | 268 | } |
mbed_official | 340:28d1f895c6fe | 269 | |
mbed_official | 340:28d1f895c6fe | 270 | /** |
mbed_official | 340:28d1f895c6fe | 271 | * @brief Enters Sleep mode. |
mbed_official | 340:28d1f895c6fe | 272 | * @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
mbed_official | 340:28d1f895c6fe | 273 | * @param Regulator: Specifies the regulator state in SLEEP mode. |
mbed_official | 441:d2c15dda23c1 | 274 | * On STM32F0 devices, this parameter is a dummy value and it is ignored |
mbed_official | 441:d2c15dda23c1 | 275 | * as regulator can't be modified in this mode. Parameter is kept for platform |
mbed_official | 441:d2c15dda23c1 | 276 | * compatibility. |
mbed_official | 340:28d1f895c6fe | 277 | * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
mbed_official | 340:28d1f895c6fe | 278 | * When WFI entry is used, tick interrupt have to be disabled if not desired as |
mbed_official | 340:28d1f895c6fe | 279 | * the interrupt wake up source. |
mbed_official | 340:28d1f895c6fe | 280 | * This parameter can be one of the following values: |
mbed_official | 340:28d1f895c6fe | 281 | * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
mbed_official | 340:28d1f895c6fe | 282 | * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
mbed_official | 340:28d1f895c6fe | 283 | * @retval None |
mbed_official | 340:28d1f895c6fe | 284 | */ |
mbed_official | 340:28d1f895c6fe | 285 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
mbed_official | 340:28d1f895c6fe | 286 | { |
mbed_official | 340:28d1f895c6fe | 287 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 288 | assert_param(IS_PWR_REGULATOR(Regulator)); |
mbed_official | 340:28d1f895c6fe | 289 | assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
mbed_official | 340:28d1f895c6fe | 290 | |
mbed_official | 340:28d1f895c6fe | 291 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
mbed_official | 340:28d1f895c6fe | 292 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); |
mbed_official | 340:28d1f895c6fe | 293 | |
mbed_official | 340:28d1f895c6fe | 294 | /* Select SLEEP mode entry -------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 295 | if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
mbed_official | 340:28d1f895c6fe | 296 | { |
mbed_official | 340:28d1f895c6fe | 297 | /* Request Wait For Interrupt */ |
mbed_official | 340:28d1f895c6fe | 298 | __WFI(); |
mbed_official | 340:28d1f895c6fe | 299 | } |
mbed_official | 340:28d1f895c6fe | 300 | else |
mbed_official | 340:28d1f895c6fe | 301 | { |
mbed_official | 340:28d1f895c6fe | 302 | /* Request Wait For Event */ |
mbed_official | 340:28d1f895c6fe | 303 | __SEV(); |
mbed_official | 340:28d1f895c6fe | 304 | __WFE(); |
mbed_official | 340:28d1f895c6fe | 305 | __WFE(); |
mbed_official | 340:28d1f895c6fe | 306 | } |
mbed_official | 340:28d1f895c6fe | 307 | } |
mbed_official | 340:28d1f895c6fe | 308 | |
mbed_official | 340:28d1f895c6fe | 309 | /** |
mbed_official | 340:28d1f895c6fe | 310 | * @brief Enters STOP mode. |
mbed_official | 340:28d1f895c6fe | 311 | * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
mbed_official | 340:28d1f895c6fe | 312 | * @note When exiting Stop mode by issuing an interrupt or a wakeup event, |
mbed_official | 340:28d1f895c6fe | 313 | * the HSI RC oscillator is selected as system clock. |
mbed_official | 340:28d1f895c6fe | 314 | * @note When the voltage regulator operates in low power mode, an additional |
mbed_official | 340:28d1f895c6fe | 315 | * startup delay is incurred when waking up from Stop mode. |
mbed_official | 340:28d1f895c6fe | 316 | * By keeping the internal regulator ON during Stop mode, the consumption |
mbed_official | 340:28d1f895c6fe | 317 | * is higher although the startup time is reduced. |
mbed_official | 340:28d1f895c6fe | 318 | * @param Regulator: Specifies the regulator state in STOP mode. |
mbed_official | 340:28d1f895c6fe | 319 | * This parameter can be one of the following values: |
mbed_official | 340:28d1f895c6fe | 320 | * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON |
mbed_official | 340:28d1f895c6fe | 321 | * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON |
mbed_official | 340:28d1f895c6fe | 322 | * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. |
mbed_official | 340:28d1f895c6fe | 323 | * This parameter can be one of the following values: |
mbed_official | 340:28d1f895c6fe | 324 | * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction |
mbed_official | 340:28d1f895c6fe | 325 | * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction |
mbed_official | 340:28d1f895c6fe | 326 | * @retval None |
mbed_official | 340:28d1f895c6fe | 327 | */ |
mbed_official | 340:28d1f895c6fe | 328 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
mbed_official | 340:28d1f895c6fe | 329 | { |
mbed_official | 340:28d1f895c6fe | 330 | uint32_t tmpreg = 0; |
mbed_official | 340:28d1f895c6fe | 331 | |
mbed_official | 340:28d1f895c6fe | 332 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 333 | assert_param(IS_PWR_REGULATOR(Regulator)); |
mbed_official | 340:28d1f895c6fe | 334 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
mbed_official | 340:28d1f895c6fe | 335 | |
mbed_official | 340:28d1f895c6fe | 336 | /* Select the regulator state in STOP mode ---------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 337 | tmpreg = PWR->CR; |
mbed_official | 340:28d1f895c6fe | 338 | |
mbed_official | 340:28d1f895c6fe | 339 | /* Clear PDDS and LPDS bits */ |
mbed_official | 340:28d1f895c6fe | 340 | tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); |
mbed_official | 340:28d1f895c6fe | 341 | |
mbed_official | 340:28d1f895c6fe | 342 | /* Set LPDS bit according to Regulator value */ |
mbed_official | 340:28d1f895c6fe | 343 | tmpreg |= Regulator; |
mbed_official | 340:28d1f895c6fe | 344 | |
mbed_official | 340:28d1f895c6fe | 345 | /* Store the new value */ |
mbed_official | 340:28d1f895c6fe | 346 | PWR->CR = tmpreg; |
mbed_official | 340:28d1f895c6fe | 347 | |
mbed_official | 340:28d1f895c6fe | 348 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
mbed_official | 340:28d1f895c6fe | 349 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
mbed_official | 340:28d1f895c6fe | 350 | |
mbed_official | 340:28d1f895c6fe | 351 | /* Select STOP mode entry --------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 352 | if(STOPEntry == PWR_STOPENTRY_WFI) |
mbed_official | 340:28d1f895c6fe | 353 | { |
mbed_official | 340:28d1f895c6fe | 354 | /* Request Wait For Interrupt */ |
mbed_official | 340:28d1f895c6fe | 355 | __WFI(); |
mbed_official | 340:28d1f895c6fe | 356 | } |
mbed_official | 340:28d1f895c6fe | 357 | else |
mbed_official | 340:28d1f895c6fe | 358 | { |
mbed_official | 340:28d1f895c6fe | 359 | /* Request Wait For Event */ |
mbed_official | 340:28d1f895c6fe | 360 | __SEV(); |
mbed_official | 340:28d1f895c6fe | 361 | __WFE(); |
mbed_official | 340:28d1f895c6fe | 362 | __WFE(); |
mbed_official | 340:28d1f895c6fe | 363 | } |
mbed_official | 340:28d1f895c6fe | 364 | |
mbed_official | 340:28d1f895c6fe | 365 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
mbed_official | 340:28d1f895c6fe | 366 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); |
mbed_official | 340:28d1f895c6fe | 367 | } |
mbed_official | 340:28d1f895c6fe | 368 | |
mbed_official | 340:28d1f895c6fe | 369 | /** |
mbed_official | 340:28d1f895c6fe | 370 | * @brief Enters STANDBY mode. |
mbed_official | 340:28d1f895c6fe | 371 | * @note In Standby mode, all I/O pins are high impedance except for: |
mbed_official | 340:28d1f895c6fe | 372 | * - Reset pad (still available) |
mbed_official | 340:28d1f895c6fe | 373 | * - RTC alternate function pins if configured for tamper, time-stamp, RTC |
mbed_official | 340:28d1f895c6fe | 374 | * Alarm out, or RTC clock calibration out. |
mbed_official | 340:28d1f895c6fe | 375 | * - WKUP pins if enabled. |
mbed_official | 340:28d1f895c6fe | 376 | * STM32F0x8 devices, the Stop mode is available, but it is |
mbed_official | 340:28d1f895c6fe | 377 | * aningless to distinguish between voltage regulator in Low power |
mbed_official | 340:28d1f895c6fe | 378 | * mode and voltage regulator in Run mode because the regulator |
mbed_official | 340:28d1f895c6fe | 379 | * not used and the core is supplied directly from an external source. |
mbed_official | 340:28d1f895c6fe | 380 | * Consequently, the Standby mode is not available on those devices. |
mbed_official | 340:28d1f895c6fe | 381 | * @retval None |
mbed_official | 340:28d1f895c6fe | 382 | */ |
mbed_official | 340:28d1f895c6fe | 383 | void HAL_PWR_EnterSTANDBYMode(void) |
mbed_official | 340:28d1f895c6fe | 384 | { |
mbed_official | 340:28d1f895c6fe | 385 | /* Select STANDBY mode */ |
mbed_official | 340:28d1f895c6fe | 386 | PWR->CR |= (uint32_t)PWR_CR_PDDS; |
mbed_official | 340:28d1f895c6fe | 387 | |
mbed_official | 340:28d1f895c6fe | 388 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
mbed_official | 340:28d1f895c6fe | 389 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
mbed_official | 340:28d1f895c6fe | 390 | |
mbed_official | 340:28d1f895c6fe | 391 | /* This option is used to ensure that store operations are completed */ |
mbed_official | 340:28d1f895c6fe | 392 | #if defined ( __CC_ARM) |
mbed_official | 340:28d1f895c6fe | 393 | __force_stores(); |
mbed_official | 340:28d1f895c6fe | 394 | #endif |
mbed_official | 340:28d1f895c6fe | 395 | /* Request Wait For Interrupt */ |
mbed_official | 340:28d1f895c6fe | 396 | __WFI(); |
mbed_official | 340:28d1f895c6fe | 397 | } |
mbed_official | 340:28d1f895c6fe | 398 | |
mbed_official | 340:28d1f895c6fe | 399 | /** |
mbed_official | 441:d2c15dda23c1 | 400 | * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. |
mbed_official | 441:d2c15dda23c1 | 401 | * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
mbed_official | 441:d2c15dda23c1 | 402 | * re-enters SLEEP mode when an interruption handling is over. |
mbed_official | 441:d2c15dda23c1 | 403 | * Setting this bit is useful when the processor is expected to run only on |
mbed_official | 441:d2c15dda23c1 | 404 | * interruptions handling. |
mbed_official | 441:d2c15dda23c1 | 405 | * @retval None |
mbed_official | 441:d2c15dda23c1 | 406 | */ |
mbed_official | 441:d2c15dda23c1 | 407 | void HAL_PWR_EnableSleepOnExit(void) |
mbed_official | 441:d2c15dda23c1 | 408 | { |
mbed_official | 441:d2c15dda23c1 | 409 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
mbed_official | 441:d2c15dda23c1 | 410 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
mbed_official | 441:d2c15dda23c1 | 411 | } |
mbed_official | 441:d2c15dda23c1 | 412 | |
mbed_official | 441:d2c15dda23c1 | 413 | |
mbed_official | 441:d2c15dda23c1 | 414 | /** |
mbed_official | 441:d2c15dda23c1 | 415 | * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. |
mbed_official | 441:d2c15dda23c1 | 416 | * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
mbed_official | 441:d2c15dda23c1 | 417 | * re-enters SLEEP mode when an interruption handling is over. |
mbed_official | 441:d2c15dda23c1 | 418 | * @retval None |
mbed_official | 441:d2c15dda23c1 | 419 | */ |
mbed_official | 441:d2c15dda23c1 | 420 | void HAL_PWR_DisableSleepOnExit(void) |
mbed_official | 441:d2c15dda23c1 | 421 | { |
mbed_official | 441:d2c15dda23c1 | 422 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
mbed_official | 441:d2c15dda23c1 | 423 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
mbed_official | 441:d2c15dda23c1 | 424 | } |
mbed_official | 441:d2c15dda23c1 | 425 | |
mbed_official | 441:d2c15dda23c1 | 426 | |
mbed_official | 441:d2c15dda23c1 | 427 | |
mbed_official | 441:d2c15dda23c1 | 428 | /** |
mbed_official | 441:d2c15dda23c1 | 429 | * @brief Enables CORTEX M4 SEVONPEND bit. |
mbed_official | 441:d2c15dda23c1 | 430 | * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes |
mbed_official | 441:d2c15dda23c1 | 431 | * WFE to wake up when an interrupt moves from inactive to pended. |
mbed_official | 441:d2c15dda23c1 | 432 | * @retval None |
mbed_official | 441:d2c15dda23c1 | 433 | */ |
mbed_official | 441:d2c15dda23c1 | 434 | void HAL_PWR_EnableSEVOnPend(void) |
mbed_official | 441:d2c15dda23c1 | 435 | { |
mbed_official | 441:d2c15dda23c1 | 436 | /* Set SEVONPEND bit of Cortex System Control Register */ |
mbed_official | 441:d2c15dda23c1 | 437 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
mbed_official | 441:d2c15dda23c1 | 438 | } |
mbed_official | 441:d2c15dda23c1 | 439 | |
mbed_official | 441:d2c15dda23c1 | 440 | |
mbed_official | 441:d2c15dda23c1 | 441 | /** |
mbed_official | 441:d2c15dda23c1 | 442 | * @brief Disables CORTEX M4 SEVONPEND bit. |
mbed_official | 441:d2c15dda23c1 | 443 | * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes |
mbed_official | 441:d2c15dda23c1 | 444 | * WFE to wake up when an interrupt moves from inactive to pended. |
mbed_official | 441:d2c15dda23c1 | 445 | * @retval None |
mbed_official | 441:d2c15dda23c1 | 446 | */ |
mbed_official | 441:d2c15dda23c1 | 447 | void HAL_PWR_DisableSEVOnPend(void) |
mbed_official | 441:d2c15dda23c1 | 448 | { |
mbed_official | 441:d2c15dda23c1 | 449 | /* Clear SEVONPEND bit of Cortex System Control Register */ |
mbed_official | 441:d2c15dda23c1 | 450 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
mbed_official | 441:d2c15dda23c1 | 451 | } |
mbed_official | 441:d2c15dda23c1 | 452 | |
mbed_official | 441:d2c15dda23c1 | 453 | /** |
mbed_official | 340:28d1f895c6fe | 454 | * @} |
mbed_official | 340:28d1f895c6fe | 455 | */ |
mbed_official | 340:28d1f895c6fe | 456 | |
mbed_official | 340:28d1f895c6fe | 457 | /** |
mbed_official | 340:28d1f895c6fe | 458 | * @} |
mbed_official | 340:28d1f895c6fe | 459 | */ |
mbed_official | 340:28d1f895c6fe | 460 | |
mbed_official | 340:28d1f895c6fe | 461 | #endif /* HAL_PWR_MODULE_ENABLED */ |
mbed_official | 340:28d1f895c6fe | 462 | /** |
mbed_official | 340:28d1f895c6fe | 463 | * @} |
mbed_official | 340:28d1f895c6fe | 464 | */ |
mbed_official | 340:28d1f895c6fe | 465 | |
mbed_official | 340:28d1f895c6fe | 466 | /** |
mbed_official | 340:28d1f895c6fe | 467 | * @} |
mbed_official | 340:28d1f895c6fe | 468 | */ |
mbed_official | 340:28d1f895c6fe | 469 | |
mbed_official | 340:28d1f895c6fe | 470 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |