Flotsam / mbed-modifed

Modified version of the mbed library for use with the Nucleo boards.

Dependents:   EEPROMWrite Full-Project

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c@630:825f75ca301e, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 10:45:10 2015 +0100
Revision:
630:825f75ca301e
Parent:
441:d2c15dda23c1 
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10



Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/



NUCLEO_F031K6 : Add new target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file system_stm32f0xx.c
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 630:825f75ca301e 5 * @version V2.2.2
mbed_official 630:825f75ca301e 6 * @date 26-June-2015
mbed_official 340:28d1f895c6fe 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
mbed_official 340:28d1f895c6fe 8 *
mbed_official 340:28d1f895c6fe 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 340:28d1f895c6fe 10 * user application:
mbed_official 340:28d1f895c6fe 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 340:28d1f895c6fe 12 * before branch to main program. This call is made inside
mbed_official 340:28d1f895c6fe 13 * the "startup_stm32f0xx.s" file.
mbed_official 340:28d1f895c6fe 14 *
mbed_official 340:28d1f895c6fe 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 340:28d1f895c6fe 16 * by the user application to setup the SysTick
mbed_official 340:28d1f895c6fe 17 * timer or configure other parameters.
mbed_official 340:28d1f895c6fe 18 *
mbed_official 340:28d1f895c6fe 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 340:28d1f895c6fe 20 * be called whenever the core clock is changed
mbed_official 340:28d1f895c6fe 21 * during program execution.
mbed_official 340:28d1f895c6fe 22 *
mbed_official 340:28d1f895c6fe 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 340:28d1f895c6fe 24 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
mbed_official 340:28d1f895c6fe 25 * configure the system clock before to branch to main program.
mbed_official 340:28d1f895c6fe 26 *
mbed_official 340:28d1f895c6fe 27 * 3. This file configures the system clock as follows:
mbed_official 340:28d1f895c6fe 28 *=============================================================================
mbed_official 340:28d1f895c6fe 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 340:28d1f895c6fe 30 * | (external 8 MHz clock) | (internal 48 MHz)
mbed_official 340:28d1f895c6fe 31 * | 2- PLL_HSE_XTAL |
mbed_official 340:28d1f895c6fe 32 * | (external 8 MHz xtal) |
mbed_official 340:28d1f895c6fe 33 *-----------------------------------------------------------------------------
mbed_official 340:28d1f895c6fe 34 * SYSCLK(MHz) | 48 | 48
mbed_official 340:28d1f895c6fe 35 *-----------------------------------------------------------------------------
mbed_official 340:28d1f895c6fe 36 * AHBCLK (MHz) | 48 | 48
mbed_official 340:28d1f895c6fe 37 *-----------------------------------------------------------------------------
mbed_official 340:28d1f895c6fe 38 * APB1CLK (MHz) | 48 | 48
mbed_official 340:28d1f895c6fe 39 *-----------------------------------------------------------------------------
mbed_official 340:28d1f895c6fe 40 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 340:28d1f895c6fe 41 *=============================================================================
mbed_official 340:28d1f895c6fe 42 ******************************************************************************
mbed_official 340:28d1f895c6fe 43 * @attention
mbed_official 340:28d1f895c6fe 44 *
mbed_official 630:825f75ca301e 45 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 46 *
mbed_official 340:28d1f895c6fe 47 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 48 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 49 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 50 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 52 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 53 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 55 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 56 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 57 *
mbed_official 340:28d1f895c6fe 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 68 *
mbed_official 340:28d1f895c6fe 69 ******************************************************************************
mbed_official 340:28d1f895c6fe 70 */
mbed_official 340:28d1f895c6fe 71
mbed_official 340:28d1f895c6fe 72 /** @addtogroup CMSIS
mbed_official 340:28d1f895c6fe 73 * @{
mbed_official 340:28d1f895c6fe 74 */
mbed_official 340:28d1f895c6fe 75
mbed_official 340:28d1f895c6fe 76 /** @addtogroup stm32f0xx_system
mbed_official 340:28d1f895c6fe 77 * @{
mbed_official 340:28d1f895c6fe 78 */
mbed_official 340:28d1f895c6fe 79
mbed_official 340:28d1f895c6fe 80 /** @addtogroup STM32F0xx_System_Private_Includes
mbed_official 340:28d1f895c6fe 81 * @{
mbed_official 340:28d1f895c6fe 82 */
mbed_official 340:28d1f895c6fe 83
mbed_official 340:28d1f895c6fe 84 #include "stm32f0xx.h"
mbed_official 340:28d1f895c6fe 85
mbed_official 340:28d1f895c6fe 86 /**
mbed_official 340:28d1f895c6fe 87 * @}
mbed_official 340:28d1f895c6fe 88 */
mbed_official 340:28d1f895c6fe 89
mbed_official 340:28d1f895c6fe 90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
mbed_official 340:28d1f895c6fe 91 * @{
mbed_official 340:28d1f895c6fe 92 */
mbed_official 340:28d1f895c6fe 93
mbed_official 340:28d1f895c6fe 94 /**
mbed_official 340:28d1f895c6fe 95 * @}
mbed_official 340:28d1f895c6fe 96 */
mbed_official 340:28d1f895c6fe 97
mbed_official 340:28d1f895c6fe 98 /** @addtogroup STM32F0xx_System_Private_Defines
mbed_official 340:28d1f895c6fe 99 * @{
mbed_official 340:28d1f895c6fe 100 */
mbed_official 340:28d1f895c6fe 101 #if !defined (HSE_VALUE)
mbed_official 340:28d1f895c6fe 102 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 340:28d1f895c6fe 103 This value can be provided and adapted by the user application. */
mbed_official 340:28d1f895c6fe 104 #endif /* HSE_VALUE */
mbed_official 340:28d1f895c6fe 105
mbed_official 340:28d1f895c6fe 106 #if !defined (HSI_VALUE)
mbed_official 340:28d1f895c6fe 107 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 340:28d1f895c6fe 108 This value can be provided and adapted by the user application. */
mbed_official 340:28d1f895c6fe 109 #endif /* HSI_VALUE */
mbed_official 630:825f75ca301e 110
mbed_official 340:28d1f895c6fe 111 /**
mbed_official 340:28d1f895c6fe 112 * @}
mbed_official 340:28d1f895c6fe 113 */
mbed_official 340:28d1f895c6fe 114
mbed_official 340:28d1f895c6fe 115 /** @addtogroup STM32F0xx_System_Private_Macros
mbed_official 340:28d1f895c6fe 116 * @{
mbed_official 340:28d1f895c6fe 117 */
mbed_official 340:28d1f895c6fe 118
mbed_official 340:28d1f895c6fe 119 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 340:28d1f895c6fe 120 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 340:28d1f895c6fe 121 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 340:28d1f895c6fe 122
mbed_official 340:28d1f895c6fe 123 /**
mbed_official 340:28d1f895c6fe 124 * @}
mbed_official 340:28d1f895c6fe 125 */
mbed_official 340:28d1f895c6fe 126
mbed_official 340:28d1f895c6fe 127 /** @addtogroup STM32F0xx_System_Private_Variables
mbed_official 340:28d1f895c6fe 128 * @{
mbed_official 340:28d1f895c6fe 129 */
mbed_official 340:28d1f895c6fe 130 /* This variable is updated in three ways:
mbed_official 340:28d1f895c6fe 131 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 340:28d1f895c6fe 132 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 340:28d1f895c6fe 133 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 340:28d1f895c6fe 134 Note: If you use this function to configure the system clock there is no need to
mbed_official 340:28d1f895c6fe 135 call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official 340:28d1f895c6fe 136 updated automatically.
mbed_official 340:28d1f895c6fe 137 */
mbed_official 340:28d1f895c6fe 138 uint32_t SystemCoreClock = 48000000;
mbed_official 441:d2c15dda23c1 139
mbed_official 340:28d1f895c6fe 140 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 340:28d1f895c6fe 141
mbed_official 340:28d1f895c6fe 142 /**
mbed_official 340:28d1f895c6fe 143 * @}
mbed_official 340:28d1f895c6fe 144 */
mbed_official 340:28d1f895c6fe 145
mbed_official 340:28d1f895c6fe 146 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
mbed_official 340:28d1f895c6fe 147 * @{
mbed_official 340:28d1f895c6fe 148 */
mbed_official 340:28d1f895c6fe 149
mbed_official 340:28d1f895c6fe 150 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 340:28d1f895c6fe 151 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 340:28d1f895c6fe 152 #endif
mbed_official 340:28d1f895c6fe 153
mbed_official 340:28d1f895c6fe 154 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 340:28d1f895c6fe 155
mbed_official 340:28d1f895c6fe 156 /**
mbed_official 340:28d1f895c6fe 157 * @}
mbed_official 340:28d1f895c6fe 158 */
mbed_official 340:28d1f895c6fe 159
mbed_official 340:28d1f895c6fe 160 /** @addtogroup STM32F0xx_System_Private_Functions
mbed_official 340:28d1f895c6fe 161 * @{
mbed_official 340:28d1f895c6fe 162 */
mbed_official 340:28d1f895c6fe 163
mbed_official 340:28d1f895c6fe 164 /**
mbed_official 340:28d1f895c6fe 165 * @brief Setup the microcontroller system.
mbed_official 340:28d1f895c6fe 166 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
mbed_official 340:28d1f895c6fe 167 * @param None
mbed_official 340:28d1f895c6fe 168 * @retval None
mbed_official 340:28d1f895c6fe 169 */
mbed_official 340:28d1f895c6fe 170 void SystemInit(void)
mbed_official 340:28d1f895c6fe 171 {
mbed_official 340:28d1f895c6fe 172 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 340:28d1f895c6fe 173 /* Set HSION bit */
mbed_official 340:28d1f895c6fe 174 RCC->CR |= (uint32_t)0x00000001;
mbed_official 340:28d1f895c6fe 175
mbed_official 340:28d1f895c6fe 176 #if defined (STM32F051x8) || defined (STM32F058x8)
mbed_official 340:28d1f895c6fe 177 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
mbed_official 340:28d1f895c6fe 178 RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official 340:28d1f895c6fe 179 #else
mbed_official 340:28d1f895c6fe 180 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
mbed_official 340:28d1f895c6fe 181 RCC->CFGR &= (uint32_t)0x08FFB80C;
mbed_official 340:28d1f895c6fe 182 #endif /* STM32F051x8 or STM32F058x8 */
mbed_official 340:28d1f895c6fe 183
mbed_official 340:28d1f895c6fe 184 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 340:28d1f895c6fe 185 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 340:28d1f895c6fe 186
mbed_official 340:28d1f895c6fe 187 /* Reset HSEBYP bit */
mbed_official 340:28d1f895c6fe 188 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 340:28d1f895c6fe 189
mbed_official 340:28d1f895c6fe 190 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official 340:28d1f895c6fe 191 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official 340:28d1f895c6fe 192
mbed_official 340:28d1f895c6fe 193 /* Reset PREDIV[3:0] bits */
mbed_official 340:28d1f895c6fe 194 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 340:28d1f895c6fe 195
mbed_official 630:825f75ca301e 196 #if defined (STM32F072xB) || defined (STM32F078xx)
mbed_official 441:d2c15dda23c1 197 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 340:28d1f895c6fe 198 RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
mbed_official 441:d2c15dda23c1 199 #elif defined (STM32F071xB)
mbed_official 441:d2c15dda23c1 200 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
mbed_official 441:d2c15dda23c1 201 RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
mbed_official 340:28d1f895c6fe 202 #elif defined (STM32F091xC) || defined (STM32F098xx)
mbed_official 441:d2c15dda23c1 203 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
mbed_official 441:d2c15dda23c1 204 RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
mbed_official 441:d2c15dda23c1 205 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
mbed_official 441:d2c15dda23c1 206 /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
mbed_official 441:d2c15dda23c1 207 RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
mbed_official 441:d2c15dda23c1 208 #elif defined (STM32F051x8) || defined (STM32F058xx)
mbed_official 441:d2c15dda23c1 209 /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
mbed_official 441:d2c15dda23c1 210 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
mbed_official 441:d2c15dda23c1 211 #elif defined (STM32F042x6) || defined (STM32F048xx)
mbed_official 441:d2c15dda23c1 212 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 441:d2c15dda23c1 213 RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
mbed_official 441:d2c15dda23c1 214 #elif defined (STM32F070x6) || defined (STM32F070xB)
mbed_official 441:d2c15dda23c1 215 /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
mbed_official 441:d2c15dda23c1 216 RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
mbed_official 441:d2c15dda23c1 217 /* Set default USB clock to PLLCLK, since there is no HSI48 */
mbed_official 441:d2c15dda23c1 218 RCC->CFGR3 |= (uint32_t)0x00000080;
mbed_official 340:28d1f895c6fe 219 #else
mbed_official 441:d2c15dda23c1 220 #warning "No target selected"
mbed_official 340:28d1f895c6fe 221 #endif
mbed_official 340:28d1f895c6fe 222
mbed_official 340:28d1f895c6fe 223 /* Reset HSI14 bit */
mbed_official 340:28d1f895c6fe 224 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official 340:28d1f895c6fe 225
mbed_official 340:28d1f895c6fe 226 /* Disable all interrupts */
mbed_official 340:28d1f895c6fe 227 RCC->CIR = 0x00000000;
mbed_official 340:28d1f895c6fe 228 }
mbed_official 340:28d1f895c6fe 229
mbed_official 340:28d1f895c6fe 230 /**
mbed_official 340:28d1f895c6fe 231 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 340:28d1f895c6fe 232 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 340:28d1f895c6fe 233 * be used by the user application to setup the SysTick timer or configure
mbed_official 340:28d1f895c6fe 234 * other parameters.
mbed_official 340:28d1f895c6fe 235 *
mbed_official 340:28d1f895c6fe 236 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 340:28d1f895c6fe 237 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 340:28d1f895c6fe 238 * based on this variable will be incorrect.
mbed_official 340:28d1f895c6fe 239 *
mbed_official 340:28d1f895c6fe 240 * @note - The system frequency computed by this function is not the real
mbed_official 340:28d1f895c6fe 241 * frequency in the chip. It is calculated based on the predefined
mbed_official 340:28d1f895c6fe 242 * constant and the selected clock source:
mbed_official 340:28d1f895c6fe 243 *
mbed_official 340:28d1f895c6fe 244 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 340:28d1f895c6fe 245 *
mbed_official 340:28d1f895c6fe 246 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 340:28d1f895c6fe 247 *
mbed_official 340:28d1f895c6fe 248 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 340:28d1f895c6fe 249 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 340:28d1f895c6fe 250 *
mbed_official 340:28d1f895c6fe 251 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 340:28d1f895c6fe 252 * 8 MHz) but the real value may vary depending on the variations
mbed_official 340:28d1f895c6fe 253 * in voltage and temperature.
mbed_official 340:28d1f895c6fe 254 *
mbed_official 340:28d1f895c6fe 255 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 340:28d1f895c6fe 256 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 340:28d1f895c6fe 257 * frequency of the crystal used. Otherwise, this function may
mbed_official 340:28d1f895c6fe 258 * have wrong result.
mbed_official 340:28d1f895c6fe 259 *
mbed_official 340:28d1f895c6fe 260 * - The result of this function could be not correct when using fractional
mbed_official 340:28d1f895c6fe 261 * value for HSE crystal.
mbed_official 340:28d1f895c6fe 262 *
mbed_official 340:28d1f895c6fe 263 * @param None
mbed_official 340:28d1f895c6fe 264 * @retval None
mbed_official 340:28d1f895c6fe 265 */
mbed_official 340:28d1f895c6fe 266 void SystemCoreClockUpdate (void)
mbed_official 340:28d1f895c6fe 267 {
mbed_official 340:28d1f895c6fe 268 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 340:28d1f895c6fe 269
mbed_official 340:28d1f895c6fe 270 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 271 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 340:28d1f895c6fe 272
mbed_official 340:28d1f895c6fe 273 switch (tmp)
mbed_official 340:28d1f895c6fe 274 {
mbed_official 340:28d1f895c6fe 275 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 340:28d1f895c6fe 276 SystemCoreClock = HSI_VALUE;
mbed_official 340:28d1f895c6fe 277 break;
mbed_official 340:28d1f895c6fe 278 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 340:28d1f895c6fe 279 SystemCoreClock = HSE_VALUE;
mbed_official 340:28d1f895c6fe 280 break;
mbed_official 340:28d1f895c6fe 281 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 340:28d1f895c6fe 282 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 340:28d1f895c6fe 283 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 340:28d1f895c6fe 284 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 340:28d1f895c6fe 285 pllmull = ( pllmull >> 18) + 2;
mbed_official 340:28d1f895c6fe 286 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 340:28d1f895c6fe 287
mbed_official 340:28d1f895c6fe 288 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
mbed_official 340:28d1f895c6fe 289 {
mbed_official 340:28d1f895c6fe 290 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
mbed_official 340:28d1f895c6fe 291 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
mbed_official 340:28d1f895c6fe 292 }
mbed_official 340:28d1f895c6fe 293 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
mbed_official 340:28d1f895c6fe 294 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
mbed_official 340:28d1f895c6fe 295 {
mbed_official 340:28d1f895c6fe 296 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
mbed_official 340:28d1f895c6fe 297 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
mbed_official 340:28d1f895c6fe 298 }
mbed_official 340:28d1f895c6fe 299 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
mbed_official 340:28d1f895c6fe 300 else
mbed_official 340:28d1f895c6fe 301 {
mbed_official 630:825f75ca301e 302 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
mbed_official 630:825f75ca301e 303 || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
mbed_official 630:825f75ca301e 304 || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
mbed_official 340:28d1f895c6fe 305 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
mbed_official 340:28d1f895c6fe 306 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
mbed_official 340:28d1f895c6fe 307 #else
mbed_official 340:28d1f895c6fe 308 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
mbed_official 340:28d1f895c6fe 309 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 441:d2c15dda23c1 310 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
mbed_official 441:d2c15dda23c1 311 STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
mbed_official 441:d2c15dda23c1 312 STM32F091xC || STM32F098xx || STM32F030xC */
mbed_official 340:28d1f895c6fe 313 }
mbed_official 340:28d1f895c6fe 314 break;
mbed_official 340:28d1f895c6fe 315 default: /* HSI used as system clock */
mbed_official 340:28d1f895c6fe 316 SystemCoreClock = HSI_VALUE;
mbed_official 340:28d1f895c6fe 317 break;
mbed_official 340:28d1f895c6fe 318 }
mbed_official 340:28d1f895c6fe 319 /* Compute HCLK clock frequency ----------------*/
mbed_official 340:28d1f895c6fe 320 /* Get HCLK prescaler */
mbed_official 340:28d1f895c6fe 321 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 340:28d1f895c6fe 322 /* HCLK clock frequency */
mbed_official 340:28d1f895c6fe 323 SystemCoreClock >>= tmp;
mbed_official 340:28d1f895c6fe 324 }
mbed_official 340:28d1f895c6fe 325
mbed_official 340:28d1f895c6fe 326 /**
mbed_official 340:28d1f895c6fe 327 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 340:28d1f895c6fe 328 * AHB/APBx prescalers and Flash settings
mbed_official 340:28d1f895c6fe 329 * @note This function should be called only once the RCC clock configuration
mbed_official 340:28d1f895c6fe 330 * is reset to the default reset state (done in SystemInit() function).
mbed_official 340:28d1f895c6fe 331 * @param None
mbed_official 340:28d1f895c6fe 332 * @retval None
mbed_official 340:28d1f895c6fe 333 */
mbed_official 340:28d1f895c6fe 334 void SetSysClock(void)
mbed_official 340:28d1f895c6fe 335 {
mbed_official 340:28d1f895c6fe 336 /* 1- Try to start with HSE and external clock */
mbed_official 340:28d1f895c6fe 337 #if USE_PLL_HSE_EXTC != 0
mbed_official 340:28d1f895c6fe 338 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 340:28d1f895c6fe 339 #endif
mbed_official 340:28d1f895c6fe 340 {
mbed_official 340:28d1f895c6fe 341 /* 2- If fail try to start with HSE and external xtal */
mbed_official 340:28d1f895c6fe 342 #if USE_PLL_HSE_XTAL != 0
mbed_official 340:28d1f895c6fe 343 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 340:28d1f895c6fe 344 #endif
mbed_official 340:28d1f895c6fe 345 {
mbed_official 340:28d1f895c6fe 346 /* 3- If fail start with HSI clock */
mbed_official 340:28d1f895c6fe 347 if (SetSysClock_PLL_HSI() == 0)
mbed_official 340:28d1f895c6fe 348 {
mbed_official 340:28d1f895c6fe 349 while(1)
mbed_official 340:28d1f895c6fe 350 {
mbed_official 340:28d1f895c6fe 351 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 340:28d1f895c6fe 352 }
mbed_official 340:28d1f895c6fe 353 }
mbed_official 340:28d1f895c6fe 354 }
mbed_official 340:28d1f895c6fe 355 }
mbed_official 340:28d1f895c6fe 356
mbed_official 340:28d1f895c6fe 357 // Output clock on MCO pin(PA8) for debugging purpose
mbed_official 630:825f75ca301e 358 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
mbed_official 340:28d1f895c6fe 359 }
mbed_official 340:28d1f895c6fe 360
mbed_official 340:28d1f895c6fe 361 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 340:28d1f895c6fe 362 /******************************************************************************/
mbed_official 340:28d1f895c6fe 363 /* PLL (clocked by HSE) used as System clock source */
mbed_official 340:28d1f895c6fe 364 /******************************************************************************/
mbed_official 340:28d1f895c6fe 365 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 340:28d1f895c6fe 366 {
mbed_official 630:825f75ca301e 367 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
mbed_official 630:825f75ca301e 368 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
mbed_official 630:825f75ca301e 369 //Select HSI as system clock source to allow modification of the PLL configuration
mbed_official 630:825f75ca301e 370 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
mbed_official 630:825f75ca301e 371 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
mbed_official 630:825f75ca301e 372 if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 630:825f75ca301e 373 {
mbed_official 630:825f75ca301e 374 return 0; // FAIL
mbed_official 630:825f75ca301e 375 }
mbed_official 340:28d1f895c6fe 376
mbed_official 630:825f75ca301e 377
mbed_official 340:28d1f895c6fe 378 // Select HSE oscillator as PLL source
mbed_official 630:825f75ca301e 379 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 340:28d1f895c6fe 380 if (bypass == 0) {
mbed_official 340:28d1f895c6fe 381 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
mbed_official 340:28d1f895c6fe 382 } else {
mbed_official 340:28d1f895c6fe 383 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
mbed_official 340:28d1f895c6fe 384 }
mbed_official 340:28d1f895c6fe 385 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 340:28d1f895c6fe 386 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 340:28d1f895c6fe 387 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
mbed_official 340:28d1f895c6fe 388 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official 340:28d1f895c6fe 389 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 340:28d1f895c6fe 390 return 0; // FAIL
mbed_official 340:28d1f895c6fe 391 }
mbed_official 340:28d1f895c6fe 392
mbed_official 340:28d1f895c6fe 393 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 340:28d1f895c6fe 394 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 340:28d1f895c6fe 395 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 340:28d1f895c6fe 396 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 340:28d1f895c6fe 397 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 340:28d1f895c6fe 398 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 340:28d1f895c6fe 399 return 0; // FAIL
mbed_official 340:28d1f895c6fe 400 }
mbed_official 340:28d1f895c6fe 401
mbed_official 340:28d1f895c6fe 402 // Output clock on MCO pin(PA8) for debugging purpose
mbed_official 340:28d1f895c6fe 403 //if (bypass == 0)
mbed_official 340:28d1f895c6fe 404 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
mbed_official 340:28d1f895c6fe 405 //else
mbed_official 340:28d1f895c6fe 406 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
mbed_official 340:28d1f895c6fe 407
mbed_official 340:28d1f895c6fe 408 return 1; // OK
mbed_official 340:28d1f895c6fe 409 }
mbed_official 340:28d1f895c6fe 410 #endif
mbed_official 340:28d1f895c6fe 411
mbed_official 340:28d1f895c6fe 412 /******************************************************************************/
mbed_official 340:28d1f895c6fe 413 /* PLL (clocked by HSI) used as System clock source */
mbed_official 340:28d1f895c6fe 414 /******************************************************************************/
mbed_official 340:28d1f895c6fe 415 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 340:28d1f895c6fe 416 {
mbed_official 340:28d1f895c6fe 417 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 340:28d1f895c6fe 418 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 340:28d1f895c6fe 419
mbed_official 630:825f75ca301e 420 // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
mbed_official 630:825f75ca301e 421 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
mbed_official 630:825f75ca301e 422 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 340:28d1f895c6fe 423 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 630:825f75ca301e 424 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
mbed_official 630:825f75ca301e 425 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
mbed_official 630:825f75ca301e 426 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official 340:28d1f895c6fe 427 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 340:28d1f895c6fe 428 return 0; // FAIL
mbed_official 340:28d1f895c6fe 429 }
mbed_official 340:28d1f895c6fe 430
mbed_official 340:28d1f895c6fe 431 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 340:28d1f895c6fe 432 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 340:28d1f895c6fe 433 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 340:28d1f895c6fe 434 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 340:28d1f895c6fe 435 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 340:28d1f895c6fe 436 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 340:28d1f895c6fe 437 return 0; // FAIL
mbed_official 340:28d1f895c6fe 438 }
mbed_official 340:28d1f895c6fe 439
mbed_official 340:28d1f895c6fe 440 // Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official 630:825f75ca301e 441 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz
mbed_official 340:28d1f895c6fe 442
mbed_official 340:28d1f895c6fe 443 return 1; // OK
mbed_official 340:28d1f895c6fe 444 }
mbed_official 340:28d1f895c6fe 445
mbed_official 340:28d1f895c6fe 446 /**
mbed_official 340:28d1f895c6fe 447 * @}
mbed_official 340:28d1f895c6fe 448 */
mbed_official 340:28d1f895c6fe 449
mbed_official 340:28d1f895c6fe 450 /**
mbed_official 340:28d1f895c6fe 451 * @}
mbed_official 340:28d1f895c6fe 452 */
mbed_official 340:28d1f895c6fe 453
mbed_official 340:28d1f895c6fe 454 /**
mbed_official 340:28d1f895c6fe 455 * @}
mbed_official 340:28d1f895c6fe 456 */
mbed_official 340:28d1f895c6fe 457
mbed_official 340:28d1f895c6fe 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 340:28d1f895c6fe 459