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Modified version of the mbed library for use with the Nucleo boards.

Dependents: EEPROMWrite Full-Project

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h@630:825f75ca301e, 2015-09-28 (annotated)

Committer:: mbed_official
Date:: Mon Sep 28 10:45:10 2015 +0100
Revision:: 630:825f75ca301e
Parent:: 441:d2c15dda23c1

Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10

Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/

NUCLEO_F031K6 : Add new target

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	441:d2c15dda23c1	1	/**
mbed_official	441:d2c15dda23c1	2	******************************************************************************
mbed_official	441:d2c15dda23c1	3	* @file stm32f070xb.h
mbed_official	441:d2c15dda23c1	4	* @author MCD Application Team
mbed_official	630:825f75ca301e	5	* @version V2.2.2
mbed_official	630:825f75ca301e	6	* @date 26-June-2015
mbed_official	441:d2c15dda23c1	7	* @brief CMSIS STM32F070xB devices Peripheral Access Layer Header File.
mbed_official	441:d2c15dda23c1	8	*
mbed_official	441:d2c15dda23c1	9	* This file contains:
mbed_official	441:d2c15dda23c1	10	* - Data structures and the address mapping for all peripherals
mbed_official	441:d2c15dda23c1	11	* - Peripheral's registers declarations and bits definition
mbed_official	441:d2c15dda23c1	12	* - Macros to access peripherals registers hardware
mbed_official	441:d2c15dda23c1	13	*
mbed_official	441:d2c15dda23c1	14	******************************************************************************
mbed_official	441:d2c15dda23c1	15	* @attention
mbed_official	441:d2c15dda23c1	16	*
mbed_official	630:825f75ca301e	17	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	441:d2c15dda23c1	18	*
mbed_official	441:d2c15dda23c1	19	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	441:d2c15dda23c1	20	* are permitted provided that the following conditions are met:
mbed_official	441:d2c15dda23c1	21	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	441:d2c15dda23c1	22	* this list of conditions and the following disclaimer.
mbed_official	441:d2c15dda23c1	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	441:d2c15dda23c1	24	* this list of conditions and the following disclaimer in the documentation
mbed_official	441:d2c15dda23c1	25	* and/or other materials provided with the distribution.
mbed_official	441:d2c15dda23c1	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	441:d2c15dda23c1	27	* may be used to endorse or promote products derived from this software
mbed_official	441:d2c15dda23c1	28	* without specific prior written permission.
mbed_official	441:d2c15dda23c1	29	*
mbed_official	441:d2c15dda23c1	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	441:d2c15dda23c1	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	441:d2c15dda23c1	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	441:d2c15dda23c1	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	441:d2c15dda23c1	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	441:d2c15dda23c1	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	441:d2c15dda23c1	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	441:d2c15dda23c1	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	441:d2c15dda23c1	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	441:d2c15dda23c1	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	441:d2c15dda23c1	40	*
mbed_official	441:d2c15dda23c1	41	******************************************************************************
mbed_official	441:d2c15dda23c1	42	*/
mbed_official	441:d2c15dda23c1	43
mbed_official	441:d2c15dda23c1	44	/** @addtogroup CMSIS_Device
mbed_official	441:d2c15dda23c1	45	* @{
mbed_official	441:d2c15dda23c1	46	*/
mbed_official	441:d2c15dda23c1	47
mbed_official	441:d2c15dda23c1	48	/** @addtogroup stm32f070xb
mbed_official	441:d2c15dda23c1	49	* @{
mbed_official	441:d2c15dda23c1	50	*/
mbed_official	441:d2c15dda23c1	51
mbed_official	441:d2c15dda23c1	52	#ifndef __STM32F070xB_H
mbed_official	441:d2c15dda23c1	53	#define __STM32F070xB_H
mbed_official	441:d2c15dda23c1	54
mbed_official	441:d2c15dda23c1	55	#ifdef __cplusplus
mbed_official	441:d2c15dda23c1	56	extern "C" {
mbed_official	441:d2c15dda23c1	57	#endif /* __cplusplus */
mbed_official	441:d2c15dda23c1	58
mbed_official	441:d2c15dda23c1	59	/** @addtogroup Configuration_section_for_CMSIS
mbed_official	441:d2c15dda23c1	60	* @{
mbed_official	441:d2c15dda23c1	61	*/
mbed_official	441:d2c15dda23c1	62	/**
mbed_official	441:d2c15dda23c1	63	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official	441:d2c15dda23c1	64	*/
mbed_official	441:d2c15dda23c1	65	#define __CM0_REV 0 /!< Core Revision r0p0 /
mbed_official	441:d2c15dda23c1	66	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
mbed_official	441:d2c15dda23c1	67	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
mbed_official	441:d2c15dda23c1	68	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
mbed_official	441:d2c15dda23c1	69
mbed_official	441:d2c15dda23c1	70	/**
mbed_official	441:d2c15dda23c1	71	* @}
mbed_official	441:d2c15dda23c1	72	*/
mbed_official	441:d2c15dda23c1	73
mbed_official	441:d2c15dda23c1	74	/** @addtogroup Peripheral_interrupt_number_definition
mbed_official	441:d2c15dda23c1	75	* @{
mbed_official	441:d2c15dda23c1	76	*/
mbed_official	441:d2c15dda23c1	77
mbed_official	441:d2c15dda23c1	78	/**
mbed_official	441:d2c15dda23c1	79	* @brief STM32F070xB device Interrupt Number Definition
mbed_official	441:d2c15dda23c1	80	*/
mbed_official	441:d2c15dda23c1	81	typedef enum
mbed_official	441:d2c15dda23c1	82	{
mbed_official	441:d2c15dda23c1	83	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
mbed_official	441:d2c15dda23c1	84	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
mbed_official	441:d2c15dda23c1	85	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
mbed_official	441:d2c15dda23c1	86	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
mbed_official	441:d2c15dda23c1	87	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
mbed_official	441:d2c15dda23c1	88	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
mbed_official	441:d2c15dda23c1	89
mbed_official	441:d2c15dda23c1	90	/**** STM32F070xB specific Interrupt Numbers ************************************************/
mbed_official	441:d2c15dda23c1	91	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
mbed_official	441:d2c15dda23c1	92	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
mbed_official	441:d2c15dda23c1	93	FLASH_IRQn = 3, /!< FLASH global Interrupt /
mbed_official	441:d2c15dda23c1	94	RCC_IRQn = 4, /!< RCC Global Interrupts /
mbed_official	441:d2c15dda23c1	95	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
mbed_official	441:d2c15dda23c1	96	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
mbed_official	441:d2c15dda23c1	97	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
mbed_official	441:d2c15dda23c1	98	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
mbed_official	441:d2c15dda23c1	99	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
mbed_official	441:d2c15dda23c1	100	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
mbed_official	441:d2c15dda23c1	101	ADC1_IRQn = 12, /!< ADC1 interrupts (ADC interrupt combined with EXTI Lines 21 and 22 /
mbed_official	441:d2c15dda23c1	102	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
mbed_official	441:d2c15dda23c1	103	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
mbed_official	441:d2c15dda23c1	104	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
mbed_official	441:d2c15dda23c1	105	TIM6_IRQn = 17, /!< TIM6 global Interrupts /
mbed_official	441:d2c15dda23c1	106	TIM7_IRQn = 18, /!< TIM7 global Interrupt /
mbed_official	441:d2c15dda23c1	107	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
mbed_official	441:d2c15dda23c1	108	TIM15_IRQn = 20, /!< TIM15 global Interrupt /
mbed_official	441:d2c15dda23c1	109	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
mbed_official	441:d2c15dda23c1	110	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
mbed_official	441:d2c15dda23c1	111	I2C1_IRQn = 23, /!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) /
mbed_official	441:d2c15dda23c1	112	I2C2_IRQn = 24, /!< I2C2 Event Interrupt /
mbed_official	441:d2c15dda23c1	113	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
mbed_official	441:d2c15dda23c1	114	SPI2_IRQn = 26, /!< SPI2 global Interrupt /
mbed_official	441:d2c15dda23c1	115	USART1_IRQn = 27, /!< USART1 global Interrupt /
mbed_official	441:d2c15dda23c1	116	USART2_IRQn = 28, /!< USART2 global Interrupt /
mbed_official	441:d2c15dda23c1	117	USART3_4_IRQn = 29, /!< USART3 and USART4 global Interrupts /
mbed_official	441:d2c15dda23c1	118	USB_IRQn = 31 /!< USB global Interrupts & EXTI Line18 Interrupt /
mbed_official	441:d2c15dda23c1	119	} IRQn_Type;
mbed_official	441:d2c15dda23c1	120
mbed_official	441:d2c15dda23c1	121	/**
mbed_official	441:d2c15dda23c1	122	* @}
mbed_official	441:d2c15dda23c1	123	*/
mbed_official	441:d2c15dda23c1	124
mbed_official	441:d2c15dda23c1	125	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official	441:d2c15dda23c1	126	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
mbed_official	441:d2c15dda23c1	127	#include <stdint.h>
mbed_official	441:d2c15dda23c1	128
mbed_official	441:d2c15dda23c1	129	/** @addtogroup Peripheral_registers_structures
mbed_official	441:d2c15dda23c1	130	* @{
mbed_official	441:d2c15dda23c1	131	*/
mbed_official	441:d2c15dda23c1	132
mbed_official	441:d2c15dda23c1	133	/**
mbed_official	441:d2c15dda23c1	134	* @brief Analog to Digital Converter
mbed_official	441:d2c15dda23c1	135	*/
mbed_official	441:d2c15dda23c1	136
mbed_official	441:d2c15dda23c1	137	typedef struct
mbed_official	441:d2c15dda23c1	138	{
mbed_official	441:d2c15dda23c1	139	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
mbed_official	441:d2c15dda23c1	140	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
mbed_official	441:d2c15dda23c1	141	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
mbed_official	441:d2c15dda23c1	142	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
mbed_official	441:d2c15dda23c1	143	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
mbed_official	441:d2c15dda23c1	144	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
mbed_official	441:d2c15dda23c1	145	uint32_t RESERVED1; /!< Reserved, 0x18 /
mbed_official	441:d2c15dda23c1	146	uint32_t RESERVED2; /!< Reserved, 0x1C /
mbed_official	441:d2c15dda23c1	147	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
mbed_official	441:d2c15dda23c1	148	uint32_t RESERVED3; /!< Reserved, 0x24 /
mbed_official	441:d2c15dda23c1	149	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
mbed_official	441:d2c15dda23c1	150	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
mbed_official	441:d2c15dda23c1	151	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
mbed_official	441:d2c15dda23c1	152	}ADC_TypeDef;
mbed_official	441:d2c15dda23c1	153
mbed_official	441:d2c15dda23c1	154	typedef struct
mbed_official	441:d2c15dda23c1	155	{
mbed_official	441:d2c15dda23c1	156	__IO uint32_t CCR;
mbed_official	441:d2c15dda23c1	157	}ADC_Common_TypeDef;
mbed_official	441:d2c15dda23c1	158
mbed_official	441:d2c15dda23c1	159	/**
mbed_official	441:d2c15dda23c1	160	* @brief CRC calculation unit
mbed_official	441:d2c15dda23c1	161	*/
mbed_official	441:d2c15dda23c1	162
mbed_official	441:d2c15dda23c1	163	typedef struct
mbed_official	441:d2c15dda23c1	164	{
mbed_official	441:d2c15dda23c1	165	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	166	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	167	uint8_t RESERVED0; /!< Reserved, 0x05 /
mbed_official	441:d2c15dda23c1	168	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	441:d2c15dda23c1	169	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	170	uint32_t RESERVED2; /!< Reserved, 0x0C /
mbed_official	441:d2c15dda23c1	171	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	172	__IO uint32_t RESERVED3; /!< Reserved, 0x14 /
mbed_official	441:d2c15dda23c1	173	}CRC_TypeDef;
mbed_official	441:d2c15dda23c1	174
mbed_official	441:d2c15dda23c1	175	/**
mbed_official	441:d2c15dda23c1	176	* @brief Debug MCU
mbed_official	441:d2c15dda23c1	177	*/
mbed_official	441:d2c15dda23c1	178
mbed_official	441:d2c15dda23c1	179	typedef struct
mbed_official	441:d2c15dda23c1	180	{
mbed_official	441:d2c15dda23c1	181	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	182	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	183	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	184	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	185	}DBGMCU_TypeDef;
mbed_official	441:d2c15dda23c1	186
mbed_official	441:d2c15dda23c1	187	/**
mbed_official	441:d2c15dda23c1	188	* @brief DMA Controller
mbed_official	441:d2c15dda23c1	189	*/
mbed_official	441:d2c15dda23c1	190
mbed_official	441:d2c15dda23c1	191	typedef struct
mbed_official	441:d2c15dda23c1	192	{
mbed_official	441:d2c15dda23c1	193	__IO uint32_t CCR; /!< DMA channel x configuration register /
mbed_official	441:d2c15dda23c1	194	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
mbed_official	441:d2c15dda23c1	195	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
mbed_official	441:d2c15dda23c1	196	__IO uint32_t CMAR; /!< DMA channel x memory address register /
mbed_official	441:d2c15dda23c1	197	}DMA_Channel_TypeDef;
mbed_official	441:d2c15dda23c1	198
mbed_official	441:d2c15dda23c1	199	typedef struct
mbed_official	441:d2c15dda23c1	200	{
mbed_official	441:d2c15dda23c1	201	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	202	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	203	}DMA_TypeDef;
mbed_official	441:d2c15dda23c1	204
mbed_official	441:d2c15dda23c1	205	/**
mbed_official	441:d2c15dda23c1	206	* @brief External Interrupt/Event Controller
mbed_official	441:d2c15dda23c1	207	*/
mbed_official	441:d2c15dda23c1	208
mbed_official	441:d2c15dda23c1	209	typedef struct
mbed_official	441:d2c15dda23c1	210	{
mbed_official	441:d2c15dda23c1	211	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	212	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	213	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	214	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	215	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	216	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	217	}EXTI_TypeDef;
mbed_official	441:d2c15dda23c1	218
mbed_official	441:d2c15dda23c1	219	/**
mbed_official	441:d2c15dda23c1	220	* @brief FLASH Registers
mbed_official	441:d2c15dda23c1	221	*/
mbed_official	441:d2c15dda23c1	222	typedef struct
mbed_official	441:d2c15dda23c1	223	{
mbed_official	441:d2c15dda23c1	224	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	225	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	226	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	227	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	228	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	229	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	230	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
mbed_official	441:d2c15dda23c1	231	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
mbed_official	441:d2c15dda23c1	232	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
mbed_official	441:d2c15dda23c1	233	}FLASH_TypeDef;
mbed_official	441:d2c15dda23c1	234
mbed_official	441:d2c15dda23c1	235
mbed_official	441:d2c15dda23c1	236	/**
mbed_official	441:d2c15dda23c1	237	* @brief Option Bytes Registers
mbed_official	441:d2c15dda23c1	238	*/
mbed_official	441:d2c15dda23c1	239	typedef struct
mbed_official	441:d2c15dda23c1	240	{
mbed_official	441:d2c15dda23c1	241	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	242	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
mbed_official	441:d2c15dda23c1	243	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	244	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
mbed_official	441:d2c15dda23c1	245	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	246	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
mbed_official	441:d2c15dda23c1	247	__IO uint16_t WRP2; /!< FLASH option byte write protection 2, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	248	__IO uint16_t WRP3; /!< FLASH option byte write protection 3, Address offset: 0x0E /
mbed_official	441:d2c15dda23c1	249	}OB_TypeDef;
mbed_official	441:d2c15dda23c1	250
mbed_official	441:d2c15dda23c1	251	/**
mbed_official	441:d2c15dda23c1	252	* @brief General Purpose I/O
mbed_official	441:d2c15dda23c1	253	*/
mbed_official	441:d2c15dda23c1	254
mbed_official	441:d2c15dda23c1	255	typedef struct
mbed_official	441:d2c15dda23c1	256	{
mbed_official	441:d2c15dda23c1	257	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	258	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	259	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	260	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	261	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	262	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	263	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
mbed_official	441:d2c15dda23c1	264	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
mbed_official	441:d2c15dda23c1	265	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
mbed_official	441:d2c15dda23c1	266	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
mbed_official	441:d2c15dda23c1	267	}GPIO_TypeDef;
mbed_official	441:d2c15dda23c1	268
mbed_official	441:d2c15dda23c1	269	/**
mbed_official	441:d2c15dda23c1	270	* @brief SysTem Configuration
mbed_official	441:d2c15dda23c1	271	*/
mbed_official	441:d2c15dda23c1	272
mbed_official	441:d2c15dda23c1	273	typedef struct
mbed_official	441:d2c15dda23c1	274	{
mbed_official	441:d2c15dda23c1	275	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	276	uint32_t RESERVED; /!< Reserved, 0x04 /
mbed_official	441:d2c15dda23c1	277	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
mbed_official	441:d2c15dda23c1	278	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
mbed_official	441:d2c15dda23c1	279	}SYSCFG_TypeDef;
mbed_official	441:d2c15dda23c1	280
mbed_official	441:d2c15dda23c1	281	/**
mbed_official	441:d2c15dda23c1	282	* @brief Inter-integrated Circuit Interface
mbed_official	441:d2c15dda23c1	283	*/
mbed_official	441:d2c15dda23c1	284
mbed_official	441:d2c15dda23c1	285	typedef struct
mbed_official	441:d2c15dda23c1	286	{
mbed_official	441:d2c15dda23c1	287	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	288	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	289	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	290	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	291	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	292	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	293	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
mbed_official	441:d2c15dda23c1	294	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
mbed_official	441:d2c15dda23c1	295	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
mbed_official	441:d2c15dda23c1	296	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
mbed_official	441:d2c15dda23c1	297	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
mbed_official	441:d2c15dda23c1	298	}I2C_TypeDef;
mbed_official	441:d2c15dda23c1	299
mbed_official	441:d2c15dda23c1	300	/**
mbed_official	441:d2c15dda23c1	301	* @brief Independent WATCHDOG
mbed_official	441:d2c15dda23c1	302	*/
mbed_official	441:d2c15dda23c1	303
mbed_official	441:d2c15dda23c1	304	typedef struct
mbed_official	441:d2c15dda23c1	305	{
mbed_official	441:d2c15dda23c1	306	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	307	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	308	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	309	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	310	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	311	}IWDG_TypeDef;
mbed_official	441:d2c15dda23c1	312
mbed_official	441:d2c15dda23c1	313	/**
mbed_official	441:d2c15dda23c1	314	* @brief Power Control
mbed_official	441:d2c15dda23c1	315	*/
mbed_official	441:d2c15dda23c1	316
mbed_official	441:d2c15dda23c1	317	typedef struct
mbed_official	441:d2c15dda23c1	318	{
mbed_official	441:d2c15dda23c1	319	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	320	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	321	}PWR_TypeDef;
mbed_official	441:d2c15dda23c1	322
mbed_official	441:d2c15dda23c1	323	/**
mbed_official	441:d2c15dda23c1	324	* @brief Reset and Clock Control
mbed_official	441:d2c15dda23c1	325	*/
mbed_official	630:825f75ca301e	326
mbed_official	441:d2c15dda23c1	327	typedef struct
mbed_official	441:d2c15dda23c1	328	{
mbed_official	441:d2c15dda23c1	329	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	330	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	331	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	332	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	333	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	334	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	335	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
mbed_official	441:d2c15dda23c1	336	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
mbed_official	441:d2c15dda23c1	337	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
mbed_official	441:d2c15dda23c1	338	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
mbed_official	441:d2c15dda23c1	339	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
mbed_official	441:d2c15dda23c1	340	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
mbed_official	441:d2c15dda23c1	341	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
mbed_official	441:d2c15dda23c1	342	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
mbed_official	441:d2c15dda23c1	343	}RCC_TypeDef;
mbed_official	441:d2c15dda23c1	344
mbed_official	441:d2c15dda23c1	345	/**
mbed_official	441:d2c15dda23c1	346	* @brief Real-Time Clock
mbed_official	441:d2c15dda23c1	347	*/
mbed_official	441:d2c15dda23c1	348	typedef struct
mbed_official	441:d2c15dda23c1	349	{
mbed_official	441:d2c15dda23c1	350	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	351	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	352	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	353	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	354	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
mbed_official	630:825f75ca301e	355	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
mbed_official	630:825f75ca301e	356	uint32_t RESERVED1; /!< Reserved, Address offset: 0x18 /
mbed_official	441:d2c15dda23c1	357	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
mbed_official	630:825f75ca301e	358	uint32_t RESERVED2; /!< Reserved, Address offset: 0x20 /
mbed_official	441:d2c15dda23c1	359	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
mbed_official	441:d2c15dda23c1	360	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
mbed_official	441:d2c15dda23c1	361	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
mbed_official	441:d2c15dda23c1	362	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
mbed_official	441:d2c15dda23c1	363	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
mbed_official	441:d2c15dda23c1	364	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
mbed_official	441:d2c15dda23c1	365	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
mbed_official	441:d2c15dda23c1	366	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
mbed_official	441:d2c15dda23c1	367	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
mbed_official	441:d2c15dda23c1	368	}RTC_TypeDef;
mbed_official	441:d2c15dda23c1	369
mbed_official	441:d2c15dda23c1	370	/**
mbed_official	441:d2c15dda23c1	371	* @brief Serial Peripheral Interface
mbed_official	441:d2c15dda23c1	372	*/
mbed_official	441:d2c15dda23c1	373
mbed_official	441:d2c15dda23c1	374	typedef struct
mbed_official	441:d2c15dda23c1	375	{
mbed_official	441:d2c15dda23c1	376	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	377	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	378	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	379	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	380	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	381	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	382	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
mbed_official	441:d2c15dda23c1	383	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
mbed_official	441:d2c15dda23c1	384	__IO uint32_t RESERVED1;/!< Reserved, Address offset: 0x20 /
mbed_official	441:d2c15dda23c1	385	}SPI_TypeDef;
mbed_official	441:d2c15dda23c1	386
mbed_official	441:d2c15dda23c1	387	/**
mbed_official	441:d2c15dda23c1	388	* @brief TIM
mbed_official	441:d2c15dda23c1	389	*/
mbed_official	441:d2c15dda23c1	390	typedef struct
mbed_official	441:d2c15dda23c1	391	{
mbed_official	441:d2c15dda23c1	392	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	393	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	394	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	395	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	396	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	397	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	398	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
mbed_official	441:d2c15dda23c1	399	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
mbed_official	441:d2c15dda23c1	400	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
mbed_official	441:d2c15dda23c1	401	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
mbed_official	441:d2c15dda23c1	402	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
mbed_official	441:d2c15dda23c1	403	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
mbed_official	441:d2c15dda23c1	404	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
mbed_official	441:d2c15dda23c1	405	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
mbed_official	441:d2c15dda23c1	406	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
mbed_official	441:d2c15dda23c1	407	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
mbed_official	441:d2c15dda23c1	408	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
mbed_official	441:d2c15dda23c1	409	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
mbed_official	441:d2c15dda23c1	410	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
mbed_official	441:d2c15dda23c1	411	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
mbed_official	441:d2c15dda23c1	412	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
mbed_official	441:d2c15dda23c1	413	}TIM_TypeDef;
mbed_official	441:d2c15dda23c1	414
mbed_official	441:d2c15dda23c1	415
mbed_official	441:d2c15dda23c1	416	/**
mbed_official	441:d2c15dda23c1	417	* @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official	441:d2c15dda23c1	418	*/
mbed_official	441:d2c15dda23c1	419
mbed_official	441:d2c15dda23c1	420	typedef struct
mbed_official	441:d2c15dda23c1	421	{
mbed_official	441:d2c15dda23c1	422	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	423	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	424	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	425	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	426	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	427	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	428	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
mbed_official	441:d2c15dda23c1	429	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
mbed_official	441:d2c15dda23c1	430	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
mbed_official	441:d2c15dda23c1	431	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
mbed_official	441:d2c15dda23c1	432	uint16_t RESERVED1; /!< Reserved, 0x26 /
mbed_official	441:d2c15dda23c1	433	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
mbed_official	441:d2c15dda23c1	434	uint16_t RESERVED2; /!< Reserved, 0x2A /
mbed_official	441:d2c15dda23c1	435	}USART_TypeDef;
mbed_official	441:d2c15dda23c1	436
mbed_official	441:d2c15dda23c1	437	/**
mbed_official	441:d2c15dda23c1	438	* @brief Universal Serial Bus Full Speed Device
mbed_official	441:d2c15dda23c1	439	*/
mbed_official	441:d2c15dda23c1	440
mbed_official	441:d2c15dda23c1	441	typedef struct
mbed_official	441:d2c15dda23c1	442	{
mbed_official	441:d2c15dda23c1	443	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	444	__IO uint16_t RESERVED0; /!< Reserved /
mbed_official	441:d2c15dda23c1	445	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	446	__IO uint16_t RESERVED1; /!< Reserved /
mbed_official	441:d2c15dda23c1	447	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	448	__IO uint16_t RESERVED2; /!< Reserved /
mbed_official	441:d2c15dda23c1	449	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
mbed_official	441:d2c15dda23c1	450	__IO uint16_t RESERVED3; /!< Reserved /
mbed_official	441:d2c15dda23c1	451	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
mbed_official	441:d2c15dda23c1	452	__IO uint16_t RESERVED4; /!< Reserved /
mbed_official	441:d2c15dda23c1	453	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
mbed_official	441:d2c15dda23c1	454	__IO uint16_t RESERVED5; /!< Reserved /
mbed_official	441:d2c15dda23c1	455	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
mbed_official	441:d2c15dda23c1	456	__IO uint16_t RESERVED6; /!< Reserved /
mbed_official	441:d2c15dda23c1	457	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
mbed_official	441:d2c15dda23c1	458	__IO uint16_t RESERVED7[17]; /!< Reserved /
mbed_official	441:d2c15dda23c1	459	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
mbed_official	441:d2c15dda23c1	460	__IO uint16_t RESERVED8; /!< Reserved /
mbed_official	441:d2c15dda23c1	461	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
mbed_official	441:d2c15dda23c1	462	__IO uint16_t RESERVED9; /!< Reserved /
mbed_official	441:d2c15dda23c1	463	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
mbed_official	441:d2c15dda23c1	464	__IO uint16_t RESERVEDA; /!< Reserved /
mbed_official	441:d2c15dda23c1	465	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
mbed_official	441:d2c15dda23c1	466	__IO uint16_t RESERVEDB; /!< Reserved /
mbed_official	441:d2c15dda23c1	467	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
mbed_official	441:d2c15dda23c1	468	__IO uint16_t RESERVEDC; /!< Reserved /
mbed_official	441:d2c15dda23c1	469	__IO uint16_t LPMCSR; /!< LPM Control and Status register, Address offset: 0x54 /
mbed_official	441:d2c15dda23c1	470	__IO uint16_t RESERVEDD; /!< Reserved /
mbed_official	441:d2c15dda23c1	471	__IO uint16_t BCDR; /!< Battery Charging detector register, Address offset: 0x58 /
mbed_official	441:d2c15dda23c1	472	__IO uint16_t RESERVEDE; /!< Reserved /
mbed_official	441:d2c15dda23c1	473	}USB_TypeDef;
mbed_official	441:d2c15dda23c1	474
mbed_official	441:d2c15dda23c1	475	/**
mbed_official	441:d2c15dda23c1	476	* @brief Window WATCHDOG
mbed_official	441:d2c15dda23c1	477	*/
mbed_official	441:d2c15dda23c1	478	typedef struct
mbed_official	441:d2c15dda23c1	479	{
mbed_official	441:d2c15dda23c1	480	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
mbed_official	441:d2c15dda23c1	481	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
mbed_official	441:d2c15dda23c1	482	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
mbed_official	441:d2c15dda23c1	483	}WWDG_TypeDef;
mbed_official	441:d2c15dda23c1	484
mbed_official	441:d2c15dda23c1	485	/**
mbed_official	441:d2c15dda23c1	486	* @}
mbed_official	441:d2c15dda23c1	487	*/
mbed_official	441:d2c15dda23c1	488
mbed_official	441:d2c15dda23c1	489	/** @addtogroup Peripheral_memory_map
mbed_official	441:d2c15dda23c1	490	* @{
mbed_official	441:d2c15dda23c1	491	*/
mbed_official	441:d2c15dda23c1	492
mbed_official	441:d2c15dda23c1	493	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
mbed_official	630:825f75ca301e	494	#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /!< FLASH END address of bank1 /
mbed_official	441:d2c15dda23c1	495	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
mbed_official	441:d2c15dda23c1	496	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
mbed_official	441:d2c15dda23c1	497
mbed_official	441:d2c15dda23c1	498	/!< Peripheral memory map /
mbed_official	441:d2c15dda23c1	499	#define APBPERIPH_BASE PERIPH_BASE
mbed_official	441:d2c15dda23c1	500	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official	441:d2c15dda23c1	501	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official	441:d2c15dda23c1	502
mbed_official	441:d2c15dda23c1	503	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
mbed_official	441:d2c15dda23c1	504	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
mbed_official	441:d2c15dda23c1	505	#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
mbed_official	441:d2c15dda23c1	506	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
mbed_official	441:d2c15dda23c1	507	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official	441:d2c15dda23c1	508	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official	441:d2c15dda23c1	509	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official	441:d2c15dda23c1	510	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
mbed_official	441:d2c15dda23c1	511	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
mbed_official	441:d2c15dda23c1	512	#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
mbed_official	441:d2c15dda23c1	513	#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
mbed_official	441:d2c15dda23c1	514	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official	441:d2c15dda23c1	515	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
mbed_official	441:d2c15dda23c1	516	#define USB_BASE (APBPERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
mbed_official	441:d2c15dda23c1	517	#define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
mbed_official	441:d2c15dda23c1	518	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official	441:d2c15dda23c1	519	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official	441:d2c15dda23c1	520	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official	441:d2c15dda23c1	521	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official	441:d2c15dda23c1	522	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official	441:d2c15dda23c1	523	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
mbed_official	441:d2c15dda23c1	524	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official	441:d2c15dda23c1	525	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
mbed_official	441:d2c15dda23c1	526	#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
mbed_official	441:d2c15dda23c1	527	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
mbed_official	441:d2c15dda23c1	528	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
mbed_official	441:d2c15dda23c1	529	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official	441:d2c15dda23c1	530
mbed_official	441:d2c15dda23c1	531	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official	441:d2c15dda23c1	532	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official	441:d2c15dda23c1	533	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official	441:d2c15dda23c1	534	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official	441:d2c15dda23c1	535	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official	441:d2c15dda23c1	536	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official	441:d2c15dda23c1	537
mbed_official	441:d2c15dda23c1	538	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official	441:d2c15dda23c1	539	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
mbed_official	441:d2c15dda23c1	540	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
mbed_official	441:d2c15dda23c1	541	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official	441:d2c15dda23c1	542
mbed_official	441:d2c15dda23c1	543	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official	441:d2c15dda23c1	544	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official	441:d2c15dda23c1	545	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official	441:d2c15dda23c1	546	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official	441:d2c15dda23c1	547	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official	441:d2c15dda23c1	548
mbed_official	441:d2c15dda23c1	549	/**
mbed_official	441:d2c15dda23c1	550	* @}
mbed_official	441:d2c15dda23c1	551	*/
mbed_official	441:d2c15dda23c1	552
mbed_official	441:d2c15dda23c1	553	/** @addtogroup Peripheral_declaration
mbed_official	441:d2c15dda23c1	554	* @{
mbed_official	441:d2c15dda23c1	555	*/
mbed_official	441:d2c15dda23c1	556
mbed_official	441:d2c15dda23c1	557	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official	441:d2c15dda23c1	558	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official	441:d2c15dda23c1	559	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official	441:d2c15dda23c1	560	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official	441:d2c15dda23c1	561	#define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official	441:d2c15dda23c1	562	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official	441:d2c15dda23c1	563	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official	441:d2c15dda23c1	564	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official	441:d2c15dda23c1	565	#define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official	441:d2c15dda23c1	566	#define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official	441:d2c15dda23c1	567	#define USART4 ((USART_TypeDef *) USART4_BASE)
mbed_official	441:d2c15dda23c1	568	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official	441:d2c15dda23c1	569	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official	441:d2c15dda23c1	570	#define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official	441:d2c15dda23c1	571	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official	441:d2c15dda23c1	572	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official	441:d2c15dda23c1	573	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official	441:d2c15dda23c1	574	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official	441:d2c15dda23c1	575	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official	441:d2c15dda23c1	576	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official	441:d2c15dda23c1	577	#define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official	441:d2c15dda23c1	578	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official	441:d2c15dda23c1	579	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official	441:d2c15dda23c1	580	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official	441:d2c15dda23c1	581	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official	441:d2c15dda23c1	582	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official	441:d2c15dda23c1	583	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official	441:d2c15dda23c1	584	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official	441:d2c15dda23c1	585	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official	441:d2c15dda23c1	586	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official	441:d2c15dda23c1	587	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official	441:d2c15dda23c1	588	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official	441:d2c15dda23c1	589	#define OB ((OB_TypeDef *) OB_BASE)
mbed_official	441:d2c15dda23c1	590	#define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official	441:d2c15dda23c1	591	#define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official	441:d2c15dda23c1	592	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official	441:d2c15dda23c1	593	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official	441:d2c15dda23c1	594	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official	441:d2c15dda23c1	595	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official	441:d2c15dda23c1	596	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official	441:d2c15dda23c1	597	#define USB ((USB_TypeDef *) USB_BASE)
mbed_official	441:d2c15dda23c1	598	/**
mbed_official	441:d2c15dda23c1	599	* @}
mbed_official	441:d2c15dda23c1	600	*/
mbed_official	441:d2c15dda23c1	601
mbed_official	441:d2c15dda23c1	602	/** @addtogroup Exported_constants
mbed_official	441:d2c15dda23c1	603	* @{
mbed_official	441:d2c15dda23c1	604	*/
mbed_official	441:d2c15dda23c1	605
mbed_official	441:d2c15dda23c1	606	/** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official	441:d2c15dda23c1	607	* @{
mbed_official	441:d2c15dda23c1	608	*/
mbed_official	441:d2c15dda23c1	609
mbed_official	441:d2c15dda23c1	610	/******************************************************************************/
mbed_official	441:d2c15dda23c1	611	/* Peripheral Registers Bits Definition */
mbed_official	441:d2c15dda23c1	612	/******************************************************************************/
mbed_official	441:d2c15dda23c1	613	/******************************************************************************/
mbed_official	441:d2c15dda23c1	614	/* */
mbed_official	441:d2c15dda23c1	615	/* Analog to Digital Converter (ADC) */
mbed_official	441:d2c15dda23c1	616	/* */
mbed_official	441:d2c15dda23c1	617	/******************************************************************************/
mbed_official	441:d2c15dda23c1	618	/****************** Bits definition for ADC_ISR register ****************/
mbed_official	441:d2c15dda23c1	619	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
mbed_official	441:d2c15dda23c1	620	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
mbed_official	441:d2c15dda23c1	621	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
mbed_official	441:d2c15dda23c1	622	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
mbed_official	441:d2c15dda23c1	623	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
mbed_official	441:d2c15dda23c1	624	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
mbed_official	441:d2c15dda23c1	625
mbed_official	441:d2c15dda23c1	626	/* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	627	#define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official	441:d2c15dda23c1	628
mbed_official	441:d2c15dda23c1	629	/****************** Bits definition for ADC_IER register ****************/
mbed_official	441:d2c15dda23c1	630	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
mbed_official	441:d2c15dda23c1	631	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
mbed_official	441:d2c15dda23c1	632	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
mbed_official	441:d2c15dda23c1	633	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
mbed_official	441:d2c15dda23c1	634	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
mbed_official	441:d2c15dda23c1	635	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
mbed_official	441:d2c15dda23c1	636
mbed_official	441:d2c15dda23c1	637	/* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	638	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official	441:d2c15dda23c1	639
mbed_official	441:d2c15dda23c1	640	/****************** Bits definition for ADC_CR register *****************/
mbed_official	441:d2c15dda23c1	641	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
mbed_official	441:d2c15dda23c1	642	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
mbed_official	441:d2c15dda23c1	643	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
mbed_official	441:d2c15dda23c1	644	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
mbed_official	441:d2c15dda23c1	645	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
mbed_official	441:d2c15dda23c1	646
mbed_official	441:d2c15dda23c1	647	/***************** Bits definition for ADC_CFGR1 register ***************/
mbed_official	441:d2c15dda23c1	648	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
mbed_official	441:d2c15dda23c1	649	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	650	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	651	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	652	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	653	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	441:d2c15dda23c1	654	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
mbed_official	441:d2c15dda23c1	655	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
mbed_official	441:d2c15dda23c1	656	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
mbed_official	441:d2c15dda23c1	657	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
mbed_official	441:d2c15dda23c1	658	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
mbed_official	441:d2c15dda23c1	659	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
mbed_official	441:d2c15dda23c1	660	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
mbed_official	441:d2c15dda23c1	661	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
mbed_official	441:d2c15dda23c1	662	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	663	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	664	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
mbed_official	441:d2c15dda23c1	665	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	666	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	667	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	668	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
mbed_official	441:d2c15dda23c1	669	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
mbed_official	441:d2c15dda23c1	670	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	671	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	672	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
mbed_official	441:d2c15dda23c1	673	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
mbed_official	441:d2c15dda23c1	674	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
mbed_official	441:d2c15dda23c1	675
mbed_official	441:d2c15dda23c1	676	/* Old WAIT bit definition, maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	677	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official	441:d2c15dda23c1	678
mbed_official	441:d2c15dda23c1	679	/***************** Bits definition for ADC_CFGR2 register ***************/
mbed_official	441:d2c15dda23c1	680	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
mbed_official	441:d2c15dda23c1	681	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
mbed_official	441:d2c15dda23c1	682	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
mbed_official	441:d2c15dda23c1	683
mbed_official	441:d2c15dda23c1	684	/* Old bit definition, maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	685	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
mbed_official	441:d2c15dda23c1	686	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
mbed_official	441:d2c15dda23c1	687
mbed_official	441:d2c15dda23c1	688	/**************** Bit definition for ADC_SMPR register ******************/
mbed_official	441:d2c15dda23c1	689	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
mbed_official	441:d2c15dda23c1	690	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	691	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	692	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	693
mbed_official	441:d2c15dda23c1	694	/* Old bit definition, maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	695	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
mbed_official	441:d2c15dda23c1	696	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
mbed_official	441:d2c15dda23c1	697	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
mbed_official	441:d2c15dda23c1	698	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
mbed_official	441:d2c15dda23c1	699
mbed_official	441:d2c15dda23c1	700	/***************** Bit definition for ADC_TR register ******************/
mbed_official	441:d2c15dda23c1	701	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
mbed_official	441:d2c15dda23c1	702	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
mbed_official	441:d2c15dda23c1	703
mbed_official	441:d2c15dda23c1	704	/* Old bit definition, maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	705	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
mbed_official	441:d2c15dda23c1	706	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
mbed_official	441:d2c15dda23c1	707
mbed_official	441:d2c15dda23c1	708	/**************** Bit definition for ADC_CHSELR register ****************/
mbed_official	441:d2c15dda23c1	709	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
mbed_official	441:d2c15dda23c1	710	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
mbed_official	441:d2c15dda23c1	711	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
mbed_official	441:d2c15dda23c1	712	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
mbed_official	441:d2c15dda23c1	713	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
mbed_official	441:d2c15dda23c1	714	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
mbed_official	441:d2c15dda23c1	715	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
mbed_official	441:d2c15dda23c1	716	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
mbed_official	441:d2c15dda23c1	717	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
mbed_official	441:d2c15dda23c1	718	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
mbed_official	441:d2c15dda23c1	719	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
mbed_official	441:d2c15dda23c1	720	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
mbed_official	441:d2c15dda23c1	721	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
mbed_official	441:d2c15dda23c1	722	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
mbed_official	441:d2c15dda23c1	723	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
mbed_official	441:d2c15dda23c1	724	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
mbed_official	441:d2c15dda23c1	725	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
mbed_official	441:d2c15dda23c1	726	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
mbed_official	441:d2c15dda23c1	727	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
mbed_official	441:d2c15dda23c1	728
mbed_official	441:d2c15dda23c1	729	/****************** Bit definition for ADC_DR register ******************/
mbed_official	441:d2c15dda23c1	730	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
mbed_official	441:d2c15dda23c1	731
mbed_official	441:d2c15dda23c1	732	/***************** Bit definition for ADC_CCR register ******************/
mbed_official	441:d2c15dda23c1	733	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
mbed_official	441:d2c15dda23c1	734	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
mbed_official	441:d2c15dda23c1	735
mbed_official	441:d2c15dda23c1	736	/******************************************************************************/
mbed_official	441:d2c15dda23c1	737	/* */
mbed_official	441:d2c15dda23c1	738	/* CRC calculation unit (CRC) */
mbed_official	441:d2c15dda23c1	739	/* */
mbed_official	441:d2c15dda23c1	740	/******************************************************************************/
mbed_official	441:d2c15dda23c1	741	/***************** Bit definition for CRC_DR register *******************/
mbed_official	441:d2c15dda23c1	742	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
mbed_official	441:d2c15dda23c1	743
mbed_official	441:d2c15dda23c1	744	/***************** Bit definition for CRC_IDR register ******************/
mbed_official	441:d2c15dda23c1	745	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
mbed_official	441:d2c15dda23c1	746
mbed_official	441:d2c15dda23c1	747	/****************** Bit definition for CRC_CR register ******************/
mbed_official	441:d2c15dda23c1	748	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
mbed_official	441:d2c15dda23c1	749	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
mbed_official	441:d2c15dda23c1	750	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
mbed_official	441:d2c15dda23c1	751	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
mbed_official	441:d2c15dda23c1	752	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
mbed_official	441:d2c15dda23c1	753
mbed_official	441:d2c15dda23c1	754	/***************** Bit definition for CRC_INIT register *****************/
mbed_official	441:d2c15dda23c1	755	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
mbed_official	441:d2c15dda23c1	756
mbed_official	441:d2c15dda23c1	757	/******************************************************************************/
mbed_official	441:d2c15dda23c1	758	/* */
mbed_official	441:d2c15dda23c1	759	/* Debug MCU (DBGMCU) */
mbed_official	441:d2c15dda23c1	760	/* */
mbed_official	441:d2c15dda23c1	761	/******************************************************************************/
mbed_official	441:d2c15dda23c1	762
mbed_official	441:d2c15dda23c1	763	/************** Bit definition for DBGMCU_IDCODE register ***************/
mbed_official	441:d2c15dda23c1	764	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
mbed_official	441:d2c15dda23c1	765
mbed_official	441:d2c15dda23c1	766	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
mbed_official	441:d2c15dda23c1	767	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	768	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	769	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	770	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	771	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	441:d2c15dda23c1	772	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
mbed_official	441:d2c15dda23c1	773	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
mbed_official	441:d2c15dda23c1	774	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
mbed_official	441:d2c15dda23c1	775	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
mbed_official	441:d2c15dda23c1	776	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
mbed_official	441:d2c15dda23c1	777	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
mbed_official	441:d2c15dda23c1	778	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
mbed_official	441:d2c15dda23c1	779	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
mbed_official	441:d2c15dda23c1	780	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
mbed_official	441:d2c15dda23c1	781	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
mbed_official	441:d2c15dda23c1	782	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
mbed_official	441:d2c15dda23c1	783
mbed_official	441:d2c15dda23c1	784	/**************** Bit definition for DBGMCU_CR register *****************/
mbed_official	441:d2c15dda23c1	785	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
mbed_official	441:d2c15dda23c1	786	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
mbed_official	441:d2c15dda23c1	787
mbed_official	441:d2c15dda23c1	788	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official	441:d2c15dda23c1	789	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
mbed_official	441:d2c15dda23c1	790	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted /
mbed_official	441:d2c15dda23c1	791	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /!< TIM7 counter stopped when core is halted /
mbed_official	441:d2c15dda23c1	792	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
mbed_official	441:d2c15dda23c1	793	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
mbed_official	441:d2c15dda23c1	794	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
mbed_official	441:d2c15dda23c1	795	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
mbed_official	441:d2c15dda23c1	796	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
mbed_official	441:d2c15dda23c1	797
mbed_official	441:d2c15dda23c1	798	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official	441:d2c15dda23c1	799	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
mbed_official	441:d2c15dda23c1	800	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /!< TIM15 counter stopped when core is halted /
mbed_official	441:d2c15dda23c1	801	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
mbed_official	441:d2c15dda23c1	802	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
mbed_official	441:d2c15dda23c1	803
mbed_official	441:d2c15dda23c1	804	/******************************************************************************/
mbed_official	441:d2c15dda23c1	805	/* */
mbed_official	441:d2c15dda23c1	806	/* DMA Controller (DMA) */
mbed_official	441:d2c15dda23c1	807	/* */
mbed_official	441:d2c15dda23c1	808	/******************************************************************************/
mbed_official	441:d2c15dda23c1	809	/***************** Bit definition for DMA_ISR register ******************/
mbed_official	441:d2c15dda23c1	810	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
mbed_official	441:d2c15dda23c1	811	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
mbed_official	441:d2c15dda23c1	812	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
mbed_official	441:d2c15dda23c1	813	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
mbed_official	441:d2c15dda23c1	814	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
mbed_official	441:d2c15dda23c1	815	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
mbed_official	441:d2c15dda23c1	816	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
mbed_official	441:d2c15dda23c1	817	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
mbed_official	441:d2c15dda23c1	818	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
mbed_official	441:d2c15dda23c1	819	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
mbed_official	441:d2c15dda23c1	820	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
mbed_official	441:d2c15dda23c1	821	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
mbed_official	441:d2c15dda23c1	822	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
mbed_official	441:d2c15dda23c1	823	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
mbed_official	441:d2c15dda23c1	824	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
mbed_official	441:d2c15dda23c1	825	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
mbed_official	441:d2c15dda23c1	826	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
mbed_official	441:d2c15dda23c1	827	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
mbed_official	441:d2c15dda23c1	828	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
mbed_official	441:d2c15dda23c1	829	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
mbed_official	441:d2c15dda23c1	830
mbed_official	441:d2c15dda23c1	831	/***************** Bit definition for DMA_IFCR register *****************/
mbed_official	441:d2c15dda23c1	832	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
mbed_official	441:d2c15dda23c1	833	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
mbed_official	441:d2c15dda23c1	834	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
mbed_official	441:d2c15dda23c1	835	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
mbed_official	441:d2c15dda23c1	836	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
mbed_official	441:d2c15dda23c1	837	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
mbed_official	441:d2c15dda23c1	838	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
mbed_official	441:d2c15dda23c1	839	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
mbed_official	441:d2c15dda23c1	840	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
mbed_official	441:d2c15dda23c1	841	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
mbed_official	441:d2c15dda23c1	842	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
mbed_official	441:d2c15dda23c1	843	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
mbed_official	441:d2c15dda23c1	844	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
mbed_official	441:d2c15dda23c1	845	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
mbed_official	441:d2c15dda23c1	846	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
mbed_official	441:d2c15dda23c1	847	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
mbed_official	441:d2c15dda23c1	848	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
mbed_official	441:d2c15dda23c1	849	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
mbed_official	441:d2c15dda23c1	850	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
mbed_official	441:d2c15dda23c1	851	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
mbed_official	441:d2c15dda23c1	852
mbed_official	441:d2c15dda23c1	853	/***************** Bit definition for DMA_CCR register ******************/
mbed_official	441:d2c15dda23c1	854	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
mbed_official	441:d2c15dda23c1	855	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
mbed_official	441:d2c15dda23c1	856	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
mbed_official	441:d2c15dda23c1	857	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
mbed_official	441:d2c15dda23c1	858	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
mbed_official	441:d2c15dda23c1	859	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
mbed_official	441:d2c15dda23c1	860	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
mbed_official	441:d2c15dda23c1	861	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
mbed_official	441:d2c15dda23c1	862
mbed_official	441:d2c15dda23c1	863	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	441:d2c15dda23c1	864	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	865	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	866
mbed_official	441:d2c15dda23c1	867	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	441:d2c15dda23c1	868	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	869	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	870
mbed_official	441:d2c15dda23c1	871	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
mbed_official	441:d2c15dda23c1	872	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	873	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	874
mbed_official	441:d2c15dda23c1	875	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
mbed_official	441:d2c15dda23c1	876
mbed_official	441:d2c15dda23c1	877	/**************** Bit definition for DMA_CNDTR register *****************/
mbed_official	441:d2c15dda23c1	878	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
mbed_official	441:d2c15dda23c1	879
mbed_official	441:d2c15dda23c1	880	/**************** Bit definition for DMA_CPAR register ******************/
mbed_official	441:d2c15dda23c1	881	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	441:d2c15dda23c1	882
mbed_official	441:d2c15dda23c1	883	/**************** Bit definition for DMA_CMAR register ******************/
mbed_official	441:d2c15dda23c1	884	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	441:d2c15dda23c1	885
mbed_official	441:d2c15dda23c1	886	/******************************************************************************/
mbed_official	441:d2c15dda23c1	887	/* */
mbed_official	441:d2c15dda23c1	888	/* External Interrupt/Event Controller (EXTI) */
mbed_official	441:d2c15dda23c1	889	/* */
mbed_official	441:d2c15dda23c1	890	/******************************************************************************/
mbed_official	441:d2c15dda23c1	891	/***************** Bit definition for EXTI_IMR register *****************/
mbed_official	441:d2c15dda23c1	892	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
mbed_official	441:d2c15dda23c1	893	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
mbed_official	441:d2c15dda23c1	894	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
mbed_official	441:d2c15dda23c1	895	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
mbed_official	441:d2c15dda23c1	896	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
mbed_official	441:d2c15dda23c1	897	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
mbed_official	441:d2c15dda23c1	898	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
mbed_official	441:d2c15dda23c1	899	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
mbed_official	441:d2c15dda23c1	900	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
mbed_official	441:d2c15dda23c1	901	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
mbed_official	441:d2c15dda23c1	902	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
mbed_official	441:d2c15dda23c1	903	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
mbed_official	441:d2c15dda23c1	904	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
mbed_official	441:d2c15dda23c1	905	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
mbed_official	441:d2c15dda23c1	906	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
mbed_official	441:d2c15dda23c1	907	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
mbed_official	441:d2c15dda23c1	908	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
mbed_official	441:d2c15dda23c1	909	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
mbed_official	441:d2c15dda23c1	910	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
mbed_official	441:d2c15dda23c1	911	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
mbed_official	441:d2c15dda23c1	912	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
mbed_official	441:d2c15dda23c1	913
mbed_official	441:d2c15dda23c1	914	/**************** Bit definition for EXTI_EMR register ******************/
mbed_official	441:d2c15dda23c1	915	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
mbed_official	441:d2c15dda23c1	916	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
mbed_official	441:d2c15dda23c1	917	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
mbed_official	441:d2c15dda23c1	918	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
mbed_official	441:d2c15dda23c1	919	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
mbed_official	441:d2c15dda23c1	920	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
mbed_official	441:d2c15dda23c1	921	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
mbed_official	441:d2c15dda23c1	922	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
mbed_official	441:d2c15dda23c1	923	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
mbed_official	441:d2c15dda23c1	924	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
mbed_official	441:d2c15dda23c1	925	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
mbed_official	441:d2c15dda23c1	926	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
mbed_official	441:d2c15dda23c1	927	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
mbed_official	441:d2c15dda23c1	928	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
mbed_official	441:d2c15dda23c1	929	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
mbed_official	441:d2c15dda23c1	930	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
mbed_official	441:d2c15dda23c1	931	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
mbed_official	441:d2c15dda23c1	932	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
mbed_official	441:d2c15dda23c1	933	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
mbed_official	441:d2c15dda23c1	934	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
mbed_official	441:d2c15dda23c1	935	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
mbed_official	441:d2c15dda23c1	936
mbed_official	441:d2c15dda23c1	937	/***************** Bit definition for EXTI_RTSR register ****************/
mbed_official	441:d2c15dda23c1	938	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
mbed_official	441:d2c15dda23c1	939	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
mbed_official	441:d2c15dda23c1	940	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
mbed_official	441:d2c15dda23c1	941	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
mbed_official	441:d2c15dda23c1	942	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
mbed_official	441:d2c15dda23c1	943	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
mbed_official	441:d2c15dda23c1	944	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
mbed_official	441:d2c15dda23c1	945	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
mbed_official	441:d2c15dda23c1	946	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
mbed_official	441:d2c15dda23c1	947	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
mbed_official	441:d2c15dda23c1	948	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
mbed_official	441:d2c15dda23c1	949	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
mbed_official	441:d2c15dda23c1	950	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
mbed_official	441:d2c15dda23c1	951	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
mbed_official	441:d2c15dda23c1	952	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
mbed_official	441:d2c15dda23c1	953	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
mbed_official	441:d2c15dda23c1	954	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
mbed_official	441:d2c15dda23c1	955	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
mbed_official	441:d2c15dda23c1	956	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
mbed_official	441:d2c15dda23c1	957	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
mbed_official	441:d2c15dda23c1	958	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
mbed_official	441:d2c15dda23c1	959	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
mbed_official	441:d2c15dda23c1	960
mbed_official	441:d2c15dda23c1	961	/***************** Bit definition for EXTI_FTSR register *****************/
mbed_official	441:d2c15dda23c1	962	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
mbed_official	441:d2c15dda23c1	963	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
mbed_official	441:d2c15dda23c1	964	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
mbed_official	441:d2c15dda23c1	965	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
mbed_official	441:d2c15dda23c1	966	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
mbed_official	441:d2c15dda23c1	967	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
mbed_official	441:d2c15dda23c1	968	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
mbed_official	441:d2c15dda23c1	969	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
mbed_official	441:d2c15dda23c1	970	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
mbed_official	441:d2c15dda23c1	971	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
mbed_official	441:d2c15dda23c1	972	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
mbed_official	441:d2c15dda23c1	973	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
mbed_official	441:d2c15dda23c1	974	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
mbed_official	441:d2c15dda23c1	975	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
mbed_official	441:d2c15dda23c1	976	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
mbed_official	441:d2c15dda23c1	977	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
mbed_official	441:d2c15dda23c1	978	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
mbed_official	441:d2c15dda23c1	979	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
mbed_official	441:d2c15dda23c1	980	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
mbed_official	441:d2c15dda23c1	981	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
mbed_official	441:d2c15dda23c1	982	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
mbed_official	441:d2c15dda23c1	983	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
mbed_official	441:d2c15dda23c1	984
mbed_official	441:d2c15dda23c1	985	/***************** Bit definition for EXTI_SWIER register *****************/
mbed_official	441:d2c15dda23c1	986	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
mbed_official	441:d2c15dda23c1	987	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
mbed_official	441:d2c15dda23c1	988	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
mbed_official	441:d2c15dda23c1	989	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
mbed_official	441:d2c15dda23c1	990	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
mbed_official	441:d2c15dda23c1	991	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
mbed_official	441:d2c15dda23c1	992	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
mbed_official	441:d2c15dda23c1	993	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
mbed_official	441:d2c15dda23c1	994	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
mbed_official	441:d2c15dda23c1	995	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
mbed_official	441:d2c15dda23c1	996	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
mbed_official	441:d2c15dda23c1	997	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
mbed_official	441:d2c15dda23c1	998	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
mbed_official	441:d2c15dda23c1	999	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
mbed_official	441:d2c15dda23c1	1000	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
mbed_official	441:d2c15dda23c1	1001	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
mbed_official	441:d2c15dda23c1	1002	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
mbed_official	441:d2c15dda23c1	1003	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
mbed_official	441:d2c15dda23c1	1004	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
mbed_official	441:d2c15dda23c1	1005	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
mbed_official	441:d2c15dda23c1	1006	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
mbed_official	441:d2c15dda23c1	1007	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
mbed_official	441:d2c15dda23c1	1008
mbed_official	441:d2c15dda23c1	1009	/**************** Bit definition for EXTI_PR register *******************/
mbed_official	441:d2c15dda23c1	1010	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
mbed_official	441:d2c15dda23c1	1011	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
mbed_official	441:d2c15dda23c1	1012	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
mbed_official	441:d2c15dda23c1	1013	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
mbed_official	441:d2c15dda23c1	1014	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
mbed_official	441:d2c15dda23c1	1015	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
mbed_official	441:d2c15dda23c1	1016	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
mbed_official	441:d2c15dda23c1	1017	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
mbed_official	441:d2c15dda23c1	1018	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
mbed_official	441:d2c15dda23c1	1019	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
mbed_official	441:d2c15dda23c1	1020	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
mbed_official	441:d2c15dda23c1	1021	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
mbed_official	441:d2c15dda23c1	1022	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
mbed_official	441:d2c15dda23c1	1023	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
mbed_official	441:d2c15dda23c1	1024	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
mbed_official	441:d2c15dda23c1	1025	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
mbed_official	441:d2c15dda23c1	1026	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
mbed_official	441:d2c15dda23c1	1027	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
mbed_official	441:d2c15dda23c1	1028	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
mbed_official	441:d2c15dda23c1	1029	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit 20 /
mbed_official	441:d2c15dda23c1	1030	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit 21 /
mbed_official	441:d2c15dda23c1	1031	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit 22 /
mbed_official	441:d2c15dda23c1	1032
mbed_official	441:d2c15dda23c1	1033	/******************************************************************************/
mbed_official	441:d2c15dda23c1	1034	/* */
mbed_official	441:d2c15dda23c1	1035	/* FLASH and Option Bytes Registers */
mbed_official	441:d2c15dda23c1	1036	/* */
mbed_official	441:d2c15dda23c1	1037	/******************************************************************************/
mbed_official	441:d2c15dda23c1	1038
mbed_official	441:d2c15dda23c1	1039	/***************** Bit definition for FLASH_ACR register ****************/
mbed_official	441:d2c15dda23c1	1040	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
mbed_official	441:d2c15dda23c1	1041
mbed_official	441:d2c15dda23c1	1042	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
mbed_official	441:d2c15dda23c1	1043	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
mbed_official	441:d2c15dda23c1	1044
mbed_official	441:d2c15dda23c1	1045	/**************** Bit definition for FLASH_KEYR register ****************/
mbed_official	441:d2c15dda23c1	1046	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
mbed_official	441:d2c15dda23c1	1047
mbed_official	441:d2c15dda23c1	1048	/*************** Bit definition for FLASH_OPTKEYR register **************/
mbed_official	441:d2c15dda23c1	1049	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
mbed_official	441:d2c15dda23c1	1050
mbed_official	441:d2c15dda23c1	1051	/**************** FLASH Keys ********************************************/
mbed_official	630:825f75ca301e	1052	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
mbed_official	630:825f75ca301e	1053	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
mbed_official	441:d2c15dda23c1	1054	to unlock the write access to the FPEC. */
mbed_official	441:d2c15dda23c1	1055
mbed_official	441:d2c15dda23c1	1056	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
mbed_official	441:d2c15dda23c1	1057	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
mbed_official	441:d2c15dda23c1	1058	unlock the write access to the option byte block */
mbed_official	441:d2c15dda23c1	1059
mbed_official	441:d2c15dda23c1	1060	/**************** Bit definition for FLASH_SR register *****************/
mbed_official	441:d2c15dda23c1	1061	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
mbed_official	441:d2c15dda23c1	1062	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
mbed_official	441:d2c15dda23c1	1063	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
mbed_official	441:d2c15dda23c1	1064	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
mbed_official	441:d2c15dda23c1	1065	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
mbed_official	441:d2c15dda23c1	1066
mbed_official	441:d2c15dda23c1	1067	/***************** Bit definition for FLASH_CR register *****************/
mbed_official	441:d2c15dda23c1	1068	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
mbed_official	441:d2c15dda23c1	1069	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
mbed_official	441:d2c15dda23c1	1070	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
mbed_official	441:d2c15dda23c1	1071	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
mbed_official	441:d2c15dda23c1	1072	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
mbed_official	441:d2c15dda23c1	1073	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
mbed_official	441:d2c15dda23c1	1074	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
mbed_official	441:d2c15dda23c1	1075	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
mbed_official	441:d2c15dda23c1	1076	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
mbed_official	441:d2c15dda23c1	1077	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
mbed_official	441:d2c15dda23c1	1078	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
mbed_official	441:d2c15dda23c1	1079
mbed_official	441:d2c15dda23c1	1080	/***************** Bit definition for FLASH_AR register *****************/
mbed_official	441:d2c15dda23c1	1081	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
mbed_official	441:d2c15dda23c1	1082
mbed_official	441:d2c15dda23c1	1083	/**************** Bit definition for FLASH_OBR register *****************/
mbed_official	441:d2c15dda23c1	1084	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
mbed_official	441:d2c15dda23c1	1085	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
mbed_official	441:d2c15dda23c1	1086	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
mbed_official	441:d2c15dda23c1	1087
mbed_official	630:825f75ca301e	1088	#define FLASH_OBR_USER ((uint32_t)0x00007700) /!< User Option Bytes /
mbed_official	441:d2c15dda23c1	1089	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
mbed_official	441:d2c15dda23c1	1090	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
mbed_official	441:d2c15dda23c1	1091	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
mbed_official	441:d2c15dda23c1	1092	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
mbed_official	441:d2c15dda23c1	1093	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
mbed_official	630:825f75ca301e	1094	#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /!< RAM parity check /
mbed_official	441:d2c15dda23c1	1095
mbed_official	441:d2c15dda23c1	1096	/* Old BOOT1 bit definition, maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	1097	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
mbed_official	441:d2c15dda23c1	1098
mbed_official	441:d2c15dda23c1	1099	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	1100	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
mbed_official	441:d2c15dda23c1	1101
mbed_official	441:d2c15dda23c1	1102	/**************** Bit definition for FLASH_WRPR register ****************/
mbed_official	441:d2c15dda23c1	1103	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /!< Write Protect /
mbed_official	441:d2c15dda23c1	1104
mbed_official	441:d2c15dda23c1	1105	/----------------------------------------------------------------------------/
mbed_official	441:d2c15dda23c1	1106
mbed_official	441:d2c15dda23c1	1107	/**************** Bit definition for OB_RDP register ********************/
mbed_official	441:d2c15dda23c1	1108	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
mbed_official	441:d2c15dda23c1	1109	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
mbed_official	441:d2c15dda23c1	1110
mbed_official	441:d2c15dda23c1	1111	/**************** Bit definition for OB_USER register *******************/
mbed_official	441:d2c15dda23c1	1112	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
mbed_official	441:d2c15dda23c1	1113	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
mbed_official	441:d2c15dda23c1	1114
mbed_official	441:d2c15dda23c1	1115	/**************** Bit definition for OB_WRP0 register *******************/
mbed_official	441:d2c15dda23c1	1116	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
mbed_official	441:d2c15dda23c1	1117	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
mbed_official	441:d2c15dda23c1	1118
mbed_official	441:d2c15dda23c1	1119	/**************** Bit definition for OB_WRP1 register *******************/
mbed_official	441:d2c15dda23c1	1120	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
mbed_official	441:d2c15dda23c1	1121	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
mbed_official	441:d2c15dda23c1	1122
mbed_official	441:d2c15dda23c1	1123	/**************** Bit definition for OB_WRP2 register *******************/
mbed_official	441:d2c15dda23c1	1124	#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
mbed_official	441:d2c15dda23c1	1125	#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
mbed_official	441:d2c15dda23c1	1126
mbed_official	441:d2c15dda23c1	1127	/**************** Bit definition for OB_WRP3 register *******************/
mbed_official	441:d2c15dda23c1	1128	#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
mbed_official	441:d2c15dda23c1	1129	#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
mbed_official	441:d2c15dda23c1	1130
mbed_official	441:d2c15dda23c1	1131	/******************************************************************************/
mbed_official	441:d2c15dda23c1	1132	/* */
mbed_official	441:d2c15dda23c1	1133	/* General Purpose IOs (GPIO) */
mbed_official	441:d2c15dda23c1	1134	/* */
mbed_official	441:d2c15dda23c1	1135	/******************************************************************************/
mbed_official	441:d2c15dda23c1	1136	/***************** Bit definition for GPIO_MODER register ***************/
mbed_official	441:d2c15dda23c1	1137	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official	441:d2c15dda23c1	1138	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1139	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1140	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official	441:d2c15dda23c1	1141	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1142	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1143	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official	441:d2c15dda23c1	1144	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1145	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1146	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official	441:d2c15dda23c1	1147	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1148	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1149	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official	441:d2c15dda23c1	1150	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1151	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1152	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official	441:d2c15dda23c1	1153	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1154	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1155	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official	441:d2c15dda23c1	1156	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1157	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1158	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official	441:d2c15dda23c1	1159	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1160	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1161	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official	441:d2c15dda23c1	1162	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	1163	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	1164	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official	441:d2c15dda23c1	1165	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	1166	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	1167	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official	441:d2c15dda23c1	1168	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	1169	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	1170	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official	441:d2c15dda23c1	1171	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	1172	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official	441:d2c15dda23c1	1173	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official	441:d2c15dda23c1	1174	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official	441:d2c15dda23c1	1175	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official	441:d2c15dda23c1	1176	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official	441:d2c15dda23c1	1177	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official	441:d2c15dda23c1	1178	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official	441:d2c15dda23c1	1179	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official	441:d2c15dda23c1	1180	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official	441:d2c15dda23c1	1181	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official	441:d2c15dda23c1	1182	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official	441:d2c15dda23c1	1183	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official	441:d2c15dda23c1	1184	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official	441:d2c15dda23c1	1185
mbed_official	441:d2c15dda23c1	1186	/**************** Bit definition for GPIO_OTYPER register ***************/
mbed_official	441:d2c15dda23c1	1187	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1188	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1189	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1190	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1191	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1192	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1193	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1194	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1195	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1196	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1197	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1198	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1199	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1200	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1201	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1202	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1203
mbed_official	441:d2c15dda23c1	1204	/************** Bit definition for GPIO_OSPEEDR register ****************/
mbed_official	441:d2c15dda23c1	1205	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official	441:d2c15dda23c1	1206	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1207	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1208	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official	441:d2c15dda23c1	1209	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1210	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1211	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official	441:d2c15dda23c1	1212	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1213	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1214	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official	441:d2c15dda23c1	1215	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1216	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1217	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official	441:d2c15dda23c1	1218	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1219	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1220	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official	441:d2c15dda23c1	1221	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1222	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1223	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official	441:d2c15dda23c1	1224	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1225	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1226	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official	441:d2c15dda23c1	1227	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1228	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1229	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official	441:d2c15dda23c1	1230	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	1231	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	1232	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official	441:d2c15dda23c1	1233	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	1234	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	1235	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official	441:d2c15dda23c1	1236	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	1237	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	1238	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official	441:d2c15dda23c1	1239	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	1240	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official	441:d2c15dda23c1	1241	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official	441:d2c15dda23c1	1242	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official	441:d2c15dda23c1	1243	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official	441:d2c15dda23c1	1244	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official	441:d2c15dda23c1	1245	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official	441:d2c15dda23c1	1246	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official	441:d2c15dda23c1	1247	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official	441:d2c15dda23c1	1248	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official	441:d2c15dda23c1	1249	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official	441:d2c15dda23c1	1250	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official	441:d2c15dda23c1	1251	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official	441:d2c15dda23c1	1252	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official	441:d2c15dda23c1	1253
mbed_official	441:d2c15dda23c1	1254	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	1255	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
mbed_official	441:d2c15dda23c1	1256	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
mbed_official	441:d2c15dda23c1	1257	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
mbed_official	441:d2c15dda23c1	1258	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
mbed_official	441:d2c15dda23c1	1259	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
mbed_official	441:d2c15dda23c1	1260	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
mbed_official	441:d2c15dda23c1	1261	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
mbed_official	441:d2c15dda23c1	1262	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
mbed_official	441:d2c15dda23c1	1263	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
mbed_official	441:d2c15dda23c1	1264	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
mbed_official	441:d2c15dda23c1	1265	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
mbed_official	441:d2c15dda23c1	1266	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
mbed_official	441:d2c15dda23c1	1267	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
mbed_official	441:d2c15dda23c1	1268	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
mbed_official	441:d2c15dda23c1	1269	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
mbed_official	441:d2c15dda23c1	1270	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
mbed_official	441:d2c15dda23c1	1271	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
mbed_official	441:d2c15dda23c1	1272	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
mbed_official	441:d2c15dda23c1	1273	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
mbed_official	441:d2c15dda23c1	1274	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
mbed_official	441:d2c15dda23c1	1275	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
mbed_official	441:d2c15dda23c1	1276	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
mbed_official	441:d2c15dda23c1	1277	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
mbed_official	441:d2c15dda23c1	1278	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
mbed_official	441:d2c15dda23c1	1279	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
mbed_official	441:d2c15dda23c1	1280	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
mbed_official	441:d2c15dda23c1	1281	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
mbed_official	441:d2c15dda23c1	1282	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
mbed_official	441:d2c15dda23c1	1283	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
mbed_official	441:d2c15dda23c1	1284	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
mbed_official	441:d2c15dda23c1	1285	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
mbed_official	441:d2c15dda23c1	1286	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
mbed_official	441:d2c15dda23c1	1287	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
mbed_official	441:d2c15dda23c1	1288	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
mbed_official	441:d2c15dda23c1	1289	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
mbed_official	441:d2c15dda23c1	1290	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
mbed_official	441:d2c15dda23c1	1291	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
mbed_official	441:d2c15dda23c1	1292	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
mbed_official	441:d2c15dda23c1	1293	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
mbed_official	441:d2c15dda23c1	1294	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
mbed_official	441:d2c15dda23c1	1295	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
mbed_official	441:d2c15dda23c1	1296	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
mbed_official	441:d2c15dda23c1	1297	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
mbed_official	441:d2c15dda23c1	1298	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
mbed_official	441:d2c15dda23c1	1299	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
mbed_official	441:d2c15dda23c1	1300	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
mbed_official	441:d2c15dda23c1	1301	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
mbed_official	441:d2c15dda23c1	1302	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
mbed_official	441:d2c15dda23c1	1303
mbed_official	441:d2c15dda23c1	1304	/***************** Bit definition for GPIO_PUPDR register ****************/
mbed_official	441:d2c15dda23c1	1305	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official	441:d2c15dda23c1	1306	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1307	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1308	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official	441:d2c15dda23c1	1309	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1310	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1311	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official	441:d2c15dda23c1	1312	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1313	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1314	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official	441:d2c15dda23c1	1315	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1316	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1317	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official	441:d2c15dda23c1	1318	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1319	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1320	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official	441:d2c15dda23c1	1321	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1322	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1323	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official	441:d2c15dda23c1	1324	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1325	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1326	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official	441:d2c15dda23c1	1327	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1328	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1329	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official	441:d2c15dda23c1	1330	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	1331	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	1332	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official	441:d2c15dda23c1	1333	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	1334	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	1335	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official	441:d2c15dda23c1	1336	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	1337	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	1338	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official	441:d2c15dda23c1	1339	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	1340	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official	441:d2c15dda23c1	1341	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official	441:d2c15dda23c1	1342	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official	441:d2c15dda23c1	1343	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official	441:d2c15dda23c1	1344	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official	441:d2c15dda23c1	1345	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official	441:d2c15dda23c1	1346	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official	441:d2c15dda23c1	1347	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official	441:d2c15dda23c1	1348	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official	441:d2c15dda23c1	1349	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official	441:d2c15dda23c1	1350	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official	441:d2c15dda23c1	1351	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official	441:d2c15dda23c1	1352	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official	441:d2c15dda23c1	1353
mbed_official	441:d2c15dda23c1	1354	/***************** Bit definition for GPIO_IDR register *****************/
mbed_official	441:d2c15dda23c1	1355	#define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1356	#define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1357	#define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1358	#define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1359	#define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1360	#define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1361	#define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1362	#define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1363	#define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1364	#define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1365	#define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1366	#define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1367	#define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1368	#define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1369	#define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1370	#define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1371
mbed_official	441:d2c15dda23c1	1372	/**************** Bit definition for GPIO_ODR register ******************/
mbed_official	441:d2c15dda23c1	1373	#define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1374	#define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1375	#define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1376	#define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1377	#define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1378	#define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1379	#define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1380	#define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1381	#define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1382	#define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1383	#define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1384	#define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1385	#define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1386	#define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1387	#define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1388	#define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1389
mbed_official	441:d2c15dda23c1	1390	/**************** Bit definition for GPIO_BSRR register ******************/
mbed_official	441:d2c15dda23c1	1391	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1392	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1393	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1394	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1395	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1396	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1397	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1398	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1399	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1400	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1401	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1402	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1403	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1404	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1405	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1406	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1407	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	1408	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	1409	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	1410	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	1411	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	1412	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	1413	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	1414	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official	441:d2c15dda23c1	1415	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official	441:d2c15dda23c1	1416	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official	441:d2c15dda23c1	1417	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official	441:d2c15dda23c1	1418	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official	441:d2c15dda23c1	1419	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official	441:d2c15dda23c1	1420	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official	441:d2c15dda23c1	1421	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official	441:d2c15dda23c1	1422	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official	441:d2c15dda23c1	1423
mbed_official	441:d2c15dda23c1	1424	/**************** Bit definition for GPIO_LCKR register ******************/
mbed_official	441:d2c15dda23c1	1425	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1426	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1427	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1428	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1429	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1430	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1431	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1432	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1433	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1434	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1435	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1436	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1437	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1438	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1439	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1440	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1441	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	1442
mbed_official	441:d2c15dda23c1	1443	/**************** Bit definition for GPIO_AFRL register ******************/
mbed_official	441:d2c15dda23c1	1444	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official	441:d2c15dda23c1	1445	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official	441:d2c15dda23c1	1446	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official	441:d2c15dda23c1	1447	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official	441:d2c15dda23c1	1448	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official	441:d2c15dda23c1	1449	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official	441:d2c15dda23c1	1450	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official	441:d2c15dda23c1	1451	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official	441:d2c15dda23c1	1452
mbed_official	441:d2c15dda23c1	1453	/**************** Bit definition for GPIO_AFRH register ******************/
mbed_official	441:d2c15dda23c1	1454	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official	441:d2c15dda23c1	1455	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official	441:d2c15dda23c1	1456	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official	441:d2c15dda23c1	1457	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official	441:d2c15dda23c1	1458	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official	441:d2c15dda23c1	1459	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official	441:d2c15dda23c1	1460	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official	441:d2c15dda23c1	1461	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official	441:d2c15dda23c1	1462
mbed_official	441:d2c15dda23c1	1463	/**************** Bit definition for GPIO_BRR register *******************/
mbed_official	441:d2c15dda23c1	1464	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	1465	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	1466	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	1467	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	1468	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	1469	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	1470	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	1471	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	1472	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	1473	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	1474	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	1475	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	1476	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1477	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1478	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1479	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	1480
mbed_official	441:d2c15dda23c1	1481	/******************************************************************************/
mbed_official	441:d2c15dda23c1	1482	/* */
mbed_official	441:d2c15dda23c1	1483	/* Inter-integrated Circuit Interface (I2C) */
mbed_official	441:d2c15dda23c1	1484	/* */
mbed_official	441:d2c15dda23c1	1485	/******************************************************************************/
mbed_official	441:d2c15dda23c1	1486
mbed_official	441:d2c15dda23c1	1487	/***************** Bit definition for I2C_CR1 register *****************/
mbed_official	441:d2c15dda23c1	1488	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
mbed_official	441:d2c15dda23c1	1489	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
mbed_official	441:d2c15dda23c1	1490	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
mbed_official	441:d2c15dda23c1	1491	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
mbed_official	441:d2c15dda23c1	1492	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
mbed_official	441:d2c15dda23c1	1493	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
mbed_official	441:d2c15dda23c1	1494	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
mbed_official	441:d2c15dda23c1	1495	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
mbed_official	441:d2c15dda23c1	1496	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
mbed_official	441:d2c15dda23c1	1497	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
mbed_official	441:d2c15dda23c1	1498	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
mbed_official	441:d2c15dda23c1	1499	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
mbed_official	441:d2c15dda23c1	1500	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
mbed_official	441:d2c15dda23c1	1501	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
mbed_official	441:d2c15dda23c1	1502	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
mbed_official	441:d2c15dda23c1	1503	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
mbed_official	441:d2c15dda23c1	1504	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
mbed_official	441:d2c15dda23c1	1505	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
mbed_official	441:d2c15dda23c1	1506	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
mbed_official	441:d2c15dda23c1	1507	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
mbed_official	441:d2c15dda23c1	1508
mbed_official	441:d2c15dda23c1	1509	/**************** Bit definition for I2C_CR2 register ******************/
mbed_official	441:d2c15dda23c1	1510	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
mbed_official	441:d2c15dda23c1	1511	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
mbed_official	441:d2c15dda23c1	1512	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
mbed_official	441:d2c15dda23c1	1513	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
mbed_official	441:d2c15dda23c1	1514	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
mbed_official	441:d2c15dda23c1	1515	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
mbed_official	441:d2c15dda23c1	1516	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
mbed_official	441:d2c15dda23c1	1517	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
mbed_official	441:d2c15dda23c1	1518	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
mbed_official	441:d2c15dda23c1	1519	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
mbed_official	441:d2c15dda23c1	1520	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
mbed_official	441:d2c15dda23c1	1521
mbed_official	441:d2c15dda23c1	1522	/***************** Bit definition for I2C_OAR1 register ****************/
mbed_official	441:d2c15dda23c1	1523	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
mbed_official	441:d2c15dda23c1	1524	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
mbed_official	441:d2c15dda23c1	1525	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
mbed_official	441:d2c15dda23c1	1526
mbed_official	441:d2c15dda23c1	1527	/***************** Bit definition for I2C_OAR2 register ****************/
mbed_official	441:d2c15dda23c1	1528	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
mbed_official	441:d2c15dda23c1	1529	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
mbed_official	441:d2c15dda23c1	1530	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
mbed_official	441:d2c15dda23c1	1531
mbed_official	441:d2c15dda23c1	1532	/***************** Bit definition for I2C_TIMINGR register **************/
mbed_official	441:d2c15dda23c1	1533	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
mbed_official	441:d2c15dda23c1	1534	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
mbed_official	441:d2c15dda23c1	1535	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
mbed_official	441:d2c15dda23c1	1536	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
mbed_official	441:d2c15dda23c1	1537	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
mbed_official	441:d2c15dda23c1	1538
mbed_official	441:d2c15dda23c1	1539	/***************** Bit definition for I2C_TIMEOUTR register **************/
mbed_official	441:d2c15dda23c1	1540	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
mbed_official	441:d2c15dda23c1	1541	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
mbed_official	441:d2c15dda23c1	1542	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
mbed_official	441:d2c15dda23c1	1543	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
mbed_official	441:d2c15dda23c1	1544	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
mbed_official	441:d2c15dda23c1	1545
mbed_official	441:d2c15dda23c1	1546	/**************** Bit definition for I2C_ISR register ******************/
mbed_official	441:d2c15dda23c1	1547	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
mbed_official	441:d2c15dda23c1	1548	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
mbed_official	441:d2c15dda23c1	1549	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
mbed_official	441:d2c15dda23c1	1550	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
mbed_official	441:d2c15dda23c1	1551	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
mbed_official	441:d2c15dda23c1	1552	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
mbed_official	441:d2c15dda23c1	1553	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
mbed_official	441:d2c15dda23c1	1554	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
mbed_official	441:d2c15dda23c1	1555	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
mbed_official	441:d2c15dda23c1	1556	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
mbed_official	441:d2c15dda23c1	1557	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
mbed_official	441:d2c15dda23c1	1558	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
mbed_official	441:d2c15dda23c1	1559	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
mbed_official	441:d2c15dda23c1	1560	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
mbed_official	441:d2c15dda23c1	1561	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
mbed_official	441:d2c15dda23c1	1562	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
mbed_official	441:d2c15dda23c1	1563	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
mbed_official	441:d2c15dda23c1	1564
mbed_official	441:d2c15dda23c1	1565	/**************** Bit definition for I2C_ICR register ******************/
mbed_official	441:d2c15dda23c1	1566	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
mbed_official	441:d2c15dda23c1	1567	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
mbed_official	441:d2c15dda23c1	1568	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
mbed_official	441:d2c15dda23c1	1569	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
mbed_official	441:d2c15dda23c1	1570	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
mbed_official	441:d2c15dda23c1	1571	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
mbed_official	441:d2c15dda23c1	1572	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
mbed_official	441:d2c15dda23c1	1573	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
mbed_official	441:d2c15dda23c1	1574	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
mbed_official	441:d2c15dda23c1	1575
mbed_official	441:d2c15dda23c1	1576	/**************** Bit definition for I2C_PECR register *****************/
mbed_official	441:d2c15dda23c1	1577	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
mbed_official	441:d2c15dda23c1	1578
mbed_official	441:d2c15dda23c1	1579	/**************** Bit definition for I2C_RXDR register *******************/
mbed_official	441:d2c15dda23c1	1580	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
mbed_official	441:d2c15dda23c1	1581
mbed_official	441:d2c15dda23c1	1582	/**************** Bit definition for I2C_TXDR register *****************/
mbed_official	441:d2c15dda23c1	1583	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
mbed_official	441:d2c15dda23c1	1584
mbed_official	441:d2c15dda23c1	1585	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	1586	/* */
mbed_official	441:d2c15dda23c1	1587	/* Independent WATCHDOG (IWDG) */
mbed_official	441:d2c15dda23c1	1588	/* */
mbed_official	441:d2c15dda23c1	1589	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	1590	/***************** Bit definition for IWDG_KR register *****************/
mbed_official	441:d2c15dda23c1	1591	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!< Key value (write only, read 0000h) /
mbed_official	441:d2c15dda23c1	1592
mbed_official	441:d2c15dda23c1	1593	/***************** Bit definition for IWDG_PR register *****************/
mbed_official	441:d2c15dda23c1	1594	#define IWDG_PR_PR ((uint32_t)0x07) /!< PR[2:0] (Prescaler divider) /
mbed_official	441:d2c15dda23c1	1595	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1596	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1597	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	1598
mbed_official	441:d2c15dda23c1	1599	/***************** Bit definition for IWDG_RLR register ****************/
mbed_official	441:d2c15dda23c1	1600	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!< Watchdog counter reload value /
mbed_official	441:d2c15dda23c1	1601
mbed_official	441:d2c15dda23c1	1602	/***************** Bit definition for IWDG_SR register *****************/
mbed_official	441:d2c15dda23c1	1603	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
mbed_official	441:d2c15dda23c1	1604	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
mbed_official	441:d2c15dda23c1	1605	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
mbed_official	441:d2c15dda23c1	1606
mbed_official	441:d2c15dda23c1	1607	/***************** Bit definition for IWDG_KR register *****************/
mbed_official	441:d2c15dda23c1	1608	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
mbed_official	441:d2c15dda23c1	1609
mbed_official	441:d2c15dda23c1	1610	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	1611	/* */
mbed_official	441:d2c15dda23c1	1612	/* Power Control (PWR) */
mbed_official	441:d2c15dda23c1	1613	/* */
mbed_official	441:d2c15dda23c1	1614	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	1615
mbed_official	441:d2c15dda23c1	1616	/****************** Bit definition for PWR_CR register *****************/
mbed_official	441:d2c15dda23c1	1617	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-power Deepsleep /
mbed_official	441:d2c15dda23c1	1618	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
mbed_official	441:d2c15dda23c1	1619	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
mbed_official	441:d2c15dda23c1	1620	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
mbed_official	441:d2c15dda23c1	1621	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
mbed_official	441:d2c15dda23c1	1622
mbed_official	441:d2c15dda23c1	1623	/***************** Bit definition for PWR_CSR register *****************/
mbed_official	441:d2c15dda23c1	1624	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
mbed_official	441:d2c15dda23c1	1625	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
mbed_official	441:d2c15dda23c1	1626
mbed_official	441:d2c15dda23c1	1627	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
mbed_official	441:d2c15dda23c1	1628	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
mbed_official	441:d2c15dda23c1	1629	#define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /!< Enable WKUP pin 4 /
mbed_official	441:d2c15dda23c1	1630	#define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /!< Enable WKUP pin 5 /
mbed_official	441:d2c15dda23c1	1631	#define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /!< Enable WKUP pin 6 /
mbed_official	441:d2c15dda23c1	1632	#define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /!< Enable WKUP pin 7 /
mbed_official	441:d2c15dda23c1	1633
mbed_official	441:d2c15dda23c1	1634	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	1635	/* */
mbed_official	441:d2c15dda23c1	1636	/* Reset and Clock Control */
mbed_official	441:d2c15dda23c1	1637	/* */
mbed_official	441:d2c15dda23c1	1638	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	1639
mbed_official	441:d2c15dda23c1	1640	/****************** Bit definition for RCC_CR register *****************/
mbed_official	441:d2c15dda23c1	1641	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
mbed_official	441:d2c15dda23c1	1642	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
mbed_official	441:d2c15dda23c1	1643
mbed_official	441:d2c15dda23c1	1644	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
mbed_official	441:d2c15dda23c1	1645	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	1646	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	1647	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	1648	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	1649	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
mbed_official	441:d2c15dda23c1	1650
mbed_official	441:d2c15dda23c1	1651	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
mbed_official	441:d2c15dda23c1	1652	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	1653	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	1654	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	1655	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	1656	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
mbed_official	441:d2c15dda23c1	1657	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
mbed_official	441:d2c15dda23c1	1658	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
mbed_official	441:d2c15dda23c1	1659	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
mbed_official	441:d2c15dda23c1	1660
mbed_official	441:d2c15dda23c1	1661	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
mbed_official	441:d2c15dda23c1	1662	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
mbed_official	441:d2c15dda23c1	1663	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
mbed_official	441:d2c15dda23c1	1664	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
mbed_official	441:d2c15dda23c1	1665	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
mbed_official	441:d2c15dda23c1	1666	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
mbed_official	441:d2c15dda23c1	1667
mbed_official	441:d2c15dda23c1	1668	/****************** Bit definition for RCC_CFGR register ***************/
mbed_official	441:d2c15dda23c1	1669	/!< SW configuration /
mbed_official	441:d2c15dda23c1	1670	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
mbed_official	441:d2c15dda23c1	1671	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1672	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1673
mbed_official	441:d2c15dda23c1	1674	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
mbed_official	441:d2c15dda23c1	1675	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
mbed_official	441:d2c15dda23c1	1676	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
mbed_official	441:d2c15dda23c1	1677
mbed_official	441:d2c15dda23c1	1678	/!< SWS configuration /
mbed_official	441:d2c15dda23c1	1679	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
mbed_official	441:d2c15dda23c1	1680	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1681	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1682
mbed_official	441:d2c15dda23c1	1683	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
mbed_official	441:d2c15dda23c1	1684	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
mbed_official	441:d2c15dda23c1	1685	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
mbed_official	441:d2c15dda23c1	1686
mbed_official	441:d2c15dda23c1	1687	/!< HPRE configuration /
mbed_official	441:d2c15dda23c1	1688	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
mbed_official	441:d2c15dda23c1	1689	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1690	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1691	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	1692	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	1693
mbed_official	441:d2c15dda23c1	1694	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
mbed_official	441:d2c15dda23c1	1695	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
mbed_official	441:d2c15dda23c1	1696	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
mbed_official	441:d2c15dda23c1	1697	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
mbed_official	441:d2c15dda23c1	1698	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
mbed_official	441:d2c15dda23c1	1699	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
mbed_official	441:d2c15dda23c1	1700	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
mbed_official	441:d2c15dda23c1	1701	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
mbed_official	441:d2c15dda23c1	1702	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
mbed_official	441:d2c15dda23c1	1703
mbed_official	441:d2c15dda23c1	1704	/!< PPRE configuration /
mbed_official	441:d2c15dda23c1	1705	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
mbed_official	441:d2c15dda23c1	1706	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1707	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1708	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	1709
mbed_official	441:d2c15dda23c1	1710	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
mbed_official	441:d2c15dda23c1	1711	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
mbed_official	441:d2c15dda23c1	1712	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
mbed_official	441:d2c15dda23c1	1713	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
mbed_official	441:d2c15dda23c1	1714	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
mbed_official	441:d2c15dda23c1	1715
mbed_official	441:d2c15dda23c1	1716	/!< ADCPPRE configuration /
mbed_official	441:d2c15dda23c1	1717	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /!< ADCPRE bit (ADC prescaler) /
mbed_official	441:d2c15dda23c1	1718
mbed_official	441:d2c15dda23c1	1719	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK divided by 2 /
mbed_official	441:d2c15dda23c1	1720	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK divided by 4 /
mbed_official	441:d2c15dda23c1	1721
mbed_official	441:d2c15dda23c1	1722	#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /!< PLL entry clock source /
mbed_official	441:d2c15dda23c1	1723	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
mbed_official	441:d2c15dda23c1	1724	#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /!< HSI/PREDIV clock selected as PLL entry clock source /
mbed_official	441:d2c15dda23c1	1725	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE/PREDIV clock selected as PLL entry clock source /
mbed_official	441:d2c15dda23c1	1726
mbed_official	441:d2c15dda23c1	1727	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
mbed_official	441:d2c15dda23c1	1728	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /!< HSE/PREDIV clock not divided for PLL entry /
mbed_official	441:d2c15dda23c1	1729	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /!< HSE/PREDIV clock divided by 2 for PLL entry /
mbed_official	441:d2c15dda23c1	1730
mbed_official	441:d2c15dda23c1	1731	/!< PLLMUL configuration /
mbed_official	441:d2c15dda23c1	1732	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
mbed_official	441:d2c15dda23c1	1733	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1734	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1735	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	1736	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	1737
mbed_official	441:d2c15dda23c1	1738	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
mbed_official	441:d2c15dda23c1	1739	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
mbed_official	441:d2c15dda23c1	1740	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
mbed_official	441:d2c15dda23c1	1741	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
mbed_official	441:d2c15dda23c1	1742	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
mbed_official	441:d2c15dda23c1	1743	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
mbed_official	441:d2c15dda23c1	1744	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
mbed_official	441:d2c15dda23c1	1745	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
mbed_official	441:d2c15dda23c1	1746	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
mbed_official	441:d2c15dda23c1	1747	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
mbed_official	441:d2c15dda23c1	1748	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
mbed_official	441:d2c15dda23c1	1749	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
mbed_official	441:d2c15dda23c1	1750	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
mbed_official	441:d2c15dda23c1	1751	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
mbed_official	441:d2c15dda23c1	1752	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
mbed_official	441:d2c15dda23c1	1753
mbed_official	441:d2c15dda23c1	1754	/!< USB configuration /
mbed_official	441:d2c15dda23c1	1755	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB prescaler /
mbed_official	441:d2c15dda23c1	1756
mbed_official	441:d2c15dda23c1	1757	/!< MCO configuration /
mbed_official	441:d2c15dda23c1	1758	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
mbed_official	441:d2c15dda23c1	1759	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1760	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1761	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	1762	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	1763
mbed_official	441:d2c15dda23c1	1764	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
mbed_official	441:d2c15dda23c1	1765	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
mbed_official	441:d2c15dda23c1	1766	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
mbed_official	441:d2c15dda23c1	1767	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
mbed_official	441:d2c15dda23c1	1768	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
mbed_official	441:d2c15dda23c1	1769	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
mbed_official	441:d2c15dda23c1	1770	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
mbed_official	441:d2c15dda23c1	1771	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
mbed_official	441:d2c15dda23c1	1772
mbed_official	441:d2c15dda23c1	1773	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /!< MCO prescaler /
mbed_official	441:d2c15dda23c1	1774	#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
mbed_official	441:d2c15dda23c1	1775	#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
mbed_official	441:d2c15dda23c1	1776	#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
mbed_official	441:d2c15dda23c1	1777	#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
mbed_official	441:d2c15dda23c1	1778	#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
mbed_official	441:d2c15dda23c1	1779	#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /!< MCO is divided by 32 /
mbed_official	441:d2c15dda23c1	1780	#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /!< MCO is divided by 64 /
mbed_official	441:d2c15dda23c1	1781	#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /!< MCO is divided by 128 /
mbed_official	441:d2c15dda23c1	1782
mbed_official	441:d2c15dda23c1	1783	#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /!< PLL is not divided to MCO /
mbed_official	441:d2c15dda23c1	1784
mbed_official	441:d2c15dda23c1	1785	/!<*************** Bit definition for RCC_CIR register ***************/
mbed_official	441:d2c15dda23c1	1786	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
mbed_official	441:d2c15dda23c1	1787	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
mbed_official	441:d2c15dda23c1	1788	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
mbed_official	441:d2c15dda23c1	1789	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
mbed_official	441:d2c15dda23c1	1790	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
mbed_official	441:d2c15dda23c1	1791	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
mbed_official	441:d2c15dda23c1	1792	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
mbed_official	441:d2c15dda23c1	1793	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
mbed_official	441:d2c15dda23c1	1794	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
mbed_official	441:d2c15dda23c1	1795	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
mbed_official	441:d2c15dda23c1	1796	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
mbed_official	441:d2c15dda23c1	1797	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
mbed_official	441:d2c15dda23c1	1798	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
mbed_official	441:d2c15dda23c1	1799	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
mbed_official	441:d2c15dda23c1	1800	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
mbed_official	441:d2c15dda23c1	1801	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
mbed_official	441:d2c15dda23c1	1802	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
mbed_official	441:d2c15dda23c1	1803	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
mbed_official	441:d2c15dda23c1	1804	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
mbed_official	441:d2c15dda23c1	1805	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
mbed_official	441:d2c15dda23c1	1806
mbed_official	441:d2c15dda23c1	1807	/*************** Bit definition for RCC_APB2RSTR register **************/
mbed_official	441:d2c15dda23c1	1808	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
mbed_official	441:d2c15dda23c1	1809	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
mbed_official	441:d2c15dda23c1	1810	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
mbed_official	441:d2c15dda23c1	1811	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
mbed_official	441:d2c15dda23c1	1812	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
mbed_official	441:d2c15dda23c1	1813	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 clock reset /
mbed_official	441:d2c15dda23c1	1814	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
mbed_official	441:d2c15dda23c1	1815	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
mbed_official	441:d2c15dda23c1	1816	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
mbed_official	441:d2c15dda23c1	1817
mbed_official	441:d2c15dda23c1	1818	/!< Old ADC1 clock reset bit definition maintained for legacy purpose /
mbed_official	441:d2c15dda23c1	1819	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
mbed_official	441:d2c15dda23c1	1820
mbed_official	441:d2c15dda23c1	1821	/*************** Bit definition for RCC_APB1RSTR register **************/
mbed_official	441:d2c15dda23c1	1822	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
mbed_official	441:d2c15dda23c1	1823	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 clock reset /
mbed_official	441:d2c15dda23c1	1824	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 clock reset /
mbed_official	441:d2c15dda23c1	1825	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
mbed_official	441:d2c15dda23c1	1826	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
mbed_official	441:d2c15dda23c1	1827	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 clock reset /
mbed_official	441:d2c15dda23c1	1828	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 clock reset /
mbed_official	441:d2c15dda23c1	1829	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 clock reset /
mbed_official	441:d2c15dda23c1	1830	#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /!< USART 4 clock reset /
mbed_official	441:d2c15dda23c1	1831	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
mbed_official	441:d2c15dda23c1	1832	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 clock reset /
mbed_official	441:d2c15dda23c1	1833	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB clock reset /
mbed_official	441:d2c15dda23c1	1834	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
mbed_official	441:d2c15dda23c1	1835
mbed_official	441:d2c15dda23c1	1836	/**************** Bit definition for RCC_AHBENR register ***************/
mbed_official	441:d2c15dda23c1	1837	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA1 clock enable /
mbed_official	441:d2c15dda23c1	1838	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
mbed_official	441:d2c15dda23c1	1839	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
mbed_official	441:d2c15dda23c1	1840	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
mbed_official	441:d2c15dda23c1	1841	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
mbed_official	441:d2c15dda23c1	1842	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
mbed_official	441:d2c15dda23c1	1843	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
mbed_official	441:d2c15dda23c1	1844	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
mbed_official	441:d2c15dda23c1	1845	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
mbed_official	441:d2c15dda23c1	1846
mbed_official	441:d2c15dda23c1	1847	/* Old Bit definition maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	1848	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
mbed_official	441:d2c15dda23c1	1849
mbed_official	441:d2c15dda23c1	1850	/*************** Bit definition for RCC_APB2ENR register ***************/
mbed_official	441:d2c15dda23c1	1851	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
mbed_official	441:d2c15dda23c1	1852	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
mbed_official	441:d2c15dda23c1	1853	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
mbed_official	441:d2c15dda23c1	1854	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
mbed_official	441:d2c15dda23c1	1855	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
mbed_official	441:d2c15dda23c1	1856	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
mbed_official	441:d2c15dda23c1	1857	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
mbed_official	441:d2c15dda23c1	1858	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
mbed_official	441:d2c15dda23c1	1859	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
mbed_official	441:d2c15dda23c1	1860
mbed_official	441:d2c15dda23c1	1861	/* Old Bit definition maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	1862	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
mbed_official	441:d2c15dda23c1	1863	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
mbed_official	441:d2c15dda23c1	1864
mbed_official	441:d2c15dda23c1	1865	/*************** Bit definition for RCC_APB1ENR register ***************/
mbed_official	441:d2c15dda23c1	1866	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
mbed_official	441:d2c15dda23c1	1867	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
mbed_official	441:d2c15dda23c1	1868	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
mbed_official	441:d2c15dda23c1	1869	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
mbed_official	441:d2c15dda23c1	1870	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
mbed_official	441:d2c15dda23c1	1871	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
mbed_official	441:d2c15dda23c1	1872	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART2 clock enable /
mbed_official	441:d2c15dda23c1	1873	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART3 clock enable /
mbed_official	441:d2c15dda23c1	1874	#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /!< USART4 clock enable /
mbed_official	441:d2c15dda23c1	1875	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
mbed_official	441:d2c15dda23c1	1876	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C2 clock enable /
mbed_official	441:d2c15dda23c1	1877	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
mbed_official	441:d2c15dda23c1	1878	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
mbed_official	441:d2c15dda23c1	1879
mbed_official	441:d2c15dda23c1	1880	/***************** Bit definition for RCC_BDCR register ****************/
mbed_official	441:d2c15dda23c1	1881	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
mbed_official	441:d2c15dda23c1	1882	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
mbed_official	441:d2c15dda23c1	1883	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
mbed_official	441:d2c15dda23c1	1884
mbed_official	441:d2c15dda23c1	1885	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
mbed_official	441:d2c15dda23c1	1886	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1887	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1888
mbed_official	441:d2c15dda23c1	1889	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
mbed_official	441:d2c15dda23c1	1890	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1891	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1892
mbed_official	441:d2c15dda23c1	1893	/!< RTC configuration /
mbed_official	441:d2c15dda23c1	1894	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
mbed_official	441:d2c15dda23c1	1895	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
mbed_official	441:d2c15dda23c1	1896	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
mbed_official	441:d2c15dda23c1	1897	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
mbed_official	441:d2c15dda23c1	1898
mbed_official	441:d2c15dda23c1	1899	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
mbed_official	441:d2c15dda23c1	1900	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
mbed_official	441:d2c15dda23c1	1901
mbed_official	441:d2c15dda23c1	1902	/***************** Bit definition for RCC_CSR register *****************/
mbed_official	441:d2c15dda23c1	1903	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
mbed_official	441:d2c15dda23c1	1904	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
mbed_official	441:d2c15dda23c1	1905	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
mbed_official	441:d2c15dda23c1	1906	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
mbed_official	441:d2c15dda23c1	1907	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
mbed_official	441:d2c15dda23c1	1908	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
mbed_official	441:d2c15dda23c1	1909	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
mbed_official	441:d2c15dda23c1	1910	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
mbed_official	441:d2c15dda23c1	1911	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
mbed_official	441:d2c15dda23c1	1912	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
mbed_official	441:d2c15dda23c1	1913	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
mbed_official	441:d2c15dda23c1	1914
mbed_official	441:d2c15dda23c1	1915	/* Old Bit definition maintained for legacy purpose */
mbed_official	441:d2c15dda23c1	1916	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
mbed_official	441:d2c15dda23c1	1917
mbed_official	441:d2c15dda23c1	1918	/***************** Bit definition for RCC_AHBRSTR register *************/
mbed_official	441:d2c15dda23c1	1919	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
mbed_official	441:d2c15dda23c1	1920	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
mbed_official	441:d2c15dda23c1	1921	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
mbed_official	441:d2c15dda23c1	1922	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /!< GPIOD clock reset /
mbed_official	441:d2c15dda23c1	1923	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /!< GPIOF clock reset /
mbed_official	441:d2c15dda23c1	1924
mbed_official	441:d2c15dda23c1	1925	/***************** Bit definition for RCC_CFGR2 register ***************/
mbed_official	441:d2c15dda23c1	1926	/!< PREDIV configuration /
mbed_official	441:d2c15dda23c1	1927	#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /!< PREDIV[3:0] bits /
mbed_official	441:d2c15dda23c1	1928	#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1929	#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1930	#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	1931	#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	1932
mbed_official	441:d2c15dda23c1	1933	#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /!< PREDIV input clock not divided /
mbed_official	441:d2c15dda23c1	1934	#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /!< PREDIV input clock divided by 2 /
mbed_official	441:d2c15dda23c1	1935	#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /!< PREDIV input clock divided by 3 /
mbed_official	441:d2c15dda23c1	1936	#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /!< PREDIV input clock divided by 4 /
mbed_official	441:d2c15dda23c1	1937	#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /!< PREDIV input clock divided by 5 /
mbed_official	441:d2c15dda23c1	1938	#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /!< PREDIV input clock divided by 6 /
mbed_official	441:d2c15dda23c1	1939	#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /!< PREDIV input clock divided by 7 /
mbed_official	441:d2c15dda23c1	1940	#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /!< PREDIV input clock divided by 8 /
mbed_official	441:d2c15dda23c1	1941	#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /!< PREDIV input clock divided by 9 /
mbed_official	441:d2c15dda23c1	1942	#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /!< PREDIV input clock divided by 10 /
mbed_official	441:d2c15dda23c1	1943	#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /!< PREDIV input clock divided by 11 /
mbed_official	441:d2c15dda23c1	1944	#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /!< PREDIV input clock divided by 12 /
mbed_official	441:d2c15dda23c1	1945	#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /!< PREDIV input clock divided by 13 /
mbed_official	441:d2c15dda23c1	1946	#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /!< PREDIV input clock divided by 14 /
mbed_official	441:d2c15dda23c1	1947	#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /!< PREDIV input clock divided by 15 /
mbed_official	441:d2c15dda23c1	1948	#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /!< PREDIV input clock divided by 16 /
mbed_official	441:d2c15dda23c1	1949
mbed_official	441:d2c15dda23c1	1950	/***************** Bit definition for RCC_CFGR3 register ***************/
mbed_official	441:d2c15dda23c1	1951	/!< USART1 Clock source selection /
mbed_official	441:d2c15dda23c1	1952	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
mbed_official	441:d2c15dda23c1	1953	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	1954	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	1955
mbed_official	441:d2c15dda23c1	1956	#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART1 clock source /
mbed_official	441:d2c15dda23c1	1957	#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /!< System clock selected as USART1 clock source /
mbed_official	441:d2c15dda23c1	1958	#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /!< LSE oscillator clock used as USART1 clock source /
mbed_official	441:d2c15dda23c1	1959	#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /!< HSI oscillator clock used as USART1 clock source /
mbed_official	441:d2c15dda23c1	1960
mbed_official	441:d2c15dda23c1	1961	/!< I2C1 Clock source selection /
mbed_official	441:d2c15dda23c1	1962	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
mbed_official	441:d2c15dda23c1	1963
mbed_official	441:d2c15dda23c1	1964	#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /!< HSI oscillator clock used as I2C1 clock source /
mbed_official	441:d2c15dda23c1	1965	#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /!< System clock selected as I2C1 clock source /
mbed_official	441:d2c15dda23c1	1966
mbed_official	441:d2c15dda23c1	1967	/!< USB Clock source selection /
mbed_official	441:d2c15dda23c1	1968	#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /!< USBSW bits /
mbed_official	441:d2c15dda23c1	1969
mbed_official	441:d2c15dda23c1	1970	#define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /!< PLLCLK selected as USB clock source /
mbed_official	441:d2c15dda23c1	1971
mbed_official	441:d2c15dda23c1	1972	/***************** Bit definition for RCC_CR2 register *****************/
mbed_official	441:d2c15dda23c1	1973	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
mbed_official	441:d2c15dda23c1	1974	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
mbed_official	441:d2c15dda23c1	1975	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
mbed_official	441:d2c15dda23c1	1976	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
mbed_official	441:d2c15dda23c1	1977	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
mbed_official	441:d2c15dda23c1	1978
mbed_official	441:d2c15dda23c1	1979	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	1980	/* */
mbed_official	441:d2c15dda23c1	1981	/* Real-Time Clock (RTC) */
mbed_official	441:d2c15dda23c1	1982	/* */
mbed_official	441:d2c15dda23c1	1983	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	1984	/****************** Bits definition for RTC_TR register ****************/
mbed_official	441:d2c15dda23c1	1985	#define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	1986	#define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official	441:d2c15dda23c1	1987	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	1988	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	1989	#define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official	441:d2c15dda23c1	1990	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	1991	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	1992	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	1993	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	1994	#define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official	441:d2c15dda23c1	1995	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	1996	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	1997	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	1998	#define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official	441:d2c15dda23c1	1999	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2000	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	2001	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	2002	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	2003	#define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official	441:d2c15dda23c1	2004	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2005	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	2006	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	2007	#define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official	441:d2c15dda23c1	2008	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	2009	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	2010	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2011	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	2012
mbed_official	441:d2c15dda23c1	2013	/****************** Bits definition for RTC_DR register ****************/
mbed_official	441:d2c15dda23c1	2014	#define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official	441:d2c15dda23c1	2015	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	2016	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	2017	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	2018	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official	441:d2c15dda23c1	2019	#define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official	441:d2c15dda23c1	2020	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	2021	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	2022	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	2023	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	2024	#define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official	441:d2c15dda23c1	2025	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	2026	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	2027	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	2028	#define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	2029	#define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official	441:d2c15dda23c1	2030	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2031	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	2032	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	2033	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	2034	#define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official	441:d2c15dda23c1	2035	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2036	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	2037	#define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official	441:d2c15dda23c1	2038	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	2039	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	2040	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2041	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	2042
mbed_official	441:d2c15dda23c1	2043	/****************** Bits definition for RTC_CR register ****************/
mbed_official	441:d2c15dda23c1	2044	#define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official	441:d2c15dda23c1	2045	#define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official	441:d2c15dda23c1	2046	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	2047	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	2048	#define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	2049	#define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	2050	#define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	2051	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	2052	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	2053	#define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	2054	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	2055	#define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official	630:825f75ca301e	2056	#define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	2057	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2058	#define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	2059	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	2060	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2061	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official	630:825f75ca301e	2062	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official	630:825f75ca301e	2063	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official	630:825f75ca301e	2064	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official	630:825f75ca301e	2065	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2066
mbed_official	441:d2c15dda23c1	2067	/****************** Bits definition for RTC_ISR register ***************/
mbed_official	441:d2c15dda23c1	2068	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	2069	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	2070	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	2071	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	2072	#define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official	630:825f75ca301e	2073	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	2074	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2075	#define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	2076	#define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	2077	#define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	2078	#define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2079	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official	630:825f75ca301e	2080	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2081	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	2082
mbed_official	441:d2c15dda23c1	2083	/****************** Bits definition for RTC_PRER register **************/
mbed_official	441:d2c15dda23c1	2084	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official	441:d2c15dda23c1	2085	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official	441:d2c15dda23c1	2086
mbed_official	630:825f75ca301e	2087	/****************** Bits definition for RTC_WUTR register **************/
mbed_official	630:825f75ca301e	2088	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official	630:825f75ca301e	2089
mbed_official	441:d2c15dda23c1	2090	/****************** Bits definition for RTC_ALRMAR register ************/
mbed_official	441:d2c15dda23c1	2091	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official	441:d2c15dda23c1	2092	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official	441:d2c15dda23c1	2093	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official	441:d2c15dda23c1	2094	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official	441:d2c15dda23c1	2095	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official	441:d2c15dda23c1	2096	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official	441:d2c15dda23c1	2097	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official	441:d2c15dda23c1	2098	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official	441:d2c15dda23c1	2099	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official	441:d2c15dda23c1	2100	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official	441:d2c15dda23c1	2101	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official	441:d2c15dda23c1	2102	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	2103	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official	441:d2c15dda23c1	2104	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	2105	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	2106	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official	441:d2c15dda23c1	2107	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	2108	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	2109	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	2110	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	2111	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	2112	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official	441:d2c15dda23c1	2113	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	2114	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	2115	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	2116	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official	441:d2c15dda23c1	2117	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2118	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	2119	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	2120	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	2121	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	2122	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official	441:d2c15dda23c1	2123	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2124	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	2125	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	2126	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official	441:d2c15dda23c1	2127	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	2128	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	2129	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2130	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	2131
mbed_official	441:d2c15dda23c1	2132	/****************** Bits definition for RTC_WPR register ***************/
mbed_official	441:d2c15dda23c1	2133	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official	441:d2c15dda23c1	2134
mbed_official	441:d2c15dda23c1	2135	/****************** Bits definition for RTC_SSR register ***************/
mbed_official	441:d2c15dda23c1	2136	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official	441:d2c15dda23c1	2137
mbed_official	441:d2c15dda23c1	2138	/****************** Bits definition for RTC_SHIFTR register ************/
mbed_official	441:d2c15dda23c1	2139	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official	441:d2c15dda23c1	2140	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official	441:d2c15dda23c1	2141
mbed_official	441:d2c15dda23c1	2142	/****************** Bits definition for RTC_TSTR register **************/
mbed_official	441:d2c15dda23c1	2143	#define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official	441:d2c15dda23c1	2144	#define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official	441:d2c15dda23c1	2145	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official	441:d2c15dda23c1	2146	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official	441:d2c15dda23c1	2147	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official	441:d2c15dda23c1	2148	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	2149	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	2150	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	2151	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official	441:d2c15dda23c1	2152	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official	441:d2c15dda23c1	2153	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	2154	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	2155	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	2156	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official	441:d2c15dda23c1	2157	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2158	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	2159	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	2160	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	2161	#define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official	441:d2c15dda23c1	2162	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2163	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	2164	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	2165	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official	441:d2c15dda23c1	2166	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	2167	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	2168	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2169	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	2170
mbed_official	441:d2c15dda23c1	2171	/****************** Bits definition for RTC_TSDR register **************/
mbed_official	441:d2c15dda23c1	2172	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official	441:d2c15dda23c1	2173	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	2174	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	2175	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	2176	#define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	2177	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official	441:d2c15dda23c1	2178	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2179	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	2180	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	2181	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	2182	#define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official	441:d2c15dda23c1	2183	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2184	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	2185	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official	441:d2c15dda23c1	2186	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	2187	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	2188	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2189	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	2190
mbed_official	441:d2c15dda23c1	2191	/****************** Bits definition for RTC_TSSSR register *************/
mbed_official	441:d2c15dda23c1	2192	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official	441:d2c15dda23c1	2193
mbed_official	441:d2c15dda23c1	2194	/****************** Bits definition for RTC_CALR register **************/
mbed_official	441:d2c15dda23c1	2195	#define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	2196	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	2197	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	2198	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official	441:d2c15dda23c1	2199	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	2200	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	2201	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2202	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	2203	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2204	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	2205	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official	441:d2c15dda23c1	2206	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	2207	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2208
mbed_official	441:d2c15dda23c1	2209	/****************** Bits definition for RTC_TAFCR register *************/
mbed_official	441:d2c15dda23c1	2210	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official	441:d2c15dda23c1	2211	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official	441:d2c15dda23c1	2212	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official	441:d2c15dda23c1	2213	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official	441:d2c15dda23c1	2214	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official	441:d2c15dda23c1	2215	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official	441:d2c15dda23c1	2216	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official	441:d2c15dda23c1	2217	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official	441:d2c15dda23c1	2218	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official	441:d2c15dda23c1	2219	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official	441:d2c15dda23c1	2220	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official	441:d2c15dda23c1	2221	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official	441:d2c15dda23c1	2222	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official	441:d2c15dda23c1	2223	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	2224	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	2225	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	2226	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	2227	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	2228
mbed_official	441:d2c15dda23c1	2229	/****************** Bits definition for RTC_ALRMASSR register **********/
mbed_official	441:d2c15dda23c1	2230	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official	441:d2c15dda23c1	2231	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official	441:d2c15dda23c1	2232	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official	441:d2c15dda23c1	2233	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official	441:d2c15dda23c1	2234	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official	441:d2c15dda23c1	2235	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official	441:d2c15dda23c1	2236
mbed_official	441:d2c15dda23c1	2237	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	2238	/* */
mbed_official	441:d2c15dda23c1	2239	/* Serial Peripheral Interface (SPI) */
mbed_official	441:d2c15dda23c1	2240	/* */
mbed_official	441:d2c15dda23c1	2241	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	2242	/***************** Bit definition for SPI_CR1 register *****************/
mbed_official	441:d2c15dda23c1	2243	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
mbed_official	441:d2c15dda23c1	2244	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
mbed_official	441:d2c15dda23c1	2245	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
mbed_official	441:d2c15dda23c1	2246	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
mbed_official	441:d2c15dda23c1	2247	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	2248	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	2249	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	2250	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
mbed_official	441:d2c15dda23c1	2251	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
mbed_official	441:d2c15dda23c1	2252	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
mbed_official	441:d2c15dda23c1	2253	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
mbed_official	441:d2c15dda23c1	2254	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
mbed_official	441:d2c15dda23c1	2255	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
mbed_official	441:d2c15dda23c1	2256	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
mbed_official	441:d2c15dda23c1	2257	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
mbed_official	441:d2c15dda23c1	2258	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
mbed_official	441:d2c15dda23c1	2259	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
mbed_official	441:d2c15dda23c1	2260
mbed_official	441:d2c15dda23c1	2261	/***************** Bit definition for SPI_CR2 register *****************/
mbed_official	441:d2c15dda23c1	2262	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
mbed_official	441:d2c15dda23c1	2263	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
mbed_official	441:d2c15dda23c1	2264	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
mbed_official	441:d2c15dda23c1	2265	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
mbed_official	441:d2c15dda23c1	2266	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
mbed_official	441:d2c15dda23c1	2267	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
mbed_official	441:d2c15dda23c1	2268	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
mbed_official	441:d2c15dda23c1	2269	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
mbed_official	441:d2c15dda23c1	2270	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
mbed_official	441:d2c15dda23c1	2271	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	2272	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	2273	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	2274	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	2275	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
mbed_official	441:d2c15dda23c1	2276	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
mbed_official	441:d2c15dda23c1	2277	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
mbed_official	441:d2c15dda23c1	2278
mbed_official	441:d2c15dda23c1	2279	/****************** Bit definition for SPI_SR register *****************/
mbed_official	441:d2c15dda23c1	2280	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
mbed_official	441:d2c15dda23c1	2281	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
mbed_official	441:d2c15dda23c1	2282	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
mbed_official	441:d2c15dda23c1	2283	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
mbed_official	441:d2c15dda23c1	2284	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
mbed_official	441:d2c15dda23c1	2285	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
mbed_official	441:d2c15dda23c1	2286	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
mbed_official	441:d2c15dda23c1	2287	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
mbed_official	441:d2c15dda23c1	2288	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	2289	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	2290	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
mbed_official	441:d2c15dda23c1	2291	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	2292	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	2293
mbed_official	441:d2c15dda23c1	2294	/****************** Bit definition for SPI_DR register *****************/
mbed_official	441:d2c15dda23c1	2295	#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data Register /
mbed_official	441:d2c15dda23c1	2296
mbed_official	441:d2c15dda23c1	2297	/***************** Bit definition for SPI_CRCPR register ***************/
mbed_official	441:d2c15dda23c1	2298	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /!< CRC polynomial register /
mbed_official	441:d2c15dda23c1	2299
mbed_official	441:d2c15dda23c1	2300	/**************** Bit definition for SPI_RXCRCR register ***************/
mbed_official	441:d2c15dda23c1	2301	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /!< Rx CRC Register /
mbed_official	441:d2c15dda23c1	2302
mbed_official	441:d2c15dda23c1	2303	/**************** Bit definition for SPI_TXCRCR register ***************/
mbed_official	441:d2c15dda23c1	2304	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /!< Tx CRC Register /
mbed_official	441:d2c15dda23c1	2305
mbed_official	441:d2c15dda23c1	2306	/**************** Bit definition for SPI_I2SCFGR register **************/
mbed_official	441:d2c15dda23c1	2307	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!< Keep for compatibility /
mbed_official	441:d2c15dda23c1	2308
mbed_official	441:d2c15dda23c1	2309	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	2310	/* */
mbed_official	441:d2c15dda23c1	2311	/* System Configuration (SYSCFG) */
mbed_official	441:d2c15dda23c1	2312	/* */
mbed_official	441:d2c15dda23c1	2313	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	2314	/*************** Bit definition for SYSCFG_CFGR1 register **************/
mbed_official	441:d2c15dda23c1	2315	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
mbed_official	441:d2c15dda23c1	2316	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
mbed_official	441:d2c15dda23c1	2317	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
mbed_official	441:d2c15dda23c1	2318
mbed_official	630:825f75ca301e	2319
mbed_official	630:825f75ca301e	2320	#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x04001F00) /!< DMA remap mask /
mbed_official	441:d2c15dda23c1	2321	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
mbed_official	441:d2c15dda23c1	2322	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
mbed_official	441:d2c15dda23c1	2323	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
mbed_official	441:d2c15dda23c1	2324	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
mbed_official	441:d2c15dda23c1	2325	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
mbed_official	630:825f75ca301e	2326	#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /!< USART3 DMA remap /
mbed_official	441:d2c15dda23c1	2327
mbed_official	441:d2c15dda23c1	2328	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
mbed_official	441:d2c15dda23c1	2329	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
mbed_official	441:d2c15dda23c1	2330	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
mbed_official	441:d2c15dda23c1	2331	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
mbed_official	441:d2c15dda23c1	2332	#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
mbed_official	630:825f75ca301e	2333
mbed_official	441:d2c15dda23c1	2334
mbed_official	441:d2c15dda23c1	2335	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
mbed_official	630:825f75ca301e	2336	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
mbed_official	630:825f75ca301e	2337	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
mbed_official	630:825f75ca301e	2338	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
mbed_official	630:825f75ca301e	2339	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
mbed_official	441:d2c15dda23c1	2340
mbed_official	441:d2c15dda23c1	2341	/**
mbed_official	441:d2c15dda23c1	2342	* @brief EXTI0 configuration
mbed_official	441:d2c15dda23c1	2343	*/
mbed_official	630:825f75ca301e	2344	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
mbed_official	630:825f75ca301e	2345	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
mbed_official	630:825f75ca301e	2346	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
mbed_official	630:825f75ca301e	2347	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
mbed_official	630:825f75ca301e	2348	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
mbed_official	441:d2c15dda23c1	2349
mbed_official	441:d2c15dda23c1	2350	/**
mbed_official	441:d2c15dda23c1	2351	* @brief EXTI1 configuration
mbed_official	441:d2c15dda23c1	2352	*/
mbed_official	630:825f75ca301e	2353	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
mbed_official	630:825f75ca301e	2354	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
mbed_official	630:825f75ca301e	2355	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
mbed_official	630:825f75ca301e	2356	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
mbed_official	630:825f75ca301e	2357	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
mbed_official	441:d2c15dda23c1	2358
mbed_official	441:d2c15dda23c1	2359	/**
mbed_official	441:d2c15dda23c1	2360	* @brief EXTI2 configuration
mbed_official	441:d2c15dda23c1	2361	*/
mbed_official	630:825f75ca301e	2362	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
mbed_official	630:825f75ca301e	2363	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
mbed_official	630:825f75ca301e	2364	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
mbed_official	630:825f75ca301e	2365	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
mbed_official	630:825f75ca301e	2366	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
mbed_official	441:d2c15dda23c1	2367
mbed_official	441:d2c15dda23c1	2368	/**
mbed_official	441:d2c15dda23c1	2369	* @brief EXTI3 configuration
mbed_official	441:d2c15dda23c1	2370	*/
mbed_official	630:825f75ca301e	2371	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
mbed_official	630:825f75ca301e	2372	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
mbed_official	630:825f75ca301e	2373	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
mbed_official	630:825f75ca301e	2374	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
mbed_official	630:825f75ca301e	2375	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
mbed_official	441:d2c15dda23c1	2376
mbed_official	441:d2c15dda23c1	2377	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
mbed_official	630:825f75ca301e	2378	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
mbed_official	630:825f75ca301e	2379	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
mbed_official	630:825f75ca301e	2380	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
mbed_official	630:825f75ca301e	2381	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
mbed_official	441:d2c15dda23c1	2382
mbed_official	441:d2c15dda23c1	2383	/**
mbed_official	441:d2c15dda23c1	2384	* @brief EXTI4 configuration
mbed_official	441:d2c15dda23c1	2385	*/
mbed_official	630:825f75ca301e	2386	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
mbed_official	630:825f75ca301e	2387	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
mbed_official	630:825f75ca301e	2388	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
mbed_official	630:825f75ca301e	2389	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
mbed_official	630:825f75ca301e	2390	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
mbed_official	441:d2c15dda23c1	2391
mbed_official	441:d2c15dda23c1	2392	/**
mbed_official	441:d2c15dda23c1	2393	* @brief EXTI5 configuration
mbed_official	441:d2c15dda23c1	2394	*/
mbed_official	630:825f75ca301e	2395	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
mbed_official	630:825f75ca301e	2396	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
mbed_official	630:825f75ca301e	2397	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
mbed_official	630:825f75ca301e	2398	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
mbed_official	630:825f75ca301e	2399	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
mbed_official	441:d2c15dda23c1	2400
mbed_official	441:d2c15dda23c1	2401	/**
mbed_official	441:d2c15dda23c1	2402	* @brief EXTI6 configuration
mbed_official	441:d2c15dda23c1	2403	*/
mbed_official	630:825f75ca301e	2404	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
mbed_official	630:825f75ca301e	2405	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
mbed_official	630:825f75ca301e	2406	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
mbed_official	630:825f75ca301e	2407	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
mbed_official	630:825f75ca301e	2408	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
mbed_official	441:d2c15dda23c1	2409
mbed_official	441:d2c15dda23c1	2410	/**
mbed_official	441:d2c15dda23c1	2411	* @brief EXTI7 configuration
mbed_official	441:d2c15dda23c1	2412	*/
mbed_official	630:825f75ca301e	2413	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
mbed_official	630:825f75ca301e	2414	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
mbed_official	630:825f75ca301e	2415	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
mbed_official	630:825f75ca301e	2416	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
mbed_official	630:825f75ca301e	2417	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
mbed_official	441:d2c15dda23c1	2418
mbed_official	441:d2c15dda23c1	2419	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
mbed_official	630:825f75ca301e	2420	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
mbed_official	630:825f75ca301e	2421	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
mbed_official	630:825f75ca301e	2422	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
mbed_official	630:825f75ca301e	2423	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
mbed_official	441:d2c15dda23c1	2424
mbed_official	441:d2c15dda23c1	2425	/**
mbed_official	441:d2c15dda23c1	2426	* @brief EXTI8 configuration
mbed_official	441:d2c15dda23c1	2427	*/
mbed_official	630:825f75ca301e	2428	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
mbed_official	630:825f75ca301e	2429	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
mbed_official	630:825f75ca301e	2430	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
mbed_official	630:825f75ca301e	2431	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
mbed_official	630:825f75ca301e	2432	#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
mbed_official	441:d2c15dda23c1	2433
mbed_official	441:d2c15dda23c1	2434	/**
mbed_official	441:d2c15dda23c1	2435	* @brief EXTI9 configuration
mbed_official	441:d2c15dda23c1	2436	*/
mbed_official	630:825f75ca301e	2437	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
mbed_official	630:825f75ca301e	2438	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
mbed_official	630:825f75ca301e	2439	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
mbed_official	630:825f75ca301e	2440	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
mbed_official	630:825f75ca301e	2441	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
mbed_official	441:d2c15dda23c1	2442
mbed_official	441:d2c15dda23c1	2443	/**
mbed_official	441:d2c15dda23c1	2444	* @brief EXTI10 configuration
mbed_official	441:d2c15dda23c1	2445	*/
mbed_official	630:825f75ca301e	2446	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
mbed_official	630:825f75ca301e	2447	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
mbed_official	630:825f75ca301e	2448	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
mbed_official	630:825f75ca301e	2449	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
mbed_official	630:825f75ca301e	2450	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
mbed_official	441:d2c15dda23c1	2451
mbed_official	441:d2c15dda23c1	2452	/**
mbed_official	441:d2c15dda23c1	2453	* @brief EXTI11 configuration
mbed_official	441:d2c15dda23c1	2454	*/
mbed_official	630:825f75ca301e	2455	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
mbed_official	630:825f75ca301e	2456	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
mbed_official	630:825f75ca301e	2457	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
mbed_official	630:825f75ca301e	2458	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
mbed_official	630:825f75ca301e	2459	#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
mbed_official	441:d2c15dda23c1	2460
mbed_official	441:d2c15dda23c1	2461	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
mbed_official	630:825f75ca301e	2462	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
mbed_official	630:825f75ca301e	2463	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
mbed_official	630:825f75ca301e	2464	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
mbed_official	630:825f75ca301e	2465	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
mbed_official	441:d2c15dda23c1	2466
mbed_official	441:d2c15dda23c1	2467	/**
mbed_official	441:d2c15dda23c1	2468	* @brief EXTI12 configuration
mbed_official	441:d2c15dda23c1	2469	*/
mbed_official	630:825f75ca301e	2470	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
mbed_official	630:825f75ca301e	2471	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
mbed_official	630:825f75ca301e	2472	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
mbed_official	630:825f75ca301e	2473	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
mbed_official	630:825f75ca301e	2474	#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
mbed_official	441:d2c15dda23c1	2475
mbed_official	441:d2c15dda23c1	2476	/**
mbed_official	441:d2c15dda23c1	2477	* @brief EXTI13 configuration
mbed_official	441:d2c15dda23c1	2478	*/
mbed_official	630:825f75ca301e	2479	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
mbed_official	630:825f75ca301e	2480	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
mbed_official	630:825f75ca301e	2481	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
mbed_official	630:825f75ca301e	2482	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
mbed_official	630:825f75ca301e	2483	#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
mbed_official	441:d2c15dda23c1	2484
mbed_official	441:d2c15dda23c1	2485	/**
mbed_official	441:d2c15dda23c1	2486	* @brief EXTI14 configuration
mbed_official	441:d2c15dda23c1	2487	*/
mbed_official	630:825f75ca301e	2488	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
mbed_official	630:825f75ca301e	2489	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
mbed_official	630:825f75ca301e	2490	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
mbed_official	630:825f75ca301e	2491	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
mbed_official	630:825f75ca301e	2492	#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
mbed_official	441:d2c15dda23c1	2493
mbed_official	441:d2c15dda23c1	2494	/**
mbed_official	441:d2c15dda23c1	2495	* @brief EXTI15 configuration
mbed_official	441:d2c15dda23c1	2496	*/
mbed_official	630:825f75ca301e	2497	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
mbed_official	630:825f75ca301e	2498	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
mbed_official	630:825f75ca301e	2499	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
mbed_official	630:825f75ca301e	2500	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
mbed_official	630:825f75ca301e	2501	#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
mbed_official	441:d2c15dda23c1	2502
mbed_official	441:d2c15dda23c1	2503	/*************** Bit definition for SYSCFG_CFGR2 register **************/
mbed_official	441:d2c15dda23c1	2504	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
mbed_official	441:d2c15dda23c1	2505	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
mbed_official	441:d2c15dda23c1	2506	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
mbed_official	441:d2c15dda23c1	2507	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
mbed_official	441:d2c15dda23c1	2508
mbed_official	441:d2c15dda23c1	2509	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	2510	/* */
mbed_official	441:d2c15dda23c1	2511	/* Timers (TIM) */
mbed_official	441:d2c15dda23c1	2512	/* */
mbed_official	441:d2c15dda23c1	2513	/*****************************************************************************/
mbed_official	441:d2c15dda23c1	2514	/***************** Bit definition for TIM_CR1 register *****************/
mbed_official	441:d2c15dda23c1	2515	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
mbed_official	441:d2c15dda23c1	2516	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
mbed_official	441:d2c15dda23c1	2517	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
mbed_official	441:d2c15dda23c1	2518	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
mbed_official	441:d2c15dda23c1	2519	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
mbed_official	441:d2c15dda23c1	2520
mbed_official	441:d2c15dda23c1	2521	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
mbed_official	441:d2c15dda23c1	2522	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2523	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2524
mbed_official	441:d2c15dda23c1	2525	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
mbed_official	441:d2c15dda23c1	2526
mbed_official	441:d2c15dda23c1	2527	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
mbed_official	441:d2c15dda23c1	2528	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2529	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2530
mbed_official	441:d2c15dda23c1	2531	/***************** Bit definition for TIM_CR2 register *****************/
mbed_official	441:d2c15dda23c1	2532	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
mbed_official	441:d2c15dda23c1	2533	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
mbed_official	441:d2c15dda23c1	2534	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
mbed_official	441:d2c15dda23c1	2535
mbed_official	441:d2c15dda23c1	2536	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
mbed_official	441:d2c15dda23c1	2537	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2538	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2539	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2540
mbed_official	441:d2c15dda23c1	2541	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
mbed_official	441:d2c15dda23c1	2542	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
mbed_official	441:d2c15dda23c1	2543	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
mbed_official	441:d2c15dda23c1	2544	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
mbed_official	441:d2c15dda23c1	2545	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
mbed_official	441:d2c15dda23c1	2546	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
mbed_official	441:d2c15dda23c1	2547	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
mbed_official	441:d2c15dda23c1	2548	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
mbed_official	441:d2c15dda23c1	2549
mbed_official	441:d2c15dda23c1	2550	/***************** Bit definition for TIM_SMCR register ****************/
mbed_official	441:d2c15dda23c1	2551	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
mbed_official	441:d2c15dda23c1	2552	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2553	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2554	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2555
mbed_official	441:d2c15dda23c1	2556	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
mbed_official	441:d2c15dda23c1	2557
mbed_official	441:d2c15dda23c1	2558	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
mbed_official	441:d2c15dda23c1	2559	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2560	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2561	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2562
mbed_official	441:d2c15dda23c1	2563	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
mbed_official	441:d2c15dda23c1	2564
mbed_official	441:d2c15dda23c1	2565	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
mbed_official	441:d2c15dda23c1	2566	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2567	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2568	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2569	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	2570
mbed_official	441:d2c15dda23c1	2571	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
mbed_official	441:d2c15dda23c1	2572	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2573	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2574
mbed_official	441:d2c15dda23c1	2575	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
mbed_official	441:d2c15dda23c1	2576	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
mbed_official	441:d2c15dda23c1	2577
mbed_official	441:d2c15dda23c1	2578	/***************** Bit definition for TIM_DIER register ****************/
mbed_official	441:d2c15dda23c1	2579	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
mbed_official	441:d2c15dda23c1	2580	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
mbed_official	441:d2c15dda23c1	2581	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
mbed_official	441:d2c15dda23c1	2582	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
mbed_official	441:d2c15dda23c1	2583	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
mbed_official	441:d2c15dda23c1	2584	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
mbed_official	441:d2c15dda23c1	2585	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
mbed_official	441:d2c15dda23c1	2586	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
mbed_official	441:d2c15dda23c1	2587	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
mbed_official	441:d2c15dda23c1	2588	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
mbed_official	441:d2c15dda23c1	2589	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
mbed_official	441:d2c15dda23c1	2590	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
mbed_official	441:d2c15dda23c1	2591	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
mbed_official	441:d2c15dda23c1	2592	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
mbed_official	441:d2c15dda23c1	2593	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
mbed_official	441:d2c15dda23c1	2594
mbed_official	441:d2c15dda23c1	2595	/****************** Bit definition for TIM_SR register *****************/
mbed_official	441:d2c15dda23c1	2596	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
mbed_official	441:d2c15dda23c1	2597	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
mbed_official	441:d2c15dda23c1	2598	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
mbed_official	441:d2c15dda23c1	2599	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
mbed_official	441:d2c15dda23c1	2600	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
mbed_official	441:d2c15dda23c1	2601	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
mbed_official	441:d2c15dda23c1	2602	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
mbed_official	441:d2c15dda23c1	2603	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
mbed_official	441:d2c15dda23c1	2604	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
mbed_official	441:d2c15dda23c1	2605	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
mbed_official	441:d2c15dda23c1	2606	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
mbed_official	441:d2c15dda23c1	2607	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
mbed_official	441:d2c15dda23c1	2608
mbed_official	441:d2c15dda23c1	2609	/***************** Bit definition for TIM_EGR register *****************/
mbed_official	441:d2c15dda23c1	2610	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
mbed_official	441:d2c15dda23c1	2611	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
mbed_official	441:d2c15dda23c1	2612	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
mbed_official	441:d2c15dda23c1	2613	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
mbed_official	441:d2c15dda23c1	2614	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
mbed_official	441:d2c15dda23c1	2615	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
mbed_official	441:d2c15dda23c1	2616	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
mbed_official	441:d2c15dda23c1	2617	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
mbed_official	441:d2c15dda23c1	2618
mbed_official	441:d2c15dda23c1	2619	/**************** Bit definition for TIM_CCMR1 register ****************/
mbed_official	441:d2c15dda23c1	2620	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
mbed_official	441:d2c15dda23c1	2621	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2622	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2623
mbed_official	441:d2c15dda23c1	2624	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
mbed_official	441:d2c15dda23c1	2625	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
mbed_official	441:d2c15dda23c1	2626
mbed_official	441:d2c15dda23c1	2627	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
mbed_official	441:d2c15dda23c1	2628	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2629	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2630	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2631
mbed_official	441:d2c15dda23c1	2632	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
mbed_official	441:d2c15dda23c1	2633
mbed_official	441:d2c15dda23c1	2634	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
mbed_official	441:d2c15dda23c1	2635	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2636	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2637
mbed_official	441:d2c15dda23c1	2638	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
mbed_official	441:d2c15dda23c1	2639	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
mbed_official	441:d2c15dda23c1	2640
mbed_official	441:d2c15dda23c1	2641	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
mbed_official	441:d2c15dda23c1	2642	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2643	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2644	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2645
mbed_official	441:d2c15dda23c1	2646	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
mbed_official	441:d2c15dda23c1	2647
mbed_official	441:d2c15dda23c1	2648	/---------------------------------------------------------------------------/
mbed_official	441:d2c15dda23c1	2649
mbed_official	441:d2c15dda23c1	2650	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
mbed_official	441:d2c15dda23c1	2651	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2652	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2653
mbed_official	441:d2c15dda23c1	2654	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
mbed_official	441:d2c15dda23c1	2655	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2656	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2657	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2658	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	2659
mbed_official	441:d2c15dda23c1	2660	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
mbed_official	441:d2c15dda23c1	2661	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2662	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2663
mbed_official	441:d2c15dda23c1	2664	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
mbed_official	441:d2c15dda23c1	2665	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2666	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2667	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2668	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	2669
mbed_official	441:d2c15dda23c1	2670	/**************** Bit definition for TIM_CCMR2 register ****************/
mbed_official	441:d2c15dda23c1	2671	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
mbed_official	441:d2c15dda23c1	2672	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2673	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2674
mbed_official	441:d2c15dda23c1	2675	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
mbed_official	441:d2c15dda23c1	2676	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
mbed_official	441:d2c15dda23c1	2677
mbed_official	441:d2c15dda23c1	2678	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
mbed_official	441:d2c15dda23c1	2679	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2680	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2681	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2682
mbed_official	441:d2c15dda23c1	2683	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
mbed_official	441:d2c15dda23c1	2684
mbed_official	441:d2c15dda23c1	2685	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
mbed_official	441:d2c15dda23c1	2686	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2687	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2688
mbed_official	441:d2c15dda23c1	2689	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
mbed_official	441:d2c15dda23c1	2690	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
mbed_official	441:d2c15dda23c1	2691
mbed_official	441:d2c15dda23c1	2692	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
mbed_official	441:d2c15dda23c1	2693	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2694	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2695	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2696
mbed_official	441:d2c15dda23c1	2697	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
mbed_official	441:d2c15dda23c1	2698
mbed_official	441:d2c15dda23c1	2699	/---------------------------------------------------------------------------/
mbed_official	441:d2c15dda23c1	2700
mbed_official	441:d2c15dda23c1	2701	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
mbed_official	441:d2c15dda23c1	2702	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2703	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2704
mbed_official	441:d2c15dda23c1	2705	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
mbed_official	441:d2c15dda23c1	2706	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2707	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2708	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2709	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	2710
mbed_official	441:d2c15dda23c1	2711	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
mbed_official	441:d2c15dda23c1	2712	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2713	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2714
mbed_official	441:d2c15dda23c1	2715	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
mbed_official	441:d2c15dda23c1	2716	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2717	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2718	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2719	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	2720
mbed_official	441:d2c15dda23c1	2721	/***************** Bit definition for TIM_CCER register ****************/
mbed_official	441:d2c15dda23c1	2722	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
mbed_official	441:d2c15dda23c1	2723	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
mbed_official	441:d2c15dda23c1	2724	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
mbed_official	441:d2c15dda23c1	2725	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
mbed_official	441:d2c15dda23c1	2726	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
mbed_official	441:d2c15dda23c1	2727	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
mbed_official	441:d2c15dda23c1	2728	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
mbed_official	441:d2c15dda23c1	2729	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
mbed_official	441:d2c15dda23c1	2730	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
mbed_official	441:d2c15dda23c1	2731	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
mbed_official	441:d2c15dda23c1	2732	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
mbed_official	441:d2c15dda23c1	2733	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
mbed_official	441:d2c15dda23c1	2734	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
mbed_official	441:d2c15dda23c1	2735	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
mbed_official	441:d2c15dda23c1	2736	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
mbed_official	441:d2c15dda23c1	2737
mbed_official	441:d2c15dda23c1	2738	/***************** Bit definition for TIM_CNT register *****************/
mbed_official	441:d2c15dda23c1	2739	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
mbed_official	441:d2c15dda23c1	2740
mbed_official	441:d2c15dda23c1	2741	/***************** Bit definition for TIM_PSC register *****************/
mbed_official	441:d2c15dda23c1	2742	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
mbed_official	441:d2c15dda23c1	2743
mbed_official	441:d2c15dda23c1	2744	/***************** Bit definition for TIM_ARR register *****************/
mbed_official	441:d2c15dda23c1	2745	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
mbed_official	441:d2c15dda23c1	2746
mbed_official	441:d2c15dda23c1	2747	/***************** Bit definition for TIM_RCR register *****************/
mbed_official	441:d2c15dda23c1	2748	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
mbed_official	441:d2c15dda23c1	2749
mbed_official	441:d2c15dda23c1	2750	/***************** Bit definition for TIM_CCR1 register ****************/
mbed_official	441:d2c15dda23c1	2751	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
mbed_official	441:d2c15dda23c1	2752
mbed_official	441:d2c15dda23c1	2753	/***************** Bit definition for TIM_CCR2 register ****************/
mbed_official	441:d2c15dda23c1	2754	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
mbed_official	441:d2c15dda23c1	2755
mbed_official	441:d2c15dda23c1	2756	/***************** Bit definition for TIM_CCR3 register ****************/
mbed_official	441:d2c15dda23c1	2757	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
mbed_official	441:d2c15dda23c1	2758
mbed_official	441:d2c15dda23c1	2759	/***************** Bit definition for TIM_CCR4 register ****************/
mbed_official	441:d2c15dda23c1	2760	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
mbed_official	441:d2c15dda23c1	2761
mbed_official	441:d2c15dda23c1	2762	/***************** Bit definition for TIM_BDTR register ****************/
mbed_official	441:d2c15dda23c1	2763	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
mbed_official	441:d2c15dda23c1	2764	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2765	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2766	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2767	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	2768	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
mbed_official	441:d2c15dda23c1	2769	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
mbed_official	441:d2c15dda23c1	2770	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
mbed_official	441:d2c15dda23c1	2771	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
mbed_official	441:d2c15dda23c1	2772
mbed_official	441:d2c15dda23c1	2773	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
mbed_official	441:d2c15dda23c1	2774	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2775	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2776
mbed_official	441:d2c15dda23c1	2777	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
mbed_official	441:d2c15dda23c1	2778	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
mbed_official	441:d2c15dda23c1	2779	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
mbed_official	441:d2c15dda23c1	2780	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
mbed_official	441:d2c15dda23c1	2781	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
mbed_official	441:d2c15dda23c1	2782	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
mbed_official	441:d2c15dda23c1	2783
mbed_official	441:d2c15dda23c1	2784	/***************** Bit definition for TIM_DCR register *****************/
mbed_official	441:d2c15dda23c1	2785	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
mbed_official	441:d2c15dda23c1	2786	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2787	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2788	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2789	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	2790	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
mbed_official	441:d2c15dda23c1	2791
mbed_official	441:d2c15dda23c1	2792	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
mbed_official	441:d2c15dda23c1	2793	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2794	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2795	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	2796	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	2797	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
mbed_official	441:d2c15dda23c1	2798
mbed_official	441:d2c15dda23c1	2799	/***************** Bit definition for TIM_DMAR register ****************/
mbed_official	441:d2c15dda23c1	2800	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
mbed_official	441:d2c15dda23c1	2801
mbed_official	441:d2c15dda23c1	2802	/***************** Bit definition for TIM14_OR register ******************/
mbed_official	441:d2c15dda23c1	2803	#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
mbed_official	441:d2c15dda23c1	2804	#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	2805	#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	2806
mbed_official	441:d2c15dda23c1	2807	/******************************************************************************/
mbed_official	441:d2c15dda23c1	2808	/* */
mbed_official	441:d2c15dda23c1	2809	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official	441:d2c15dda23c1	2810	/* */
mbed_official	441:d2c15dda23c1	2811	/******************************************************************************/
mbed_official	441:d2c15dda23c1	2812	/**************** Bit definition for USART_CR1 register *****************/
mbed_official	441:d2c15dda23c1	2813	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
mbed_official	441:d2c15dda23c1	2814	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
mbed_official	441:d2c15dda23c1	2815	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
mbed_official	441:d2c15dda23c1	2816	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
mbed_official	441:d2c15dda23c1	2817	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
mbed_official	441:d2c15dda23c1	2818	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
mbed_official	441:d2c15dda23c1	2819	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
mbed_official	441:d2c15dda23c1	2820	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
mbed_official	441:d2c15dda23c1	2821	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
mbed_official	441:d2c15dda23c1	2822	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
mbed_official	441:d2c15dda23c1	2823	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
mbed_official	441:d2c15dda23c1	2824	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length bit 0 /
mbed_official	441:d2c15dda23c1	2825	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
mbed_official	441:d2c15dda23c1	2826	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
mbed_official	441:d2c15dda23c1	2827	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
mbed_official	441:d2c15dda23c1	2828	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
mbed_official	441:d2c15dda23c1	2829	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	2830	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	2831	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	2832	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	2833	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	441:d2c15dda23c1	2834	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
mbed_official	441:d2c15dda23c1	2835	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	2836	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	2837	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
mbed_official	441:d2c15dda23c1	2838	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
mbed_official	441:d2c15dda23c1	2839	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
mbed_official	441:d2c15dda23c1	2840	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
mbed_official	441:d2c15dda23c1	2841	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
mbed_official	441:d2c15dda23c1	2842	#define USART_CR1_M1 ((uint32_t)0x10000000) /!< Word length bit 1 /
mbed_official	441:d2c15dda23c1	2843	#define USART_CR1_M ((uint32_t)0x10001000) /!< [M1:M0] Word length /
mbed_official	441:d2c15dda23c1	2844
mbed_official	441:d2c15dda23c1	2845	/**************** Bit definition for USART_CR2 register *****************/
mbed_official	441:d2c15dda23c1	2846	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
mbed_official	441:d2c15dda23c1	2847	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
mbed_official	441:d2c15dda23c1	2848	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
mbed_official	441:d2c15dda23c1	2849	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
mbed_official	441:d2c15dda23c1	2850	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
mbed_official	441:d2c15dda23c1	2851	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
mbed_official	441:d2c15dda23c1	2852	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	2853	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	2854	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< Keep for compatibility /
mbed_official	441:d2c15dda23c1	2855	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
mbed_official	441:d2c15dda23c1	2856	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
mbed_official	441:d2c15dda23c1	2857	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
mbed_official	441:d2c15dda23c1	2858	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
mbed_official	441:d2c15dda23c1	2859	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
mbed_official	441:d2c15dda23c1	2860	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
mbed_official	441:d2c15dda23c1	2861	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
mbed_official	441:d2c15dda23c1	2862	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	441:d2c15dda23c1	2863	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	441:d2c15dda23c1	2864	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
mbed_official	441:d2c15dda23c1	2865	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
mbed_official	441:d2c15dda23c1	2866
mbed_official	441:d2c15dda23c1	2867	/**************** Bit definition for USART_CR3 register *****************/
mbed_official	441:d2c15dda23c1	2868	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
mbed_official	441:d2c15dda23c1	2869	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< Keep for compatibility /
mbed_official	441:d2c15dda23c1	2870	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
mbed_official	441:d2c15dda23c1	2871	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Keep for compatibility /
mbed_official	441:d2c15dda23c1	2872	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
mbed_official	441:d2c15dda23c1	2873	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
mbed_official	441:d2c15dda23c1	2874	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
mbed_official	441:d2c15dda23c1	2875	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
mbed_official	441:d2c15dda23c1	2876	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
mbed_official	441:d2c15dda23c1	2877	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
mbed_official	441:d2c15dda23c1	2878	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
mbed_official	441:d2c15dda23c1	2879	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
mbed_official	441:d2c15dda23c1	2880	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
mbed_official	441:d2c15dda23c1	2881	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
mbed_official	441:d2c15dda23c1	2882
mbed_official	441:d2c15dda23c1	2883	/**************** Bit definition for USART_BRR register *****************/
mbed_official	441:d2c15dda23c1	2884	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
mbed_official	441:d2c15dda23c1	2885	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
mbed_official	441:d2c15dda23c1	2886
mbed_official	441:d2c15dda23c1	2887	/**************** Bit definition for USART_GTPR register ****************/
mbed_official	441:d2c15dda23c1	2888	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
mbed_official	441:d2c15dda23c1	2889	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
mbed_official	441:d2c15dda23c1	2890
mbed_official	441:d2c15dda23c1	2891
mbed_official	441:d2c15dda23c1	2892	/***************** Bit definition for USART_RTOR register ***************/
mbed_official	441:d2c15dda23c1	2893	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
mbed_official	441:d2c15dda23c1	2894	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
mbed_official	441:d2c15dda23c1	2895
mbed_official	441:d2c15dda23c1	2896	/***************** Bit definition for USART_RQR register ****************/
mbed_official	441:d2c15dda23c1	2897	#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /!< Auto-Baud Rate Request /
mbed_official	441:d2c15dda23c1	2898	#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /!< Send Break Request /
mbed_official	441:d2c15dda23c1	2899	#define USART_RQR_MMRQ ((uint32_t)0x00000004) /!< Mute Mode Request /
mbed_official	441:d2c15dda23c1	2900	#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /!< Receive Data flush Request /
mbed_official	441:d2c15dda23c1	2901
mbed_official	441:d2c15dda23c1	2902	/***************** Bit definition for USART_ISR register ****************/
mbed_official	441:d2c15dda23c1	2903	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
mbed_official	441:d2c15dda23c1	2904	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
mbed_official	441:d2c15dda23c1	2905	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
mbed_official	441:d2c15dda23c1	2906	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
mbed_official	441:d2c15dda23c1	2907	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
mbed_official	441:d2c15dda23c1	2908	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
mbed_official	441:d2c15dda23c1	2909	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
mbed_official	441:d2c15dda23c1	2910	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
mbed_official	441:d2c15dda23c1	2911	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
mbed_official	441:d2c15dda23c1	2912	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
mbed_official	441:d2c15dda23c1	2913	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
mbed_official	441:d2c15dda23c1	2914	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
mbed_official	441:d2c15dda23c1	2915	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
mbed_official	441:d2c15dda23c1	2916	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
mbed_official	441:d2c15dda23c1	2917	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
mbed_official	441:d2c15dda23c1	2918	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
mbed_official	441:d2c15dda23c1	2919	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
mbed_official	441:d2c15dda23c1	2920	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
mbed_official	441:d2c15dda23c1	2921	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
mbed_official	441:d2c15dda23c1	2922
mbed_official	441:d2c15dda23c1	2923	/***************** Bit definition for USART_ICR register ****************/
mbed_official	441:d2c15dda23c1	2924	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
mbed_official	441:d2c15dda23c1	2925	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
mbed_official	441:d2c15dda23c1	2926	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
mbed_official	441:d2c15dda23c1	2927	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
mbed_official	441:d2c15dda23c1	2928	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
mbed_official	441:d2c15dda23c1	2929	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
mbed_official	441:d2c15dda23c1	2930	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
mbed_official	441:d2c15dda23c1	2931	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
mbed_official	441:d2c15dda23c1	2932	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
mbed_official	441:d2c15dda23c1	2933
mbed_official	441:d2c15dda23c1	2934	/***************** Bit definition for USART_RDR register ****************/
mbed_official	441:d2c15dda23c1	2935	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
mbed_official	441:d2c15dda23c1	2936
mbed_official	441:d2c15dda23c1	2937	/***************** Bit definition for USART_TDR register ****************/
mbed_official	441:d2c15dda23c1	2938	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
mbed_official	441:d2c15dda23c1	2939
mbed_official	441:d2c15dda23c1	2940	/******************************************************************************/
mbed_official	441:d2c15dda23c1	2941	/* */
mbed_official	441:d2c15dda23c1	2942	/* USB Device General registers */
mbed_official	441:d2c15dda23c1	2943	/* */
mbed_official	441:d2c15dda23c1	2944	/******************************************************************************/
mbed_official	441:d2c15dda23c1	2945	#define USB_CNTR (USB_BASE + 0x40) /!< Control register /
mbed_official	441:d2c15dda23c1	2946	#define USB_ISTR (USB_BASE + 0x44) /!< Interrupt status register /
mbed_official	441:d2c15dda23c1	2947	#define USB_FNR (USB_BASE + 0x48) /!< Frame number register /
mbed_official	441:d2c15dda23c1	2948	#define USB_DADDR (USB_BASE + 0x4C) /!< Device address register /
mbed_official	441:d2c15dda23c1	2949	#define USB_BTABLE (USB_BASE + 0x50) /!< Buffer Table address register /
mbed_official	441:d2c15dda23c1	2950	#define USB_LPMCSR (USB_BASE + 0x54) /!< LPM Control and Status register /
mbed_official	441:d2c15dda23c1	2951	#define USB_BCDR (USB_BASE + 0x58) /!< Battery Charging detector register/
mbed_official	441:d2c15dda23c1	2952
mbed_official	441:d2c15dda23c1	2953	/************************** ISTR interrupt events ***********************/
mbed_official	441:d2c15dda23c1	2954	#define USB_ISTR_CTR ((uint16_t)0x8000) /!< Correct TRansfer (clear-only bit) /
mbed_official	441:d2c15dda23c1	2955	#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /!< DMA OVeR/underrun (clear-only bit) /
mbed_official	441:d2c15dda23c1	2956	#define USB_ISTR_ERR ((uint16_t)0x2000) /!< ERRor (clear-only bit) /
mbed_official	441:d2c15dda23c1	2957	#define USB_ISTR_WKUP ((uint16_t)0x1000) /!< WaKe UP (clear-only bit) /
mbed_official	441:d2c15dda23c1	2958	#define USB_ISTR_SUSP ((uint16_t)0x0800) /!< SUSPend (clear-only bit) /
mbed_official	441:d2c15dda23c1	2959	#define USB_ISTR_RESET ((uint16_t)0x0400) /!< RESET (clear-only bit) /
mbed_official	441:d2c15dda23c1	2960	#define USB_ISTR_SOF ((uint16_t)0x0200) /!< Start Of Frame (clear-only bit) /
mbed_official	441:d2c15dda23c1	2961	#define USB_ISTR_ESOF ((uint16_t)0x0100) /!< Expected Start Of Frame (clear-only bit) /
mbed_official	441:d2c15dda23c1	2962	#define USB_ISTR_L1REQ ((uint16_t)0x0080) /!< LPM L1 state request /
mbed_official	441:d2c15dda23c1	2963	#define USB_ISTR_DIR ((uint16_t)0x0010) /!< DIRection of transaction (read-only bit) /
mbed_official	441:d2c15dda23c1	2964	#define USB_ISTR_EP_ID ((uint16_t)0x000F) /!< EndPoint IDentifier (read-only bit) /
mbed_official	441:d2c15dda23c1	2965
mbed_official	441:d2c15dda23c1	2966	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
mbed_official	441:d2c15dda23c1	2967	#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
mbed_official	441:d2c15dda23c1	2968	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
mbed_official	441:d2c15dda23c1	2969	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
mbed_official	441:d2c15dda23c1	2970	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
mbed_official	441:d2c15dda23c1	2971	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
mbed_official	441:d2c15dda23c1	2972	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
mbed_official	441:d2c15dda23c1	2973	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
mbed_official	441:d2c15dda23c1	2974	#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /!< clear LPM L1 bit /
mbed_official	441:d2c15dda23c1	2975
mbed_official	441:d2c15dda23c1	2976	/*********************** CNTR control register bits definitions *********/
mbed_official	441:d2c15dda23c1	2977	#define USB_CNTR_CTRM ((uint16_t)0x8000) /!< Correct TRansfer Mask /
mbed_official	441:d2c15dda23c1	2978	#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /!< DMA OVeR/underrun Mask /
mbed_official	441:d2c15dda23c1	2979	#define USB_CNTR_ERRM ((uint16_t)0x2000) /!< ERRor Mask /
mbed_official	441:d2c15dda23c1	2980	#define USB_CNTR_WKUPM ((uint16_t)0x1000) /!< WaKe UP Mask /
mbed_official	441:d2c15dda23c1	2981	#define USB_CNTR_SUSPM ((uint16_t)0x0800) /!< SUSPend Mask /
mbed_official	441:d2c15dda23c1	2982	#define USB_CNTR_RESETM ((uint16_t)0x0400) /!< RESET Mask /
mbed_official	441:d2c15dda23c1	2983	#define USB_CNTR_SOFM ((uint16_t)0x0200) /!< Start Of Frame Mask /
mbed_official	441:d2c15dda23c1	2984	#define USB_CNTR_ESOFM ((uint16_t)0x0100) /!< Expected Start Of Frame Mask /
mbed_official	441:d2c15dda23c1	2985	#define USB_CNTR_L1REQM ((uint16_t)0x0080) /!< LPM L1 state request interrupt mask /
mbed_official	441:d2c15dda23c1	2986	#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /!< LPM L1 Resume request /
mbed_official	441:d2c15dda23c1	2987	#define USB_CNTR_RESUME ((uint16_t)0x0010) /!< RESUME request /
mbed_official	441:d2c15dda23c1	2988	#define USB_CNTR_FSUSP ((uint16_t)0x0008) /!< Force SUSPend /
mbed_official	441:d2c15dda23c1	2989	#define USB_CNTR_LPMODE ((uint16_t)0x0004) /!< Low-power MODE /
mbed_official	441:d2c15dda23c1	2990	#define USB_CNTR_PDWN ((uint16_t)0x0002) /!< Power DoWN /
mbed_official	441:d2c15dda23c1	2991	#define USB_CNTR_FRES ((uint16_t)0x0001) /!< Force USB RESet /
mbed_official	441:d2c15dda23c1	2992
mbed_official	441:d2c15dda23c1	2993	/*********************** BCDR control register bits definitions *********/
mbed_official	441:d2c15dda23c1	2994	#define USB_BCDR_DPPU ((uint16_t)0x8000) /!< DP Pull-up Enable /
mbed_official	441:d2c15dda23c1	2995	#define USB_BCDR_PS2DET ((uint16_t)0x0080) /!< PS2 port or proprietary charger detected /
mbed_official	441:d2c15dda23c1	2996	#define USB_BCDR_SDET ((uint16_t)0x0040) /!< Secondary detection (SD) status /
mbed_official	441:d2c15dda23c1	2997	#define USB_BCDR_PDET ((uint16_t)0x0020) /!< Primary detection (PD) status /
mbed_official	441:d2c15dda23c1	2998	#define USB_BCDR_DCDET ((uint16_t)0x0010) /!< Data contact detection (DCD) status /
mbed_official	441:d2c15dda23c1	2999	#define USB_BCDR_SDEN ((uint16_t)0x0008) /!< Secondary detection (SD) mode enable /
mbed_official	441:d2c15dda23c1	3000	#define USB_BCDR_PDEN ((uint16_t)0x0004) /!< Primary detection (PD) mode enable /
mbed_official	441:d2c15dda23c1	3001	#define USB_BCDR_DCDEN ((uint16_t)0x0002) /!< Data contact detection (DCD) mode enable /
mbed_official	441:d2c15dda23c1	3002	#define USB_BCDR_BCDEN ((uint16_t)0x0001) /!< Battery charging detector (BCD) enable /
mbed_official	441:d2c15dda23c1	3003
mbed_official	441:d2c15dda23c1	3004	/************************* LPM register bits definitions ****************/
mbed_official	441:d2c15dda23c1	3005	#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /!< BESL value received with last ACKed LPM Token /
mbed_official	441:d2c15dda23c1	3006	#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /!< bRemoteWake value received with last ACKed LPM Token /
mbed_official	441:d2c15dda23c1	3007	#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /!< LPM Token acknowledge enable/
mbed_official	441:d2c15dda23c1	3008	#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /!< LPM support enable /
mbed_official	441:d2c15dda23c1	3009
mbed_official	441:d2c15dda23c1	3010	/****************** FNR Frame Number Register bit definitions **********/
mbed_official	441:d2c15dda23c1	3011	#define USB_FNR_RXDP ((uint16_t)0x8000) /!< status of D+ data line /
mbed_official	441:d2c15dda23c1	3012	#define USB_FNR_RXDM ((uint16_t)0x4000) /!< status of D- data line /
mbed_official	441:d2c15dda23c1	3013	#define USB_FNR_LCK ((uint16_t)0x2000) /!< LoCKed /
mbed_official	441:d2c15dda23c1	3014	#define USB_FNR_LSOF ((uint16_t)0x1800) /!< Lost SOF /
mbed_official	441:d2c15dda23c1	3015	#define USB_FNR_FN ((uint16_t)0x07FF) /!< Frame Number /
mbed_official	441:d2c15dda23c1	3016
mbed_official	441:d2c15dda23c1	3017	/****************** DADDR Device ADDRess bit definitions **************/
mbed_official	441:d2c15dda23c1	3018	#define USB_DADDR_EF ((uint8_t)0x80) /!< USB device address Enable Function /
mbed_official	441:d2c15dda23c1	3019	#define USB_DADDR_ADD ((uint8_t)0x7F) /!< USB device address /
mbed_official	441:d2c15dda23c1	3020
mbed_official	441:d2c15dda23c1	3021	/**************************** Endpoint register ***********************/
mbed_official	441:d2c15dda23c1	3022	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
mbed_official	441:d2c15dda23c1	3023	#define USB_EP1R (USB_BASE + 0x04) /!< endpoint 1 register address /
mbed_official	441:d2c15dda23c1	3024	#define USB_EP2R (USB_BASE + 0x08) /!< endpoint 2 register address /
mbed_official	441:d2c15dda23c1	3025	#define USB_EP3R (USB_BASE + 0x0C) /!< endpoint 3 register address /
mbed_official	441:d2c15dda23c1	3026	#define USB_EP4R (USB_BASE + 0x10) /!< endpoint 4 register address /
mbed_official	441:d2c15dda23c1	3027	#define USB_EP5R (USB_BASE + 0x14) /!< endpoint 5 register address /
mbed_official	441:d2c15dda23c1	3028	#define USB_EP6R (USB_BASE + 0x18) /!< endpoint 6 register address /
mbed_official	441:d2c15dda23c1	3029	#define USB_EP7R (USB_BASE + 0x1C) /!< endpoint 7 register address /
mbed_official	441:d2c15dda23c1	3030	/* bit positions */
mbed_official	441:d2c15dda23c1	3031	#define USB_EP_CTR_RX ((uint16_t)0x8000) /!< EndPoint Correct TRansfer RX /
mbed_official	441:d2c15dda23c1	3032	#define USB_EP_DTOG_RX ((uint16_t)0x4000) /!< EndPoint Data TOGGLE RX /
mbed_official	441:d2c15dda23c1	3033	#define USB_EPRX_STAT ((uint16_t)0x3000) /!< EndPoint RX STATus bit field /
mbed_official	441:d2c15dda23c1	3034	#define USB_EP_SETUP ((uint16_t)0x0800) /!< EndPoint SETUP /
mbed_official	441:d2c15dda23c1	3035	#define USB_EP_T_FIELD ((uint16_t)0x0600) /!< EndPoint TYPE /
mbed_official	441:d2c15dda23c1	3036	#define USB_EP_KIND ((uint16_t)0x0100) /!< EndPoint KIND /
mbed_official	441:d2c15dda23c1	3037	#define USB_EP_CTR_TX ((uint16_t)0x0080) /!< EndPoint Correct TRansfer TX /
mbed_official	441:d2c15dda23c1	3038	#define USB_EP_DTOG_TX ((uint16_t)0x0040) /!< EndPoint Data TOGGLE TX /
mbed_official	441:d2c15dda23c1	3039	#define USB_EPTX_STAT ((uint16_t)0x0030) /!< EndPoint TX STATus bit field /
mbed_official	441:d2c15dda23c1	3040	#define USB_EPADDR_FIELD ((uint16_t)0x000F) /!< EndPoint ADDRess FIELD /
mbed_official	441:d2c15dda23c1	3041
mbed_official	441:d2c15dda23c1	3042	/* EndPoint REGister MASK (no toggle fields) */
mbed_official	441:d2c15dda23c1	3043	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
mbed_official	441:d2c15dda23c1	3044	/!< EP_TYPE[1:0] EndPoint TYPE /
mbed_official	441:d2c15dda23c1	3045	#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /!< EndPoint TYPE Mask /
mbed_official	441:d2c15dda23c1	3046	#define USB_EP_BULK ((uint16_t)0x0000) /!< EndPoint BULK /
mbed_official	441:d2c15dda23c1	3047	#define USB_EP_CONTROL ((uint16_t)0x0200) /!< EndPoint CONTROL /
mbed_official	441:d2c15dda23c1	3048	#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /!< EndPoint ISOCHRONOUS /
mbed_official	441:d2c15dda23c1	3049	#define USB_EP_INTERRUPT ((uint16_t)0x0600) /!< EndPoint INTERRUPT /
mbed_official	441:d2c15dda23c1	3050	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official	441:d2c15dda23c1	3051
mbed_official	441:d2c15dda23c1	3052	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
mbed_official	441:d2c15dda23c1	3053	/!< STAT_TX[1:0] STATus for TX transfer /
mbed_official	441:d2c15dda23c1	3054	#define USB_EP_TX_DIS ((uint16_t)0x0000) /!< EndPoint TX DISabled /
mbed_official	441:d2c15dda23c1	3055	#define USB_EP_TX_STALL ((uint16_t)0x0010) /!< EndPoint TX STALLed /
mbed_official	441:d2c15dda23c1	3056	#define USB_EP_TX_NAK ((uint16_t)0x0020) /!< EndPoint TX NAKed /
mbed_official	441:d2c15dda23c1	3057	#define USB_EP_TX_VALID ((uint16_t)0x0030) /!< EndPoint TX VALID /
mbed_official	441:d2c15dda23c1	3058	#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /!< EndPoint TX Data TOGgle bit1 /
mbed_official	441:d2c15dda23c1	3059	#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /!< EndPoint TX Data TOGgle bit2 /
mbed_official	441:d2c15dda23c1	3060	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
mbed_official	441:d2c15dda23c1	3061	/!< STAT_RX[1:0] STATus for RX transfer /
mbed_official	441:d2c15dda23c1	3062	#define USB_EP_RX_DIS ((uint16_t)0x0000) /!< EndPoint RX DISabled /
mbed_official	441:d2c15dda23c1	3063	#define USB_EP_RX_STALL ((uint16_t)0x1000) /!< EndPoint RX STALLed /
mbed_official	441:d2c15dda23c1	3064	#define USB_EP_RX_NAK ((uint16_t)0x2000) /!< EndPoint RX NAKed /
mbed_official	441:d2c15dda23c1	3065	#define USB_EP_RX_VALID ((uint16_t)0x3000) /!< EndPoint RX VALID /
mbed_official	441:d2c15dda23c1	3066	#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /!< EndPoint RX Data TOGgle bit1 /
mbed_official	441:d2c15dda23c1	3067	#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /!< EndPoint RX Data TOGgle bit1 /
mbed_official	441:d2c15dda23c1	3068	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
mbed_official	441:d2c15dda23c1	3069
mbed_official	441:d2c15dda23c1	3070	/******************************************************************************/
mbed_official	441:d2c15dda23c1	3071	/* */
mbed_official	441:d2c15dda23c1	3072	/* Window WATCHDOG (WWDG) */
mbed_official	441:d2c15dda23c1	3073	/* */
mbed_official	441:d2c15dda23c1	3074	/******************************************************************************/
mbed_official	441:d2c15dda23c1	3075	/***************** Bit definition for WWDG_CR register ******************/
mbed_official	441:d2c15dda23c1	3076	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
mbed_official	441:d2c15dda23c1	3077	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	3078	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	3079	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	3080	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	3081	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
mbed_official	441:d2c15dda23c1	3082	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
mbed_official	441:d2c15dda23c1	3083	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
mbed_official	441:d2c15dda23c1	3084
mbed_official	441:d2c15dda23c1	3085	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
mbed_official	441:d2c15dda23c1	3086
mbed_official	441:d2c15dda23c1	3087	/***************** Bit definition for WWDG_CFR register *****************/
mbed_official	441:d2c15dda23c1	3088	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
mbed_official	441:d2c15dda23c1	3089	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	3090	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	3091	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
mbed_official	441:d2c15dda23c1	3092	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
mbed_official	441:d2c15dda23c1	3093	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
mbed_official	441:d2c15dda23c1	3094	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
mbed_official	441:d2c15dda23c1	3095	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
mbed_official	441:d2c15dda23c1	3096
mbed_official	441:d2c15dda23c1	3097	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
mbed_official	441:d2c15dda23c1	3098	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
mbed_official	441:d2c15dda23c1	3099	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
mbed_official	441:d2c15dda23c1	3100
mbed_official	441:d2c15dda23c1	3101	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
mbed_official	441:d2c15dda23c1	3102
mbed_official	441:d2c15dda23c1	3103	/***************** Bit definition for WWDG_SR register ******************/
mbed_official	441:d2c15dda23c1	3104	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
mbed_official	441:d2c15dda23c1	3105
mbed_official	441:d2c15dda23c1	3106	/**
mbed_official	441:d2c15dda23c1	3107	* @}
mbed_official	441:d2c15dda23c1	3108	*/
mbed_official	441:d2c15dda23c1	3109
mbed_official	441:d2c15dda23c1	3110	/**
mbed_official	441:d2c15dda23c1	3111	* @}
mbed_official	441:d2c15dda23c1	3112	*/
mbed_official	441:d2c15dda23c1	3113
mbed_official	441:d2c15dda23c1	3114
mbed_official	441:d2c15dda23c1	3115	/** @addtogroup Exported_macro
mbed_official	441:d2c15dda23c1	3116	* @{
mbed_official	441:d2c15dda23c1	3117	*/
mbed_official	441:d2c15dda23c1	3118
mbed_official	441:d2c15dda23c1	3119	/**************************** ADC Instances *******************************/
mbed_official	441:d2c15dda23c1	3120	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official	441:d2c15dda23c1	3121
mbed_official	441:d2c15dda23c1	3122	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
mbed_official	441:d2c15dda23c1	3123
mbed_official	441:d2c15dda23c1	3124	/**************************** CRC Instances *******************************/
mbed_official	441:d2c15dda23c1	3125	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official	441:d2c15dda23c1	3126
mbed_official	441:d2c15dda23c1	3127	/***************************** DMA Instances ****************************/
mbed_official	441:d2c15dda23c1	3128	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
mbed_official	441:d2c15dda23c1	3129	((INSTANCE) == DMA1_Channel2) \|\| \
mbed_official	441:d2c15dda23c1	3130	((INSTANCE) == DMA1_Channel3) \|\| \
mbed_official	441:d2c15dda23c1	3131	((INSTANCE) == DMA1_Channel4) \|\| \
mbed_official	441:d2c15dda23c1	3132	((INSTANCE) == DMA1_Channel5))
mbed_official	441:d2c15dda23c1	3133
mbed_official	441:d2c15dda23c1	3134	/**************************** GPIO Instances ******************************/
mbed_official	441:d2c15dda23c1	3135	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	441:d2c15dda23c1	3136	((INSTANCE) == GPIOB) \|\| \
mbed_official	441:d2c15dda23c1	3137	((INSTANCE) == GPIOC) \|\| \
mbed_official	441:d2c15dda23c1	3138	((INSTANCE) == GPIOD) \|\| \
mbed_official	441:d2c15dda23c1	3139	((INSTANCE) == GPIOF))
mbed_official	441:d2c15dda23c1	3140
mbed_official	441:d2c15dda23c1	3141	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	441:d2c15dda23c1	3142	((INSTANCE) == GPIOB) \|\| \
mbed_official	441:d2c15dda23c1	3143	((INSTANCE) == GPIOC) \|\| \
mbed_official	441:d2c15dda23c1	3144	((INSTANCE) == GPIOD) \|\| \
mbed_official	441:d2c15dda23c1	3145	((INSTANCE) == GPIOF))
mbed_official	441:d2c15dda23c1	3146
mbed_official	441:d2c15dda23c1	3147	/**************************** GPIO Lock Instances **************************/
mbed_official	441:d2c15dda23c1	3148	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	441:d2c15dda23c1	3149	((INSTANCE) == GPIOB))
mbed_official	441:d2c15dda23c1	3150
mbed_official	441:d2c15dda23c1	3151	/**************************** I2C Instances *******************************/
mbed_official	441:d2c15dda23c1	3152	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
mbed_official	441:d2c15dda23c1	3153	((INSTANCE) == I2C2))
mbed_official	441:d2c15dda23c1	3154
mbed_official	630:825f75ca301e	3155
mbed_official	441:d2c15dda23c1	3156	/**************************** IWDG Instances ******************************/
mbed_official	441:d2c15dda23c1	3157	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official	441:d2c15dda23c1	3158
mbed_official	441:d2c15dda23c1	3159	/**************************** RTC Instances *******************************/
mbed_official	441:d2c15dda23c1	3160	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official	441:d2c15dda23c1	3161
mbed_official	441:d2c15dda23c1	3162	/**************************** SMBUS Instances *******************************/
mbed_official	441:d2c15dda23c1	3163	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official	441:d2c15dda23c1	3164
mbed_official	441:d2c15dda23c1	3165	/**************************** SPI Instances *******************************/
mbed_official	441:d2c15dda23c1	3166	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
mbed_official	441:d2c15dda23c1	3167	((INSTANCE) == SPI2))
mbed_official	441:d2c15dda23c1	3168
mbed_official	441:d2c15dda23c1	3169	/**************************** TIM Instances *******************************/
mbed_official	441:d2c15dda23c1	3170	#define IS_TIM_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3171	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3172	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3173	((INSTANCE) == TIM6) \|\| \
mbed_official	441:d2c15dda23c1	3174	((INSTANCE) == TIM7) \|\| \
mbed_official	441:d2c15dda23c1	3175	((INSTANCE) == TIM14) \|\| \
mbed_official	441:d2c15dda23c1	3176	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3177	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3178	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3179
mbed_official	441:d2c15dda23c1	3180	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3181	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3182	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3183	((INSTANCE) == TIM14) \|\| \
mbed_official	441:d2c15dda23c1	3184	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3185	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3186	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3187
mbed_official	441:d2c15dda23c1	3188	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3189	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3190	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3191	((INSTANCE) == TIM15))
mbed_official	441:d2c15dda23c1	3192
mbed_official	441:d2c15dda23c1	3193	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3194	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3195	((INSTANCE) == TIM3))
mbed_official	441:d2c15dda23c1	3196
mbed_official	441:d2c15dda23c1	3197	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3198	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3199	((INSTANCE) == TIM3))
mbed_official	441:d2c15dda23c1	3200
mbed_official	441:d2c15dda23c1	3201	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3202	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3203	((INSTANCE) == TIM3))
mbed_official	441:d2c15dda23c1	3204
mbed_official	441:d2c15dda23c1	3205	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3206	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3207	((INSTANCE) == TIM3))
mbed_official	441:d2c15dda23c1	3208
mbed_official	441:d2c15dda23c1	3209	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3210	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3211	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3212	((INSTANCE) == TIM15))
mbed_official	441:d2c15dda23c1	3213
mbed_official	441:d2c15dda23c1	3214	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3215	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3216	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3217	((INSTANCE) == TIM15))
mbed_official	441:d2c15dda23c1	3218
mbed_official	441:d2c15dda23c1	3219	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3220	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3221	((INSTANCE) == TIM3))
mbed_official	441:d2c15dda23c1	3222
mbed_official	441:d2c15dda23c1	3223	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3224	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3225	((INSTANCE) == TIM3))
mbed_official	441:d2c15dda23c1	3226
mbed_official	441:d2c15dda23c1	3227	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3228	(((INSTANCE) == TIM1))
mbed_official	441:d2c15dda23c1	3229
mbed_official	441:d2c15dda23c1	3230	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3231	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3232	((INSTANCE) == TIM3))
mbed_official	441:d2c15dda23c1	3233
mbed_official	441:d2c15dda23c1	3234	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3235	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3236	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3237	((INSTANCE) == TIM6) \|\| \
mbed_official	441:d2c15dda23c1	3238	((INSTANCE) == TIM7) \|\| \
mbed_official	441:d2c15dda23c1	3239	((INSTANCE) == TIM15))
mbed_official	441:d2c15dda23c1	3240
mbed_official	441:d2c15dda23c1	3241	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3242	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3243	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3244	((INSTANCE) == TIM15))
mbed_official	441:d2c15dda23c1	3245
mbed_official	441:d2c15dda23c1	3246	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(0)
mbed_official	441:d2c15dda23c1	3247
mbed_official	441:d2c15dda23c1	3248	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3249	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3250	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3251	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3252	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3253	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3254
mbed_official	441:d2c15dda23c1	3255	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3256	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3257	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3258	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3259	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3260
mbed_official	441:d2c15dda23c1	3261	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official	441:d2c15dda23c1	3262	((((INSTANCE) == TIM1) && \
mbed_official	441:d2c15dda23c1	3263	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	441:d2c15dda23c1	3264	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	441:d2c15dda23c1	3265	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	441:d2c15dda23c1	3266	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	441:d2c15dda23c1	3267	\|\| \
mbed_official	441:d2c15dda23c1	3268	(((INSTANCE) == TIM3) && \
mbed_official	441:d2c15dda23c1	3269	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	441:d2c15dda23c1	3270	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	441:d2c15dda23c1	3271	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	441:d2c15dda23c1	3272	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	441:d2c15dda23c1	3273	\|\| \
mbed_official	441:d2c15dda23c1	3274	(((INSTANCE) == TIM14) && \
mbed_official	441:d2c15dda23c1	3275	(((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official	441:d2c15dda23c1	3276	\|\| \
mbed_official	441:d2c15dda23c1	3277	(((INSTANCE) == TIM15) && \
mbed_official	441:d2c15dda23c1	3278	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	441:d2c15dda23c1	3279	((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official	441:d2c15dda23c1	3280	\|\| \
mbed_official	441:d2c15dda23c1	3281	(((INSTANCE) == TIM16) && \
mbed_official	441:d2c15dda23c1	3282	(((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official	441:d2c15dda23c1	3283	\|\| \
mbed_official	441:d2c15dda23c1	3284	(((INSTANCE) == TIM17) && \
mbed_official	441:d2c15dda23c1	3285	(((CHANNEL) == TIM_CHANNEL_1))))
mbed_official	441:d2c15dda23c1	3286
mbed_official	441:d2c15dda23c1	3287	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official	441:d2c15dda23c1	3288	((((INSTANCE) == TIM1) && \
mbed_official	441:d2c15dda23c1	3289	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	441:d2c15dda23c1	3290	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	441:d2c15dda23c1	3291	((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official	441:d2c15dda23c1	3292	\|\| \
mbed_official	441:d2c15dda23c1	3293	(((INSTANCE) == TIM15) && \
mbed_official	441:d2c15dda23c1	3294	((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official	441:d2c15dda23c1	3295	\|\| \
mbed_official	441:d2c15dda23c1	3296	(((INSTANCE) == TIM16) && \
mbed_official	441:d2c15dda23c1	3297	((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official	441:d2c15dda23c1	3298	\|\| \
mbed_official	441:d2c15dda23c1	3299	(((INSTANCE) == TIM17) && \
mbed_official	441:d2c15dda23c1	3300	((CHANNEL) == TIM_CHANNEL_1)))
mbed_official	441:d2c15dda23c1	3301
mbed_official	441:d2c15dda23c1	3302	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3303	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3304	((INSTANCE) == TIM3))
mbed_official	441:d2c15dda23c1	3305
mbed_official	441:d2c15dda23c1	3306	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3307	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3308	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3309	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3310	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3311
mbed_official	441:d2c15dda23c1	3312	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3313	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3314	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3315	((INSTANCE) == TIM14) \|\| \
mbed_official	441:d2c15dda23c1	3316	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3317	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3318	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3319
mbed_official	441:d2c15dda23c1	3320	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3321	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3322	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3323	((INSTANCE) == TIM6) \|\| \
mbed_official	441:d2c15dda23c1	3324	((INSTANCE) == TIM7) \|\| \
mbed_official	441:d2c15dda23c1	3325	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3326	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3327	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3328
mbed_official	441:d2c15dda23c1	3329	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3330	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3331	((INSTANCE) == TIM3) \|\| \
mbed_official	441:d2c15dda23c1	3332	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3333	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3334	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3335
mbed_official	441:d2c15dda23c1	3336	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3337	(((INSTANCE) == TIM1) \|\| \
mbed_official	441:d2c15dda23c1	3338	((INSTANCE) == TIM15) \|\| \
mbed_official	441:d2c15dda23c1	3339	((INSTANCE) == TIM16) \|\| \
mbed_official	441:d2c15dda23c1	3340	((INSTANCE) == TIM17))
mbed_official	441:d2c15dda23c1	3341
mbed_official	441:d2c15dda23c1	3342	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official	441:d2c15dda23c1	3343	((INSTANCE) == TIM14)
mbed_official	441:d2c15dda23c1	3344
mbed_official	441:d2c15dda23c1	3345	/****************** USART Instances : Synchronous mode ********************/
mbed_official	441:d2c15dda23c1	3346	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	441:d2c15dda23c1	3347	((INSTANCE) == USART2) \|\| \
mbed_official	441:d2c15dda23c1	3348	((INSTANCE) == USART3) \|\| \
mbed_official	441:d2c15dda23c1	3349	((INSTANCE) == USART4))
mbed_official	441:d2c15dda23c1	3350
mbed_official	441:d2c15dda23c1	3351	/****************** USART Instances : auto Baud rate detection ************/
mbed_official	441:d2c15dda23c1	3352	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	441:d2c15dda23c1	3353	((INSTANCE) == USART2))
mbed_official	441:d2c15dda23c1	3354
mbed_official	441:d2c15dda23c1	3355	/****************** UART Instances : Asynchronous mode ********************/
mbed_official	441:d2c15dda23c1	3356	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	441:d2c15dda23c1	3357	((INSTANCE) == USART2) \|\| \
mbed_official	441:d2c15dda23c1	3358	((INSTANCE) == USART3) \|\| \
mbed_official	441:d2c15dda23c1	3359	((INSTANCE) == USART4))
mbed_official	441:d2c15dda23c1	3360
mbed_official	441:d2c15dda23c1	3361	/****************** UART Instances : Half-Duplex mode ********************/
mbed_official	441:d2c15dda23c1	3362	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	441:d2c15dda23c1	3363	((INSTANCE) == USART2) \|\| \
mbed_official	441:d2c15dda23c1	3364	((INSTANCE) == USART3) \|\| \
mbed_official	441:d2c15dda23c1	3365	((INSTANCE) == USART4))
mbed_official	441:d2c15dda23c1	3366
mbed_official	441:d2c15dda23c1	3367	/**************** UART Instances : Hardware Flow control ******************/
mbed_official	441:d2c15dda23c1	3368	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	441:d2c15dda23c1	3369	((INSTANCE) == USART2) \|\| \
mbed_official	441:d2c15dda23c1	3370	((INSTANCE) == USART3) \|\| \
mbed_official	441:d2c15dda23c1	3371	((INSTANCE) == USART4))
mbed_official	441:d2c15dda23c1	3372
mbed_official	441:d2c15dda23c1	3373	/**************** UART Instances : Auto Baud Rate detection ******************/
mbed_official	441:d2c15dda23c1	3374	#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	441:d2c15dda23c1	3375	((INSTANCE) == USART2))
mbed_official	441:d2c15dda23c1	3376
mbed_official	630:825f75ca301e	3377	/**************** UART Instances : Driver enable detection ******************/
mbed_official	630:825f75ca301e	3378	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	630:825f75ca301e	3379	((INSTANCE) == USART2) \|\| \
mbed_official	630:825f75ca301e	3380	((INSTANCE) == USART3) \|\| \
mbed_official	630:825f75ca301e	3381	((INSTANCE) == USART4))
mbed_official	441:d2c15dda23c1	3382
mbed_official	441:d2c15dda23c1	3383	/**************************** USB Instances ******************************/
mbed_official	441:d2c15dda23c1	3384	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official	441:d2c15dda23c1	3385
mbed_official	441:d2c15dda23c1	3386	/**************************** WWDG Instances ******************************/
mbed_official	441:d2c15dda23c1	3387	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official	441:d2c15dda23c1	3388
mbed_official	441:d2c15dda23c1	3389	/**
mbed_official	441:d2c15dda23c1	3390	* @}
mbed_official	441:d2c15dda23c1	3391	*/
mbed_official	441:d2c15dda23c1	3392
mbed_official	441:d2c15dda23c1	3393
mbed_official	441:d2c15dda23c1	3394	/******************************************************************************/
mbed_official	441:d2c15dda23c1	3395	/* For a painless codes migration between the STM32F0xx device product */
mbed_official	441:d2c15dda23c1	3396	/* lines, the aliases defined below are put in place to overcome the */
mbed_official	441:d2c15dda23c1	3397	/* differences in the interrupt handlers and IRQn definitions. */
mbed_official	441:d2c15dda23c1	3398	/* No need to update developed interrupt code when moving across */
mbed_official	441:d2c15dda23c1	3399	/* product lines within the same STM32F0 Family */
mbed_official	441:d2c15dda23c1	3400	/******************************************************************************/
mbed_official	441:d2c15dda23c1	3401
mbed_official	441:d2c15dda23c1	3402	/* Aliases for __IRQn */
mbed_official	441:d2c15dda23c1	3403	#define RCC_CRS_IRQn RCC_IRQn
mbed_official	441:d2c15dda23c1	3404	#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
mbed_official	441:d2c15dda23c1	3405	#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
mbed_official	441:d2c15dda23c1	3406	#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
mbed_official	441:d2c15dda23c1	3407	#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
mbed_official	441:d2c15dda23c1	3408	#define ADC1_COMP_IRQn ADC1_IRQn
mbed_official	441:d2c15dda23c1	3409	#define TIM6_DAC_IRQn TIM6_IRQn
mbed_official	441:d2c15dda23c1	3410	#define USART3_8_IRQn USART3_4_IRQn
mbed_official	441:d2c15dda23c1	3411	#define USART3_6_IRQn USART3_4_IRQn
mbed_official	441:d2c15dda23c1	3412
mbed_official	441:d2c15dda23c1	3413	/* Aliases for __IRQHandler */
mbed_official	441:d2c15dda23c1	3414	#define RCC_CRS_IRQHandler RCC_IRQHandler
mbed_official	441:d2c15dda23c1	3415	#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
mbed_official	441:d2c15dda23c1	3416	#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
mbed_official	441:d2c15dda23c1	3417	#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
mbed_official	441:d2c15dda23c1	3418	#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
mbed_official	441:d2c15dda23c1	3419	#define ADC1_COMP_IRQHandler ADC1_IRQHandler
mbed_official	441:d2c15dda23c1	3420	#define TIM6_DAC_IRQHandler TIM6_IRQHandler
mbed_official	441:d2c15dda23c1	3421	#define USART3_8_IRQHandler USART3_4_IRQHandler
mbed_official	441:d2c15dda23c1	3422	#define USART3_6_IRQHandler USART3_4_IRQHandler
mbed_official	441:d2c15dda23c1	3423
mbed_official	441:d2c15dda23c1	3424	#ifdef __cplusplus
mbed_official	441:d2c15dda23c1	3425	}
mbed_official	441:d2c15dda23c1	3426	#endif /* __cplusplus */
mbed_official	441:d2c15dda23c1	3427
mbed_official	441:d2c15dda23c1	3428	#endif /* __STM32F070xB_H */
mbed_official	441:d2c15dda23c1	3429
mbed_official	441:d2c15dda23c1	3430	/**
mbed_official	441:d2c15dda23c1	3431	* @}
mbed_official	441:d2c15dda23c1	3432	*/
mbed_official	441:d2c15dda23c1	3433
mbed_official	441:d2c15dda23c1	3434	/**
mbed_official	441:d2c15dda23c1	3435	* @}
mbed_official	441:d2c15dda23c1	3436	*/
mbed_official	441:d2c15dda23c1	3437
mbed_official	441:d2c15dda23c1	3438	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	02 Nov 2015
Imports:	14
Forks:	0
Commits:	637
Dependents:	2
Dependencies:	0
Followers:	5

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h@630:825f75ca301e, 2015-09-28 (annotated)

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