CQ Publishing / Mbed 2 deprecated tg_201410s8_AD7714

Transistor Gijutsu, October 2014, Special Features Chapter 8，Software of the thermistor thermometer of 0.001 ° resolution， トランジスタ技術2014年10月号　特集第8章のソフトウェア　0.001℃分解能で気配もキャッチ「超敏感肌温度計」

Dependencies:   USBDevice mbed

Information

tg_201410s8_AD7714 トランジスタ技術 2014年 10月号 第8章のソフトウェア

Program for Section 8 in October. 2014 issue of the Transistor Gijutsu
(Japanese electronics magazine)

概要

このプログラムは、サーミスタの抵抗値変化をAD7714(24bitADC)で測定し、抵抗値を温度値に変換することで、0.001℃程度の分解能で温度変化を測定します。

ファイル

このソフトウエアは、次のファイルから構成されています。

  • AD7714.cpp - AD7714の内部レジスタを設定
  • Thermistor.cpp - サーミスタの抵抗値から温度値に変換
  • ExpAvr.cpp - 指数平均によるソフトウエアＬＰＦ
  • main.cpp - main()関数

詳細については、10月号の記事および上記ファイル中のコメントを参照してください。

USBDevice/USBDevice/USBRegs_STM32.h@0:de885a6da962, 2014-08-29 (annotated)

Committer:
Dance
Date:
Fri Aug 29 08:38:36 2014 +0000
Revision:
0:de885a6da962
Transistor Gijutsu, October 2014, Special Features Chapter 8; ????????2014?10??????8????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Dance 0:de885a6da962 1 /**
Dance 0:de885a6da962 2 ******************************************************************************
Dance 0:de885a6da962 3 * @file usb_regs.h
Dance 0:de885a6da962 4 * @author MCD Application Team
Dance 0:de885a6da962 5 * @version V2.1.0
Dance 0:de885a6da962 6 * @date 19-March-2012
Dance 0:de885a6da962 7 * @brief hardware registers
Dance 0:de885a6da962 8 ******************************************************************************
Dance 0:de885a6da962 9 * @attention
Dance 0:de885a6da962 10 *
Dance 0:de885a6da962 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
Dance 0:de885a6da962 12 *
Dance 0:de885a6da962 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
Dance 0:de885a6da962 14 * You may not use this file except in compliance with the License.
Dance 0:de885a6da962 15 * You may obtain a copy of the License at:
Dance 0:de885a6da962 16 *
Dance 0:de885a6da962 17 * http://www.st.com/software_license_agreement_liberty_v2
Dance 0:de885a6da962 18 *
Dance 0:de885a6da962 19 * Unless required by applicable law or agreed to in writing, software
Dance 0:de885a6da962 20 * distributed under the License is distributed on an "AS IS" BASIS,
Dance 0:de885a6da962 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Dance 0:de885a6da962 22 * See the License for the specific language governing permissions and
Dance 0:de885a6da962 23 * limitations under the License.
Dance 0:de885a6da962 24 *
Dance 0:de885a6da962 25 ******************************************************************************
Dance 0:de885a6da962 26 */
Dance 0:de885a6da962 27
Dance 0:de885a6da962 28 #ifndef __USB_OTG_REGS_H__
Dance 0:de885a6da962 29 #define __USB_OTG_REGS_H__
Dance 0:de885a6da962 30
Dance 0:de885a6da962 31 typedef struct //000h
Dance 0:de885a6da962 32 {
Dance 0:de885a6da962 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
Dance 0:de885a6da962 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
Dance 0:de885a6da962 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
Dance 0:de885a6da962 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
Dance 0:de885a6da962 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
Dance 0:de885a6da962 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
Dance 0:de885a6da962 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
Dance 0:de885a6da962 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
Dance 0:de885a6da962 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
Dance 0:de885a6da962 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
Dance 0:de885a6da962 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
Dance 0:de885a6da962 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
Dance 0:de885a6da962 45 uint32_t Reserved30[2]; /* Reserved 030h*/
Dance 0:de885a6da962 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
Dance 0:de885a6da962 47 __IO uint32_t CID; /* User ID Register 03Ch*/
Dance 0:de885a6da962 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
Dance 0:de885a6da962 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
Dance 0:de885a6da962 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
Dance 0:de885a6da962 51 }
Dance 0:de885a6da962 52 USB_OTG_GREGS;
Dance 0:de885a6da962 53
Dance 0:de885a6da962 54 typedef struct // 800h
Dance 0:de885a6da962 55 {
Dance 0:de885a6da962 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
Dance 0:de885a6da962 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
Dance 0:de885a6da962 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
Dance 0:de885a6da962 59 uint32_t Reserved0C; /* Reserved 80Ch*/
Dance 0:de885a6da962 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
Dance 0:de885a6da962 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
Dance 0:de885a6da962 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
Dance 0:de885a6da962 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
Dance 0:de885a6da962 64 uint32_t Reserved20; /* Reserved 820h*/
Dance 0:de885a6da962 65 uint32_t Reserved9; /* Reserved 824h*/
Dance 0:de885a6da962 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
Dance 0:de885a6da962 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
Dance 0:de885a6da962 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
Dance 0:de885a6da962 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
Dance 0:de885a6da962 70 }
Dance 0:de885a6da962 71 USB_OTG_DREGS;
Dance 0:de885a6da962 72
Dance 0:de885a6da962 73 typedef struct
Dance 0:de885a6da962 74 {
Dance 0:de885a6da962 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
Dance 0:de885a6da962 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
Dance 0:de885a6da962 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
Dance 0:de885a6da962 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
Dance 0:de885a6da962 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
Dance 0:de885a6da962 80 uint32_t Reserved14;
Dance 0:de885a6da962 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
Dance 0:de885a6da962 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
Dance 0:de885a6da962 83 }
Dance 0:de885a6da962 84 USB_OTG_INEPREGS;
Dance 0:de885a6da962 85
Dance 0:de885a6da962 86 typedef struct
Dance 0:de885a6da962 87 {
Dance 0:de885a6da962 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
Dance 0:de885a6da962 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
Dance 0:de885a6da962 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
Dance 0:de885a6da962 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
Dance 0:de885a6da962 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
Dance 0:de885a6da962 93 uint32_t Reserved14[3];
Dance 0:de885a6da962 94 }
Dance 0:de885a6da962 95 USB_OTG_OUTEPREGS;
Dance 0:de885a6da962 96
Dance 0:de885a6da962 97 typedef struct
Dance 0:de885a6da962 98 {
Dance 0:de885a6da962 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
Dance 0:de885a6da962 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
Dance 0:de885a6da962 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
Dance 0:de885a6da962 102 uint32_t Reserved40C; /* Reserved 40Ch*/
Dance 0:de885a6da962 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
Dance 0:de885a6da962 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
Dance 0:de885a6da962 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
Dance 0:de885a6da962 106 }
Dance 0:de885a6da962 107 USB_OTG_HREGS;
Dance 0:de885a6da962 108
Dance 0:de885a6da962 109 typedef struct
Dance 0:de885a6da962 110 {
Dance 0:de885a6da962 111 __IO uint32_t HCCHAR;
Dance 0:de885a6da962 112 __IO uint32_t HCSPLT;
Dance 0:de885a6da962 113 __IO uint32_t HCINT;
Dance 0:de885a6da962 114 __IO uint32_t HCINTMSK;
Dance 0:de885a6da962 115 __IO uint32_t HCTSIZ;
Dance 0:de885a6da962 116 uint32_t Reserved[3];
Dance 0:de885a6da962 117 }
Dance 0:de885a6da962 118 USB_OTG_HC_REGS;
Dance 0:de885a6da962 119
Dance 0:de885a6da962 120 typedef struct
Dance 0:de885a6da962 121 {
Dance 0:de885a6da962 122 USB_OTG_GREGS GREGS;
Dance 0:de885a6da962 123 uint32_t RESERVED0[188];
Dance 0:de885a6da962 124 USB_OTG_HREGS HREGS;
Dance 0:de885a6da962 125 uint32_t RESERVED1[9];
Dance 0:de885a6da962 126 __IO uint32_t HPRT;
Dance 0:de885a6da962 127 uint32_t RESERVED2[47];
Dance 0:de885a6da962 128 USB_OTG_HC_REGS HC_REGS[8];
Dance 0:de885a6da962 129 uint32_t RESERVED3[128];
Dance 0:de885a6da962 130 USB_OTG_DREGS DREGS;
Dance 0:de885a6da962 131 uint32_t RESERVED4[50];
Dance 0:de885a6da962 132 USB_OTG_INEPREGS INEP_REGS[4];
Dance 0:de885a6da962 133 uint32_t RESERVED5[96];
Dance 0:de885a6da962 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
Dance 0:de885a6da962 135 uint32_t RESERVED6[160];
Dance 0:de885a6da962 136 __IO uint32_t PCGCCTL;
Dance 0:de885a6da962 137 uint32_t RESERVED7[127];
Dance 0:de885a6da962 138 __IO uint32_t FIFO[4][1024];
Dance 0:de885a6da962 139 }
Dance 0:de885a6da962 140 USB_OTG_CORE_REGS;
Dance 0:de885a6da962 141
Dance 0:de885a6da962 142
Dance 0:de885a6da962 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
Dance 0:de885a6da962 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
Dance 0:de885a6da962 145
Dance 0:de885a6da962 146 #endif //__USB_OTG_REGS_H__
Dance 0:de885a6da962 147
Dance 0:de885a6da962 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Dance 0:de885a6da962 149