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lpc17xx_clkpwr.c@32:1e1e7730b6c8, 2014-06-16 (annotated)

Committer:
jvanhook
Date:
Mon Jun 16 15:36:29 2014 +0000
Revision:
32:1e1e7730b6c8
dfsdfgsdf

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jvanhook 32:1e1e7730b6c8 1 /***********************************************************************//**
jvanhook 32:1e1e7730b6c8 2 * @file lpc17xx_clkpwr.c
jvanhook 32:1e1e7730b6c8 3 * @brief Contains all functions support for Clock and Power Control
jvanhook 32:1e1e7730b6c8 4 * firmware library on LPC17xx
jvanhook 32:1e1e7730b6c8 5 * @version 3.0
jvanhook 32:1e1e7730b6c8 6 * @date 18. June. 2010
jvanhook 32:1e1e7730b6c8 7 * @author NXP MCU SW Application Team
jvanhook 32:1e1e7730b6c8 8 **************************************************************************
jvanhook 32:1e1e7730b6c8 9 * Software that is described herein is for illustrative purposes only
jvanhook 32:1e1e7730b6c8 10 * which provides customers with programming information regarding the
jvanhook 32:1e1e7730b6c8 11 * products. This software is supplied "AS IS" without any warranties.
jvanhook 32:1e1e7730b6c8 12 * NXP Semiconductors assumes no responsibility or liability for the
jvanhook 32:1e1e7730b6c8 13 * use of the software, conveys no license or title under any patent,
jvanhook 32:1e1e7730b6c8 14 * copyright, or mask work right to the product. NXP Semiconductors
jvanhook 32:1e1e7730b6c8 15 * reserves the right to make changes in the software without
jvanhook 32:1e1e7730b6c8 16 * notification. NXP Semiconductors also make no representation or
jvanhook 32:1e1e7730b6c8 17 * warranty that such application will be suitable for the specified
jvanhook 32:1e1e7730b6c8 18 * use without further testing or modification.
jvanhook 32:1e1e7730b6c8 19 **********************************************************************/
jvanhook 32:1e1e7730b6c8 20
jvanhook 32:1e1e7730b6c8 21 /* Peripheral group ----------------------------------------------------------- */
jvanhook 32:1e1e7730b6c8 22 /** @addtogroup CLKPWR
jvanhook 32:1e1e7730b6c8 23 * @{
jvanhook 32:1e1e7730b6c8 24 */
jvanhook 32:1e1e7730b6c8 25
jvanhook 32:1e1e7730b6c8 26 /* Includes ------------------------------------------------------------------- */
jvanhook 32:1e1e7730b6c8 27 #include "lpc17xx_clkpwr.h"
jvanhook 32:1e1e7730b6c8 28
jvanhook 32:1e1e7730b6c8 29
jvanhook 32:1e1e7730b6c8 30 /* Public Functions ----------------------------------------------------------- */
jvanhook 32:1e1e7730b6c8 31 /** @addtogroup CLKPWR_Public_Functions
jvanhook 32:1e1e7730b6c8 32 * @{
jvanhook 32:1e1e7730b6c8 33 */
jvanhook 32:1e1e7730b6c8 34
jvanhook 32:1e1e7730b6c8 35 /*********************************************************************//**
jvanhook 32:1e1e7730b6c8 36 * @brief Set value of each Peripheral Clock Selection
jvanhook 32:1e1e7730b6c8 37 * @param[in] ClkType Peripheral Clock Selection of each type,
jvanhook 32:1e1e7730b6c8 38 * should be one of the following:
jvanhook 32:1e1e7730b6c8 39 * - CLKPWR_PCLKSEL_WDT : WDT
jvanhook 32:1e1e7730b6c8 40 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
jvanhook 32:1e1e7730b6c8 41 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
jvanhook 32:1e1e7730b6c8 42 - CLKPWR_PCLKSEL_UART0 : UART 0
jvanhook 32:1e1e7730b6c8 43 - CLKPWR_PCLKSEL_UART1 : UART 1
jvanhook 32:1e1e7730b6c8 44 - CLKPWR_PCLKSEL_PWM1 : PWM 1
jvanhook 32:1e1e7730b6c8 45 - CLKPWR_PCLKSEL_I2C0 : I2C 0
jvanhook 32:1e1e7730b6c8 46 - CLKPWR_PCLKSEL_SPI : SPI
jvanhook 32:1e1e7730b6c8 47 - CLKPWR_PCLKSEL_SSP1 : SSP 1
jvanhook 32:1e1e7730b6c8 48 - CLKPWR_PCLKSEL_DAC : DAC
jvanhook 32:1e1e7730b6c8 49 - CLKPWR_PCLKSEL_ADC : ADC
jvanhook 32:1e1e7730b6c8 50 - CLKPWR_PCLKSEL_CAN1 : CAN 1
jvanhook 32:1e1e7730b6c8 51 - CLKPWR_PCLKSEL_CAN2 : CAN 2
jvanhook 32:1e1e7730b6c8 52 - CLKPWR_PCLKSEL_ACF : ACF
jvanhook 32:1e1e7730b6c8 53 - CLKPWR_PCLKSEL_QEI : QEI
jvanhook 32:1e1e7730b6c8 54 - CLKPWR_PCLKSEL_PCB : PCB
jvanhook 32:1e1e7730b6c8 55 - CLKPWR_PCLKSEL_I2C1 : I2C 1
jvanhook 32:1e1e7730b6c8 56 - CLKPWR_PCLKSEL_SSP0 : SSP 0
jvanhook 32:1e1e7730b6c8 57 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
jvanhook 32:1e1e7730b6c8 58 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
jvanhook 32:1e1e7730b6c8 59 - CLKPWR_PCLKSEL_UART2 : UART 2
jvanhook 32:1e1e7730b6c8 60 - CLKPWR_PCLKSEL_UART3 : UART 3
jvanhook 32:1e1e7730b6c8 61 - CLKPWR_PCLKSEL_I2C2 : I2C 2
jvanhook 32:1e1e7730b6c8 62 - CLKPWR_PCLKSEL_I2S : I2S
jvanhook 32:1e1e7730b6c8 63 - CLKPWR_PCLKSEL_RIT : RIT
jvanhook 32:1e1e7730b6c8 64 - CLKPWR_PCLKSEL_SYSCON : SYSCON
jvanhook 32:1e1e7730b6c8 65 - CLKPWR_PCLKSEL_MC : MC
jvanhook 32:1e1e7730b6c8 66
jvanhook 32:1e1e7730b6c8 67 * @param[in] DivVal Value of divider, should be:
jvanhook 32:1e1e7730b6c8 68 * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
jvanhook 32:1e1e7730b6c8 69 * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
jvanhook 32:1e1e7730b6c8 70 * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
jvanhook 32:1e1e7730b6c8 71 *
jvanhook 32:1e1e7730b6c8 72 * @return none
jvanhook 32:1e1e7730b6c8 73 **********************************************************************/
jvanhook 32:1e1e7730b6c8 74 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
jvanhook 32:1e1e7730b6c8 75 {
jvanhook 32:1e1e7730b6c8 76 uint32_t bitpos;
jvanhook 32:1e1e7730b6c8 77
jvanhook 32:1e1e7730b6c8 78 bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
jvanhook 32:1e1e7730b6c8 79
jvanhook 32:1e1e7730b6c8 80 /* PCLKSEL0 selected */
jvanhook 32:1e1e7730b6c8 81 if (ClkType < 32)
jvanhook 32:1e1e7730b6c8 82 {
jvanhook 32:1e1e7730b6c8 83 /* Clear two bit at bit position */
jvanhook 32:1e1e7730b6c8 84 LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
jvanhook 32:1e1e7730b6c8 85
jvanhook 32:1e1e7730b6c8 86 /* Set two selected bit */
jvanhook 32:1e1e7730b6c8 87 LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
jvanhook 32:1e1e7730b6c8 88 }
jvanhook 32:1e1e7730b6c8 89 /* PCLKSEL1 selected */
jvanhook 32:1e1e7730b6c8 90 else
jvanhook 32:1e1e7730b6c8 91 {
jvanhook 32:1e1e7730b6c8 92 /* Clear two bit at bit position */
jvanhook 32:1e1e7730b6c8 93 LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
jvanhook 32:1e1e7730b6c8 94
jvanhook 32:1e1e7730b6c8 95 /* Set two selected bit */
jvanhook 32:1e1e7730b6c8 96 LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
jvanhook 32:1e1e7730b6c8 97 }
jvanhook 32:1e1e7730b6c8 98 }
jvanhook 32:1e1e7730b6c8 99
jvanhook 32:1e1e7730b6c8 100
jvanhook 32:1e1e7730b6c8 101 /*********************************************************************//**
jvanhook 32:1e1e7730b6c8 102 * @brief Get current value of each Peripheral Clock Selection
jvanhook 32:1e1e7730b6c8 103 * @param[in] ClkType Peripheral Clock Selection of each type,
jvanhook 32:1e1e7730b6c8 104 * should be one of the following:
jvanhook 32:1e1e7730b6c8 105 * - CLKPWR_PCLKSEL_WDT : WDT
jvanhook 32:1e1e7730b6c8 106 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
jvanhook 32:1e1e7730b6c8 107 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
jvanhook 32:1e1e7730b6c8 108 - CLKPWR_PCLKSEL_UART0 : UART 0
jvanhook 32:1e1e7730b6c8 109 - CLKPWR_PCLKSEL_UART1 : UART 1
jvanhook 32:1e1e7730b6c8 110 - CLKPWR_PCLKSEL_PWM1 : PWM 1
jvanhook 32:1e1e7730b6c8 111 - CLKPWR_PCLKSEL_I2C0 : I2C 0
jvanhook 32:1e1e7730b6c8 112 - CLKPWR_PCLKSEL_SPI : SPI
jvanhook 32:1e1e7730b6c8 113 - CLKPWR_PCLKSEL_SSP1 : SSP 1
jvanhook 32:1e1e7730b6c8 114 - CLKPWR_PCLKSEL_DAC : DAC
jvanhook 32:1e1e7730b6c8 115 - CLKPWR_PCLKSEL_ADC : ADC
jvanhook 32:1e1e7730b6c8 116 - CLKPWR_PCLKSEL_CAN1 : CAN 1
jvanhook 32:1e1e7730b6c8 117 - CLKPWR_PCLKSEL_CAN2 : CAN 2
jvanhook 32:1e1e7730b6c8 118 - CLKPWR_PCLKSEL_ACF : ACF
jvanhook 32:1e1e7730b6c8 119 - CLKPWR_PCLKSEL_QEI : QEI
jvanhook 32:1e1e7730b6c8 120 - CLKPWR_PCLKSEL_PCB : PCB
jvanhook 32:1e1e7730b6c8 121 - CLKPWR_PCLKSEL_I2C1 : I2C 1
jvanhook 32:1e1e7730b6c8 122 - CLKPWR_PCLKSEL_SSP0 : SSP 0
jvanhook 32:1e1e7730b6c8 123 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
jvanhook 32:1e1e7730b6c8 124 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
jvanhook 32:1e1e7730b6c8 125 - CLKPWR_PCLKSEL_UART2 : UART 2
jvanhook 32:1e1e7730b6c8 126 - CLKPWR_PCLKSEL_UART3 : UART 3
jvanhook 32:1e1e7730b6c8 127 - CLKPWR_PCLKSEL_I2C2 : I2C 2
jvanhook 32:1e1e7730b6c8 128 - CLKPWR_PCLKSEL_I2S : I2S
jvanhook 32:1e1e7730b6c8 129 - CLKPWR_PCLKSEL_RIT : RIT
jvanhook 32:1e1e7730b6c8 130 - CLKPWR_PCLKSEL_SYSCON : SYSCON
jvanhook 32:1e1e7730b6c8 131 - CLKPWR_PCLKSEL_MC : MC
jvanhook 32:1e1e7730b6c8 132
jvanhook 32:1e1e7730b6c8 133 * @return Value of Selected Peripheral Clock Selection
jvanhook 32:1e1e7730b6c8 134 **********************************************************************/
jvanhook 32:1e1e7730b6c8 135 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
jvanhook 32:1e1e7730b6c8 136 {
jvanhook 32:1e1e7730b6c8 137 uint32_t bitpos, retval;
jvanhook 32:1e1e7730b6c8 138
jvanhook 32:1e1e7730b6c8 139 if (ClkType < 32)
jvanhook 32:1e1e7730b6c8 140 {
jvanhook 32:1e1e7730b6c8 141 bitpos = ClkType;
jvanhook 32:1e1e7730b6c8 142 retval = LPC_SC->PCLKSEL0;
jvanhook 32:1e1e7730b6c8 143 }
jvanhook 32:1e1e7730b6c8 144 else
jvanhook 32:1e1e7730b6c8 145 {
jvanhook 32:1e1e7730b6c8 146 bitpos = ClkType - 32;
jvanhook 32:1e1e7730b6c8 147 retval = LPC_SC->PCLKSEL1;
jvanhook 32:1e1e7730b6c8 148 }
jvanhook 32:1e1e7730b6c8 149
jvanhook 32:1e1e7730b6c8 150 retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
jvanhook 32:1e1e7730b6c8 151 return retval;
jvanhook 32:1e1e7730b6c8 152 }
jvanhook 32:1e1e7730b6c8 153
jvanhook 32:1e1e7730b6c8 154
jvanhook 32:1e1e7730b6c8 155
jvanhook 32:1e1e7730b6c8 156 /*********************************************************************//**
jvanhook 32:1e1e7730b6c8 157 * @brief Get current value of each Peripheral Clock
jvanhook 32:1e1e7730b6c8 158 * @param[in] ClkType Peripheral Clock Selection of each type,
jvanhook 32:1e1e7730b6c8 159 * should be one of the following:
jvanhook 32:1e1e7730b6c8 160 * - CLKPWR_PCLKSEL_WDT : WDT
jvanhook 32:1e1e7730b6c8 161 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
jvanhook 32:1e1e7730b6c8 162 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
jvanhook 32:1e1e7730b6c8 163 - CLKPWR_PCLKSEL_UART0 : UART 0
jvanhook 32:1e1e7730b6c8 164 - CLKPWR_PCLKSEL_UART1 : UART 1
jvanhook 32:1e1e7730b6c8 165 - CLKPWR_PCLKSEL_PWM1 : PWM 1
jvanhook 32:1e1e7730b6c8 166 - CLKPWR_PCLKSEL_I2C0 : I2C 0
jvanhook 32:1e1e7730b6c8 167 - CLKPWR_PCLKSEL_SPI : SPI
jvanhook 32:1e1e7730b6c8 168 - CLKPWR_PCLKSEL_SSP1 : SSP 1
jvanhook 32:1e1e7730b6c8 169 - CLKPWR_PCLKSEL_DAC : DAC
jvanhook 32:1e1e7730b6c8 170 - CLKPWR_PCLKSEL_ADC : ADC
jvanhook 32:1e1e7730b6c8 171 - CLKPWR_PCLKSEL_CAN1 : CAN 1
jvanhook 32:1e1e7730b6c8 172 - CLKPWR_PCLKSEL_CAN2 : CAN 2
jvanhook 32:1e1e7730b6c8 173 - CLKPWR_PCLKSEL_ACF : ACF
jvanhook 32:1e1e7730b6c8 174 - CLKPWR_PCLKSEL_QEI : QEI
jvanhook 32:1e1e7730b6c8 175 - CLKPWR_PCLKSEL_PCB : PCB
jvanhook 32:1e1e7730b6c8 176 - CLKPWR_PCLKSEL_I2C1 : I2C 1
jvanhook 32:1e1e7730b6c8 177 - CLKPWR_PCLKSEL_SSP0 : SSP 0
jvanhook 32:1e1e7730b6c8 178 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
jvanhook 32:1e1e7730b6c8 179 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
jvanhook 32:1e1e7730b6c8 180 - CLKPWR_PCLKSEL_UART2 : UART 2
jvanhook 32:1e1e7730b6c8 181 - CLKPWR_PCLKSEL_UART3 : UART 3
jvanhook 32:1e1e7730b6c8 182 - CLKPWR_PCLKSEL_I2C2 : I2C 2
jvanhook 32:1e1e7730b6c8 183 - CLKPWR_PCLKSEL_I2S : I2S
jvanhook 32:1e1e7730b6c8 184 - CLKPWR_PCLKSEL_RIT : RIT
jvanhook 32:1e1e7730b6c8 185 - CLKPWR_PCLKSEL_SYSCON : SYSCON
jvanhook 32:1e1e7730b6c8 186 - CLKPWR_PCLKSEL_MC : MC
jvanhook 32:1e1e7730b6c8 187
jvanhook 32:1e1e7730b6c8 188 * @return Value of Selected Peripheral Clock
jvanhook 32:1e1e7730b6c8 189 **********************************************************************/
jvanhook 32:1e1e7730b6c8 190 uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
jvanhook 32:1e1e7730b6c8 191 {
jvanhook 32:1e1e7730b6c8 192 uint32_t retval, div;
jvanhook 32:1e1e7730b6c8 193
jvanhook 32:1e1e7730b6c8 194 retval = SystemCoreClock;
jvanhook 32:1e1e7730b6c8 195 div = CLKPWR_GetPCLKSEL(ClkType);
jvanhook 32:1e1e7730b6c8 196
jvanhook 32:1e1e7730b6c8 197 switch (div)
jvanhook 32:1e1e7730b6c8 198 {
jvanhook 32:1e1e7730b6c8 199 case 0:
jvanhook 32:1e1e7730b6c8 200 div = 4;
jvanhook 32:1e1e7730b6c8 201 break;
jvanhook 32:1e1e7730b6c8 202
jvanhook 32:1e1e7730b6c8 203 case 1:
jvanhook 32:1e1e7730b6c8 204 div = 1;
jvanhook 32:1e1e7730b6c8 205 break;
jvanhook 32:1e1e7730b6c8 206
jvanhook 32:1e1e7730b6c8 207 case 2:
jvanhook 32:1e1e7730b6c8 208 div = 2;
jvanhook 32:1e1e7730b6c8 209 break;
jvanhook 32:1e1e7730b6c8 210
jvanhook 32:1e1e7730b6c8 211 case 3:
jvanhook 32:1e1e7730b6c8 212 div = 8;
jvanhook 32:1e1e7730b6c8 213 break;
jvanhook 32:1e1e7730b6c8 214 }
jvanhook 32:1e1e7730b6c8 215 retval /= div;
jvanhook 32:1e1e7730b6c8 216
jvanhook 32:1e1e7730b6c8 217 return retval;
jvanhook 32:1e1e7730b6c8 218 }
jvanhook 32:1e1e7730b6c8 219
jvanhook 32:1e1e7730b6c8 220
jvanhook 32:1e1e7730b6c8 221
jvanhook 32:1e1e7730b6c8 222 /*********************************************************************//**
jvanhook 32:1e1e7730b6c8 223 * @brief Configure power supply for each peripheral according to NewState
jvanhook 32:1e1e7730b6c8 224 * @param[in] PPType Type of peripheral used to enable power,
jvanhook 32:1e1e7730b6c8 225 * should be one of the following:
jvanhook 32:1e1e7730b6c8 226 * - CLKPWR_PCONP_PCTIM0 : Timer 0
jvanhook 32:1e1e7730b6c8 227 - CLKPWR_PCONP_PCTIM1 : Timer 1
jvanhook 32:1e1e7730b6c8 228 - CLKPWR_PCONP_PCUART0 : UART 0
jvanhook 32:1e1e7730b6c8 229 - CLKPWR_PCONP_PCUART1 : UART 1
jvanhook 32:1e1e7730b6c8 230 - CLKPWR_PCONP_PCPWM1 : PWM 1
jvanhook 32:1e1e7730b6c8 231 - CLKPWR_PCONP_PCI2C0 : I2C 0
jvanhook 32:1e1e7730b6c8 232 - CLKPWR_PCONP_PCSPI : SPI
jvanhook 32:1e1e7730b6c8 233 - CLKPWR_PCONP_PCRTC : RTC
jvanhook 32:1e1e7730b6c8 234 - CLKPWR_PCONP_PCSSP1 : SSP 1
jvanhook 32:1e1e7730b6c8 235 - CLKPWR_PCONP_PCAD : ADC
jvanhook 32:1e1e7730b6c8 236 - CLKPWR_PCONP_PCAN1 : CAN 1
jvanhook 32:1e1e7730b6c8 237 - CLKPWR_PCONP_PCAN2 : CAN 2
jvanhook 32:1e1e7730b6c8 238 - CLKPWR_PCONP_PCGPIO : GPIO
jvanhook 32:1e1e7730b6c8 239 - CLKPWR_PCONP_PCRIT : RIT
jvanhook 32:1e1e7730b6c8 240 - CLKPWR_PCONP_PCMC : MC
jvanhook 32:1e1e7730b6c8 241 - CLKPWR_PCONP_PCQEI : QEI
jvanhook 32:1e1e7730b6c8 242 - CLKPWR_PCONP_PCI2C1 : I2C 1
jvanhook 32:1e1e7730b6c8 243 - CLKPWR_PCONP_PCSSP0 : SSP 0
jvanhook 32:1e1e7730b6c8 244 - CLKPWR_PCONP_PCTIM2 : Timer 2
jvanhook 32:1e1e7730b6c8 245 - CLKPWR_PCONP_PCTIM3 : Timer 3
jvanhook 32:1e1e7730b6c8 246 - CLKPWR_PCONP_PCUART2 : UART 2
jvanhook 32:1e1e7730b6c8 247 - CLKPWR_PCONP_PCUART3 : UART 3
jvanhook 32:1e1e7730b6c8 248 - CLKPWR_PCONP_PCI2C2 : I2C 2
jvanhook 32:1e1e7730b6c8 249 - CLKPWR_PCONP_PCI2S : I2S
jvanhook 32:1e1e7730b6c8 250 - CLKPWR_PCONP_PCGPDMA : GPDMA
jvanhook 32:1e1e7730b6c8 251 - CLKPWR_PCONP_PCENET : Ethernet
jvanhook 32:1e1e7730b6c8 252 - CLKPWR_PCONP_PCUSB : USB
jvanhook 32:1e1e7730b6c8 253 *
jvanhook 32:1e1e7730b6c8 254 * @param[in] NewState New state of Peripheral Power, should be:
jvanhook 32:1e1e7730b6c8 255 * - ENABLE : Enable power for this peripheral
jvanhook 32:1e1e7730b6c8 256 * - DISABLE : Disable power for this peripheral
jvanhook 32:1e1e7730b6c8 257 *
jvanhook 32:1e1e7730b6c8 258 * @return none
jvanhook 32:1e1e7730b6c8 259 **********************************************************************/
jvanhook 32:1e1e7730b6c8 260 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
jvanhook 32:1e1e7730b6c8 261 {
jvanhook 32:1e1e7730b6c8 262 if (NewState == ENABLE)
jvanhook 32:1e1e7730b6c8 263 {
jvanhook 32:1e1e7730b6c8 264 LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK;
jvanhook 32:1e1e7730b6c8 265 }
jvanhook 32:1e1e7730b6c8 266 else if (NewState == DISABLE)
jvanhook 32:1e1e7730b6c8 267 {
jvanhook 32:1e1e7730b6c8 268 LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
jvanhook 32:1e1e7730b6c8 269 }
jvanhook 32:1e1e7730b6c8 270 }
jvanhook 32:1e1e7730b6c8 271
jvanhook 32:1e1e7730b6c8 272
jvanhook 32:1e1e7730b6c8 273 /*********************************************************************//**
jvanhook 32:1e1e7730b6c8 274 * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
jvanhook 32:1e1e7730b6c8 275 * @param[in] None
jvanhook 32:1e1e7730b6c8 276 * @return None
jvanhook 32:1e1e7730b6c8 277 **********************************************************************/
jvanhook 32:1e1e7730b6c8 278 void CLKPWR_Sleep(void)
jvanhook 32:1e1e7730b6c8 279 {
jvanhook 32:1e1e7730b6c8 280 LPC_SC->PCON = 0x00;
jvanhook 32:1e1e7730b6c8 281 /* Sleep Mode*/
jvanhook 32:1e1e7730b6c8 282 __WFI();
jvanhook 32:1e1e7730b6c8 283 }
jvanhook 32:1e1e7730b6c8 284
jvanhook 32:1e1e7730b6c8 285
jvanhook 32:1e1e7730b6c8 286 /*********************************************************************//**
jvanhook 32:1e1e7730b6c8 287 * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
jvanhook 32:1e1e7730b6c8 288 * @param[in] None
jvanhook 32:1e1e7730b6c8 289 * @return None
jvanhook 32:1e1e7730b6c8 290 **********************************************************************/
jvanhook 32:1e1e7730b6c8 291 void CLKPWR_DeepSleep(void)
jvanhook 32:1e1e7730b6c8 292 {
jvanhook 32:1e1e7730b6c8 293 /* Deep-Sleep Mode, set SLEEPDEEP bit */
jvanhook 32:1e1e7730b6c8 294 SCB->SCR = 0x4;
jvanhook 32:1e1e7730b6c8 295 LPC_SC->PCON = 0x8;
jvanhook 32:1e1e7730b6c8 296 /* Deep Sleep Mode*/
jvanhook 32:1e1e7730b6c8 297 __WFI();
jvanhook 32:1e1e7730b6c8 298 }
jvanhook 32:1e1e7730b6c8 299
jvanhook 32:1e1e7730b6c8 300
jvanhook 32:1e1e7730b6c8 301 /*********************************************************************//**
jvanhook 32:1e1e7730b6c8 302 * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
jvanhook 32:1e1e7730b6c8 303 * @param[in] None
jvanhook 32:1e1e7730b6c8 304 * @return None
jvanhook 32:1e1e7730b6c8 305 **********************************************************************/
jvanhook 32:1e1e7730b6c8 306 void CLKPWR_PowerDown(void)
jvanhook 32:1e1e7730b6c8 307 {
jvanhook 32:1e1e7730b6c8 308 /* Deep-Sleep Mode, set SLEEPDEEP bit */
jvanhook 32:1e1e7730b6c8 309 SCB->SCR = 0x4;
jvanhook 32:1e1e7730b6c8 310 LPC_SC->PCON = 0x09;
jvanhook 32:1e1e7730b6c8 311 /* Power Down Mode*/
jvanhook 32:1e1e7730b6c8 312 __WFI();
jvanhook 32:1e1e7730b6c8 313 }
jvanhook 32:1e1e7730b6c8 314
jvanhook 32:1e1e7730b6c8 315
jvanhook 32:1e1e7730b6c8 316 /*********************************************************************//**
jvanhook 32:1e1e7730b6c8 317 * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
jvanhook 32:1e1e7730b6c8 318 * @param[in] None
jvanhook 32:1e1e7730b6c8 319 * @return None
jvanhook 32:1e1e7730b6c8 320 **********************************************************************/
jvanhook 32:1e1e7730b6c8 321 void CLKPWR_DeepPowerDown(void)
jvanhook 32:1e1e7730b6c8 322 {
jvanhook 32:1e1e7730b6c8 323 /* Deep-Sleep Mode, set SLEEPDEEP bit */
jvanhook 32:1e1e7730b6c8 324 SCB->SCR = 0x4;
jvanhook 32:1e1e7730b6c8 325 LPC_SC->PCON = 0x03;
jvanhook 32:1e1e7730b6c8 326 /* Deep Power Down Mode*/
jvanhook 32:1e1e7730b6c8 327 __WFI();
jvanhook 32:1e1e7730b6c8 328 }
jvanhook 32:1e1e7730b6c8 329
jvanhook 32:1e1e7730b6c8 330 /**
jvanhook 32:1e1e7730b6c8 331 * @}
jvanhook 32:1e1e7730b6c8 332 */
jvanhook 32:1e1e7730b6c8 333
jvanhook 32:1e1e7730b6c8 334 /**
jvanhook 32:1e1e7730b6c8 335 * @}
jvanhook 32:1e1e7730b6c8 336 */
jvanhook 32:1e1e7730b6c8 337
jvanhook 32:1e1e7730b6c8 338 /* --------------------------------- End Of File ------------------------------ */