Yoshihiro TSUBOI
Originally from Donal's blog article. http://mbed.org/users/donalm/code/BLE_Health_Thermometer_Blog/ Changed low freq. clock source from XTAL to IRC.
Dependents: BLE_Health_Thermometer_IRC BLE_RCBController_micono_test BLE_konashi_PIO_test BLE_ADT7410_TMP102_Sample ... more
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BLE_API_Native_blog
by 
Donal Morrissey
Revision 10:eb5f77205fb5, committed 2014-02-17
- Comitter:
- ktownsend
- Date:
- Mon Feb 17 11:06:48 2014 +0000
- Parent:
- 7:98bd2ebda25e
- Child:
- 11:2eda55259984
- Commit message:
- Removed unnecessary files
Changed in this revision
--- a/hw/nRF51822n/common/common.h Thu Feb 13 11:27:58 2014 +0000 +++ b/hw/nRF51822n/common/common.h Mon Feb 17 11:06:48 2014 +0000 @@ -68,7 +68,7 @@ #include "ble_error.h" //------------- MCU header -------------// -#include "nrf.h" +//#include "nrf.h" //--------------------------------------------------------------------+ // TYPEDEFS
--- a/hw/nRF51822n/nordic/app_common/app_button.cpp Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,250 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#include "app_button.h"
-#include <string.h>
-#include "nordic_common.h"
-#include "app_util.h"
-#include "app_gpiote.h"
-#include "app_timer.h"
-#include "app_error.h"
-
-
-static app_button_cfg_t * mp_buttons = NULL; /**< Button configuration. */
-static uint8_t m_button_count; /**< Number of configured buttons. */
-static uint32_t m_active_low_states_mask; /**< Mask representing buttons which are active low. */
-static uint32_t m_active_high_states_mask; /**< Mask representing buttons which are active high. */
-static uint32_t m_detection_delay; /**< Delay before a button is reported as pushed. */
-static app_button_evt_schedule_func_t m_evt_schedule_func; /**< Pointer to function for propagating button events to the scheduler. */
-static app_gpiote_user_id_t m_gpiote_user_id; /**< GPIOTE user id for buttons module. */
-static app_timer_id_t m_detection_delay_timer_id; /**< Polling timer id. */
-
-
-/**@brief Function for executing the application button handler for specified button.
- *
- * @param[in] p_btn Button that has been pushed.
- */
-static void button_handler_execute(app_button_cfg_t * p_btn)
-{
- if (m_evt_schedule_func != NULL)
- {
- uint32_t err_code = m_evt_schedule_func(p_btn->button_handler, p_btn->pin_no);
- APP_ERROR_CHECK(err_code);
- }
- else
- {
- p_btn->button_handler(p_btn->pin_no);
- }
-}
-
-
-/**@brief Function for handling the timeout that delays reporting buttons as pushed.
- *
- * @details The detection_delay_timeout_handler(...) is a call-back issued from the app_timer
- * module. It is called with the p_context parameter. The p_context parameter is
- * provided to the app_timer module when a timer is started, using the call
- * @ref app_timer_start. On @ref app_timer_start the p_context will be holding the
- * currently pressed buttons.
- *
- * @param[in] p_context Pointer used for passing information app_start_timer() was called.
- * In the app_button module the p_context holds information on pressed
- * buttons.
- */
-static void detection_delay_timeout_handler(void * p_context)
-{
- uint32_t err_code;
- uint32_t event_pins_mask;
- uint32_t current_state_pins;
- uint32_t active_pins = 0;
-
- // Get state of pins when timer was started.
- event_pins_mask = (uint32_t)p_context;
-
- // Get current state of pins.
- err_code = app_gpiote_pins_state_get(m_gpiote_user_id, ¤t_state_pins);
- if (err_code != NRF_SUCCESS)
- {
- return;
- }
-
- active_pins = current_state_pins & m_active_high_states_mask;
- active_pins |= (~current_state_pins & m_active_low_states_mask);
- event_pins_mask &= active_pins;
-
- // Check if any event generating pins are still active.
- if (event_pins_mask != 0)
- {
- uint8_t i;
-
- // Pushed button(s) detected, execute button handler(s).
- for (i = 0; i < m_button_count; i++)
- {
- app_button_cfg_t * p_btn = &mp_buttons[i];
-
- if (((event_pins_mask & (1 << p_btn->pin_no)) != 0) && (p_btn->button_handler != NULL))
- {
- button_handler_execute(p_btn);
- }
- }
- }
-}
-
-
-/**@brief Function for handling the GPIOTE event.
- *
- * @details Saves the current status of the button pins, and starts a timer. If the timer is already
- * running, it will be restarted.
- *
- * @param[in] event_pins_low_to_high Mask telling which pin(s) had a low to high transition.
- * @param[in] event_pins_high_to_low Mask telling which pin(s) had a high to low transition.
- */
-static void gpiote_event_handler(uint32_t event_pins_low_to_high, uint32_t event_pins_high_to_low)
-{
- uint32_t err_code;
-
- // Start detection timer. If timer is already running, the detection period is restarted.
- // NOTE: Using the p_context parameter of app_timer_start() to transfer the pin states to the
- // timeout handler (by casting event_pins_mask into the equally sized void * p_context
- // parameter).
- STATIC_ASSERT(sizeof(void *) == sizeof(uint32_t));
-
- err_code = app_timer_stop(m_detection_delay_timer_id);
- if (err_code != NRF_SUCCESS)
- {
- // The impact in app_button of the app_timer queue running full is losing a button press.
- // The current implementation ensures that the system will continue working as normal.
- return;
- }
-
- err_code = app_timer_start(m_detection_delay_timer_id,
- m_detection_delay,
- (void *)(event_pins_low_to_high | event_pins_high_to_low));
- if (err_code != NRF_SUCCESS)
- {
- // The impact in app_button of the app_timer queue running full is losing a button press.
- // The current implementation ensures that the system will continue working as normal.
- }
-}
-
-
-uint32_t app_button_init(app_button_cfg_t * p_buttons,
- uint8_t button_count,
- uint32_t detection_delay,
- app_button_evt_schedule_func_t evt_schedule_func)
-{
- uint32_t err_code;
-
- if (detection_delay < APP_TIMER_MIN_TIMEOUT_TICKS)
- {
- return NRF_ERROR_INVALID_PARAM;
- }
-
- // Save configuration.
- mp_buttons = p_buttons;
- m_button_count = button_count;
- m_detection_delay = detection_delay;
- m_evt_schedule_func = evt_schedule_func;
-
- // Configure pins.
- m_active_high_states_mask = 0;
- m_active_low_states_mask = 0;
-
- while (button_count--)
- {
- app_button_cfg_t * p_btn = &p_buttons[button_count];
-
- // Configure pin.
- nrf_gpio_cfg_input(p_btn->pin_no, p_btn->pull_cfg);
-
- // Build GPIOTE user registration masks.
- m_active_high_states_mask |= ((p_btn->active_high ? 1 : 0) << p_btn->pin_no);
- m_active_low_states_mask |= ((p_btn->active_high ? 0 : 1) << p_btn->pin_no);
- }
-
- // Register button module as a GPIOTE user.
- err_code = app_gpiote_user_register(&m_gpiote_user_id,
- m_active_high_states_mask,
- m_active_low_states_mask,
- gpiote_event_handler);
- if (err_code != NRF_SUCCESS)
- {
- return err_code;
- }
-
- // Create polling timer.
- return app_timer_create(&m_detection_delay_timer_id,
- APP_TIMER_MODE_SINGLE_SHOT,
- detection_delay_timeout_handler);
-}
-
-
-uint32_t app_button_enable(void)
-{
- if (mp_buttons == NULL)
- {
- return NRF_ERROR_INVALID_STATE;
- }
-
- return app_gpiote_user_enable(m_gpiote_user_id);
-}
-
-
-uint32_t app_button_disable(void)
-{
- uint32_t err_code;
-
- if (mp_buttons == NULL)
- {
- return NRF_ERROR_INVALID_STATE;
- }
-
- err_code = app_gpiote_user_disable(m_gpiote_user_id);
- if (err_code != NRF_SUCCESS)
- {
- return err_code;
- }
-
- // Make sure polling timer is not running.
- return app_timer_stop(m_detection_delay_timer_id);
-}
-
-
-uint32_t app_button_is_pushed(uint8_t pin_no, bool * p_is_pushed)
-{
- uint32_t err_code;
- uint32_t active_pins;
- uint32_t pin_mask = 0;
-
- if (mp_buttons == NULL)
- {
- return NRF_ERROR_INVALID_STATE;
- }
-
- err_code = app_gpiote_pins_state_get(m_gpiote_user_id, &active_pins);
- if (err_code != NRF_SUCCESS)
- {
- return err_code;
- }
-
- pin_mask = (1 << pin_no);
-
- if ((pin_mask & active_pins) == 0)
- {
- *p_is_pushed = ((m_active_low_states_mask & pin_mask) ? true : false);
- }
- else
- {
- *p_is_pushed = ((m_active_high_states_mask & pin_mask) ? true : false);
- }
-
- return NRF_SUCCESS;
-}
--- a/hw/nRF51822n/nordic/app_common/app_gpiote.cpp Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,303 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#include "app_gpiote.h"
-#include <stdlib.h>
-#include <string.h>
-#include "app_util.h"
-#include "nrf_error.h"
-#include "nrf_gpio.h"
-
-
-/**@brief GPIOTE user type. */
-typedef struct
-{
- uint32_t pins_mask; /**< Mask defining which pins user wants to monitor. */
- uint32_t pins_low_to_high_mask; /**< Mask defining which pins will generate events to this user when toggling low->high. */
- uint32_t pins_high_to_low_mask; /**< Mask defining which pins will generate events to this user when toggling high->low. */
- uint32_t sense_high_pins; /**< Mask defining which pins are configured to generate GPIOTE interrupt on transition to high level. */
- app_gpiote_event_handler_t event_handler; /**< Pointer to function to be executed when an event occurs. */
-} gpiote_user_t;
-
-STATIC_ASSERT(sizeof(gpiote_user_t) <= GPIOTE_USER_NODE_SIZE);
-STATIC_ASSERT(sizeof(gpiote_user_t) % 4 == 0);
-
-static uint32_t m_enabled_users_mask; /**< Mask for tracking which users are enabled. */
-static uint8_t m_user_array_size; /**< Size of user array. */
-static uint8_t m_user_count; /**< Number of registered users. */
-static gpiote_user_t * mp_users = NULL; /**< Array of GPIOTE users. */
-
-
-/**@brief Function for toggling sense level for specified pins.
- *
- * @param[in] p_user Pointer to user structure.
- * @param[in] pins Bitmask specifying for which pins the sense level is to be toggled.
- */
-static void sense_level_toggle(gpiote_user_t * p_user, uint32_t pins)
-{
- uint32_t pin_no;
-
- for (pin_no = 0; pin_no < NO_OF_PINS; pin_no++)
- {
- uint32_t pin_mask = (1 << pin_no);
-
- if ((pins & pin_mask) != 0)
- {
- uint32_t sense;
-
- // Invert sensing.
- if ((p_user->sense_high_pins & pin_mask) == 0)
- {
- sense = GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos;
- p_user->sense_high_pins |= pin_mask;
- }
- else
- {
- sense = GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos;
- p_user->sense_high_pins &= ~pin_mask;
- }
-
- NRF_GPIO->PIN_CNF[pin_no] &= ~GPIO_PIN_CNF_SENSE_Msk;
- NRF_GPIO->PIN_CNF[pin_no] |= sense;
- }
- }
-}
-
-
-/**@brief Function for handling the GPIOTE interrupt.
- */
- /*
-extern "C" void GPIOTE_IRQHandler(void)
-{
- uint8_t i;
- uint32_t pins_state = NRF_GPIO->IN;
-
- // Clear event.
- NRF_GPIOTE->EVENTS_PORT = 0;
-
- // Check all users.
- for (i = 0; i < m_user_count; i++)
- {
- gpiote_user_t * p_user = &mp_users[i];
-
- // Check if user is enabled.
- if (((1 << i) & m_enabled_users_mask) != 0)
- {
- uint32_t transition_pins;
- uint32_t event_low_to_high;
- uint32_t event_high_to_low;
-
- // Find set of pins on which there has been a transition.
- transition_pins = (pins_state ^ ~p_user->sense_high_pins) & p_user->pins_mask;
-
- // Toggle SENSE level for all pins that have changed state.
- sense_level_toggle(p_user, transition_pins);
-
- // Call user event handler if an event has occurred.
- event_high_to_low = (~pins_state & p_user->pins_high_to_low_mask) & transition_pins;
- event_low_to_high = (pins_state & p_user->pins_low_to_high_mask) & transition_pins;
-
- if ((event_low_to_high | event_high_to_low) != 0)
- {
- p_user->event_handler(event_low_to_high, event_high_to_low);
- }
- }
- }
-}
-*/
-
-/**@brief Function for sense disabling for all pins for specified user.
- *
- * @param[in] user_id User id.
- */
-static void pins_sense_disable(app_gpiote_user_id_t user_id)
-{
- uint32_t pin_no;
-
- for (pin_no = 0; pin_no < 32; pin_no++)
- {
- if ((mp_users[user_id].pins_mask & (1 << pin_no)) != 0)
- {
- NRF_GPIO->PIN_CNF[pin_no] &= ~GPIO_PIN_CNF_SENSE_Msk;
- NRF_GPIO->PIN_CNF[pin_no] |= GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos;
- }
- }
-}
-
-
-uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer)
-{
- if (p_buffer == NULL)
- {
- return NRF_ERROR_INVALID_PARAM;
- }
-
- // Check that buffer is correctly aligned.
- if (!is_word_aligned(p_buffer))
- {
- return NRF_ERROR_INVALID_PARAM;
- }
-
- // Initialize file globals.
- mp_users = (gpiote_user_t *)p_buffer;
- m_user_array_size = max_users;
- m_user_count = 0;
- m_enabled_users_mask = 0;
-
- memset(mp_users, 0, m_user_array_size * sizeof(gpiote_user_t));
-
- // Initialize GPIOTE interrupt (will not be enabled until app_gpiote_user_enable() is called).
- NRF_GPIOTE->INTENCLR = 0xFFFFFFFF;
-
- NVIC_ClearPendingIRQ(GPIOTE_IRQn);
- NVIC_SetPriority(GPIOTE_IRQn, APP_IRQ_PRIORITY_HIGH);
- NVIC_EnableIRQ(GPIOTE_IRQn);
-
- return NRF_SUCCESS;
-}
-
-
-uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id,
- uint32_t pins_low_to_high_mask,
- uint32_t pins_high_to_low_mask,
- app_gpiote_event_handler_t event_handler)
-{
- // Check state and parameters.
- if (mp_users == NULL)
- {
- return NRF_ERROR_INVALID_STATE;
- }
- if (event_handler == NULL)
- {
- return NRF_ERROR_INVALID_PARAM;
- }
- if (m_user_count >= m_user_array_size)
- {
- return NRF_ERROR_NO_MEM;
- }
-
- // Allocate new user.
- mp_users[m_user_count].pins_mask = pins_low_to_high_mask | pins_high_to_low_mask;
- mp_users[m_user_count].pins_low_to_high_mask = pins_low_to_high_mask;
- mp_users[m_user_count].pins_high_to_low_mask = pins_high_to_low_mask;
- mp_users[m_user_count].event_handler = event_handler;
-
- *p_user_id = m_user_count++;
-
- // Make sure SENSE is disabled for all pins.
- pins_sense_disable(*p_user_id);
-
- return NRF_SUCCESS;
-}
-
-
-uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id)
-{
- uint32_t pin_no;
- uint32_t pins_state;
-
- // Check state and parameters.
- if (mp_users == NULL)
- {
- return NRF_ERROR_INVALID_STATE;
- }
- if (user_id >= m_user_count)
- {
- return NRF_ERROR_INVALID_PARAM;
- }
-
- // Clear any pending event.
- NRF_GPIOTE->EVENTS_PORT = 0;
- pins_state = NRF_GPIO->IN;
-
- // Enable user.
- if (m_enabled_users_mask == 0)
- {
- NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Msk;
- }
- m_enabled_users_mask |= (1 << user_id);
-
- // Enable sensing for all pins for specified user.
- mp_users[user_id].sense_high_pins = 0;
- for (pin_no = 0; pin_no < 32; pin_no++)
- {
- uint32_t pin_mask = (1 << pin_no);
-
- if ((mp_users[user_id].pins_mask & pin_mask) != 0)
- {
- uint32_t sense;
-
- if ((pins_state & pin_mask) != 0)
- {
- sense = GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos;
- }
- else
- {
- sense = GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos;
- mp_users[user_id].sense_high_pins |= pin_mask;
- }
-
- NRF_GPIO->PIN_CNF[pin_no] &= ~GPIO_PIN_CNF_SENSE_Msk;
- NRF_GPIO->PIN_CNF[pin_no] |= sense;
- }
- }
-
- return NRF_SUCCESS;
-}
-
-
-uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id)
-{
- // Check state and parameters.
- if (mp_users == NULL)
- {
- return NRF_ERROR_INVALID_STATE;
- }
- if (user_id >= m_user_count)
- {
- return NRF_ERROR_INVALID_PARAM;
- }
-
- // Disable sensing for all pins for specified user.
- pins_sense_disable(user_id);
-
- // Disable user.
- m_enabled_users_mask &= ~(1UL << user_id);
- if (m_enabled_users_mask == 0)
- {
- NRF_GPIOTE->INTENCLR = GPIOTE_INTENSET_PORT_Msk;
- }
-
- return NRF_SUCCESS;
-}
-
-
-uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins)
-{
- gpiote_user_t * p_user;
-
- // Check state and parameters.
- if (mp_users == NULL)
- {
- return NRF_ERROR_INVALID_STATE;
- }
- if (user_id >= m_user_count)
- {
- return NRF_ERROR_INVALID_PARAM;
- }
-
- // Get pins.
- p_user = &mp_users[user_id];
- *p_pins = NRF_GPIO->IN & p_user->pins_mask;
-
- return NRF_SUCCESS;
-}
--- a/hw/nRF51822n/nordic/app_common/app_timer.cpp Thu Feb 13 11:27:58 2014 +0000
+++ b/hw/nRF51822n/nordic/app_common/app_timer.cpp Mon Feb 17 11:06:48 2014 +0000
@@ -16,7 +16,8 @@
#include "nrf51_bitfields.h"
#include "nrf_soc.h"
#include "app_error.h"
-#include "nrf_delay.h"
+//#include "nrf_delay.h"
+#include "mbed.h"
#include "app_util.h"
@@ -160,7 +161,7 @@
NVIC_EnableIRQ(RTC1_IRQn);
NRF_RTC1->TASKS_START = 1;
- nrf_delay_us(MAX_RTC_TASKS_DELAY);
+ wait(0.0000001 * MAX_RTC_TASKS_DELAY);
}
@@ -174,7 +175,7 @@
NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
NRF_RTC1->TASKS_STOP = 1;
- nrf_delay_us(MAX_RTC_TASKS_DELAY);
+ wait(0.0000001 * MAX_RTC_TASKS_DELAY);
}
@@ -972,10 +973,9 @@
m_ticks_elapsed_q_read_ind = 0;
m_ticks_elapsed_q_write_ind = 0;
- // KTOWN: 1302024: This interrupt isn't used
- //NVIC_ClearPendingIRQ(SWI0_IRQn);
- //NVIC_SetPriority(SWI0_IRQn, SWI0_IRQ_PRI);
- //NVIC_EnableIRQ(SWI0_IRQn);
+ NVIC_ClearPendingIRQ(SWI0_IRQn);
+ NVIC_SetPriority(SWI0_IRQn, SWI0_IRQ_PRI);
+ NVIC_EnableIRQ(SWI0_IRQn);
rtc1_init(prescaler);
--- a/hw/nRF51822n/nordic/app_common/pstorage.cpp Thu Feb 13 11:27:58 2014 +0000 +++ b/hw/nRF51822n/nordic/app_common/pstorage.cpp Mon Feb 17 11:06:48 2014 +0000 @@ -16,7 +16,7 @@ #include "nordic_common.h" #include "nrf_error.h" #include "nrf_assert.h" -#include "nrf.h" +//#include "nrf.h" #include "nrf_soc.h" #include "app_util.h" #include "pstorage.h"
--- a/hw/nRF51822n/nordic/ble/ble_bondmngr.cpp Thu Feb 13 11:27:58 2014 +0000 +++ b/hw/nRF51822n/nordic/ble/ble_bondmngr.cpp Mon Feb 17 11:06:48 2014 +0000 @@ -20,7 +20,7 @@ #include "ble_srv_common.h" #include "app_util.h" #include "nrf_assert.h" -#include "nrf.h" +//#include "nrf.h" #include "nrf51_bitfields.h" #include "crc16.h" #include "pstorage.h"
--- a/hw/nRF51822n/nordic/ble/ble_flash.cpp Thu Feb 13 11:27:58 2014 +0000 +++ b/hw/nRF51822n/nordic/ble/ble_flash.cpp Mon Feb 17 11:06:48 2014 +0000 @@ -17,7 +17,7 @@ #include "nrf_soc.h" #include "nordic_common.h" #include "nrf_error.h" -#include "nrf.h" +//#include "nrf.h" #include "nrf51_bitfields.h" #include "app_util.h"
--- a/hw/nRF51822n/nordic/nordic.txt Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,300 +0,0 @@ - Le volume dans le lecteur C s'appelle BOOTCAMP - Le numéro de série du volume est 7A29-D22E - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\app_common - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 8 705 app_button.c -23/01/2014 16:10 1 845 app_fifo.c -23/01/2014 16:10 9 335 app_gpiote.c -23/01/2014 16:10 6 458 app_scheduler.c -23/01/2014 16:10 38 941 app_timer.c -23/01/2014 16:10 17 911 app_uart.c -23/01/2014 16:10 19 513 app_uart_fifo.c -23/01/2014 16:10 937 crc16.c -23/01/2014 16:10 8 081 hci_mem_pool.c -23/01/2014 16:10 12 637 hci_slip.c -23/01/2014 16:10 31 335 hci_transport.c -23/01/2014 16:10 27 457 pstorage.c - 12 fichier(s) 183 155 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\ble - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 19 794 ble_advdata.c -23/01/2014 16:10 580 ble_advdata_parser.c -23/01/2014 16:10 54 507 ble_bondmngr.c -23/01/2014 16:10 3 990 ble_central_bondmngr.c -23/01/2014 16:10 10 227 ble_conn_params.c -23/01/2014 16:10 2 154 ble_debug_assert_handler.c -23/01/2014 16:10 26 934 ble_dtm.c -23/01/2014 16:10 1 935 ble_error_log.c -23/01/2014 16:10 8 266 ble_flash.c -23/01/2014 16:10 1 514 ble_racp.c -23/01/2014 16:10 1 827 ble_radio_notification.c -23/01/2014 16:10 1 633 ble_sensorsim.c -23/01/2014 16:10 <REP> ble_services - 12 fichier(s) 133 361 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\ble\ble_services - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 40 149 ble_ans_c.c -23/01/2014 16:10 9 752 ble_bas.c -23/01/2014 16:10 14 872 ble_bps.c -23/01/2014 16:10 15 695 ble_cscs.c -23/01/2014 16:10 19 817 ble_dfu.c -23/01/2014 16:10 10 248 ble_dis.c -23/01/2014 16:10 40 961 ble_gls.c -23/01/2014 16:10 2 536 ble_gls_db.c -23/01/2014 16:10 46 241 ble_hids.c -23/01/2014 16:10 14 378 ble_hrs.c -23/01/2014 16:10 13 965 ble_hts.c -23/01/2014 16:10 4 671 ble_ias.c -23/01/2014 16:10 8 779 ble_ias_c.c -23/01/2014 16:10 6 135 ble_lls.c -23/01/2014 16:10 12 728 ble_rscs.c -23/01/2014 16:10 21 465 ble_sc_ctrlpt.c -23/01/2014 16:10 1 307 ble_srv_common.c -23/01/2014 16:10 3 483 ble_tps.c - 18 fichier(s) 287 182 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 <REP> app_common -23/01/2014 16:10 <REP> ble -23/01/2014 16:10 <REP> boards -23/01/2014 16:10 855 boards.h -23/01/2014 16:10 1 272 common.h -23/01/2014 16:10 2 792 compiler_abstraction.h -23/01/2014 16:10 12 980 console.h -23/01/2014 16:10 <REP> esb -23/01/2014 16:10 <REP> ext_sensors -23/01/2014 16:10 <REP> gcc -23/01/2014 16:10 <REP> gzll -23/01/2014 16:10 <REP> gzp -23/01/2014 16:10 3 069 nordic_common.h -23/01/2014 16:10 845 nrf.h -23/01/2014 16:10 90 492 nrf51.h -23/01/2014 16:10 385 146 nrf51_bitfields.h -23/01/2014 16:10 32 236 nrf51_deprecated.h -23/01/2014 16:10 2 130 nrf_assert.h -23/01/2014 16:10 1 408 nrf_delay.h -23/01/2014 16:10 1 879 nrf_ecb.h -23/01/2014 16:10 15 421 nrf_gpio.h -23/01/2014 16:10 6 994 nrf_gpiote.h -23/01/2014 16:10 2 311 nrf_nvmc.h -23/01/2014 16:10 1 739 nrf_temp.h -23/01/2014 16:10 <REP> s110 -23/01/2014 16:10 <REP> s120 -23/01/2014 16:10 <REP> sd_common -23/01/2014 16:10 2 582 simple_uart.h -23/01/2014 16:10 4 357 spi_master.h -23/01/2014 16:10 6 244 spi_slave.h -23/01/2014 16:10 1 192 system_nrf51.h -23/01/2014 16:10 4 657 twi_master.h - 21 fichier(s) 580 601 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\app_common - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 8 249 app_button.h -23/01/2014 16:10 3 008 app_error.h -23/01/2014 16:10 3 059 app_fifo.h -23/01/2014 16:10 8 149 app_gpiote.h -23/01/2014 16:10 6 290 app_scheduler.h -23/01/2014 16:10 16 098 app_timer.h -23/01/2014 16:10 16 292 app_uart.h -23/01/2014 16:10 12 106 app_util.h -23/01/2014 16:10 1 409 crc16.h -23/01/2014 16:10 5 140 hci_mem_pool.h -23/01/2014 16:10 945 hci_mem_pool_internal.h -23/01/2014 16:10 6 122 hci_slip.h -23/01/2014 16:10 9 739 hci_transport.h -23/01/2014 16:10 19 189 pstorage.h - 14 fichier(s) 115 795 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\ble - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 6 132 ble_advdata.h -23/01/2014 16:10 304 ble_advdata_parser.h -23/01/2014 16:10 17 086 ble_bondmngr.h -23/01/2014 16:10 650 ble_central_bondmngr.h -23/01/2014 16:10 5 841 ble_conn_params.h -23/01/2014 16:10 2 261 ble_date_time.h -23/01/2014 16:10 2 068 ble_debug_assert_handler.h -23/01/2014 16:10 7 194 ble_dtm.h -23/01/2014 16:10 3 034 ble_error_log.h -23/01/2014 16:10 5 842 ble_flash.h -23/01/2014 16:10 5 765 ble_racp.h -23/01/2014 16:10 1 738 ble_radio_notification.h -23/01/2014 16:10 2 334 ble_sensorsim.h -23/01/2014 16:10 <REP> ble_services -23/01/2014 16:10 <REP> rpc - 13 fichier(s) 60 249 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\ble\ble_services - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 21 145 ble_ans_c.h -23/01/2014 16:10 6 750 ble_bas.h -23/01/2014 16:10 9 025 ble_bps.h -23/01/2014 16:10 9 947 ble_cscs.h -23/01/2014 16:10 14 110 ble_dfu.h -23/01/2014 16:10 4 749 ble_dis.h -23/01/2014 16:10 16 676 ble_gls.h -23/01/2014 16:10 2 634 ble_gls_db.h -23/01/2014 16:10 18 015 ble_hids.h -23/01/2014 16:10 10 370 ble_hrs.h -23/01/2014 16:10 8 368 ble_hts.h -23/01/2014 16:10 4 606 ble_ias.h -23/01/2014 16:10 5 898 ble_ias_c.h -23/01/2014 16:10 4 971 ble_lls.h -23/01/2014 16:10 7 866 ble_rscs.h -23/01/2014 16:10 12 675 ble_sc_ctrlpt.h -23/01/2014 16:10 1 770 ble_sensor_location.h -23/01/2014 16:10 16 545 ble_srv_common.h -23/01/2014 16:10 3 114 ble_tps.h - 19 fichier(s) 179 234 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\ble\rpc - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 3 777 ble_rpc_cmd_decoder.h -23/01/2014 16:10 2 280 ble_rpc_cmd_decoder_gap.h -23/01/2014 16:10 2 298 ble_rpc_cmd_decoder_gatts.h -23/01/2014 16:10 2 541 ble_rpc_cmd_encoder.h -23/01/2014 16:10 3 121 ble_rpc_defines.h -23/01/2014 16:10 1 588 ble_rpc_event_decoder.h -23/01/2014 16:10 1 628 ble_rpc_event_decoder_gap.h -23/01/2014 16:10 2 040 ble_rpc_event_decoder_gatts.h -23/01/2014 16:10 1 147 ble_rpc_event_encoder.h -23/01/2014 16:10 1 236 ble_rpc_event_encoder_gap.h -23/01/2014 16:10 1 251 ble_rpc_event_encoder_gatts.h -23/01/2014 16:10 976 ble_rpc_pkt_receiver.h - 12 fichier(s) 23 883 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\boards - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 1 653 nrf6310.h -23/01/2014 16:10 957 pca10000.h -23/01/2014 16:10 927 pca10001.h -23/01/2014 16:10 928 pca10003.h -23/01/2014 16:10 926 pca1000x.h - 5 fichier(s) 5 391 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\esb - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 20 671 nrf_esb.h -23/01/2014 16:10 7 860 nrf_esb_constants.h - 2 fichier(s) 28 531 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\ext_sensors - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 9 767 adns2080.h -23/01/2014 16:10 3 410 cherry8x16.h -23/01/2014 16:10 2 399 ds1624.h -23/01/2014 16:10 2 302 mpu6050.h -23/01/2014 16:10 3 625 nRF6350.h -23/01/2014 16:10 1 991 sdio.h -23/01/2014 16:10 4 408 synaptics_touchpad.h - 7 fichier(s) 27 902 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\gcc - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 33 182 core_cm0.h -23/01/2014 16:10 17 814 core_cmFunc.h -23/01/2014 16:10 20 855 core_cmInstr.h - 3 fichier(s) 71 851 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\gzll - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 28 349 nrf_gzll.h -23/01/2014 16:10 9 533 nrf_gzll_constants.h - 2 fichier(s) 37 882 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\gzp - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 21 868 nrf_gzp.h - 1 fichier(s) 21 868 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\s110 - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 15 918 ble.h -23/01/2014 16:10 1 713 ble_err.h -23/01/2014 16:10 48 197 ble_gap.h -23/01/2014 16:10 9 859 ble_gatt.h -23/01/2014 16:10 20 964 ble_gattc.h -23/01/2014 16:10 33 958 ble_gatts.h -23/01/2014 16:10 3 441 ble_hci.h -23/01/2014 16:10 5 065 ble_l2cap.h -23/01/2014 16:10 2 333 ble_ranges.h -23/01/2014 16:10 9 136 ble_types.h -23/01/2014 16:10 2 644 nrf_error.h -23/01/2014 16:10 1 118 nrf_error_sdm.h -23/01/2014 16:10 1 917 nrf_error_soc.h -23/01/2014 16:10 7 525 nrf_sdm.h -23/01/2014 16:10 30 878 nrf_soc.h -23/01/2014 16:10 969 nrf_svc.h -23/01/2014 16:10 1 693 softdevice_assert.h - 17 fichier(s) 197 328 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\s120 - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 16 272 ble.h -23/01/2014 16:10 1 826 ble_err.h -23/01/2014 16:10 56 022 ble_gap.h -23/01/2014 16:10 9 813 ble_gatt.h -23/01/2014 16:10 20 640 ble_gattc.h -23/01/2014 16:10 33 802 ble_gatts.h -23/01/2014 16:10 4 501 ble_hci.h -23/01/2014 16:10 5 307 ble_l2cap.h -23/01/2014 16:10 2 773 ble_ranges.h -23/01/2014 16:10 9 173 ble_types.h -23/01/2014 16:10 2 644 nrf_error.h -23/01/2014 16:10 1 118 nrf_error_sdm.h -23/01/2014 16:10 1 917 nrf_error_soc.h -23/01/2014 16:10 7 325 nrf_sdm.h -23/01/2014 16:10 26 341 nrf_soc.h -23/01/2014 16:10 967 nrf_svc.h -23/01/2014 16:10 1 693 softdevice_assert.h - 17 fichier(s) 202 134 octets - - Répertoire de C:\Shared\Dropbox\microBuilder\Code\mbed\nRF51822_ARM\mbed_bleapi\hw\nRF51822n\nordic\nrf-sdk\sd_common - -23/01/2014 16:10 <REP> . -23/01/2014 16:10 <REP> .. -23/01/2014 16:10 3 205 ant_stack_handler_types.h -23/01/2014 16:10 2 887 ble_stack_handler_types.h -23/01/2014 16:10 8 784 softdevice_handler.h - 3 fichier(s) 14 876 octets - - Total des fichiers listés : - 179 fichier(s) 2 171 223 octets - 53 Rép(s) 47 448 313 856 octets libres
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_ans_c.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,348 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_ans_c Alert Notification Service Client
- * @{
- * @ingroup ble_sdk_srv
- * @brief Alert Notification module.
- *
- * @details This module implements the Alert Notification Client according to the
- * Alert Notification Profile.
- *
- * @note The application must propagate BLE stack events to the Alert Notification Client module
- * by calling ble_ans_c_on_ble_evt() from the from the @ref ble_stack_handler callback.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-#ifndef BLE_ANS_C_H__
-#define BLE_ANS_C_H__
-
-#include "ble.h"
-#include "ble_gatts.h"
-#include "ble_types.h"
-#include "ble_bondmngr.h"
-
-#define ANS_NB_OF_CHARACTERISTICS 5 /**< Number of characteristics as defined by Alert Notification Service specification. */
-#define ANS_NB_OF_SERVICES 1 /**< Number of services supported in one central. */
-#define INVALID_SERVICE_HANDLE_BASE 0xF0 /**< Base for indicating invalid service handle. */
-#define INVALID_SERVICE_HANDLE (INVALID_SERVICE_HANDLE_BASE + 0x0F) /**< Indication that the current service handle is invalid. */
-#define INVALID_SERVICE_HANDLE_DISC (INVALID_SERVICE_HANDLE_BASE + 0x0E) /**< Indication that the current service handle is invalid but the service has been discovered. */
-#define BLE_ANS_INVALID_HANDLE 0xFF /**< Indication that the current service handle is invalid. */
-
-// Forward declaration of the ble_ans_c_t type.
-typedef struct ble_ans_c_s ble_ans_c_t;
-
-/** Alerts types as defined in the alert category id; UUID: 0x2A43. */
-typedef enum
-{
- ANS_TYPE_SIMPLE_ALERT = 0, /**< General text alert or non-text alert.*/
- ANS_TYPE_EMAIL = 1, /**< Alert when email messages arrives.*/
- ANS_TYPE_NEWS = 2, /**< News feeds such as RSS, Atom.*/
- ANS_TYPE_NOTIFICATION_CALL = 3, /**< Incoming call.*/
- ANS_TYPE_MISSED_CALL = 4, /**< Missed call.*/
- ANS_TYPE_SMS_MMS = 5, /**< SMS/MMS message arrives.*/
- ANS_TYPE_VOICE_MAIL = 6, /**< Voice mail.*/
- ANS_TYPE_SCHEDULE = 7, /**< Alert occurred on calendar, planner.*/
- ANS_TYPE_HIGH_PRIORITIZED_ALERT = 8, /**< Alert that should be handled as high priority.*/
- ANS_TYPE_INSTANT_MESSAGE = 9, /**< Alert for incoming instant messages.*/
- ANS_TYPE_ALL_ALERTS = 0xFF /**< Identifies All Alerts. */
-} ble_ans_category_id_t;
-
-/** Alerts notification control point commands as defined in the Alert Notification Specification;
- * UUID: 0x2A44.
- */
-typedef enum
-{
- ANS_ENABLE_NEW_INCOMING_ALERT_NOTIFICATION = 0, /**< Enable New Incoming Alert Notification.*/
- ANS_ENABLE_UNREAD_CATEGORY_STATUS_NOTIFICATION = 1, /**< Enable Unread Category Status Notification.*/
- ANS_DISABLE_NEW_INCOMING_ALERT_NOTIFICATION = 2, /**< Disable New Incoming Alert Notification.*/
- ANS_DISABLE_UNREAD_CATEGORY_STATUS_NOTIFICATION = 3, /**< Disable Unread Category Status Notification.*/
- ANS_NOTIFY_NEW_INCOMING_ALERT_IMMEDIATELY = 4, /**< Notify New Incoming Alert immediately.*/
- ANS_NOTIFY_UNREAD_CATEGORY_STATUS_IMMEDIATELY = 5, /**< Notify Unread Category Status immediately.*/
-} ble_ans_command_id_t;
-
-/**@brief Alert Notification Event types that are passed from client to application on an event. */
-typedef enum
-{
- BLE_ANS_C_EVT_DISCOVER_COMPLETE, /**< A successful connection has been established and the characteristics of the server has been fetched. */
- BLE_ANS_C_EVT_DISCOVER_FAILED, /**< It was not possible to discover service or characteristics of the connected peer. */
- BLE_ANS_C_EVT_RECONNECT, /**< A re-connection to a known and previously discovered central has occurred. */
- BLE_ANS_C_EVT_DISCONN_COMPLETE, /**< The connection has been taken down. */
- BLE_ANS_C_EVT_NOTIFICATION, /**< A valid Alert Notification has been received from the server.*/
- BLE_ANS_C_EVT_READ_RESP, /**< A read response has been received from the server.*/
- BLE_ANS_C_EVT_WRITE_RESP /**< A write response has been received from the server.*/
-} ble_ans_c_evt_type_t;
-
-/**@brief Alert Notification Control Point structure. */
-typedef struct
-{
- ble_ans_command_id_t command; /**< The command to be written to the control point, see @ref ble_ans_command_id_t. */
- ble_ans_category_id_t category; /**< The category for the control point for which the command applies, see @ref ble_ans_category_id_t. */
-} ble_ans_control_point_t;
-
-/**@brief Alert Notification Setting structure containing the supported alerts in the service.
- *
- *@details
- * The structure contains bit fields describing which alerts that are supported:
- * 0 = Unsupported
- * 1 = Supported
- */
-typedef struct
-{
- uint8_t ans_simple_alert_support : 1; /**< Support for General text alert or non-text alert.*/
- uint8_t ans_email_support : 1; /**< Support for Alert when email messages arrives.*/
- uint8_t ans_news_support : 1; /**< Support for News feeds such as RSS, Atom.*/
- uint8_t ans_notification_call_support : 1; /**< Support for Incoming call.*/
- uint8_t ans_missed_call_support : 1; /**< Support for Missed call.*/
- uint8_t ans_sms_mms_support : 1; /**< Support for SMS/MMS message arrives.*/
- uint8_t ans_voice_mail_support : 1; /**< Support for Voice mail.*/
- uint8_t ans_schedule_support : 1; /**< Support for Alert occurred on calendar, planner.*/
- uint8_t ans_high_prioritized_alert_support : 1; /**< Support for Alert that should be handled as high priority.*/
- uint8_t ans_instant_message_support : 1; /**< Support for Alert for incoming instant messages.*/
- uint8_t reserved : 6; /**< Reserved for future use. */
-} ble_ans_alert_settings_t;
-
-/**@brief Alert Notification structure
- */
-typedef struct
-{
- uint8_t alert_category; /**< Alert category to which this alert belongs.*/
- uint8_t alert_category_count; /**< Number of alerts in the category. */
- uint32_t alert_msg_length; /**< Length of optional text message send by the server. */
- uint8_t * p_alert_msg_buf; /**< Pointer to buffer containing the optional text message. */
-} ble_ans_alert_notification_t;
-
-/**@brief Alert Notification Event structure
- *
- * @details The structure contains the event that should be handled, as well as
- * additional information.
- */
-typedef struct
-{
- ble_ans_c_evt_type_t evt_type; /**< Type of event. */
- ble_uuid_t uuid; /**< UUID of the event in case of an alert or notification. */
- union
- {
- ble_ans_alert_settings_t settings; /**< Setting returned from server on read request. */
- ble_ans_alert_notification_t alert; /**< Alert Notification data sent by the server. */
- uint32_t error_code; /**< Additional status/error code if the event was caused by a stack error or gatt status, e.g. during service discovery. */
- } data;
-} ble_ans_c_evt_t;
-
-/**@brief Alert Notification event handler type. */
-typedef void (*ble_ans_c_evt_handler_t) (ble_ans_c_evt_t * p_evt);
-
-/**@brief Alert Notification structure. This contains various status information for the client. */
-typedef struct ble_ans_c_s
-{
- ble_ans_c_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Alert Notification Client Application. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- int8_t central_handle; /**< Handle for the currently connected central if we have a bond in the bond manager. */
- uint8_t service_handle; /**< Handle to the service in the database to use for this instance. */
- uint32_t message_buffer_size; /**< Size of message buffer to hold the additional text messages received on notifications. */
- uint8_t * p_message_buffer; /**< Pointer to the buffer to be used for additional text message handling. */
-} ble_ans_c_t;
-
-/**@brief Alert Notification init structure. This contains all options and data needed for
- * initialization of the client.*/
-typedef struct
-{
- ble_ans_c_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Battery Service. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- uint32_t message_buffer_size; /**< Size of buffer to handle messages. */
- uint8_t * p_message_buffer; /**< Pointer to buffer for passing messages. */
-} ble_ans_c_init_t;
-
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Alert Notification Client.
- *
- * @param[in] p_ans Alert Notification Client structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_ans_c_on_ble_evt(ble_ans_c_t * p_ans, const ble_evt_t * p_ble_evt);
-
-
-/**@brief Function for handling the Alert Notification Client - Bond Manager stack event.
- *
- * @details Handles all events from the Bond Manager of interest to the Alert Notification Client.
- * The Alert Notification Client will use the events of re-connection to existing central
- * and creation of new bonds for handling of service discovery and writing of the Alert
- * Notification Control Point for re-send of New Alert and Unread Alert notifications.
- *
- * @param[in] p_ans Alert Notification Client structure.
- * @param[in] p_bond_mgmr_evt Event received from the Bond Manager.
- */
-void ble_ans_c_on_bondmgmr_evt(ble_ans_c_t * p_ans, const ble_bondmngr_evt_t * p_bond_mgmr_evt);
-
-
-/**@brief Function for initializing the Alert Notification Client.
- *
- * @param[out] p_ans Alert Notification Client structure. This structure will have to be
- * supplied by the application. It will be initialized by this function,
- * and will later be used to identify this particular client instance.
- * @param[in] p_ans_init Information needed to initialize the client.
- *
- * @return NRF_SUCCESS on successful initialization of client, otherwise an error code.
- */
-uint32_t ble_ans_c_init(ble_ans_c_t * p_ans, const ble_ans_c_init_t * p_ans_init);
-
-
-/**@brief Function for writing the to CCCD to enable new alert notifications from the Alert Notification Service.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by
- * the application. It identifies the particular client instance to use.
- *
- * @return NRF_SUCCESS on successful writing of the CCCD, otherwise an error code.
- */
-uint32_t ble_ans_c_enable_notif_new_alert(const ble_ans_c_t * p_ans);
-
-
-/**@brief Function for writing to the CCCD to enable unread alert notifications from the Alert Notification Service.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by
- * the application. It identifies the particular client instance to use.
- *
- * @return NRF_SUCCESS on successful writing of the CCCD, otherwise an error code.
- */
-uint32_t ble_ans_c_enable_notif_unread_alert(const ble_ans_c_t * p_ans);
-
-
-/**@brief Function for writing to the CCCD to disable new alert notifications from the Alert Notification Service.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by
- * the application. It identifies the particular client instance to use.
- *
- * @return NRF_SUCCESS on successful writing of the CCCD, otherwise an error code.
- */
-uint32_t ble_ans_c_disable_notif_new_alert(const ble_ans_c_t * p_ans);
-
-
-/**@brief Function for writing to the CCCD to disable unread alert notifications from the Alert Notification Service.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by
- * the application. It identifies the particular client instance to use.
- *
- * @return NRF_SUCCESS on successful writing of the CCCD, otherwise an error code.
- */
-uint32_t ble_ans_c_disable_notif_unread_alert(const ble_ans_c_t * p_ans);
-
-
-/**@brief Function for writing to the Alert Notification Control Point to specify alert notification behavior in the
- * Alert Notification Service on the Central.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be
- * supplied by the application. It identifies the particular client
- * instance to use.
- * @param[in] p_control_point Alert Notification Control Point structure. This structure
- * specifies the values to write to the Alert Notification Control
- * Point, UUID 0x2A44.
- *
- * @return NRF_SUCCESS on successful writing of the Control Point, otherwise an error code.
- */
-uint32_t ble_ans_c_control_point_write(const ble_ans_c_t * p_ans,
- const ble_ans_control_point_t * p_control_point);
-
-
-/**@brief Function for reading the Supported New Alert characteristic value of the service.
- * The value describes the alerts supported in the central.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by
- * the application. It identifies the particular client instance to use.
- *
- * @return NRF_SUCCESS on successful transmission of the read request, otherwise an error code.
- */
-uint32_t ble_ans_c_new_alert_read(const ble_ans_c_t * p_ans);
-
-
-/**@brief Function for reading the Supported Unread Alert characteristic value of the service.
- * The value describes the alerts supported in the central.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by
- * the application. It identifies the particular client instance to use.
- *
- * @return NRF_SUCCESS on successful transmission of the read request, otherwise an error code.
- */
-uint32_t ble_ans_c_unread_alert_read(const ble_ans_c_t * p_ans);
-
-
-/**@brief Function for requesting the peer to notify the New Alert characteristics immediately.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by
- * the application. It identifies the particular client instance to use.
- * @param[in] category The category ID for which the peer should notify the client.
- *
- * @return NRF_SUCCESS on successful transmission of the read request, otherwise an error code.
- */
-uint32_t ble_ans_c_new_alert_notify(const ble_ans_c_t * p_ans, ble_ans_category_id_t category);
-
-
-/**@brief Function for requesting the peer to notify the Unread Alert characteristics immediately.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by
- * the application. It identifies the particular client instance to use.
- * @param[in] category The category ID for which the peer should notify the client.
- *
- * @return NRF_SUCCESS on successful transmission of the read request, otherwise an error code.
- */
-uint32_t ble_ans_c_unread_alert_notify(const ble_ans_c_t * p_ans, ble_ans_category_id_t category);
-
-
-/**@brief Function for loading previous discovered service and characteristic handles for bonded centrals from
- * flash into RAM.
- *
- * @details Read the database of all discovered service and characteristic handles from flash.
- * If the flash does not contain any valid data, the array of discovered service handles in
- * RAM will be empty.
- *
- * @param[in] p_ans Alert Notification structure. This structure will have to be supplied by the
- * application. It identifies the particular client instance to use.
- *
- * @note Currently the Alert Notification Client uses only one page in flash.
- *
- * @return NRF_SUCCESS if all operations went successfully, an error_code otherwise.
- */
-uint32_t ble_ans_c_service_load(const ble_ans_c_t * p_ans);
-
-
-/**@brief Function for storing discovered service and characteristic handles for bonded centrals into flash memory.
- *
- * @details This function will erase the flash page (if the data to store
- * are diferent than the one already stored) and then write into flash. Those
- * operations could prevent the radio to run.
- *
- * @note Do not call this function while in a connection or when advertising. If you do, the
- * behavior is undefined.
- *
- * @return NRF_SUCCESS if all operations went successfully, an error_code otherwise.
- */
-uint32_t ble_ans_c_service_store(void);
-
-
-/**@brief Function for deleting the Alert Notification Client database from flash.
- *
- * @details After calling this function you should call ble_ans_c_init(...) to re-initialize
- * the RAM database.
- *
- * @return NRF_SUCCESS if all operations went successfully.
- */
-uint32_t ble_ans_c_service_delete(void);
-
-#endif // BLE_ANS_C_H__
-
-/** @} */
-
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_bas.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,133 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_bas Battery Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Battery Service module.
- *
- * @details This module implements the Battery Service with the Battery Level characteristic.
- * During initialization it adds the Battery Service and Battery Level characteristic
- * to the BLE stack database. Optionally it can also add a Report Reference descriptor
- * to the Battery Level characteristic (used when including the Battery Service in
- * the HID service).
- *
- * If specified, the module will support notification of the Battery Level characteristic
- * through the ble_bas_battery_level_update() function.
- * If an event handler is supplied by the application, the Battery Service will
- * generate Battery Service events to the application.
- *
- * @note The application must propagate BLE stack events to the Battery Service module by calling
- * ble_bas_on_ble_evt() from the from the @ref ble_stack_handler callback.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_BAS_H__
-#define BLE_BAS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-
-/**@brief Battery Service event type. */
-typedef enum
-{
- BLE_BAS_EVT_NOTIFICATION_ENABLED, /**< Battery value notification enabled event. */
- BLE_BAS_EVT_NOTIFICATION_DISABLED /**< Battery value notification disabled event. */
-} ble_bas_evt_type_t;
-
-/**@brief Battery Service event. */
-typedef struct
-{
- ble_bas_evt_type_t evt_type; /**< Type of event. */
-} ble_bas_evt_t;
-
-// Forward declaration of the ble_bas_t type.
-typedef struct ble_bas_s ble_bas_t;
-
-/**@brief Battery Service event handler type. */
-typedef void (*ble_bas_evt_handler_t) (ble_bas_t * p_bas, ble_bas_evt_t * p_evt);
-
-/**@brief Battery Service init structure. This contains all options and data needed for
- * initialization of the service.*/
-typedef struct
-{
- ble_bas_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Battery Service. */
- bool support_notification; /**< TRUE if notification of Battery Level measurement is supported. */
- ble_srv_report_ref_t * p_report_ref; /**< If not NULL, a Report Reference descriptor with the specified value will be added to the Battery Level characteristic */
- uint8_t initial_batt_level; /**< Initial battery level */
- ble_srv_cccd_security_mode_t battery_level_char_attr_md; /**< Initial security level for battery characteristics attribute */
- ble_gap_conn_sec_mode_t battery_level_report_read_perm; /**< Initial security level for battery report read attribute */
-} ble_bas_init_t;
-
-/**@brief Battery Service structure. This contains various status information for the service. */
-typedef struct ble_bas_s
-{
- ble_bas_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Battery Service. */
- uint16_t service_handle; /**< Handle of Battery Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t battery_level_handles; /**< Handles related to the Battery Level characteristic. */
- uint16_t report_ref_handle; /**< Handle of the Report Reference descriptor. */
- uint8_t battery_level_last; /**< Last Battery Level measurement passed to the Battery Service. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- bool is_notification_supported; /**< TRUE if notification of Battery Level is supported. */
-} ble_bas_t;
-
-/**@brief Function for initializing the Battery Service.
- *
- * @param[out] p_bas Battery Service structure. This structure will have to be supplied by
- * the application. It will be initialized by this function, and will later
- * be used to identify this particular service instance.
- * @param[in] p_bas_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_bas_init(ble_bas_t * p_bas, const ble_bas_init_t * p_bas_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Battery Service.
- *
- * @note For the requirements in the BAS specification to be fulfilled,
- * ble_bas_battery_level_update() must be called upon reconnection if the
- * battery level has changed while the service has been disconnected from a bonded
- * client.
- *
- * @param[in] p_bas Battery Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_bas_on_ble_evt(ble_bas_t * p_bas, ble_evt_t * p_ble_evt);
-
-/**@brief Function for updating the battery level.
- *
- * @details The application calls this function after having performed a battery measurement. If
- * notification has been enabled, the battery level characteristic is sent to the client.
- *
- * @note For the requirements in the BAS specification to be fulfilled,
- * this function must be called upon reconnection if the battery level has changed
- * while the service has been disconnected from a bonded client.
- *
- * @param[in] p_bas Battery Service structure.
- * @param[in] battery_level New battery measurement value (in percent of full capacity).
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_bas_battery_level_update(ble_bas_t * p_bas, uint8_t battery_level);
-
-#endif // BLE_BAS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_bps.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,161 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_bps Blood Pressure Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Blood Pressure Service module.
- *
- * @details This module implements the Blood Pressure Service.
- *
- * If an event handler is supplied by the application, the Blood Pressure
- * Service will generate Blood Pressure Service events to the application.
- *
- * @note The application must propagate BLE stack events to the Blood Pressure Service
- * module by calling ble_bps_on_ble_evt() from the from the @ref ble_stack_handler function.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_BPS_H__
-#define BLE_BPS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-#include "ble_date_time.h"
-
-// Blood Pressure Feature bits
-#define BLE_BPS_FEATURE_BODY_MOVEMENT_BIT (0x01 << 0) /**< Body Movement Detection Support bit. */
-#define BLE_BPS_FEATURE_CUFF_FIT_BIT (0x01 << 1) /**< Cuff Fit Detection Support bit. */
-#define BLE_BPS_FEATURE_IRREGULAR_PULSE_BIT (0x01 << 2) /**< Irregular Pulse Detection Support bit. */
-#define BLE_BPS_FEATURE_PULSE_RATE_RANGE_BIT (0x01 << 3) /**< Pulse Rate Range Detection Support bit. */
-#define BLE_BPS_FEATURE_MEASUREMENT_POSITION_BIT (0x01 << 4) /**< Measurement Position Detection Support bit. */
-#define BLE_BPS_FEATURE_MULTIPLE_BOND_BIT (0x01 << 5) /**< Multiple Bond Support bit. */
-
-/**@brief Blood Pressure Service event type. */
-typedef enum
-{
- BLE_BPS_EVT_INDICATION_ENABLED, /**< Blood Pressure value indication enabled event. */
- BLE_BPS_EVT_INDICATION_DISABLED, /**< Blood Pressure value indication disabled event. */
- BLE_BPS_EVT_INDICATION_CONFIRMED /**< Confirmation of a blood pressure measurement indication has been received. */
-} ble_bps_evt_type_t;
-
-/**@brief Blood Pressure Service event. */
-typedef struct
-{
- ble_bps_evt_type_t evt_type; /**< Type of event. */
-} ble_bps_evt_t;
-
-// Forward declaration of the ble_bps_t type.
-typedef struct ble_bps_s ble_bps_t;
-
-/**@brief Blood Pressure Service event handler type. */
-typedef void (*ble_bps_evt_handler_t) (ble_bps_t * p_bps, ble_bps_evt_t * p_evt);
-
-/**@brief SFLOAT format (IEEE-11073 16-bit FLOAT, defined as a 16-bit vlue with 12-bit mantissa and
- * 4-bit exponent. */
-typedef struct
-{
- int8_t exponent; /**< Base 10 exponent, only 4 bits */
- int16_t mantissa; /**< Mantissa, only 12 bits */
-} ieee_float16_t;
-
-/**@brief Blood Pressure Service init structure. This contains all options and data
- * needed for initialization of the service. */
-typedef struct
-{
- ble_bps_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Blood Pressure Service. */
- ble_srv_cccd_security_mode_t bps_meas_attr_md; /**< Initial security level for blood pressure measurement attribute */
- ble_srv_security_mode_t bps_feature_attr_md; /**< Initial security level for blood pressure feature attribute */
- uint16_t feature; /**< Initial value for blood pressure feature */
-} ble_bps_init_t;
-
-/**@brief Blood Pressure Service structure. This contains various status information for
- * the service. */
-typedef struct ble_bps_s
-{
- ble_bps_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Blood Pressure Service. */
- uint16_t service_handle; /**< Handle of Blood Pressure Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t meas_handles; /**< Handles related to the Blood Pressure Measurement characteristic. */
- ble_gatts_char_handles_t feature_handles; /**< Handles related to the Blood Pressure Feature characteristic. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- uint16_t feature; /**< Value of Blood Pressure feature. */
-} ble_bps_t;
-
-/**@brief Blood Pressure Service measurement structure. This contains a Blood Pressure
- * measurement. */
-typedef struct ble_bps_meas_s
-{
- bool blood_pressure_units_in_kpa; /**< Blood Pressure Units Flag, 0=mmHg, 1=kPa */
- bool time_stamp_present; /**< Time Stamp Flag, 0=not present, 1=present. */
- bool pulse_rate_present; /**< Pulse Rate Flag, 0=not present, 1=present. */
- bool user_id_present; /**< User ID Flag, 0=not present, 1=present. */
- bool measurement_status_present; /**< Measurement Status Flag, 0=not present, 1=present. */
- ieee_float16_t blood_pressure_systolic; /**< Blood Pressure Measurement Compound Value - Systolic. */
- ieee_float16_t blood_pressure_diastolic; /**< Blood Pressure Measurement Compound Value - Diastolic . */
- ieee_float16_t mean_arterial_pressure; /**< Blood Pressure Measurement Compound Value - Mean Arterial Pressure. */
- ble_date_time_t time_stamp; /**< Time Stamp. */
- ieee_float16_t pulse_rate; /**< Pulse Rate. */
- uint8_t user_id; /**< User ID. */
- uint16_t measurement_status; /**< Measurement Status. */
-} ble_bps_meas_t;
-
-/**@brief Function for initializing the Blood Pressure Service.
- *
- * @param[out] p_bps Blood Pressure Service structure. This structure will have to
- * be supplied by the application. It will be initialized by this function,
- * and will later be used to identify this particular service instance.
- * @param[in] p_bps_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_bps_init(ble_bps_t * p_bps, const ble_bps_init_t * p_bps_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Blood Pressure Service.
- *
- * @param[in] p_bps Blood Pressure Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_bps_on_ble_evt(ble_bps_t * p_bps, ble_evt_t * p_ble_evt);
-
-/**@brief Function for sending blood pressure measurement if indication has been enabled.
- *
- * @details The application calls this function after having performed a Blood Pressure
- * measurement. If indication has been enabled, the measurement data is encoded and
- * sent to the client.
- *
- * @param[in] p_bps Blood Pressure Service structure.
- * @param[in] p_bps_meas Pointer to new blood pressure measurement.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_bps_measurement_send(ble_bps_t * p_bps, ble_bps_meas_t * p_bps_meas);
-
-/**@brief Function for checking if indication of Blood Pressure Measurement is currently enabled.
- *
- * @param[in] p_bps Blood Pressure Service structure.
- * @param[out] p_indication_enabled TRUE if indication is enabled, FALSE otherwise.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_bps_is_indication_enabled(ble_bps_t * p_bps, bool * p_indication_enabled);
-
-#endif // BLE_BPS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_cscs.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,161 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_csc Cycling Speed and Cadence Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Cycling Speed and Cadence Service module.
- *
- * @details This module implements the Cycling Speed and Cadence Service. If enabled, notification
- * of the Cycling Speead and Candence Measurement is performed when the application
- * calls ble_cscs_measurement_send().
- *
- * To use this service, you need to provide the the supported features (@ref BLE_CSCS_FEATURES).
- * If you choose to support Wheel revolution data (feature bit @ref BLE_CSCS_FEATURE_WHEEL_REV_BIT),
- * you then need to support the 'setting of cumulative value' operation by the supporting the
- * Speed and Cadence Control Point (@ref ble_sdk_srv_sc_ctrlpt) by setting the @ref BLE_SRV_SC_CTRLPT_CUM_VAL_OP_SUPPORTED
- * bit of the ctrplt_supported_functions in the @ref ble_cscs_init_t structure.
- * If you want to support the 'start autocalibration' control point feature, you need, after the @ref BLE_SC_CTRLPT_EVT_START_CALIBRATION
- * has been received and the auto calibration is finished, to call the @ref ble_sc_ctrlpt_rsp_send to indicate that the operation is finished
- * and thus be able to receive new control point operations.
- * If you want to support the 'sensor location' related operation, you need to provide a list of supported location in the
- * @ref ble_cscs_init_t structure.
- *
- *
- * @note The application or the service using this module must propagate BLE stack events to the
- * Cycling Speead and Candence Service module by calling ble_cscs_on_ble_evt() from the
- * from the @ref ble_stack_handler function. This service will forward the event to the @ref ble_sdk_srv_sc_ctrlpt module.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_CSCS_H__
-#define BLE_CSCS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-#include "ble_sc_ctrlpt.h"
-#include "ble_sensor_location.h"
-
-/** @defgroup BLE_CSCS_FEATURES Cycling Speed and Cadence Service feature bits
- * @{ */
-#define BLE_CSCS_FEATURE_WHEEL_REV_BIT (0x01 << 0) /**< Wheel Revolution Data Supported bit. */
-#define BLE_CSCS_FEATURE_CRANK_REV_BIT (0x01 << 1) /**< Crank Revolution Data Supported bit. */
-#define BLE_CSCS_FEATURE_MULTIPLE_SENSORS_BIT (0x01 << 2) /**< Multiple Sensor Locations Supported bit. */
-/** @} */
-
-/**@brief Cycling Speed and Cadence Service event type. */
-typedef enum
-{
- BLE_CSCS_EVT_NOTIFICATION_ENABLED, /**< Cycling Speed and Cadence value notification enabled event. */
- BLE_CSCS_EVT_NOTIFICATION_DISABLED /**< Cycling Speed and Cadence value notification disabled event. */
-} ble_cscs_evt_type_t;
-
-/**@brief Cycling Speed and Cadence Service event. */
-typedef struct
-{
- ble_cscs_evt_type_t evt_type; /**< Type of event. */
-} ble_cscs_evt_t;
-
-// Forward declaration of the ble_csc_t type.
-typedef struct ble_cscs_s ble_cscs_t;
-
-/**@brief Cycling Speed and Cadence Service event handler type. */
-typedef void (*ble_cscs_evt_handler_t) (ble_cscs_t * p_cscs, ble_cscs_evt_t * p_evt);
-
-/**@brief Cycling Speed and Cadence Service init structure. This contains all options and data
-* needed for initialization of the service. */
-typedef struct
-{
- ble_cscs_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Cycling Speed and Cadence Service. */
- ble_srv_cccd_security_mode_t csc_meas_attr_md; /**< Initial security level for cycling speed and cadence measurement attribute */
- ble_srv_cccd_security_mode_t csc_ctrlpt_attr_md; /**< Initial security level for cycling speed and cadence control point attribute */
- ble_srv_security_mode_t csc_feature_attr_md; /**< Initial security level for feature attribute */
- uint16_t feature; /**< Initial value for features of sensor @ref BLE_CSCS_FEATURES. */
- uint8_t ctrplt_supported_functions; /**< Supported control point functionnalities see @ref BLE_SRV_SC_CTRLPT_SUPP_FUNC. */
- ble_sc_ctrlpt_evt_handler_t ctrlpt_evt_handler; /**< Event handler */
- ble_sensor_location_t *list_supported_locations; /**< List of supported sensor locations.*/
- uint8_t size_list_supported_locations; /**< Number of supported sensor locations in the list.*/
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- ble_sensor_location_t *sensor_location; /**< Initial Sensor Location, if NULL, sensor_location characteristic is not added*/
- ble_srv_cccd_security_mode_t csc_sensor_loc_attr_md; /**< Initial security level for sensor location attribute */
-} ble_cscs_init_t;
-
-/**@brief Cycling Speed and Cadence Service structure. This contains various status information for
- * the service. */
-typedef struct ble_cscs_s
-{
- ble_cscs_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Cycling Speed and Cadence Service. */
- uint16_t service_handle; /**< Handle of Cycling Speed and Cadence Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t meas_handles; /**< Handles related to the Cycling Speed and Cadence Measurement characteristic. */
- ble_gatts_char_handles_t feature_handles; /**< Handles related to the Cycling Speed and Cadence feature characteristic. */
- ble_gatts_char_handles_t sensor_loc_handles; /**< Handles related to the Cycling Speed and Cadence Sensor Location characteristic. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- uint16_t feature; /**< Bit mask of features available on sensor. */
- ble_sc_ctrlpt_t ctrl_pt; /**< data for speed and cadence control point */
-} ble_cscs_t;
-
-/**@brief Cycling Speed and Cadence Service measurement structure. This contains a Cycling Speed and
- * Cadence Service measurement. */
-typedef struct ble_cscs_meas_s
-{
- bool is_wheel_rev_data_present; /**< True if Wheel Revolution Data is present in the measurement. */
- bool is_crank_rev_data_present; /**< True if Crank Revolution Data is present in the measurement. */
- uint32_t cumulative_wheel_revs; /**< Cumulative Wheel Revolutions. */
- uint16_t last_wheel_event_time; /**< Last Wheel Event Time. */
- uint16_t cumulative_crank_revs; /**< Cumulative Crank Revolutions. */
- uint16_t last_crank_event_time; /**< Last Crank Event Time. */
-} ble_cscs_meas_t;
-
-/**@brief Function for initializing the Cycling Speed and Cadence Service.
- *
- * @param[out] p_cscs Cycling Speed and Cadence Service structure. This structure will have to
- * be supplied by the application. It will be initialized by this function,
- * and will later be used to identify this particular service instance.
- * @param[in] p_cscs_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_cscs_init(ble_cscs_t * p_cscs, const ble_cscs_init_t * p_cscs_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Cycling Speed and Cadence
- * Service.
- *
- * @param[in] p_cscs Cycling Speed and Cadence Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_cscs_on_ble_evt(ble_cscs_t * p_cscs, ble_evt_t * p_ble_evt);
-
-/**@brief Function for sending cycling speed and cadence measurement if notification has been enabled.
- *
- * @details The application calls this function after having performed a Cycling Speed and Cadence
- * Service measurement. If notification has been enabled, the measurement data is encoded
- * and sent to the client.
- *
- * @param[in] p_cscs Cycling Speed and Cadence Service structure.
- * @param[in] p_measurement Pointer to new cycling speed and cadence measurement.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_cscs_measurement_send(ble_cscs_t * p_cscs, ble_cscs_meas_t * p_measurement);
-
-#endif // BLE_CSCS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_dfu.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,234 +0,0 @@
-/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/**@file
- *
- * @defgroup ble_sdk_srv_dfu Device Firmware Update Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Device Firmware Update Service
- *
- * @details The Device Firmware Update (DFU) service is a GATT based service that can be used for
- * performing firmware updates over BLE. Note that this implementation uses vendor
- * specific UUIDs for service and characteristics and is intended to demonstrate the
- * firmware updates over BLE. Refer @ref dfu_ble_service_spec and @ref
- * dfu_ble_profile_spec for more information on the service and profile respectively.
- */
-
-#ifndef BLE_DFU_H__
-#define BLE_DFU_H__
-
-#include <stdint.h>
-#include "ble_gatts.h"
-#include "ble.h"
-#include "ble_srv_common.h"
-
-#define BLE_DFU_SERVICE_UUID 0x1530 /**< The UUID of the DFU Service. */
-#define BLE_DFU_PKT_CHAR_UUID 0x1532 /**< The UUID of the DFU Packet Characteristic. */
-#define BLE_DFU_CTRL_PT_UUID 0x1531 /**< The UUID of the DFU Control Point. */
-#define BLE_DFU_STATUS_REP_UUID 0x1533 /**< The UUID of the DFU Status Report Characteristic. */
-
-
-/**@brief DFU Event type.
- *
- * @details This enumeration contains the types of events that will be received from the DFU Service.
- */
-typedef enum
-{
- BLE_DFU_START, /**< The event indicating that the peer wants the application to prepare for a new firmware update. */
- BLE_DFU_RECEIVE_INIT_DATA, /**< The event indicating that the peer wants the application to prepare to receive init parameters. */
- BLE_DFU_RECEIVE_APP_DATA, /**< The event indicating that the peer wants the application to prepare to receive the new firmware image. */
- BLE_DFU_VALIDATE, /**< The event indicating that the peer wants the application to validate the newly received firmware image. */
- BLE_DFU_ACTIVATE_N_RESET, /**< The event indicating that the peer wants the application to undergo activate new firmware and restart with new valid application */
- BLE_DFU_SYS_RESET, /**< The event indicating that the peer wants the application to undergo a reset and start the currently valid application image.*/
- BLE_DFU_PKT_RCPT_NOTIF_ENABLED, /**< The event indicating that the peer has enabled packet receipt notifications. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify each time the number of packets indicated by num_of_pkts field in @ref ble_dfu_evt_t is received.*/
- BLE_DFU_PKT_RCPT_NOTIF_DISABLED, /**< The event indicating that the peer has disabled the packet receipt notifications.*/
- BLE_DFU_PACKET_WRITE, /**< The event indicating that the peer has written a value to the 'DFU Packet' characteristic. The data received from the peer will be present in the @ref ble_dfu_pkt_write element contained within @ref ble_dfu_evt_t.*/
- BLE_DFU_BYTES_RECEIVED_SEND /**< The event indicating that the peer is requesting for the number of bytes of firmware data last received by the application. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify in response to this event. */
-} ble_dfu_evt_type_t;
-
-/**@brief DFU Procedure type.
- *
- * @details This enumeration contains the types of DFU procedures.
- */
-typedef enum
-{
- BLE_DFU_START_PROCEDURE = 1, /**< DFU Start procedure.*/
- BLE_DFU_INIT_PROCEDURE = 2, /**< DFU Initialization procedure.*/
- BLE_DFU_RECEIVE_APP_PROCEDURE = 3, /**< Firmware receiving procedure.*/
- BLE_DFU_VALIDATE_PROCEDURE = 4, /**< Firmware image validation procedure .*/
- BLE_DFU_PKT_RCPT_REQ_PROCEDURE = 8 /**< Packet receipt notification request procedure. */
-} ble_dfu_procedure_t;
-
-/**@brief DFU Response value type.
- */
-typedef enum
-{
- BLE_DFU_RESP_VAL_SUCCESS = 1, /**< Success.*/
- BLE_DFU_RESP_VAL_INVALID_STATE, /**< Invalid state.*/
- BLE_DFU_RESP_VAL_NOT_SUPPORTED, /**< Operation not supported.*/
- BLE_DFU_RESP_VAL_DATA_SIZE, /**< Data size exceeds limit.*/
- BLE_DFU_RESP_VAL_CRC_ERROR, /**< CRC Error.*/
- BLE_DFU_RESP_VAL_OPER_FAILED /**< Operation failed.*/
-} ble_dfu_resp_val_t;
-
-/**@brief DFU Packet structure.
- *
- * @details This structure contains the value of the DFU Packet characteristic as written by the
- * peer and the length of the value written. It will be filled by the DFU Service when the
- * peer writes to the DFU Packet characteristic.
- */
-typedef struct
-{
- uint8_t len; /**< Length of the packet received. */
- uint8_t * p_data; /**< Pointer to the received packet. This will point to a word aligned memory location.*/
-} ble_dfu_pkt_write_t;
-
-/**@brief Packet receipt notification request structure.
- *
- * @details This structure contains the contents of the packet receipt notification request
- * sent by the DFU Controller.
- */
-typedef struct
-{
- uint16_t num_of_pkts; /**< The number of packets of firmware data to be received by application before sending the next Packet Receipt Notification to the peer. */
-} ble_pkt_rcpt_notif_req_t;
-
-/**@brief DFU Event structure.
- *
- * @details This structure contains the event generated by the DFU Service based on the data
- * received from the peer.
- */
-typedef struct
-{
- ble_dfu_evt_type_t ble_dfu_evt_type; /**< Type of the event.*/
- union
- {
- ble_dfu_pkt_write_t ble_dfu_pkt_write; /**< The DFU packet received. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PACKET_WRITE.*/
- ble_pkt_rcpt_notif_req_t pkt_rcpt_notif_req; /**< Packet receipt notification request. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PKT_RCPT_NOTIF_ENABLED.*/
- } evt;
-} ble_dfu_evt_t;
-
-// Forward declaration of the ble_dfu_t type.
-typedef struct ble_dfu_s ble_dfu_t;
-
-/**@brief DFU Service event handler type. */
-typedef void (*ble_dfu_evt_handler_t) (ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt);
-
-/**@brief DFU service structure.
- *
- * @details This structure contains status information related to the service.
- */
-typedef struct ble_dfu_s
-{
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the S110 SoftDevice). This will be BLE_CONN_HANDLE_INVALID when not in a connection. */
- uint16_t service_handle; /**< Handle of DFU Service (as provided by the S110 SoftDevice). */
- uint8_t uuid_type; /**< UUID type assigned for DFU Service by the S110 SoftDevice. */
- ble_gatts_char_handles_t dfu_pkt_handles; /**< Handles related to the DFU Packet characteristic. */
- ble_gatts_char_handles_t dfu_ctrl_pt_handles; /**< Handles related to the DFU Control Point characteristic. */
- ble_gatts_char_handles_t dfu_status_rep_handles; /**< Handles related to the DFU Status Report characteristic. */
- ble_dfu_evt_handler_t evt_handler; /**< The event handler to be called when an event is to be sent to the application.*/
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
-} ble_dfu_t;
-
-/**@brief DFU service initialization structure.
- *
- * @details This structure contains the initialization information for the DFU Service. The
- * application needs to fill this structure and pass it to the DFU Service using the
- * @ref ble_dfu_init function.
- */
-typedef struct
-{
- ble_dfu_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Device Firmware Update Service. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
-} ble_dfu_init_t;
-
-/**@brief Function for handling a BLE event.
- *
- * @details The DFU service expects the application to call this function each time an event
- * is received from the S110 SoftDevice. This function processes the event, if it is
- * relevant for the DFU service and calls the DFU event handler of the application if
- * necessary.
- *
- * @param[in] p_dfu Pointer to the DFU service structure.
- * @param[in] p_ble_evt Pointer to the event received from S110 SoftDevice.
- */
-void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt);
-
-/**@brief Function for initializing the DFU service.
- *
- * @param[out] p_dfu Device Firmware Update service structure. This structure will have to be
- * supplied by the application. It will be initialized by this function,
- * and will later be used to identify the service instance.
- * @param[in] p_dfu_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS if the DFU service and its characteristics were successfully added to the
- * S110 SoftDevice. Otherwise an error code.
- * This function returns NRF_ERROR_NULL if the value of evt_handler in p_dfu_init
- * structure provided is NULL or if the pointers supplied as input are NULL.
- */
-uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init);
-
-/**@brief Function for sending response to a control point command.
- *
- * @details This function will encode a DFU Control Point response using the given input
- * parameters and will send a notification of the same to the peer.
- *
- * @param[in] p_dfu Pointer to the DFU service structure.
- * @param[in] dfu_proc Procedure for which this response is to be sent.
- * @param[in] resp_val Response value.
- *
- * @return NRF_SUCCESS if the DFU Service has successfully requested the S110 SoftDevice to
- * send the notification. Otherwise an error code.
- * This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
- * peer or if the DFU service is not initialized or if the notification of the DFU
- * Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
- * if the pointer p_dfu is NULL.
- */
-uint32_t ble_dfu_response_send(ble_dfu_t * p_dfu,
- ble_dfu_procedure_t dfu_proc,
- ble_dfu_resp_val_t resp_val);
-
-/**@brief Function for notifying the peer about the number of bytes of firmware data received.
- *
- * @param[in] p_dfu Pointer to the DFU service structure.
- * @param[in] num_of_firmware_bytes_rcvd Number of bytes.
- *
- * @return NRF_SUCCESS if the DFU Service has successfully requested the S110 SoftDevice to send
- * the notification. Otherwise an error code.
- * This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
- * peer or if the DFU service is not initialized or if the notification of the DFU
- * Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
- * if the pointer p_dfu is NULL.
- */
-uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd);
-
-/**@brief Function for sending Packet Receipt Notification to the peer.
- *
- * This function will encode the number of bytes received as input parameter into a
- * notification of the control point characteristic and send it to the peer.
- *
- * @param[in] p_dfu Pointer to the DFU service structure.
- * @param[in] num_of_firmware_bytes_rcvd Number of bytes of firmware image received.
- *
- * @return NRF_SUCCESS if the DFU Service has successfully requested the S110 SoftDevice to send
- * the notification. Otherwise an error code.
- * This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
- * peer or if the DFU service is not initialized or if the notification of the DFU
- * Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
- * if the pointer p_dfu is NULL.
- */
-uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd);
-
-#endif // BLE_DFU_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_dis.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,95 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_dis Device Information Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Device Information Service module.
- *
- * @details This module implements the Device Information Service.
- * During initialization it adds the Device Information Service to the BLE stack database.
- * It then encodes the supplied information, and adds the curresponding characteristics.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_DIS_H__
-#define BLE_DIS_H__
-
-#include <stdint.h>
-#include "ble_srv_common.h"
-
-// Vendor ID Source values
-#define BLE_DIS_VENDOR_ID_SRC_BLUETOOTH_SIG 1 /**< Vendor ID assigned by Bluetooth SIG. */
-#define BLE_DIS_VENDOR_ID_SRC_USB_IMPL_FORUM 2 /**< Vendor ID assigned by USB Implementer's Forum. */
-
-/**@brief System ID parameters */
-typedef struct
-{
- uint64_t manufacturer_id; /**< Manufacturer ID. Only 5 LSOs shall be used. */
- uint32_t organizationally_unique_id; /**< Organizationally unique ID. Only 3 LSOs shall be used. */
-} ble_dis_sys_id_t;
-
-/**@brief IEEE 11073-20601 Regulatory Certification Data List Structure */
-typedef struct
-{
- uint8_t * p_list; /**< Pointer the byte array containing the encoded opaque structure based on IEEE 11073-20601 specification. */
- uint8_t list_len; /**< Length of the byte array. */
-} ble_dis_reg_cert_data_list_t;
-
-/**@brief PnP ID parameters */
-typedef struct
-{
- uint8_t vendor_id_source; /**< Vendor ID Source. see @ref DIS_VENDOR_ID_SRC_VALUES. */
- uint16_t vendor_id; /**< Vendor ID. */
- uint16_t product_id; /**< Product ID. */
- uint16_t product_version; /**< Product Version. */
-} ble_dis_pnp_id_t;
-
-/**@brief Device Information Service init structure. This contains all possible characteristics
- * needed for initialization of the service.
- */
-typedef struct
-{
- ble_srv_utf8_str_t manufact_name_str; /**< Manufacturer Name String. */
- ble_srv_utf8_str_t model_num_str; /**< Model Number String. */
- ble_srv_utf8_str_t serial_num_str; /**< Serial Number String. */
- ble_srv_utf8_str_t hw_rev_str; /**< Hardware Revision String. */
- ble_srv_utf8_str_t fw_rev_str; /**< Firmware Revision String. */
- ble_srv_utf8_str_t sw_rev_str; /**< Software Revision String. */
- ble_dis_sys_id_t * p_sys_id; /**< System ID. The helper function @ref dis_sys_id_encode can be used to encode the value of this characteristic. */
- ble_dis_reg_cert_data_list_t * p_reg_cert_data_list; /**< IEEE 11073-20601 Regulatory Certification Data List. */
- ble_dis_pnp_id_t * p_pnp_id; /**< PnP ID. The helper function @ref dis_pnp_id_encode can be used to encode the value of this characteristic. */
- ble_srv_security_mode_t dis_attr_md; /**< Initial Security Setting for Device Information Characteristics. */
-} ble_dis_init_t;
-
-/**@brief Function for initializing the Device Information Service.
- *
- * @details This call allows the application to initialize the device information service.
- * It adds the DIS service and DIS characteristics to the database, using the initial
- * values supplied through the p_dis_init parameter. Characteristics which are not to be
- * added, shall be set to NULL in p_dis_init.
- *
- * @param[in] p_dis_init The structure containing the values of characteristics needed by the
- * service.
- *
- * @return NRF_SUCCESS on successful initialization of service.
- */
-uint32_t ble_dis_init(const ble_dis_init_t * p_dis_init);
-
-#endif // BLE_DIS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_gls.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,265 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_gls Glucose Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Glucose Service module.
- *
- * @details This module implements the Glucose Service.
- *
- * @note The application must propagate BLE stack events to the Glucose Service module by calling
- * ble_gls_on_ble_evt() from the from the @ref ble_stack_handler callback.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_GLS_H__
-#define BLE_GLS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-#include "ble_date_time.h"
-
-/**@brief Glucose feature */
-#define BLE_GLS_FEATURE_LOW_BATT 0x0001 /**< Low Battery Detection During Measurement Supported */
-#define BLE_GLS_FEATURE_MALFUNC 0x0002 /**< Sensor Malfunction Detection Supported */
-#define BLE_GLS_FEATURE_SAMPLE_SIZE 0x0004 /**< Sensor Sample Size Supported */
-#define BLE_GLS_FEATURE_INSERT_ERR 0x0008 /**< Sensor Strip Insertion Error Detection Supported */
-#define BLE_GLS_FEATURE_TYPE_ERR 0x0010 /**< Sensor Strip Type Error Detection Supported */
-#define BLE_GLS_FEATURE_RES_HIGH_LOW 0x0020 /**< Sensor Result High-Low Detection Supported */
-#define BLE_GLS_FEATURE_TEMP_HIGH_LOW 0x0040 /**< Sensor Temperature High-Low Detection Supported */
-#define BLE_GLS_FEATURE_READ_INT 0x0080 /**< Sensor Read Interrupt Detection Supported */
-#define BLE_GLS_FEATURE_GENERAL_FAULT 0x0010 /**< General Device Fault Supported */
-#define BLE_GLS_FEATURE_TIME_FAULT 0x0020 /**< Time Fault Supported */
-#define BLE_GLS_FEATURE_MULTI_BOND 0x0040 /**< Multiple Bond Supported */
-
-/**@brief Glucose measurement flags */
-#define BLE_GLS_MEAS_FLAG_TIME_OFFSET 0x01 /**< Time Offset Present */
-#define BLE_GLS_MEAS_FLAG_CONC_TYPE_LOC 0x02 /**< Glucose Concentration, Type, and Sample Location Present */
-#define BLE_GLS_MEAS_FLAG_UNITS_KG_L 0x00 /**< Glucose Concentration Units kg/L */
-#define BLE_GLS_MEAS_FLAG_UNITS_MOL_L 0x04 /**< Glucose Concentration Units mol/L */
-#define BLE_GLS_MEAS_FLAG_SENSOR_STATUS 0x08 /**< Sensor Status Annunciation Present */
-#define BLE_GLS_MEAS_FLAG_CONTEXT_INFO 0x10 /**< Context Information Follows */
-
-/**@brief Glucose measurement type */
-#define BLE_GLS_MEAS_TYPE_CAP_BLOOD 1 /**< Capillary whole blood */
-#define BLE_GLS_MEAS_TYPE_CAP_PLASMA 2 /**< Capillary plasma */
-#define BLE_GLS_MEAS_TYPE_VEN_BLOOD 3 /**< Venous whole blood */
-#define BLE_GLS_MEAS_TYPE_VEN_PLASMA 4 /**< Venous plasma */
-#define BLE_GLS_MEAS_TYPE_ART_BLOOD 5 /**< Arterial whole blood */
-#define BLE_GLS_MEAS_TYPE_ART_PLASMA 6 /**< Arterial plasma */
-#define BLE_GLS_MEAS_TYPE_UNDET_BLOOD 7 /**< Undetermined whole blood */
-#define BLE_GLS_MEAS_TYPE_UNDET_PLASMA 8 /**< Undetermined plasma */
-#define BLE_GLS_MEAS_TYPE_FLUID 9 /**< Interstitial fluid (ISF) */
-#define BLE_GLS_MEAS_TYPE_CONTROL 10 /**< Control solution */
-
-/**@brief Glucose measurement location */
-#define BLE_GLS_MEAS_LOC_FINGER 1 /**< Finger */
-#define BLE_GLS_MEAS_LOC_AST 2 /**< Alternate Site Test (AST) */
-#define BLE_GLS_MEAS_LOC_EAR 3 /**< Earlobe */
-#define BLE_GLS_MEAS_LOC_CONTROL 4 /**< Control solution */
-#define BLE_GLS_MEAS_LOC_NOT_AVAIL 15 /**< Sample Location value not available */
-
-/**@brief Glucose sensor status annunciation */
-#define BLE_GLS_MEAS_STATUS_BATT_LOW 0x0001 /**< Device battery low at time of measurement */
-#define BLE_GLS_MEAS_STATUS_SENSOR_FAULT 0x0002 /**< Sensor malfunction or faulting at time of measurement */
-#define BLE_GLS_MEAS_STATUS_SAMPLE_SIZE 0x0004 /**< Sample size for blood or control solution insufficient at time of measurement */
-#define BLE_GLS_MEAS_STATUS_STRIP_INSERT 0x0008 /**< Strip insertion error */
-#define BLE_GLS_MEAS_STATUS_STRIP_TYPE 0x0010 /**< Strip type incorrect for device */
-#define BLE_GLS_MEAS_STATUS_RESULT_HIGH 0x0020 /**< Sensor result higher than the device can process */
-#define BLE_GLS_MEAS_STATUS_RESULT_LOW 0x0040 /**< Sensor result lower than the device can process */
-#define BLE_GLS_MEAS_STATUS_TEMP_HIGH 0x0080 /**< Sensor temperature too high for valid test/result at time of measurement */
-#define BLE_GLS_MEAS_STATUS_TEMP_LOW 0x0100 /**< Sensor temperature too low for valid test/result at time of measurement */
-#define BLE_GLS_MEAS_STATUS_STRIP_PULL 0x0200 /**< Sensor read interrupted because strip was pulled too soon at time of measurement */
-#define BLE_GLS_MEAS_STATUS_GENERAL_FAULT 0x0400 /**< General device fault has occurred in the sensor */
-#define BLE_GLS_MEAS_STATUS_TIME_FAULT 0x0800 /**< Time fault has occurred in the sensor and time may be inaccurate */
-
-/**@brief Glucose measurement context flags */
-#define BLE_GLS_CONTEXT_FLAG_CARB 0x01 /**< Carbohydrate id and carbohydrate present */
-#define BLE_GLS_CONTEXT_FLAG_MEAL 0x02 /**< Meal present */
-#define BLE_GLS_CONTEXT_FLAG_TESTER 0x04 /**< Tester-health present */
-#define BLE_GLS_CONTEXT_FLAG_EXERCISE 0x08 /**< Exercise duration and exercise intensity present */
-#define BLE_GLS_CONTEXT_FLAG_MED 0x10 /**< Medication ID and medication present */
-#define BLE_GLS_CONTEXT_FLAG_MED_KG 0x00 /**< Medication value units, kilograms */
-#define BLE_GLS_CONTEXT_FLAG_MED_L 0x20 /**< Medication value units, liters */
-#define BLE_GLS_CONTEXT_FLAG_HBA1C 0x40 /**< Hba1c present */
-#define BLE_GLS_CONTEXT_FLAG_EXT 0x80 /**< Extended flags present */
-
-/**@brief Glucose measurement context carbohydrate ID */
-#define BLE_GLS_CONTEXT_CARB_BREAKFAST 1 /**< Breakfast */
-#define BLE_GLS_CONTEXT_CARB_LUNCH 2 /**< Lunch */
-#define BLE_GLS_CONTEXT_CARB_DINNER 3 /**< Dinner */
-#define BLE_GLS_CONTEXT_CARB_SNACK 4 /**< Snack */
-#define BLE_GLS_CONTEXT_CARB_DRINK 5 /**< Drink */
-#define BLE_GLS_CONTEXT_CARB_SUPPER 6 /**< Supper */
-#define BLE_GLS_CONTEXT_CARB_BRUNCH 7 /**< Brunch */
-
-/**@brief Glucose measurement context meal */
-#define BLE_GLS_CONTEXT_MEAL_PREPRANDIAL 1 /**< Preprandial (before meal) */
-#define BLE_GLS_CONTEXT_MEAL_POSTPRANDIAL 2 /**< Postprandial (after meal) */
-#define BLE_GLS_CONTEXT_MEAL_FASTING 3 /**< Fasting */
-#define BLE_GLS_CONTEXT_MEAL_CASUAL 4 /**< Casual (snacks, drinks, etc.) */
-#define BLE_GLS_CONTEXT_MEAL_BEDTIME 5 /**< Bedtime */
-
-/**@brief Glucose measurement context tester */
-#define BLE_GLS_CONTEXT_TESTER_SELF 1 /**< Self */
-#define BLE_GLS_CONTEXT_TESTER_PRO 2 /**< Health care professional */
-#define BLE_GLS_CONTEXT_TESTER_LAB 3 /**< Lab test */
-#define BLE_GLS_CONTEXT_TESTER_NOT_AVAIL 15 /**< Tester value not available */
-
-/**@brief Glucose measurement context health */
-#define BLE_GLS_CONTEXT_HEALTH_MINOR 1 /**< Minor health issues */
-#define BLE_GLS_CONTEXT_HEALTH_MAJOR 2 /**< Major health issues */
-#define BLE_GLS_CONTEXT_HEALTH_MENSES 3 /**< During menses */
-#define BLE_GLS_CONTEXT_HEALTH_STRESS 4 /**< Under stress */
-#define BLE_GLS_CONTEXT_HEALTH_NONE 5 /**< No health issues */
-#define BLE_GLS_CONTEXT_HEALTH_NOT_AVAIL 15 /**< Health value not available */
-
-/**@brief Glucose measurement context medication ID */
-#define BLE_GLS_CONTEXT_MED_RAPID 1 /**< Rapid acting insulin */
-#define BLE_GLS_CONTEXT_MED_SHORT 2 /**< Short acting insulin */
-#define BLE_GLS_CONTEXT_MED_INTERMED 3 /**< Intermediate acting insulin */
-#define BLE_GLS_CONTEXT_MED_LONG 4 /**< Long acting insulin */
-#define BLE_GLS_CONTEXT_MED_PREMIX 5 /**< Pre-mixed insulin */
-
-/**@brief SFLOAT format (IEEE-11073 16-bit FLOAT, meaning 4 bits for exponent (base 10) and 12 bits mantissa) */
-typedef struct
-{
- int8_t exponent; /**< Base 10 exponent, should be using only 4 bits */
- int16_t mantissa; /**< Mantissa, should be using only 12 bits */
-} sfloat_t;
-
-/**@brief Glucose Service event type. */
-typedef enum
-{
- BLE_GLS_EVT_NOTIFICATION_ENABLED, /**< Glucose value notification enabled event. */
- BLE_GLS_EVT_NOTIFICATION_DISABLED /**< Glucose value notification disabled event. */
-} ble_gls_evt_type_t;
-
-/**@brief Glucose Service event. */
-typedef struct
-{
- ble_gls_evt_type_t evt_type; /**< Type of event. */
-} ble_gls_evt_t;
-
-// Forward declaration of the ble_gls_t type.
-typedef struct ble_gls_s ble_gls_t;
-
-/**@brief Glucose Service event handler type. */
-typedef void (*ble_gls_evt_handler_t) (ble_gls_t * p_gls, ble_gls_evt_t * p_evt);
-
-/**@brief Glucose Measurement structure. This contains glucose measurement value. */
-typedef struct
-{
- uint8_t flags; /**< Flags */
- uint16_t sequence_number; /**< Sequence number */
- ble_date_time_t base_time; /**< Time stamp */
- int16_t time_offset; /**< Time offset */
- sfloat_t glucose_concentration; /**< Glucose concentration */
- uint8_t type; /**< Type */
- uint8_t sample_location; /**< Sample location */
- uint16_t sensor_status_annunciation; /**< Sensor status annunciation */
-} ble_gls_meas_t;
-
-/**@brief Glucose measurement context structure */
-typedef struct
-{
- uint8_t flags; /**< Flags */
- uint8_t extended_flags; /**< Extended Flags */
- uint8_t carbohydrate_id; /**< Carbohydrate ID */
- sfloat_t carbohydrate; /**< Carbohydrate */
- uint8_t meal; /**< Meal */
- uint8_t tester_and_health; /**< Tester and health */
- uint16_t exercise_duration; /**< Exercise Duration */
- uint8_t exercise_intensity; /**< Exercise Intensity */
- uint8_t medication_id; /**< Medication ID */
- sfloat_t medication; /**< Medication */
- uint16_t hba1c; /**< HbA1c */
-} ble_gls_meas_context_t;
-
-/**@brief Glucose measurement record */
-typedef struct
-{
- ble_gls_meas_t meas; /**< Glucose measurement */
- ble_gls_meas_context_t context; /**< Glucose measurement context */
-} ble_gls_rec_t;
-
-/**@brief Glucose Service init structure. This contains all options and data needed for
- * initialization of the service. */
-typedef struct
-{
- ble_gls_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Glucose Service. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- uint16_t feature; /**< Glucose Feature value indicating supported features. */
- bool is_context_supported; /**< Determines if optional Glucose Measurement Context is to be supported. */
-} ble_gls_init_t;
-
-/**@brief Glucose Service structure. This contains various status information for the service. */
-typedef struct ble_gls_s
-{
- ble_gls_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Glucose Service. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- uint16_t service_handle; /**< Handle of Glucose Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t glm_handles; /**< Handles related to the Glucose Measurement characteristic. */
- ble_gatts_char_handles_t glm_context_handles; /**< Handles related to the Glucose Measurement Context characteristic. */
- ble_gatts_char_handles_t glf_handles; /**< Handles related to the Glucose Feature characteristic. */
- ble_gatts_char_handles_t racp_handles; /**< Handles related to the Record Access Control Point characteristic. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- uint16_t feature;
- bool is_context_supported;
-} ble_gls_t;
-
-/**@brief Function for initializing the Glucose Service.
- *
- * @details This call allows the application to initialize the Glucose Service.
- *
- * @param[out] p_gls Glucose Service structure. This structure will have to be supplied by
- * the application. It will be initialized by this function, and will later
- * be used to identify this particular service instance.
- * @param[in] p_gls_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_gls_init(ble_gls_t * p_gls, const ble_gls_init_t * p_gls_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Glucose Service.
- *
- * @param[in] p_gls Glucose Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_gls_on_ble_evt(ble_gls_t * p_gls, ble_evt_t * p_ble_evt);
-
-/**@brief Function for reporting a new glucose measurement to the glucose service module.
- *
- * @details The application calls this function after having performed a new glucose measurement.
- * The new measurement is recorded in the RACP database.
- *
- * @param[in] p_gls Glucose Service structure.
- * @param[in] p_rec Pointer to glucose record (measurement plus context).
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_gls_glucose_new_meas(ble_gls_t * p_gls, ble_gls_rec_t * p_rec);
-
-#endif // BLE_GLS_H__
-
-/** @} */
-
-/** @endcond */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_gls_db.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_gls_db Glucose Database Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Glucose Service module.
- *
- * @details This module implements at database of stored glucose measurement values.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, These APIs must not be modified. However, the corresponding
- * functions' implementations can be modified.
- */
-
-#ifndef BLE_GLS_DB_H__
-#define BLE_GLS_DB_H__
-
-#include <stdint.h>
-#include "ble_gls.h"
-
-#define BLE_GLS_DB_MAX_RECORDS 20
-
-/**@brief Function for initializing the glucose record database.
- *
- * @details This call initializes the database holding glucose records.
- *
- * @return NRF_SUCCESS on success.
- */
-uint32_t ble_gls_db_init(void);
-
-/**@brief Function for getting the number of records in the database.
- *
- * @details This call returns the number of records in the database.
- *
- * @return Number of records in the database.
- */
-uint16_t ble_gls_db_num_records_get(void);
-
-/**@brief Function for getting a record from the database.
- *
- * @details This call returns a specified record from the database.
- *
- * @param[in] record_num Index of the record to retrieve.
- * @param[out] p_rec Pointer to record structure where retrieved record is copied to.
- *
- * @return NRF_SUCCESS on success.
- */
-uint32_t ble_gls_db_record_get(uint8_t record_num, ble_gls_rec_t * p_rec);
-
-/**@brief Function for adding a record at the end of the database.
- *
- * @details This call adds a record as the last record in the database.
- *
- * @param[in] p_rec Pointer to record to add to database.
- *
- * @return NRF_SUCCESS on success.
- */
-uint32_t ble_gls_db_record_add(ble_gls_rec_t * p_rec);
-
-/**@brief Function for deleting a database entry.
- *
- * @details This call deletes an record from the database.
- *
- * @param[in] record_num Index of record to delete.
- *
- * @return NRF_SUCCESS on success.
- */
-uint32_t ble_gls_db_record_delete(uint8_t record_num);
-
-#endif // BLE_GLS_DB_H__
-
-/** @} */
-
-/** @endcond */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_hids.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,297 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_hids Human Interface Device Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Human Interface Device Service module.
- *
- * @details This module implements the Human Interface Device Service with the corresponding set of
- * characteristics. During initialization it adds the Human Interface Device Service and
- * a set of characteristics as per the Human Interface Device Service specification and
- * the user requirements to the BLE stack database.
- *
- * If enabled, notification of Input Report characteristics is performed when the
- * application calls the corresponding ble_hids_xx_input_report_send() function.
- *
- * If an event handler is supplied by the application, the Human Interface Device Service
- * will generate Human Interface Device Service events to the application.
- *
- * @note The application must propagate BLE stack events to the Human Interface Device Service
- * module by calling ble_hids_on_ble_evt() from the @ref ble_stack_handler callback.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_HIDS_H__
-#define BLE_HIDS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-
-// Report Type values
-#define BLE_HIDS_REP_TYPE_INPUT 1
-#define BLE_HIDS_REP_TYPE_OUTPUT 2
-#define BLE_HIDS_REP_TYPE_FEATURE 3
-
-// Maximum number of the various Report Types
-#define BLE_HIDS_MAX_INPUT_REP 10
-#define BLE_HIDS_MAX_OUTPUT_REP 10
-#define BLE_HIDS_MAX_FEATURE_REP 10
-
-// Information Flags
-#define HID_INFO_FLAG_REMOTE_WAKE_MSK 0x01
-#define HID_INFO_FLAG_NORMALLY_CONNECTABLE_MSK 0x02
-
-/**@brief HID Service characteristic id. */
-typedef struct
-{
- uint16_t uuid; /**< UUID of characteristic. */
- uint8_t rep_type; /**< Type of report (only used for BLE_UUID_REPORT_CHAR, see @ref BLE_HIDS_REPORT_TYPE). */
- uint8_t rep_index; /**< Index of the characteristic (only used for BLE_UUID_REPORT_CHAR). */
-} ble_hids_char_id_t;
-
-/**@brief HID Service event type. */
-typedef enum
-{
- BLE_HIDS_EVT_HOST_SUSP, /**< Suspend command received. */
- BLE_HIDS_EVT_HOST_EXIT_SUSP, /**< Exit suspend command received. */
- BLE_HIDS_EVT_NOTIF_ENABLED, /**< Notification enabled event. */
- BLE_HIDS_EVT_NOTIF_DISABLED, /**< Notification disabled event. */
- BLE_HIDS_EVT_REP_CHAR_WRITE, /**< A new value has been written to an Report characteristic. */
- BLE_HIDS_EVT_BOOT_MODE_ENTERED, /**< Boot mode entered. */
- BLE_HIDS_EVT_REPORT_MODE_ENTERED /**< Report mode entered. */
-} ble_hids_evt_type_t;
-
-/**@brief HID Service event. */
-typedef struct
-{
- ble_hids_evt_type_t evt_type; /**< Type of event. */
- union
- {
- struct
- {
- ble_hids_char_id_t char_id; /**< Id of characteristic for which notification has been started. */
- } notification;
- struct
- {
- ble_hids_char_id_t char_id; /**< Id of characteristic having been written. */
- } char_write;
- } params;
-} ble_hids_evt_t;
-
-// Forward declaration of the ble_hids_t type.
-typedef struct ble_hids_s ble_hids_t;
-
-/**@brief HID Service event handler type. */
-typedef void (*ble_hids_evt_handler_t) (ble_hids_t * p_hids, ble_hids_evt_t * p_evt);
-
-/**@brief HID Information characteristic value. */
-typedef struct
-{
- uint16_t bcd_hid; /**< 16-bit unsigned integer representing version number of base USB HID Specification implemented by HID Device */
- uint8_t b_country_code; /**< Identifies which country the hardware is localized for. Most hardware is not localized and thus this value would be zero (0). */
- uint8_t flags; /**< See http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.hid_information.xml */
- ble_srv_security_mode_t security_mode; /**< Security mode for the HID Information characteristic. */
-} ble_hids_hid_information_t;
-
-/**@brief HID Service Input Report characteristic init structure. This contains all options and
- * data needed for initialization of one Input Report characteristic. */
-typedef struct
-{
- uint16_t max_len; /**< Maximum length of characteristic value. */
- ble_srv_report_ref_t rep_ref; /**< Value of the Report Reference descriptor. */
- ble_srv_cccd_security_mode_t security_mode; /**< Security mode for the HID Input Report characteristic, including cccd. */
-} ble_hids_inp_rep_init_t;
-
-/**@brief HID Service Output Report characteristic init structure. This contains all options and
- * data needed for initialization of one Output Report characteristic. */
-typedef struct
-{
- uint16_t max_len; /**< Maximum length of characteristic value. */
- ble_srv_report_ref_t rep_ref; /**< Value of the Report Reference descriptor. */
- ble_srv_cccd_security_mode_t security_mode; /**< Security mode for the HID Output Report characteristic, including cccd. */
-} ble_hids_outp_rep_init_t;
-
-/**@brief HID Service Feature Report characteristic init structure. This contains all options and
- * data needed for initialization of one Feature Report characteristic. */
-typedef struct
-{
- uint16_t max_len; /**< Maximum length of characteristic value. */
- ble_srv_report_ref_t rep_ref; /**< Value of the Report Reference descriptor. */
- ble_srv_cccd_security_mode_t security_mode; /**< Security mode for the HID Service Feature Report characteristic, including cccd. */
-} ble_hids_feature_rep_init_t;
-
-/**@brief HID Service Report Map characteristic init structure. This contains all options and data
- * needed for initialization of the Report Map characteristic. */
-typedef struct
-{
- uint8_t data_len; /**< Length of report map data. */
- uint8_t * p_data; /**< Report map data. */
- ble_uuid_t * p_ext_rep_ref; /**< Optional External Report Reference descriptor (will be added if != NULL). */
- ble_srv_security_mode_t security_mode; /**< Security mode for the HID Service Report Map characteristic. */
-} ble_hids_rep_map_init_t;
-
-/**@brief HID Report characteristic structure. */
-typedef struct
-{
- ble_gatts_char_handles_t char_handles; /**< Handles related to the Report characteristic. */
- uint16_t ref_handle; /**< Handle of the Report Reference descriptor. */
-} ble_hids_rep_char_t;
-
-/**@brief HID Service init structure. This contains all options and data needed for initialization
- * of the service. */
-typedef struct
-{
- ble_hids_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the HID Service. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- bool is_kb; /**< TRUE if device is operating as a keyboard, FALSE if it is not. */
- bool is_mouse; /**< TRUE if device is operating as a mouse, FALSE if it is not. */
- uint8_t inp_rep_count; /**< Number of Input Report characteristics. */
- ble_hids_inp_rep_init_t * p_inp_rep_array; /**< Information about the Input Report characteristics. */
- uint8_t outp_rep_count; /**< Number of Output Report characteristics. */
- ble_hids_outp_rep_init_t * p_outp_rep_array; /**< Information about the Output Report characteristics. */
- uint8_t feature_rep_count; /**< Number of Feature Report characteristics. */
- ble_hids_feature_rep_init_t * p_feature_rep_array; /**< Information about the Feature Report characteristics. */
- ble_hids_rep_map_init_t rep_map; /**< Information nedeed for initialization of the Report Map characteristic. */
- ble_hids_hid_information_t hid_information; /**< Value of the HID Information characteristic. */
- uint8_t included_services_count; /**< Number of services to include in HID service. */
- uint16_t * p_included_services_array; /**< Array of services to include in HID service. */
- ble_srv_security_mode_t security_mode_protocol; /**< Security settings for HID service protocol attribute */
- ble_srv_security_mode_t security_mode_ctrl_point; /**< Security settings for HID service Control Point attribute */
- ble_srv_cccd_security_mode_t security_mode_boot_mouse_inp_rep; /**< Security settings for HID service Mouse input report attribute */
- ble_srv_cccd_security_mode_t security_mode_boot_kb_inp_rep; /**< Security settings for HID service Keyboard input report attribute */
- ble_srv_security_mode_t security_mode_boot_kb_outp_rep; /**< Security settings for HID service Keyboard output report attribute */
-} ble_hids_init_t;
-
-/**@brief HID Service structure. This contains various status information for the service. */
-typedef struct ble_hids_s
-{
- ble_hids_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the HID Service. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- uint16_t service_handle; /**< Handle of HID Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t protocol_mode_handles; /**< Handles related to the Protocol Mode characteristic (will only be created if ble_hids_init_t.is_kb or ble_hids_init_t.is_mouse is set). */
- uint8_t inp_rep_count; /**< Number of Input Report characteristics. */
- ble_hids_rep_char_t inp_rep_array[BLE_HIDS_MAX_INPUT_REP]; /**< Information about the Input Report characteristics. */
- uint8_t outp_rep_count; /**< Number of Output Report characteristics. */
- ble_hids_rep_char_t outp_rep_array[BLE_HIDS_MAX_OUTPUT_REP]; /**< Information about the Output Report characteristics. */
- uint8_t feature_rep_count; /**< Number of Feature Report characteristics. */
- ble_hids_rep_char_t feature_rep_array[BLE_HIDS_MAX_FEATURE_REP]; /**< Information about the Feature Report characteristics. */
- ble_gatts_char_handles_t rep_map_handles; /**< Handles related to the Report Map characteristic. */
- uint16_t rep_map_ext_rep_ref_handle; /**< Handle of the Report Map External Report Reference descriptor. */
- ble_gatts_char_handles_t boot_kb_inp_rep_handles; /**< Handles related to the Boot Keyboard Input Report characteristic (will only be created if ble_hids_init_t.is_kb is set). */
- ble_gatts_char_handles_t boot_kb_outp_rep_handles; /**< Handles related to the Boot Keyboard Output Report characteristic (will only be created if ble_hids_init_t.is_kb is set). */
- ble_gatts_char_handles_t boot_mouse_inp_rep_handles; /**< Handles related to the Boot Mouse Input Report characteristic (will only be created if ble_hids_init_t.is_mouse is set). */
- ble_gatts_char_handles_t hid_information_handles; /**< Handles related to the Report Map characteristic. */
- ble_gatts_char_handles_t hid_control_point_handles; /**< Handles related to the Report Map characteristic. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
-} ble_hids_t;
-
-/**@brief Function for initializing the HID Service.
- *
- * @param[out] p_hids HID Service structure. This structure will have to be supplied by the
- * application. It will be initialized by this function, and will later be
- * used to identify this particular service instance.
- * @param[in] p_hids_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_hids_init(ble_hids_t * p_hids, const ble_hids_init_t * p_hids_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the HID Service.
- *
- * @param[in] p_hids HID Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_hids_on_ble_evt(ble_hids_t * p_hids, ble_evt_t * p_ble_evt);
-
-/**@brief Function for sending Input Report.
- *
- * @details Sends data on an Input Report characteristic.
- *
- * @param[in] p_hids HID Service structure.
- * @param[in] rep_index Index of the characteristic (corresponding to the index in
- * ble_hids_t.inp_rep_array as passed to ble_hids_init()).
- * @param[in] len Length of data to be sent.
- * @param[in] p_data Pointer to data to be sent.
- *
- * @return NRF_SUCCESS on successful sending of input report, otherwise an error code.
- */
-uint32_t ble_hids_inp_rep_send(ble_hids_t * p_hids,
- uint8_t rep_index,
- uint16_t len,
- uint8_t * p_data);
-
-/**@brief Function for sending Boot Keyboard Input Report.
- *
- * @details Sends data on an Boot Keyboard Input Report characteristic.
- *
- * @param[in] p_hids HID Service structure.
- * @param[in] len Length of data to be sent.
- * @param[in] p_data Pointer to data to be sent.
- *
- * @return NRF_SUCCESS on successful sending of the report, otherwise an error code.
- */
-uint32_t ble_hids_boot_kb_inp_rep_send(ble_hids_t * p_hids,
- uint16_t len,
- uint8_t * p_data);
-
-/**@brief Function for sending Boot Mouse Input Report.
- *
- * @details Sends data on an Boot Mouse Input Report characteristic.
- *
- * @param[in] p_hids HID Service structure.
- * @param[in] buttons State of mouse buttons.
- * @param[in] x_delta Horizontal movement.
- * @param[in] y_delta Vertical movement.
- * @param[in] optional_data_len Length of optional part of Boot Mouse Input Report.
- * @param[in] p_optional_data Optional part of Boot Mouse Input Report.
- *
- * @return NRF_SUCCESS on successful sending of the report, otherwise an error code.
- */
-uint32_t ble_hids_boot_mouse_inp_rep_send(ble_hids_t * p_hids,
- uint8_t buttons,
- int8_t x_delta,
- int8_t y_delta,
- uint16_t optional_data_len,
- uint8_t * p_optional_data);
-
-/**@brief Function for getting the current value of Output Report from the stack.
- *
- * @details Fetches the current value of the output report characteristic from the stack.
- *
- * @param[in] p_hids HID Service structure.
- * @param[in] rep_index Index of the characteristic (corresponding to the index in
- * ble_hids_t.outp_rep_array as passed to ble_hids_init()).
- * @param[in] len Length of output report needed.
- * @param[in] offset Offset in bytes to read from.
- * @param[out] p_outp_rep Pointer to the output report.
- *
- * @return NRF_SUCCESS on successful read of the report, otherwise an error code.
- */
-uint32_t ble_hids_outp_rep_get(ble_hids_t * p_hids,
- uint8_t rep_index,
- uint16_t len,
- uint8_t offset,
- uint8_t * p_outp_rep);
-
-#endif // BLE_HIDS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_hrs.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,194 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_hrs Heart Rate Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Heart Rate Service module.
- *
- * @details This module implements the Heart Rate Service with the Heart Rate Measurement,
- * Body Sensor Location and Heart Rate Control Point characteristics.
- * During initialization it adds the Heart Rate Service and Heart Rate Measurement
- * characteristic to the BLE stack database. Optionally it also adds the
- * Body Sensor Location and Heart Rate Control Point characteristics.
- *
- * If enabled, notification of the Heart Rate Measurement characteristic is performed
- * when the application calls ble_hrs_heart_rate_measurement_send().
- *
- * The Heart Rate Service also provides a set of functions for manipulating the
- * various fields in the Heart Rate Measurement characteristic, as well as setting
- * the Body Sensor Location characteristic value.
- *
- * If an event handler is supplied by the application, the Heart Rate Service will
- * generate Heart Rate Service events to the application.
- *
- * @note The application must propagate BLE stack events to the Heart Rate Service module by calling
- * ble_hrs_on_ble_evt() from the from the @ref ble_stack_handler callback.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_HRS_H__
-#define BLE_HRS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-
-// Body Sensor Location values
-#define BLE_HRS_BODY_SENSOR_LOCATION_OTHER 0
-#define BLE_HRS_BODY_SENSOR_LOCATION_CHEST 1
-#define BLE_HRS_BODY_SENSOR_LOCATION_WRIST 2
-#define BLE_HRS_BODY_SENSOR_LOCATION_FINGER 3
-#define BLE_HRS_BODY_SENSOR_LOCATION_HAND 4
-#define BLE_HRS_BODY_SENSOR_LOCATION_EAR_LOBE 5
-#define BLE_HRS_BODY_SENSOR_LOCATION_FOOT 6
-
-#define BLE_HRS_MAX_BUFFERED_RR_INTERVALS 20 /**< Size of RR Interval buffer inside service. */
-
-/**@brief Heart Rate Service event type. */
-typedef enum
-{
- BLE_HRS_EVT_NOTIFICATION_ENABLED, /**< Heart Rate value notification enabled event. */
- BLE_HRS_EVT_NOTIFICATION_DISABLED /**< Heart Rate value notification disabled event. */
-} ble_hrs_evt_type_t;
-
-/**@brief Heart Rate Service event. */
-typedef struct
-{
- ble_hrs_evt_type_t evt_type; /**< Type of event. */
-} ble_hrs_evt_t;
-
-// Forward declaration of the ble_hrs_t type.
-typedef struct ble_hrs_s ble_hrs_t;
-
-/**@brief Heart Rate Service event handler type. */
-typedef void (*ble_hrs_evt_handler_t) (ble_hrs_t * p_hrs, ble_hrs_evt_t * p_evt);
-
-/**@brief Heart Rate Service init structure. This contains all options and data needed for
- * initialization of the service. */
-typedef struct
-{
- ble_hrs_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Heart Rate Service. */
- bool is_sensor_contact_supported; /**< Determines if sensor contact detection is to be supported. */
- uint8_t * p_body_sensor_location; /**< If not NULL, initial value of the Body Sensor Location characteristic. */
- ble_srv_cccd_security_mode_t hrs_hrm_attr_md; /**< Initial security level for heart rate service measurement attribute */
- ble_srv_security_mode_t hrs_bsl_attr_md; /**< Initial security level for body sensor location attribute */
-} ble_hrs_init_t;
-
-/**@brief Heart Rate Service structure. This contains various status information for the service. */
-typedef struct ble_hrs_s
-{
- ble_hrs_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Heart Rate Service. */
- bool is_expended_energy_supported; /**< TRUE if Expended Energy measurement is supported. */
- bool is_sensor_contact_supported; /**< TRUE if sensor contact detection is supported. */
- uint16_t service_handle; /**< Handle of Heart Rate Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t hrm_handles; /**< Handles related to the Heart Rate Measurement characteristic. */
- ble_gatts_char_handles_t bsl_handles; /**< Handles related to the Body Sensor Location characteristic. */
- ble_gatts_char_handles_t hrcp_handles; /**< Handles related to the Heart Rate Control Point characteristic. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- bool is_sensor_contact_detected; /**< TRUE if sensor contact has been detected. */
- uint16_t rr_interval[BLE_HRS_MAX_BUFFERED_RR_INTERVALS]; /**< Set of RR Interval measurements since the last Heart Rate Measurement transmission. */
- uint16_t rr_interval_count; /**< Number of RR Interval measurements since the last Heart Rate Measurement transmission. */
-} ble_hrs_t;
-
-/**@brief Function for initializing the Heart Rate Service.
- *
- * @param[out] p_hrs Heart Rate Service structure. This structure will have to be supplied by
- * the application. It will be initialized by this function, and will later
- * be used to identify this particular service instance.
- * @param[in] p_hrs_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_hrs_init(ble_hrs_t * p_hrs, const ble_hrs_init_t * p_hrs_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Heart Rate Service.
- *
- * @param[in] p_hrs Heart Rate Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_hrs_on_ble_evt(ble_hrs_t * p_hrs, ble_evt_t * p_ble_evt);
-
-/**@brief Function for sending heart rate measurement if notification has been enabled.
- *
- * @details The application calls this function after having performed a heart rate measurement.
- * If notification has been enabled, the heart rate measurement data is encoded and sent to
- * the client.
- *
- * @param[in] p_hrs Heart Rate Service structure.
- * @param[in] heart_rate New heart rate measurement.
- * @param[in] include_expended_energy Determines if expended energy will be included in the
- * heart rate measurement data.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_hrs_heart_rate_measurement_send(ble_hrs_t * p_hrs, uint16_t heart_rate);
-
-/**@brief Function for adding a RR Interval measurement to the RR Interval buffer.
- *
- * @details All buffered RR Interval measurements will be included in the next heart rate
- * measurement message, up to the maximum number of measurements that will fit into the
- * message. If the buffer is full, the oldest measurement in the buffer will be deleted.
- *
- * @param[in] p_hrs Heart Rate Service structure.
- * @param[in] rr_interval New RR Interval measurement (will be buffered until the next
- * transmission of Heart Rate Measurement).
- */
-void ble_hrs_rr_interval_add(ble_hrs_t * p_hrs, uint16_t rr_interval);
-
-/**@brief Function for checking if RR Interval buffer is full.
- *
- * @param[in] p_hrs Heart Rate Service structure.
- *
- * @return true if RR Interval buffer is full, false otherwise.
- */
-bool ble_hrs_rr_interval_buffer_is_full(ble_hrs_t * p_hrs);
-
-/**@brief Function for setting the state of the Sensor Contact Supported bit.
- *
- * @param[in] p_hrs Heart Rate Service structure.
- * @param[in] is_sensor_contact_supported New state of the Sensor Contact Supported bit.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_hrs_sensor_contact_supported_set(ble_hrs_t * p_hrs, bool is_sensor_contact_supported);
-
-/**@brief Function for setting the state of the Sensor Contact Detected bit.
- *
- * @param[in] p_hrs Heart Rate Service structure.
- * @param[in] is_sensor_contact_detected TRUE if sensor contact is detected, FALSE otherwise.
- */
-void ble_hrs_sensor_contact_detected_update(ble_hrs_t * p_hrs, bool is_sensor_contact_detected);
-
-/**@brief Function for setting the Body Sensor Location.
- *
- * @details Sets a new value of the Body Sensor Location characteristic. The new value will be sent
- * to the client the next time the client reads the Body Sensor Location characteristic.
- *
- * @param[in] p_hrs Heart Rate Service structure.
- * @param[in] body_sensor_location New Body Sensor Location.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_hrs_body_sensor_location_set(ble_hrs_t * p_hrs, uint8_t body_sensor_location);
-
-#endif // BLE_HRS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_hts.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,160 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_hts Health Thermometer Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Health Thermometer Service module.
- *
- * @details This module implements the Health Thermometer Service.
- *
- * If an event handler is supplied by the application, the Health Thermometer
- * Service will generate Health Thermometer Service events to the application.
- *
- * @note The application must propagate BLE stack events to the Health Thermometer Service
- * module by calling ble_hts_on_ble_evt() from the from the @ref ble_stack_handler function.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_HTS_H__
-#define BLE_HTS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-#include "ble_date_time.h"
-
-// Temperature Type measurement locations
-#define BLE_HTS_TEMP_TYPE_ARMPIT 1
-#define BLE_HTS_TEMP_TYPE_BODY 2
-#define BLE_HTS_TEMP_TYPE_EAR 3
-#define BLE_HTS_TEMP_TYPE_FINGER 4
-#define BLE_HTS_TEMP_TYPE_GI_TRACT 5
-#define BLE_HTS_TEMP_TYPE_MOUTH 6
-#define BLE_HTS_TEMP_TYPE_RECTUM 7
-#define BLE_HTS_TEMP_TYPE_TOE 8
-#define BLE_HTS_TEMP_TYPE_EAR_DRUM 9
-
-/**@brief Health Thermometer Service event type. */
-typedef enum
-{
- BLE_HTS_EVT_INDICATION_ENABLED, /**< Health Thermometer value indication enabled event. */
- BLE_HTS_EVT_INDICATION_DISABLED, /**< Health Thermometer value indication disabled event. */
- BLE_HTS_EVT_INDICATION_CONFIRMED /**< Confirmation of a temperature measurement indication has been received. */
-} ble_hts_evt_type_t;
-
-/**@brief Health Thermometer Service event. */
-typedef struct
-{
- ble_hts_evt_type_t evt_type; /**< Type of event. */
-} ble_hts_evt_t;
-
-// Forward declaration of the ble_hts_t type.
-typedef struct ble_hts_s ble_hts_t;
-
-/**@brief Health Thermometer Service event handler type. */
-typedef void (*ble_hts_evt_handler_t) (ble_hts_t * p_hts, ble_hts_evt_t * p_evt);
-
-/**@brief FLOAT format (IEEE-11073 32-bit FLOAT, defined as a 32-bit value with a 24-bit mantissa
- * and an 8-bit exponent. */
-typedef struct
-{
- int8_t exponent; /**< Base 10 exponent */
- int32_t mantissa; /**< Mantissa, should be using only 24 bits */
-} ieee_float32_t;
-
-/**@brief Health Thermometer Service init structure. This contains all options and data
- * needed for initialization of the service. */
-typedef struct
-{
- ble_hts_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Health Thermometer Service. */
- ble_srv_cccd_security_mode_t hts_meas_attr_md; /**< Initial security level for health thermometer measurement attribute */
- ble_srv_security_mode_t hts_temp_type_attr_md; /**< Initial security level for health thermometer tempearture type attribute */
- uint8_t temp_type_as_characteristic; /**< Set non-zero if temp type given as characteristic */
- uint8_t temp_type; /**< Temperature type if temperature characteristic is used */
-} ble_hts_init_t;
-
-/**@brief Health Thermometer Service structure. This contains various status information for
- * the service. */
-typedef struct ble_hts_s
-{
- ble_hts_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Health Thermometer Service. */
- uint16_t service_handle; /**< Handle of Health Thermometer Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t meas_handles; /**< Handles related to the Health Thermometer Measurement characteristic. */
- ble_gatts_char_handles_t temp_type_handles; /**< Handles related to the Health Thermometer Temperature Type characteristic. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- uint8_t temp_type; /**< Temperature type indicates where the measurement was taken. */
-} ble_hts_t;
-
-/**@brief Health Thermometer Service measurement structure. This contains a Health Thermometer
- * measurement. */
-typedef struct ble_hts_meas_s
-{
- bool temp_in_fahr_units; /**< True if Temperature is in Fahrenheit units, Celcius otherwise. */
- bool time_stamp_present; /**< True if Time Stamp is present. */
- bool temp_type_present; /**< True if Temperature Type is present. */
- ieee_float32_t temp_in_celcius; /**< Temperature Measurement Value (Celcius). */
- ieee_float32_t temp_in_fahr; /**< Temperature Measurement Value (Fahrenheit). */
- ble_date_time_t time_stamp; /**< Time Stamp. */
- uint8_t temp_type; /**< Temperature Type. */
-} ble_hts_meas_t;
-
-/**@brief Function for initializing the Health Thermometer Service.
- *
- * @param[out] p_hts Health Thermometer Service structure. This structure will have to
- * be supplied by the application. It will be initialized by this function,
- * and will later be used to identify this particular service instance.
- * @param[in] p_hts_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_hts_init(ble_hts_t * p_hts, const ble_hts_init_t * p_hts_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Health Thermometer Service.
- *
- * @param[in] p_hts Health Thermometer Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_hts_on_ble_evt(ble_hts_t * p_hts, ble_evt_t * p_ble_evt);
-
-/**@brief Function for sending health thermometer measurement if indication has been enabled.
- *
- * @details The application calls this function after having performed a Health Thermometer
- * measurement. If indication has been enabled, the measurement data is encoded and
- * sent to the client.
- *
- * @param[in] p_hts Health Thermometer Service structure.
- * @param[in] p_hts_meas Pointer to new health thermometer measurement.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_hts_measurement_send(ble_hts_t * p_hts, ble_hts_meas_t * p_hts_meas);
-
-/**@brief Function for checking if indication of Temperature Measurement is currently enabled.
- *
- * @param[in] p_hts Health Thermometer Service structure.
- * @param[out] p_indication_enabled TRUE if indication is enabled, FALSE otherwise.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_hts_is_indication_enabled(ble_hts_t * p_hts, bool * p_indication_enabled);
-
-#endif // BLE_HTS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_ias.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,112 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_ias Immediate Alert Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Immediate Alert Service module.
- *
- * @details This module implements the Immediate Alert Service with the Alert Level characteristic.
- * During initialization it adds the Immediate Alert Service and Alert Level characteristic
- * to the BLE stack database.
- *
- * The application must supply an event handler for receiving Immediate Alert Service
- * events. Using this handler, the service will notify the application when the
- * Alert Level characteristic value changes.
- *
- * The service also provides a function for letting the application poll the current
- * value of the Alert Level characteristic.
- *
- * @note The application must propagate BLE stack events to the Immediate Alert Service
- * module by calling ble_ias_on_ble_evt() from the @ref ble_stack_handler callback.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
-*/
-
-#ifndef BLE_IAS_H__
-#define BLE_IAS_H__
-
-#include <stdint.h>
-#include "ble.h"
-
-/**@brief Immediate Alert Service event type. */
-typedef enum
-{
- BLE_IAS_EVT_ALERT_LEVEL_UPDATED /**< Alert Level Updated event. */
-} ble_ias_evt_type_t;
-
-/**@brief Immediate Alert Service event. */
-typedef struct
-{
- ble_ias_evt_type_t evt_type; /**< Type of event. */
- union
- {
- uint8_t alert_level; /**< New Alert Level value. */
- } params;
-} ble_ias_evt_t;
-
-// Forward declaration of the ble_ias_t type.
-typedef struct ble_ias_s ble_ias_t;
-
-/**@brief Immediate Alert Service event handler type. */
-typedef void (*ble_ias_evt_handler_t) (ble_ias_t * p_ias, ble_ias_evt_t * p_evt);
-
-/**@brief Immediate Alert Service init structure. This contains all options and data needed for
- * initialization of the service. */
-typedef struct
-{
- ble_ias_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Immediate Alert Service. */
-} ble_ias_init_t;
-
-/**@brief Immediate Alert Service structure. This contains various status information for the
- * service. */
-typedef struct ble_ias_s
-{
- ble_ias_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Immediate Alert Service. */
- uint16_t service_handle; /**< Handle of Immediate Alert Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t alert_level_handles; /**< Handles related to the Alert Level characteristic. */
-} ble_ias_t;
-
-/**@brief Function for initializing the Immediate Alert Service.
- *
- * @param[out] p_ias Immediate Alert Service structure. This structure will have to be
- * supplied by the application. It will be initialized by this function,
- * and will later be used to identify this particular service instance.
- * @param[in] p_ias_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_ias_init(ble_ias_t * p_ias, const ble_ias_init_t * p_ias_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Immediate Alert Service.
- *
- * @param[in] p_ias Immediate Alert Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_ias_on_ble_evt(ble_ias_t * p_ias, ble_evt_t * p_ble_evt);
-
-/**@brief Function for getting current value of the Alert Level characteristic.
- *
- * @param[in] p_ias Immediate Alert Service structure.
- * @param[out] p_alert_level Current Alert Level value.
- */
-uint32_t ble_ias_alert_level_get(ble_ias_t * p_ias, uint8_t * p_alert_level);
-
-#endif // BLE_IAS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_ias_c.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,119 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_ias_c Immediate Alert Service Client
- * @{
- * @ingroup ble_sdk_srv
- * @brief Immediate Alert Service Client module
- *
- * @details This module implements the Immediate Alert Service client - locator role of the Find Me
- * profile. On @ref BLE_GAP_EVT_CONNECTED event, this module starts discovery of the
- * Immediate Alert Service with Alert Level characteristic at the peer. This module will
- * indicate the application about a successful service & characteristic discovery using
- * @ref BLE_IAS_C_EVT_CHAR_DISCOVERED event. The application can use @ref
- * ble_ias_c_send_alert_level function to signal alerts to the peer.
- *
- * @note The application must propagate BLE stack events to this module by calling
- * ble_ias_c_on_ble_evt() from the from the @ref ble_stack_handler callback function.
- */
-
-#ifndef BLE_IAS_C_H__
-#define BLE_IAS_C_H__
-
-#include "ble_srv_common.h"
-#include "ble_gattc.h"
-#include "ble.h"
-#include <stdint.h>
-
-// Forward declaration of the ble_ias_c_t type.
-typedef struct ble_ias_c_s ble_ias_c_t;
-
-/**@brief Immediate Alert Service client event type. */
-typedef enum
-{
- BLE_IAS_C_EVT_SRV_DISCOVERED, /**< Event indicating that the Immediate Alert Service is found at the peer. */
- BLE_IAS_C_EVT_SRV_NOT_FOUND, /**< Event indicating that the Immediate Alert Service is not found at the peer. */
- BLE_IAS_C_EVT_DISCONN_COMPLETE /**< Event indicating that the Immediate Alert Service client module has completed the processing of BLE_GAP_EVT_DISCONNECTED event. This event is raised only if a valid instance of IAS was found at the peer during the discovery phase. This event can be used the application to do clean up related to the IAS Client.*/
-} ble_ias_c_evt_type_t;
-
-/**@brief Immediate Alert Service client event. */
-typedef struct
-{
- ble_ias_c_evt_type_t evt_type; /**< Type of event. */
-} ble_ias_c_evt_t;
-
-/**@brief Immediate Alert Service client event handler type. */
-typedef void (*ble_ias_c_evt_handler_t) (ble_ias_c_t * p_ias_c, ble_ias_c_evt_t * p_evt);
-
-/**@brief IAS Client structure. This contains various status information for the client. */
-typedef struct ble_ias_c_s
-{
- ble_ias_c_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Immediate Alert Service client. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- uint16_t alert_level_handle; /**< Handle of Alert Level characteristic at peer (as provided by the BLE stack). */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
-} ble_ias_c_t;
-
-/**@brief IAS Client init structure. This contains all options and data needed for initialization of
- * the client.*/
-typedef struct
-{
- ble_ias_c_evt_handler_t evt_handler; /**< Event handler to be called for handling events from the Immediate Alert Service client. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
-} ble_ias_c_init_t;
-
-/**@brief Function for initializing the Immediate Alert Service client.
- *
- * @details This call allows the application to initialize the Immediate Alert Service client.
- *
- * @param[out] p_ias_c Immediate Alert Service client structure. This structure will have to
- * be supplied by the application. It will be initialized by this
- * function, and will later be used to identify this particular client
- * instance.
- * @param[in] p_ias_c_init Information needed to initialize the Immediate Alert Service client.
- *
- * @return NRF_SUCCESS on successful initialization of service.
- */
-uint32_t ble_ias_c_init(ble_ias_c_t * p_ias_c, const ble_ias_c_init_t * p_ias_c_init);
-
-/**@brief Function for sending alert level to the peer.
- *
- * @details This function allows the application to send an alert to the peer.
- *
- * @param[in] p_ias_c Immediate Alert Service client structure.
- * @param[in] alert_level Required alert level to be sent to the peer.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_ias_c_send_alert_level(const ble_ias_c_t * p_ias_c, uint8_t alert_level);
-
-/**@brief Function for handling the Application's BLE Stack events for Immediate Alert Service client.
- *
- * @details Handles all events from the BLE stack of interest to the Immediate Alert Service client.
- *
- * @param[in] p_ias_c Immediate Alert Service client structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_ias_c_on_ble_evt(ble_ias_c_t * p_ias_c, const ble_evt_t * p_ble_evt);
-
-/**@brief Function for checking whether the peer's Immediate Alert Service instance and the alert level
- * characteristic have been discovered.
- * @param[in] p_ias_c Immediate Alert Service client structure.
- */
-static __INLINE bool ble_ias_c_is_ias_discovered(const ble_ias_c_t * p_ias_c)
-{
- return (p_ias_c->alert_level_handle != BLE_GATT_HANDLE_INVALID);
-}
-
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_lls.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,115 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_lls Link Loss Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Link Loss Service module.
- *
- * @details This module implements the Link Loss Service with the Alert Level characteristic.
- * During initialization it adds the Link Loss Service and Alert Level characteristic
- * to the BLE stack database.
- *
- * The application must supply an event handler for receiving Link Loss Service
- * events. Using this handler, the service will notify the application when the
- * link has been lost, and which Alert Level has been set.
- *
- * The service also provides a function for letting the application poll the current
- * value of the Alert Level characteristic.
- *
- * @note The application must propagate BLE stack events to the Link Loss Service
- * module by calling ble_lls_on_ble_evt() from the @ref ble_stack_handler callback.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
-*/
-
-#ifndef BLE_LLS_H__
-#define BLE_LLS_H__
-
-#include <stdint.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-
-/**@brief Link Loss Service event type. */
-typedef enum
-{
- BLE_LLS_EVT_LINK_LOSS_ALERT /**< Alert Level Updated event. */
-} ble_lls_evt_type_t;
-
-/**@brief Link Loss Service event. */
-typedef struct
-{
- ble_lls_evt_type_t evt_type; /**< Type of event. */
- union
- {
- uint8_t alert_level; /**< New Alert Level value. */
- } params;
-} ble_lls_evt_t;
-
-// Forward declaration of the ble_lls_t type.
-typedef struct ble_lls_s ble_lls_t;
-
-/**@brief Link Loss Service event handler type. */
-typedef void (*ble_lls_evt_handler_t) (ble_lls_t * p_lls, ble_lls_evt_t * p_evt);
-
-/**@brief Link Loss Service init structure. This contains all options and data needed for initialization of the service. */
-typedef struct
-{
- ble_lls_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Link Loss Service. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- uint8_t initial_alert_level; /**< Initial value of the Alert Level characteristic. */
- ble_srv_security_mode_t lls_attr_md; /**< Initial Security Setting for Link Loss Service Characteristics. */
-} ble_lls_init_t;
-
-/**@brief Link Loss Service structure. This contains various status information for the service. */
-typedef struct ble_lls_s
-{
- ble_lls_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Link Loss Service. */
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- uint16_t service_handle; /**< Handle of Link Loss Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t alert_level_handles; /**< Handles related to the Alert Level characteristic. */
-} ble_lls_t;
-
-/**@brief Function for initializing the Link Loss Service.
- *
- * @param[out] p_lls Link Loss Service structure. This structure will have to be supplied by
- * the application. It will be initialized by this function, and will later
- * be used to identify this particular service instance.
- * @param[in] p_lls_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_lls_init(ble_lls_t * p_lls, const ble_lls_init_t * p_lls_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Link Loss Service.
- *
- * @param[in] p_lls Link Loss Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_lls_on_ble_evt(ble_lls_t * p_lls, ble_evt_t * p_ble_evt);
-
-/**@brief Function for getting current value of the Alert Level characteristic.
- *
- * @param[in] p_lls Link Loss Service structure.
- * @param[out] p_alert_level Current Alert Level value.
- */
-uint32_t ble_lls_alert_level_get(ble_lls_t * p_lls, uint8_t * p_alert_level);
-
-#endif // BLE_LLS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_rscs.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,140 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_rsc Running Speed and Cadence Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief Running Speed and Cadence Service module.
- *
- * @details This module implements the Running Speed and Cadence Service. If enabled, notification
- * of the Running Speead and Candence Measurement is performed when the application
- * calls ble_rscs_measurement_send().
- *
- * If an event handler is supplied by the application, the Running Speed and Cadence
- * Service will generate Running Speed and Cadence Service events to the application.
- *
- * @note The application must propagate BLE stack events to the Running Speead and Candence Service
- * module by calling ble_rscs_on_ble_evt() from the from the @ref ble_stack_handler function.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_RSCS_H__
-#define BLE_RSCS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-
-/**@brief Running Speed and Cadence Service feature bits. */
-#define BLE_RSCS_FEATURE_INSTANT_STRIDE_LEN_BIT (0x01 << 0) /**< Instantaneous Stride Length Measurement Supported bit. */
-#define BLE_RSCS_FEATURE_TOTAL_DISTANCE_BIT (0x01 << 1) /**< Total Distance Measurement Supported bit. */
-#define BLE_RSCS_FEATURE_WALKING_OR_RUNNING_STATUS_BIT (0x01 << 2) /**< Walking or Running Status Supported bit. */
-#define BLE_RSCS_FEATURE_CALIBRATION_PROCEDURE_BIT (0x01 << 3) /**< Calibration Procedure Supported bit. */
-#define BLE_RSCS_FEATURE_MULTIPLE_SENSORS_BIT (0x01 << 4) /**< Multiple Sensor Locations Supported bit. */
-
-/**@brief Running Speed and Cadence Service event type. */
-typedef enum
-{
- BLE_RSCS_EVT_NOTIFICATION_ENABLED, /**< Running Speed and Cadence value notification enabled event. */
- BLE_RSCS_EVT_NOTIFICATION_DISABLED /**< Running Speed and Cadence value notification disabled event. */
-} ble_rscs_evt_type_t;
-
-/**@brief Running Speed and Cadence Service event. */
-typedef struct
-{
- ble_rscs_evt_type_t evt_type; /**< Type of event. */
-} ble_rscs_evt_t;
-
-// Forward declaration of the ble_rsc_t type.
-typedef struct ble_rscs_s ble_rscs_t;
-
-/**@brief Running Speed and Cadence Service event handler type. */
-typedef void (*ble_rscs_evt_handler_t) (ble_rscs_t * p_rscs, ble_rscs_evt_t * p_evt);
-
-/**@brief Running Speed and Cadence Service init structure. This contains all options and data
- * needed for initialization of the service. */
-typedef struct
-{
- ble_rscs_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Running Speed and Cadence Service. */
- ble_srv_cccd_security_mode_t rsc_meas_attr_md; /**< Initial security level for running speed and cadence measurement attribute */
- ble_srv_security_mode_t rsc_feature_attr_md; /**< Initial security level for feature attribute */
- uint16_t feature; /**< Initial value for features of sensor. */
-} ble_rscs_init_t;
-
-/**@brief Running Speed and Cadence Service structure. This contains various status information for
- * the service. */
-typedef struct ble_rscs_s
-{
- ble_rscs_evt_handler_t evt_handler; /**< Event handler to be called for handling events in the Running Speed and Cadence Service. */
- uint16_t service_handle; /**< Handle of Running Speed and Cadence Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t meas_handles; /**< Handles related to the Running Speed and Cadence Measurement characteristic. */
- ble_gatts_char_handles_t feature_handles; /**< Handles related to the Running Speed and Cadence feature characteristic. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- uint16_t feature; /**< Bit mask of features available on sensor. */
-} ble_rscs_t;
-
-/**@brief Running Speed and Cadence Service measurement structure. This contains a Running Speed and
- * Cadence measurement. */
-typedef struct ble_rscs_meas_s
-{
- bool is_inst_stride_len_present; /**< True if Instantaneous Stride Length is present in the measurement. */
- bool is_total_distance_present; /**< True if Total Distance is present in the measurement. */
- bool is_running; /**< True if running, False if walking. */
- uint16_t inst_speed; /**< Instantaneous Speed. */
- uint8_t inst_cadence; /**< Instantaneous Cadence. */
- uint16_t inst_stride_length; /**< Instantaneous Stride Length. */
- uint32_t total_distance; /**< Total Distance. */
-} ble_rscs_meas_t;
-
-/**@brief Function for initializing the Running Speed and Cadence Service.
- *
- * @param[out] p_rscs Running Speed and Cadence Service structure. This structure will have to
- * be supplied by the application. It will be initialized by this function,
- * and will later be used to identify this particular service instance.
- * @param[in] p_rscs_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_rscs_init(ble_rscs_t * p_rscs, const ble_rscs_init_t * p_rscs_init);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack of interest to the Running Speed and Cadence
- * Service.
- *
- * @param[in] p_rscs Running Speed and Cadence Service structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_rscs_on_ble_evt(ble_rscs_t * p_rscs, ble_evt_t * p_ble_evt);
-
-/**@brief Function for sending running speed and cadence measurement if notification has been enabled.
- *
- * @details The application calls this function after having performed a Running Speed and Cadence
- * measurement. If notification has been enabled, the measurement data is encoded and sent
- * to the client.
- *
- * @param[in] p_rscs Running Speed and Cadence Service structure.
- * @param[in] p_measurement Pointer to new running speed and cadence measurement.
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_rscs_measurement_send(ble_rscs_t * p_rscs, ble_rscs_meas_t * p_measurement);
-
-#endif // BLE_RSCS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_sc_ctrlpt.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,206 +0,0 @@
-/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_sc_ctrlpt Speed and Cadence Control Point
- * @{
- * @ingroup ble_sdk_srv
- * @brief Speed and Cadence Control Point module.
- *
- * @details This module implements the Speed and Cadence control point behavior. It is used
- * by the @ref ble_sdk_srv_csc module and the ble_sdk_srv_rsc module for control point
- * mechanisms like setting a cumulative value, Start an automatic calibration,
- * Update the sensor location or request the supported locations.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_SC_CTRLPT_H__
-#define BLE_SC_CTRLPT_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-#include "ble_sensor_location.h"
-
-#define BLE_SC_CTRLPT_MAX_LEN 19 /**< maximum lenght for Speed and cadence control point characteristic value. */
-#define BLE_SC_CTRLPT_MIN_LEN 1 /**< minimum length for Speed and cadence control point characteristic value. */
-
-// Forward declaration of the ble_sc_ctrlpt_t type.
-typedef struct ble_sc_ctrlpt_s ble_sc_ctrlpt_t;
-
-
-/**@brief Speed and Cadence Control Point event type. */
-typedef enum
-{
- BLE_SC_CTRLPT_EVT_UPDATE_LOCATION, /**< rcvd update location opcode (the control point handles the change of location automatically, the event just informs the application in case it needs to adjust its algorithm). */
- BLE_SC_CTRLPT_EVT_SET_CUMUL_VALUE, /**< rcvd set cumulative value opcode, it is then up to the application to use the new cumulative value. */
- BLE_SC_CTRLPT_EVT_START_CALIBRATION, /**< rcvd start calibration opcode, the application needs, at the end ot the calibration to call ble_sc_ctrlpt_send_rsp. */
-} ble_sc_ctrlpt_evt_type_t;
-
-
-/**@brief Speed and Cadence Control point event. */
-typedef struct
-{
- ble_sc_ctrlpt_evt_type_t evt_type; /**< Type of event. */
- union
- {
- ble_sensor_location_t update_location;
- uint32_t cumulative_value;
- }params;
-} ble_sc_ctrlpt_evt_t;
-
-
-/** Speed and Cadence Control Point operator code (see RSC service specification)*/
-typedef enum {
- BLE_SCPT_SET_CUMULATIVE_VALUE = 0x01, /**< Operator to set a given cumulative value. */
- BLE_SCPT_START_AUTOMATIC_CALIBRATION = 0x02, /**< Operator to start automatic calibration. */
- BLE_SCPT_UPDATE_SENSOR_LOCATION = 0x03, /**< Operator to update the sensor location. */
- BLE_SCPT_REQUEST_SUPPORTED_SENSOR_LOCATIONS = 0x04, /**< Operator to request the supported sensor locations. */
- BLE_SCPT_RESPONSE_CODE = 0x10, /**< Response Code. */
-} ble_scpt_operator_t;
-
-
-/** Speed and Cadence Control Point response parameter (see RSC service specification)*/
-typedef enum {
- BLE_SCPT_SUCCESS = 0x01, /**< Sucess Response. */
- BLE_SCPT_OP_CODE_NOT_SUPPORTED = 0x02, /**< Error Response received opcode not supported. */
- BLE_SCPT_INVALID_PARAMETER = 0x03, /**< Error Response received parameter invalid. */
- BLE_SCPT_OPERATION_FAILED = 0x04, /**< Error Response operation failed. */
-} ble_scpt_response_t;
-
-
-/** Speed and Cadence Control Point procedure status (indicates is a procedure is in progress or not and which procedure is in progress*/
-typedef enum {
- BLE_SCPT_NO_PROC_IN_PROGRESS = 0x00, /**< No procedure in progress. */
- BLE_SCPT_AUTOMATIC_CALIB_IN_PROGRESS = 0x01, /**< Automatic Calibration is in progress. */
- BLE_SCPT_INDICATION_PENDING = 0x02, /**< Control Point Indication is pending. */
- BLE_SCPT_IND_CONFIRM_PENDING = 0x03, /**< Waiting for the indication confirmation. */
-}ble_scpt_procedure_status_t;
-
-/**@brief Speed and Cadence Control point event handler type. */
-typedef ble_scpt_response_t (*ble_sc_ctrlpt_evt_handler_t) (ble_sc_ctrlpt_t * p_sc_ctrlpt,
- ble_sc_ctrlpt_evt_t * p_evt);
-
-
-typedef struct{
- ble_scpt_operator_t opcode;
- uint32_t cumulative_value;
- ble_sensor_location_t location;
-}ble_sc_ctrlpt_val_t;
-
-
-typedef struct{
- ble_scpt_operator_t opcode;
- ble_scpt_response_t status;
- ble_sensor_location_t location_list[BLE_NB_MAX_SENSOR_LOCATIONS];
-}ble_sc_ctrlpt_rsp_t;
-
-
-
-#define BLE_SRV_SC_CTRLPT_SENSOR_LOCATIONS_OP_SUPPORTED 0x01 /**< Support for sensor location related operations */
-#define BLE_SRV_SC_CTRLPT_CUM_VAL_OP_SUPPORTED 0x02 /**< Support for setting cumulative value related operations */
-#define BLE_SRV_SC_CTRLPT_START_CALIB_OP_SUPPORTED 0x04 /**< Support for starting calibration related operations */
-
-
-/**@brief Speed and Cadence Control Point init structure. This contains all options and data
-* needed for initialization of the Speed and Cadence Control Point module. */
-typedef struct
-{
- ble_srv_cccd_security_mode_t sc_ctrlpt_attr_md; /**< Initial security level for cycling speed and cadence control point attribute */
- uint8_t supported_functions; /**< supported control point functionnalities see @ref BLE_SRV_SC_CTRLPT_SUPP_FUNC. */
- uint16_t service_handle; /**< Handle of the parent service (as provided by the BLE stack). */
- ble_sc_ctrlpt_evt_handler_t evt_handler; /**< event handler */
- ble_sensor_location_t *list_supported_locations; /**< list of supported sensor locations.*/
- uint8_t size_list_supported_locations; /**< number of supported sensor locations in the list.*/
- uint16_t sensor_location_handle; /**< handle for the sensor location characteristic (if sensor_location related operation are supported).*/
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
-} ble_cs_ctrlpt_init_t;
-
-
-/**@brief Speed and Cadence Control Point response indication structure. */
-typedef struct
-{
- ble_scpt_response_t status; /**< control point response status .*/
- uint8_t len; /**< control point response length .*/
- uint8_t encoded_ctrl_rsp[BLE_SC_CTRLPT_MAX_LEN]; /**< control point encoded response.*/
-}ble_sc_ctrlpt_resp_t;
-
-
-/**@brief Speed and Cadence Control Point structure. This contains various status information for
- * the Speed and Cadence Control Point behavior. */
-typedef struct ble_sc_ctrlpt_s
-{
- uint8_t supported_functions; /**< supported control point functionnalities see @ref BLE_SRV_SC_CTRLPT_SUPP_FUNC. */
- uint16_t service_handle; /**< Handle of the parent service (as provided by the BLE stack). */
- ble_gatts_char_handles_t sc_ctrlpt_handles; /**< Handles related to the Speed and Cadence Control Point characteristic. */
- uint16_t conn_handle; /**< Handle of the current connection (as provided by the BLE stack, is BLE_CONN_HANDLE_INVALID if not in a connection). */
- ble_sensor_location_t list_supported_locations[BLE_NB_MAX_SENSOR_LOCATIONS]; /**< list of supported sensor locations.*/
- uint8_t size_list_supported_locations; /**< number of supported sensor locations in the list.*/
- ble_sc_ctrlpt_evt_handler_t evt_handler; /**< Handle of the parent service (as provided by the BLE stack). */
- uint16_t sensor_location_handle; /**< handle for the sensor location characteristic (if sensor_location related operation are supported).*/
- ble_scpt_procedure_status_t procedure_status; /**< status of possible procedure*/
- ble_srv_error_handler_t error_handler; /**< Function to be called in case of an error. */
- ble_sc_ctrlpt_resp_t response; /**< pending response data.*/
-} ble_sc_ctrlpt_t;
-
-#define SCPT_OPCODE_POS 0 /**< Request opcode position. */
-#define SCPT_PARAMETER_POS 1 /**< Request parameter position. */
-
-#define SCPT_RESPONSE_REQUEST_OPCODE_POS 1 /**< Response position of requested opcode. */
-#define SCPT_RESPONSE_CODE_POS 2 /**< Response position of response code. */
-#define SCPT_RESPONSE_PARAMETER 3 /**< Response position of response parameter. */
-
-#define SCPT_MIN_RESPONSE_SIZE 3 /**< Minimum size for control point response. */
-#define SCPT_MAX_RESPONSE_SIZE (SCPT_MIN_RESPONSE_SIZE + NB_MAX_SENSOR_LOCATIONS) /**< Maximum size for control point response. */
-
-
-/**@brief Function for Initializing the Speed and Cadence Control Point.
- *
- * @details Function for Initializing the Speed and Cadence Control Point.
- * @param[in] p_sc_ctrlpt Speed and Cadence Control Point structure.
- * @param[in] p_cscs_init Information needed to initialize the control point behavior.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_sc_ctrlpt_init(ble_sc_ctrlpt_t * p_sc_ctrlpt,
- const ble_cs_ctrlpt_init_t * p_sc_ctrlpt_init);
-
-
-/**@brief Function for sending a control point response.
- *
- * @details Function for sending a control point response when the control point received was
- * BLE_SCPT_START_AUTOMATIC_CALIBRATION. To be called after the calibration procedure is finished.
- *
- * @param[in] p_sc_ctrlpt Speed and Cadence Control Point structure.
- * @param[in] response_status status to include in the control point response.
- */
-uint32_t ble_sc_ctrlpt_rsp_send(ble_sc_ctrlpt_t * p_sc_ctrlpt, ble_scpt_response_t response_status);
-
-
-/**@brief Speed and Cadence Control Point BLE stack event handler.
- *
- * @details Handles all events from the BLE stack of interest to the Speed and Cadence Control Point.
- *
- * @param[in] p_sc_ctrlpt Speed and Cadence Control Point structure.
- * @param[in] p_ble_evt Event received from the BLE stack.
- */
-void ble_sc_ctrlpt_on_ble_evt(ble_sc_ctrlpt_t * p_sc_ctrlpt, ble_evt_t * p_ble_evt);
-
-
-#endif // BLE_SC_CTRLPT_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_sensor_location.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
- /* Attention!
-* To maintain compliance with Nordic Semiconductor ASAs Bluetooth profile
-* qualification listings, this section of source code must not be modified.
-*/
-
-#ifndef BLE_SENSOR_LOCATION_H__
-#define BLE_SENSOR_LOCATION_H__
-
-typedef enum {
- BLE_SENSOR_LOCATION_OTHER = 0 , /**<-- Other */
- BLE_SENSOR_LOCATION_TOP_OF_SHOE = 1 , /**<-- Top of shoe */
- BLE_SENSOR_LOCATION_IN_SHOE = 2 , /**<-- In shoe */
- BLE_SENSOR_LOCATION_HIP = 3 , /**<-- Hip */
- BLE_SENSOR_LOCATION_FRONT_WHEEL = 4 , /**<-- Front Wheel */
- BLE_SENSOR_LOCATION_LEFT_CRANK = 5 , /**<-- Left Crank */
- BLE_SENSOR_LOCATION_RIGHT_CRANK = 6 , /**<-- Right Crank */
- BLE_SENSOR_LOCATION_LEFT_PEDAL = 7 , /**<-- Left Pedal */
- BLE_SENSOR_LOCATION_RIGHT_PEDAL = 8 , /**<-- Right Pedal */
- BLE_SENSOR_LOCATION_FRONT_HUB = 9 , /**<-- Front Hub */
- BLE_SENSOR_LOCATION_REAR_DROPOUT = 10, /**<-- Rear Dropout */
- BLE_SENSOR_LOCATION_CHAINSTAY = 11, /**<-- Chainstay */
- BLE_SENSOR_LOCATION_REAR_WHEEL = 12, /**<-- Rear Wheel */
- BLE_SENSOR_LOCATION_REAR_HUB = 13, /**<-- Rear Hub */
-}ble_sensor_location_t;
-
-#define BLE_NB_MAX_SENSOR_LOCATIONS 14
-
-#endif // BLE_SENSOR_LOCATION_H__
--- a/hw/nRF51822n/nordic/nrf-sdk/ble/ble_services/ble_tps.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_tps TX Power Service
- * @{
- * @ingroup ble_sdk_srv
- * @brief TX Power Service module.
- *
- * @details This module implements the TX Power Service with the TX Power Level characteristic.
- * During initialization it adds the TX Power Service and TX Power Level characteristic
- * with the specified initial value to the BLE stack database.
- *
- * It provides a function for letting the application update the TX Power Level
- * characteristic.
- *
- * @note Attention!
- * To maintain compliance with Nordic Semiconductor ASA Bluetooth profile
- * qualification listings, this section of source code must not be modified.
- */
-
-#ifndef BLE_TPS_H__
-#define BLE_TPS_H__
-
-#include <stdint.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-
-/**@brief TX Power Service init structure. This contains all options and data needed for
- * initialization of the service. */
-typedef struct
-{
- int8_t initial_tx_power_level; /**< Initial value of the TX Power Level characteristic (in dBm). */
- ble_srv_security_mode_t tps_attr_md; /**< Initial Security Setting for TX Power Service Characteristics. */
-} ble_tps_init_t;
-
-/**@brief TX Power Service structure. This contains various status information for the service. */
-typedef struct
-{
- uint16_t service_handle; /**< Handle of TX Power Service (as provided by the BLE stack). */
- ble_gatts_char_handles_t tx_power_level_handles; /**< Handles related to the TX Power Level characteristic. */
-} ble_tps_t;
-
-/**@brief Function for initializing the TX Power Service.
- *
- * @param[out] p_tps TX Power Service structure. This structure will have to be supplied by
- * the application. It will be initialized by this function, and will later
- * be used to identify this particular service instance.
- * @param[in] p_tps_init Information needed to initialize the service.
- *
- * @return NRF_SUCCESS on successful initialization of service, otherwise an error code.
- */
-uint32_t ble_tps_init(ble_tps_t * p_hrs, const ble_tps_init_t * p_tps_init);
-
-/**@brief Function for setting the state of the Sensor Contact Detected bit.
- *
- * @param[in] p_tps TX Power Service structure.
- * @param[in] tx_power_level New TX Power Level (unit dBm, range -100 to 20).
- *
- * @return NRF_SUCCESS on success, otherwise an error code.
- */
-uint32_t ble_tps_tx_power_level_set(ble_tps_t * p_tps, int8_t tx_power_level);
-
-#endif // BLE_TPS_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/boards.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,31 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ -#ifndef BOARDS_H -#define BOARDS_H - -#include "nordic_global.h" - -#if defined(BOARD_NRF6310) - #include "boards/nrf6310.h" -#elif defined(BOARD_PCA10000) - #include "boards/pca10000.h" -#elif defined(BOARD_PCA10001) - #include "boards/pca10001.h" -#elif defined(BOARD_PCA10003) - #include "boards/pca10003.h" -#elif defined(BOARD_PCA1000x) - #include "boards/pca1000x.h" -#else -#error "Board is not defined" -#endif - -#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/boards/nrf6310.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,51 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ -#ifndef NRF6310_H__ -#define NRF6310_H__ - -#include "nrf_gpio.h" - -#define LED_START 8 -#define LED_0 8 -#define LED_1 9 -#define LED_2 10 -#define LED_3 11 -#define LED_4 12 -#define LED_5 13 -#define LED_6 14 -#define LED_7 15 -#define LED_STOP 15 - -#define BUTTON_START 0 -#define BUTTON_0 0 -#define BUTTON_1 1 -#define BUTTON_2 2 -#define BUTTON_3 3 -#define BUTTON_4 4 -#define BUTTON_5 5 -#define BUTTON_6 6 -#define BUTTON_7 7 -#define BUTTON_STOP 7 -#define BUTTON_PULL NRF_GPIO_PIN_NOPULL - -#define RX_PIN_NUMBER 16 // UART RX pin number. -#define TX_PIN_NUMBER 17 // UART TX pin number. -#define CTS_PIN_NUMBER 18 // UART Clear To Send pin number. Not used if HWFC is set to false -#define RTS_PIN_NUMBER 19 // Not used if HWFC is set to false -#define HWFC false // UART hardware flow control - -#define SPIS_MISO_PIN 20 // SPI MISO signal. -#define SPIS_CSN_PIN 21 // SPI CSN signal. -#define SPIS_MOSI_PIN 22 // SPI MOSI signal. -#define SPIS_SCK_PIN 23 // SPI SCK signal. - -#endif // NRF6310_H__
--- a/hw/nRF51822n/nordic/nrf-sdk/boards/pca10000.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,36 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ -#ifndef PCA10000_H -#define PCA10000_H - -// Definitions for PCA10000 v2.0.0 or higher -#if 1 -#define LED_RGB_RED 21 -#define LED_RGB_GREEN 22 -#define LED_RGB_BLUE 23 - -#define RX_PIN_NUMBER 11 -#define TX_PIN_NUMBER 9 -#define CTS_PIN_NUMBER 10 -#define RTS_PIN_NUMBER 8 -#define HWFC true - -// Definitions for PCA10000 v1.0 -#else -#define RX_PIN_NUMBER 3 -#define TX_PIN_NUMBER 1 -#define CTS_PIN_NUMBER 2 -#define RTS_PIN_NUMBER 0 -#define HWFC true -#endif - -#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/boards/pca10001.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,34 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ -#ifndef PCA10001_H -#define PCA10001_H - -#include "nrf_gpio.h" - -#define LED_START 18 -#define LED_0 18 -#define LED_1 19 -#define LED_STOP 19 - -#define BUTTON_START 16 -#define BUTTON_0 16 -#define BUTTON_1 17 -#define BUTTON_STOP 17 -#define BUTTON_PULL NRF_GPIO_PIN_PULLUP - -#define RX_PIN_NUMBER 11 -#define TX_PIN_NUMBER 9 -#define CTS_PIN_NUMBER 10 -#define RTS_PIN_NUMBER 8 -#define HWFC false - -#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/boards/pca10003.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,34 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ -#ifndef PCA10003_H -#define PCA10003_H - -#include "nrf_gpio.h" - -#define LED_START 18 -#define LED_0 18 -#define LED_1 19 -#define LED_STOP 19 - -#define BUTTON_START 16 -#define BUTTON_0 16 -#define BUTTON_1 17 -#define BUTTON_STOP 17 -#define BUTTON_PULL NRF_GPIO_PIN_PULLUP - -#define RX_PIN_NUMBER 11 -#define TX_PIN_NUMBER 9 -#define CTS_PIN_NUMBER 10 -#define RTS_PIN_NUMBER 8 -#define HWFC true - -#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/boards/pca1000x.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,34 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ -#ifndef PCA1000x_H -#define PCA1000x_H - -#include "nrf_gpio.h" - -#define LED_START 18 -#define LED_0 18 -#define LED_1 19 -#define LED_STOP 19 - -#define BUTTON_START 16 -#define BUTTON_0 16 -#define BUTTON_1 17 -#define BUTTON_STOP 17 -#define BUTTON_PULL NRF_GPIO_PIN_PULLUP - -#define RX_PIN_NUMBER 11 -#define TX_PIN_NUMBER 9 -#define CTS_PIN_NUMBER 10 -#define RTS_PIN_NUMBER 8 -#define HWFC true - -#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/common.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,39 +0,0 @@ - /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef COMMON_H -#define COMMON_H - -/*lint ++flb "Enter library region" */ - -#include <stdbool.h> -#include <stdint.h> -#include "nordic_global.h" - -/* @file -* @brief Common header file for generic macros and definitions - * - */ - -/* - * GPIO glue macros, this can be used to define a pin number in source/header file and use that macro for pin - * configuration using this expansion. - * example: - * #define RESET_PIN 8 - * NRF_GPIO->PINCNF(RESET_PIN) = XXX ; // Expanded NRF_GPIO->PIN_CNF[8] = XXX - */ -#define PINX_GLUE(x, y, z) x##y##_##z /*!< first level glue for pin macros */ -#define PINCNF(p) PINX_GLUE(PIN,p,CNF) /*!< gpio configure pin number 'p' */ -#define PINOUT(p) PINX_GLUE(PIN,p,OUT) /*!< gpio out pin number 'p' */ - -/*lint --flb "Leave library region" */ -#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/compiler_abstraction.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-
-#ifndef _COMPILER_ABSTRACTION_H
-#define _COMPILER_ABSTRACTION_H
-
-#include "nordic_global.h"
-
-/*lint ++flb "Enter library region" */
-
-#if defined ( __CC_ARM )
-
- #ifndef __ASM
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #endif
-
- #ifndef __INLINE
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #endif
-
- #define GET_SP() __current_sp() /*!> read current SP function for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
-
- #ifndef __ASM
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #endif
-
- #ifndef __INLINE
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #endif
-
- #define GET_SP() __get_SP() /*!> read current SP function for IAR Compiler */
-
-#elif defined ( __GNUC__ )
-
- #ifndef __ASM
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #endif
-
- #ifndef __INLINE
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #endif
-
- #define GET_SP() gcc_current_sp() /*!> read current SP function for GNU Compiler */
-
- static inline unsigned int gcc_current_sp(void)
- {
- register unsigned sp asm("sp");
- return sp;
- }
-
-#elif defined ( __TASKING__ )
-
- #ifndef __ASM
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #endif
-
- #ifndef __INLINE
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #endif
-
- #define GET_SP() __get_MSP() /*!> read current SP function for TASKING Compiler */
-
-#endif
-
-/*lint --flb "Leave library region" */
-
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/console.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,344 +0,0 @@ -/* Copyright (c) 2007 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - - -/** \file - * - * \section console_description Description - * - * Higher-level functions for writing to, and reading from, the UART. - * - * Lower-level functions are provided by hal_uart.h and its implementations, - * which this module uses to obtain hardware indpendency. - * - * Before the other functions of this module is used, the module must be initialized - * by calling console_init(). - * Also, the interrupt used by the UART must be enabled. - * - * Functions for writing to the UART have a "put" infix, functions for reading - * from he UART a "get" infix. - * - * The newline problem is of interest. See e.g. - * <URL: http://en.wikipedia.org/wiki/Newline >. - * The newline style used by default by this module is ASCII CR and LF (x0D x0A). - * The module may be configured to use other newline styles, including setting different - * newline styles for input and output, see the section on configuration further below. - * - * To print a newline only, call console_put_newline(), or console_put_line() with a - * properly casted empty string as argument: - * - console_put_newline() - * - console_put_line((uint8_t *)"") - * - * The newline solution is not completely general, see the comments to console_get_line(). - * - * End-of-file and end-of-file representation may also be of concern. This has not been - * dealt with in any way in this module. - * - * This module provides optional echo of input to output. This may e.g. be used to enable - * the other part to see what is sent from that side (if other part does not have local echo) - * or to ensure that the UART communication is working. See the configuration section for - * info on how to turn on this feature. - * - * A note on input-to-output echo and newline: If echo is enabled and an input newline is read, - * an output newline, which may be different (dependent upon module configuration), is echoed - * back. - * - * A note on terminology: In this file, what is meant by a "string" is a zero-terminated - * sequence (an array) of characters (or octets). This as opposed to a sequence of characters - * without such termination. - * - * String constants (like "this one") are (per the C standard) of type "array of character". - * Therefore, Lint may complain if string constants are used as arguments to the functions - * in this module. To avoid this, cast the string to uint8_t like this: - * console_put_string((uint8_t *)"this one"). - * - * \section console_configuration Configuration - * - * The module may be configured by the use of suitable defines. To change the newline style - * used, define CONSOLE_NEWLINE_INPUT and CONSOLE_NEWLINE_OUTPUT to suitable values. (See - * this file (console.h) for possible values.) To enable echoing of input to output, define - * CONSOLE_ENABLE_ECHO. - * - * \section console_note Note - * - * The console functions that access the UART driver will enable the rewired - * interrupts for the driver. This ensures that the driver will not stall and - * lock the program. The interrupts will be restored to their former value - * before returning to the caller in each instance that this is used. - * - */ - -#ifndef CONSOLE_H__ -#define CONSOLE_H__ - -#include <stdint.h> -#include <stdbool.h> -#include "nordic_global.h" - -/* Newline character sequences */ -#define CONSOLE_NEWLINE_CRLF "\r\n" //!< CRLF newline -#define CONSOLE_NEWLINE_CR "\r" //!< CR newline -#define CONSOLE_NEWLINE_LF "\n" //!< LF newline -#define CONSOLE_NEWLINE_CRLF_NUMERIC "\x0D\x0A" //!< Hardcoded ASCII values for CRLF -#define CONSOLE_NEWLINE_CR_NUMERIC "\x0D" //!< It is possible, though unlikely, that -#define CONSOLE_NEWLINE_LF_NUMERIC "\x0A" //!< CR and LF do not equal these values. - -#define CONSOLE_NEWLINE_DEFAULT CONSOLE_NEWLINE_CRLF_NUMERIC /*!< Default newline style */ - -/* Newline style for input */ -#ifndef CONSOLE_NEWLINE_INPUT - /* CONSOLE_NEWLINE_INPUT was not defined in console_config.h */ - #define CONSOLE_NEWLINE_INPUT CONSOLE_NEWLINE_DEFAULT //!< Newline style for input -#endif - -/* Newline style for output */ -#ifndef CONSOLE_NEWLINE_OUTPUT - /* CONSOLE_NEWLINE_OUTPUT was not defined in console_config.h */ - #define CONSOLE_NEWLINE_OUTPUT CONSOLE_NEWLINE_DEFAULT //!< Newline style for output -#endif - -/** - * @brief Function for initializing the console. - * Init must be called prior to any other console functions. - * The success of init() can be tested using the console_available() function. - * console_init() is idempotent (can be called multiple times) - * \post Interrupts required for the console I/O device (UART) are enabled. -*/ -void console_init(void); - -/** \brief Function for testing if the console is available. - * - * \return true if console is initialised and I/O peripheral is initialised - * \return false if console is not initialised or I/O peripheral init failed. -*/ -bool console_available(void); - - -/** \brief Function for printing a string. - * - * Print a zero-terminated string of characters (octets). - * - * \param[in] string Pointer to the string. - * \pre only works if init() previously called - */ -void console_put_string(uint8_t const * string); - - -/** \brief Function for printing a string and newline. - * - * Print a zero-terminated string of characters (octets) - * and thereafter the output newline sequence. - * - * \param[in] string Pointer to the string. - * \pre only works if init() previously called - */ -void console_put_line(uint8_t const * string); - - -/** \brief Function for printing a newline (the newline output sequence). - * \pre only works if init() previously called - */ -void console_put_newline(void); - - -/** \brief Function for printing a number of characters (octets). - * - * \param[in] chars Pointer to the characters - * \param[in] num_chars Number of characters to print - * \pre only works if init() previously called - */ -void console_put_chars(uint8_t const * chars, uint8_t num_chars); - - -/** \brief Function for reading a number of characters (octets) and append zero-termination. - * - * \param[out] string Pointer to characters - * \param[in] num_chars Number of characters to read. - * \warning: Note that due to the appended zero termination, there must - * be room for num_chars + 1 octets in the space pointed to by argument chars. - * \pre only works if init() previously called - */ -void console_get_string(uint8_t * string, uint8_t num_chars); - -/** \brief Function for reading a line. - * - * Read characters until end of line or until a maximum number - * of characters have been read, whatever comes first. - * The characters read are returned as a zero-terminated string - * (withouth the newline). - * - * \warning The function has a limitation in that it assumes that if the - * start of a newline sequence is found, the rest of the newline sequence must - * follow. The consequence of this is that if a leading part of the newline - * sequence (the "leading part") is found in the input, followed by something - * that is not the rest of the newline sequence, both the leading part and - * the first part of what follows will be silently discarded. - * (The practical reason for this behaviour is the limitation on string length - * given by the max_len parameter combined with the fact that hal_uart does not - * provide a means of "putting back" already read characters. It is - * possible to implement the function is such a way that this limitation would - * apply only when the string is too full to fit a number of characters equal to - * the number of characters in a newline sequence. Letting it apply all the time - * seems more consistent, though.) - * - * \param[out] string Pointer to the string - * \param[in] max_len Maximum length of string, including zero terminator. - * Note that max_len must be at least two (max_len >= 2). - * \pre only works if init() previously called - */ -void console_get_line(uint8_t * string, uint8_t max_len); - -/** \brief Function for getting number of characters sent to console. - * - * - * \return Number of characters (0..255) -*/ -bool console_chars_available(void); - -/** \brief Function for reading a number of characters (octets). - * - * \param[out] chars Pointer to characters - * \param[in] num_chars Number of characters to read - * \pre only works if init() previously called - */ -void console_get_chars(uint8_t * chars, uint8_t num_chars); - - -/** \brief Function for writing a single character (octet). - * - * This function is nothing but a direct wrapper for hal_uart_putchar(). - * It is provided here for completeness only. You may consider to use - * hal_uart_putchar() directly instead. - * \param ch Character to write - * \pre only works if init() previously called - */ -void console_put_char(uint8_t ch); - - -/** \brief Function for reading a single character (octet). - * - * This function is a wrapper for hal_uart_getchar(), with the additional opption - * of echo of input to output (if the console module is so configured, see the - * module documentation). - * \pre only works if init() previously called - * \return Read character - */ -uint8_t console_get_char(void); - - -/** \brief Function for printing the decimal ASCII representation of an 8-bit number. - * - * \warning: This function is larger and more complex than the corresponding - * functions to write hexadecimal representations. - * - * \param b Number in the range [0 255] - * \pre only works if init() previously called - */ -void console_put_decbyte(uint8_t b); - - -/** \brief Function for printing the decimal ASCII representation of a 16-bit number. - * - * \warning: This function is larger and more complex than the corresponding - * functions to write hexadecimal representations. - * - * \param w Number in the range [0 65535] - * \pre only works if init() previously called - */ -void console_put_decword(uint16_t w); - - -/** \brief Function for printing the decimal ASCII representation of a 32-bit number. - * - * \warning: This function is larger and more complex than the corresponding - * functions to write hexadecimal representations. - * - * \param ww Number in the range [0 4294967295] - * \pre only works if init() previously called - */ -void console_put_dec32bit(uint32_t ww); - - -/** \brief Function for printing the hexadecimal ASCII representation of a nibble (half an octet, four bits). - * - * Four bits (a nibble) equals one hexadecimal digit. - * - * \param n A number from zero to 15, both inclusive - * \pre only works if init() previously called - */ -void console_put_hexnybble(uint8_t n); - - -/** \brief Function for printing the hexadecimal ASCII representation of a byte (an octet). - * - * \param b A byte (an octet) - */ -void console_put_hexbyte(uint8_t b); - - -/** \brief Function for printing the hexadecimal ASCII representation of a word (two octets). - * - * \param w A word (sixten-bits, two octets) - */ -void console_put_hexword(uint16_t w); - -/** \brief Function for printing a string of hexbytes. - * - * \param p a pointer to the first element - * \param n the length of the array - */ -void console_put_hexbytearray(uint8_t* p, uint8_t n); - -/** \brief Function for reading one hexadecimal digit. - * - * Read the hexadecimal ASCII representation of a nibble (half an octet, four bits) - * - * \warning: The function returns zero on invalid input (i.e. input that is not an - * hexadecimal digit). - * - * \return A number from zero to 15, both inclusive - * \pre only works if init() previously called - */ -uint8_t console_get_hexnybble(void); - - -/** \brief Function for reading two hexadecimal digits. - * - * Read the hexadecimal ASCII representation of a byte (an octet) - * - * \warning: Invalid input: Input characters that are not hexadecimal digits - * are treated as the hexadecimal digit zero. - * - * \return A number from zero to 255, both inclusive - */ -uint8_t console_get_hexbyte(void); - - -/** \brief Function for reading four hexadecimal digits. - * - * Read the hexadecimal ASCII representation of a word (16 bits) - * - * \warning: Invalid input: Input characters that are not hexadecimal digits - * are treated as the hexadecimal digit zero. - * - * \return A number from zero to 65535, both inclusive - */ -uint16_t console_get_hexword(void); - -/** \brief Function for checking if the last tx is completed. - * - * \return TRUE, if the tx is completed, FALSE, is the Tx is in progress - */ -bool console_tx_completed(void); - -#endif -
--- a/hw/nRF51822n/nordic/nrf-sdk/esb/nrf_esb.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,697 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- * $LastChangedRevision: 19572 $
- */
-
-
-/**
- * @file
- * @brief Enhanced ShockBurst API.
- *
-*/
-
-#ifndef NRF_ESB_H__
-#define NRF_ESB_H__
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "nrf_esb_constants.h"
-
-
-/**
- * @defgroup esb_02_api Application Programming Interface (API)
- * @{
- * @ingroup modules_02_esb
- * @brief Enhanced ShockBurst Application Programming Interface (API).
-*/
-
-
-/**
- * @enum nrf_esb_mode_t
- * @brief Enumerator used for selecting the ESB mode.
- */
-typedef enum
-{
- NRF_ESB_MODE_PTX, ///< Primary Transmitter mode
- NRF_ESB_MODE_PRX, ///< Primary Receiver mode
-} nrf_esb_mode_t;
-
-
-/**
- * @enum nrf_esb_packet_t
- * @brief Enumerator used for selecting TX packet type used in
- * PTX mode.
- */
-typedef enum
-{
- NRF_ESB_PACKET_USE_ACK, ///< PTX packet requires ACK.
- NRF_ESB_PACKET_NO_ACK, ///< PTX packet does not require ACK.
-} nrf_esb_packet_t ;
-
-
-/**
- * @enum nrf_esb_base_address_length_t
- * @brief Enumerator used for selecting the base address length.
- */
-typedef enum
-{
- NRF_ESB_BASE_ADDRESS_LENGTH_2B, ///< 2 byte address length
- NRF_ESB_BASE_ADDRESS_LENGTH_3B, ///< 3 byte address length
- NRF_ESB_BASE_ADDRESS_LENGTH_4B ///< 4 byte address length
-} nrf_esb_base_address_length_t;
-
-
-/**
- * @enum nrf_esb_output_power_t
- * @brief Enumerator used for selecting the TX output power.
- */
-typedef enum
-{
- NRF_ESB_OUTPUT_POWER_4_DBM, ///< 4 dBm output power.
- NRF_ESB_OUTPUT_POWER_0_DBM, ///< 0 dBm output power.
- NRF_ESB_OUTPUT_POWER_N4_DBM, ///< -4 dBm output power.
- NRF_ESB_OUTPUT_POWER_N8_DBM, ///< -8 dBm output power.
- NRF_ESB_OUTPUT_POWER_N12_DBM, ///< -12 dBm output power.
- NRF_ESB_OUTPUT_POWER_N16_DBM, ///< -16 dBm output power.
- NRF_ESB_OUTPUT_POWER_N20_DBM ///< -20 dBm output power.
-} nrf_esb_output_power_t;
-
-
-/**
- * @enum nrf_esb_datarate_t
- * @brief Enumerator used for selecting the radio data rate.
- */
-typedef enum
-{
- NRF_ESB_DATARATE_250_KBPS, ///< 250 Kbps datarate
- NRF_ESB_DATARATE_1_MBPS, ///< 1 Mbps datarate
- NRF_ESB_DATARATE_2_MBPS, ///< 1 Mbps datarate
-} nrf_esb_datarate_t;
-
-
-/**
- * @enum nrf_esb_crc_length_t
- * @brief Enumerator used for selecting the CRC length.
- */
-typedef enum
-{
- NRF_ESB_CRC_OFF, ///< CRC check disabled
- NRF_ESB_CRC_LENGTH_1_BYTE, ///< CRC check set to 8-bit
- NRF_ESB_CRC_LENGTH_2_BYTE ///< CRC check set to 16-bit
-} nrf_esb_crc_length_t;
-
-/**
- * @enum nrf_esb_xosc_ctl_t
- * @brief Enumerator used for specifying whether switching the
- * external 16 MHz oscillator on/off shall be handled automatically
- * inside ESB or manually by the application.
- */
-typedef enum
-{
- NRF_ESB_XOSC_CTL_AUTO, ///< Switch XOSC on/off automatically
- NRF_ESB_XOSC_CTL_MANUAL ///< Switch XOSC on/off manually
-} nrf_esb_xosc_ctl_t;
-
-/******************************************************************************/
-/** @name General API functions
- * @{ */
-/******************************************************************************/
-
-/**
- * @brief Initialize ESB.
- *
- * @param mode The mode to initialize ESB in.
- *
- * @retval true If ESB initialized.
- * @retval false If ESB failed to initialize.
- */
-bool nrf_esb_init(nrf_esb_mode_t mode);
-
-
-/**
- * @brief Enable ESB.
- *
- * Equivalent to setting CE high in legacy ESB.
- *
- * When enabled the behaviour described for the current ESB mode will apply.
- */
-void nrf_esb_enable(void);
-
-/**
- * @brief Disable ESB.
- *
- * Equivalent to setting CE low in legacy ESB.
- *
- * When calling this function ESB will begin disabling,
- * and will be fully disabled when ESB calls nrf_esb_disabled().
- * If there are any pending notifications (callbacks) , or if any new notifications
- * are being added to the internal notification queue while ESB is disabling,
- * these will be sent to the application before ESB is fully disabled.
- *
- * After ESB has been fully disabled, no more notifications will be
- * sent to the application.
- */
-void nrf_esb_disable(void);
-
-/** Check whether ESB is enabled or disabled.
- *
- * @retval true If ESB is enabled.
- * @retval false If ESB is disabled.
- */
-bool nrf_esb_is_enabled(void);
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name functions
- * @{ */
-/******************************************************************************/
-
-/**
- * @brief TX success callback.
- *
- * In PTX mode this function is called after the PTX has sent a packet
- * and received the corresponding ACK packet from a PRX.
- *
- * In PRX mode this function is called after a payload in ACK is assumed
- * successfully transmitted, that is when the PRX received a new packet
- * (new PID or CRC) and the previous ACK sent to a PTX contained a
- * payload.
- *
- * @param tx_pipe The pipe on which the ACK packet was received.
- *
- * @param rssi Received signal strength indicator in dBm of measured ACK.
- *
- * As the RSSI measurement requires a minimum on-air duration of the received
- * packet, the measured RSSI value will not be reliable when ALL of the following
- * criteria are met:
- *
- * - Datarate = 2 Mbps
- * - Payload length = 0
- * - CRC is off
- *
- */
-void nrf_esb_tx_success(uint32_t tx_pipe, int32_t rssi);
-
-
-/**
- * @brief TX failed callback (PTX mode only).
- *
- * This is called after the maximum number of TX attempts
- * were reached for a packet. The packet is deleted from the TX FIFO.
- *
- * Note that when NRF_ESB_PACKET_NO_ACK is used this callback is
- * always made after sending a packet.
- * @sa nrf_esb_set_max_number_of_tx_attempts().
- *
- * @param tx_pipe The pipe that failed to send a packet.
- */
-void nrf_esb_tx_failed(uint32_t tx_pipe);
-
-
-/**
- * @brief RX data ready callback.
- *
- * PTX mode: This is called after an ACK is received from a PRX containing a
- * payload.
- *
- * PRX mode: This is called after a packet is received from a PTX ACK is
- * received from a PRX containing a payload.
- *
- * @param rx_pipe is the pipe on which a packet was received.
- * This value must be < NRF_ESB_CONST_PIPE_COUNT.
- *
- * @param rssi Received signal strength indicator in dBm of packet.
- *
- * As the RSSI measurement requires a minimum on-air duration of the received
- * packet, the measured RSSI value will not be reliable when ALL of the following
- * criteria are met:
- *
- * - Datarate = 2 Mbps
- * - Payload length = 0
- * - CRC is off
- *
- */
-void nrf_esb_rx_data_ready(uint32_t rx_pipe, int32_t rssi);
-
-
-/**
- * @brief Disabled callback.
- *
- * This is called after ESB enters the disabled state.
- * There is no further CPU use by ESB, the radio is disabled and the timer is
- * powered down.
- */
-void nrf_esb_disabled(void);
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Packet transmission and receiving functions
- * @{ */
-/******************************************************************************/
-
-/**
- * @brief Add a packet to the tail of the TX FIFO.
- *
- * In PTX mode, the packet will be transmitted at the next occation when ESB is enabled.
- * In PRX mode, the payload will be piggybacked to onto an ACK.
- *
- * @param payload Pointer to the payload.
- * @param payload_length The number of bytes of the payload to transmit.
- * @param pipe The pipe for which to add the payload. This value must be < NRF_ESB_CONST_PIPE_COUNT.
- * @param packet_type Specifies whether an ACK is required (ignored when in
- * PRX mode, or when the dynamic ack feature is disabled).
- * @sa nrf_esb_enable_dyn_ack()
- *
- * @retval true If the packet was successfully added to the TX FIFO.
- * @retval false If pipe was invalid, payload pointer was NULL, payload length
- was invalid, insufficient space in FIFO memory pool or
- insufficient packets in TX queue.
- */
-bool nrf_esb_add_packet_to_tx_fifo(uint32_t pipe, uint8_t * payload, uint32_t payload_length, nrf_esb_packet_t packet_type);
-
-
-/**
- * @brief Fetch a packet from the head of the RX FIFO.
- *
- * @param payload Pointer to copy the payload to.
- * @param payload_length Pointer to copy the payload length to. The
- * payload length is given in bytes (0 to NRF_ESB_CONST_MAX_PAYLOAD_LENGTH).
- * @param pipe Pipe for which to add the payload. This value must be < NRF_ESB_CONST_PIPE_COUNT.
- *
- * @retval true If the fetch was successful.
- * @retval false If there was no packet in the FIFO or the payload pointer
- * was NULL.
- */
-bool nrf_esb_fetch_packet_from_rx_fifo(uint32_t pipe, uint8_t * payload, uint32_t* payload_length);
-
-
-/**
- * @brief Get the number of packets residing in the TX FIFO on a specific
- * pipe.
- *
- * @param pipe The pipe for which to check. This value must be < NRF_ESB_CONST_PIPE_COUNT.
- *
- * @retval The number of packets in the TX FIFO for the pipe.
- */
-uint32_t nrf_esb_get_tx_fifo_packet_count(uint32_t pipe);
-
-
-/**
- * @brief Get the number of packets residing in the RX FIFO on a specific
- * pipe.
- *
- * @param pipe The pipe for which to check. This value must be < NRF_ESB_CONST_PIPE_COUNT.
- *
- * @retval The number of packets in the RX FIFO for the pipe.
- */
-uint32_t nrf_esb_get_rx_fifo_packet_count(uint32_t pipe);
-
-
-/**
- * @brief Flush the RX FIFO for a specific pipe.
- *
- * Delete all the packets and free the memory of the TX FIFO for a
- * specific pipe.
- *
- * Note that it is not allowed to flush a TX FIFO when
- * ESB is enabled.
- *
- * @param pipe The pipe for which to flush. This value must be < NRF_ESB_CONST_PIPE_COUNT.
- */
-void nrf_esb_flush_tx_fifo(uint32_t pipe);
-
-
-/**
- * @brief Flush the RX FIFO for a specific pipe.
- *
- * Delete all the packets and free the memory of the RX FIFO for a
- * specific pipe.
- *
- * @param pipe The pipe for which to flush. This value must be < NRF_ESB_CONST_PIPE_COUNT.
- */
-void nrf_esb_flush_rx_fifo(uint32_t pipe);
-
-
-/**
- * @brief Get the total number of transmission attempts
- * used for sending the previous successful packet.
- *
- * The value applies to the packet for which the latest
- * nrf_esb_tx_data_sent callback was made.
- *
- * @return The number of transmission attempts for the
- * previous transmitted packet.
- */
-uint16_t nrf_esb_get_tx_attempts(void);
-
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Configuration functions
- *
- * Configuration 'set' functions may only be called while ESB is disabled. The
- * new parameter comes into effect when ESB is enabled again.
- *
- * Configuration 'get' functions may be called at any time.
- *
- * @{ */
-/******************************************************************************/
-
-
-/**
- * @brief Set the mode.
- *
- * @param mode The mode to be used.
- * See nrf_esb_mode_t for a list of valid modes.
- *
- * @retval true if the mode was set properly.
- * @retval false if the mode is invalid.
- */
-bool nrf_esb_set_mode(nrf_esb_mode_t mode);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_mode().
- *
- * @return The current ESB mode.
- */
-nrf_esb_mode_t nrf_esb_get_mode(void);
-
-
-/**
- * @brief Set the base address length.
- *
- * @param length The base address length.
- *
- * @retval true If the address length was set.
- * @retval false If the length was invalid.
- */
-bool nrf_esb_set_base_address_length(nrf_esb_base_address_length_t length);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_base_address_length().
- *
- * @return The current base_address length.
- */
-nrf_esb_base_address_length_t nrf_esb_get_base_address_length(void);
-
-
-/**
- * @brief Set the base address for pipe 0.
- *
- * The full on-air address for each pipe is composed of a multi-byte base address
- * and a prefix address byte.
- *
- * For packets to be received correctly, the most significant byte of
- * the base address should not be an alternating sequence of 0s and 1s i.e.
- * it should not be 0x55 or 0xAA.
- *
- * @param base_address is the 4 byte base address. The parameter is
- * 4 bytes, however only the least L significant bytes are used, where L is
- * set by nrf_esb_set_base_address_length().
- *
- * @retval true if base_address_0 was set.
- * @retval false if ESB was enabled.
- */
-bool nrf_esb_set_base_address_0(uint32_t base_address);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_base_address_0().
- *
- * @return Base address 0.
- */
-uint32_t nrf_esb_get_base_address_0(void);
-
-
-/**
- * @brief Set the base address for pipes 1-7.
- *
- * Pipes 1 through 7 share base_address_1. @sa nrf_esb_set_base_address_0.
- *
- * @param base_address is the 4 byte base address. The parameter is
- * 4 bytes, however only the least L significant bytes are used, where L is
- * set by nrf_esb_set_base_address_length().
- *
- * @retval true If base_address_1 was set.
- * @retval false If ESB was enabled.
- */
-bool nrf_esb_set_base_address_1(uint32_t base_address);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_base_address_1().
- *
- * @return Base address 1.
- */
-uint32_t nrf_esb_get_base_address_1(void);
-
-
-/**
- * @brief Set the address prefix byte for a specific pipe.
- *
- * Each pipe should have its own unique prefix byte.
- *
- * @param pipe The pipe that the address should apply to. This value must be < NRF_ESB_CONST_PIPE_COUNT.
- * @param address The address prefix byte.
- *
- * @retval true If the address prefix byte was set.
- * @retval false If ESB was enabled or if the pipe was invalid.
- */
-bool nrf_esb_set_address_prefix_byte(uint32_t pipe, uint8_t address);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_address_prefix_byte().
- *
- * @param pipe the pipe for which to get the address. This value must be < NRF_ESB_CONST_PIPE_COUNT.
- * @param out_address is the pointer in which to return the address byte.
- *
- * @retval true If the value was set.
- * @retval false If ESB was enabled, or the pipe was invalid,
- * or the out_address pointer was NULL.
- */
-bool nrf_esb_get_address_prefix_byte(uint32_t pipe, uint8_t* out_address);
-
-
-/**
- * @brief Set which pipes the node shall listen on in PRX mode.
- *
- * This value is a bitmap, and each bit corresponds to a given pipe number.
- * Bit 0 set to "1" enables pipes 0, bit 1 set to "1" enables pipe 1
- * and so forth.
- * The maximum number of pipes is defined by NRF_CONST_ESB_PIPE_COUNT.
- *
- * @param pipes A bitmap specifying which pipes to monitor.
- *
- * @retval true If the bitmap was set.
- * @retval false If ESB was enabled.
- */
-bool nrf_esb_set_enabled_prx_pipes(uint32_t pipes);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_enabled_prx_pipes().
- *
- * @return Bitmap holding the current enabled pipes.
- */
-uint32_t nrf_esb_get_enabled_prx_pipes(void);
-
-
-/**
- * @brief Set the retransmission delay.
- *
- * The retransmission delay is the delay from the start of a packet
- * that failed to receive the ACK until the start of the retransmission
- * attempt.
- *
- * The minimum value of the retransmission delay is dependent of the
- * radio data rate and the payload size(s).(@sa nrf_esb_set_datarate()).
- * As a rule of thumb, when using 32 byte payloads in each direction (forward and ACK):
- *
- * - For NRF_ESB_DATARATE_2_MBPS the retransmission delay must be >= 600 us.
- * - For NRF_ESB_DATARATE_1_MBPS the retransmission delay must >= 900 us.
- * - For NRF_ESB_DATARATE_250_KBPS the retransmission delay must be >= 2700 us.
- *
- * @param delay_us The delay in microseconds between each
- * retransmission attempt.
- *
- * @retval true If the retransmit delay was set.
- * @retval false If ESB was enabled.
- */
-bool nrf_esb_set_retransmit_delay(uint32_t delay_us);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_retransmit_delay().
- *
- * @return The current retransmission delay.
- */
-uint32_t nrf_esb_get_retransmit_delay(void);
-
-
-/**
- * @brief Set the maximum number of TX attempts
- * that can be used for a single packet.
- *
- * @param attempts The maximum number of TX attempts.
- * 0 indicates that a packet can use a infinite number of attempts.
- *
- * @retval false If ESB was enabled.
- */
-bool nrf_esb_set_max_number_of_tx_attempts(uint16_t attempts);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_max_number_of_retransmits().
- *
- * @return The current number of maximum retransmission attempts.
- */
-uint16_t nrf_esb_get_max_number_of_tx_attempts(void);
-
-
-/**
- * @brief Set the Radio Frequency (RF) channel.
- *
- * The valid channels are in the range 0 <= channel <= 125, where the
- * actual centre frequency is (2400 + channel) MHz.
- *
- * @param channel The RF Channel to use.
- *
- * @return false If ESB was enabled.
- */
-bool nrf_esb_set_channel(uint32_t channel);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_channel().
- *
- * @return The current RF channel.
- */
-uint32_t nrf_esb_get_channel(void);
-
-
-/**
- * @brief Set the radio TX output power.
- *
- * @param power The output power.
- *
- * @return false If the output_power was invalid.
- */
-bool nrf_esb_set_output_power(nrf_esb_output_power_t power);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_output_power().
- *
- * @return The output power.
- */
-nrf_esb_output_power_t nrf_esb_get_output_power(void);
-
-
-/**
- * @brief Set the radio datarate.
- *
- * @param datarate Datarate.
- *
- * @retval false If the datarate was invalid.
- */
-bool nrf_esb_set_datarate(nrf_esb_datarate_t datarate);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_datarate().
- *
- * @return The current datarate.
- */
-nrf_esb_datarate_t nrf_esb_get_datarate(void);
-
-
-/**
- * @brief Set the CRC length.
- *
- * The CRC length should be the same on both PTX and PRX in order
- * to ensure correct operation.
- *
- * @param length The CRC length.
- *
- * @retval false If ESB was enabled or the length was invalid.
- */
-bool nrf_esb_set_crc_length(nrf_esb_crc_length_t length);
-
-
-/**
- * @brief Get function counterpart to nrf_esb_set_crc_length().
- *
- * @return The current CRC length.
- */
-nrf_esb_crc_length_t nrf_esb_get_crc_length(void);
-
-
-/**
- * @brief Set whether start/stop of external oscillator (XOSC) shall be handled
- * automatically inside ESB or manually by the application.
- *
- * When controlling the XOSC manually from the application it is
- * required that the XOSC is started before ESB is enabled.
- *
- * When start/stop of the XOSC is handled automatically by ESB,
- * the XOSC will only be running when needed, that is when the radio
- * is being used or when ESB needs to maintain synchronization.
- *
- * It is required that the XOSC is started in order for the radio to be
- * able to send or receive any packets.
- *
- * @param xosc_ctl setting for XOSC control.
- *
- * @retval true if the parameter was set.
- * @retval false if Gazell was enabled or the xosc_ctl value was invalid.
- */
-bool nrf_esb_set_xosc_ctl(nrf_esb_xosc_ctl_t xosc_ctl);
-
-
-/**
- * @brief Enable dynamic ACK feature. After initialization this feature is disabled.
- *
- * The dynamic ACK feature must be enabled in order for the @b packet_type
- * parameter in the nrf_esb_add_packet_to_tx_fifo() function to have any effect,
- * or for the ACK bit of received packets to be evaluated.
- *
- * When the dynamic ACK feature is disabled, all packets will be ACK'ed.
- */
-void nrf_esb_enable_dyn_ack(void);
-
-/**
- * @brief Disable dynamic ACK feature.
- *
- * @sa nrf_esb_enable_dyn_ack()
- */
-void nrf_esb_disable_dyn_ack(void);
-
-
-/**
- * Get function counterpart for nrf_esb_set_xosc_ctl();
- *
- * @return The XOSC control setting.
- */
-nrf_esb_xosc_ctl_t nrf_esb_get_xosc_ctl(void);
-
-
-/** @} */
-/** @} */
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/esb/nrf_esb_constants.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,141 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- * $LastChangedRevision: 32956 $
- */
-
-
-/**
- * @file
- * @brief Enhanced ShockBurst constants and default values.
- *
- * NOTE! Changing values here has no effect. They are only provided as a reference.
- */
-
-#ifndef NRF_ESB_CONSTANTS_H__
-#define NRF_ESB_CONSTANTS_H__
-
-/**
- * @addtogroup esb_02_api
- * @{
-*/
-
-
-/*****************************************************************************/
-/** @name Hardware resources used by Enhanced ShockBurst */
-/*****************************************************************************/
-#define NRF_ESB_HIGH_IRQ_PRIORITY 0 ///< Interrupt priority the ESB timer and the radio
-#define NRF_ESB_LOW_IRQ_PRIORITY 1 ///< Interrupt priority for ESB callback functions.
-
-#ifndef USE_SD_HW_RESOURCES
-#define NRF_ESB_SWI_IRQn SWI0_IRQn ///< Software interrupt # used for callback functions.
-#define NRF_ESB_SWI_IRQ_HANDLER SWI0_IRQHandler ///< Software interrupt handler used for callback functions.
-
-#define NRF_ESB_TIMER NRF_TIMER2 ///< Timer to be used as flywheel timer.
-#define NRF_ESB_TIMER_PERPOWER_Msk POWER_PERPOWER_TIMER2_Msk ///< PERPOWER mask for the timer.
-#define NRF_ESB_TIMER_IRQn TIMER2_IRQn ///< Interrupt # for the timer.
-#define NRF_ESB_TIMER_IRQ_HANDLER TIMER2_IRQHandler ///< Interrupt handler for the timer.
-
-// In addition, ESB uses the radio peripheral and radio interrupts.
-
-/*
- * PPI configuration
- */
-#define NRF_ESB_PPI_EEP0 (NRF_PPI -> CH0_EEP) ///< ESB PPI event endpoint 0.
-#define NRF_ESB_PPI_TEP0 (NRF_PPI -> CH0_TEP) ///< ESB PPI task endpoint 0.
-#define NRF_ESB_PPI_EEP1 (NRF_PPI -> CH1_EEP) ///< ESB PPI event endpoint 1.
-#define NRF_ESB_PPI_TEP1 (NRF_PPI -> CH1_TEP) ///< ESB PPI task endpoint 1.
-#define NRF_ESB_PPI_EEP2 (NRF_PPI -> CH2_EEP) ///< ESB PPI event endpoint 2.
-#define NRF_ESB_PPI_TEP2 (NRF_PPI -> CH2_TEP) ///< ESB PPI task endpoint 2.
-
-#define NRF_ESB_PPI_CHEN_MSK_0_AND_1 (0x03) ///< Channel enable/disable mask for PPI endpoint 0 and 1.
-#define NRF_ESB_PPI_CHEN_MSK_2 (0x04) ///< Channel enable/disable mask for PPI endpoint 2.
-#else
-#define NRF_ESB_SWI_IRQn SWI1_IRQn ///< Software interrupt # used for callback functions.
-#define NRF_ESB_SWI_IRQ_HANDLER SWI1_IRQHandler ///< Software interrupt handler used for callback functions.
-
-#define NRF_ESB_TIMER NRF_TIMER0 ///< Timer to be used as flywheel timer.
-#define NRF_ESB_TIMER_PERPOWER_Msk POWER_PERPOWER_TIMER0_Msk ///< PERPOWER mask for the timer.
-#define NRF_ESB_TIMER_IRQn TIMER0_IRQn ///< Interrupt # for the timer.
-#define NRF_ESB_TIMER_IRQ_HANDLER TIMER0_IRQHandler ///< Interrupt handler for the timer.
-
-// In addition, ESB uses the radio peripheral and radio interrupts.
-
-/*
- * PPI configuration
- */
-#define NRF_ESB_PPI_EEP0 (NRF_PPI -> CH8_EEP) ///< ESB PPI event endpoint 0.
-#define NRF_ESB_PPI_TEP0 (NRF_PPI -> CH8_TEP) ///< ESB PPI task endpoint 0.
-#define NRF_ESB_PPI_EEP1 (NRF_PPI -> CH9_EEP) ///< ESB PPI event endpoint 1.
-#define NRF_ESB_PPI_TEP1 (NRF_PPI -> CH9_TEP) ///< ESB PPI task endpoint 1.
-#define NRF_ESB_PPI_EEP2 (NRF_PPI -> CH10_EEP) ///< ESB PPI event endpoint 2.
-#define NRF_ESB_PPI_TEP2 (NRF_PPI -> CH10_TEP) ///< ESB PPI task endpoint 2.
-
-#define NRF_ESB_PPI_CHEN_MSK_0_AND_1 (0x300) ///< Channel enable/disable mask for PPI endpoint 0 and 1.
-#define NRF_ESB_PPI_CHEN_MSK_2 (0x400) ///< Channel enable/disable mask for PPI endpoint 2.
-
-#endif
-
-#define NRF_ESB_CONST_PIPE_COUNT 8 ///< Number of TX pipes (at least one for each Device-Host pairs).
-#define NRF_ESB_CONST_FIFO_LENGTH 3 ///< Maximum number of packets allowed in a TX or RX FIFO.
-#define NRF_ESB_CONST_MAX_TOTAL_PACKETS 6 ///< Maximum number of packets available for reservation at any one time.
-#define NRF_ESB_CONST_MAX_PAYLOAD_LENGTH 32 ///< Maximum allowed payload length in bytes.
-#define NRF_ESB_CONST_CALLBACK_QUEUE_LENGTH 10 ///< Maximum number of notifications allowed in the callback queue.
-/** @} */
-
-
-/*****************************************************************************/
-/** @name Constant pipe and FIFO configuration */
-/*****************************************************************************/
-#define NRF_ESB_CONST_PIPE_COUNT 8 ///< Number of transmission pipes (at least one for each Device-Host pairs).
-#define NRF_ESB_CONST_QUEUE_LENGTH 3 ///< Maximum number of packets allowed in a TX or RX queue.
-#define NRF_ESB_CONST_MAX_TOTAL_PACKETS 6 ///< Maximum number of packets available for reservation at any one time.
-#define NRF_ESB_CONST_MAX_PAYLOAD_LENGTH 32 ///< Maximum allowed payload length in bytes.
-#define NRF_ESB_CONST_CALLBACK_QUEUE_LENGTH 10 ///< Maximum number of notifications allowed in the callback queue.
-
-/** @} */
-
-/*****************************************************************************/
-/** @name Default parameters */
-/*****************************************************************************/
-
-/*
-Corresponds to Legacy nRFgo SDK ESB addresses:
-Address pipe 0 {0xE7, 0xE7, 0xE7, 0xE7, 0xE7}
-Address pipe 1 {0xC2, 0xC2, 0xC2, 0xC2, 0xC2}
-Address pipe 2 {0xC3, 0xC2, 0xC2, 0xC2, 0xC2}
-Address pipe 3 {0xC4, 0xC2, 0xC2, 0xC2, 0xC2}
-*/
-
-#define NRF_ESB_DEFAULT_BASE_ADDRESS_0 0xE7E7E7E7 ///< Default base address 0.
-#define NRF_ESB_DEFAULT_BASE_ADDRESS_1 0xC2C2C2C2 ///< Default base address 1.
-#define NRF_ESB_DEFAULT_PREFIX_BYTE_0 0xE7 ///< Default prefix address pipe 0.
-#define NRF_ESB_DEFAULT_PREFIX_BYTE_1 0xC2 ///< Default prefix address pipe 1.
-#define NRF_ESB_DEFAULT_PREFIX_BYTE_2 0xC3 ///< Default prefix address pipe 2.
-#define NRF_ESB_DEFAULT_PREFIX_BYTE_3 0xC4 ///< Default prefix address pipe 3.
-#define NRF_ESB_DEFAULT_PREFIX_BYTE_4 0xC5 ///< Default prefix address pipe 4.
-#define NRF_ESB_DEFAULT_PREFIX_BYTE_5 0xC6 ///< Default prefix address pipe 5.
-#define NRF_ESB_DEFAULT_PREFIX_BYTE_6 0xC7 ///< Default prefix address pipe 6.
-#define NRF_ESB_DEFAULT_PREFIX_BYTE_7 0xC8 ///< Default prefix address pipe 7.
-#define NRF_ESB_DEFAULT_BASE_ADDRESS_LENGTH NRF_ESB_BASE_ADDRESS_LENGTH_4B ///< Default on-air base address length.
-#define NRF_ESB_DEFAULT_CRC_LENGTH NRF_ESB_CRC_LENGTH_1_BYTE ///< Default CRC length.
-#define NRF_ESB_DEFAULT_ENABLED_PRX_PIPES 0xFF ///< Default enabled RX pipes.
-#define NRF_ESB_DEFAULT_MAX_NUMBER_OF_RETRANSMITS 15 ///< Default number of retransmits.
-#define NRF_ESB_DEFAULT_OUTPUT_POWER NRF_ESB_OUTPUT_POWER_0_DBM ///< Default TX output power.
-#define NRF_ESB_DEFAULT_DATARATE NRF_ESB_DATARATE_2_MBPS ///< Default datarate.
-#define NRF_ESB_DEFAULT_RETRANSMIT_DELAY 600 ///< Default retransmit delay.
-#define NRF_ESB_DEFAULT_CHANNEL (10)
-#define NRF_ESB_DEFAULT_XOSC_CTL NRF_ESB_XOSC_CTL_AUTO ///< Default setting for controlling the XOSC
-
-/** @} */
-
-/** @} */
-
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/ext_sensors/adns2080.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,281 +0,0 @@
- /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef ADNS2080_H
-#define ADNS2080_H
-
-/*lint ++flb "Enter library region" */
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/** @file
-* @brief ADNS2080 mouse sensor driver
-*
-* @defgroup nrf_drivers_adns2080 ADNS2080 driver
-* @{
-* @ingroup nrf_drivers
-* @brief ADNS2080 mouse sensor driver.
-*/
-
-/**
- * Describes return values for @ref adns2080_init.
- */
-typedef enum
-{
- ADNS2080_OK, /*!< Operation was succesful */
- ADNS2080_SERIAL_COMM_FAILURE, /*!< Serial communication failed */
- ADNS2080_CHIP_NOT_DETECTED, /*!< Product/Revision ID was not what was expected */
- ADNS2080_INVALID_PARAMETER /*!< Given parameters were not valid */
-} adns2080_status_t;
-
-/**
- * ADNS2080 motion output pin polarity values.
- */
-typedef enum
-{
- ADNS2080_MOTION_OUTPUT_POLARITY_LOW = 0, /*!< Motion output polarity active low */
- ADNS2080_MOTION_OUTPUT_POLARITY_HIGH = 1 /*!< Motion output polarity active high */
-} motion_output_polarity_t;
-
-/**
- * Motion output pin configuration.
- */
-typedef enum
-{
- ADNS2080_MOTION_OUTPUT_SENSITIVITY_LEVEL = 0, /*!< Motion output pin will be driven low/high (depending on the polarity setting) as long as there is motion data in DELTA registers */
- ADNS2080_MOTION_OUTPUT_SENSITIVITY_EDGE = 1 /*!< Motion output pin will be driven low/high (depending on the polarity setting) for 380 ns when motion is detected during rest modes */
-} motion_output_sensitivity_t;
-
-/**
- * Mouse sensor resolution values.
- */
-typedef enum
-{
- ADNS2080_RESOLUTION_250DPI = 1, /*!< 250 dpi resolution */
- ADNS2080_RESOLUTION_500DPI = 2, /*!< 500 dpi resolution */
- ADNS2080_RESOLUTION_1000DPI = 0, /*!< 1000 dpi resolution */
- ADNS2080_RESOLUTION_1250DPI = 3, /*!< 1250 dpi resolution */
- ADNS2080_RESOLUTION_1500DPI = 4, /*!< 1500 dpi resolution */
- ADNS2080_RESOLUTION_1750DPI = 5, /*!< 1750 dpi resolution */
- ADNS2080_RESOLUTION_2000DPI = 6 /*!< 2000 dpi resolution */
-} adns2080_resolution_t;
-
-/**
- * Mouse sensor forced mode options.
- */
-typedef enum
-{
- ADNS2080_MODE_NORMAL = 0, /*!< Normal operation mode */
- ADNS2080_MODE_REST1 = 1, /*!< Rest1 operation mode */
- ADNS2080_MODE_REST2 = 2, /*!< Rest2 operation mode */
- ADNS2080_MODE_REST3 = 3, /*!< Rest3 operation mode */
- ADNS2080_MODE_RUN1 = 4, /*!< Run1 operation mode */
- ADNS2080_MODE_RUN2 = 5, /*!< Run2 operation mode */
- ADNS2080_MODE_IDLE = 6 /*!< Idle operation mode */
-} adns2080_mode_t;
-
-/**
- * Mouse sensor motion reporting bits.
- */
-typedef enum
-{
- ADNS2080_MOTION_BITS_8 = 0, /*!< Motion reporting uses 8 bits */
- ADNS2080_MOTION_BITS_12 = 1 /*!< Motion reporting uses 12 bits */
-} adns2080_motion_bits_t;
-
-/**
- * @brief Function for initializing the mouse sensor chip.
- *
- * Valid mouse sensor information will be available 50 milliseconds after this
- * function finishes.
- *
- * @return
- * @retval ADNS2080_OK Mouse sensor was initialized succesfully.
- * @retval ADNS2080_SERIAL_COMM_FAILURE Serial communications failure.
- * @retval ADNS2080_CHIP_NOT_DETECTED Could not find revision 0 ADNS2080 chip.
- */
-adns2080_status_t adns2080_init(void);
-
-/**
- * @brief Function for resetting the mouse sensor chip.
- *
- * Valid mouse sensor information will be available 50 milliseconds after this
- * function finishes.
- * All register settings will be lost and need to be reloaded.
- *
- */
-void adns2080_reset(void);
-
-/**
- * @brief Function for reading mouse sensor product ID.
- *
- * Chip is expected to be initialized before calling this function.
- * Returned product ID should always be 0x2A.
- *
- * @return Product ID.
- */
-uint8_t adns2080_product_id_read(void);
-
-/**
- * @brief Function for reading mouse sensor revision ID.
- *
- * Chip is expected to be initialized before calling this function.
- *
- * @return Product ID.
- */
-uint8_t adns2080_revision_id_read(void); // also note there is "not rev id" register
-
-/**
- * @brief Function for powering down the mouse sensor.
- *
- * Chip is expected to be initialized before calling this function.
- * Serial port should not be accessed during the power down. To exit the power
- * down mode, @ref adns2080_wakeup must be called.
- *
- */
-void adns2080_powerdown(void);
-
-/**
- * @brief Function for waking up the mouse sensor.
- *
- * After wakeup, all mouse sensor settings must be reloaded. Valid mouse sensor
- * information will be available 55 milliseconds after this function finishes.
- */
-void adns2080_wakeup(void);
-
-/**
- * @brief Function for configuring the MOTION interrupt output pin.
- *
- * When motion is detected by the mouse sensor, the chip has a MOTION pin
- * indicating there is motion data in DELTA_X and DELTA_Y registers. This
- * function configures the polarity and sensitivity of that pin.
- *
- * Chip is expected to be initialized before calling this function.
- *
- * @param polarity MOTION output pin is either active LOW (default) or active HIGH
- * @param sensitivity Level or Edge (default) sensitive
- * @return
- * @retval ADNS2080_OK Operation succeeded.
- * @retval ADNS2080_INVALID_PARAMETER One of the parameters was not within valid range.
- */
-adns2080_status_t adns2080_motion_interrupt_set(motion_output_polarity_t polarity, motion_output_sensitivity_t sensitivity);
-
-/**
- * @brief Function for setting mouse sensor resolution.
- *
- * Chip is expected to be initialized before calling this function.
- *
- * @param resolution Desired resolution.
- * @return
- * @retval ADNS2080_OK Operation succeeded.
- * @retval ADNS2080_INVALID_PARAMETER One of the parameters was not within valid range.
- */
-adns2080_status_t adns2080_resolution_set(adns2080_resolution_t resolution);
-
-/**
- * @brief Function for setting number of bits used for mouse sensor motion reporting.
- *
- * Chip is expected to be initialized before calling this function.
- *
- * @param motion_bits Desired number of bits.
- * @return
- * @retval ADNS2080_OK Operation succeeded.
- * @retval ADNS2080_INVALID_PARAMETER One of the parameters was not within valid range.
- */
-adns2080_status_t adns2080_motion_bits_set(adns2080_motion_bits_t motion_bits);
-
-/**
- * @brief Function for reading number of bits used for mouse sensor motion reporting.
- *
- * Chip is expected to be initialized before calling this function.
- *
- * @return motion_bits Number of bits.
- */
-adns2080_motion_bits_t adns2080_motion_bits_read(void);
-
-/**
- * @brief Function for reading X- and Y-axis movement (in counts) since last report.
- *
- * Absolute value is determined by resolution.
- * Chip is expected to be initialized before calling this function.
- *
- * @param p_delta_x Location to store X-axis movement
- * @param p_delta_y Location to store Y-axis movement
- */
-void adns2080_movement_read(int16_t *p_delta_x, int16_t *p_delta_y);
-
-/**
- * @brief Function for checking if motion has been detected since last call.
- *
- * Chip is expected to be initialized before calling this function.
- *
- * @return
- * @retval true, if movement has been detected
- * @retval false, if no movement has been detected
- */
-bool adns2080_is_motion_detected(void);
-
-/**
- * @brief Function for setting mouse sensor Rest1, Rest2 and Rest3 mode motion detection time period.
- *
- * Allowed range for the periods is 0x01 to 0xFD.
- * Resulting period is derived from the following equation :
- * Period = (Rest period + 1) * 10 milliseconds
- * Chip is expected to be initialized before calling this function.
- *
- * @param rest1_period Rest1 period
- * @param rest2_period Rest2 period
- * @param rest3_period Rest3 period
- */
-void adns2080_rest_periods_set(uint8_t rest1_period, uint8_t rest2_period, uint8_t rest3_period);
-
-/**
- * @brief Function for setting mouse sensor mode downshift time periods.
- *
- * Allowed range for run_to_rest1_mode_time period is 0x00 to 0xFF.
- * Allowed range for rest1_to_rest2_mode_time period is 0x01 to 0xFF.
- * Allowed range for rest2_to_rest3_mode_time period is 0x01 to 0xFF.
- *
- * Chip is expected to be initialized before calling this function.
- *
- * @param run_to_rest1_mode_time Run mode to Rest1 mode downshift time period (Time = run_to_rest1_mode_time * 8 * 4)
- * @param rest1_to_rest2_mode_time Rest1 mode to Rest2 mode downshift time period (Time = rest1_to_rest2_mode_time * rest1_period * 16)
- * @param rest2_to_rest3_mode_time Rest2 mode to Rest3 mode downshift time period (Time = rest2_to_rest3_mode_time * rest2_period * 128)
- */
-void adns2080_downshift_times_set(uint8_t run_to_rest1_mode_time, uint8_t rest1_to_rest2_mode_time, uint8_t rest2_to_rest3_mode_time);
-
-/**
- * @brief Function for forcing mouse sensor to a certain operating mode.
- *
- * Chip is expected to be initialized before calling this function.
- * Normal operation will not continue until this function is called with ADNS2080_MODE_NORMAL parameter.
- *
- * @param mode Mode to force the sensor to.
- */
-void adns2080_force_mode_set(adns2080_mode_t mode);
-
-/**
- * @brief Function for reading the current forced operating mode.
- *
- * Chip is expected to be initialized before calling this function.
- *
- * @return Mode the sensor is forced to.
- */
-adns2080_mode_t adns2080_force_mode_read(void);
-
-/**
- *@}
- **/
-
-/*lint --flb "Leave library region" */
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/ext_sensors/cherry8x16.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,83 +0,0 @@
- /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef CHERRY8x16_H
-#define CHERRY8x16_H
-
-/*lint ++flb "Enter library region" */
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/** @file
-* @brief Cherry 8x16 keyboard matrix driver
-*
-*
-* @defgroup nrf_drivers_cherry8x16 Cherry 8x16 keyboard matrix driver
-* @{
-* @ingroup nrf_drivers
-* @brief Cherry 8x16 keyboard matrix driver.
-*/
-
-#define CHERRY8x16_MAX_NUM_OF_PRESSED_KEYS 6 //!< Maximum number of pressed keys kept in buffers
-#define CHERRY8x16_DEFAULT_KEY_LOOKUP_MATRIX (const uint8_t*)0 //!< If passed to @ref cherry8x16_init, default lookup matrix will be used
-
-#define KEY_PACKET_MODIFIER_KEY_INDEX (0) //!< Index in the key packet where modifier keys such as ALT and Control are stored
-#define KEY_PACKET_RESERVED_INDEX (1) //!< Index in the key packet where OEMs can store information
-#define KEY_PACKET_KEY_INDEX (2) //!< Start index in the key packet where pressed keys are stored
-#define KEY_PACKET_MAX_KEYS (6) //!< Maximum number of keys that can be stored into the key packet
-#define KEY_PACKET_SIZE (KEY_PACKET_KEY_INDEX+KEY_PACKET_MAX_KEYS) //!< Total size of the key packet in bytes
-#define KEY_PACKET_NO_KEY (0) //!< Value to be stored to key index to indicate no key is pressed
-
-
-/**
- * Describes return values for:
- * @ref cherry8x16_init
- */
-typedef enum
-{
- CHERRY8x16_OK, /*!< Operation was succesful. */
- CHERRY8x16_NOT_DETECTED, /*!< Product/Revision ID was not what was expected */
- CHERRY8x16_INVALID_PARAMETER /*!< Given parameters were not valid */
-} cherry8x16_status_t;
-
-/**
- * @brief Function for initializing the driver.
- *
- * @note Before calling this function, setup row_port as IO inputs with pulldowns enabled and column_port as IO outputs.
- *
- * @param row_port Pointer to GPIO port address that is used as key matrix row input.
- * @param column_port Pointer to GPIO port address that is used as key matrix column output.
- * @param key_lookup_matrix If NULL, use a default key lookup matrix. Otherwise pointer to a 128 (8x16) element array containing HID keycodes.
- * @return
- * @retval CHERRY8X16_OK Peripheral was initialized succesfully.
- * @retval CHERRY8X16_NOT_DETECTED Could not detect the peripheral.
- */
-cherry8x16_status_t cherry8x16_init(const uint8_t volatile * row_port, uint16_t * column_port, const uint8_t * key_lookup_matrix);
-
-/**
- * @brief Function for creating a new key packet if new data is available and key ghosting is not detected.
- *
- * @param p_key_packet Array that will hold the created key packet. Previously created packet will be discarded.
- * @param p_key_packet_size Key packet size in bytes.
- * @return
- * @retval true If new packet was created.
- * @retval false If packet was not created.
- */
-bool cherry8x16_new_packet(const uint8_t ** p_key_packet, uint8_t *p_key_packet_size);
-
-/**
- *@}
- **/
-
-/*lint --flb "Leave library region" */
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/ext_sensors/ds1624.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
- /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef DS1624_H
-#define DS1624_H
-
-/*lint ++flb "Enter library region" */
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/** @file
-* @brief DS1624 digital temperature sensor driver.
-*
-*
-* @defgroup nrf_drivers_ds1624 DS1624 digital temperature sensor driver
-* @{
-* @ingroup nrf_drivers
-* @brief DS1624 digital temperature sensor driver.
-*/
-
-/**
- * @brief Function for initializing DS1624 temperature sensor to 1-shot mode.
- *
- * @note Before calling this function, you must initialize twi_master first.
- *
- * @param device_address Bits [2:0] for the device address. All other bits must be zero.
- * @return
- * @retval true If communication succeeded with the device.
- * @retval false If communication failed with the device.
- */
-bool ds1624_init(uint8_t device_address);
-
-/**
- * @brief Function for reading temperature from the sensor.
- *
- * @param temperature_in_celcius Memory location to store temperature in full celcius degrees.
- * @param temperature_fraction Memory location to store temperature's fraction part in 0.03125 celcius degree increments.
- * @return
- * @retval true Temperature was successfully read
- * @retval false Temperature reading failed or conversion was not yet complete
- */
-bool ds1624_temp_read(int8_t *temperature_in_celcius, int8_t *temperature_fraction);
-
-/**
- * @brief Function for starting temperature conversion. Valid data will be available 400-1000 milliseconds after exiting this function.
- *
- * @return
- * @retval true Temperature conversion started.
- * @retval false Temperature converion failed to start.
-*/
-bool ds1624_start_temp_conversion(void);
-
-/**
- * @brief Function for checking if temperature conversion is done.
- *
- * @return
- * @retval true Temperature conversion done.
- * @retval false Temperature converion still in progress.
-*/
-bool ds1624_is_temp_conversion_done(void);
-
-/**
- *@}
- **/
-
-/*lint --flb "Leave library region" */
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/ext_sensors/mpu6050.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,74 +0,0 @@
-/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef MPU6050_H
-#define MPU6050_H
-
-/*lint ++flb "Enter library region" */
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/** @file
-* @brief MPU6050 gyro/accelerometer driver.
-*
-*
-* @defgroup nrf_drivers_mpu6050 MPU6050 gyro/accelerometer driver
-* @{
-* @ingroup nrf_drivers
-* @brief MPU6050 gyro/accelerometer driver.
-*/
-
-/**
- * @brief Function for initializing MPU6050 and verifies it's on the bus.
- *
- * @param device_address Device TWI address in bits [6:0].
- * @return
- * @retval true MPU6050 found on the bus and ready for operation.
- * @retval false MPU6050 not found on the bus or communication failure.
- */
-bool mpu6050_init(uint8_t device_address);
-
-/**
- @brief Function for writing a MPU6050 register contents over TWI.
- @param[in] register_address Register address to start writing to
- @param[in] value Value to write to register
- @retval true Register write succeeded
- @retval false Register write failed
-*/
-bool mpu6050_register_write(uint8_t register_address, const uint8_t value);
-
-/**
- @brief Function for reading MPU6050 register contents over TWI.
- Reads one or more consecutive registers.
- @param[in] register_address Register address to start reading from
- @param[in] number_of_bytes Number of bytes to read
- @param[out] destination Pointer to a data buffer where read data will be stored
- @retval true Register read succeeded
- @retval false Register read failed
-*/
-bool mpu6050_register_read(uint8_t register_address, uint8_t *destination, uint8_t number_of_bytes);
-
-/**
- @brief Function for reading and verifying MPU6050 product ID.
- @retval true Product ID is what was expected
- @retval false Product ID was not what was expected
-*/
-bool mpu6050_verify_product_id(void);
-
-/**
- *@}
- **/
-
-/*lint --flb "Leave library region" */
-
-#endif /* MPU6050_H */
--- a/hw/nRF51822n/nordic/nrf-sdk/ext_sensors/nRF6350.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,118 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef NRF6350_H_ -#define NRF6350_H_ - -#include <stdbool.h> -#include <stdint.h> - -#define LCD_LLEN 16 //!< LCD Line length - -#define JS_BUTTON_NONE 0x00 //!< Joystick not touched -#define JS_BUTTON_LEFT 0x01 //!< joystick pulled left -#define JS_BUTTON_PUSH 0x02 //!< joystick pushed -#define JS_BUTTON_DOWN 0x04 //!< joystick pulled down -#define JS_BUTTON_UP 0x08 //!< joystick pulled up -#define JS_BUTTON_RIGHT 0x10 //!< joystick pulled right -#define LCD_UPPER_LINE 0x00 //!< LCD upper line -#define LCD_LOWER_LINE 0x40 //!< LCD lower line -#define LCD_CONTRAST_LOW 0x00 //!< LCD Low contrast -#define LCD_CONTRAST_MEDIUM 0x02 //!< LCD Medium contrast -#define LCD_CONTRAST_HIGH 0x08 //!< LCD High contrast - - -/** - * @brief Function for initializing the LCD display prior to writing. - * @return - * @retval true Operation succeeded - * @retval false Operation failed - */ -bool nrf6350_lcd_init(void); - -/** - * @brief Function for writing a text string on the LCD-display. - * - * @param p_text A pointer to the text string to be written - * @param size Size of the text string to be written - * @param line The line the text should be written to - * @param pos The start position of the text on the line - * @return - * @retval true Write succeeded - * @retval false Write failed - */ -bool nrf6350_lcd_write_string(const char *p_text, uint8_t size, uint8_t line, uint8_t pos); - -/** - * @brief Function for clearing the contents of the LCD-display. - * - * @return - * @retval true Operation succeeded - * @retval false Operation failed - */ -bool nrf6350_lcd_clear(void); - -/** - * @brief Function for adjusting the contrast of the LCD-display, select between - * LCD_CONTRAST_LOW, LCD_CONTRAST_MEDIUM and LCD_CONTRAST_HIGH. - * - * @param contrast The desired contrast of the lcd display - * @return - * @retval true Operation succeeded - * @retval false Operation failed - */ -bool nrf6350_lcd_set_contrast(uint8_t contrast); - -/** - * @brief Function for turning ON the LCD-display. - * - * @return - * @retval true Operation succeeded - * @retval false Operation failed - */ -bool nrf6350_lcd_on(void); - -/** - * @brief Function for turning OFF the LCD-display. - * - * @return - * @retval true Operation succeeded - * @retval false Operation failed - */ -bool nrf6350_lcd_off(void); - -/** - * @brief Function for getting the position of the joystick. - * - * @param val pointer to a 2 byte array where the X,Y position is stored - * @return - * @retval true Operation succeeded - * @retval false Operation failed - */ -bool nrf6350_js_get_value(int8_t *val); - -/** - * @brief Function for getting the status of the joystick. - * - * @param js_state pointer to a uint8_t that receives the status of the joystick - * @return - * @retval true Operation succeeded - * @retval false Operation failed - */ -bool nrf6350_js_get_status(uint8_t *js_state); - -/** @brief Function for transferring data over TWI bus. Used the first time you want to communicate nRF6350 to bypass a fail. - */ -bool nrf6350_lcd_wake_up(void); - -#endif // NRF6350_H_ -/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/ext_sensors/sdio.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,69 +0,0 @@
- /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef SDIO_H
-#define SDIO_H
-
-/*lint ++flb "Enter library region" */
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/** @file
-* @brief 2-wire serial interface driver (compatible with ADNS2080 mouse sensor driver)
-*
-*
-* @defgroup nrf_drivers_sdio SDIO driver
-* @{
-* @ingroup nrf_drivers
-* @brief 2-wire serial interface driver.
-*/
-
-/**
- * @brief Function for initializing 2-wire serial interface and trying to handle stuck slaves.
- *
- */
-void sdio_init(void);
-
-/**
- * @brief Function for reading a byte over 2-wire serial interface.
- *
- * Developer needs to implement this function in a way that suits the hardware.
- * @param address Register address to read from
- * @return Byte read
- */
-uint8_t sdio_read_byte(uint8_t address);
-
-/**
- * @brief Function for reading several bytes over 2-wire serial interface using burst mode.
- *
- * Developer needs to implement this function in a way that suits the hardware.
- * @param target_buffer Buffer location to store read bytes to
- * @param target_buffer_size Bytes allocated for target_buffer
- */
-void sdio_read_burst(uint8_t *target_buffer, uint8_t target_buffer_size);
-
-/**
- * @brief Function for writing a byte over 2-wire serial interface.
- *
- * Developer needs to implement this function in a way that suits the hardware.
- * @param address Register address to write to
- * @param data_byte Data byte to write
- */
-void sdio_write_byte(uint8_t address, uint8_t data_byte);
-
-/**
- *@}
- **/
-
-/*lint --flb "Leave library region" */
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/ext_sensors/synaptics_touchpad.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef SYNAPTICS_TOUCHPAD_H
-#define SYNAPTICS_TOUCHPAD_H
-
-/*lint ++flb "Enter library region" */
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/** @file
-* @brief Synaptics Touchpad driver.
-*
-*
-* @defgroup nrf_drivers_synaptics_touchpad Synaptics Touchpad driver.
-* @{
-* @ingroup nrf_drivers
-* @brief Synaptics Touchpad driver.
-*/
-
-/**
- Touchpad register addresses.
-*/
-#define TOUCHPAD_INT_STATUS 0x14 //!< Interrupt status register
-#define TOUCHPAD_BUTTON_STATUS 0x41 //!< Button status register
-#define TOUCHPAD_FINGER0_REL 0x30 //!< First register in finger delta block
-#define TOUCHPAD_GESTURE_FLAGS 0x3A //!< Gesture flags 0
-#define TOUCHPAD_SCROLL 0x3F //!< Scroll zone X / horizontal multifinger scroll
-#define TOUCHPAD_CONTROL 0x42 //!< Device control register
-#define TOUCHPAD_COMMAND 0x8F //!< Device command register
-
-#define TOUCHPAD_RESET 0x54 //!< Address of reset
-#define TOUCHPAD_PAGESELECT 0xFF //!< Address of page select (can be found in every page at the same address)
-#define TOUCHPAD_PRODUCT_ID 0xA2 //!< Address of product ID string
-
-/**
- Operational states
-*/
-typedef enum
-{
- SleepmodeNormal = 0x00, //!< Normal operation
- SleepmodeSensorSleep = 0x01 //!< Low power operation
-} TouchpadSleepMode_t;
-
-/**
- @brief Function for Touchpad initialization.
- @param device_address TWI address of the device in bits [6:0]
- @retval true Touchpad was successfully identified and initialized
- @retval false Unexpected product ID or communication failure
-*/
-bool touchpad_init(uint8_t device_address);
-
-/**
- @brief Function for attempting to soft-reset the device.
- @retval true Reset succeeded
- @retval false Reset failed
-*/
-bool touchpad_reset(void);
-
-/**
- @brief Function for reading the interrupt status register of the device. This clears all interrupts.
- @param interrupt_status Address to store interrupt status to.
- @retval true Register contents read successfully to interrupt_status
- @retval false Reading failed
-*/
-bool touchpad_interrupt_status_read(uint8_t *interrupt_status);
-
-/**
- @brief Function for sleep mode configuration.
- @note In low power mode the touchpad do not generate interrupts from touch sensing.
- @param[in] mode Operational mode
- @retval true Sleep mode set successfully
- @retval false Sleep mode setting failed
-*/
-bool touchpad_set_sleep_mode(TouchpadSleepMode_t mode);
-
-/**
- @brief Function for reading a touchpad register contents over TWI.
- @param[in] register_address Register address
- @param[out] value Pointer to a data buffer where read data will be stored
- @retval true Register read succeeded
- @retval false Register read failed
-*/
-bool touchpad_read_register(uint8_t register_address, uint8_t *value);
-
-/**
- @brief Function for writing a touchpad register contents over TWI.
- @param[in] register_address Register address
- @param[in] value Value to write to register
- @retval true Register write succeeded
- @retval false Register write failed
-*/
-bool touchpad_write_register(uint8_t register_address, uint8_t value);
-
-/**
- @brief Function for writing touchpad register contents over TWI.
- Writes one or more consecutive registers.
- @param[out] product_id Pointer to a address to store product ID. Memory must be allocated for product_id_bytes number of bytes.
- @param[in] product_id_bytes Number of bytes to read
- @retval true Product ID read succeeded
- @retval false Product ID read failed
-*/
-bool touchpad_product_id_read(uint8_t *product_id, uint8_t product_id_bytes);
-
-/**
- @brief Function for reading and verifying touchpad's product ID.
- @retval true Product ID is what was expected
- @retval false Product ID was not what was expected
-*/
-bool touchpad_product_id_verify(void);
-
-/**
- *@}
- **/
-
-/*lint --flb "Leave library region" */
-
-#endif /* __TOUCHPAD_H__ */
--- a/hw/nRF51822n/nordic/nrf-sdk/gcc/core_cm0.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,682 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
- @{
- */
-
-/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0_REV
- #define __CM0_REV 0x0000
- #warning "__CM0_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
- are only accessible over DAP and not via processor. Therefore
- they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/** \brief Function for enabling External Interrupt.
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Function for disabling External Interrupt.
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Function for getting Pending Interrupt.
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief Function for setting Pending Interrupt.
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Function for clearing Pending Interrupt.
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Function for setting Interrupt Priority.
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief Function for getting Interrupt Priority.
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Function for System Reset.
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief Function for system Tick Configuration.
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/gcc/core_cmFunc.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,636 +0,0 @@
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/** \brief Function for getting Control Register.
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/** \brief Function for setting Control Register.
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Function for getting IPSR Register.
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/** \brief Function for getting APSR Register.
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Function for getting xPSR Register.
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/** \brief Function for getting Process Stack Pointer.
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/** \brief Function for setting Process Stack Pointer.
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Function for getting Main Stack Pointer.
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/** \brief Function for setting Main Stack Pointer.
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Function for getting Priority Mask.
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/** \brief Function for setting Priority Mask.
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Function for enabling FIQ.
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Function for disabling FIQ.
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Function for getting Base Priority.
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/** \brief Function for setting Base Priority.
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Function for getting Fault Mask.
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/** \brief Function for setting Fault Mask.
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Function for getting FPSCR.
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Function for setting FPSCR.
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Function for enabling IRQ Interrupts.
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief Function for disabling IRQ Interrupts.
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief Function for getting Control Register.
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for setting Control Register.
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief Function for getting IPSR Register.
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for getting APSR Register.
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for getting xPSR Register.
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for getting Process Stack Pointer.
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for setting Process Stack Pointer.
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief Function for getting Main Stack Pointer.
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for setting Main Stack Pointer.
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief Function for getting Priority Mask.
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for setting Priority Mask.
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Function for enabling FIQ.
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief Function for disabling FIQ.
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief Function for getting Base Priority.
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for setting Base Priority.
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Function for getting Fault Mask.
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Function for setting Fault Mask.
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Function for getting FPSCR.
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Function for setting FPSCR.
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */
--- a/hw/nRF51822n/nordic/nrf-sdk/gcc/core_cmInstr.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,688 +0,0 @@
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V3.20
- * @date 05. March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() __isb(0xF)
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __dsb(0xF)
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __dmb(0xF)
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Function for reversing byte order (16 bit).
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-/** \brief Function for reversing byte order in signed short value.
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __RBIT __rbit
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX __clrex
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief Function for No Operation.
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/** \brief Function for Wait For Interrupt.
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/** \brief Function for Wait For Event.
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/** \brief Function for Send Event.
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/** \brief Function for Instruction Synchronization Barrier.
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb");
-}
-
-
-/** \brief Function for Data Synchronization Barrier.
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb");
-}
-
-
-/** \brief Function for Data Memory Barrier.
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb");
-}
-
-
-/** \brief Function for reversing byte order (32 bit).
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Function for reversing byte order (16 bit).
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief Function for reversing byte order in signed short value.
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- uint32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Function for rotating Right in unsigned value (32 bit).
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief Function for Breakpoint.
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Function for reversing bit order of value.
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Function for the LDR Exclusive (8 bit).
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return(result);
-}
-
-
-/** \brief Function for the LDR Exclusive (16 bit).
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return(result);
-}
-
-
-/** \brief Function for the LDR Exclusive (32 bit).
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief Function for the STR Exclusive (8 bit).
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Function for the STR Exclusive (16 bit).
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Function for the STR Exclusive (32 bit).
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Function for removing the exclusive lock.
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Function for counting leading zeros.
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
--- a/hw/nRF51822n/nordic/nrf-sdk/gzll/nrf_gzll.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,883 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- * $LastChangedRevision: 29442 $
- */
-
-
-/**
- * @file
- * @brief Gazell Link Layer API.
- */
-
-#ifndef NRF_GZLL_H__
-#define NRF_GZLL_H__
-
-#include "stdbool.h"
-#include "nrf.h"
-#include "nrf_gzll_constants.h"
-
-
-/**
-* @defgroup gzll_02_api Application Programming Interface (API)
-* @{
-* @ingroup modules_01_gzll
-* @brief Gazell Link Layer Application Programming Interface (API).
-*/
-
-
-/**
- * @enum nrf_gzll_mode_t
- * @brief Enumerator used for selecting Gazell mode.
- */
-typedef enum
-{
- NRF_GZLL_MODE_DEVICE, ///< Device mode
- NRF_GZLL_MODE_HOST, ///< Host mode
-} nrf_gzll_mode_t;
-
-
-/**
- * @enum nrf_gzll_device_channel_selection_policy_t
- * @brief Enumerator used for selecting Gazell Device channel
- * selection policy.
- */
-typedef enum
-{
- NRF_GZLL_DEVICE_CHANNEL_SELECTION_POLICY_USE_SUCCESSFUL, ///< Start on previous successful channel
- NRF_GZLL_DEVICE_CHANNEL_SELECTION_POLICY_USE_CURRENT, ///< Start on channel currently monitored by Host
-} nrf_gzll_device_channel_selection_policy_t;
-
-
-/**
- * @enum nrf_gzll_tx_power_t
- * @brief Enumerator used for selecting the transmit (TX) power.
- */
-typedef enum
-{
- NRF_GZLL_TX_POWER_4_DBM, ///< 4 dBm transmit power.
- NRF_GZLL_TX_POWER_0_DBM, ///< 0 dBm transmit power.
- NRF_GZLL_TX_POWER_N4_DBM, ///< -4 dBm transmit power.
- NRF_GZLL_TX_POWER_N8_DBM, ///< -8 dBm transmit power.
- NRF_GZLL_TX_POWER_N12_DBM, ///< -12 dBm transmit power.
- NRF_GZLL_TX_POWER_N16_DBM, ///< -16 dBm transmit power.
- NRF_GZLL_TX_POWER_N20_DBM ///< -20 dBm transmit power.
-} nrf_gzll_tx_power_t;
-
-
-/**
- * @enum nrf_gzll_datarate_t
- * @brief Enumerator used for selecting the radio datarate.
- */
-typedef enum
-{
- NRF_GZLL_DATARATE_250KBIT, ///< 250 Kbps datarate.
- NRF_GZLL_DATARATE_1MBIT, ///< 1 Mbps datarate.
- NRF_GZLL_DATARATE_2MBIT ///< 2 Mbps datarate.
-} nrf_gzll_datarate_t;
-
-
-/**
- * @enum nrf_gzll_xosc_ctl_t
- * @brief Enumerator used for specifying whether switching the
- * external 16 MHz oscillator on/off shall be handled automatically
- * inside Gazell or manually by the application.
- */
-typedef enum
-{
- NRF_GZLL_XOSC_CTL_AUTO, ///< Switch XOSC on/off automatically
- NRF_GZLL_XOSC_CTL_MANUAL ///< Switch XOSC on/off manually
-} nrf_gzll_xosc_ctl_t;
-
-/**
- * @enum nrf_gzll_error_code_t
- * @brief Enumerator used for error codes for Gazell API functions
- */
-typedef enum
-{
- NRF_GZLL_ERROR_CODE_NO_ERROR = 0,
- ///< No error has been detected.
- NRF_GZLL_ERROR_CODE_FAILED_TO_INITIALIZE = 1,
- ///< The function NRF_GZLL_init failed.
- NRF_GZLL_ERROR_CODE_ATTEMPTED_TO_CONFIGURE_WHEN_ENABLED = 2,
- ///< A call to a configuration 'set' function was made while Gazell was
- ///< enabled.
- NRF_GZLL_ERROR_CODE_POINTER_IS_NULL = 3,
- ///< A null pointer was given as an input to a function.
- NRF_GZLL_ERROR_CODE_INVALID_PIPE = 4,
- ///< An invalid pipe number was given as an input to a function.
- NRF_GZLL_ERROR_CODE_INVALID_MODE = 5,
- ///< An invalid value for the nrf_gzll_mode_t enumerator was given as input
- ///< to a function.
- NRF_GZLL_ERROR_CODE_INVALID_PAYLOAD_LENGTH = 6,
- ///< An invalid payload length was given as an input to a function.
- NRF_GZLL_ERROR_CODE_INVALID_CHANNEL_TABLE_SIZE = 7,
- ///< An invalid channel table size was given as an input to a function.
- NRF_GZLL_ERROR_CODE_INSUFFICIENT_PACKETS_AVAILABLE = 8,
- ///< There are insufficient packets in the Gazell memory pool to
- ///< successfully execute the operation.
- NRF_GZLL_ERROR_CODE_ATTEMPTED_TO_ADD_TO_FULL_FIFO = 9,
- ///< There is insufficient space in the TX FIFO for the data packet.
- NRF_GZLL_ERROR_CODE_NO_SPACE_IN_RX_FIFO_FOR_ACK = 10,
- ///< There is insufficient space in the RX FIFO for the ACK.
- NRF_GZLL_ERROR_CODE_ATTEMPTED_TO_FETCH_FROM_EMPTY_FIFO = 11,
- ///< Attempted to fetch a packet from an empty FIFO. Use the functions nrf_gzll_get_tx_fifo_packet_count() or nrf_gzll_get_rx_fifo_packet_count()
- NRF_GZLL_ERROR_CODE_ATTEMPTED_TO_FLUSH_WHEN_ENABLED = 12,
- ///< Attempted to fetch a packet from an empty FIFO. Use the functions nrf_gzll_get_tx_fifo_packet_count() or nrf_gzll_get_rx_fifo_packet_count()
- NRF_GZLL_ERROR_CODE_INVALID_PARAMETER = 14,
- ///< Attempted to set a variable which was not valid.
- NRF_GZLL_ERROR_CODE_INTERNAL_ASSERT_OCCURRED = 15,
- ///< An internal assert occurred.
- NRF_GZLL_ERROR_CODE_CALLBACK_NOT_IMPLEMENTED = 16,
- ///< A callback was called but not implemented by the application.
- NRF_GZLL_ERROR_CODE_NUMBER_OF_ERROR_CODES = 17,
- ///< Number of possible error codes.
-} nrf_gzll_error_code_t;
-
-
-/**
- * @struct nrf_gzll_device_tx_info_t;
- * @brief Data structure containing information about the last packet
- * transmission.
- */
-typedef struct
-{
- bool payload_received_in_ack;
- ///< A payload was received in the ACK.
- uint16_t num_tx_attempts;
- ///< Number of attempts used on previous Device packet transmission.
- uint16_t num_channel_switches;
- ///< Number of channel switches needed during previous packet transmission.
- int16_t rssi;
- ///< Received signal strength indicator in dBm. @sa nrf_gzll_enable_rssi().
-} nrf_gzll_device_tx_info_t;
-
-/**
- * @struct nrf_gzll_host_rx_info_t;
- * @brief Data structure containing information about the last packet
- * received.
- */
-typedef struct
-{
- bool packet_removed_from_tx_fifo;
- ///< A payload was received in the ACK.
- int16_t rssi;
- ///< Received signal strength indicator in dBm. @sa nrf_gzll_enable_rssi().
-} nrf_gzll_host_rx_info_t;
-
-
-
-
-/******************************************************************************/
-/** @name General API functions
- * @{ */
-/******************************************************************************/
-
-
-/**
- * @brief Initialize Gazell.
- *
- * @param mode The mode to initialize Gazell in.
- *
- * @retval true if Gazell initialized.
- * @retval false if Gazell failed to initialize.
- */
-bool nrf_gzll_init(nrf_gzll_mode_t mode);
-
-
-/**
- * @brief Enable Gazell.
- *
- * When enabled the behaviour described for the current Gazell Link Layer mode
- * will apply.
- *
- * @retval false if nrf_gzll_init has not previously been called.
- */
-bool nrf_gzll_enable(void);
-
-
-/**
- * @brief Disable Gazell.
- *
- * When calling this function the Gazell Link Layer will begin disabling,
- * and will be fully disabled when Gazell calls nrf_gzll_disabled().
- * If there are any pending notifications, or if any new notifications are
- * being added to the internal notification queue while Gazell is disabling,
- * these will be sent to the application before Gazell is fully disabled.
- *
- * After Gazell has been fully disabled, no more notifications will be sent to
- * the application.
- */
-void nrf_gzll_disable(void);
-
-
-/** Check whether Gazell is enabled or disabled.
- *
- * @retval true If Gazell is enabled.
- * @retval false If Gazell is disabled.
- */
-bool nrf_gzll_is_enabled(void);
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Device mode callback functions
- * @{ */
-/******************************************************************************/
-
-
-/**
- * @brief ACK received callback (Device mode only).
- *
- * This callback is made when the Device receives an ACK (acknowledgement)
- * packet.
- * @sa nrf_gzll_ack_payload_received.
- *
- * @param pipe is the pipe on which an ACK packet was received.
- * @param tx_info struct used to indicate whether a payload was received in the
- * ack, as well as the number of TX attempts and channel switches required.
- */
-void nrf_gzll_device_tx_success(uint32_t pipe, nrf_gzll_device_tx_info_t tx_info);
-
-
-/**
- * @brief Transmission failed callback (Device mode only).
- *
- * This callback is made when a packet does not receive an ACK after
- * nrf_gzll_max_retries is reached. The packet is deleted by Gazell.
- *
- * @param pipe is the pipe on which the transmission failed.
- * @param tx_info struct used to indicate whether a payload was received
- * in the ack, as well as RSSI and the number of TX attempts and
- * channel switches required.
- */
-void nrf_gzll_device_tx_failed(uint32_t pipe, nrf_gzll_device_tx_info_t tx_info);
-
-
-/** @} */
-
-
-
-/******************************************************************************/
-/** @name Host mode callback functions
- * @{ */
-/******************************************************************************/
-
-/**
- * @brief Data packet received callback (Host mode only).
- *
- * This callback is made when a Host receives a data packet from a Device.
- *
- * @param pipe is the pipe on which the data packet was received.
- * @param rx_info struct used to indicate whether a payload was removed from the
- * pipe's TX FIFO, as well as RSSI.
- */
-void nrf_gzll_host_rx_data_ready(uint32_t pipe, nrf_gzll_host_rx_info_t rx_info);
-
-
-/** @} */
-
-/******************************************************************************/
-/** @name Callback functions for both Device and Host mode
- * @{ */
-/******************************************************************************/
-
-
-/**
- * @brief Disabled callback.
- *
- * This is called after Gazell enters the disabled state.
- * There is no further CPU use by Gazell, the radio is disabled and the timer is
- * powered down.
- */
-void nrf_gzll_disabled(void);
-
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Packet transmission and receiving functions
- * @{ */
-/******************************************************************************/
-
-/**
- * @brief Add a packet to the tail of the TX FIFO.
- *
- * In Device mode, the packet will be added.
- * In Host mode, the payload will be piggybacked onto an ACK.
- *
- * @param pipe Pipe to which to add the payload. This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- * @param payload Pointer to the payload.
- * @param length Number of bytes of the payload to transmit
- * (0 to NRF_GZLL_CONST_MAX_PAYLOAD_LENGTH).
- *
- * @retval true if the packet was successfully added to the TX FIFO.
- * @retval false if unsuccessful, check nrf_gzll_error_code_t for more information.
- */
-bool nrf_gzll_add_packet_to_tx_fifo(uint32_t pipe, uint8_t * payload, uint32_t length);
-
-
-/**
- * @brief Fetch a packet from the head of the RX FIFO.
- *
- * @param pipe Pipe from which to fetch the payload. This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- * @param payload Pointer to copy the payload to.
- * @param length Length must be at least as large as the the number of bytes
- * in the received payload length.
- *
- * @retval true If the fetch was successful.
- * @retval false If unsuccessful, check nrf_gzll_error_code_t for more information.
- */
-bool nrf_gzll_fetch_packet_from_rx_fifo(uint32_t pipe, uint8_t * payload, uint32_t* length);
-
-
-/**
- * @brief Get the number of packets in the TX FIFO on a specific pipe.
- *
- * @param pipe The pipe for which to check. This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- *
- * @retval >=0 The number of packets in the TX FIFO for the pipe.
- * @retval -1 If the pipe number is invalid.
- */
-int32_t nrf_gzll_get_tx_fifo_packet_count(uint32_t pipe);
-
-
-/**
- * @brief Get the number of packets in the RX FIFO on a specific pipe.
- *
- * @param pipe The pipe for which to check. This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- * @retval >=0 The number of packets in the RX FIFO for the pipe.
- * @retval -1 If the pipe number is invalid.
- */
-int32_t nrf_gzll_get_rx_fifo_packet_count(uint32_t pipe);
-
-
-/**
- * @brief Get the total number of packets residing in all TX and RX FIFOs.
- *
- * Can be used to check against NRF_GZLL_CONST_MAX_TOTAL_PACKETS to
- * determine if there is free space in the memory pool for more packets.
- *
- * @return The number of packets residing in all TX and RX FIFOs.
- */
-uint32_t nrf_gzll_get_total_allocated_packet_count(void);
-
-
-/**
- * @brief Check if adding a packet to a pipe's TX FIFO should be successful.
- *
- * Checks if there is another space in the pipe's TX and RX FIFOs
- * as well as enough overall space in the packet pool.
- *
- * @param pipe The pip for which to check. This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- *
- * @retval true If there is another space.
- * @retval false If there is not enough space, or the pipe is invalid.
- */
-bool nrf_gzll_ok_to_add_packet_to_tx_fifo(uint32_t pipe);
-
-/**
- * @brief Flush the RX FIFO for a specific pipe.
- *
- * Delete all the packets and free the memory of the TX FIFO for a
- * specific pipe.
- *
- * Note that it is not allowed to flush a TX FIFO when
- * Gazell is enabled.
- *
- * @param pipe is the pipe for which to flush. This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- * @retval true if the pipe was flushed.
- * @retval false if the pipe was not flushed.
- */
-bool nrf_gzll_flush_tx_fifo(uint32_t pipe);
-
-
-/**
- * @brief Flush the RX FIFO for a specific pipe.
- *
- * Delete all the packets and free the memory of the RX FIFO for a
- * specific pipe.
- *
- * @param pipe is the pipe for which to flush. This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- * @retval true if the pipe was flushed.
- * @retval false if the pipe was not flushed.
- */
-bool nrf_gzll_flush_rx_fifo(uint32_t pipe);
-
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Configuration functions
- *
- * Configuration 'set' functions may only be called while Gazell is disabled. The
- * new parameter comes into effect when Gazell is enabled again.
- *
- * Configuration 'get' functions may be called at any time.
- *
- * @{ */
-/******************************************************************************/
-
-
-/**
- * @brief Set the mode.
- *
- * @param mode The mode to be used.
- * See nrf_gzll_mode_t for a list of valid modes.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled or the mode was invalid.
- */
-bool nrf_gzll_set_mode(nrf_gzll_mode_t mode);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_mode().
- *
- * @return The current mode.
- */
-nrf_gzll_mode_t nrf_gzll_get_mode(void);
-
-
-/**
- * @brief Set the base address for pipe 0.
- *
- * The full on-air address for each pipe is composed of a multi-byte base address
- * prepended to a prefix byte.
- *
- * For packets to be received correctly, the most significant byte of
- * the base address should not be an alternating sequence of 0s and 1s i.e.
- * it should not be 0x55 or 0xAA.
- *
- * @param base_address The 4 byte base address. All bytes are used.
- *
- * @retval true If the parameter was set.
- * @return false If Gazell was enabled.
- */
-bool nrf_gzll_set_base_address_0(uint32_t base_address);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_base_address_0().
- *
- * @return Base address 0.
- */
-uint32_t nrf_gzll_get_base_address_0(void);
-
-
-/**
- * @brief Set the base address for pipes 1-7.
- *
- * Pipes 1 through 7 share base_address_1. @sa nrf_gzll_set_base_address_0.
- *
- * @param base_address The 4 byte base address.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled.
- */
-bool nrf_gzll_set_base_address_1(uint32_t base_address);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_base_address_1().
- *
- * @return Base address 1.
- */
-uint32_t nrf_gzll_get_base_address_1(void);
-
-
-/**
- * @brief Set the address prefix byte for a specific pipe.
- *
- * Each pipe should have its own unique prefix byte.
- *
- * @param pipe The pipe that the address should apply to.
- * This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- * @param address_prefix_byte The address prefix byte.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled, or if the pipe was invalid.
- */
-bool nrf_gzll_set_address_prefix_byte(uint32_t pipe, uint8_t address_prefix_byte);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_address_prefix_byte().
- *
- * @param pipe The pipe for which to get the address.
- * This value must be < NRF_GZLL_CONST_PIPE_COUNT.
- * @param out_address_prefix_byte The pointer in which to return the
- * address prefix byte.
- *
- * @retval true If the parameter was returned.
- * @retval false If Gazell was enabled, the pipe was invalid or
- * out_address was a NULL pointer.
- */
-bool nrf_gzll_get_address_prefix_byte(uint32_t pipe, uint8_t* out_address_prefix_byte);
-
-
-/**
- * @brief Set which pipes shall listen for packets in Host mode.
- *
- * This value is a bitmap, and each bit corresponds to a given pipe number.
- * Bit 0 set to "1" enables pipes 0, bit 1 set to "1" enables pipe 1
- * and so forth.
- * The maximum number of pipes is defined by NRF_GZLL_CONST_PIPE_COUNT.
- *
- * @param pipes A bitmap specifying which pipes to monitor.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled.
- */
-bool nrf_gzll_set_rx_pipes_enabled(uint32_t pipes);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_rx_pipes_enabled().
- *
- * @return Bitmap holding the current enabled pipes.
- */
-uint32_t nrf_gzll_get_rx_pipes_enabled(void);
-
-
-/**
- * @brief Set the timeslot period.
- *
- * The length in microseconds of a Gazell link layer timeslot.
- *
- * The minimum value of the timeslot period is dependent of the
- * radio data rate (@sa nrf_gzll_set_datarate()).
- *
- * - For NRF_GZLL_DATARATE_2MBIT the timeslot period must be >= 600 us.
- * - For NRF_GZLL_DATARATE_1MBIT the timeslot period must be >= 900 us.
- * - For NRF_GZLL_DATARATE_250KBIT the timeslot period must be >= 2700 us.
- *
- * @param period_us The timeslot period in microseconds.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled.
- */
-bool nrf_gzll_set_timeslot_period(uint32_t period_us);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_get_timeslot_period().
- *
- * @return The current timeslot period.
- */
-uint32_t nrf_gzll_get_timeslot_period(void);
-
-
-/**
- * @brief Set the Device channel selection policy
- *
- * The policy determines the initial channel when starting a new packet.
- * transmission.
- *
- * @param policy The channel selection policy.
- *
- * @arg NRF_GZLL_DEVICE_CHANNEL_SELECTION_POLICY_USE_SUCCESSFUL specifies
- * that a new packet transmission always shall use the previous
- * successful channel from the channel table. If Gazell is "in sync", Gazell
- * will wait until this channel is being monitored by the Host before starting
- * the transmission.
- *
- * @arg NRF_GZLL_DEVICE_CHANNEL_SELECTION_POLICY_USE_CURRENT specifies that
- * Gazell shall transmit on the channel that is currently being monitored by the
- * Host. This parameter is only used when Gazell is "in sync". When "out of" sync,
- * Gazell will always start using the "previous successful" channel.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled or the policy was invalid.
- */
-bool nrf_gzll_set_device_channel_selection_policy(nrf_gzll_device_channel_selection_policy_t policy);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_device_channel_selection_policy().
- *
- * @return the Device channel selection policy.
- */
-nrf_gzll_device_channel_selection_policy_t nrf_gzll_get_device_channel_selection_policy(void);
-
-
-/**
- * @brief Set the number of timeslots that Gazell shall
- * reside on a single channel before switching to another channel.
- *
- * This parameter applies in Host mode and for a Device that is
- * in the "in sync" state.
- *
- * Since the Device and Host can not be in perfect synchronization, a
- * transmission should overlap to adjacent timeslots on the Host.
- * Therefore this value should be at least 2.
- *
- * @sa nrf_gzll_set_timeslots_per_channel_when_device_out_of_sync
- *
- * @param timeslots The number of timeslots to reside on
- * each channel before channel switch.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled.
- */
-bool nrf_gzll_set_timeslots_per_channel(uint32_t timeslots);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_timeslots_per_channel().
- *
- * @return The current number of timeslots.
- */
-uint32_t nrf_gzll_get_timeslots_per_channel(void);
-
-
-/**
- * @brief Set the number of timeslots that a Gazell shall
- * reside on a single channel before switching to another channel when
- * in the "out of sync" state.
- *
- * This value should be set so that the Device transmits on one channel
- * while the Host goes through a full channel rotation, i.e.,
- * channel_table_size*timeslots_per_channel.
- * This ensures that the channels on the Device and Host will coincide
- * at some point.
- * Further increasing the value has been observed to provide better performance
- * in the presence of interferers.
- *
- * @param timeslots The number of timeslots to reside on
- * each channel before channel switch.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled.
- */
-bool nrf_gzll_set_timeslots_per_channel_when_device_out_of_sync(uint32_t timeslots);
-
-
-/**
- * @brief Get function counterpart to
- * nrf_gzll_set_timeslots_per_channel_when_device_out_of_sync().
- *
- * @return The current number of timeslots.
- */
-uint32_t nrf_gzll_get_timeslots_per_channel_when_device_out_of_sync(void);
-
-
-/**
- * @brief Set the number of timeslots after a successful
- * reception of a Device or Host packet that the Gazell Link Layer shall assume
- * that the link is synchronized. A value of 0 implies that the
- * link is always out of sync.
- *
- * @param lifetime The sync lifetime in number of timeslots.
- *
- * @retval true If the sync lifetime was set.
- * @retval false If Gazell was enabled.
- */
-bool nrf_gzll_set_sync_lifetime(uint32_t lifetime);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_sync_lifetime().
- *
- * @return The sync lifetime measured in number of timeslots.
- */
-uint32_t nrf_gzll_get_sync_lifetime(void);
-
-
-/**
- * @brief Set the maximum number of TX attempts
- * that can be used for a single packet.
- *
- * After the maximum number of attempts have been spent without
- * receiving any ACK from the Host, the transmission will be terminated
- * and the nrf_gzll_device_tx_failed() callback will be called.
- *
- * @param max_tx_attempts The maximum number of TX attempts.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled.
- */
-bool nrf_gzll_set_max_tx_attempts(uint16_t max_tx_attempts);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_max_tx_attempts().
- *
- * @return The current max Device TX attempts.
- */
-uint16_t nrf_gzll_get_max_tx_attempts(void);
-
-
-/**
- * @brief Set the table of Radio Frequency (RF) channels.
- *
- * The valid channels are in the range 0 <= channel <= 125, where the
- * actual centre frequency is (2400 + channel) MHz.
- * The maximum channel table size is defined by
- * NRF_GZLL_CONST_MAX_CHANNEL_TABLE_SIZE.
- *
- * @param channel_table Pointer to the channel table.
- * @param size The size of the channel table.
- *
- * @retval true If the channel table was set.
- * @retval false If Gazell was enabled, or the channel_table pointer was NULL,
- * or the size was invalid.
- */
-bool nrf_gzll_set_channel_table(uint8_t* channel_table, uint32_t size);
-
-
-/**
- * @brief Get the table of Radio Frequency (RF) channels.
- *
- * @param channel_table Pointer to copy the channel table to.
- * @param size Pointer to copy the size of the channel table to.
- * The value already at size must be at least the size
- * of the channel table.
- *
- * @retval true If the channel table was copied to channel_table.
- * @retval false If the channel_table pointer was NULL,
- * or the size was not large enough.
- */
-bool nrf_gzll_get_channel_table(uint8_t* channel_table, uint32_t* size);
-
-
-/**
- * @brief Get the current channel table size.
- *
- * @return The current channel table size.
- */
-uint32_t nrf_gzll_get_channel_table_size(void);
-
-
-/**
- * @brief Set the radio TX power.
- *
- * @param tx_power TX power.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled or the TX power was invalid.
-*/
-bool nrf_gzll_set_tx_power(nrf_gzll_tx_power_t tx_power);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_tx_power().
- *
- * @return The current TX power.
- */
-nrf_gzll_tx_power_t nrf_gzll_get_tx_power(void);
-
-
-/**
- * @brief Set the radio datarate.
- *
- * @param data_rate Datarate.
- *
- * @retval true If the parameter was set.
- * @retval false If Gazell was enabled or the datarate was invalid.
- */
-bool nrf_gzll_set_datarate(nrf_gzll_datarate_t data_rate);
-
-
-/**
- * @brief Get function counterpart to nrf_gzll_set_datarate().
- *
- * @return The current datarate.
- */
-nrf_gzll_datarate_t nrf_gzll_get_datarate(void);
-
-
-/**
- * @brief Set whether start/stop of external oscillator (XOSC) shall be handled
- * automatically inside Gazell or manually by the application.
- *
- * When controlling the XOSC manually from the application it is
- * required that the XOSC is started before Gazell is enabled.
- *
- * When start/stop of the XOSC is handled automatically by Gazell,
- * the XOSC will only be running when needed, that is when the radio
- * is being used or when Gazell needs to maintain synchronization.
- *
- * It is required that the XOSC is started in order for the radio to be
- * able to send or receive any packets.
- *
- * @param xosc_ctl setting for XOSC control.
- *
- * @retval true if the parameter was set.
- * @retval false if Gazell was enabled or the xosc_ctl value was invalid.
- */
-bool nrf_gzll_set_xosc_ctl(nrf_gzll_xosc_ctl_t xosc_ctl);
-
-
-/**
- * Get function counterpart for nrf_gzll_set_xosc_ctl();
- *
- * @return The XOSC control setting.
- */
-nrf_gzll_xosc_ctl_t nrf_gzll_get_xosc_ctl(void);
-
-
-/**
- * @brief Set Gazell to disable automatically after a certain number of timeslot ticks.
- *
- * @param num_ticks Number of timeslot ticks.
- *
- */
-void nrf_gzll_set_auto_disable(uint32_t num_ticks);
-
-
-/**
- * @brief Get the number of timeslot ticks that have occurred since
- * nrf_gzll_init() was called.
- *
- * @return Number of timeslot ticks.
- *
- */
-uint32_t nrf_gzll_get_tick_count(void);
-
-
-/**
- * @brief Clear the internal timeslot tick count variable that is read
- * by nrf_gzll_get_tick_count().
- *
- */
-void nrf_gzll_clear_tick_count(void);
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Error handling functions
- * @{ */
-/******************************************************************************/
-
-
-/**
- * @brief Gets the Gazell error code.
- *
- * @return The current error code.
- */
-nrf_gzll_error_code_t nrf_gzll_get_error_code(void);
-
-
-/**
- * @brief Reset the Gazell error code.
- *
- * The error code is reset to NRF_GZLL_ERROR_CODE_NO_ERRROR.
- */
-void nrf_gzll_reset_error_code(void);
-
-/** @} */
-
-/** @} */
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/gzll/nrf_gzll_constants.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,165 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- * $LastChangedRevision: 32956 $
- */
-
-
-/**
- * @file
- * @brief Gazell Link Layer constants and default values.
- *
- * NOTE! Changing values here has no effect. They are only provided as a reference.
- */
-
-#ifndef NRF_GZLL_CONSTANTS_H__
-#define NRF_GZLL_CONSTANTS_H__
-
-
-/**
- * @addtogroup gzll_02_api
- * @{
- */
-
-
-/*****************************************************************************/
-/** @name Hardware resources used by Gazell */
-/*****************************************************************************/
-#define NRF_GZLL_HIGH_IRQ_PRIORITY 0 ///< Interrupt priority the Gazell timer and the radio
-#define NRF_GZLL_LOW_IRQ_PRIORITY 1 ///< Interrupt priority for Gazell callback functions.
-
-#ifndef USE_SD_HW_RESOURCES
-#define NRF_GZLL_SWI_IRQn SWI0_IRQn ///< Software interrupt # used for callback functions.
-#define NRF_GZLL_SWI_IRQ_HANDLER SWI0_IRQHandler ///< Software interrupt handler used for callback functions.
-
-#define NRF_GZLL_TIMER NRF_TIMER2 ///< Timer to be used as flywheel timer.
-#define NRF_GZLL_TIMER_PERPOWER_Msk POWER_PERPOWER_TIMER2_Msk ///< PERPOWER mask for the timer.
-#define NRF_GZLL_TIMER_IRQn TIMER2_IRQn ///< Interrupt # for the timer.
-#define NRF_GZLL_TIMER_IRQ_HANDLER TIMER2_IRQHandler ///< Interrupt handler for the timer.
-
-// In addition, Gazell uses the radio peripheral and radio interrupts.
-
-/*
- * PPI configuration
- */
-#define NRF_GZLL_PPI_EEP0 (NRF_PPI -> CH0_EEP) ///< Gazell PPI event endpoint 0
-#define NRF_GZLL_PPI_TEP0 (NRF_PPI -> CH0_TEP) ///< Gazell PPI task endpoint 0
-#define NRF_GZLL_PPI_EEP1 (NRF_PPI -> CH1_EEP) ///< Gazell PPI event endpoint 1
-#define NRF_GZLL_PPI_TEP1 (NRF_PPI -> CH1_TEP) ///< Gazell PPI task endpoint 1
-#define NRF_GZLL_PPI_EEP2 (NRF_PPI -> CH2_EEP) ///< Gazell PPI event endpoint 2
-#define NRF_GZLL_PPI_TEP2 (NRF_PPI -> CH2_TEP) ///< Gazell PPI task endpoint 2
-
-#define NRF_GZLL_PPI_CHEN_MSK_0_AND_1 (0x03) ///< Channel enable/disable mask for PPI endpoint 0 and 1.
-#define NRF_GZLL_PPI_CHEN_MSK_2 (0x04) ///< Channel enable/disable mask for PPI endpoint 2.
-
-#else
-
-#define NRF_GZLL_SWI_IRQn SWI1_IRQn ///< Software interrupt # used for callback functions.
-#define NRF_GZLL_SWI_IRQ_HANDLER SWI1_IRQHandler ///< Software interrupt handler used for callback functions.
-
-#define NRF_GZLL_TIMER NRF_TIMER0 ///< Timer to be used as flywheel timer.
-#define NRF_GZLL_TIMER_PERPOWER_Msk POWER_PERPOWER_TIMER0_Msk ///< PERPOWER mask for the timer.
-#define NRF_GZLL_TIMER_IRQn TIMER0_IRQn ///< Interrupt # for the timer.
-#define NRF_GZLL_TIMER_IRQ_HANDLER TIMER0_IRQHandler ///< Interrupt handler for the timer.
-
-// In addition, Gazell uses the radio peripheral and radio interrupts.
-
-/*
- * PPI configuration
- */
-#define NRF_GZLL_PPI_EEP0 (NRF_PPI -> CH8_EEP) ///< Gazell PPI event endpoint 0
-#define NRF_GZLL_PPI_TEP0 (NRF_PPI -> CH8_TEP) ///< Gazell PPI task endpoint 0
-#define NRF_GZLL_PPI_EEP1 (NRF_PPI -> CH9_EEP) ///< Gazell PPI event endpoint 1
-#define NRF_GZLL_PPI_TEP1 (NRF_PPI -> CH9_TEP) ///< Gazell PPI task endpoint 1
-#define NRF_GZLL_PPI_EEP2 (NRF_PPI -> CH10_EEP) ///< Gazell PPI event endpoint 2
-#define NRF_GZLL_PPI_TEP2 (NRF_PPI -> CH10_TEP) ///< Gazell PPI task endpoint 2
-
-#define NRF_GZLL_PPI_CHEN_MSK_0_AND_1 (0x300) ///< Channel enable/disable mask for PPI endpoint 0 and 1.
-#define NRF_GZLL_PPI_CHEN_MSK_2 (0x400) ///< Channel enable/disable mask for PPI endpoint 2.
-
-#endif
-
-#define NRF_GZLL_CONST_PIPE_COUNT 8 ///< Number of TX pipes (at least one for each Device-Host pairs).
-#define NRF_GZLL_CONST_FIFO_LENGTH 3 ///< Maximum number of packets allowed in a TX or RX FIFO.
-#define NRF_GZLL_CONST_MAX_TOTAL_PACKETS 6 ///< Maximum number of packets available for reservation at any one time.
-#define NRF_GZLL_CONST_MAX_PAYLOAD_LENGTH 32 ///< Maximum allowed payload length in bytes.
-#define NRF_GZLL_CONST_CALLBACK_QUEUE_LENGTH 10 ///< Maximum number of notifications allowed in the callback queue.
-/** @} */
-
-
-
-/*****************************************************************************/
-/** @name Constant pipe and FIFO configuration */
-/*****************************************************************************/
-#define NRF_GZLL_CONST_PIPE_COUNT 8 ///< Number of TX pipes (at least one for each Device-Host pairs).
-#define NRF_GZLL_CONST_FIFO_LENGTH 3 ///< Maximum number of packets allowed in a TX or RX FIFO.
-#define NRF_GZLL_CONST_MAX_TOTAL_PACKETS 6 ///< Maximum number of packets available for reservation at any one time.
-#define NRF_GZLL_CONST_MAX_PAYLOAD_LENGTH 32 ///< Maximum allowed payload length in bytes.
-#define NRF_GZLL_CONST_CALLBACK_QUEUE_LENGTH 10 ///< Maximum number of notifications allowed in the callback queue.
-/** @} */
-
-
-
-/*****************************************************************************/
-/** @name Default radio configuration */
-/*****************************************************************************/
-#define NRF_GZLL_DEFAULT_TX_POWER NRF_GZLL_TX_POWER_0_DBM ///< Default TX power.
-#define NRF_GZLL_DEFAULT_DATARATE NRF_GZLL_DATARATE_2MBIT ///< Default data rate.
-#define NRF_GZLL_DEFAULT_CHANNEL_TABLE {4, 25, 42, 63, 77} ///< Default channel table.
-#define NRF_GZLL_DEFAULT_CHANNEL_TABLE_SIZE 5 ///< Default channel table size.
-#define NRF_GZLL_CONST_MAX_CHANNEL_TABLE_SIZE 16 ///< Maximum channel table size allowed by Gazell.
-/** @} */
-
-
-/*****************************************************************************/
-/** @name Default Address configuration */
-/*****************************************************************************/
-/*
-Corresponds to Legacy nRFgo SDK Gazell config:
-#define GZLL_DEFAULT_ADDRESS_PIPE0 {0x01, 0x04, 0x07, 0x0A, 0x0D} // {1, 4, 7, 10, 13}
-#define GZLL_DEFAULT_ADDRESS_PIPE1 {0x02, 0x05, 0x08, 0x0B, 0x0E} // {2, 5, 8, 11, 14}
-#define GZLL_DEFAULT_ADDRESS_PIPE2 3
-#define GZLL_DEFAULT_ADDRESS_PIPE3 4
-#define GZLL_DEFAULT_ADDRESS_PIPE4 5
-#define GZLL_DEFAULT_ADDRESS_PIPE5 6
-*/
-#define NRF_GZLL_DEFAULT_FULL_ADDRESS_PIPE0 {0x01, 0x04, 0x07, 0x0A, 0x0D} ///< Corresponding legacy Gazell pipe 0 address.
-#define NRF_GZLL_DEFAULT_BASE_ADDRESS_0 0x0D0A0704 ///< Default base address 0.
-#define NRF_GZLL_DEFAULT_BASE_ADDRESS_1 0x0E0B0805 ///< Default base address 1.
-#define NRF_GZLL_DEFAULT_PREFIX_BYTE_0 1 ///< Default prefix address pipe 0.
-#define NRF_GZLL_DEFAULT_PREFIX_BYTE_1 2 ///< Default prefix address pipe 1.
-#define NRF_GZLL_DEFAULT_PREFIX_BYTE_2 3 ///< Default prefix address pipe 2.
-#define NRF_GZLL_DEFAULT_PREFIX_BYTE_3 4 ///< Default prefix address pipe 3.
-#define NRF_GZLL_DEFAULT_PREFIX_BYTE_4 5 ///< Default prefix address pipe 4.
-#define NRF_GZLL_DEFAULT_PREFIX_BYTE_5 6 ///< Default prefix address pipe 5.
-#define NRF_GZLL_DEFAULT_PREFIX_BYTE_6 7 ///< Default prefix address pipe 6.
-#define NRF_GZLL_DEFAULT_PREFIX_BYTE_7 8 ///< Default prefix address pipe 7.
-#define NRF_GZLL_DEFAULT_BASE_ADDRESS_LENGTH NRF_GZLL_BASE_ADDRESS_LENGTH_4B ///< Default on-air base address length.
-
-#define NRF_GZLL_DEFAULT_RX_PIPES_ENABLED 0x000000FF ///< Enabled Rx pipes. See nrf_gzll_set_rx_pipes_enabled().
-
-/** @} */
-
-
-/*****************************************************************************/
-/** @name Default timeslot and synchronization configuration */
-/*****************************************************************************/
-#define NRF_GZLL_DEFAULT_TIMESLOT_PERIOD 600 ///< Default timeslot period.
-#define NRF_GZLL_DEFAULT_TIMESLOTS_PER_CHANNEL 2 ///< Timeslots use by the Host and by the Device when communication is in sync.
-#define NRF_GZLL_DEFAULT_TIMESLOTS_PER_CHANNEL_WHEN_DEVICE_OUT_OF_SYNC 15 ///< Timeslots use by the Device before communication is in sync.
-#define NRF_GZLL_DEFAULT_SYNC_LIFETIME (3*NRF_GZLL_DEFAULT_CHANNEL_TABLE_SIZE*NRF_GZLL_DEFAULT_TIMESLOTS_PER_CHANNEL) ///< Number of timeslots to keep the timer running so that communication remains synchronized.
-#define NRF_GZLL_DEFAULT_DEVICE_CHANNEL_SELECTION_POLICY NRF_GZLL_DEVICE_CHANNEL_SELECTION_POLICY_USE_SUCCESSFUL ///< Default channel Gazell Device channel selection policy
-#define NRF_GZLL_DEFAULT_MAX_TX_ATTEMPTS 0 ///< Default maximum TX attempts for each packet. A value of zero implies maximum
-#define NRF_GZLL_DEFAULT_XOSC_CTL NRF_GZLL_XOSC_CTL_AUTO ///< Deafult setting for controlling the XOSC
-/** @} */
-
-
-/** @} */
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/gzp/nrf_gzp.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,630 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
-*
-* The information contained herein is property of Nordic Semiconductor ASA.
-* Terms and conditions of usage are described in detail in NORDIC
-* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
-*
-* Licensees are granted free, non-transferable use of the information. NO
-* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
-* the file.
-*
-* $LastChangedRevision: 25678 $
-*/
-
-/**
- * @file
- * @brief Gazell Pairing API
- */
-
-#ifndef __GZP_H
-#define __GZP_H
-
-#include "nrf.h"
-#include "nrf_gzp_config.h"
-#include <stdbool.h>
-
-
-/**
-* @defgroup gzp_02_api Application Programming Interface (API)
-* @{
-* @ingroup modules_02_gzp
-* @brief Gazell Pairing API.
-*/
-
-
-/******************************************************************************/
-/** @name Pairing configuration defines
- * @{ */
-/******************************************************************************/
-
-
-#define GZP_PAIRING_PIPE 0 ///< Pipe reserved for initial pairing communication.
-#define GZP_DATA_PIPE 1 ///< Pipe reserved for GZP encrypted data communication (one pipe only).
-#define GZP_TX_RX_TRANS_DELAY 10 ///< Time to wait between request and fetch packets in RX_PERIODS (2 timeslot periods)
-#define GZP_SYSTEM_ADDRESS_WIDTH 4 ///< Must equal Gazell base address length.
-
-
-#define GZP_VALIDATION_ID {0x32, 0x53, 0x66} ///< Validation ID. Required to be shared by Host and Device. Not a secret.
-#define GZP_VALIDATION_ID_LENGTH 3 ///< Validation ID length in bytes.
-#define GZP_HOST_ID_LENGTH 5 ///< Host ID length in bytes.
-#define GZP_SESSION_TOKEN_LENGTH GZP_HOST_ID_LENGTH ///< Session token length in bytes.
-#define GZP_DYN_KEY_LENGTH (16 - GZP_VALIDATION_ID_LENGTH) ///< Dynamic key length in bytes.
-
-#define GZP_HOST_RX_POWER_THRESHOLD -64 ///< RSSI threshold for when signal strength in RX packet power is high enough.
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Device -> Host packet definitions
- * @{ */
-/******************************************************************************/
-
-#define GZP_CMD_HOST_ADDRESS_REQ_PAYLOAD_LENGTH 1 ///< "Host address request" packet, payload length
-
-#define GZP_CMD_HOST_ADDRESS_FETCH_PAYLOAD_LENGTH 1 ///< "Host address fetch" packet, payload length
-
-#define GZP_CMD_HOST_ID_REQ_SESSION_TOKEN 1 ///< "Host ID request" packet, session token position
-#define GZP_CMD_HOST_ID_REQ_PAYLOAD_LENGTH (GZP_CMD_HOST_ID_REQ_SESSION_TOKEN + GZP_SESSION_TOKEN_LENGTH) ///< "Host ID request" payload length
-
-#if (GZP_CMD_HOST_ID_REQ_PAYLOAD_LENGTH > 17)
-#error GZP_SESSION_TOKEN_LENGTH too long.
-#endif
-
-
-#define GZP_CMD_HOST_ID_FETCH_VALIDATION_ID 1 ///< "Host ID fetch" packet
-#define GZP_CMD_HOST_ID_FETCH_PAYLOAD_LENGTH (GZP_CMD_HOST_ID_FETCH_VALIDATION_ID + GZP_VALIDATION_ID_LENGTH) ///< "Host ID fetch" payload length
-
-#if (GZP_CMD_HOST_ID_FETCH_PAYLOAD_LENGTH > 17)
-#error GZP_VALIDATION_ID_LENGTH set too long.
-#endif
-
-#define GZP_CMD_KEY_UPDATE_PREPARE_PAYLOAD_LENGTH 1 ///< "Key update prepare" payload length
-
-#define GZP_CMD_KEY_UPDATE_VALIDATION_ID 1 ///< "Key update" packet, validation ID position
-#define GZP_CMD_KEY_UPDATE_NEW_KEY (GZP_CMD_KEY_UPDATE_VALIDATION_ID + GZP_VALIDATION_ID_LENGTH) ///< "Key update" packet, new key position
-#define GZP_CMD_KEY_UPDATE_PAYLOAD_LENGTH (GZP_CMD_KEY_UPDATE_NEW_KEY + GZP_DYN_KEY_LENGTH) ///< "Key update" packet, payload length
-
-#if (GZP_CMD_KEY_UPDATE_PAYLOAD_LENGTH > 17)
-#error Sum (GZP_VALIDATION_ID_LENGTH + GZP_DYN_KEY_LENGTH) too high.
-#endif
-
-
-#define GZP_CMD_ENCRYPTED_USER_DATA_VALIDATION_ID 1 ///< "Encrypted user data" packet, validation ID position
-#define GZP_CMD_ENCRYPTED_USER_DATA_PAYLOAD ((GZP_CMD_ENCRYPTED_USER_DATA_VALIDATION_ID + GZP_VALIDATION_ID_LENGTH)) ///< "Encrypted user data" packet, user data position
-#define GZP_ENCRYPTED_USER_DATA_PACKET_OVERHEAD ( GZP_CMD_ENCRYPTED_USER_DATA_VALIDATION_ID + GZP_VALIDATION_ID_LENGTH) ///< "Encrypted user data" packet, packet overhead length
-#define GZP_ENCRYPTED_USER_DATA_MAX_LENGTH (17 - GZP_ENCRYPTED_USER_DATA_PACKET_OVERHEAD) ///< "Encrypted user data" packet, max payload length
-
-#if(GZP_MAX_FW_PAYLOAD_LENGTH < 17)
- #error GZP_MAX_FW_PAYLOAD_LENGTH must be greater or equal to 17.
-#endif
-
-#define GZP_CMD_FETCH_RESP_PAYLOAD_LENGTH 1 ///< General "fetch response" packet, payload_length
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Host -> Device packet definitions
- * @{ */
-/******************************************************************************/
-
-
-#define GZP_CMD_HOST_ADDRESS_RESP_ADDRESS 1 ///< "Host address fetch" response packet, address position
-#define GZP_CMD_HOST_ADDRESS_RESP_PAYLOAD_LENGTH (GZP_CMD_HOST_ADDRESS_RESP_ADDRESS + GZP_SYSTEM_ADDRESS_WIDTH) ///< ///< "Host address fetch" response packet, payload length
-
-#if(GZP_MAX_ACK_PAYLOAD_LENGTH < GZP_CMD_HOST_ADDRESS_RESP_PAYLOAD_LENGTH)
- #error GZP_MAX_ACK_PAYLOAD_LENGTH must be greater or equal to GZP_CMD_HOST_ADDRESS_RESP_PAYLOAD_LENGTH.
-#endif
-
-
-#define GZP_CMD_HOST_ID_FETCH_RESP_VALIDATION_ID 1 ///< "Host ID fetch" response packet, validation ID position
-#define GZP_CMD_HOST_ID_FETCH_RESP_STATUS (GZP_CMD_HOST_ID_FETCH_RESP_VALIDATION_ID + GZP_VALIDATION_ID_LENGTH) ///< "Host ID fetch" response packet, status position
-#define GZP_CMD_HOST_ID_FETCH_RESP_HOST_ID (GZP_CMD_HOST_ID_FETCH_RESP_STATUS + 1) ///< "Host ID fetch" response packet, Host ID position
-#define GZP_CMD_HOST_ID_FETCH_RESP_PAYLOAD_LENGTH (GZP_CMD_HOST_ID_FETCH_RESP_HOST_ID + GZP_HOST_ID_LENGTH) ///< "Host ID fetch" response packet, payload length
-
-#if(GZP_MAX_ACK_PAYLOAD_LENGTH < GZP_CMD_HOST_ID_FETCH_RESP_PAYLOAD_LENGTH)
- #error GZP_MAX_ACK_PAYLOAD_LENGTH must be greater or equal to GZP_CMD_HOST_ID_FETCH_RESP_PAYLOAD_LENGTH.
-#endif
-
-
-#define GZP_CMD_KEY_UPDATE_PREPARE_RESP_SESSION_TOKEN 1 ///< "Key update prepare" response packet, session token position
-#define GZP_CMD_KEY_UPDATE_PREPARE_RESP_PAYLOAD_LENGTH (GZP_CMD_KEY_UPDATE_PREPARE_RESP_SESSION_TOKEN + GZP_SESSION_TOKEN_LENGTH) ///< "Key update prepare" response packet, payload length position
-
-#if(GZP_MAX_ACK_PAYLOAD_LENGTH < GZP_CMD_KEY_UPDATE_PREPARE_RESP_PAYLOAD_LENGTH)
- #error GZP_MAX_ACK_PAYLOAD_LENGTH must be greater or equal to GZP_CMD_KEY_UPDATE_PREPARE_RESP_PAYLOAD_LENGTH.
-#endif
-
-
-#define GZP_CMD_ENCRYPTED_USER_DATA_RESP_SESSION_TOKEN 1 ///< "Encrypted user data" response packet, session token position
-#define GZP_CMD_ENCRYPTED_USER_DATA_RESP_VALIDATION_ID (GZP_CMD_ENCRYPTED_USER_DATA_RESP_SESSION_TOKEN + GZP_SESSION_TOKEN_LENGTH) ///< "Encrypted user data" response packet, validation ID position
-#define GZP_CMD_ENCRYPTED_USER_DATA_RESP_PAYLOAD_LENGTH (GZP_CMD_ENCRYPTED_USER_DATA_RESP_VALIDATION_ID + GZP_VALIDATION_ID_LENGTH) ///< "Encrypted user data" response packet, payload length position
-
-#if(GZP_MAX_ACK_PAYLOAD_LENGTH < GZP_CMD_ENCRYPTED_USER_DATA_RESP_PAYLOAD_LENGTH)
- #error GZP_MAX_ACK_PAYLOAD_LENGTH must be greater or equal to GZP_CMD_ENCRYPTED_USER_DATA_RESP_PAYLOAD_LENGTH.
-#endif
-
-#if(GZP_VALIDATION_ID_LENGTH > GZP_HOST_ID_LENGTH)
- #error GZP_HOST_ID_LENGTH should be greater or equal to GZP_VALIDATION_ID_LENGTH.
-#endif
-
-#if(GZP_SESSION_TOKEN_LENGTH != GZP_HOST_ID_LENGTH)
- #error GZP_SESSION_TOKEN_LENGTH must equal GZP_HOST_ID_LENGTH.
-#endif
-
-#ifdef GZLL_CRYPT_ENABLE
- #error Gazell encryption can not be enabled when using the Gazell pairing library. \
- GZLL_CRYPT_ENABLE must be undefined.
-#endif
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Typedefs
- * @{ */
-/******************************************************************************/
-
-
-/**
- * @enum gzp_key_select_t
- * @brief Enumerator used for selecting the key to be used for encryption.
- */
-typedef enum
-{
- GZP_ID_EXCHANGE, ///< "Secret key" only
- GZP_KEY_EXCHANGE, ///< "Secret key" and "Host ID"
- GZP_DATA_EXCHANGE ///< "Dynamic key" and "Host ID"
-} gzp_key_select_t;
-
-
-/**
- * @enum gzp_cmd_t
- * @brief Enumerator used in the first payload byte of each packet to
- * indicate the packet type.
- */
-typedef enum
-{
- GZP_CMD_HOST_ADDRESS_REQ = 0, ///< Host address request
- GZP_CMD_HOST_ADDRESS_FETCH, ///< Host address fetch
- GZP_CMD_HOST_ID_REQ, ///< Host ID request
- GZP_CMD_HOST_ID_FETCH, ///< Host ID fetch request
- GZP_CMD_KEY_UPDATE_PREPARE, ///< Key update prepare
- GZP_CMD_KEY_UPDATE, ///< Key update
- GZP_CMD_ENCRYPTED_USER_DATA, ///< Encrypted user data
- GZP_CMD_FETCH_RESP, ///< Fetch response
- GZP_CMD_HOST_ADDRESS_RESP, ///< Host address response
- GZP_CMD_HOST_ID_FETCH_RESP, ///< Host ID fetch response
- GZP_CMD_KEY_UPDATE_PREPARE_RESP, ///< Key update prepare
- GZP_CMD_ENCRYPTED_USER_DATA_RESP, ///< Encrypted user data response
-} gzp_cmd_t;
-
-
-/**
- * @enum gzp_id_req_res_t
- * @brief Enumerator used to identify the state of the current
- * Host ID request.
- */
-typedef enum
-{
- GZP_ID_RESP_PENDING, ///< ID response pending
- GZP_ID_RESP_GRANTED, ///< ID response granted
- GZP_ID_RESP_REJECTED, ///< ID response rejected
- GZP_ID_RESP_FAILED, ///< ID response failed
- GZP_ID_RESP_NO_REQUEST ///< Default value. No ID request has yet been received.
-} gzp_id_req_res_t;
-
-
-/** @} */
-
-
-/******************************************************************************/
-/** @name Misc. function prototypes
- * @{ */
-/******************************************************************************/
-
-/**
- * Set the session token.
- *
- * @param token Pointer to the session token to set.
- */
-void gzp_crypt_set_session_token(const uint8_t *token);
-
-
-/**
- * Get the session token.
- *
- * @param dst_token Pointer to write the session token.
- */
-void gzp_crypt_get_session_token(uint8_t *dst_token);
-
-
-/**
- * Set the dynamic key.
- *
- * @param dyn_key Pointer to the dynamic key to set.
- */
-void gzp_crypt_set_dyn_key(const uint8_t* dyn_key);
-
-
-/**
- * Get the dynamic key.
- *
- * @param dst_key Pointer to write the dynamic key too.
- */
-void gzp_crypt_get_dyn_key(uint8_t *dst_key);
-
-
-/**
- * Set the Host ID.
- *
- * @param src Pointer to the Host ID to set.
- */
-static void gzp_set_host_id(const uint8_t* src);
-
-
-/**
- * Get the Host ID.
- *
- * @param dst Pointer to write the Host ID to.
- */
-void gzp_get_host_id(uint8_t *dst);
-
-
-/**
- * Selecting what key-set that should be used when encrypting data
- * using gzp_crypt().
- *
- * @param key_select Key-set to use.
- */
-void gzp_crypt_select_key(gzp_key_select_t key_select);
-
-
-/**
- * Encypt / decrypt data.
- *
- * The current "session token" will be used as initialization vector (IV).
- * The AES key to be used is selected by gzp_crypt_select_key().
- * AES is a symmetric encryption scheme, this function can be used
- * to perform both encryption and decryption.
- *
- * @param dst Destination to write encrypted data to. Should be 16 bytes long.
- * @param src Source data to encrypt.
- * @param length Length in bytes of src.
- */
-void gzp_crypt(uint8_t* dst, const uint8_t* src, uint8_t length);
-
-
-/**
- * Compare the *src_id with a pre-defined validation ID.
- *
- * @param src_id Pointer to the source validation ID to compare to.
- *
- * @retval true If *src_id equals the pre-defined ID.
- * @retval false If *src_id does not equal the pre-defined ID.
- */
-bool gzp_validate_id(const uint8_t *src_id);
-
-
-/**
- * Add the pre-defined validation ID to dst_id.
- * GZP_VALIDATION_ID_LENGTH bytes will be added.
- *
- * @param dst_id Pointer to add the GZP validation ID to.
- */
-void gzp_add_validation_id(uint8_t *dst_id);
-
-
-/**
- * Generate random bytes.
- *
- * @param dst Destination to write the random bytes to.
- * @param n Number of bytes to generate.
- */
-void gzp_random_numbers_generate(uint8_t *dst, uint8_t n);
-
-
-/**
- * Update the channel table and the system address.
- *
- * The channel table is updated to pseudo-random set generated using the
- * system address. The channel table still includes GZP_CHANNEL_MAX and
- * GZP_CHANNEL_MIN.
- * The system address is applied to base address 1 and therefore applies
- * to pipes 1-7.
- *
- * @param system_address Pointer to the system_address to set.
- *
- * @retval true If theradio parameters were updated successfully.
- * @retval false If there was an error updated the radio parameters.
- */
-bool gzp_update_radio_params(const uint8_t *system_address);
-
-
-/**
- * Generate a set of channels from a 4 byte address.
- *
- * @param ch_dst Destination to write the channel set to. The channel set
- * includes GZP_CHANNEL_MAX and GZP_CHANNEL_MIN.
- * @param address Four byte address to generate the channel set from.
- * @param channel_set_size Size of the channel set to generate.
- */
-void gzp_generate_channels(uint8_t *ch_dst, const uint8_t * address, uint8_t channel_set_size);
-
-
-/**
- * Perform an XOR on two byte strings.
- *
- * @param dst Destination to write the result to. Should be of size length.
- * @param src
- * @param pad
- * @param length Number of bytes to perform the XOR operation on.
- */
-void gzp_xor_cipher(uint8_t* dst, const uint8_t* src, const uint8_t* pad, uint8_t length);
-
-
-/******************************************************************************/
-/** @name Common Device and Host functions
- * @{ */
-/******************************************************************************/
-
-
-/**
- * Initialization function. This function initializes the Gazell Pairing Library.
-
- * This function must be called before any of the other Gazell Pairing Library functions are
- * used and must be called @b after gzll_init() is called.
- *
- */
-void gzp_init(void);
-
-/**
- * Function for erasing all pairing data.
- */
-void gzp_erase_pairing_data(void);
-
-/**
- * Disable Gazell and sleep while waiting for nrf_gzll_disabled callback.
- */
-void nrf_gzp_disable_gzll(void);
-
-/**
- Function for cancelling an ongoing (pending) "Host ID request".
-
- After calling this function the "Host ID request" status will go to
- "ID request Idle".
-*/
-void gzp_id_req_cancel(void);
-
-/**
- * Flush the GZLL RX FIFO for a specific pipe while GZLL is disabled.
- *
- * @param pipe Pipe.
- */
-void nrf_gzp_flush_rx_fifo(uint32_t pipe);
-
-/**
-@name Device functions
-*/
-
-/**
- * Check whether current GZP packet transaction has completed.
- *
- * @retval true
- * @retval false
- */
-bool nrf_gzp_tx_complete(void);
-
-/**
- * Check whether previous GZP packet transaction was successful.
- *
- * @retval true
- * @retval false
- */
-bool nrf_gzp_tx_success(void);
-
-/**
- * Reset tx_complete status.
- */
-void nrf_gzp_reset_tx_complete(void);
-
-/**
- * Reset tx_success status.
- */
-void nrf_gzp_reset_tx_success(void);
-
-/**
-* Function to check whether a Device has existing pairing data, implying that it is
-* paired to a Host.
-*
-* @retval -2 The pairing database is empty.
-* @retval -1 The device has a system address but no Host ID.
-* @retval >=0 The device has a system address and HostID at this index value in the database.
-*/
-int8_t gzp_get_pairing_status(void);
-
-/**
- Function for sending a "system address" request to a Host.
-
- When calling this function the Device will attempt acquiring the "system address" from
- any Host within close proximity.
-
- If a host is located within close proximity and pairing is enabled in the Host,
- a "system address" will be sent in return to the Device.
-
- The new "system address" will apply immediately in the Device, and the new "system address"
- will be stored in non volatile (NV) memory.
-
- Note. Using OTP devices limits the number of times a new "system address" can
- be stored in NV memory.
-
- @return
-
- @retval true if new "system address" was received from a Host.
- @retval false if no "system address" was received from a Host.
-*/
-bool gzp_address_req_send(void);
-
-/**
- Function for sending a "Host ID request" to a Host.
-
- The "Host ID" is needed to be able to send encrypted data using
- gzp_crypt_data_send().
-
- The request will be sent using the "system address" previously received using
- gzp_address_req_send().
-
- It is not required that the Host is within close proximity in order to acquire the
- "Host ID".
-
- The new "Host ID" will apply immediately for the Device, and the new "Host ID"
- will be stored in non volatile (NV) memory.
-
- Note. Using OTP devices limits the number of times a new "Host ID" can
- be stored in NV memory.
-
- @return
-
- @retval GZP_ID_RESP_PENDING if a "Host ID request" has been sent to the Host, but the Host application has
- not yet decided whether to Grant or Reject the "ID request".
- @retval GZP_ID_RESP_GRANTED if the "Host ID" has been received from the Host. The received "Host ID" will be stored
- in non volatile memory.
- @retval GZP_ID_RESP_REJECTED if the Host application has rejected the "Host ID request".
- @retval GZP_ID_RESP_FAILED if failing to send a request or receive a response from the Host.
-*/
-gzp_id_req_res_t gzp_id_req_send(void);
-
-/**
- Function for sending encrypted user data to the Host.
-
- Before any data can be sent the Device must acquire both the Host's
- "system address" by using gzp_address_req_send() and the "Host ID" by using
- gzp_id_req_send().
-
- @param *src is a pointer to the data packet to be sent.
- @param length is the length of the data packet to be sent.
-
-
- @return
- @retval true if the data was successfully transmitted and decrypted by the Host.
- @retval false if data transmission failed or Host failed to decryption data correctly.
-*/
-bool gzp_crypt_data_send(const uint8_t *src, uint8_t length);
-
-
-/**
-@name Host functions
-*/
-
-/**
- Function for enabling/disabling pairing in a host. When pairing is enabled the host will
- be monitoring for "system address" and "Host ID" requests from Devices.
-
- A "system address request" received from a Device will always be granted.
- When a "host ID request" has been received, the Host application have to grant,
- reject or cancel this by using one of the following functions:
-
- - gzp_id_req_grant()
- - gzp_id_req_reject()
- - gzp_id_req_cancel()
-
- @param enable
- @arg true enables pairing.
- @arg false disables pairing.
-*/
-void gzp_pairing_enable(bool enable);
-
-/**
- * Execute the Gazell Pairing Library Host operation.
- *
- * This function must be called regularly by the Host application.
- */
-void gzp_host_execute(void);
-
-/**
- * Address exchanged check.
- *
- * @retval true If a "system address" was delivered to a requesting Device during the
- * previous call to gzp_host_execute();
- * @retval false Otherwise.
-*/
-bool gzp_address_exchanged(void);
-
-/**
- Function for checking if a "Host ID request" has been received from a Device.
-
- If a request has been received, the Pairing library will enter "ID request pending"
- state.
-
- The application is responsible for responding to this request by calling
- one of the following functions:
-
- - gzp_id_req_grant()
- - gzp_id_req_reject()
- - gzp_id_req_cancel()
-
- @retval true if a "Host ID request" has been received (internal state is "ID request pending")
- @retval false if no "Host ID request" has been received (internal state is "ID request idle")
-*/
-bool gzp_id_req_received(void);
-
-/**
- Function for rejecting the previously received "Host ID request". This function should be called
- only when a "Host ID request" has been received (internal state is "ID request pending").
-
- The internal state of the Pairing library will remain "ID request pending" until the a "reject" message
- has been successfully transmitted to the requesting Device. After this the internal state will
- change to "ID request idle".
-*/
-void gzp_id_req_reject(void);
-
-/**
- * Function for granting the previously received "Host ID request". This function should be called
- only when a "Host ID request" has been received (internal state is "ID request pending").
-
- The internal state of the Pairing library will remain "ID request pending" until the "Host ID" has
- been successfully transmitted to the requesting Device. After this the internal state will
- change to "ID request idle".
-*/
-void gzp_id_req_grant(void);
-
-
-/**
- * Check if user data has been received.
- *
- * @retval true If encrypted user data has been received.
- * @retval false Otherwise.
-*/
-bool gzp_crypt_user_data_received(void);
-
-/**
- Function for reading encrypted user data.
-
- Note that the read user data will be automatically decrypted. Only data
- that was decrypted correctly will be presented.
-
- @param dst* is a pointer to where the received data will be written.
- @param length* is a pointer for returning the number of bytes received. Only 1 byte will
- be writtem to length*.
-
- @return
- @retval true if data has been received and is written to dst*
- @retval false if no data has been received.
-*/
-bool gzp_crypt_user_data_read(uint8_t* dst, uint8_t* length);
-
-
-/**
- Function emulating behavior of gzll_rx_start() in legeacy nRF24xx Gaell
- linbrary.
-
- This functions sets Gazell in Host mode and starts reception (enable).
-*/
-void gzll_rx_start(void);
-
-
-/** @} */
-/** @} */
-/** @} */
-
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/nrf.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,35 +0,0 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - - -#ifndef NRF_H -#define NRF_H - -#include "nordic_global.h" - -#ifndef _WIN32 - -/* Family selection for main includes. NRF51 must be selected. */ -#ifdef NRF51 - #include "nrf51.h" - #include "nrf51_bitfields.h" - #include "nrf51_deprecated.h" -#else - #error "Device family must be defined. See nrf.h." -#endif /* NRF51 */ - -#include "compiler_abstraction.h" - -#endif /* _WIN32 */ - -#endif /* NRF_H */ -
--- a/hw/nRF51822n/nordic/nrf-sdk/nrf51.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1246 +0,0 @@
-
-/****************************************************************************************************//**
- * @file nRF51.h
- *
- * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
- * nRF51 from Nordic Semiconductor.
- *
- * @version V2.4C
- * @date 19. December 2013
- *
- * @note Generated with SVDConv V2.77p
- * from CMSIS SVD File 'nRF51.xml' Version 2.4C,
- *
- * @par Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- *
- *******************************************************************************************************/
-
-
-
-/** @addtogroup Nordic Semiconductor
- * @{
- */
-
-/** @addtogroup nRF51
- * @{
- */
-
-#ifndef NRF51_H
-#define NRF51_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* ------------------------- Interrupt Number Definition ------------------------ */
-
-typedef enum {
-/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
- POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
- RADIO_IRQn = 1, /*!< 1 RADIO */
- UART0_IRQn = 2, /*!< 2 UART0 */
- SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
- SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
- GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
- ADC_IRQn = 7, /*!< 7 ADC */
- TIMER0_IRQn = 8, /*!< 8 TIMER0 */
- TIMER1_IRQn = 9, /*!< 9 TIMER1 */
- TIMER2_IRQn = 10, /*!< 10 TIMER2 */
- RTC0_IRQn = 11, /*!< 11 RTC0 */
- TEMP_IRQn = 12, /*!< 12 TEMP */
- RNG_IRQn = 13, /*!< 13 RNG */
- ECB_IRQn = 14, /*!< 14 ECB */
- CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
- WDT_IRQn = 16, /*!< 16 WDT */
- RTC1_IRQn = 17, /*!< 17 RTC1 */
- QDEC_IRQn = 18, /*!< 18 QDEC */
- LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
- SWI0_IRQn = 20, /*!< 20 SWI0 */
- SWI1_IRQn = 21, /*!< 21 SWI1 */
- SWI2_IRQn = 22, /*!< 22 SWI2 */
- SWI3_IRQn = 23, /*!< 23 SWI3 */
- SWI4_IRQn = 24, /*!< 24 SWI4 */
- SWI5_IRQn = 25 /*!< 25 SWI5 */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
- * @{
- */
-
-
-/* ================================================================================ */
-/* ================ Processor and Core Peripheral Section ================ */
-/* ================================================================================ */
-
-/* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
-#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
-#include "system_nrf51.h" /*!< nRF51 System */
-
-
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
-
-
-/* ------------------- Start of section using anonymous unions ------------------ */
-#if defined(__CC_ARM)
- #pragma push
- #pragma anon_unions
-#elif defined(__ICCARM__)
- #pragma language=extended
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
- #pragma warning 586
-#else
- #warning Not supported compiler type
-#endif
-
-
-typedef struct {
- __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
- __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
- __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
- __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
- __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
- __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
-} AMLI_RAMPRI_Type;
-
-typedef struct {
- __O uint32_t EN; /*!< Enable channel group. */
- __O uint32_t DIS; /*!< Disable channel group. */
-} PPI_TASKS_CHG_Type;
-
-typedef struct {
- __IO uint32_t EEP; /*!< Channel event end-point. */
- __IO uint32_t TEP; /*!< Channel task end-point. */
-} PPI_CH_Type;
-
-
-/* ================================================================================ */
-/* ================ POWER ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Power Control. (POWER)
- */
-
-typedef struct { /*!< POWER Structure */
- __I uint32_t RESERVED0[30];
- __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
- __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
- __I uint32_t RESERVED1[34];
- __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __IO uint32_t RESETREAS; /*!< Reset reason. */
- __I uint32_t RESERVED4[9];
- __I uint32_t RAMSTATUS; /*!< Ram status register. */
- __I uint32_t RESERVED5[53];
- __O uint32_t SYSTEMOFF; /*!< System off register. */
- __I uint32_t RESERVED6[3];
- __IO uint32_t POFCON; /*!< Power failure configuration. */
- __I uint32_t RESERVED7[2];
- __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
- register. */
- __I uint32_t RESERVED8;
- __IO uint32_t RAMON; /*!< Ram on/off. */
- __I uint32_t RESERVED9[7];
- __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
- is a retained register. */
- __I uint32_t RESERVED10[12];
- __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
- __I uint32_t RESERVED11[291];
- __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
-} NRF_POWER_Type;
-
-
-/* ================================================================================ */
-/* ================ CLOCK ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Clock control. (CLOCK)
- */
-
-typedef struct { /*!< CLOCK Structure */
- __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
- __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
- __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
- __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
- __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
- __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
- __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
- __I uint32_t RESERVED0[57];
- __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
- __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
- __I uint32_t RESERVED1;
- __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
- __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
- __I uint32_t RESERVED2[124];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[63];
- __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART triggered status. */
- __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
- __I uint32_t RESERVED4;
- __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
- __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
- __IO uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
- triggered. */
- __I uint32_t RESERVED5[62];
- __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
- __I uint32_t RESERVED6[7];
- __IO uint32_t CTIV; /*!< Calibration timer interval. */
- __I uint32_t RESERVED7[5];
- __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
-} NRF_CLOCK_Type;
-
-
-/* ================================================================================ */
-/* ================ MPU ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Memory Protection Unit. (MPU)
- */
-
-typedef struct { /*!< MPU Structure */
- __I uint32_t RESERVED0[330];
- __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
- __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
- __I uint32_t RESERVED1[52];
- __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
- __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
- __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
- __I uint32_t RESERVED2[256];
- __IO uint32_t ENRBDREG; /*!< Enable or disable RBD. */
-} NRF_MPU_Type;
-
-
-/* ================================================================================ */
-/* ================ PU ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Patch unit. (PU)
- */
-
-typedef struct { /*!< PU Structure */
- __I uint32_t RESERVED0[448];
- __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
- __I uint32_t RESERVED1[24];
- __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
- __I uint32_t RESERVED2[24];
- __IO uint32_t PATCHEN; /*!< Patch enable register. */
- __IO uint32_t PATCHENSET; /*!< Patch enable register. */
- __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
-} NRF_PU_Type;
-
-
-/* ================================================================================ */
-/* ================ AMLI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief AHB Multi-Layer Interface. (AMLI)
- */
-
-typedef struct { /*!< AMLI Structure */
- __I uint32_t RESERVED0[896];
- AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
-} NRF_AMLI_Type;
-
-
-/* ================================================================================ */
-/* ================ RADIO ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief The radio. (RADIO)
- */
-
-typedef struct { /*!< RADIO Structure */
- __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
- __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
- __O uint32_t TASKS_START; /*!< Start radio. */
- __O uint32_t TASKS_STOP; /*!< Stop radio. */
- __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
- __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
- __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
- __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
- __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
- __I uint32_t RESERVED0[55];
- __IO uint32_t EVENTS_READY; /*!< Ready event. */
- __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
- __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
- __IO uint32_t EVENTS_END; /*!< End event. */
- __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
- __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
- __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
- __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
- sample is ready for readout at the RSSISAMPLE register. */
- __I uint32_t RESERVED1[2];
- __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
- __I uint32_t RESERVED2[53];
- __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
- __I uint32_t RESERVED3[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED4[61];
- __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
- __I uint32_t RESERVED5;
- __I uint32_t RXMATCH; /*!< Received address. */
- __I uint32_t RXCRC; /*!< Received CRC. */
- __IO uint32_t DAI; /*!< Device address match index. */
- __I uint32_t RESERVED6[60];
- __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
- __IO uint32_t FREQUENCY; /*!< Frequency. */
- __IO uint32_t TXPOWER; /*!< Output power. */
- __IO uint32_t MODE; /*!< Data rate and modulation. */
- __IO uint32_t PCNF0; /*!< Packet configuration 0. */
- __IO uint32_t PCNF1; /*!< Packet configuration 1. */
- __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
- __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
- __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
- __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
- __IO uint32_t TXADDRESS; /*!< Transmit address select. */
- __IO uint32_t RXADDRESSES; /*!< Receive address select. */
- __IO uint32_t CRCCNF; /*!< CRC configuration. */
- __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
- __IO uint32_t CRCINIT; /*!< CRC initial value. */
- __IO uint32_t TEST; /*!< Test features enable register. */
- __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
- __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
- __I uint32_t RESERVED7;
- __I uint32_t STATE; /*!< Current radio state. */
- __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
- __I uint32_t RESERVED8[2];
- __IO uint32_t BCC; /*!< Bit counter compare. */
- __I uint32_t RESERVED9[39];
- __IO uint32_t DAB[8]; /*!< Device address base segment. */
- __IO uint32_t DAP[8]; /*!< Device address prefix. */
- __IO uint32_t DACNF; /*!< Device address match configuration. */
- __I uint32_t RESERVED10[56];
- __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
- __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
- __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
- __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
- __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
- __I uint32_t RESERVED11[561];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RADIO_Type;
-
-
-/* ================================================================================ */
-/* ================ UART ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Universal Asynchronous Receiver/Transmitter. (UART)
- */
-
-typedef struct { /*!< UART Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
- __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
- __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
- __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
- __I uint32_t RESERVED0[3];
- __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
- __I uint32_t RESERVED1[56];
- __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
- __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
- __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
- __I uint32_t RESERVED2[4];
- __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
- __I uint32_t RESERVED3;
- __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
- __I uint32_t RESERVED4[7];
- __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
- __I uint32_t RESERVED5[46];
- __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
- __I uint32_t RESERVED6[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED7[93];
- __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
- __I uint32_t RESERVED8[31];
- __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
- __I uint32_t RESERVED9;
- __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
- __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
- __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
- __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
- __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
- Once read the character is consummed. If read when no character
- available, the UART will stop working. */
- __O uint32_t TXD; /*!< TXD register. */
- __I uint32_t RESERVED10;
- __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
- __I uint32_t RESERVED11[17];
- __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
- __I uint32_t RESERVED12[675];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_UART_Type;
-
-
-/* ================================================================================ */
-/* ================ SPI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief SPI master 0. (SPI)
- */
-
-typedef struct { /*!< SPI Structure */
- __I uint32_t RESERVED0[66];
- __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
- __I uint32_t RESERVED1[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[125];
- __IO uint32_t ENABLE; /*!< Enable SPI. */
- __I uint32_t RESERVED3;
- __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
- __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
- __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
- __I uint32_t RESERVED4;
- __IO uint32_t RXD; /*!< RX data. */
- __IO uint32_t TXD; /*!< TX data. */
- __I uint32_t RESERVED5;
- __IO uint32_t FREQUENCY; /*!< SPI frequency */
- __I uint32_t RESERVED6[11];
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED7[681];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_SPI_Type;
-
-
-/* ================================================================================ */
-/* ================ TWI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Two-wire interface master 0. (TWI)
- */
-
-typedef struct { /*!< TWI Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
- __I uint32_t RESERVED1[2];
- __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
- __I uint32_t RESERVED2;
- __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
- __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
- __I uint32_t RESERVED3[56];
- __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
- __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
- __I uint32_t RESERVED4[4];
- __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
- __I uint32_t RESERVED5;
- __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
- __I uint32_t RESERVED6[4];
- __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
- __I uint32_t RESERVED7[3];
- __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
- __I uint32_t RESERVED8[45];
- __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
- __I uint32_t RESERVED9[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED10[110];
- __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
- __I uint32_t RESERVED11[14];
- __IO uint32_t ENABLE; /*!< Enable two-wire master. */
- __I uint32_t RESERVED12;
- __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
- __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
- __I uint32_t RESERVED13[2];
- __IO uint32_t RXD; /*!< RX data register. */
- __IO uint32_t TXD; /*!< TX data register. */
- __I uint32_t RESERVED14;
- __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
- __I uint32_t RESERVED15[24];
- __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
- __I uint32_t RESERVED16[668];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TWI_Type;
-
-
-/* ================================================================================ */
-/* ================ SPIS ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief SPI slave 1. (SPIS)
- */
-
-typedef struct { /*!< SPIS Structure */
- __I uint32_t RESERVED0[9];
- __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
- __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
- __I uint32_t RESERVED1[54];
- __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
- __I uint32_t RESERVED2[8];
- __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
- __I uint32_t RESERVED3[53];
- __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
- __I uint32_t RESERVED4[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED5[61];
- __I uint32_t SEMSTAT; /*!< Semaphore status. */
- __I uint32_t RESERVED6[15];
- __IO uint32_t STATUS; /*!< Status from last transaction. */
- __I uint32_t RESERVED7[47];
- __IO uint32_t ENABLE; /*!< Enable SPIS. */
- __I uint32_t RESERVED8;
- __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
- __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
- __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
- __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
- __I uint32_t RESERVED9[7];
- __IO uint32_t RXDPTR; /*!< RX data pointer. */
- __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
- __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
- __I uint32_t RESERVED10;
- __IO uint32_t TXDPTR; /*!< TX data pointer. */
- __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
- __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
- __I uint32_t RESERVED11;
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED12;
- __IO uint32_t DEF; /*!< Default character. */
- __I uint32_t RESERVED13[24];
- __IO uint32_t ORC; /*!< Over-read character. */
- __I uint32_t RESERVED14[654];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_SPIS_Type;
-
-
-/* ================================================================================ */
-/* ================ GPIOTE ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief GPIO tasks and events. (GPIOTE)
- */
-
-typedef struct { /*!< GPIOTE Structure */
- __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
- __I uint32_t RESERVED0[60];
- __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
- __I uint32_t RESERVED1[27];
- __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
- __I uint32_t RESERVED2[97];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[129];
- __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
- __I uint32_t RESERVED4[695];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_GPIOTE_Type;
-
-
-/* ================================================================================ */
-/* ================ ADC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Analog to digital converter. (ADC)
- */
-
-typedef struct { /*!< ADC Structure */
- __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
- __O uint32_t TASKS_STOP; /*!< Stop ADC. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[61];
- __I uint32_t BUSY; /*!< ADC busy register. */
- __I uint32_t RESERVED3[63];
- __IO uint32_t ENABLE; /*!< ADC enable. */
- __IO uint32_t CONFIG; /*!< ADC configuration register. */
- __I uint32_t RESULT; /*!< Result of ADC conversion. */
- __I uint32_t RESERVED4[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_ADC_Type;
-
-
-/* ================================================================================ */
-/* ================ TIMER ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Timer 0. (TIMER)
- */
-
-typedef struct { /*!< TIMER Structure */
- __O uint32_t TASKS_START; /*!< Start Timer. */
- __O uint32_t TASKS_STOP; /*!< Stop Timer. */
- __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
- __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
- __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
- __I uint32_t RESERVED0[11];
- __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
- __I uint32_t RESERVED2[44];
- __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
- __I uint32_t RESERVED3[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED4[126];
- __IO uint32_t MODE; /*!< Timer Mode selection. */
- __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
- __I uint32_t RESERVED5;
- __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
- clock frequency is divided by 2^SCALE. */
- __I uint32_t RESERVED6[11];
- __IO uint32_t CC[4]; /*!< Capture/compare registers. */
- __I uint32_t RESERVED7[683];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TIMER_Type;
-
-
-/* ================================================================================ */
-/* ================ RTC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Real time counter 0. (RTC)
- */
-
-typedef struct { /*!< RTC Structure */
- __O uint32_t TASKS_START; /*!< Start RTC Counter. */
- __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
- __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
- __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
- __I uint32_t RESERVED0[60];
- __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
- __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
- __I uint32_t RESERVED1[14];
- __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
- __I uint32_t RESERVED2[109];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[13];
- __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
- __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
- the value of EVTEN. */
- __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
- gives the value of EVTEN. */
- __I uint32_t RESERVED4[110];
- __IO uint32_t COUNTER; /*!< Current COUNTER value. */
- __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
- Must be written when RTC is STOPed. */
- __I uint32_t RESERVED5[13];
- __IO uint32_t CC[4]; /*!< Capture/compare registers. */
- __I uint32_t RESERVED6[683];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RTC_Type;
-
-
-/* ================================================================================ */
-/* ================ TEMP ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Temperature Sensor. (TEMP)
- */
-
-typedef struct { /*!< TEMP Structure */
- __O uint32_t TASKS_START; /*!< Start temperature measurement. */
- __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[127];
- __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
- __I uint32_t RESERVED3[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TEMP_Type;
-
-
-/* ================================================================================ */
-/* ================ RNG ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Random Number Generator. (RNG)
- */
-
-typedef struct { /*!< RNG Structure */
- __O uint32_t TASKS_START; /*!< Start the random number generator. */
- __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
- __I uint32_t RESERVED1[63];
- __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
- __I uint32_t RESERVED3[126];
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t VALUE; /*!< RNG random number. */
- __I uint32_t RESERVED4[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RNG_Type;
-
-
-/* ================================================================================ */
-/* ================ ECB ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief AES ECB Mode Encryption. (ECB)
- */
-
-typedef struct { /*!< ECB Structure */
- __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
- will not initiate a new encryption and the ERRORECB event will
- be triggered. */
- __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
- this will will trigger the ERRORECB event. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
- __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
- error. */
- __I uint32_t RESERVED1[127];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
- __I uint32_t RESERVED3[701];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_ECB_Type;
-
-
-/* ================================================================================ */
-/* ================ AAR ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Accelerated Address Resolver. (AAR)
- */
-
-typedef struct { /*!< AAR Structure */
- __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
- data structure. */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
- __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
- __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t STATUS; /*!< Resolution status. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable AAR. */
- __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
- __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
- __I uint32_t RESERVED5;
- __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
- resolution. A minimum of 3 bytes must be reserved. */
- __I uint32_t RESERVED6[697];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_AAR_Type;
-
-
-/* ================================================================================ */
-/* ================ CCM ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief AES CCM Mode Encryption. (CCM)
- */
-
-typedef struct { /*!< CCM Structure */
- __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
- itself when completed. */
- __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
- completed. */
- __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
- __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
- __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< CCM enable. */
- __IO uint32_t MODE; /*!< Operation mode. */
- __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
- __IO uint32_t INPTR; /*!< Pointer to input packet. */
- __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
- resolution. A minimum of 43 bytes must be reserved. */
- __I uint32_t RESERVED5[697];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_CCM_Type;
-
-
-/* ================================================================================ */
-/* ================ WDT ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Watchdog Timer. (WDT)
- */
-
-typedef struct { /*!< WDT Structure */
- __O uint32_t TASKS_START; /*!< Start the watchdog. */
- __I uint32_t RESERVED0[63];
- __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[61];
- __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
- __I uint32_t REQSTATUS; /*!< Request status. */
- __I uint32_t RESERVED3[63];
- __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
- __IO uint32_t RREN; /*!< Reload request enable. */
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED4[60];
- __O uint32_t RR[8]; /*!< Reload requests registers. */
- __I uint32_t RESERVED5[631];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_WDT_Type;
-
-
-/* ================================================================================ */
-/* ================ QDEC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Rotary decoder. (QDEC)
- */
-
-typedef struct { /*!< QDEC Structure */
- __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
- __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
- __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
- and clears the ACC registers. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
- __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
- ACC register different than zero. */
- __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[125];
- __IO uint32_t ENABLE; /*!< Enable the QDEC. */
- __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
- __IO uint32_t SAMPLEPER; /*!< Sample period. */
- __I int32_t SAMPLE; /*!< Motion sample value. */
- __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
- __I int32_t ACC; /*!< Accumulated valid transitions register. */
- __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
- task. */
- __IO uint32_t PSELLED; /*!< Pin select for LED output. */
- __IO uint32_t PSELA; /*!< Pin select for phase A input. */
- __IO uint32_t PSELB; /*!< Pin select for phase B input. */
- __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
- __I uint32_t RESERVED4[5];
- __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
- __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
- __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
- task. */
- __I uint32_t RESERVED5[684];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_QDEC_Type;
-
-
-/* ================================================================================ */
-/* ================ LPCOMP ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Wakeup Comparator. (LPCOMP)
- */
-
-typedef struct { /*!< LPCOMP Structure */
- __O uint32_t TASKS_START; /*!< Start the comparator. */
- __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
- __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
- __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
- __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
- __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t RESULT; /*!< Result of last compare. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
- __IO uint32_t PSEL; /*!< Input pin select. */
- __IO uint32_t REFSEL; /*!< Reference select. */
- __IO uint32_t EXTREFSEL; /*!< External reference select. */
- __I uint32_t RESERVED5[4];
- __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
- __I uint32_t RESERVED6[694];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_LPCOMP_Type;
-
-
-/* ================================================================================ */
-/* ================ COMP ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Comparator. (COMP)
- */
-
-typedef struct { /*!< COMP Structure */
- __O uint32_t TASKS_START; /*!< Start the comparator. */
- __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
- __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
- __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
- __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
- __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t RESULT; /*!< Compare result. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable the COMP. */
- __IO uint32_t PSEL; /*!< Input pin select. */
- __IO uint32_t REFSEL; /*!< Reference select. */
- __IO uint32_t EXTREFSEL; /*!< External reference select. */
- __I uint32_t RESERVED5[8];
- __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
- __IO uint32_t MODE; /*!< Mode configuration. */
- __I uint32_t RESERVED6[689];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_COMP_Type;
-
-
-/* ================================================================================ */
-/* ================ SWI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief SW Interrupts. (SWI)
- */
-
-typedef struct { /*!< SWI Structure */
- __I uint32_t UNUSED; /*!< Unused. */
-} NRF_SWI_Type;
-
-
-/* ================================================================================ */
-/* ================ NVMC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Non Volatile Memory Controller. (NVMC)
- */
-
-typedef struct { /*!< NVMC Structure */
- __I uint32_t RESERVED0[256];
- __I uint32_t READY; /*!< Ready flag. */
- __I uint32_t RESERVED1[64];
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
- __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
- __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
- __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
-} NRF_NVMC_Type;
-
-
-/* ================================================================================ */
-/* ================ PPI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief PPI controller. (PPI)
- */
-
-typedef struct { /*!< PPI Structure */
- PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
- __I uint32_t RESERVED0[312];
- __IO uint32_t CHEN; /*!< Channel enable. */
- __IO uint32_t CHENSET; /*!< Channel enable set. */
- __IO uint32_t CHENCLR; /*!< Channel enable clear. */
- __I uint32_t RESERVED1;
- PPI_CH_Type CH[16]; /*!< PPI Channel. */
- __I uint32_t RESERVED2[156];
- __IO uint32_t CHG[4]; /*!< Channel group configuration. */
-} NRF_PPI_Type;
-
-
-/* ================================================================================ */
-/* ================ FICR ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Factory Information Configuration. (FICR)
- */
-
-typedef struct { /*!< FICR Structure */
- __I uint32_t RESERVED0[4];
- __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
- __I uint32_t CODESIZE; /*!< Code memory size in pages. */
- __I uint32_t RBD; /*!< RBD. */
- __I uint32_t RESERVED1[3];
- __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
- __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
- __I uint32_t RESERVED2;
- __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
- __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
- __I uint32_t RESERVED3[5];
- __I uint32_t CONFIGID; /*!< Configuration identifier. */
- __I uint32_t DEVICEID[2]; /*!< Device identifier. */
- __I uint32_t RESERVED4[6];
- __I uint32_t ER[4]; /*!< Encryption root. */
- __I uint32_t IR[4]; /*!< Identity root. */
- __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
- __I uint32_t DEVICEADDR[2]; /*!< Device address. */
- __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
- __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
- mode. */
- __I uint32_t RESERVED5[10];
- __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
- mode. */
-} NRF_FICR_Type;
-
-
-/* ================================================================================ */
-/* ================ UICR ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief User Information Configuration. (UICR)
- */
-
-typedef struct { /*!< UICR Structure */
- __IO uint32_t CLENR0; /*!< Length of code region 0. */
- __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
- __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
- __I uint32_t RESERVED0;
- __I uint32_t FWID; /*!< Firmware ID. */
- __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
-} NRF_UICR_Type;
-
-
-/* ================================================================================ */
-/* ================ GPIO ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief General purpose input and output. (GPIO)
- */
-
-typedef struct { /*!< GPIO Structure */
- __I uint32_t RESERVED0[321];
- __IO uint32_t OUT; /*!< Write GPIO port. */
- __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
- __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
- __I uint32_t IN; /*!< Read GPIO port. */
- __IO uint32_t DIR; /*!< Direction of GPIO pins. */
- __IO uint32_t DIRSET; /*!< DIR set register. */
- __IO uint32_t DIRCLR; /*!< DIR clear register. */
- __I uint32_t RESERVED1[120];
- __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
-} NRF_GPIO_Type;
-
-
-/* -------------------- End of section using anonymous unions ------------------- */
-#if defined(__CC_ARM)
- #pragma pop
-#elif defined(__ICCARM__)
- /* leave anonymous unions enabled */
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
- /* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
- #pragma warning restore
-#else
- #warning Not supported compiler type
-#endif
-
-
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-
-#define NRF_POWER_BASE 0x40000000UL
-#define NRF_CLOCK_BASE 0x40000000UL
-#define NRF_MPU_BASE 0x40000000UL
-#define NRF_PU_BASE 0x40000000UL
-#define NRF_AMLI_BASE 0x40000000UL
-#define NRF_RADIO_BASE 0x40001000UL
-#define NRF_UART0_BASE 0x40002000UL
-#define NRF_SPI0_BASE 0x40003000UL
-#define NRF_TWI0_BASE 0x40003000UL
-#define NRF_SPI1_BASE 0x40004000UL
-#define NRF_TWI1_BASE 0x40004000UL
-#define NRF_SPIS1_BASE 0x40004000UL
-#define NRF_GPIOTE_BASE 0x40006000UL
-#define NRF_ADC_BASE 0x40007000UL
-#define NRF_TIMER0_BASE 0x40008000UL
-#define NRF_TIMER1_BASE 0x40009000UL
-#define NRF_TIMER2_BASE 0x4000A000UL
-#define NRF_RTC0_BASE 0x4000B000UL
-#define NRF_TEMP_BASE 0x4000C000UL
-#define NRF_RNG_BASE 0x4000D000UL
-#define NRF_ECB_BASE 0x4000E000UL
-#define NRF_AAR_BASE 0x4000F000UL
-#define NRF_CCM_BASE 0x4000F000UL
-#define NRF_WDT_BASE 0x40010000UL
-#define NRF_RTC1_BASE 0x40011000UL
-#define NRF_QDEC_BASE 0x40012000UL
-#define NRF_LPCOMP_BASE 0x40013000UL
-#define NRF_COMP_BASE 0x40013000UL
-#define NRF_SWI_BASE 0x40014000UL
-#define NRF_NVMC_BASE 0x4001E000UL
-#define NRF_PPI_BASE 0x4001F000UL
-#define NRF_FICR_BASE 0x10000000UL
-#define NRF_UICR_BASE 0x10001000UL
-#define NRF_GPIO_BASE 0x50000000UL
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-
-#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
-#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
-#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
-#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
-#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
-#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
-#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
-#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
-#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
-#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
-#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
-#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
-#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
-#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
-#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
-#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
-#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
-#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
-#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
-#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
-#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
-#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
-#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
-#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
-#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
-#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
-#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
-#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
-#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
-#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
-#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
-#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
-#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
-#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group nRF51 */
-/** @} */ /* End of group Nordic Semiconductor */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* nRF51_H */
-
--- a/hw/nRF51822n/nordic/nrf-sdk/nrf51_bitfields.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6762 +0,0 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - - -#ifndef __NRF51_BITS_H -#define __NRF51_BITS_H - -/*lint ++flb "Enter library region */ - -#include <core_cm0.h> -#include "nordic_global.h" - -/* Peripheral: AAR */ -/* Description: Accelerated Address Resolver. */ - -/* Register: AAR_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on NOTRESOLVED event. */ -#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ -#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ -#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on RESOLVED event. */ -#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ -#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ -#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on END event. */ -#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ -#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: AAR_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on NOTRESOLVED event. */ -#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ -#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ -#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on RESOLVED event. */ -#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ -#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ -#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDKSGEN event. */ -#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ -#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: AAR_STATUS */ -/* Description: Resolution status. */ - -/* Bits 3..0 : The IRK used last time an address was resolved. */ -#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ - -/* Register: AAR_ENABLE */ -/* Description: Enable AAR. */ - -/* Bits 1..0 : Enable AAR. */ -#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ -#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ - -/* Register: AAR_NIRK */ -/* Description: Number of Identity root Keys in the IRK data structure. */ - -/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ -#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ -#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ - -/* Register: AAR_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: ADC */ -/* Description: Analog to digital converter. */ - -/* Register: ADC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on END event. */ -#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ -#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: ADC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on END event. */ -#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ -#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: ADC_BUSY */ -/* Description: ADC busy register. */ - -/* Bit 0 : ADC busy register. */ -#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ -#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ -#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ -#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ - -/* Register: ADC_ENABLE */ -/* Description: ADC enable. */ - -/* Bits 1..0 : ADC enable. */ -#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ -#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ - -/* Register: ADC_CONFIG */ -/* Description: ADC configuration register. */ - -/* Bits 17..16 : ADC external reference pin selection. */ -#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ -#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ -#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ -#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ - -/* Bits 15..8 : ADC analog pin selection. */ -#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ -#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ -#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ - -/* Bits 6..5 : ADC reference selection. */ -#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ -#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ -#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ -#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ -#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ - -/* Bits 4..2 : ADC input selection. */ -#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ -#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ -#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ - -/* Bits 1..0 : ADC resolution. */ -#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ -#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ -#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ -#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ -#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ - -/* Register: ADC_RESULT */ -/* Description: Result of ADC conversion. */ - -/* Bits 9..0 : Result of ADC conversion. */ -#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ - -/* Register: ADC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: AMLI */ -/* Description: AHB Multi-Layer Interface. */ - -/* Register: AMLI_RAMPRI_CPU0 */ -/* Description: Configurable priority configuration register for CPU0. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_SPIS1 */ -/* Description: Configurable priority configuration register for SPIS1. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_RADIO */ -/* Description: Configurable priority configuration register for RADIO. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_ECB */ -/* Description: Configurable priority configuration register for ECB. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_CCM */ -/* Description: Configurable priority configuration register for CCM. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_AAR */ -/* Description: Configurable priority configuration register for AAR. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Peripheral: CCM */ -/* Description: AES CCM Mode Encryption. */ - -/* Register: CCM_SHORTS */ -/* Description: Shortcut for the CCM. */ - -/* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: CCM_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on ERROR event. */ -#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ -#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on ENDCRYPT event. */ -#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ -#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ -#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on ENDKSGEN event. */ -#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ -#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ -#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: CCM_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on ERROR event. */ -#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ -#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on ENDCRYPT event. */ -#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ -#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ -#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDKSGEN event. */ -#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ -#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ -#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: CCM_MICSTATUS */ -/* Description: CCM RX MIC check result. */ - -/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ -#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ -#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ -#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ -#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ - -/* Register: CCM_ENABLE */ -/* Description: CCM enable. */ - -/* Bits 1..0 : CCM enable. */ -#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ -#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ - -/* Register: CCM_MODE */ -/* Description: Operation mode. */ - -/* Bit 0 : CCM mode operation. */ -#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ -#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ - -/* Register: CCM_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: CLOCK */ -/* Description: Clock control. */ - -/* Register: CLOCK_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 4 : Enable interrupt on CTTO event. */ -#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ -#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ -#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on DONE event. */ -#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ -#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ -#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: CLOCK_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 4 : Disable interrupt on CTTO event. */ -#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ -#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ -#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on DONE event. */ -#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ -#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ -#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: CLOCK_HFCLKRUN */ -/* Description: Task HFCLKSTART triggered status. */ - -/* Bit 0 : Task HFCLKSTART triggered or not. */ -#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART not triggered. */ -#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART not triggered. */ - -/* Register: CLOCK_HFCLKSTAT */ -/* Description: High frequency clock status. */ - -/* Bit 16 : State for the HFCLK. */ -#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ -#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ - -/* Bit 0 : Active clock source for the HF clock. */ -#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ -#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ - -/* Register: CLOCK_LFCLKRUN */ -/* Description: Task LFCLKSTART triggered status. */ - -/* Bit 0 : Task LFCLKSTART triggered or not. */ -#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART not triggered. */ -#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART not triggered. */ - -/* Register: CLOCK_LFCLKSTAT */ -/* Description: Low frequency clock status. */ - -/* Bit 16 : State for the LF clock. */ -#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ -#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ - -/* Bits 1..0 : Active clock source for the LF clock. */ -#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ -#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ -#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ - -/* Register: CLOCK_LFCLKSRCCOPY */ -/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ - -/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ - -/* Register: CLOCK_LFCLKSRC */ -/* Description: Clock source for the LFCLK clock. */ - -/* Bits 1..0 : Clock source. */ -#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ -#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ -#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ - -/* Register: CLOCK_CTIV */ -/* Description: Calibration timer interval. */ - -/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ -#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ -#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ - -/* Register: CLOCK_XTALFREQ */ -/* Description: Crystal frequency. */ - -/* Bits 7..0 : External Xtal frequency selection. */ -#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used. */ -#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used. */ - - -/* Peripheral: COMP */ -/* Description: Comparator. */ - -/* Register: COMP_SHORTS */ -/* Description: Shortcut for the COMP. */ - -/* Bit 4 : Short-cut between CROSS event and STOP task. */ -#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Short-cut between UP event and STOP task. */ -#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Short-cut between DOWN event and STOP task. */ -#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Short-cut between RADY event and STOP task. */ -#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Short-cut between READY event and SAMPLE task. */ -#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: COMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 3 : Enable interrupt on CROSS event. */ -#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on UP event. */ -#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on DOWN event. */ -#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: COMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 3 : Disable interrupt on CROSS event. */ -#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on UP event. */ -#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on DOWN event. */ -#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: COMP_RESULT */ -/* Description: Compare result. */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define COMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ -#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ - -/* Register: COMP_ENABLE */ -/* Description: Enable the COMP. */ - -/* Bits 1..0 : Enable or disable COMP. */ -#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled COMP. */ -#define COMP_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable COMP. */ - -/* Register: COMP_PSEL */ -/* Description: Input pin select. */ - -/* Bits 2..0 : Analog input pin select. */ -#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ - -/* Register: COMP_REFSEL */ -/* Description: Reference select. */ - -/* Bits 2..0 : Reference select. */ -#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Int1V5 (0UL) /*!< Use internal 1V5 as reference. */ -#define COMP_REFSEL_REFSEL_Int2V0 (1UL) /*!< Use internal 2V0 as reference. */ -#define COMP_REFSEL_REFSEL_Int2V5 (2UL) /*!< Use internal 2V5 as reference. */ -#define COMP_REFSEL_REFSEL_Supply (4UL) /*!< Use supply as reference. */ -#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< Use external analog reference as reference. */ - -/* Register: COMP_EXTREFSEL */ -/* Description: External reference select. */ - -/* Bit 0 : External analog reference pin selection. */ -#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ - -/* Register: COMP_TH */ -/* Description: Threshold configuration for hysteresis unit. */ - -/* Bits 13..8 : VDOWN configuration. */ -#define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */ -#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ - -/* Bits 5..0 : VUP configuration. */ -#define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */ -#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ - -/* Register: COMP_MODE */ -/* Description: Mode configuration. */ - -/* Bit 8 : Main operation mode. */ -#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ -#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ -#define COMP_MODE_MAIN_Single (0UL) /*!< Single ended mode. */ -#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode. */ - -/* Bits 1..0 : Speed and power mode. */ -#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ -#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ -#define COMP_MODE_SP_Low (0UL) /*!< Low power mode. */ -#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode. */ -#define COMP_MODE_SP_High (2UL) /*!< High speed mode. */ - -/* Register: COMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define COMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define COMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define COMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: ECB */ -/* Description: AES ECB Mode Encryption. */ - -/* Register: ECB_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 1 : Enable interrupt on ERRORECB event. */ -#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ -#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ -#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on ENDECB event. */ -#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ -#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ -#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: ECB_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 1 : Disable interrupt on ERRORECB event. */ -#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ -#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ -#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDECB event. */ -#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ -#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ -#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: ECB_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: FICR */ -/* Description: Factory Information Configuration. */ - -/* Register: FICR_RBD */ -/* Description: RBD. */ - -/* Bit 0 : RBD. */ -#define FICR_RBD_RBD_Pos (0UL) /*!< Position of RBD field. */ -#define FICR_RBD_RBD_Msk (0x1UL << FICR_RBD_RBD_Pos) /*!< Bit mask of RBD field. */ -#define FICR_RBD_RBD_NoRoyalty (0x0UL) /*!< No royalty. */ -#define FICR_RBD_RBD_Royalty (0x1UL) /*!< Royalty. */ - -/* Register: FICR_PPFC */ -/* Description: Pre-programmed factory code present. */ - -/* Bits 7..0 : Pre-programmed factory code present. */ -#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ -#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ -#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ -#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ - -/* Register: FICR_CONFIGID */ -/* Description: Configuration identifier. */ - -/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ -#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ -#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ - -/* Bits 15..0 : Hardware Identification Number. */ -#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ -#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ - -/* Register: FICR_DEVICEADDRTYPE */ -/* Description: Device address type. */ - -/* Bit 0 : Device address type. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ - -/* Register: FICR_OVERRIDEEN */ -/* Description: Radio calibration override enable. */ - -/* Bit 3 : Override default values for BLE_1Mbit mode. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ - -/* Bit 0 : Override default values for NRF_1Mbit mode. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ - - -/* Peripheral: GPIO */ -/* Description: General purpose input and output. */ - -/* Register: GPIO_OUT */ -/* Description: Write GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ - -/* Register: GPIO_OUTSET */ -/* Description: Set individual bits in GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ - -/* Register: GPIO_OUTCLR */ -/* Description: Clear individual bits in GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ - -/* Register: GPIO_IN */ -/* Description: Read GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ - -/* Register: GPIO_DIR */ -/* Description: Direction of GPIO pins. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ - -/* Register: GPIO_DIRSET */ -/* Description: DIR set register. */ - -/* Bit 31 : Set as output pin 31. */ -#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ - -/* Bit 30 : Set as output pin 30. */ -#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ - -/* Bit 29 : Set as output pin 29. */ -#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ - -/* Bit 28 : Set as output pin 28. */ -#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ - -/* Bit 27 : Set as output pin 27. */ -#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ - -/* Bit 26 : Set as output pin 26. */ -#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ - -/* Bit 25 : Set as output pin 25. */ -#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ - -/* Bit 24 : Set as output pin 24. */ -#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ - -/* Bit 23 : Set as output pin 23. */ -#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ - -/* Bit 22 : Set as output pin 22. */ -#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ - -/* Bit 21 : Set as output pin 21. */ -#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ - -/* Bit 20 : Set as output pin 20. */ -#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ - -/* Bit 19 : Set as output pin 19. */ -#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ - -/* Bit 18 : Set as output pin 18. */ -#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ - -/* Bit 17 : Set as output pin 17. */ -#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ - -/* Bit 16 : Set as output pin 16. */ -#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ - -/* Bit 15 : Set as output pin 15. */ -#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ - -/* Bit 14 : Set as output pin 14. */ -#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ - -/* Bit 13 : Set as output pin 13. */ -#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ - -/* Bit 12 : Set as output pin 12. */ -#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ - -/* Bit 11 : Set as output pin 11. */ -#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ - -/* Bit 10 : Set as output pin 10. */ -#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ - -/* Bit 9 : Set as output pin 9. */ -#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ - -/* Bit 8 : Set as output pin 8. */ -#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ - -/* Bit 7 : Set as output pin 7. */ -#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ - -/* Bit 6 : Set as output pin 6. */ -#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ - -/* Bit 5 : Set as output pin 5. */ -#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ - -/* Bit 4 : Set as output pin 4. */ -#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ - -/* Bit 3 : Set as output pin 3. */ -#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ - -/* Bit 2 : Set as output pin 2. */ -#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ - -/* Bit 1 : Set as output pin 1. */ -#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ - -/* Bit 0 : Set as output pin 0. */ -#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ - -/* Register: GPIO_DIRCLR */ -/* Description: DIR clear register. */ - -/* Bit 31 : Set as input pin 31. */ -#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 30 : Set as input pin 30. */ -#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 29 : Set as input pin 29. */ -#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 28 : Set as input pin 28. */ -#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 27 : Set as input pin 27. */ -#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 26 : Set as input pin 26. */ -#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 25 : Set as input pin 25. */ -#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 24 : Set as input pin 24. */ -#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 23 : Set as input pin 23. */ -#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 22 : Set as input pin 22. */ -#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 21 : Set as input pin 21. */ -#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 20 : Set as input pin 20. */ -#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 19 : Set as input pin 19. */ -#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 18 : Set as input pin 18. */ -#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 17 : Set as input pin 17. */ -#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 16 : Set as input pin 16. */ -#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 15 : Set as input pin 15. */ -#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 14 : Set as input pin 14. */ -#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 13 : Set as input pin 13. */ -#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 12 : Set as input pin 12. */ -#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 11 : Set as input pin 11. */ -#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 10 : Set as input pin 10. */ -#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 9 : Set as input pin 9. */ -#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 8 : Set as input pin 8. */ -#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 7 : Set as input pin 7. */ -#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 6 : Set as input pin 6. */ -#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 5 : Set as input pin 5. */ -#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 4 : Set as input pin 4. */ -#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 3 : Set as input pin 3. */ -#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 2 : Set as input pin 2. */ -#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 1 : Set as input pin 1. */ -#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 0 : Set as input pin 0. */ -#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ - -/* Register: GPIO_PIN_CNF */ -/* Description: Configuration of GPIO pins. */ - -/* Bits 17..16 : Pin sensing mechanism. */ -#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ -#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ -#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ - -/* Bits 10..8 : Drive configuration. */ -#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ - -/* Bits 3..2 : Pull-up or -down configuration. */ -#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ -#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ -#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ -#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ -#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ - -/* Bit 1 : Connect or disconnect input path. */ -#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ -#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ - -/* Bit 0 : Pin direction. */ -#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ -#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ -#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ -#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ - - -/* Peripheral: GPIOTE */ -/* Description: GPIO tasks and events. */ - -/* Register: GPIOTE_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 31 : Enable interrupt on PORT event. */ -#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ -#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on IN[3] event. */ -#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on IN[2] event. */ -#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on IN[1] event. */ -#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on IN[0] event. */ -#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: GPIOTE_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 31 : Disable interrupt on PORT event. */ -#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on IN[3] event. */ -#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on IN[2] event. */ -#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on IN[1] event. */ -#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on IN[0] event. */ -#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: GPIOTE_CONFIG */ -/* Description: Channel configuration registers. */ - -/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ -#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ -#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ - -/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ -#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ -#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ -#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ - -/* Bits 12..8 : Pin select. */ -#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ -#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ - -/* Bits 1..0 : Mode */ -#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ -#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ -#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ - -/* Register: GPIOTE_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: LPCOMP */ -/* Description: Wakeup Comparator. */ - -/* Register: LPCOMP_SHORTS */ -/* Description: Shortcut for the LPCOMP. */ - -/* Bit 4 : Short-cut between CROSS event and STOP task. */ -#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Short-cut between UP event and STOP task. */ -#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Short-cut between DOWN event and STOP task. */ -#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Short-cut between RADY event and STOP task. */ -#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Short-cut between READY event and SAMPLE task. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: LPCOMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 3 : Enable interrupt on CROSS event. */ -#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on UP event. */ -#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on DOWN event. */ -#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: LPCOMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 3 : Disable interrupt on CROSS event. */ -#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on UP event. */ -#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on DOWN event. */ -#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: LPCOMP_RESULT */ -/* Description: Result of last compare. */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ -#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ - -/* Register: LPCOMP_ENABLE */ -/* Description: Enable the LPCOMP. */ - -/* Bits 1..0 : Enable or disable LPCOMP. */ -#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ -#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ - -/* Register: LPCOMP_PSEL */ -/* Description: Input pin select. */ - -/* Bits 2..0 : Analog input pin select. */ -#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ - -/* Register: LPCOMP_REFSEL */ -/* Description: Reference select. */ - -/* Bits 2..0 : Reference select. */ -#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ - -/* Register: LPCOMP_EXTREFSEL */ -/* Description: External reference select. */ - -/* Bit 0 : External analog reference pin selection. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ - -/* Register: LPCOMP_ANADETECT */ -/* Description: Analog detect configuration. */ - -/* Bits 1..0 : Analog detect configuration. */ -#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ -#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ -#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ -#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ -#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ - -/* Register: LPCOMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: MPU */ -/* Description: Memory Protection Unit. */ - -/* Register: MPU_PERR0 */ -/* Description: Configuration of peripherals in mpu regions. */ - -/* Bit 31 : PPI region configuration. */ -#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ -#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ -#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 30 : NVMC region configuration. */ -#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ -#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ -#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 19 : LPCOMP_COMP region configuration. */ -#define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /*!< Position of LPCOMP_COMP field. */ -#define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /*!< Bit mask of LPCOMP_COMP field. */ -#define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 18 : QDEC region configuration. */ -#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ -#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ -#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 17 : RTC1 region configuration. */ -#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ -#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ -#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 16 : WDT region configuration. */ -#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ -#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ -#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 15 : CCM and AAR region configuration. */ -#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ -#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ -#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 14 : ECB region configuration. */ -#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ -#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ -#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 13 : RNG region configuration. */ -#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ -#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ -#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 12 : TEMP region configuration. */ -#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ -#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ -#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 11 : RTC0 region configuration. */ -#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ -#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ -#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 10 : TIMER2 region configuration. */ -#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ -#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ -#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 9 : TIMER1 region configuration. */ -#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ -#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ -#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 8 : TIMER0 region configuration. */ -#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ -#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ -#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 7 : ADC region configuration. */ -#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ -#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ -#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 6 : GPIOTE region configuration. */ -#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ -#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ -#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 4 : SPI1 and TWI1 region configuration. */ -#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ -#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ -#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 3 : SPI0 and TWI0 region configuration. */ -#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ -#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ -#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 2 : UART0 region configuration. */ -#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ -#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ -#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 1 : RADIO region configuration. */ -#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ -#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ -#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 0 : POWER_CLOCK region configuration. */ -#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ -#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ -#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Register: MPU_PROTENSET0 */ -/* Description: Protection bit enable set register for low addresses. */ - -/* Bit 31 : Protection enable for region 31. */ -#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ -#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ -#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 30 : Protection enable for region 30. */ -#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ -#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ -#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 29 : Protection enable for region 29. */ -#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ -#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ -#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 28 : Protection enable for region 28. */ -#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ -#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ -#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 27 : Protection enable for region 27. */ -#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ -#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ -#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 26 : Protection enable for region 26. */ -#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ -#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ -#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 25 : Protection enable for region 25. */ -#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ -#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ -#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 24 : Protection enable for region 24. */ -#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ -#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ -#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 23 : Protection enable for region 23. */ -#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ -#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ -#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 22 : Protection enable for region 22. */ -#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ -#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ -#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 21 : Protection enable for region 21. */ -#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ -#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ -#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 20 : Protection enable for region 20. */ -#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ -#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ -#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 19 : Protection enable for region 19. */ -#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ -#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ -#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 18 : Protection enable for region 18. */ -#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ -#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ -#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 17 : Protection enable for region 17. */ -#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ -#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ -#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 16 : Protection enable for region 16. */ -#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ -#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ -#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 15 : Protection enable for region 15. */ -#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ -#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ -#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 14 : Protection enable for region 14. */ -#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ -#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ -#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 13 : Protection enable for region 13. */ -#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ -#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ -#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 12 : Protection enable for region 12. */ -#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ -#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ -#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 11 : Protection enable for region 11. */ -#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ -#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ -#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 10 : Protection enable for region 10. */ -#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ -#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ -#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 9 : Protection enable for region 9. */ -#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ -#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ -#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 8 : Protection enable for region 8. */ -#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ -#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ -#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 7 : Protection enable for region 7. */ -#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ -#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ -#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 6 : Protection enable for region 6. */ -#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ -#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ -#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 5 : Protection enable for region 5. */ -#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ -#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ -#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 4 : Protection enable for region 4. */ -#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ -#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ -#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 3 : Protection enable for region 3. */ -#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ -#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ -#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 2 : Protection enable for region 2. */ -#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ -#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ -#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 1 : Protection enable for region 1. */ -#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ -#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ -#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 0 : Protection enable for region 0. */ -#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ -#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ -#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ - -/* Register: MPU_PROTENSET1 */ -/* Description: Protection bit enable set register for high addresses. */ - -/* Bit 31 : Protection enable for region 63. */ -#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ -#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ -#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 30 : Protection enable for region 62. */ -#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ -#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ -#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 29 : Protection enable for region 61. */ -#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ -#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ -#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 28 : Protection enable for region 60. */ -#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ -#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ -#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 27 : Protection enable for region 59. */ -#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ -#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ -#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 26 : Protection enable for region 58. */ -#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ -#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ -#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 25 : Protection enable for region 57. */ -#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ -#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ -#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 24 : Protection enable for region 56. */ -#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ -#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ -#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 23 : Protection enable for region 55. */ -#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ -#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ -#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 22 : Protection enable for region 54. */ -#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ -#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ -#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 21 : Protection enable for region 53. */ -#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ -#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ -#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 20 : Protection enable for region 52. */ -#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ -#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ -#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 19 : Protection enable for region 51. */ -#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ -#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ -#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 18 : Protection enable for region 50. */ -#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ -#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ -#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 17 : Protection enable for region 49. */ -#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ -#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ -#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 16 : Protection enable for region 48. */ -#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ -#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ -#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 15 : Protection enable for region 47. */ -#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ -#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ -#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 14 : Protection enable for region 46. */ -#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ -#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ -#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 13 : Protection enable for region 45. */ -#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ -#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ -#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 12 : Protection enable for region 44. */ -#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ -#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ -#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 11 : Protection enable for region 43. */ -#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ -#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ -#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 10 : Protection enable for region 42. */ -#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ -#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ -#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 9 : Protection enable for region 41. */ -#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ -#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ -#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 8 : Protection enable for region 40. */ -#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ -#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ -#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 7 : Protection enable for region 39. */ -#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ -#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ -#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 6 : Protection enable for region 38. */ -#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ -#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ -#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 5 : Protection enable for region 37. */ -#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ -#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ -#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 4 : Protection enable for region 36. */ -#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ -#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ -#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 3 : Protection enable for region 35. */ -#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ -#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ -#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 2 : Protection enable for region 34. */ -#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ -#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ -#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 1 : Protection enable for region 33. */ -#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ -#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ -#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 0 : Protection enable for region 32. */ -#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ -#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ -#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ - -/* Register: MPU_DISABLEINDEBUG */ -/* Description: Disable protection mechanism in debug mode. */ - -/* Bit 0 : Disable protection mechanism in debug mode. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ - -/* Register: MPU_ENRBDREG */ -/* Description: Enable or disable RBD. */ - -/* Bit 0 : Enable or disable RBD. */ -#define MPU_ENRBDREG_ENRBDREG_Pos (0UL) /*!< Position of ENRBDREG field. */ -#define MPU_ENRBDREG_ENRBDREG_Msk (0x1UL << MPU_ENRBDREG_ENRBDREG_Pos) /*!< Bit mask of ENRBDREG field. */ -#define MPU_ENRBDREG_ENRBDREG_Disabled (0x0UL) /*!< RBD disabled. */ -#define MPU_ENRBDREG_ENRBDREG_Enabled (0x1UL) /*!< RBD enabled. */ - - -/* Peripheral: NVMC */ -/* Description: Non Volatile Memory Controller. */ - -/* Register: NVMC_READY */ -/* Description: Ready flag. */ - -/* Bit 0 : NVMC ready. */ -#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ -#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ -#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ -#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ - -/* Register: NVMC_CONFIG */ -/* Description: Configuration register. */ - -/* Bits 1..0 : Program write enable. */ -#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ -#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ -#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ -#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ -#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ - -/* Register: NVMC_ERASEALL */ -/* Description: Register for erasing all non-volatile user memory. */ - -/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ -#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ -#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ - -/* Register: NVMC_ERASEUICR */ -/* Description: Register for start erasing User Information Congfiguration Registers. */ - -/* Bit 0 : It can only be used when all contents of code region 1 are erased. */ -#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ -#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ -#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ -#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ - - -/* Peripheral: POWER */ -/* Description: Power Control. */ - -/* Register: POWER_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on POFWARN event. */ -#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ -#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ -#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: POWER_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on POFWARN event. */ -#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ -#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ -#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: POWER_RESETREAS */ -/* Description: Reset reason. */ - -/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ -#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ -#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ - -/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ -#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ -#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ - -/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ -#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ -#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ - -/* Bit 3 : Reset from CPU lock-up detected. */ -#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ -#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ - -/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ -#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ -#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ - -/* Bit 1 : Reset from watchdog detected. */ -#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ -#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ - -/* Bit 0 : Reset from pin-reset detected. */ -#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ -#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ - -/* Register: POWER_RAMSTATUS */ -/* Description: Ram status register. */ - -/* Bit 3 : RAM block 3 status. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ - -/* Bit 2 : RAM block 2 status. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ - -/* Bit 1 : RAM block 1 status. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ - -/* Bit 0 : RAM block 0 status. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ - -/* Register: POWER_SYSTEMOFF */ -/* Description: System off register. */ - -/* Bit 0 : Enter system off mode. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ - -/* Register: POWER_POFCON */ -/* Description: Power failure configuration. */ - -/* Bits 2..1 : Set threshold level. */ -#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ -#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ -#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ -#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ -#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ -#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ - -/* Bit 0 : Power failure comparator enable. */ -#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ -#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ -#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ -#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ - -/* Register: POWER_GPREGRET */ -/* Description: General purpose retention register. This register is a retained register. */ - -/* Bits 7..0 : General purpose retention register. */ -#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ -#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ - -/* Register: POWER_RAMON */ -/* Description: Ram on/off. */ - -/* Bit 19 : RAM block 3 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM3_Pos (19UL) /*!< Position of OFFRAM3 field. */ -#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ -#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ - -/* Bit 18 : RAM block 2 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM2_Pos (18UL) /*!< Position of OFFRAM2 field. */ -#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ -#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ - -/* Bit 17 : RAM block 1 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ -#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ -#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ - -/* Bit 16 : RAM block 0 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ -#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ -#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ - -/* Bit 3 : RAM block 3 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM3_Pos (3UL) /*!< Position of ONRAM3 field. */ -#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ -#define POWER_RAMON_ONRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in ON mode. */ -#define POWER_RAMON_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ - -/* Bit 2 : RAM block 2 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM2_Pos (2UL) /*!< Position of ONRAM2 field. */ -#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ -#define POWER_RAMON_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ -#define POWER_RAMON_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ - -/* Bit 1 : RAM block 1 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ -#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ -#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ -#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ - -/* Bit 0 : RAM block 0 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ -#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ -#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ -#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ - -/* Register: POWER_RESET */ -/* Description: Pin reset functionality configuration register. This register is a retained register. */ - -/* Bit 0 : Enable pin reset in debug interface mode. */ -#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ -#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ -#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ -#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ - -/* Register: POWER_DCDCEN */ -/* Description: DCDC converter enable configuration register. */ - -/* Bit 0 : Enable DCDC converter. */ -#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ -#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ -#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ -#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ - -/* Register: POWER_DCDCFORCE */ -/* Description: DCDC power-up force register. */ - -/* Bit 1 : DCDC power-up force on. */ -#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ -#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ -#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ -#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ - -/* Bit 0 : DCDC power-up force off. */ -#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ -#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ -#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ -#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ - - -/* Peripheral: PPI */ -/* Description: PPI controller. */ - -/* Register: PPI_CHEN */ -/* Description: Channel enable. */ - -/* Bit 31 : Enable PPI channel 31. */ -#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 30 : Enable PPI channel 30. */ -#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 29 : Enable PPI channel 29. */ -#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 28 : Enable PPI channel 28. */ -#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 27 : Enable PPI channel 27. */ -#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 26 : Enable PPI channel 26. */ -#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 25 : Enable PPI channel 25. */ -#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 24 : Enable PPI channel 24. */ -#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 23 : Enable PPI channel 23. */ -#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 22 : Enable PPI channel 22. */ -#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 21 : Enable PPI channel 21. */ -#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 20 : Enable PPI channel 20. */ -#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 15 : Enable PPI channel 15. */ -#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 14 : Enable PPI channel 14. */ -#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 13 : Enable PPI channel 13. */ -#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 12 : Enable PPI channel 12. */ -#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 11 : Enable PPI channel 11. */ -#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 10 : Enable PPI channel 10. */ -#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 9 : Enable PPI channel 9. */ -#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 8 : Enable PPI channel 8. */ -#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 7 : Enable PPI channel 7. */ -#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 6 : Enable PPI channel 6. */ -#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 5 : Enable PPI channel 5. */ -#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 4 : Enable PPI channel 4. */ -#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 3 : Enable PPI channel 3. */ -#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ -#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ - -/* Bit 2 : Enable PPI channel 2. */ -#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 1 : Enable PPI channel 1. */ -#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 0 : Enable PPI channel 0. */ -#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ - -/* Register: PPI_CHENSET */ -/* Description: Channel enable set. */ - -/* Bit 31 : Enable PPI channel 31. */ -#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 30 : Enable PPI channel 30. */ -#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 29 : Enable PPI channel 29. */ -#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 28 : Enable PPI channel 28. */ -#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 27 : Enable PPI channel 27. */ -#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 26 : Enable PPI channel 26. */ -#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 25 : Enable PPI channel 25. */ -#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 24 : Enable PPI channel 24. */ -#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 23 : Enable PPI channel 23. */ -#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 22 : Enable PPI channel 22. */ -#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 21 : Enable PPI channel 21. */ -#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 20 : Enable PPI channel 20. */ -#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 15 : Enable PPI channel 15. */ -#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 14 : Enable PPI channel 14. */ -#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 13 : Enable PPI channel 13. */ -#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 12 : Enable PPI channel 12. */ -#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 11 : Enable PPI channel 11. */ -#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 10 : Enable PPI channel 10. */ -#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 9 : Enable PPI channel 9. */ -#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 8 : Enable PPI channel 8. */ -#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 7 : Enable PPI channel 7. */ -#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 6 : Enable PPI channel 6. */ -#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 5 : Enable PPI channel 5. */ -#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 4 : Enable PPI channel 4. */ -#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 3 : Enable PPI channel 3. */ -#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 2 : Enable PPI channel 2. */ -#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 1 : Enable PPI channel 1. */ -#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 0 : Enable PPI channel 0. */ -#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ - -/* Register: PPI_CHENCLR */ -/* Description: Channel enable clear. */ - -/* Bit 31 : Disable PPI channel 31. */ -#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 30 : Disable PPI channel 30. */ -#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 29 : Disable PPI channel 29. */ -#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 28 : Disable PPI channel 28. */ -#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 27 : Disable PPI channel 27. */ -#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 26 : Disable PPI channel 26. */ -#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 25 : Disable PPI channel 25. */ -#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 24 : Disable PPI channel 24. */ -#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 23 : Disable PPI channel 23. */ -#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 22 : Disable PPI channel 22. */ -#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 21 : Disable PPI channel 21. */ -#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 20 : Disable PPI channel 20. */ -#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 15 : Disable PPI channel 15. */ -#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 14 : Disable PPI channel 14. */ -#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 13 : Disable PPI channel 13. */ -#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 12 : Disable PPI channel 12. */ -#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 11 : Disable PPI channel 11. */ -#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 10 : Disable PPI channel 10. */ -#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 9 : Disable PPI channel 9. */ -#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 8 : Disable PPI channel 8. */ -#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 7 : Disable PPI channel 7. */ -#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 6 : Disable PPI channel 6. */ -#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 5 : Disable PPI channel 5. */ -#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 4 : Disable PPI channel 4. */ -#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 3 : Disable PPI channel 3. */ -#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 2 : Disable PPI channel 2. */ -#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 1 : Disable PPI channel 1. */ -#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 0 : Disable PPI channel 0. */ -#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ - -/* Register: PPI_CHG */ -/* Description: Channel group configuration. */ - -/* Bit 31 : Include CH31 in channel group. */ -#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ - -/* Bit 30 : Include CH30 in channel group. */ -#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ - -/* Bit 29 : Include CH29 in channel group. */ -#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ - -/* Bit 28 : Include CH28 in channel group. */ -#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ - -/* Bit 27 : Include CH27 in channel group. */ -#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ - -/* Bit 26 : Include CH26 in channel group. */ -#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ - -/* Bit 25 : Include CH25 in channel group. */ -#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ - -/* Bit 24 : Include CH24 in channel group. */ -#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ - -/* Bit 23 : Include CH23 in channel group. */ -#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ - -/* Bit 22 : Include CH22 in channel group. */ -#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ - -/* Bit 21 : Include CH21 in channel group. */ -#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ - -/* Bit 20 : Include CH20 in channel group. */ -#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ - -/* Bit 15 : Include CH15 in channel group. */ -#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ - -/* Bit 14 : Include CH14 in channel group. */ -#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ - -/* Bit 13 : Include CH13 in channel group. */ -#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ - -/* Bit 12 : Include CH12 in channel group. */ -#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ - -/* Bit 11 : Include CH11 in channel group. */ -#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ - -/* Bit 10 : Include CH10 in channel group. */ -#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ - -/* Bit 9 : Include CH9 in channel group. */ -#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ - -/* Bit 8 : Include CH8 in channel group. */ -#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ - -/* Bit 7 : Include CH7 in channel group. */ -#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ - -/* Bit 6 : Include CH6 in channel group. */ -#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ - -/* Bit 5 : Include CH5 in channel group. */ -#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ - -/* Bit 4 : Include CH4 in channel group. */ -#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ - -/* Bit 3 : Include CH3 in channel group. */ -#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ - -/* Bit 2 : Include CH2 in channel group. */ -#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ - -/* Bit 1 : Include CH1 in channel group. */ -#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ - -/* Bit 0 : Include CH0 in channel group. */ -#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ - - -/* Peripheral: PU */ -/* Description: Patch unit. */ - -/* Register: PU_PATCHADDR */ -/* Description: Relative address of patch instructions. */ - -/* Bits 24..0 : Relative address of patch instructions. */ -#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */ -#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */ - -/* Register: PU_PATCHEN */ -/* Description: Patch enable register. */ - -/* Bit 7 : Patch 7 enabled. */ -#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ -#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ -#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 6 : Patch 6 enabled. */ -#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ -#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ -#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 5 : Patch 5 enabled. */ -#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ -#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ -#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 4 : Patch 4 enabled. */ -#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ -#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ -#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 3 : Patch 3 enabled. */ -#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ -#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ -#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 2 : Patch 2 enabled. */ -#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ -#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ -#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 1 : Patch 1 enabled. */ -#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ -#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ -#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 0 : Patch 0 enabled. */ -#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ -#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ -#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */ - -/* Register: PU_PATCHENSET */ -/* Description: Patch enable register. */ - -/* Bit 7 : Patch 7 enabled. */ -#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ -#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ -#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 6 : Patch 6 enabled. */ -#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ -#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ -#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 5 : Patch 5 enabled. */ -#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ -#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ -#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 4 : Patch 4 enabled. */ -#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ -#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ -#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 3 : Patch 3 enabled. */ -#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ -#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ -#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 2 : Patch 2 enabled. */ -#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ -#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ -#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 1 : Patch 1 enabled. */ -#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ -#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ -#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 0 : Patch 0 enabled. */ -#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ -#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ -#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */ - -/* Register: PU_PATCHENCLR */ -/* Description: Patch disable register. */ - -/* Bit 7 : Patch 7 enabled. */ -#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ -#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ -#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 6 : Patch 6 enabled. */ -#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ -#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ -#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 5 : Patch 5 enabled. */ -#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ -#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ -#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 4 : Patch 4 enabled. */ -#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ -#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ -#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 3 : Patch 3 enabled. */ -#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ -#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ -#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 2 : Patch 2 enabled. */ -#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ -#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ -#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 1 : Patch 1 enabled. */ -#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ -#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ -#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 0 : Patch 0 enabled. */ -#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ -#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ -#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */ - - -/* Peripheral: QDEC */ -/* Description: Rotary decoder. */ - -/* Register: QDEC_SHORTS */ -/* Description: Shortcut for the QDEC. */ - -/* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: QDEC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on ACCOF event. */ -#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ -#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ -#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on REPORTRDY event. */ -#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ -#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ -#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on SAMPLERDY event. */ -#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ -#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ -#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: QDEC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on ACCOF event. */ -#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ -#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ -#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on REPORTRDY event. */ -#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ -#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ -#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on SAMPLERDY event. */ -#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ -#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ -#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: QDEC_ENABLE */ -/* Description: Enable the QDEC. */ - -/* Bit 0 : Enable or disable QDEC. */ -#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ -#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ - -/* Register: QDEC_LEDPOL */ -/* Description: LED output pin polarity. */ - -/* Bit 0 : LED output pin polarity. */ -#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ -#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ -#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ -#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ - -/* Register: QDEC_SAMPLEPER */ -/* Description: Sample period. */ - -/* Bits 2..0 : Sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ -#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ -#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ - -/* Register: QDEC_SAMPLE */ -/* Description: Motion sample value. */ - -/* Bits 31..0 : Last sample taken in compliment to 2. */ -#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ -#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ - -/* Register: QDEC_REPORTPER */ -/* Description: Number of samples to generate an EVENT_REPORTRDY. */ - -/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ -#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ - -/* Register: QDEC_DBFEN */ -/* Description: Enable debouncer input filters. */ - -/* Bit 0 : Enable debounce input filters. */ -#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ -#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ -#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ -#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ - -/* Register: QDEC_LEDPRE */ -/* Description: Time LED is switched ON before the sample. */ - -/* Bits 7..0 : Period in us the LED in switched on prior to sampling. */ -#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ -#define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ - -/* Register: QDEC_ACCDBL */ -/* Description: Accumulated double (error) transitions register. */ - -/* Bits 3..0 : Accumulated double (error) transitions. */ -#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ -#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ - -/* Register: QDEC_ACCDBLREAD */ -/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ - -/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ -#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ -#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ - -/* Register: QDEC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RADIO */ -/* Description: The radio. */ - -/* Register: RADIO_SHORTS */ -/* Description: Shortcut for the radio. */ - -/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 5 : Shortcut between END event and START task. */ -#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ -#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ -#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between DISABLED event and RXEN task. */ -#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ -#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ -#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Shortcut between DISABLED event and TXEN task. */ -#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ -#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ -#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Shortcut between END event and DISABLE task. */ -#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ -#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ -#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between READY event and START task. */ -#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ -#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ -#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: RADIO_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 10 : Enable interrupt on BCMATCH event. */ -#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ -#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ -#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on RSSIEND event. */ -#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ -#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ -#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 6 : Enable interrupt on DEVMISS event. */ -#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ -#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ -#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 5 : Enable interrupt on DEVMATCH event. */ -#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ -#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ -#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 4 : Enable interrupt on DISABLED event. */ -#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ -#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ -#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on END event. */ -#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ -#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on PAYLOAD event. */ -#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ -#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ -#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on ADDRESS event. */ -#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ -#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ -#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RADIO_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 10 : Disable interrupt on BCMATCH event. */ -#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ -#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ -#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on RSSIEND event. */ -#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ -#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ -#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 6 : Disable interrupt on DEVMISS event. */ -#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ -#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ -#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 5 : Disable interrupt on DEVMATCH event. */ -#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ -#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ -#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 4 : Disable interrupt on DISABLED event. */ -#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ -#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ -#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on END event. */ -#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ -#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on PAYLOAD event. */ -#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ -#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ -#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on ADDRESS event. */ -#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ -#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ -#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RADIO_CRCSTATUS */ -/* Description: CRC status of received packet. */ - -/* Bit 0 : CRC status of received packet. */ -#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ -#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ -#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ -#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ - -/* Register: RADIO_RXMATCH */ -/* Description: Received address. */ - -/* Bits 2..0 : Logical address in which previous packet was received. */ -#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ -#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ - -/* Register: RADIO_RXCRC */ -/* Description: Received CRC. */ - -/* Bits 23..0 : CRC field of previously received packet. */ -#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ -#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ - -/* Register: RADIO_DAI */ -/* Description: Device address match index. */ - -/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */ -#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ -#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ - -/* Register: RADIO_FREQUENCY */ -/* Description: Frequency. */ - -/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ -#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ - -/* Register: RADIO_TXPOWER */ -/* Description: Output power. */ - -/* Bits 7..0 : Radio output power. Decision point: TXEN task. */ -#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ -#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ - -/* Register: RADIO_MODE */ -/* Description: Data rate and modulation. */ - -/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ -#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ - -/* Register: RADIO_PCNF0 */ -/* Description: Packet configuration 0. */ - -/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ -#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ -#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ - -/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ -#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ -#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ - -/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ -#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ -#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ - -/* Register: RADIO_PCNF1 */ -/* Description: Packet configuration 1. */ - -/* Bit 25 : Packet whitening enable. */ -#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ -#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ -#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ -#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ - -/* Bit 24 : On air endianness of packet length field. Decision point: START task. */ -#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ -#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ - -/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ -#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ -#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ - -/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ -#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ -#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ - -/* Bits 7..0 : Maximum length of packet payload in number of bytes. */ -#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ -#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ - -/* Register: RADIO_PREFIX0 */ -/* Description: Prefixes bytes for logical addresses 0 to 3. */ - -/* Bits 31..24 : Address prefix 3. Decision point: START task. */ -#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ -#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ - -/* Bits 23..16 : Address prefix 2. Decision point: START task. */ -#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ -#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ - -/* Bits 15..8 : Address prefix 1. Decision point: START task. */ -#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ -#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ - -/* Bits 7..0 : Address prefix 0. Decision point: START task. */ -#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ -#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ - -/* Register: RADIO_PREFIX1 */ -/* Description: Prefixes bytes for logical addresses 4 to 7. */ - -/* Bits 31..24 : Address prefix 7. Decision point: START task. */ -#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ -#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ - -/* Bits 23..16 : Address prefix 6. Decision point: START task. */ -#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ -#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ - -/* Bits 15..8 : Address prefix 5. Decision point: START task. */ -#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ -#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ - -/* Bits 7..0 : Address prefix 4. Decision point: START task. */ -#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ -#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ - -/* Register: RADIO_TXADDRESS */ -/* Description: Transmit address select. */ - -/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ -#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ -#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ - -/* Register: RADIO_RXADDRESSES */ -/* Description: Receive address select. */ - -/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ -#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ -#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ -#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ -#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ -#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ -#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ -#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ -#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ -#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ -#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ -#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ -#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ -#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ -#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ -#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ -#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ - -/* Register: RADIO_CRCCNF */ -/* Description: CRC configuration. */ - -/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /*!< Position of SKIP_ADDR field. */ -#define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /*!< Bit mask of SKIP_ADDR field. */ -#define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ -#define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ - -/* Bits 1..0 : CRC length. Decision point: START task. */ -#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ -#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ -#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ -#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ -#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ -#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ - -/* Register: RADIO_CRCPOLY */ -/* Description: CRC polynomial. */ - -/* Bits 23..1 : CRC polynomial. Decision point: START task. */ -#define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /*!< Position of CRCPOLY field. */ -#define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ - -/* Register: RADIO_CRCINIT */ -/* Description: CRC initial value. */ - -/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ -#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ -#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ - -/* Register: RADIO_TEST */ -/* Description: Test features enable register. */ - -/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ -#define RADIO_TEST_PLL_LOCK_Pos (1UL) /*!< Position of PLL_LOCK field. */ -#define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /*!< Bit mask of PLL_LOCK field. */ -#define RADIO_TEST_PLL_LOCK_Disabled (0UL) /*!< PLL lock disabled. */ -#define RADIO_TEST_PLL_LOCK_Enabled (1UL) /*!< PLL lock enabled. */ - -/* Bit 0 : Constant carrier. Decision point: TXEN task. */ -#define RADIO_TEST_CONST_CARRIER_Pos (0UL) /*!< Position of CONST_CARRIER field. */ -#define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /*!< Bit mask of CONST_CARRIER field. */ -#define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ -#define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ - -/* Register: RADIO_TIFS */ -/* Description: Inter Frame Spacing in microseconds. */ - -/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ -#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ -#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ - -/* Register: RADIO_RSSISAMPLE */ -/* Description: RSSI sample. */ - -/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ -#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ -#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ - -/* Register: RADIO_STATE */ -/* Description: Current radio state. */ - -/* Bits 3..0 : Current radio state. */ -#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ -#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ -#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ -#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ -#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ -#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ -#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ -#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ -#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ -#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ -#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ - -/* Register: RADIO_DATAWHITEIV */ -/* Description: Data whitening initial value. */ - -/* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ - -/* Register: RADIO_DAP */ -/* Description: Device address prefix. */ - -/* Bits 15..0 : Device address prefix. */ -#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ -#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ - -/* Register: RADIO_DACNF */ -/* Description: Device address match configuration. */ - -/* Bit 15 : TxAdd for device address 7. */ -#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ -#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ - -/* Bit 14 : TxAdd for device address 6. */ -#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ -#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ - -/* Bit 13 : TxAdd for device address 5. */ -#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ -#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ - -/* Bit 12 : TxAdd for device address 4. */ -#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ -#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ - -/* Bit 11 : TxAdd for device address 3. */ -#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ -#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ - -/* Bit 10 : TxAdd for device address 2. */ -#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ -#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ - -/* Bit 9 : TxAdd for device address 1. */ -#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ -#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ - -/* Bit 8 : TxAdd for device address 0. */ -#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ -#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ - -/* Bit 7 : Enable or disable device address matching using device address 7. */ -#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ -#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ -#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ - -/* Bit 6 : Enable or disable device address matching using device address 6. */ -#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ -#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ -#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ - -/* Bit 5 : Enable or disable device address matching using device address 5. */ -#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ -#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ -#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ - -/* Bit 4 : Enable or disable device address matching using device address 4. */ -#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ -#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ -#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ - -/* Bit 3 : Enable or disable device address matching using device address 3. */ -#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ -#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ -#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ - -/* Bit 2 : Enable or disable device address matching using device address 2. */ -#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ -#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ -#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ - -/* Bit 1 : Enable or disable device address matching using device address 1. */ -#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ -#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ -#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ - -/* Bit 0 : Enable or disable device address matching using device address 0. */ -#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ -#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ -#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ - -/* Register: RADIO_OVERRIDE0 */ -/* Description: Trim value override register 0. */ - -/* Bits 31..0 : Trim value override register 0. */ -#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ -#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ - -/* Register: RADIO_OVERRIDE1 */ -/* Description: Trim value override register 1. */ - -/* Bits 31..0 : Trim value override register 1. */ -#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ -#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ - -/* Register: RADIO_OVERRIDE2 */ -/* Description: Trim value override register 2. */ - -/* Bits 31..0 : Trim value override register 2. */ -#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ -#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ - -/* Register: RADIO_OVERRIDE3 */ -/* Description: Trim value override register 3. */ - -/* Bits 31..0 : Trim value override register 3. */ -#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ -#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ - -/* Register: RADIO_OVERRIDE4 */ -/* Description: Trim value override register 4. */ - -/* Bit 31 : Enable or disable override of default trim values. */ -#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ -#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ -#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ - -/* Bits 27..0 : Trim value override register 4. */ -#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ -#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ - -/* Register: RADIO_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RNG */ -/* Description: Random Number Generator. */ - -/* Register: RNG_SHORTS */ -/* Description: Shortcut for the RNG. */ - -/* Bit 0 : Short-cut between VALRDY event and STOP task. */ -#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ -#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ -#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: RNG_INTENSET */ -/* Description: Interrupt enable set register */ - -/* Bit 0 : Enable interrupt on VALRDY event. */ -#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ -#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ -#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RNG_INTENCLR */ -/* Description: Interrupt enable clear register */ - -/* Bit 0 : Disable interrupt on VALRDY event. */ -#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ -#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ -#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RNG_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 0 : Digital error correction enable. */ -#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ -#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ -#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ -#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ - -/* Register: RNG_VALUE */ -/* Description: RNG random number. */ - -/* Bits 7..0 : Generated random number. */ -#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ -#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ - -/* Register: RNG_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RTC */ -/* Description: Real time counter 0. */ - -/* Register: RTC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 19 : Enable interrupt on COMPARE[3] event. */ -#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 18 : Enable interrupt on COMPARE[2] event. */ -#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 17 : Enable interrupt on COMPARE[1] event. */ -#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 16 : Enable interrupt on COMPARE[0] event. */ -#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on OVRFLW event. */ -#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on TICK event. */ -#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RTC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 19 : Disable interrupt on COMPARE[3] event. */ -#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 18 : Disable interrupt on COMPARE[2] event. */ -#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 17 : Disable interrupt on COMPARE[1] event. */ -#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 16 : Disable interrupt on COMPARE[0] event. */ -#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on OVRFLW event. */ -#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on TICK event. */ -#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RTC_EVTEN */ -/* Description: Configures event enable routing to PPI for each RTC event. */ - -/* Bit 19 : COMPARE[3] event enable. */ -#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 18 : COMPARE[2] event enable. */ -#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 17 : COMPARE[1] event enable. */ -#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 16 : COMPARE[0] event enable. */ -#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 1 : OVRFLW event enable. */ -#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 0 : TICK event enable. */ -#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ - -/* Register: RTC_EVTENSET */ -/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ - -/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ -#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ - -/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ -#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ - -/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ -#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ - -/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ -#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ - -/* Bit 1 : Enable routing to PPI of OVRFLW event. */ -#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ - -/* Bit 0 : Enable routing to PPI of TICK event. */ -#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ - -/* Register: RTC_EVTENCLR */ -/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ - -/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ -#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ -#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ -#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ -#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 1 : Disable routing to PPI of OVRFLW event. */ -#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 0 : Disable routing to PPI of TICK event. */ -#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ - -/* Register: RTC_COUNTER */ -/* Description: Current COUNTER value. */ - -/* Bits 23..0 : Counter value. */ -#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ -#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ - -/* Register: RTC_PRESCALER */ -/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ - -/* Bits 11..0 : RTC PRESCALER value. */ -#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ - -/* Register: RTC_CC */ -/* Description: Capture/compare registers. */ - -/* Bits 23..0 : Compare value. */ -#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ -#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ - -/* Register: RTC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: SPI */ -/* Description: SPI master 0. */ - -/* Register: SPI_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on READY event. */ -#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ -#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: SPI_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on READY event. */ -#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ -#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: SPI_ENABLE */ -/* Description: Enable SPI. */ - -/* Bits 2..0 : Enable or disable SPI. */ -#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ -#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ - -/* Register: SPI_RXD */ -/* Description: RX data. */ - -/* Bits 7..0 : RX data from last transfer. */ -#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: SPI_TXD */ -/* Description: TX data. */ - -/* Bits 7..0 : TX data for next transfer. */ -#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: SPI_FREQUENCY */ -/* Description: SPI frequency */ - -/* Bits 31..0 : SPI data rate. */ -#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ -#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ -#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ -#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ - -/* Register: SPI_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 2 : Serial clock (SCK) polarity. */ -#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ -#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ - -/* Bit 1 : Serial clock (SCK) phase. */ -#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ -#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ - -/* Bit 0 : Bit order. */ -#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ -#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ - -/* Register: SPI_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: SPIS */ -/* Description: SPI slave 1. */ - -/* Register: SPIS_SHORTS */ -/* Description: Shortcuts for SPIS. */ - -/* Bit 2 : Shortcut between END event and the ACQUIRE task. */ -#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ -#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: SPIS_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 10 : Enable interrupt on ACQUIRED event. */ -#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on END event. */ -#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ -#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: SPIS_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 10 : Disable interrupt on ACQUIRED event. */ -#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on END event. */ -#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ -#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: SPIS_SEMSTAT */ -/* Description: Semaphore status. */ - -/* Bits 1..0 : Semaphore status. */ -#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ -#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ -#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ -#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ - -/* Register: SPIS_STATUS */ -/* Description: Status from last transaction. */ - -/* Bit 1 : RX buffer overflow detected, and prevented. */ -#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ -#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ -#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ - -/* Bit 0 : TX buffer overread detected, and prevented. */ -#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ -#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ -#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ - -/* Register: SPIS_ENABLE */ -/* Description: Enable SPIS. */ - -/* Bits 2..0 : Enable or disable SPIS. */ -#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ -#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ - -/* Register: SPIS_MAXRX */ -/* Description: Maximum number of bytes in the receive buffer. */ - -/* Bits 7..0 : Maximum number of bytes in the receive buffer. */ -#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ -#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ - -/* Register: SPIS_AMOUNTRX */ -/* Description: Number of bytes received in last granted transaction. */ - -/* Bits 7..0 : Number of bytes received in last granted transaction. */ -#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ -#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ - -/* Register: SPIS_MAXTX */ -/* Description: Maximum number of bytes in the transmit buffer. */ - -/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ -#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ -#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ - -/* Register: SPIS_AMOUNTTX */ -/* Description: Number of bytes transmitted in last granted transaction. */ - -/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ -#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ -#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ - -/* Register: SPIS_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 2 : Serial clock (SCK) polarity. */ -#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ -#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ - -/* Bit 1 : Serial clock (SCK) phase. */ -#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ -#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ - -/* Bit 0 : Bit order. */ -#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ -#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ - -/* Register: SPIS_DEF */ -/* Description: Default character. */ - -/* Bits 7..0 : Default character. */ -#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ -#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ - -/* Register: SPIS_ORC */ -/* Description: Over-read character. */ - -/* Bits 7..0 : Over-read character. */ -#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ -#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ - -/* Register: SPIS_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TEMP */ -/* Description: Temperature Sensor. */ - -/* Register: TEMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on DATARDY event. */ -#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ -#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ -#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TEMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on DATARDY event. */ -#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ -#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ -#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TEMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TIMER */ -/* Description: Timer 0. */ - -/* Register: TIMER_SHORTS */ -/* Description: Shortcuts for Timer. */ - -/* Bit 11 : Shortcut between CC[3] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 10 : Shortcut between CC[2] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 9 : Shortcut between CC[1] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 8 : Shortcut between CC[0] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: TIMER_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 19 : Enable interrupt on COMPARE[3] */ -#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 18 : Enable interrupt on COMPARE[2] */ -#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 17 : Enable interrupt on COMPARE[1] */ -#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 16 : Enable interrupt on COMPARE[0] */ -#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TIMER_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 19 : Disable interrupt on COMPARE[3] */ -#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 18 : Disable interrupt on COMPARE[2] */ -#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 17 : Disable interrupt on COMPARE[1] */ -#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 16 : Disable interrupt on COMPARE[0] */ -#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TIMER_MODE */ -/* Description: Timer Mode selection. */ - -/* Bit 0 : Select Normal or Counter mode. */ -#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ -#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ - -/* Register: TIMER_BITMODE */ -/* Description: Sets timer behaviour. */ - -/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ -#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ - -/* Register: TIMER_PRESCALER */ -/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ - -/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ -#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ - -/* Register: TIMER_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TWI */ -/* Description: Two-wire interface master 0. */ - -/* Register: TWI_SHORTS */ -/* Description: Shortcuts for TWI. */ - -/* Bit 1 : Shortcut between BB event and the STOP task. */ -#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ -#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ -#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between BB event and the SUSPEND task. */ -#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ -#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ -#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ -#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: TWI_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 18 : Enable interrupt on SUSPENDED event. */ -#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 14 : Enable interrupt on BB event. */ -#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ -#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ -#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 9 : Enable interrupt on ERROR event. */ -#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on TXDSENT event. */ -#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ -#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ -#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on READY event. */ -#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ -#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ -#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on STOPPED event. */ -#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TWI_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 18 : Disable interrupt on SUSPENDED event. */ -#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 14 : Disable interrupt on BB event. */ -#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ -#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ -#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 9 : Disable interrupt on ERROR event. */ -#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on TXDSENT event. */ -#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ -#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ -#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on RXDREADY event. */ -#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ -#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ -#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on STOPPED event. */ -#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TWI_ERRORSRC */ -/* Description: Two-wire error source. Write error field to 1 to clear error. */ - -/* Bit 2 : NACK received after sending a data byte. */ -#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ -#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ -#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ -#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ -#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 1 : NACK received after sending the address. */ -#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ -#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ -#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ -#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ -#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ - -/* Register: TWI_ENABLE */ -/* Description: Enable two-wire master. */ - -/* Bits 2..0 : Enable or disable W2M */ -#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ -#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ - -/* Register: TWI_RXD */ -/* Description: RX data register. */ - -/* Bits 7..0 : RX data from last transfer. */ -#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: TWI_TXD */ -/* Description: TX data register. */ - -/* Bits 7..0 : TX data for next transfer. */ -#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: TWI_FREQUENCY */ -/* Description: Two-wire frequency. */ - -/* Bits 31..0 : Two-wire master clock frequency. */ -#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ -#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ -#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ - -/* Register: TWI_ADDRESS */ -/* Description: Address used in the two-wire transfer. */ - -/* Bits 6..0 : Two-wire address. */ -#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ -#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ - -/* Register: TWI_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: UART */ -/* Description: Universal Asynchronous Receiver/Transmitter. */ - -/* Register: UART_SHORTS */ -/* Description: Shortcuts for TWI. */ - -/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ -#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ -#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between CTS event and the STARTRX task. */ -#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ -#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: UART_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 17 : Enable interrupt on RXTO event. */ -#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 9 : Enable interrupt on ERROR event. */ -#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on TXRDY event. */ -#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on RXRDY event. */ -#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on NCTS event. */ -#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on CTS event. */ -#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: UART_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 17 : Disable interrupt on RXTO event. */ -#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 9 : Disable interrupt on ERROR event. */ -#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on TXRDY event. */ -#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on RXRDY event. */ -#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on NCTS event. */ -#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on CTS event. */ -#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: UART_ERRORSRC */ -/* Description: Error source. Write error field to 1 to clear error. */ - -/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ -#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ -#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ -#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ -#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ -#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ -#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ -#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ -#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ - -/* Register: UART_ENABLE */ -/* Description: Enable UART and acquire IOs. */ - -/* Bits 2..0 : Enable or disable UART and acquire IOs. */ -#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ -#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ - -/* Register: UART_RXD */ -/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */ - -/* Bits 7..0 : RX data from previous transfer. Double buffered. */ -#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: UART_TXD */ -/* Description: TXD register. */ - -/* Bits 7..0 : TX data for transfer. */ -#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: UART_BAUDRATE */ -/* Description: UART Baudrate. */ - -/* Bits 31..0 : UART baudrate. */ -#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ -#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ -#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ - -/* Register: UART_CONFIG */ -/* Description: Configuration of parity and hardware flow control register. */ - -/* Bits 3..1 : Include parity bit. */ -#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ -#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ - -/* Bit 0 : Hardware flow control. */ -#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ -#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ -#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ -#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ - -/* Register: UART_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: UICR */ -/* Description: User Information Configuration. */ - -/* Register: UICR_RBPCONF */ -/* Description: Readback protection configuration. */ - -/* Bits 15..8 : Readback protect all code in the device. */ -#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ -#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ -#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ -#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ - -/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ -#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ -#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ -#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ -#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ - -/* Register: UICR_XTALFREQ */ -/* Description: Reset value for CLOCK XTALFREQ register. */ - -/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ -#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ -#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ -#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ - -/* Register: UICR_FWID */ -/* Description: Firmware ID. */ - -/* Bits 15..0 : Identification number for the firmware loaded into the chip. */ -#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ -#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ - - -/* Peripheral: WDT */ -/* Description: Watchdog Timer. */ - -/* Register: WDT_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on TIMEOUT event. */ -#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ -#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ -#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: WDT_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on TIMEOUT event. */ -#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ -#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ -#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: WDT_RUNSTATUS */ -/* Description: Watchdog running status. */ - -/* Bit 0 : Watchdog running status. */ -#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ -#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ -#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ -#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ - -/* Register: WDT_REQSTATUS */ -/* Description: Request status. */ - -/* Bit 7 : Request status for RR[7]. */ -#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ -#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ - -/* Bit 6 : Request status for RR[6]. */ -#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ -#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ - -/* Bit 5 : Request status for RR[5]. */ -#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ -#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ - -/* Bit 4 : Request status for RR[4]. */ -#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ -#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ - -/* Bit 3 : Request status for RR[3]. */ -#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ -#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ - -/* Bit 2 : Request status for RR[2]. */ -#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ -#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ - -/* Bit 1 : Request status for RR[1]. */ -#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ -#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ - -/* Bit 0 : Request status for RR[0]. */ -#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ -#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ - -/* Register: WDT_RREN */ -/* Description: Reload request enable. */ - -/* Bit 7 : Enable or disable RR[7] register. */ -#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ -#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ -#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ - -/* Bit 6 : Enable or disable RR[6] register. */ -#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ -#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ -#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ - -/* Bit 5 : Enable or disable RR[5] register. */ -#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ -#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ -#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ - -/* Bit 4 : Enable or disable RR[4] register. */ -#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ -#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ -#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ - -/* Bit 3 : Enable or disable RR[3] register. */ -#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ -#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ -#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ - -/* Bit 2 : Enable or disable RR[2] register. */ -#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ -#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ -#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ - -/* Bit 1 : Enable or disable RR[1] register. */ -#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ -#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ -#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ - -/* Bit 0 : Enable or disable RR[0] register. */ -#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ -#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ -#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ - -/* Register: WDT_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ -#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ -#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ -#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ -#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ - -/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ -#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ -#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ - -/* Register: WDT_RR */ -/* Description: Reload requests registers. */ - -/* Bits 31..0 : Reload register. */ -#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ -#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ -#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ - -/* Register: WDT_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/*lint --flb "Leave library region" */ -#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/nrf51_deprecated.h Thu Feb 13 11:27:58 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,359 +0,0 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - - -#ifndef NRF51_DEPRECATED_H -#define NRF51_DEPRECATED_H - -#include "nordic_global.h" - -/*lint ++flb "Enter library region */ - -/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and - * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these - * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. - */ - - -/* FICR */ -#define SIZERAMBLOCK0 SIZERAMBLOCK[0] /*!< Size of RAM block 0 in bytes. */ -#define SIZERAMBLOCK1 SIZERAMBLOCK[1] /*!< Size of RAM block 1 in bytes. */ -#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Size of RAM block 2 in bytes. */ -#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Size of RAM block 3 in bytes. */ -#define DEVICEID0 DEVICEID[0] /*!< Device identifier, bits 31 to 0. */ -#define DEVICEID1 DEVICEID[1] /*!< Device identifier, bits 63 to 32. */ -#define ER0 ER[0] /*!< Encryption root, bits 31..0. */ -#define ER1 ER[1] /*!< Encryption root, bits 63..32. */ -#define ER2 ER[2] /*!< Encryption root, bits 95..64. */ -#define ER3 ER[3] /*!< Encryption root, bits 127..96. */ -#define IR0 IR[0] /*!< Identity root, bits 31..0. */ -#define IR1 IR[1] /*!< Identity root, bits 63..32. */ -#define IR2 IR[2] /*!< Identity root, bits 95..64. */ -#define IR3 IR[3] /*!< Identity root, bits 127..96. */ -#define DEVICEADDR0 DEVICEADDR[0] /*!< Device address, bits 31..0. */ -#define DEVICEADDR1 DEVICEADDR[1] /*!< Device address, bits 63..32. */ - - -/* PPI */ -#define TASKS_CHG0EN TASKS_CHG[0].EN /*!< Enable channel group 0. */ -#define TASKS_CHG0DIS TASKS_CHG[0].DIS /*!< Disable channel group 0. */ -#define TASKS_CHG1EN TASKS_CHG[1].EN /*!< Enable channel group 1. */ -#define TASKS_CHG1DIS TASKS_CHG[1].DIS /*!< Disable channel group 1. */ -#define TASKS_CHG2EN TASKS_CHG[2].EN /*!< Enable channel group 2. */ -#define TASKS_CHG2DIS TASKS_CHG[2].DIS /*!< Disable channel group 2. */ -#define TASKS_CHG3EN TASKS_CHG[3].EN /*!< Enable channel group 3. */ -#define TASKS_CHG3DIS TASKS_CHG[3].DIS /*!< Disable channel group 3. */ -#define CH0_EEP CH[0].EEP /*!< Channel 0 event end-point. */ -#define CH0_TEP CH[0].TEP /*!< Channel 0 task end-point. */ -#define CH1_EEP CH[1].EEP /*!< Channel 1 event end-point. */ -#define CH1_TEP CH[1].TEP /*!< Channel 1 task end-point. */ -#define CH2_EEP CH[2].EEP /*!< Channel 2 event end-point. */ -#define CH2_TEP CH[2].TEP /*!< Channel 2 task end-point. */ -#define CH3_EEP CH[3].EEP /*!< Channel 3 event end-point. */ -#define CH3_TEP CH[3].TEP /*!< Channel 3 task end-point. */ -#define CH4_EEP CH[4].EEP /*!< Channel 4 event end-point. */ -#define CH4_TEP CH[4].TEP /*!< Channel 4 task end-point. */ -#define CH5_EEP CH[5].EEP /*!< Channel 5 event end-point. */ -#define CH5_TEP CH[5].TEP /*!< Channel 5 task end-point. */ -#define CH6_EEP CH[6].EEP /*!< Channel 6 event end-point. */ -#define CH6_TEP CH[6].TEP /*!< Channel 6 task end-point. */ -#define CH7_EEP CH[7].EEP /*!< Channel 7 event end-point. */ -#define CH7_TEP CH[7].TEP /*!< Channel 7 task end-point. */ -#define CH8_EEP CH[8].EEP /*!< Channel 8 event end-point. */ -#define CH8_TEP CH[8].TEP /*!< Channel 8 task end-point. */ -#define CH9_EEP CH[9].EEP /*!< Channel 9 event end-point. */ -#define CH9_TEP CH[9].TEP /*!< Channel 9 task end-point. */ -#define CH10_EEP CH[10].EEP /*!< Channel 10 event end-point. */ -#define CH10_TEP CH[10].TEP /*!< Channel 10 task end-point. */ -#define CH11_EEP CH[11].EEP /*!< Channel 11 event end-point. */ -#define CH11_TEP CH[11].TEP /*!< Channel 11 task end-point. */ -#define CH12_EEP CH[12].EEP /*!< Channel 12 event end-point. */ -#define CH12_TEP CH[12].TEP /*!< Channel 12 task end-point. */ -#define CH13_EEP CH[13].EEP /*!< Channel 13 event end-point. */ -#define CH13_TEP CH[13].TEP /*!< Channel 13 task end-point. */ -#define CH14_EEP CH[14].EEP /*!< Channel 14 event end-point. */ -#define CH14_TEP CH[14].TEP /*!< Channel 14 task end-point. */ -#define CH15_EEP CH[15].EEP /*!< Channel 15 event end-point. */ -#define CH15_TEP CH[15].TEP /*!< Channel 15 task end-point. */ -#define CHG0 CHG[0] /*!< Channel group 0. */ -#define CHG1 CHG[1] /*!< Channel group 1. */ -#define CHG2 CHG[2] /*!< Channel group 2. */ -#define CHG3 CHG[3] /*!< Channel group 3. */ - - - -#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos /*!< Position of CH15 field. */ -#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk /*!< Bit mask of CH15 field. */ -#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included /*!< Channel included. */ -#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos /*!< Position of CH14 field. */ -#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk /*!< Bit mask of CH14 field. */ -#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included /*!< Channel included. */ -#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos /*!< Position of CH13 field. */ -#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk /*!< Bit mask of CH13 field. */ -#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included /*!< Channel included. */ -#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos /*!< Position of CH12 field. */ -#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk /*!< Bit mask of CH12 field. */ -#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included /*!< Channel included. */ -#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos /*!< Position of CH11 field. */ -#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk /*!< Bit mask of CH11 field. */ -#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included /*!< Channel included. */ -#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos /*!< Position of CH10 field. */ -#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk /*!< Bit mask of CH10 field. */ -#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included /*!< Channel included. */ -#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos /*!< Position of CH9 field. */ -#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk /*!< Bit mask of CH9 field. */ -#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included /*!< Channel included. */ -#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos /*!< Position of CH8 field. */ -#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk /*!< Bit mask of CH8 field. */ -#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included /*!< Channel included. */ -#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos /*!< Position of CH7 field. */ -#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk /*!< Bit mask of CH7 field. */ -#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included /*!< Channel included. */ -#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos /*!< Position of CH6 field. */ -#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk /*!< Bit mask of CH6 field. */ -#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included /*!< Channel included. */ -#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos /*!< Position of CH5 field. */ -#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk /*!< Bit mask of CH5 field. */ -#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included /*!< Channel included. */ -#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos /*!< Position of CH4 field. */ -#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk /*!< Bit mask of CH4 field. */ -#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included /*!< Channel included. */ -#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos /*!< Position of CH3 field. */ -#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk /*!< Bit mask of CH3 field. */ -#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included /*!< Channel included. */ -#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos /*!< Position of CH2 field. */ -#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk /*!< Bit mask of CH2 field. */ -#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included /*!< Channel included. */ -#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos /*!< Position of CH1 field. */ -#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk /*!< Bit mask of CH1 field. */ -#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included /*!< Channel included. */ -#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos /*!< Position of CH0 field. */ -#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk /*!< Bit mask of CH0 field. */ -#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded /*!< Channel excluded. */ -#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included /*!< Channel included. */ - -#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos /*!< Position of CH15 field. */ -#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk /*!< Bit mask of CH15 field. */ -#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included /*!< Channel included. */ -#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos /*!< Position of CH14 field. */ -#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk /*!< Bit mask of CH14 field. */ -#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included /*!< Channel included. */ -#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos /*!< Position of CH13 field. */ -#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk /*!< Bit mask of CH13 field. */ -#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included /*!< Channel included. */ -#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos /*!< Position of CH12 field. */ -#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk /*!< Bit mask of CH12 field. */ -#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included /*!< Channel included. */ -#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos /*!< Position of CH11 field. */ -#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk /*!< Bit mask of CH11 field. */ -#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included /*!< Channel included. */ -#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos /*!< Position of CH10 field. */ -#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk /*!< Bit mask of CH10 field. */ -#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included /*!< Channel included. */ -#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos /*!< Position of CH9 field. */ -#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk /*!< Bit mask of CH9 field. */ -#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included /*!< Channel included. */ -#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos /*!< Position of CH8 field. */ -#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk /*!< Bit mask of CH8 field. */ -#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included /*!< Channel included. */ -#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos /*!< Position of CH7 field. */ -#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk /*!< Bit mask of CH7 field. */ -#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included /*!< Channel included. */ -#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos /*!< Position of CH6 field. */ -#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk /*!< Bit mask of CH6 field. */ -#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included /*!< Channel included. */ -#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos /*!< Position of CH5 field. */ -#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk /*!< Bit mask of CH5 field. */ -#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included /*!< Channel included. */ -#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos /*!< Position of CH4 field. */ -#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk /*!< Bit mask of CH4 field. */ -#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included /*!< Channel included. */ -#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos /*!< Position of CH3 field. */ -#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk /*!< Bit mask of CH3 field. */ -#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included /*!< Channel included. */ -#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos /*!< Position of CH2 field. */ -#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk /*!< Bit mask of CH2 field. */ -#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included /*!< Channel included. */ -#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos /*!< Position of CH1 field. */ -#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk /*!< Bit mask of CH1 field. */ -#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included /*!< Channel included. */ -#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos /*!< Position of CH0 field. */ -#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk /*!< Bit mask of CH0 field. */ -#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded /*!< Channel excluded. */ -#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included /*!< Channel included. */ - -#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos /*!< Position of CH15 field. */ -#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk /*!< Bit mask of CH15 field. */ -#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included /*!< Channel included. */ -#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos /*!< Position of CH14 field. */ -#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk /*!< Bit mask of CH14 field. */ -#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included /*!< Channel included. */ -#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos /*!< Position of CH13 field. */ -#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk /*!< Bit mask of CH13 field. */ -#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included /*!< Channel included. */ -#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos /*!< Position of CH12 field. */ -#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk /*!< Bit mask of CH12 field. */ -#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included /*!< Channel included. */ -#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos /*!< Position of CH11 field. */ -#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk /*!< Bit mask of CH11 field. */ -#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included /*!< Channel included. */ -#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos /*!< Position of CH10 field. */ -#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk /*!< Bit mask of CH10 field. */ -#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included /*!< Channel included. */ -#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos /*!< Position of CH9 field. */ -#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk /*!< Bit mask of CH9 field. */ -#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included /*!< Channel included. */ -#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos /*!< Position of CH8 field. */ -#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk /*!< Bit mask of CH8 field. */ -#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included /*!< Channel included. */ -#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos /*!< Position of CH7 field. */ -#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk /*!< Bit mask of CH7 field. */ -#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included /*!< Channel included. */ -#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos /*!< Position of CH6 field. */ -#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk /*!< Bit mask of CH6 field. */ -#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included /*!< Channel included. */ -#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos /*!< Position of CH5 field. */ -#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk /*!< Bit mask of CH5 field. */ -#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included /*!< Channel included. */ -#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos /*!< Position of CH4 field. */ -#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk /*!< Bit mask of CH4 field. */ -#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included /*!< Channel included. */ -#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos /*!< Position of CH3 field. */ -#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk /*!< Bit mask of CH3 field. */ -#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included /*!< Channel included. */ -#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos /*!< Position of CH2 field. */ -#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk /*!< Bit mask of CH2 field. */ -#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included /*!< Channel included. */ -#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos /*!< Position of CH1 field. */ -#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk /*!< Bit mask of CH1 field. */ -#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included /*!< Channel included. */ -#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos /*!< Position of CH0 field. */ -#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk /*!< Bit mask of CH0 field. */ -#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded /*!< Channel excluded. */ -#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included /*!< Channel included. */ - -#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos /*!< Position of CH15 field. */ -#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk /*!< Bit mask of CH15 field. */ -#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included /*!< Channel included. */ -#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos /*!< Position of CH14 field. */ -#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk /*!< Bit mask of CH14 field. */ -#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included /*!< Channel included. */ -#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos /*!< Position of CH13 field. */ -#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk /*!< Bit mask of CH13 field. */ -#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included /*!< Channel included. */ -#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos /*!< Position of CH12 field. */ -#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk /*!< Bit mask of CH12 field. */ -#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included /*!< Channel included. */ -#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos /*!< Position of CH11 field. */ -#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk /*!< Bit mask of CH11 field. */ -#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included /*!< Channel included. */ -#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos /*!< Position of CH10 field. */ -#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk /*!< Bit mask of CH10 field. */ -#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included /*!< Channel included. */ -#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos /*!< Position of CH9 field. */ -#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk /*!< Bit mask of CH9 field. */ -#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included /*!< Channel included. */ -#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos /*!< Position of CH8 field. */ -#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk /*!< Bit mask of CH8 field. */ -#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included /*!< Channel included. */ -#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos /*!< Position of CH7 field. */ -#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk /*!< Bit mask of CH7 field. */ -#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included /*!< Channel included. */ -#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos /*!< Position of CH6 field. */ -#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk /*!< Bit mask of CH6 field. */ -#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included /*!< Channel included. */ -#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos /*!< Position of CH5 field. */ -#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk /*!< Bit mask of CH5 field. */ -#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included /*!< Channel included. */ -#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos /*!< Position of CH4 field. */ -#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk /*!< Bit mask of CH4 field. */ -#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included /*!< Channel included. */ -#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos /*!< Position of CH3 field. */ -#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk /*!< Bit mask of CH3 field. */ -#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included /*!< Channel included. */ -#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos /*!< Position of CH2 field. */ -#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk /*!< Bit mask of CH2 field. */ -#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included /*!< Channel included. */ -#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos /*!< Position of CH1 field. */ -#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk /*!< Bit mask of CH1 field. */ -#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included /*!< Channel included. */ -#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos /*!< Position of CH0 field. */ -#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk /*!< Bit mask of CH0 field. */ -#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded /*!< Channel excluded. */ -#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included /*!< Channel included. */ - -#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm /*!< -30dBm. */ - -/*lint --flb "Leave library region" */ - -#endif /* NRF51_DEPRECATED_H */ -
--- a/hw/nRF51822n/nordic/nrf-sdk/nrf_delay.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-#ifndef _NRF_DELAY_H
-#define _NRF_DELAY_H
-
-#include "nordic_global.h"
-#include "nrf.h"
-
-/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
-#if defined ( __CC_ARM )
-static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
-{
-loop
- SUBS R0, R0, #1
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- BNE loop
- BX LR
-}
-#elif defined ( __ICCARM__ )
-static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
-{
-__ASM (
-"loop:\n\t"
- " SUBS R0, R0, #1\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " NOP\n\t"
- " BNE loop\n\t");
-}
-#elif defined ( __GNUC__ )
-static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
-{
- do
- {
- __ASM volatile (
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- "NOP\n\t"
- );
- } while (--number_of_us);
-}
-#endif
-
-void nrf_delay_ms(uint32_t volatile number_of_ms);
-
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/nrf_gpiote.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,157 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-#ifndef NRF_GPIOTE_H__
-#define NRF_GPIOTE_H__
-
-#include "nordic_global.h"
-#include "nrf.h"
-
-/**
-* @defgroup nrf_gpiote GPIOTE abstraction
-* @{
-* @ingroup nrf_drivers
-* @brief GPIOTE abstraction for configuration of channels.
-*/
-
-
- /**
- * @enum nrf_gpiote_polarity_t
- * @brief Polarity for GPIOTE channel enumerator.
- */
-typedef enum
-{
- NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high
- NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low
- NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle
-} nrf_gpiote_polarity_t;
-
-
- /**
- * @enum nrf_gpiote_outinit_t
- * @brief Initial output value for GPIOTE channel enumerator.
- */
-typedef enum
-{
- NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high
- NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low
-} nrf_gpiote_outinit_t;
-
-
-/**
- * @brief Function for configuring GPIOTE channel as output, setting the properly desired output level.
- *
- *
- * @param channel_number specifies the GPIOTE channel [0:3] to configure as an output channel.
- * @param pin_number specifies the pin number [0:30] to use in the GPIOTE channel.
- * @param polarity specifies the desired polarity in the output GPIOTE channel.
- * @param initial_value specifies the initial value of the GPIOTE channel input after the channel configuration.
- */
-static __INLINE void nrf_gpiote_task_config(uint32_t channel_number, uint32_t pin_number, nrf_gpiote_polarity_t polarity, nrf_gpiote_outinit_t initial_value)
-{
- /* Check if the output desired is high or low */
- if (initial_value == NRF_GPIOTE_INITIAL_VALUE_LOW)
- {
- /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
- on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
- correct state in GPIOTE but not in the OUT register. */
- NRF_GPIO->OUTCLR = (1 << pin_number);
-
- /* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
- NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
- (31UL << GPIOTE_CONFIG_PSEL_Pos) |
- (GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
- }
- else
- {
- /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
- on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
- correct state in GPIOTE but not in the OUT register. */
- NRF_GPIO->OUTSET = (1 << pin_number);
-
- /* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
- NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
- (31UL << GPIOTE_CONFIG_PSEL_Pos) |
- (GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
- }
-
- /* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
- __NOP();
- __NOP();
- __NOP();
-
- /* Launch the task to take the GPIOTE channel output to the desired level */
- NRF_GPIOTE->TASKS_OUT[channel_number] = 1;
-
-
- /* Finally configure the channel as the caller expects. If OUTINIT works, the channel is configured properly.
- If it does not, the channel output inheritance sets the proper level. */
- NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
- ((uint32_t)pin_number << GPIOTE_CONFIG_PSEL_Pos) |
- ((uint32_t)polarity << GPIOTE_CONFIG_POLARITY_Pos) |
- ((uint32_t)initial_value << GPIOTE_CONFIG_OUTINIT_Pos);
-
- /* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
- __NOP();
- __NOP();
- __NOP();
-}
-
-/**
- * @brief Function for configuring GPIOTE channel as input, automatically clearing an event that appears in some cases under configuration.
- *
- * Note that the pin must be configured as connected input for this
- * function to have any effect.
- *
- * Note that when configuring the channel as input an event might be triggered. Care of disabling interrupts
- * for that channel is left to the user.
- *
- * @param channel_number specifies the GPIOTE channel [0:3] to configure as an input channel.
- * @param pin_number specifies the pin number [0:30] to use in the GPIOTE channel.
- * @param polarity specifies the desired polarity in the output GPIOTE channel.
- */
-static __INLINE void nrf_gpiote_event_config(uint32_t channel_number, uint32_t pin_number, nrf_gpiote_polarity_t polarity)
-{
- /* Configure the channel as the caller expects */
- NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) |
- ((uint32_t)pin_number << GPIOTE_CONFIG_PSEL_Pos) |
- ((uint32_t)polarity << GPIOTE_CONFIG_POLARITY_Pos);
-
- /* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
- __NOP();
- __NOP();
- __NOP();
-
- /* Clear the event that appears in some cases */
- NRF_GPIOTE->EVENTS_IN[channel_number] = 0;
-}
-
-
-/**
- * @brief Function for unconfiguring GPIOTE channel.
- *
- *
- * Note that when unconfiguring the channel, the pin is configured as GPIO PIN_CNF configuration.
- *
- * @param channel_number specifies the GPIOTE channel [0:3] to unconfigure.
- */
-static __INLINE void nrf_gpiote_unconfig(uint32_t channel_number)
-{
- /* Unonfigure the channel as the caller expects */
- NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos) |
- (31UL << GPIOTE_CONFIG_PSEL_Pos) |
- (GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
-}
-
-
-/** @} */
-
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,322 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-/**
- @addtogroup BLE_COMMON BLE SoftDevice Common
- @{
- @defgroup ble_api Events, type definitions and API calls
- @{
-
- @brief Module independent events, type definitions and API calls for the S120 SoftDevice.
-
- */
-
-#ifndef BLE_H__
-#define BLE_H__
-
-#include "ble_ranges.h"
-#include "ble_types.h"
-#include "ble_gap.h"
-#include "ble_l2cap.h"
-#include "ble_gatt.h"
-#include "ble_gattc.h"
-#include "ble_gatts.h"
-
-/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations
- * @{ */
-
-/**
- * @brief Common API SVC numbers.
- */
-enum BLE_COMMON_SVCS
-{
- SD_BLE_EVT_GET = BLE_SVC_BASE, /**< Get an event from the pending events queue. */
- SD_BLE_TX_BUFFER_COUNT_GET, /**< Get the total number of available application transmission buffers from the stack. */
- SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific UUID. */
- SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */
- SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */
- SD_BLE_VERSION_GET, /**< Get the local version information (company id, LMP Version, LMP Subversion). */
- SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */
-};
-
-
-/**
- * @brief BLE Module Independent Event IDs.
- */
-enum BLE_COMMON_EVTS
-{
- BLE_EVT_TX_COMPLETE = BLE_EVT_BASE, /**< Transmission Complete. */
- BLE_EVT_USER_MEM_REQUEST, /**< User Memory request. */
- BLE_EVT_USER_MEM_RELEASE /**< User Memory release. */
-};
-
-/** @} */
-
-/** @addtogroup BLE_COMMON_DEFINES Defines
- * @{ */
-
-/** @defgroup BLE_USER_MEM_TYPES User Memory Types
- * @{ */
-#define BLE_USER_MEM_TYPE_INVALID 0x00 /**< Invalid User Memory Types. */
-#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES 0x01 /**< User Memory for GATTS queued writes. */
-/** @} */
-
-/** @brief Maximum number of Vendor Specific UUIDs.
-*/
-#define BLE_UUID_VS_MAX_COUNT 10
-
-/** @brief Required pointer alignment for BLE Events.
-*/
-#define BLE_EVTS_PTR_ALIGNMENT 4
-
-/** @} */
-
-/** @addtogroup BLE_COMMON_STRUCTURES Structures
- * @{ */
-
-/**@brief User Memory Block. */
-typedef struct
-{
- uint8_t* p_mem; /**< Pointer to the start of the user memory block. */
- uint16_t len; /**< Length in bytes of the user memory block. */
-} ble_user_mem_block_t;
-
-/**
- * @brief TX complete event.
- */
-typedef struct
-{
- uint8_t count; /**< Number of packets transmitted. */
-} ble_evt_tx_complete_t;
-
-/**@brief Event structure for BLE_EVT_USER_MEM_REQUEST. */
-typedef struct
-{
- uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
-} ble_evt_user_mem_request_t;
-
-/**@brief Event structure for BLE_EVT_USER_MEM_RELEASE. */
-typedef struct
-{
- uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
- ble_user_mem_block_t mem_block; /**< User memory block */
-} ble_evt_user_mem_release_t;
-
-
-/**@brief Event structure for events not associated with a specific function module. */
-typedef struct
-{
- uint16_t conn_handle; /**< Connection Handle on which this event occured. */
- union
- {
- ble_evt_tx_complete_t tx_complete; /**< Transmission Complete. */
- ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */
- ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */
- } params; /**< Event Parameters. */
-} ble_common_evt_t;
-
-/**@brief BLE Event header. */
-typedef struct
-{
- uint16_t evt_id; /**< Value from a BLE_<module>_EVT series. */
- uint16_t evt_len; /**< Length in octets excluding this header. */
-} ble_evt_hdr_t;
-
-/**@brief Common BLE Event type, wrapping the module specific event reports. */
-typedef struct
-{
- ble_evt_hdr_t header; /**< Event header. */
- union
- {
- ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */
- ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */
- ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */
- ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */
- ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */
- } evt; /**< Event Union. */
-} ble_evt_t;
-
-
-/**
- * @brief Version Information.
- */
-typedef struct
-{
- uint8_t version_number; /**< LMP Version number for BT 4.0 spec is 6 (https://www.bluetooth.org/technical/assignednumbers/link_layer.htm). */
- uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */
- uint16_t subversion_number; /**< LMP Sub Version number corresponds to the SoftDevice Config ID. */
-} ble_version_t;
-
-/** @} */
-
-/** @addtogroup BLE_COMMON_FUNCTIONS Functions
- * @{ */
-
-/**@brief Get an event from the pending events queue.
- *
- * @param[in] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length. This buffer <b>must be 4-byte aligned in memory</b>.
- * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length.
- *
- * @details This call allows the application to pull a BLE event from the BLE stack. The application is signalled that an event is
- * available from the BLE Stack by the triggering of the SD_EVENT_IRQn interrupt (mapped to IRQ 22).
- * The application is free to choose whether to call this function from thread mode (main context) or directly from the Interrupt Service Routine
- * that maps to SD_EVENT_IRQn. In any case however, and because the BLE stack runs at a higher priority than the application, this function should be called
- * in a loop (until @ref NRF_ERROR_NOT_FOUND is returned) every time SD_EVENT_IRQn is raised to ensure that all available events are pulled from the stack.
- * Failure to do so could potentially leave events in the internal queue without the application being aware of this fact.
- * Sizing the p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to be copied into
- * application memory. If the buffer provided is not large enough to fit the entire contents of the event, @ref NRF_ERROR_DATA_SIZE will be returned
- * and the application can then call again with a larger buffer size.
- * Please note that because of the variable length nature of some events, sizeof(ble_evt_t) will not always be large enough to fit certain events,
- * and so it is the application's responsibility to provide an amount of memory large enough so that the relevant event is copied in full.
- * The application may "peek" the event length by providing p_dest as a NULL pointer and inspecting the value of *p_len upon return.
- *
- * @note The pointer supplied must be aligned to the extend defined by @ref BLE_EVTS_PTR_ALIGNMENT
- *
- * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied.
- * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled.
- * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer.
- */
-SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t* p_dest, uint16_t *p_len));
-
-
-/**@brief Get the total number of available application transmission buffers in the BLE stack.
- *
- * @details This call allows the application to obtain the total number of
- * transmission buffers available for application data. Please note that
- * this does not give the number of free buffers, but rather the total amount of them.
- * The application has two options to handle its own application transmission buffers:
- * - Use a simple arithmetic calculation: at boot time the application should use this function
- * to find out the total amount of buffers available to it and store it in a variable.
- * Every time a packet that consumes an application buffer is sent using any of the
- * exposed functions in this BLE API, the application should decrement that variable.
- * Conversely, whenever a @ref BLE_EVT_TX_COMPLETE event is received by the application
- * it should retrieve the count field in such event and add that number to the same
- * variable storing the number of available packets.
- * This mechanism allows the application to be aware at any time of the number of
- * application packets available in the BLE stack's internal buffers, and therefore
- * it can know with certainty whether it is possible to send more data or it has to
- * wait for a @ref BLE_EVT_TX_COMPLETE event before it proceeds.
- * - Choose to simply not keep track of available buffers at all, and instead handle the
- * @ref BLE_ERROR_NO_TX_BUFFERS error by queuing the packet to be transmitted and
- * try again as soon as a @ref BLE_EVT_TX_COMPLETE event arrives.
- *
- * The API functions that <b>may</b> consume an application buffer depending on
- * the parameters supplied to them can be found below:
- *
- * - @ref sd_ble_gattc_write (write without response only)
- * - @ref sd_ble_gatts_hvx (notifications only)
- * - @ref sd_ble_l2cap_tx (all packets)
- *
- * @param[out] p_count Pointer to a uint8_t which will contain the number of application transmission buffers upon
- * successful return.
- *
- * @retval ::NRF_SUCCESS Number of application transmission buffers retrieved successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- */
-SVCALL(SD_BLE_TX_BUFFER_COUNT_GET, uint32_t, sd_ble_tx_buffer_count_get(uint8_t* p_count));
-
-
-/**@brief Add a Vendor Specific UUID.
- *
- * @details This call enables the application to add a vendor specific UUID to the BLE stack's table,
- * for later use all other modules and APIs. This then allows the application to use the shorter,
- * 24-bit @ref ble_uuid_t format when dealing with both 16-bit and 128-bit UUIDs without having to
- * check for lengths and having split code paths. The way that this is accomplished is by extending the
- * grouping mechanism that the Bluetooth SIG standard base UUID uses for all other 128-bit UUIDs. The
- * type field in the @ref ble_uuid_t structure is an index (relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN)
- * to the table populated by multiple calls to this function, and the uuid field in the same structure contains the 2 bytes
- * (byte 12 and byte 13) corresponding to the TimeLow portion of the UUID. The number of possible 128-bit
- * UUIDs available to the application is therefore the number of Vendor Specific UUIDs added with the help
- * of this function times 65536, although restricted to modifying the TimeLow bytes for each of the entries in the supplied array.
- *
- * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by
- * the 16-bit uuid field in @ref ble_uuid_t.
- *
- *
- * @param[in] p_vs_uuid Pointer to a 16-octet (128-bit) little endian Vendor Specific UUID disregarding
- * the TimeLow (bytes 12 and 13) portion of it.
- * @param[out] p_uuid_type Pointer where the type field in @ref ble_uuid_t corresponding to this UUID will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added the Vendor Specific UUID.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_NO_MEM If the size exceeds the number of free slots for VS UUIDs.
- * @retval ::NRF_ERROR_INVALID_LENGTH If vs_uuid_count is 0.
- * @retval ::NRF_ERROR_INVALID_ADDR if p_vs_uuids is NULL or invalid.
- */
-SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const * const p_vs_uuid, uint8_t * const p_uuid_type));
-
-
-/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure.
- *
- * @details The raw UUID bytes excluding the TimeLow portion (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared
- * to the corresponding ones in each entry of the table of vendor specific UUIDs populated with @ref sd_ble_uuid_vs_add
- * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index
- * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type.
- *
- * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE.
- *
- * @param[in] uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes).
- * @param[in] p_uuid_le Pointer pointing to little endian raw UUID bytes.
- * @param[in,out] p_uuid Pointer to a @ref ble_uuid_t structure to be filled in.
- *
- * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length.
- * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs.
- */
-SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const * const p_uuid_le, ble_uuid_t * const p_uuid));
-
-
-/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit).
- *
- * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed.
- *
- * @param[in] p_uuid Pointer to a @ref ble_uuid_t structure that will be encoded into bytes.
- * @param[out] p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes).
- * @param[out] p_uuid_le Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully encoded into the buffer.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type.
- */
-SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const * const p_uuid, uint8_t * const p_uuid_le_len, uint8_t * const p_uuid_le));
-
-
-/**@brief Get Version Information.
- *
- * @details This call allows the application to get the BLE stack version information.
- *
- * @param[in] p_version Pointer to ble_version_t structure to be filled in.
- *
- * @retval ::NRF_SUCCESS Version information stored successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- */
-SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t * p_version));
-
-
-/**@brief Provide a user memory block.
- *
- * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_block Pointer to a user memory block structure.
- *
- * @return @ref NRF_SUCCESS Successfully queued a response to the peer.
- * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @return @ref NRF_ERROR_INVALID_STATE No execute write request pending.
- */
-SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t *p_block));
-
-/** @} */
-
-#endif /* BLE_H__ */
-
-/**
- @}
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_err.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
- /**
- @addtogroup BLE_COMMON
- @{
- @addtogroup nrf_error
- @{
- @ingroup BLE_COMMON
- @}
-
- @defgroup ble_err General error codes
- @{
-
- @brief General error code definitions for the BLE API.
-
- @ingroup BLE_COMMON
-*/
-#ifndef NRF_BLE_ERR_H__
-#define NRF_BLE_ERR_H__
-
-#include "nrf_error.h"
-
-/* @defgroup BLE_ERRORS Error Codes
- * @{ */
-#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM+0x001) /**< Invalid connection handle. */
-#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid attribute handle. */
-#define BLE_ERROR_NO_TX_BUFFERS (NRF_ERROR_STK_BASE_NUM+0x003) /**< Buffer capacity exceeded. */
-#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM+0x004) /**< Invalid role (Master or Slave). */
-/** @} */
-
-
-/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges
- * @brief Assignment of subranges for module specific error codes.
- * @note For specific error codes, see ble_<module>.h or ble_error_<module>.h.
- * @{ */
-#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */
-#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */
-#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */
-#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */
-/** @} */
-
-#endif
-
-
-/**
- @}
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_gap.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1045 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-/**
- @addtogroup BLE_GAP Generic Access Profile (GAP)
- @{
- @brief Definitions and prototypes for the GAP interface.
- */
-
-#ifndef BLE_GAP_H__
-#define BLE_GAP_H__
-
-#include "ble_types.h"
-#include "ble_ranges.h"
-#include "nrf_svc.h"
-
-
-/** @addtogroup BLE_GAP_ENUMERATIONS Enumerations
- * @{ */
-
-/**
- * @brief GAP API SVC numbers.
- */
-enum BLE_GAP_SVCS
-{
- SD_BLE_GAP_ADDRESS_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */
- SD_BLE_GAP_ADDRESS_GET, /**< Get own Bluetooth Address. */
- SD_BLE_GAP_ADV_DATA_SET, /**< Set Advertisement Data. */
- SD_BLE_GAP_ADV_START, /**< Start Advertising. */
- SD_BLE_GAP_ADV_STOP, /**< Stop Advertising. */
- SD_BLE_GAP_CONN_PARAM_UPDATE, /**< Connection Parameter Update. */
- SD_BLE_GAP_DISCONNECT, /**< Disconnect. */
- SD_BLE_GAP_TX_POWER_SET, /**< Set TX Power. */
- SD_BLE_GAP_APPEARANCE_SET, /**< Set Appearance. */
- SD_BLE_GAP_APPEARANCE_GET, /**< Get Appearance. */
- SD_BLE_GAP_PPCP_SET, /**< Set PPCP. */
- SD_BLE_GAP_PPCP_GET, /**< Get PPCP. */
- SD_BLE_GAP_DEVICE_NAME_SET, /**< Set Device Name. */
- SD_BLE_GAP_DEVICE_NAME_GET, /**< Get Device Name. */
- SD_BLE_GAP_AUTHENTICATE, /**< Initiate Pairing/Bonding. */
- SD_BLE_GAP_SEC_PARAMS_REPLY, /**< Reply with Security Parameters. */
- SD_BLE_GAP_AUTH_KEY_REPLY, /**< Reply with an authentication key. */
- SD_BLE_GAP_ENCRYPT, /**< Initiate encryption procedure. */
- SD_BLE_GAP_SEC_INFO_REPLY, /**< Reply with Security Information. */
- SD_BLE_GAP_CONN_SEC_GET, /**< Obtain connection security level. */
- SD_BLE_GAP_RSSI_START, /**< Start reporting of changes in RSSI. */
- SD_BLE_GAP_RSSI_STOP, /**< Stop reporting of changes in RSSI. */
- SD_BLE_GAP_SCAN_START, /**< Start Scanning. */
- SD_BLE_GAP_SCAN_STOP, /**< Stop Scanning. */
- SD_BLE_GAP_CONNECT, /**< Connect. */
- SD_BLE_GAP_CONNECT_CANCEL, /**< Cancel ongoing connection procedure. */
-};
-
-/**
- * @brief GAP Event IDs.
- * Those IDs uniquely identify an event coming from the stack to the application.
- */
-enum BLE_GAP_EVTS
-{
- BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connection established. */
- BLE_GAP_EVT_DISCONNECTED, /**< Disconnected from peer. */
- BLE_GAP_EVT_CONN_PARAM_UPDATE, /**< Connection Parameters updated. */
- BLE_GAP_EVT_SEC_PARAMS_REQUEST, /**< Request to provide security parameters. */
- BLE_GAP_EVT_SEC_INFO_REQUEST, /**< Request to provide security information. */
- BLE_GAP_EVT_PASSKEY_DISPLAY, /**< Request to display a passkey to the user. */
- BLE_GAP_EVT_AUTH_KEY_REQUEST, /**< Request to provide an authentication key. */
- BLE_GAP_EVT_AUTH_STATUS, /**< Authentication procedure completed with status. */
- BLE_GAP_EVT_CONN_SEC_UPDATE, /**< Connection security updated. */
- BLE_GAP_EVT_TIMEOUT, /**< Timeout expired. */
- BLE_GAP_EVT_RSSI_CHANGED, /**< Signal strength measurement report. */
- BLE_GAP_EVT_ADV_REPORT, /**< Advertisement report. */
- BLE_GAP_EVT_SEC_REQUEST, /**< Security Request. */
- BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, /**< Connection Parameter Update Request. */
-};
-
-/** @} */
-
-/** @addtogroup BLE_GAP_DEFINES Defines
- * @{ */
-
-/** @defgroup BLE_ERRORS_GAP SVC return values specific to GAP
- * @{ */
-#define BLE_ERROR_GAP_UUID_LIST_MISMATCH (NRF_GAP_ERR_BASE + 0x000) /**< UUID list does not contain an integral number of UUIDs. */
-#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST (NRF_GAP_ERR_BASE + 0x001) /**< Use of Whitelist not permitted with discoverable advertising. */
-#define BLE_ERROR_GAP_INVALID_BLE_ADDR (NRF_GAP_ERR_BASE + 0x002) /**< The upper two bits of the address do not correspond to the specified address type. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_ROLES GAP Roles
- * @note Not explicitly used in peripheral API, but will be relevant for central API.
- * @{ */
-#define BLE_GAP_ROLE_INVALID 0x0 /**< Invalid Role. */
-#define BLE_GAP_ROLE_PERIPH 0x1 /**< Peripheral Role. */
-#define BLE_GAP_ROLE_CENTRAL 0x2 /**< Central Role. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources
- * @{ */
-#define BLE_GAP_TIMEOUT_SRC_ADVERTISEMENT 0x00 /**< Advertisement timeout. */
-#define BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST 0x01 /**< Security request timeout. */
-#define BLE_GAP_TIMEOUT_SRC_SCAN 0x02 /**< Scanning timeout. */
-#define BLE_GAP_TIMEOUT_SRC_CONN 0x03 /**< Connection timeout. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_ADDR_TYPES GAP Address types
- * @{ */
-#define BLE_GAP_ADDR_TYPE_PUBLIC 0x00 /**< Public address. */
-#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC 0x01 /**< Random Static address. */
-#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE 0x02 /**< Private Resolvable address. */
-#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Private Non-Resolvable address. */
-/** @} */
-
-
-/** @brief BLE address length. */
-#define BLE_GAP_ADDR_LEN 6
-
-
-/** @defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format
- * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm
- * @{ */
-#define BLE_GAP_AD_TYPE_FLAGS 0x01 /**< Flags for discoverability. */
-#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE 0x02 /**< Partial list of 16 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE 0x03 /**< Complete list of 16 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE 0x04 /**< Partial list of 32 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE 0x05 /**< Complete list of 32 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE 0x06 /**< Partial list of 128 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE 0x07 /**< Complete list of 128 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME 0x08 /**< Short local device name. */
-#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME 0x09 /**< Complete local device name. */
-#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL 0x0A /**< Transmit power level. */
-#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE 0x0D /**< Class of device. */
-#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C 0x0E /**< Simple Pairing Hash C. */
-#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R 0x0F /**< Simple Pairing Randomizer R. */
-#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE 0x10 /**< Security Manager TK Value. */
-#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS 0x11 /**< Security Manager Out Of Band Flags. */
-#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 /**< Slave Connection Interval Range. */
-#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT 0x14 /**< List of 16-bit Service Solicitation UUIDs. */
-#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT 0x15 /**< List of 128-bit Service Solicitation UUIDs. */
-#define BLE_GAP_AD_TYPE_SERVICE_DATA 0x16 /**< Service Data. */
-#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS 0x17 /**< Public Target Address. */
-#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS 0x18 /**< Random Target Address. */
-#define BLE_GAP_AD_TYPE_APPEARANCE 0x19 /**< Appearance. */
-#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA 0xFF /**< Manufacturer Specific Data. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags
- * @{ */
-#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE (0x01) /**< LE Limited Discoverable Mode. */
-#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE (0x02) /**< LE General Discoverable Mode. */
-#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED (0x04) /**< BR/EDR not supported. */
-#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER (0x08) /**< Simultaneous LE and BR/EDR, Controller. */
-#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST (0x10) /**< Simultaneous LE and BR/EDR, Host. */
-#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE Limited Discoverable Mode, BR/EDR not supported. */
-#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE General Discoverable Mode, BR/EDR not supported. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min
- * @{ */
-#define BLE_GAP_ADV_INTERVAL_MIN 0x0020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */
-#define BLE_GAP_ADV_NONCON_INTERVAL_MIN 0x00A0 /**< Minimum Advertising interval in 625 us units for non connectable mode, i.e. 100 ms. */
-#define BLE_GAP_ADV_INTERVAL_MAX 0x4000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */
- /** @} */
-
-
-/** @defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min
- * @{ */
-#define BLE_GAP_SCAN_INTERVAL_MIN 0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */
-#define BLE_GAP_SCAN_INTERVAL_MAX 0x4000 /**< Maximum Scan interval in 625 us units, i.e. 10.24 s. */
- /** @} */
-
-
-/** @defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min
- * @{ */
-#define BLE_GAP_SCAN_WINDOW_MIN 0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */
-#define BLE_GAP_SCAN_WINDOW_MAX 0x4000 /**< Maximum Scan window in 625 us units, i.e. 10.24 s. */
- /** @} */
-
-
-/** @defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min
- * @{ */
-#define BLE_GAP_SCAN_TIMEOUT_MIN 0x0001 /**< Minimum Scan timeout in seconds. */
-#define BLE_GAP_SCAN_TIMEOUT_MAX 0xFFFF /**< Maximum Scan timeout in seconds. */
- /** @} */
-
-
-/** @brief Maximum size of advertising data in octets. */
-#define BLE_GAP_ADV_MAX_SIZE 31
-
-
-/** @defgroup BLE_GAP_ADV_TYPES GAP Advertising types
- * @{ */
-#define BLE_GAP_ADV_TYPE_ADV_IND 0x00 /**< Connectable undirected. */
-#define BLE_GAP_ADV_TYPE_ADV_DIRECT_IND 0x01 /**< Connectable directed. */
-#define BLE_GAP_ADV_TYPE_ADV_SCAN_IND 0x02 /**< Scannable undirected. */
-#define BLE_GAP_ADV_TYPE_ADV_NONCONN_IND 0x03 /**< Non connectable undirected. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies
- * @{ */
-#define BLE_GAP_ADV_FP_ANY 0x00 /**< Allow scan requests and connect requests from any device. */
-#define BLE_GAP_ADV_FP_FILTER_SCANREQ 0x01 /**< Filter scan requests with whitelist. */
-#define BLE_GAP_ADV_FP_FILTER_CONNREQ 0x02 /**< Filter connect requests with whitelist. */
-#define BLE_GAP_ADV_FP_FILTER_BOTH 0x03 /**< Filter both scan and connect requests with whitelist. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values
- * @{ */
-#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX 180 /**< Maximum advertising time in limited discoverable mode (TGAP(lim_adv_timeout) = 180s in spec (Addendum 2)). */
-#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED 0 /**< Unlimited advertising in general discoverable mode. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_DISC_MODES GAP Discovery modes
- * @{ */
-#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE 0x00 /**< Not discoverable discovery Mode. */
-#define BLE_GAP_DISC_MODE_LIMITED 0x01 /**< Limited Discovery Mode. */
-#define BLE_GAP_DISC_MODE_GENERAL 0x02 /**< General Discovery Mode. */
-/** @} */
-
-/** @defgroup BLE_GAP_IO_CAPS GAP IO Capabilities
- * @{ */
-#define BLE_GAP_IO_CAPS_DISPLAY_ONLY 0x00 /**< Display Only. */
-#define BLE_GAP_IO_CAPS_DISPLAY_YESNO 0x01 /**< Display and Yes/No entry. */
-#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY 0x02 /**< Keyboard Only. */
-#define BLE_GAP_IO_CAPS_NONE 0x03 /**< No I/O capabilities. */
-#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY 0x04 /**< Keyboard and Display. */
-/** @} */
-
-
-/** @defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types
- * @{ */
-#define BLE_GAP_AUTH_KEY_TYPE_NONE 0x00 /**< No key (may be used to reject). */
-#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY 0x01 /**< 6-digit Passkey. */
-#define BLE_GAP_AUTH_KEY_TYPE_OOB 0x02 /**< Out Of Band data. */
-/** @} */
-
-/** @defgroup BLE_GAP_SEC_STATUS GAP Security status
- * @{ */
-#define BLE_GAP_SEC_STATUS_SUCCESS 0x00 /**< Procedure completed with success. */
-#define BLE_GAP_SEC_STATUS_TIMEOUT 0x01 /**< Procedure timed out. */
-#define BLE_GAP_SEC_STATUS_PDU_INVALID 0x02 /**< Invalid PDU received. */
-#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED 0x81 /**< Passkey entry failed (user cancelled or other). */
-#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE 0x82 /**< Out of Band Key not available. */
-#define BLE_GAP_SEC_STATUS_AUTH_REQ 0x83 /**< Authentication requirements not met. */
-#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE 0x84 /**< Confirm value failed. */
-#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP 0x85 /**< Pairing not supported. */
-#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE 0x86 /**< Encryption key size. */
-#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED 0x87 /**< Unsupported SMP command. */
-#define BLE_GAP_SEC_STATUS_UNSPECIFIED 0x88 /**< Unspecified reason. */
-#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS 0x89 /**< Too little time elapsed since last attempt. */
-#define BLE_GAP_SEC_STATUS_INVALID_PARAMS 0x8A /**< Invalid parameters. */
-/** @} */
-
-/** @defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources
- * @{ */
-#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL 0x00 /**< Local failure. */
-#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE 0x01 /**< Remote failure. */
-/** @} */
-
-/** @defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits
- * @{ */
-#define BLE_GAP_CP_MIN_CONN_INTVL_NONE 0xFFFF /**< No new minimum connction interval specified in connect parameters. */
-#define BLE_GAP_CP_MIN_CONN_INTVL_MIN 0x0006 /**< Lowest mimimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
-#define BLE_GAP_CP_MIN_CONN_INTVL_MAX 0x0C80 /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
-#define BLE_GAP_CP_MAX_CONN_INTVL_NONE 0xFFFF /**< No new maximum connction interval specified in connect parameters. */
-#define BLE_GAP_CP_MAX_CONN_INTVL_MIN 0x0006 /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
-#define BLE_GAP_CP_MAX_CONN_INTVL_MAX 0x0C80 /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
-#define BLE_GAP_CP_SLAVE_LATENCY_MAX 0x03E8 /**< Highest slave latency permitted, in connection events. */
-#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE 0xFFFF /**< No new supervision timeout specified in connect parameters. */
-#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN 0x000A /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */
-#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX 0x0C80 /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */
-/** @} */
-
-
-/**@brief GAP device name maximum writable length. */
-#define BLE_GAP_DEVNAME_MAX_WR_LEN 20
-
-/**@brief GAP device name maximum length. */
-#define BLE_GAP_DEVNAME_MAX_LEN 31
-
-
-/** @defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters
- *
- * See @ref ble_gap_conn_sec_mode_t.
- * @{ */
-/** @brief Set sec_mode pointed to by ptr to have no access rights.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0)
-/** @brief Set sec_mode pointed to by ptr to require no protection, open link.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0)
-/** @brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0)
-/** @brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0)
-/** @brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0)
-/** @brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0)
-/** @} */
-
-
-/**@brief GAP Security Random Number Length. */
-#define BLE_GAP_SEC_RAND_LEN 8
-
-/**@brief GAP Security Key Length. */
-#define BLE_GAP_SEC_KEY_LEN 16
-
-/**@brief Maximum amount of addresses in a whitelist. */
-#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8)
-
-/**@brief Maximum amount of IRKs in a whitelist.
- * @note The number of IRKs is limited to 8, even if the hardware supports more.
- */
-#define BLE_GAP_WHITELIST_IRK_MAX_COUNT (8)
-
-/** @defgroup GAP_SEC_MODES GAP Security Modes
- * @{ */
-#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */
-/** @} */
-
-/** @} */
-
-/** @addtogroup BLE_GAP_STRUCTURES Structures
- * @{ */
-
-/**@brief Bluetooth Low Energy address. */
-typedef struct
-{
- uint8_t addr_type; /**< See @ref BLE_GAP_ADDR_TYPES. */
- uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. */
-} ble_gap_addr_t;
-
-
-/**@brief GAP connection parameters. */
-typedef struct
-{
- uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
- uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
- uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/
- uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/
-} ble_gap_conn_params_t;
-
-
-/**@brief GAP link requirements.
- *
- * See Bluetooth Core specification, Volume 3 Part C 10.2 for details.
- *
- * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n
- * Security Mode 1 Level 1: No security is needed (aka open link).\n
- * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n
- * Security Mode 1 Level 3: MITM protected encrypted link required.\n
- * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n
- * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n
- */
-typedef struct
-{
- uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */
- uint8_t lv : 4; /**< Level (1, 2 or 3), 0 for no permissions at all. */
-
-} ble_gap_conn_sec_mode_t;
-
-
-
-/**@brief GAP connection security status.*/
-typedef struct
-{
- ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/
- uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets.*/
-} ble_gap_conn_sec_t;
-
-
-
-/**@brief Identity Resolving Key. */
-typedef struct
-{
- uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */
-} ble_gap_irk_t;
-
-
-/**@brief White list structure. */
-typedef struct
-{
- ble_gap_addr_t ** pp_addrs; /**< Pointer to array of device address pointers, pointing to addresses to be used in whitelist. NULL if none are given. */
- uint8_t addr_count; /**< Count of device addresses in array, up to @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. */
- ble_gap_irk_t ** pp_irks; /**< Pointer to array of Identity Resolving Key (IRK) pointers, each pointing to an IRK in the whitelist. NULL if none are given. */
- uint8_t irk_count; /**< Count of IRKs in array, up to @ref BLE_GAP_WHITELIST_IRK_MAX_COUNT. */
-} ble_gap_whitelist_t;
-
-
-/**@brief GAP advertising parameters.*/
-typedef struct
-{
- uint8_t type; /**< See @ref BLE_GAP_ADV_TYPES. */
- ble_gap_addr_t* p_peer_addr; /**< For BLE_GAP_CONN_MODE_DIRECTED mode only, known peer address. */
- uint8_t fp; /**< Filter Policy, see @ref BLE_GAP_ADV_FILTER_POLICIES. */
- ble_gap_whitelist_t * p_whitelist; /**< Pointer to whitelist, NULL if none is given. */
- uint16_t interval; /**< Advertising interval between 0x0020 and 0x4000 in 0.625 ms units (20ms to 10.24s), see @ref BLE_GAP_ADV_INTERVALS. This parameter must be set to 0 if type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND. */
- uint16_t timeout; /**< Advertising timeout between 0x0001 and 0x3FFF in seconds, 0x0000 disables timeout. See also @ref BLE_GAP_ADV_TIMEOUT_VALUES. This parameter must be set to 0 if type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND. */
-} ble_gap_adv_params_t;
-
-
-/**@brief GAP scanning parameters. */
-typedef struct
-{
- uint8_t active : 1; /**< If 1, perform active scanning (scan requests). */
- uint8_t selective : 1; /**< If 1, ignore unknown devices (non white listed). */
- ble_gap_whitelist_t * p_whitelist; /**< Pointer to whitelist, NULL if none is given. */
- uint16_t interval; /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
- uint16_t window; /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
- uint16_t timeout; /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */
-} ble_gap_scan_params_t;
-
-
-/** @brief Keys that can be exchanged. */
-typedef struct
-{
- uint8_t enc : 1; /**< Long Term Key and Master Identification. */
- uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */
- uint8_t sign : 1; /**< Connection Signature Resolving Key. */
-} ble_gap_sec_kdist_t;
-
-
-/**@brief GAP security parameters. */
-typedef struct
-{
- uint8_t bond : 1; /**< Perform bonding. */
- uint8_t mitm : 1; /**< Man In The Middle protection required. */
- uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */
- uint8_t oob : 1; /**< Out Of Band data available. */
- uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. */
- uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */
- ble_gap_sec_kdist_t kdist_periph; /**< Key distribution bitmap: keys that the peripheral device will distribute. */
- ble_gap_sec_kdist_t kdist_central; /**< Key distribution bitmap: keys that the central device will distribute. */
-} ble_gap_sec_params_t;
-
-
-/**@brief GAP Encryption Information. */
-typedef struct
-{
- uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */
- uint8_t auth : 1; /**< Authenticated Key. */
- uint8_t ltk_len : 7; /**< LTK length in octets. */
-} ble_gap_enc_info_t;
-
-
-/**@brief GAP Master Identification. */
-typedef struct
-{
- uint16_t ediv; /**< Encrypted Diversifier. */
- uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */
-} ble_gap_master_id_t;
-
-
-/**@brief GAP Signing Information. */
-typedef struct
-{
- uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */
-} ble_gap_sign_info_t;
-
-
-/** @brief Event data for connected event. */
-typedef struct
-{
- ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */
- uint8_t irk_match :1; /**< If 1, peer device's address resolved using an IRK. */
- uint8_t irk_match_idx :7; /**< Index in IRK list where the address was matched. */
- ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */
-} ble_gap_evt_connected_t;
-
-
-/** @brief Event data for disconnected event. */
-typedef struct
-{
- ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */
- uint8_t reason; /**< HCI error code. */
-} ble_gap_evt_disconnected_t;
-
-
-/** @brief Event data for connection parameter update event. */
-typedef struct
-{
- ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */
-} ble_gap_evt_conn_param_update_t;
-
-
-/** @brief Event data for security parameters request event. */
-typedef struct
-{
- ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */
-} ble_gap_evt_sec_params_request_t;
-
-
-/** @brief Event data for security info request event. */
-typedef struct
-{
- ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */
- ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */
- uint8_t enc_info : 1; /**< If 1, Encryption Information required. */
- uint8_t id_info : 1; /**< If 1, Identity Information required. */
- uint8_t sign_info : 1; /**< If 1, Signing Information required. */
-} ble_gap_evt_sec_info_request_t;
-
-
-/** @brief Event data for passkey display event. */
-typedef struct
-{
- uint8_t passkey[6]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */
-} ble_gap_evt_passkey_display_t;
-
-
-/** @brief Event data for authentication key request event. */
-typedef struct
-{
- uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */
-} ble_gap_evt_auth_key_request_t;
-
-
-/** @brief Security levels supported.
- * @note See Bluetooth Specification Version 4.0 Volume 3, Chapter 10.
-*/
-typedef struct
-{
- uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */
- uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */
- uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */
-} ble_gap_sec_levels_t;
-
-
-/** @brief Encryption Key. */
-typedef struct
-{
- ble_gap_enc_info_t enc_info; /**< Encryption Information. */
- ble_gap_master_id_t master_id; /**< Master Identification. */
-} ble_gap_enc_key_t;
-
-
-/** @brief Identity Key. */
-typedef struct
-{
- ble_gap_irk_t id_info; /**< Identity Information. */
- ble_gap_addr_t id_addr_info; /**< Identity Address Information. */
-} ble_gap_id_key_t;
-
-
-/** @brief Security Keys. */
-typedef struct
-{
- ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */
- ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */
- ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */
-} ble_gap_sec_keys_t;
-
-
-/** @brief Security key set (both Peripheral and Central keys).
- * Note that when distributing Bluetooth addresses pertaining to the local device those
- * will have to be filled in by the user. */
-typedef struct
-{
- ble_gap_sec_keys_t keys_periph; /**< Keys distributed by the device in the Peripheral role. */
- ble_gap_sec_keys_t keys_central; /**< Keys distributed by the device in the Central role. */
-} ble_gap_sec_keyset_t;
-
-
-/** @brief Event data for authentication status event. */
-typedef struct
-{
- uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */
- uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
- uint8_t bonded : 1; /**< Procedure resulted in a bond. */
- ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */
- ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */
- ble_gap_sec_kdist_t kdist_periph; /**< Bitmap stating which keys were exchanged (distributed) by the peripheral. */
- ble_gap_sec_kdist_t kdist_central; /**< Bitmap stating which keys were exchanged (distributed) by the central. */
-} ble_gap_evt_auth_status_t;
-
-
-/** @brief Event data for connection security update event. */
-typedef struct
-{
- ble_gap_conn_sec_t conn_sec; /**< Connection security level. */
-} ble_gap_evt_conn_sec_update_t;
-
-
-/** @brief Event data for timeout event. */
-typedef struct
-{
- uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */
-} ble_gap_evt_timeout_t;
-
-
-/** @brief Event data for advertisement report event. */
-typedef struct
-{
- int8_t rssi; /**< Received Signal Strength Indication in dBm. */
-} ble_gap_evt_rssi_changed_t;
-
-
-/** @brief Event data for advertisement report event. */
-typedef struct
-{
- ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */
- int8_t rssi; /**< Received Signal Strength Indication in dBm. */
- uint8_t scan_rsp : 1; /**< If 1, the report corresponds to a scan response and the type field may be ignored. */
- uint8_t type : 2; /**< See @ref BLE_GAP_ADV_TYPES. Only valid if the scan_rsp field is 0. */
- uint8_t dlen : 5; /**< Advertisement or scan response data length. */
- uint8_t data[BLE_GAP_ADV_MAX_SIZE]; /**< Advertisement or scan response data. */
-} ble_gap_evt_adv_report_t;
-
-/** @brief Event data for security request event. */
-typedef struct
-{
- uint8_t bond : 1; /**< Perform bonding. */
- uint8_t mitm : 1; /**< Man In The Middle protection required. */
-} ble_gap_evt_sec_request_t;
-
-/** @brief Event data for connection parameter update request event. */
-typedef struct
-{
- ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */
-} ble_gap_evt_conn_param_update_request_t;
-
-/**@brief GAP event callback event structure. */
-typedef struct
-{
- uint16_t conn_handle; /**< Connection Handle on which event occured. */
- union /**< union alternative identified by evt_id in enclosing struct. */
- {
- ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */
- ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */
- ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */
- ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */
- ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */
- ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */
- ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */
- ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */
- ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */
- ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */
- ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event parameters. */
- ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */
- ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */
- ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */
- } params; /**< Event Parameters. */
-
-} ble_gap_evt_t;
-
-/** @} */
-
-
-/** @addtogroup BLE_GAP_FUNCTIONS Functions
- * @{ */
-
-/**@brief Set local Bluetooth address.
- *
- * @param[in] p_addr Pointer to address structure.
- *
- * @retval ::NRF_SUCCESS Address successfully set.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address.
- */
-SVCALL(SD_BLE_GAP_ADDRESS_SET, uint32_t, sd_ble_gap_address_set(ble_gap_addr_t const * const p_addr));
-
-
-/**@brief Get local Bluetooth address.
- *
- * @param[out] p_addr Pointer to address structure.
- *
- * @retval ::NRF_SUCCESS Address successfully retrieved.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- */
-SVCALL(SD_BLE_GAP_ADDRESS_GET, uint32_t, sd_ble_gap_address_get(ble_gap_addr_t * const p_addr));
-
-
-/**@brief Set, clear or update advertisement and scan response data.
- *
- * @note The format of the advertisement data will be checked by this call to ensure interoperability.
- * Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and
- * duplicating the local name in the advertisement data and scan response data.
- *
- * @note: To clear the advertisement data and set it to a 0-length packet, simply provide a valid pointer (p_data/p_sr_data) with its corresponding
- * length (dlen/srdlen) set to 0.
- *
- * @note: The call will fail if p_data and p_sr_data are both NULL since this would have no effect.
- *
- * @param[in] p_data Raw data to be placed in advertisement packet. If NULL, no changes are made to the current advertisement packet data.
- * @param[in] dlen Data length for p_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_data is NULL, can be 0 if p_data is not NULL.
- * @param[in] p_sr_data Raw data to be placed in scan response packet. If NULL, no changes are made to the current scan response packet data.
- * @param[in] srdlen Data length for p_sr_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_sr_data is NULL, can be 0 if p_data is not NULL.
- *
- * @retval ::NRF_SUCCESS Advertisement data successfully updated or cleared.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied.
- * @retval ::NRF_ERROR_INVALID_DATA Invalid data type(s) supplied, check the advertising data format specification.
- * @retval ::NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied.
- * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied.
- */
-SVCALL(SD_BLE_GAP_ADV_DATA_SET, uint32_t, sd_ble_gap_adv_data_set(uint8_t const * const p_data, uint8_t dlen, uint8_t const * const p_sr_data, uint8_t srdlen));
-
-
-/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
- *
- * @param[in] p_adv_params Pointer to advertising parameters structure.
- *
- * @retval ::NRF_SUCCESS The BLE stack has started advertising.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check the accepted ranges and limits.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Bluetooth address supplied.
- * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible.
- * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
- */
-SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(ble_gap_adv_params_t const * const p_adv_params));
-
-
-/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
- *
- * @retval ::NRF_SUCCESS The BLE stack has stopped advertising.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in advertising state).
- */
-SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(void));
-
-
-/**@brief Update connection parameters.
- *
- * @details In the central role this will initiate a Link Layer connection parameter update procedure,
- * otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for
- * the central to perform the procedure. In both cases, and regardless of success or failure, the application
- * will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event.
- *
- * @details This function can be used both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested.
- *
- * @note If both a connection supervision timeout and a maximum connection interval are specified, then the following constraint
- * applies: (conn_sup_timeout * 8) >= (max_conn_interval * (slave_latency + 1))
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_conn_params Pointer to desired connection parameters. If NULL is provided on a peripheral role,
- * the parameters in the PPCP characteristic of the GAP service will be used instead.
- * If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected
- *
- * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
- * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, process pending events and retry.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- */
-SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const * const p_conn_params));
-
-
-/**@brief Disconnect (GAP Link Termination).
- *
- * @details This call initiates the disconnection procedure, and its completion will be communicated to the application
- * with a BLE_GAP_EVT_DISCONNECTED event.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES.
- *
- * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (disconnection is already in progress or not connected at all).
- */
-SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code));
-
-
-/**@brief Set the radio's transmit power.
- *
- * @param[in] tx_power Radio transmit power in dBm (accepted values are -40, -30, -20, -16, -12, -8, -4, 0, and 4 dBm).
- *
- * @note -40 dBm will not actually give -40 dBm, but will instead be remapped to -30 dBm.
- *
- * @retval ::NRF_SUCCESS Successfully changed the transmit power.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- */
-SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(int8_t tx_power));
-
-
-/**@brief Set GAP Appearance value.
- *
- * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES.
- *
- * @retval ::NRF_SUCCESS Appearance value set successfully.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- */
-SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance));
-
-
-/**@brief Get GAP Appearance value.
- *
- * @param[out] p_appearance Appearance (16-bit), see @ref BLE_APPEARANCES.
- *
- * @retval ::NRF_SUCCESS Appearance value retrieved successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- */
-SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t * const p_appearance));
-
-
-/**@brief Set GAP Peripheral Preferred Connection Parameters.
- *
- * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters.
- *
- * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- */
-SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const * const p_conn_params));
-
-
-/**@brief Get GAP Peripheral Preferred Connection Parameters.
- *
- * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored.
- *
- * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- */
-SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t * const p_conn_params));
-
-
-/**@brief Set GAP device name.
- *
- * @param[in] p_write_perm Write permissions for the Device Name characteristic see @ref ble_gap_conn_sec_mode_t.
- * @param[in] p_dev_name Pointer to a UTF-8 encoded, <b>non NULL-terminated</b> string.
- * @param[in] len Length of the UTF-8, <b>non NULL-terminated</b> string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN).
- *
- * @retval ::NRF_SUCCESS GAP device name and permissions set successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
- */
-SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const * const p_write_perm, uint8_t const * const p_dev_name, uint16_t len));
-
-
-/**@brief Get GAP device name.
- *
- * @param[out] p_dev_name Pointer to an empty buffer where the UTF-8 <b>non NULL-terminated</b> string will be placed.
- * @param[in,out] p_len Length of the buffer pointed by p_dev_name, bytes returned on output.
- *
- * @retval ::NRF_SUCCESS GAP device name retrieved successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
- */
-SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t * const p_dev_name, uint16_t * const p_len));
-
-
-/**@brief Initiate GAP Authentication procedure.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing procedure.
- * In the peripheral role, only the timeout, bond and mitm fields of this structure are used.
- *
- * @details In the central role, this function will send an SMP Pairing Request, otherwise in the peripheral role, an SMP Security Request will be sent.
- *
- * @note Calling this function may result in the following events depending on the outcome and parameters: @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST,
- * @ref BLE_GAP_EVT_SEC_INFO_REQUEST, @ref BLE_GAP_EVT_AUTH_KEY_REQUEST, @ref BLE_GAP_EVT_AUTH_STATUS.
- *
- *
- * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const * const p_sec_params));
-
-
-/**@brief Reply with GAP security parameters.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS.
- * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. As a central this must be set to NULL, as the parameters have
- * already been provided during a previous call to @ref sd_ble_gap_authenticate.
- * @param[in] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys distributed as a result of the ongoing security procedure
- * will be stored into the memory referenced inside this structure. Bluetooth addresses distributed by the local device constitute an
- * exception, since those will have to be filled in by the user before calling this function.
- * A NULL pointer will result in the keys not being stored at all.
- *
- * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an NRF_ERROR_INVALID_STATE.
- * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
- *
- * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const * const p_sec_params, ble_gap_sec_keyset_t const * const p_sec_keyset));
-
-
-/**@brief Reply with an authentication key.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES.
- * @param[in] key If key type is BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL.
- * If key type is BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination).
- * If key type is BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in Little Endian format.
- *
- * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST, calling it at other times will result in an NRF_ERROR_INVALID_STATE.
- * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
- *
- * @retval ::NRF_SUCCESS Authentication key successfully set.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const * const key));
-
-
-/**@brief Initiate GAP Encryption procedure.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure.
- * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure.
- *
- * @details In the central role, this function will initiate the encryption procedure using the encryption information provided.
- *
- * @note Calling this function may result in the following event depending on the outcome and parameters: @ref BLE_GAP_EVT_CONN_SEC_UPDATE.
- *
- * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in Slave role.
- */
-SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const * const p_master_id, ble_gap_enc_info_t const * const p_enc_info));
-
-
-/**@brief Reply with GAP security information.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available.
- * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available.
- * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available.
- *
- * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in NRF_ERROR_INVALID_STATE.
- * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
- * @note Data signing is not implemented yet. p_sign_info must therefore be NULL.
- *
- * @retval ::NRF_SUCCESS Successfully accepted security information.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const * const p_enc_info, ble_gap_irk_t const * const p_id_info, ble_gap_sign_info_t const * const p_sign_info));
-
-
-/**@brief Get the current connection security.
- *
- * @param[in] conn_handle Connection handle.
- * @param[out] p_conn_sec Pointer to a @ref ble_gap_conn_sec_t structure to be filled in.
- *
- * @retval ::NRF_SUCCESS Current connection security successfully retrieved.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t * const p_conn_sec));
-
-
-/**@brief Start reporting the received signal strength to the application.
- *
- * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called.
- *
- * @param[in] conn_handle Connection handle.
- *
- * @retval ::NRF_SUCCESS Successfully activated RSSI reporting.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle));
-
-
-/**@brief Stop reporting the received singnal strength.
- *
- * An RSSI change detected before the call but not yet received by the application
- * may be reported after @ref sd_ble_gap_rssi_stop has been called.
- *
- * @param[in] conn_handle Connection handle.
- *
- * @retval ::NRF_SUCCESS Successfully deactivated RSSI reporting.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle));
-
-/**@brief Start scanning (GAP Discovery procedure, Observer Procedure).
- *
- * @param[in] p_scan_params Pointer to scan parameters structure.
- * @retval ::NRF_SUCCESS Successfully initiated scanning procedure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
- * @retval ::NRF_ERROR_NOT_SUPPORTED A selected feature is not supported (selective scanning).
- */
-SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const * const p_scan_params));
-
-
-/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure).
- *
- * @retval ::NRF_SUCCESS Successfully stopped scanning procedure.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in scanning state).
- */
-SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void));
-
-
-/**@brief Create a connection (GAP Link Establishment).
- *
- * @param[in] p_peer_addr Pointer to peer address. If the selective bit is set in @ref ble_gap_scan_params_t, then this must be NULL.
- * @param[in] p_scan_params Pointer to scan parameters structure.
- * @param[in] p_conn_params Pointer to desired connection parameters.
- *
- * @retval ::NRF_SUCCESS Successfully initiated connection procedure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address.
- * @retval ::NRF_ERROR_NO_MEM limit of available connections reached.
- * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
-*/
-SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const * const p_peer_addr, ble_gap_scan_params_t const * const p_scan_params, ble_gap_conn_params_t const * const p_conn_params));
-
-
-/**@brief Cancel a connection establishment.
- *
- * @retval ::NRF_SUCCESS Successfully cancelled an inprogress connection procedure.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- */
-SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void));
-
-/** @} */
-
-#endif // BLE_GAP_H__
-
-/**
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_gatt.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,165 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
- /**
- @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common
- @{
- @brief Common definitions and prototypes for the GATT interfaces.
- */
-
-#ifndef BLE_GATT_H__
-#define BLE_GATT_H__
-
-#include "ble_types.h"
-#include "ble_ranges.h"
-
-
-/** @addtogroup BLE_GATT_DEFINES Defines
- * @{ */
-
-/** @brief Default MTU size. */
-#define GATT_MTU_SIZE_DEFAULT 23
-
-/** @brief Only the default MTU size of 23 is currently supported. */
-#define GATT_RX_MTU 23
-
-
-/**@brief Invalid Attribute Handle. */
-#define BLE_GATT_HANDLE_INVALID 0x0000
-
-/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources
- * @{ */
-#define BLE_GATT_TIMEOUT_SRC_PROTOCOL 0x00 /**< ATT Protocol timeout. */
-/** @} */
-
-/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations
- * @{ */
-#define BLE_GATT_OP_INVALID 0x00 /**< Invalid Operation. */
-#define BLE_GATT_OP_WRITE_REQ 0x01 /**< Write Request. */
-#define BLE_GATT_OP_WRITE_CMD 0x02 /**< Write Command. */
-#define BLE_GATT_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */
-#define BLE_GATT_OP_PREPARE_WRITE_REQ 0x04 /**< Prepare Write Request. */
-#define BLE_GATT_OP_EXECUTE_WRITE_REQ 0x05 /**< Execute Write Request. */
-/** @} */
-
-/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations
- * @{ */
-#define BLE_GATT_HVX_INVALID 0x00 /**< Invalid Operation. */
-#define BLE_GATT_HVX_NOTIFICATION 0x01 /**< Handle Value Notification. */
-#define BLE_GATT_HVX_INDICATION 0x02 /**< Handle Value Indication. */
-/** @} */
-
-/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes
- * @{ */
-#define BLE_GATT_STATUS_SUCCESS 0x0000 /**< Success. */
-#define BLE_GATT_STATUS_UNKNOWN 0x0001 /**< Unknown or not applicable status. */
-#define BLE_GATT_STATUS_ATTERR_INVALID 0x0100 /**< ATT Error: Invalid Error Code. */
-#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE 0x0101 /**< ATT Error: Invalid Attribute Handle. */
-#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED 0x0102 /**< ATT Error: Read not permitted. */
-#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED 0x0103 /**< ATT Error: Write not permitted. */
-#define BLE_GATT_STATUS_ATTERR_INVALID_PDU 0x0104 /**< ATT Error: Used in ATT as Invalid PDU. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION 0x0105 /**< ATT Error: Authenticated link required. */
-#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED 0x0106 /**< ATT Error: Used in ATT as Request Not Supported. */
-#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET 0x0107 /**< ATT Error: Offset specified was past the end of the attribute. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION 0x0108 /**< ATT Error: Used in ATT as Insufficient Authorisation. */
-#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL 0x0109 /**< ATT Error: Used in ATT as Prepare Queue Full. */
-#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND 0x010A /**< ATT Error: Used in ATT as Attribute not found. */
-#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG 0x010B /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE 0x010C /**< ATT Error: Encryption key size used is insufficient. */
-#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH 0x010D /**< ATT Error: Invalid value size. */
-#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR 0x010E /**< ATT Error: Very unlikely error. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION 0x010F /**< ATT Error: Encrypted link required. */
-#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE 0x0110 /**< ATT Error: Attribute type is not a supported grouping attribute. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES 0x0111 /**< ATT Error: Encrypted link required. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN 0x0112 /**< ATT Error: Reserved for Future Use range #1 begin. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END 0x017F /**< ATT Error: Reserved for Future Use range #1 end. */
-#define BLE_GATT_STATUS_ATTERR_APP_BEGIN 0x0180 /**< ATT Error: Application range begin. */
-#define BLE_GATT_STATUS_ATTERR_APP_END 0x019F /**< ATT Error: Application range end. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN 0x01A0 /**< ATT Error: Reserved for Future Use range #2 begin. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END 0x01DF /**< ATT Error: Reserved for Future Use range #2 end. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN 0x01E0 /**< ATT Error: Reserved for Future Use range #3 begin. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END 0x01FC /**< ATT Error: Reserved for Future Use range #3 end. */
-#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR 0x01FD /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */
-#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG 0x01FE /**< ATT Common Profile and Service Error: Procedure Already in Progress. */
-#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE 0x01FF /**< ATT Common Profile and Service Error: Out Of Range. */
-/** @} */
-
-
-/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats
- * @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml
- * @{ */
-#define BLE_GATT_CPF_FORMAT_RFU 0x00 /**< Reserved For Future Use. */
-#define BLE_GATT_CPF_FORMAT_BOOLEAN 0x01 /**< Boolean. */
-#define BLE_GATT_CPF_FORMAT_2BIT 0x02 /**< Unsigned 2-bit integer. */
-#define BLE_GATT_CPF_FORMAT_NIBBLE 0x03 /**< Unsigned 4-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT8 0x04 /**< Unsigned 8-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT12 0x05 /**< Unsigned 12-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT16 0x06 /**< Unsigned 16-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT24 0x07 /**< Unsigned 24-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT32 0x08 /**< Unsigned 32-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT48 0x09 /**< Unsigned 48-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT64 0x0A /**< Unsigned 64-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT128 0x0B /**< Unsigned 128-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT8 0x0C /**< Signed 2-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT12 0x0D /**< Signed 12-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT16 0x0E /**< Signed 16-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT24 0x0F /**< Signed 24-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT32 0x10 /**< Signed 32-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT48 0x11 /**< Signed 48-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT64 0x12 /**< Signed 64-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT128 0x13 /**< Signed 128-bit integer. */
-#define BLE_GATT_CPF_FORMAT_FLOAT32 0x14 /**< IEEE-754 32-bit floating point. */
-#define BLE_GATT_CPF_FORMAT_FLOAT64 0x15 /**< IEEE-754 64-bit floating point. */
-#define BLE_GATT_CPF_FORMAT_SFLOAT 0x16 /**< IEEE-11073 16-bit SFLOAT. */
-#define BLE_GATT_CPF_FORMAT_FLOAT 0x17 /**< IEEE-11073 32-bit FLOAT. */
-#define BLE_GATT_CPF_FORMAT_DUINT16 0x18 /**< IEEE-20601 format. */
-#define BLE_GATT_CPF_FORMAT_UTF8S 0x19 /**< UTF-8 string. */
-#define BLE_GATT_CPF_FORMAT_UTF16S 0x1A /**< UTF-16 string. */
-#define BLE_GATT_CPF_FORMAT_STRUCT 0x1B /**< Opaque Structure. */
-/** @} */
-
-/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces
- * @{
- */
-#define BLE_GATT_CPF_NAMESPACE_BTSIG 0x01 /**< Bluetooth SIG defined Namespace. */
-#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */
-/** @} */
-
-/** @} */
-
-/** @addtogroup BLE_GATT_STRUCTURES Structures
- * @{ */
-
-/**@brief GATT Characteristic Properties. */
-typedef struct
-{
- /* Standard properties */
- uint8_t broadcast :1; /**< Broadcasting of value permitted. */
- uint8_t read :1; /**< Reading value permitted. */
- uint8_t write_wo_resp :1; /**< Writing value with Write Command permitted. */
- uint8_t write :1; /**< Writing value with Write Request permitted. */
- uint8_t notify :1; /**< Notications of value permitted. */
- uint8_t indicate :1; /**< Indications of value permitted. */
- uint8_t auth_signed_wr :1; /**< Writing value with Signed Write Command permitted. */
-} ble_gatt_char_props_t;
-
-/**@brief GATT Characteristic Extended Properties. */
-typedef struct
-{
- /* Extended properties */
- uint8_t reliable_wr :1; /**< Writing value with Queued Write Request permitted. */
- uint8_t wr_aux :1; /**< Writing the Characteristic User Description permitted. */
-} ble_gatt_char_ext_props_t;
-
-#endif // BLE_GATT_H__
-
-/** @} */
-
-/**
- @}
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_gattc.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,401 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-/**
- @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client
- @{
- @brief Definitions and prototypes for the GATT Client interface.
- */
-
-#ifndef BLE_GATTC_H__
-#define BLE_GATTC_H__
-
-#include "ble_gatt.h"
-#include "ble_types.h"
-#include "ble_ranges.h"
-#include "nrf_svc.h"
-
-/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations
- * @{ */
-
-/**@brief GATTC API SVC numbers. */
-enum BLE_GATTC_SVCS
-{
- SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */
- SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */
- SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */
- SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */
- SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */
- SD_BLE_GATTC_READ, /**< Generic read. */
- SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */
- SD_BLE_GATTC_WRITE, /**< Generic write. */
- SD_BLE_GATTC_HV_CONFIRM /**< Handle Value Confirmation. */
-};
-
-/**
- * @brief GATT Client Event IDs.
- */
-enum BLE_GATTC_EVTS
-{
- BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. */
- BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. */
- BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. */
- BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. */
- BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. */
- BLE_GATTC_EVT_READ_RSP, /**< Read Response event. */
- BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. */
- BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. */
- BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. */
- BLE_GATTC_EVT_TIMEOUT /**< Timeout event. */
-};
-
-/** @} */
-
-/** @addtogroup BLE_GATTC_DEFINES Defines
- * @{ */
-
-/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC
- * @{ */
-#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */
-/** @} */
-
-/**@brief Last Attribute Handle. */
-#define BLE_GATTC_HANDLE_END 0xFFFF
-
-/** @} */
-
-/** @addtogroup BLE_GATTC_STRUCTURES Structures
- * @{ */
-
-typedef struct
-{
- uint16_t start_handle; /**< Start Handle. */
- uint16_t end_handle; /**< End Handle. */
-} ble_gattc_handle_range_t;
-
-
-/**@brief GATT service. */
-typedef struct
-{
- ble_uuid_t uuid; /**< Service UUID. */
- ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */
-} ble_gattc_service_t;
-
-
-/**@brief GATT include. */
-typedef struct
-{
- uint16_t handle; /**< Include Handle. */
- ble_gattc_service_t included_srvc; /**< Handle of the included service. */
-} ble_gattc_include_t;
-
-
-/**@brief GATT characteristic. */
-typedef struct
-{
- ble_uuid_t uuid; /**< Characteristic UUID. */
- ble_gatt_char_props_t char_props; /**< Characteristic Properties. */
- uint8_t char_ext_props : 1; /**< Extended properties present. */
- uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */
- uint16_t handle_value; /**< Handle of the Characteristic Value. */
-} ble_gattc_char_t;
-
-
-/**@brief GATT descriptor. */
-typedef struct
-{
- uint16_t handle; /**< Descriptor Handle. */
- ble_uuid_t uuid; /**< Descriptor UUID. */
-} ble_gattc_desc_t;
-
-
-/**@brief Write Parameters. */
-typedef struct
-{
- uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */
- uint16_t handle; /**< Handle to the attribute to be written. */
- uint16_t offset; /**< Offset in bytes. */
- uint16_t len; /**< Length of data in bytes. */
- uint8_t* p_value; /**< Pointer to the value data. */
-} ble_gattc_write_params_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */
-typedef struct
-{
- uint16_t count; /**< Service count. */
- ble_gattc_service_t services[1]; /**< Service data, variable length. */
-} ble_gattc_evt_prim_srvc_disc_rsp_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_REL_DISC_RSP. */
-typedef struct
-{
- uint16_t count; /**< Include count. */
- ble_gattc_include_t includes[1]; /**< Include data, variable length. */
-} ble_gattc_evt_rel_disc_rsp_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_CHAR_DISC_RSP. */
-typedef struct
-{
- uint16_t count; /**< Characteristic count. */
- ble_gattc_char_t chars[1]; /**< Characteristic data, variable length. */
-} ble_gattc_evt_char_disc_rsp_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_DESC_DISC_RSP. */
-typedef struct
-{
- uint16_t count; /**< Descriptor count. */
- ble_gattc_desc_t descs[1]; /**< Descriptor data, variable length. */
-} ble_gattc_evt_desc_disc_rsp_t;
-
-/**@brief GATT read by UUID handle value pair. */
-typedef struct
-{
- uint16_t handle; /**< Attribute Handle. */
- uint8_t *p_value; /**< Pointer to value, variable length (length available as value_len in ble_gattc_evt_read_by_uuid_rsp_t).
- Please note that this pointer is absolute to the memory provided by the user when retrieving the event,
- so it will effectively point to a location inside the handle_value array. */
-} ble_gattc_handle_value_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */
-typedef struct
-{
- uint16_t count; /**< Handle-Value Pair Count. */
- uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */
- ble_gattc_handle_value_t handle_value[1]; /**< Handle-Value(s) list, variable length. */
-} ble_gattc_evt_char_val_by_uuid_read_rsp_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_READ_RSP. */
-typedef struct
-{
- uint16_t handle; /**< Attribute Handle. */
- uint16_t offset; /**< Offset of the attribute data. */
- uint16_t len; /**< Attribute data length. */
- uint8_t data[1]; /**< Attribute data, variable length. */
-} ble_gattc_evt_read_rsp_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */
-typedef struct
-{
- uint16_t len; /**< Concatenated Attribute values length. */
- uint8_t values[1]; /**< Attribute values, variable length. */
-} ble_gattc_evt_char_vals_read_rsp_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_WRITE_RSP. */
-typedef struct
-{
- uint16_t handle; /**< Attribute Handle. */
- uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */
- uint16_t len; /**< Prepare write data length. */
- uint8_t data[1]; /**< Prepare write data, variable length. */
-} ble_gattc_evt_write_rsp_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_HVX. */
-typedef struct
-{
- uint16_t handle; /**< Handle to which the HVx operation applies. */
- uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
- uint16_t len; /**< Attribute data length. */
- uint8_t data[1]; /**< Attribute data, variable length. */
-} ble_gattc_evt_hvx_t;
-
-/**@brief Event structure for BLE_GATTC_EVT_TIMEOUT. */
-typedef struct
-{
- uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
-} ble_gattc_evt_timeout_t;
-
-/**@brief GATTC event type. */
-typedef struct
-{
- uint16_t conn_handle; /**< Connection Handle on which event occured. */
- uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
- union
- {
- ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */
- ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */
- ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */
- ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */
- ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */
- ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */
- ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */
- ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */
- ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */
- ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */
- } params; /**< Event Parameters */
-} ble_gattc_evt_t;
-
-/** @} */
-
-/** @addtogroup BLE_GATTC_FUNCTIONS Functions
- * @{ */
-
-/**@brief Initiate or continue a GATT Primary Service Discovery procedure.
- *
- * @details This function initiates a Primary Service discovery, starting from the supplied handle.
- * If the last service has not been reached, this must be called again with an updated start handle value to continue the search.
- *
- * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
- * type BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] start_handle Handle to start searching from.
- * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- */
-SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const * const p_srvc_uuid));
-
-
-/**@brief Initiate or continue a GATT Relationship Discovery procedure.
- *
- * @details This function initiates the Find Included Services sub-procedure. If the last included service has not been reached,
- * this must be called again with an updated handle range to continue the search.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- */
-SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * const p_handle_range));
-
-
-/**@brief Initiate or continue a GATT Characteristic Discovery procedure.
- *
- * @details This function initiates a Characteristic discovery procedure. If the last Characteristic has not been reached,
- * this must be called again with an updated handle range to continue the discovery.
- *
- * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
- * type BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- */
-SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * const p_handle_range));
-
-
-/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure.
- *
- * @details This function initiates the Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached,
- * this must be called again with an updated handle range to continue the discovery.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- */
-SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * const p_handle_range));
-
-
-/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure.
- *
- * @details This function initiates the Read using Characteristic UUID procedure. If the last Characteristic has not been reached,
- * this must be called again with an updated handle range to continue the discovery.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_uuid Pointer to a Characteristic value UUID to read.
- * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- */
-SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const * const p_uuid, ble_gattc_handle_range_t const * const p_handle_range));
-
-
-/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure.
- *
- * @details This function initiates a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor
- * to be read is longer than GATT_MTU - 1, this function must be called multiple times with appropriate offset to read the
- * complete value.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] handle The handle of the attribute to be read.
- * @param[in] offset Offset into the attribute value to be read.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- */
-SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset));
-
-
-/**@brief Initiate a GATT Read Multiple Characteristic Values procedure.
- *
- * @details This function initiates a GATT Read Multiple Characteristic Values procedure.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read.
- * @param[in] handle_count The number of handles in p_handles.
- *
- * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- */
-SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const * const p_handles, uint16_t handle_count));
-
-
-/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure.
- *
- * @details This function can perform all write procedures described in GATT.
- *
- * @note It is important to note that a write without response will <b>consume an application buffer</b>, and will therefore
- * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. A write on the other hand will use the
- * standard client internal buffer and thus will only generate a @ref BLE_GATTC_EVT_WRITE_RSP event as soon as the write response
- * has been received from the peer. Please see the documentation of @ref sd_ble_tx_buffer_count_get for more details.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_write_params A pointer to a write parameters structure.
- *
- * @retval ::NRF_SUCCESS Successfully started the Write procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
- * @retval ::NRF_ERROR_BUSY Procedure already in progress.
- * @retval ::BLE_ERROR_NO_TX_BUFFERS There are no available buffers left.
- */
-SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const * const p_write_params));
-
-
-/**@brief Send a Handle Value Confirmation to the GATT Server.
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] handle The handle of the attribute in the indication.
- *
- * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE No Indication pending to be confirmed.
- * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle.
- */
-SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle));
-
-/** @} */
-
-#endif /* BLE_GATTC_H__ */
-
-/**
- @}
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_gatts.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,554 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-/**
- @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server
- @{
- @brief Definitions and prototypes for the GATTS interface.
- */
-
-#ifndef BLE_GATTS_H__
-#define BLE_GATTS_H__
-
-#include "ble_types.h"
-#include "ble_ranges.h"
-#include "ble_l2cap.h"
-#include "ble_gap.h"
-#include "ble_gatt.h"
-#include "nrf_svc.h"
-
-/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations
- * @{ */
-
-/**
- * @brief GATTS API SVC numbers.
- */
-enum BLE_GATTS_SVCS
-{
- SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */
- SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */
- SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */
- SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */
- SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */
- SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */
- SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */
- SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */
- SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */
- SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */
- SD_BLE_GATTS_SYS_ATTR_GET, /**< Get updated persistent system attributes after terminating a connection. */
-};
-
-/**
- * @brief GATT Server Event IDs.
- */
-enum BLE_GATTS_EVTS
-{
- BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. */
- BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. */
- BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending, awaiting a sd_ble_gatts_sys_attr_set(). */
- BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. */
- BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. */
- BLE_GATTS_EVT_TIMEOUT /**< Timeout. */
-};
-
-/** @} */
-
-/** @addtogroup BLE_GATTS_DEFINES Defines
- * @{ */
-
-/** @brief Only the default MTU size of 23 is currently supported. */
-#define GATT_RX_MTU 23
-
-/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS
- * @{ */
-#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */
-#define BLE_ERROR_GATTS_SYS_ATTR_MISSING (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */
-/** @} */
-
-/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths
- * @{ */
-#define BLE_GATTS_FIX_ATTR_LEN_MAX (510) /**< Maximum length for fixed length Attribute Values. */
-#define BLE_GATTS_VAR_ATTR_LEN_MAX (512) /**< Maximum length for variable length Attribute Values. */
-/** @} */
-
-/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types
- * @{ */
-#define BLE_GATTS_SRVC_TYPE_INVALID 0x00 /**< Invalid Service Type. */
-#define BLE_GATTS_SRVC_TYPE_PRIMARY 0x01 /**< Primary Service. */
-#define BLE_GATTS_SRVC_TYPE_SECONDARY 0x02 /**< Secondary Type. */
-/** @} */
-
-
-/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types
- * @{ */
-#define BLE_GATTS_ATTR_TYPE_INVALID 0x00 /**< Invalid Attribute Type. */
-#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL 0x01 /**< Primary Service Declaration. */
-#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL 0x02 /**< Secondary Service Declaration. */
-#define BLE_GATTS_ATTR_TYPE_INC_DECL 0x03 /**< Include Declaration. */
-#define BLE_GATTS_ATTR_TYPE_CHAR_DECL 0x04 /**< Characteristic Declaration. */
-#define BLE_GATTS_ATTR_TYPE_CHAR_VAL 0x05 /**< Characteristic Value. */
-#define BLE_GATTS_ATTR_TYPE_DESC 0x06 /**< Descriptor. */
-#define BLE_GATTS_ATTR_TYPE_OTHER 0x07 /**< Other, non-GATT specific type. */
-/** @} */
-
-
-/** @defgroup BLE_GATTS_OPS GATT Server Operations
- * @{ */
-#define BLE_GATTS_OP_INVALID 0x00 /**< Invalid Operation. */
-#define BLE_GATTS_OP_WRITE_REQ 0x01 /**< Write Request. */
-#define BLE_GATTS_OP_WRITE_CMD 0x02 /**< Write Command. */
-#define BLE_GATTS_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */
-#define BLE_GATTS_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */
-#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL 0x05 /**< Execute Write Request: Cancel all prepared writes. */
-#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW 0x06 /**< Execute Write Request: Immediately execute all prepared writes. */
-/** @} */
-
-/** @defgroup BLE_GATTS_VLOCS GATT Value Locations
- * @{ */
-#define BLE_GATTS_VLOC_INVALID 0x00 /**< Invalid Location. */
-#define BLE_GATTS_VLOC_STACK 0x01 /**< Attribute Value is located in stack memory, no user memory is required. */
-#define BLE_GATTS_VLOC_USER 0x02 /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack
- will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */
-/** @} */
-
-/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types
- * @{ */
-#define BLE_GATTS_AUTHORIZE_TYPE_INVALID 0x00 /**< Invalid Type. */
-#define BLE_GATTS_AUTHORIZE_TYPE_READ 0x01 /**< Authorize a Read Operation. */
-#define BLE_GATTS_AUTHORIZE_TYPE_WRITE 0x02 /**< Authorize a Write Request Operation. */
-/** @} */
-
-
-/** @} */
-
-/** @addtogroup BLE_GATTS_STRUCTURES Structures
- * @{ */
-
-/**@brief Attribute metadata. */
-typedef struct
-{
- ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */
- ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */
- uint8_t vlen :1; /**< Variable length attribute. */
- uint8_t vloc :2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/
- uint8_t rd_auth :1; /**< Read Authorization and value will be requested from the application on every read operation. */
- uint8_t wr_auth :1; /**< Write Authorization will be requested from the application on every Write Request operation (but not Write Command). */
-} ble_gatts_attr_md_t;
-
-
-/**@brief GATT Attribute. */
-typedef struct
-{
- ble_uuid_t* p_uuid; /**< Pointer to the attribute UUID. */
- ble_gatts_attr_md_t* p_attr_md; /**< Pointer to the attribute metadata structure. */
- uint16_t init_len; /**< Initial attribute value length in bytes. */
- uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */
- uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */
- uint8_t* p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer
- that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location.
- The stack may access that memory directly without the application's knowledge. */
-} ble_gatts_attr_t;
-
-
-/**@brief GATT Attribute Context. */
-typedef struct
-{
- ble_uuid_t srvc_uuid; /**< Service UUID. */
- ble_uuid_t char_uuid; /**< Characteristic UUID if applicable (BLE_UUID_TYPE_UNKNOWN if N/A). */
- ble_uuid_t desc_uuid; /**< Descriptor UUID if applicable (BLE_UUID_TYPE_UNKNOWN if N/A). */
- uint16_t srvc_handle; /**< Service Handle. */
- uint16_t value_handle; /**< Characteristic Handle if applicable (BLE_GATT_HANDLE_INVALID if N/A). */
- uint8_t type; /**< Attribute Type, see @ref BLE_GATTS_ATTR_TYPES. */
-} ble_gatts_attr_context_t;
-
-
-/**@brief GATT Characteristic Presentation Format. */
-typedef struct
-{
- uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */
- int8_t exponent; /**< Exponent for integer data types. */
- uint16_t unit; /**< UUID from Bluetooth Assigned Numbers. */
- uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
- uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
-} ble_gatts_char_pf_t;
-
-
-/**@brief GATT Characteristic metadata. */
-typedef struct
-{
- ble_gatt_char_props_t char_props; /**< Characteristic Properties. */
- ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */
- uint8_t* p_char_user_desc; /**< Pointer to a UTF-8, NULL if the descriptor is not required. */
- uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */
- uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */
- ble_gatts_char_pf_t* p_char_pf; /**< Pointer to a presentation format structure or NULL if the descriptor is not required. */
- ble_gatts_attr_md_t* p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */
- ble_gatts_attr_md_t* p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */
- ble_gatts_attr_md_t* p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */
-} ble_gatts_char_md_t;
-
-
-/**@brief GATT Characteristic Definition Handles. */
-typedef struct
-{
- uint16_t value_handle; /**< Handle to the characteristic value. */
- uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or BLE_GATT_HANDLE_INVALID if not present. */
- uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or BLE_GATT_HANDLE_INVALID if not present. */
- uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or BLE_GATT_HANDLE_INVALID if not present. */
-} ble_gatts_char_handles_t;
-
-
-/**@brief GATT HVx parameters. */
-typedef struct
-{
- uint16_t handle; /**< Characteristic Value Handle. */
- uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
- uint16_t offset; /**< Offset within the attribute value. */
- uint16_t* p_len; /**< Length in bytes to be written, length in bytes written after successful return. */
- uint8_t* p_data; /**< Actual data content, use NULL to use the current attribute value. */
-} ble_gatts_hvx_params_t;
-
-/**@brief GATT Read Authorization parameters. */
-typedef struct
-{
- uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
- uint8_t update : 1; /**< If set, data supplied in p_data will be used in the ATT response. */
- uint16_t offset; /**< Offset of the attribute value being updated. */
- uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */
- uint8_t* p_data; /**< Pointer to new value used to update the attribute value. */
-} ble_gatts_read_authorize_params_t;
-
-/**@brief GATT Write Authorisation parameters. */
-typedef struct
-{
- uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
-} ble_gatts_write_authorize_params_t;
-
-/**@brief GATT Read or Write Authorize Reply parameters. */
-typedef struct
-{
- uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
- union {
- ble_gatts_read_authorize_params_t read; /**< Read authorization parameters. */
- ble_gatts_write_authorize_params_t write; /**< Write authorization parameters. */
- } params; /**< Reply Parameters. */
-} ble_gatts_rw_authorize_reply_params_t;
-
-
-
-/**@brief Event structure for BLE_GATTS_EVT_WRITE. */
-typedef struct
-{
- uint16_t handle; /**< Attribute Handle. */
- uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */
- ble_gatts_attr_context_t context; /**< Attribute Context. */
- uint16_t offset; /**< Offset for the write operation. */
- uint16_t len; /**< Length of the incoming data. */
- uint8_t data[1]; /**< Incoming data, variable length. */
-} ble_gatts_evt_write_t;
-
-/**@brief Event structure for authorize read request. */
-typedef struct
-{
- uint16_t handle; /**< Attribute Handle. */
- ble_gatts_attr_context_t context; /**< Attribute Context. */
- uint16_t offset; /**< Offset for the read operation. */
-} ble_gatts_evt_read_t;
-
-/**@brief Event structure for BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */
-typedef struct
-{
- uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
- union {
- ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */
- ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */
- } request; /**< Request Parameters. */
-} ble_gatts_evt_rw_authorize_request_t;
-
-/**@brief Event structure for BLE_GATTS_EVT_SYS_ATTR_MISSING. */
-typedef struct
-{
- uint8_t hint; /**< Hint (TBD). */
-} ble_gatts_evt_sys_attr_missing_t;
-
-
-/**@brief Event structure for BLE_GATTS_EVT_HVC. */
-typedef struct
-{
- uint16_t handle; /**< Attribute Handle. */
-} ble_gatts_evt_hvc_t;
-
-/**@brief Event structure for BLE_GATTS_EVT_TIMEOUT. */
-typedef struct
-{
- uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
-} ble_gatts_evt_timeout_t;
-
-
-/**@brief GATT Server event callback event structure. */
-typedef struct
-{
- uint16_t conn_handle; /**< Connection Handle on which event occurred. */
- union
- {
- ble_gatts_evt_write_t write; /**< Write Event Parameters. */
- ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */
- ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */
- ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */
- ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */
- } params; /**< Event Parameters. */
-} ble_gatts_evt_t;
-
-/** @} */
-
-/** @addtogroup BLE_GATTS_FUNCTIONS Functions
- * @{ */
-
-/**@brief Add a service declaration to the local server ATT table.
- *
- * @param[in] type Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES.
- * @param[in] p_uuid Pointer to service UUID.
- * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored.
- *
- * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to
- * add a secondary service declaration that is not referenced by another service later in the ATT table.
- *
- * @retval ::NRF_SUCCESS Successfully added a service declaration.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- */
-SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const*const p_uuid, uint16_t *const p_handle));
-
-
-/**@brief Add an include declaration to the local server ATT table.
- *
- * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential addition is supported at this time).
- *
- * @note The included service must already be present in the ATT table prior to this call.
- *
- * @param[in] service_handle Handle of the service where the included service is to be placed, if BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
- * @param[in] inc_srvc_handle Handle of the included service.
- * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added an include declaration.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
- */
-SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *const p_include_handle));
-
-
-/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the local server ATT table.
- *
- * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential addition is supported at this time).
- *
- * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writeable auxiliaries bits,
- * readable (no security) and writeable (selectable) CCCDs and SCCDs and valid presentation format values.
- *
- * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions.
- *
- * @param[in] service_handle Handle of the service where the characteristic is to be placed, if BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
- * @param[in] p_char_md Characteristic metadata.
- * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value.
- * @param[out] p_handles Pointer to the structure where the assigned handles will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added a characteristic.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
- */
-SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const*const p_char_md, ble_gatts_attr_t const*const p_attr_char_value, ble_gatts_char_handles_t *const p_handles));
-
-
-/**@brief Add a descriptor to the local server ATT table.
- *
- * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential addition is supported at this time).
- *
- * @param[in] char_handle Handle of the characteristic where the descriptor is to be placed, if BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
- * @param[in] p_attr Pointer to the attribute structure.
- * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added a descriptor.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
- */
-SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const * const p_attr, uint16_t* const p_handle));
-
-/**@brief Set the value of a given attribute.
- *
- * @param[in] handle Attribute handle.
- * @param[in] offset Offset in bytes to write from.
- * @param[in,out] p_len Length in bytes to be written, length in bytes written after successful return.
- * @param[in] p_value Pointer to a buffer (at least len bytes long) containing the desired attribute value.
- *
- * @retval ::NRF_SUCCESS Successfully set the value of the attribute.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
- */
-SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t handle, uint16_t offset, uint16_t* const p_len, uint8_t const * const p_value));
-
-/**@brief Get the value of a given attribute.
- *
- * @param[in] handle Attribute handle.
- * @param[in] offset Offset in bytes to read from.
- * @param[in,out] p_len Length in bytes to be read, length in bytes read after successful return.
- * @param[in,out] p_data Pointer to a buffer (at least len bytes long) where to store the attribute value.
- *
- * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
- */
-SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t handle, uint16_t offset, uint16_t *const p_len, uint8_t* const p_data));
-
-/**@brief Notify or Indicate an attribute value.
- *
- * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation
- * (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that
- * the application can atomically perform a value update and a server initiated transaction with a single API call.
- * If the application chooses to indicate an attribute value, a @ref BLE_GATTS_EVT_HVC will be sent up as soon as the confirmation arrives from
- * the peer.
- *
- * @note The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution.
- * When receiveing the error codes @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and
- * @ref BLE_ERROR_NO_TX_BUFFERS the ATT table has been updated.
- * The caller can check whether the value has been updated by looking at the contents of *(p_hvx_params->p_len).
- *
- * @note It is important to note that a notification will <b>consume an application buffer</b>, and will therefore
- * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. An indication on the other hand will use the
- * standard server internal buffer and thus will only generate a @ref BLE_GATTS_EVT_HVC event as soon as the confirmation
- * has been received from the peer. Please see the documentation of @ref sd_ble_tx_buffer_count_get for more details.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_hvx_params Pointer to an HVx parameters structure. If the p_data member contains a non-NULL pointer the attribute value will be updated with
- * the contents pointed by it before sending the notification or indication.
- *
- * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate.
- * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, notifications or indications must be enabled in the CCCD.
- * @retval ::NRF_ERROR_BUSY Procedure already in progress.
- * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
- * @retval ::BLE_ERROR_NO_TX_BUFFERS There are no available buffers to send the data, applies only to notifications.
- */
-SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const*const p_hvx_params));
-
-/**@brief Indicate the Service Changed attribute value.
- *
- * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the attribute
- * table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will
- * be issued.
- *
- * @note Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] start_handle Start of affected attribute handle range.
- * @param[in] end_handle End of affected attribute handle range.
- *
- * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, notifications or indications must be enabled in the CCCD.
- * @retval ::NRF_ERROR_BUSY Procedure already in progress.
- * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
- */
-SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle));
-
-/**@brief Respond to a Read/Write authorization request.
- *
- * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application.
- *
- * @retval ::NRF_SUCCESS Successfully queued a response to the peer, and in the case of a write operation, ATT table updated.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE No authorization request pending.
- * @retval ::NRF_ERROR_INVALID_PARAM Authorization op invalid,
- * or for Read Authorization reply: requested handles not replied with,
- * or for Write Authorization reply: handle supplied does not match requested handle.
- */
-SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const*const p_rw_authorize_reply_params));
-
-
-/**@brief Update persistent system attribute information.
- *
- * @details Supply to the stack information about persistent system attributes.
- * This call is legal in the connected state only, and is usually
- * made immediately after a connection is established and the bond identified.
- * usually as a response to a BLE_GATTS_EVT_SYS_ATTR_MISSING.
- *
- * p_sysattrs may point directly to the application's stored copy of the struct.
- * If the pointer is NULL, the system attribute info is initialized, assuming that
- * the application does not have any previously saved data for this bond.
- *
- * @note The state of persistent system attributes is reset upon connection and then remembered for its duration.
- *
- * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially.
- * This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or
- * reset the SoftDevice to return to a known state.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_sys_attr_data Pointer to a saved copy of system attributes supplied to the stack, or NULL.
- * @param[in] len Size of data pointed by p_sys_attr_data, in octets.
- *
- * @retval ::NRF_SUCCESS Successfully set the system attribute information.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- */
-SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const*const p_sys_attr_data, uint16_t len));
-
-
-/**@brief Retrieve persistent system attribute information from the stack.
- *
- * @details This call is used to retrieve information about values to be stored perisistently by the application
- * after a connection has been terminated. When a new connection is made to the same bond, the values
- * should be restored using @ref sd_ble_gatts_sys_attr_set.
- * The data should be read before any new advertising is started, or any new connection established. The connection handle for
- * the previous now defunct connection will remain valid until a new one is created to allow this API call to refer to it.
- *
- * @param[in] conn_handle Connection handle of the recently terminated connection.
- * @param[in] p_sys_attr_data Pointer to a buffer where updated information about system attributes will be filled in. NULL can be provided to
- * obtain the length of the data
- * @param[in,out] p_len Size of application buffer if p_sys_attr_data is not NULL. Unconditially updated to actual length of system attribute data.
- *
- * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer.
- */
-SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t * const p_sys_attr_data, uint16_t* const p_len));
-
-/** @} */
-
-#endif // BLE_GATTS_H__
-
-/**
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_hci.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,96 +0,0 @@
-/*
- Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
-
- The information contained herein is confidential property of Nordic Semiconductor. The use,
- copying, transfer or disclosure of such information is prohibited except by express written
- agreement with Nordic Semiconductor.
- */
-/**
- @addtogroup BLE_COMMON
- @{
-*/
-
-
-#ifndef BLE_HCI_H__
-#define BLE_HCI_H__
-
-/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes
- * @{ */
-
-#define BLE_HCI_STATUS_CODE_SUCCESS 0x00 /**< Success. */
-#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND 0x01 /**< Unknown BLE Command. */
-#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER 0x02 /**< Unknown Connection Identifier. */
-/*0x03 Hardware Failure
-0x04 Page Timeout
-*/
-#define BLE_HCI_AUTHENTICATION_FAILURE 0x05 /**< Authentication Failure. */
-#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING 0x06 /**< Pin or Key missing. */
-#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED 0x07 /**< Memory Capacity Exceeded. */
-#define BLE_HCI_CONNECTION_TIMEOUT 0x08 /**< Connection Timeout. */
-/*0x09 Connection Limit Exceeded
-0x0A Synchronous Connection Limit To A Device Exceeded
-0x0B ACL Connection Already Exists*/
-#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED 0x0C /**< Command Disallowed. */
-/*0x0D Connection Rejected due to Limited Resources
-0x0E Connection Rejected Due To Security Reasons
-0x0F Connection Rejected due to Unacceptable BD_ADDR
-0x10 Connection Accept Timeout Exceeded
-0x11 Unsupported Feature or Parameter Value*/
-#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12 /**< Invalid BLE Command Parameters. */
-#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION 0x13 /**< Remote User Terminated Connection. */
-#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14 /**< Remote Device Terminated Connection due to low resources.*/
-#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF 0x15 /**< Remote Device Terminated Connection due to power off. */
-#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION 0x16 /**< Local Host Terminated Connection. */
-/*
-0x17 Repeated Attempts
-0x18 Pairing Not Allowed
-0x19 Unknown LMP PDU
-*/
-#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A /**< Unsupported Remote Feature. */
-/*
-0x1B SCO Offset Rejected
-0x1C SCO Interval Rejected
-0x1D SCO Air Mode Rejected*/
-#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS 0x1E /**< Invalid LMP Parameters. */
-#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR 0x1F /**< Unspecified Error. */
-/*0x20 Unsupported LMP Parameter Value
-0x21 Role Change Not Allowed
-*/
-#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT 0x22 /**< LMP Response Timeout. */
-/*0x23 LMP Error Transaction Collision*/
-#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED 0x24 /**< LMP PDU Not Allowed. */
-/*0x25 Encryption Mode Not Acceptable
-0x26 Link Key Can Not be Changed
-0x27 Requested QoS Not Supported
-*/
-#define BLE_HCI_INSTANT_PASSED 0x28 /**< Instant Passed. */
-#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED 0x29 /**< Pairing with Unit Key Unsupported. */
-#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION 0x2A /**< Different Transaction Collision. */
-/*
-0x2B Reserved
-0x2C QoS Unacceptable Parameter
-0x2D QoS Rejected
-0x2E Channel Classification Not Supported
-0x2F Insufficient Security
-0x30 Parameter Out Of Mandatory Range
-0x31 Reserved
-0x32 Role Switch Pending
-0x33 Reserved
-0x34 Reserved Slot Violation
-0x35 Role Switch Failed
-0x36 Extended Inquiry Response Too Large
-0x37 Secure Simple Pairing Not Supported By Host.
-0x38 Host Busy - Pairing
-0x39 Connection Rejected due to No Suitable Channel Found*/
-#define BLE_HCI_CONTROLLER_BUSY 0x3A /**< Controller Busy. */
-#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE 0x3B /**< Connection Interval Unacceptable. */
-#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT 0x3C /**< Directed Adverisement Timeout. */
-#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE 0x3D /**< Connection Terminated due to MIC Failure. */
-#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED 0x3E /**< Connection Failed to be Established. */
-
-/** @} */
-
-
-#endif // BLE_HCI_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_l2cap.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,149 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-/**
- @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP)
- @{
- @brief Definitions and prototypes for the L2CAP interface.
- */
-
-#ifndef BLE_L2CAP_H__
-#define BLE_L2CAP_H__
-
-#include "ble_types.h"
-#include "ble_ranges.h"
-#include "ble_err.h"
-#include "nrf_svc.h"
-
-/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations
- * @{ */
-
-/**@brief L2CAP API SVC numbers. */
-enum BLE_L2CAP_SVCS
-{
- SD_BLE_L2CAP_CID_REGISTER = BLE_L2CAP_SVC_BASE, /**< Register a CID. */
- SD_BLE_L2CAP_CID_UNREGISTER, /**< Unregister a CID. */
- SD_BLE_L2CAP_TX /**< Transmit a packet. */
-};
-
-/**@brief L2CAP Event IDs. */
-enum BLE_L2CAP_EVTS
-{
- BLE_L2CAP_EVT_RX = BLE_L2CAP_EVT_BASE /**< L2CAP packet received. */
-};
-
-/** @} */
-
-
-/**@addtogroup BLE_L2CAP_DEFINES Defines
- * @{ */
-
-/**@defgroup BLE_ERRORS_L2CAP SVC return values specific to L2CAP
- * @{ */
-#define BLE_ERROR_L2CAP_CID_IN_USE (NRF_L2CAP_ERR_BASE + 0x000) /**< CID already in use. */
-/** @} */
-
-/**@brief Default L2CAP MTU. */
-#define BLE_L2CAP_MTU_DEF (23)
-
-/**@brief Invalid Channel Identifier. */
-#define BLE_L2CAP_CID_INVALID (0x0000)
-
-/**@brief Dynamic Channel Identifier base. */
-#define BLE_L2CAP_CID_DYN_BASE (0x0040)
-
-/**@brief Maximum amount of dynamic CIDs. */
-#define BLE_L2CAP_CID_DYN_MAX (8)
-
-/** @} */
-
-/**@addtogroup BLE_L2CAP_STRUCTURES Structures
- * @{ */
-
-/**@brief Packet header format for L2CAP transmission. */
-typedef struct
-{
- uint16_t len; /**< Length of valid info in data member. */
- uint16_t cid; /**< Channel ID on which packet is transmitted. */
-} ble_l2cap_header_t;
-
-
-/**@brief L2CAP Received packet event report. */
-typedef struct
-{
- ble_l2cap_header_t header; /**< L2CAP packet header. */
- uint8_t data[1]; /**< Packet data, variable length. */
-} ble_l2cap_evt_rx_t;
-
-
-/**@brief L2CAP event callback event structure. */
-typedef struct
-{
- uint16_t conn_handle; /**< Connection Handle on which event occured. */
- union
- {
- ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */
- } params; /**< Event Parameters. */
-} ble_l2cap_evt_t;
-
-/** @} */
-
-/**@addtogroup BLE_L2CAP_FUNCTIONS Functions
- * @{ */
-
-/**@brief Register a CID with L2CAP.
- *
- * @details This registers a higher protocol layer with the L2CAP multiplexer, and is requried prior to all operations on the CID.
- *
- * @param[in] cid L2CAP CID.
- *
- * @retval ::NRF_SUCCESS Successfully registered a CID with the L2CAP layer.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CID must be above @ref BLE_L2CAP_CID_DYN_BASE.
- * @retval ::BLE_ERROR_L2CAP_CID_IN_USE L2CAP CID already in use.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- */
-SVCALL(SD_BLE_L2CAP_CID_REGISTER, uint32_t, sd_ble_l2cap_cid_register(uint16_t cid));
-
-/**@brief Unregister a CID with L2CAP.
- *
- * @details This unregisters a previously registerd higher protocol layer with the L2CAP multiplexer.
- *
- * @param[in] cid L2CAP CID.
- *
- * @retval ::NRF_SUCCESS Successfully unregistered the CID.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_NOT_FOUND CID not previously registered.
- */
-SVCALL(SD_BLE_L2CAP_CID_UNREGISTER, uint32_t, sd_ble_l2cap_cid_unregister(uint16_t cid));
-
-/**@brief Transmit an L2CAP packet.
- *
- * @note It is important to note that a call to this function will <b>consume an application buffer</b>, and will therefore
- * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted.
- * Please see the documentation of @ref sd_ble_tx_buffer_count_get for more details.
- *
- * @param[in] conn_handle Connection Handle.
- * @param[in] p_header Pointer to a packet header containing length and CID.
- * @param[in] p_data Pointer to the data to be transmitted.
- *
- * @retval ::NRF_SUCCESS Successfully queued an L2CAP packet for transmission.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CIDs must be registered beforehand with @ref sd_ble_l2cap_cid_register.
- * @retval ::NRF_ERROR_NOT_FOUND CID not found.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- * @retval ::BLE_ERROR_NO_TX_BUFFERS Not enough application buffers available.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, see @ref BLE_L2CAP_MTU_DEF.
- */
-SVCALL(SD_BLE_L2CAP_TX, uint32_t, sd_ble_l2cap_tx(uint16_t conn_handle, ble_l2cap_header_t const * const p_header, uint8_t const * const p_data));
-
-/** @} */
-
-#endif // BLE_L2CAP_H__
-
-/**
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_ranges.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-/*
- Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
-
- The information contained herein is confidential property of Nordic Semiconductor. The use,
- copying, transfer or disclosure of such information is prohibited except by express written
- agreement with Nordic Semiconductor.
- */
-/**
- @addtogroup BLE_COMMON
- @{
- @defgroup ble_ranges Module specific SVC and event number subranges
- @{
-
- @brief Definition of SVC and event number subranges for each API module.
-
- @note
- SVCs and event numbers are split into subranges for each API module.
- Each module receives its entire allocated range of SVC calls, whether implemented or not,
- but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range.
-
- Note that the symbols BLE_<module>_SVC_LAST is the end of the allocated SVC range,
- rather than the last SVC function call actually defined and implemented.
-
- Specific SVC and event values are defined in each module's ble_<module>.h file,
- which defines names of each individual SVC code based on the range start value.
-*/
-
-#ifndef BLE_RANGES_H__
-#define BLE_RANGES_H__
-
-#define BLE_SVC_BASE 0x50 /**< Common BLE SVC base. */
-#define BLE_SVC_LAST 0x5B /**< Total: 12. */
-
-#define BLE_RESERVED_SVC_BASE 0x5C /**< Reserved BLE SVC base. */
-#define BLE_RESERVED_SVC_LAST 0x5F /**< Total: 4. */
-
-#define BLE_GAP_SVC_BASE 0x60 /**< GAP BLE SVC base. */
-#define BLE_GAP_SVC_LAST 0x7F /**< Total: 32. */
-
-#define BLE_GATTC_SVC_BASE 0x80 /**< GATTC BLE SVC base. */
-#define BLE_GATTC_SVC_LAST 0x9F /**< Total: 32. */
-
-#define BLE_GATTS_SVC_BASE 0xA0 /**< GATTS BLE SVC base. */
-#define BLE_GATTS_SVC_LAST 0xAF /**< Total: 16. */
-
-#define BLE_L2CAP_SVC_BASE 0xB0 /**< L2CAP BLE SVC base. */
-#define BLE_L2CAP_SVC_LAST 0xBF /**< Total: 16. */
-
-
-#define BLE_EVT_INVALID 0x00 /**< Invalid BLE Event. */
-
-#define BLE_EVT_BASE 0x01 /**< Common BLE Event base. */
-#define BLE_EVT_LAST 0x0F /**< Total: 15. */
-
-#define BLE_GAP_EVT_BASE 0x10 /**< GAP BLE Event base. */
-#define BLE_GAP_EVT_LAST 0x2F /**< Total: 32. */
-
-#define BLE_GATTC_EVT_BASE 0x30 /**< GATTC BLE Event base. */
-#define BLE_GATTC_EVT_LAST 0x4F /**< Total: 32. */
-
-#define BLE_GATTS_EVT_BASE 0x50 /**< GATTS BLE Event base. */
-#define BLE_GATTS_EVT_LAST 0x6F /**< Total: 32. */
-
-#define BLE_L2CAP_EVT_BASE 0x70 /**< L2CAP BLE Event base. */
-#define BLE_L2CAP_EVT_LAST 0x8F /**< Total: 32. */
-
-#endif /* BLE_RANGES_H__ */
-
-/**
- @}
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/ble_types.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,160 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-/**
- @addtogroup BLE_COMMON
- @{
- @defgroup ble_types Common types and macro definitions
- @{
-
- @brief Common types and macro definitions for the S120 SoftDevice.
- */
-
-#ifndef BLE_TYPES_H__
-#define BLE_TYPES_H__
-
-#include <stdint.h>
-
-/** @addtogroup BLE_TYPES_DEFINES Defines
- * @{ */
-
-/** @defgroup BLE_CONN_HANDLES BLE Connection Handles
- * @{ */
-#define BLE_CONN_HANDLE_INVALID 0xFFFF /**< Invalid Connection Handle. */
-#define BLE_CONN_HANDLE_ALL 0xFFFE /**< Applies to all Connection Handles. */
-/** @} */
-
-
-/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs
- * @{ */
-/* Generic UUIDs, applicable to all services */
-#define BLE_UUID_UNKNOWN 0x0000 /**< Reserved UUID. */
-#define BLE_UUID_SERVICE_PRIMARY 0x2800 /**< Primary Service. */
-#define BLE_UUID_SERVICE_SECONDARY 0x2801 /**< Secondary Service. */
-#define BLE_UUID_SERVICE_INCLUDE 0x2802 /**< Include. */
-#define BLE_UUID_CHARACTERISTIC 0x2803 /**< Characteristic. */
-#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP 0x2900 /**< Characteristic Extended Properties Descriptor. */
-#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC 0x2901 /**< Characteristic User Description Descriptor. */
-#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG 0x2902 /**< Client Characteristic Configuration Descriptor. */
-#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG 0x2903 /**< Server Characteristic Configuration Descriptor. */
-#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT 0x2904 /**< Characteristic Presentation Format Descriptor. */
-#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT 0x2905 /**< Characteristic Aggregate Format Descriptor. */
-/* GATT specific UUIDs */
-#define BLE_UUID_GATT 0x1801 /**< Generic Attribute Profile. */
-#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED 0x2A05 /**< Service Changed Characteristic. */
-/* GAP specific UUIDs */
-#define BLE_UUID_GAP 0x1800 /**< Generic Access Profile. */
-#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME 0x2A00 /**< Device Name Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE 0x2A01 /**< Appearance Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_PPF 0x2A02 /**< Peripheral Privacy Flag Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR 0x2A03 /**< Reconnection Address Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_PPCP 0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */
-/** @} */
-
-
-/** @defgroup BLE_UUID_TYPES Types of UUID
- * @{ */
-#define BLE_UUID_TYPE_UNKNOWN 0x00 /**< Invalid UUID type. */
-#define BLE_UUID_TYPE_BLE 0x01 /**< Bluetooth SIG UUID (16-bit). */
-#define BLE_UUID_TYPE_VENDOR_BEGIN 0x02 /**< Vendor UUID types start at this index (128-bit). */
-/** @} */
-
-
-/** @defgroup BLE_APPEARANCES Bluetooth Appearance values
- * @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml
- * @{ */
-#define BLE_APPEARANCE_UNKNOWN 0 /**< Unknown. */
-#define BLE_APPEARANCE_GENERIC_PHONE 64 /**< Generic Phone. */
-#define BLE_APPEARANCE_GENERIC_COMPUTER 128 /**< Generic Computer. */
-#define BLE_APPEARANCE_GENERIC_WATCH 192 /**< Generic Watch. */
-#define BLE_APPEARANCE_WATCH_SPORTS_WATCH 193 /**< Watch: Sports Watch. */
-#define BLE_APPEARANCE_GENERIC_CLOCK 256 /**< Generic Clock. */
-#define BLE_APPEARANCE_GENERIC_DISPLAY 320 /**< Generic Display. */
-#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL 384 /**< Generic Remote Control. */
-#define BLE_APPEARANCE_GENERIC_EYE_GLASSES 448 /**< Generic Eye-glasses. */
-#define BLE_APPEARANCE_GENERIC_TAG 512 /**< Generic Tag. */
-#define BLE_APPEARANCE_GENERIC_KEYRING 576 /**< Generic Keyring. */
-#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER 640 /**< Generic Media Player. */
-#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER 704 /**< Generic Barcode Scanner. */
-#define BLE_APPEARANCE_GENERIC_THERMOMETER 768 /**< Generic Thermometer. */
-#define BLE_APPEARANCE_THERMOMETER_EAR 769 /**< Thermometer: Ear. */
-#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR 832 /**< Generic Heart rate Sensor. */
-#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT 833 /**< Heart Rate Sensor: Heart Rate Belt. */
-#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE 896 /**< Generic Blood Pressure. */
-#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM 897 /**< Blood Pressure: Arm. */
-#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST 898 /**< Blood Pressure: Wrist. */
-#define BLE_APPEARANCE_GENERIC_HID 960 /**< Human Interface Device (HID). */
-#define BLE_APPEARANCE_HID_KEYBOARD 961 /**< Keyboard (HID Subtype). */
-#define BLE_APPEARANCE_HID_MOUSE 962 /**< Mouse (HID Subtype). */
-#define BLE_APPEARANCE_HID_JOYSTICK 963 /**< Joystiq (HID Subtype). */
-#define BLE_APPEARANCE_HID_GAMEPAD 964 /**< Gamepad (HID Subtype). */
-#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE 965 /**< Digitizer Tablet (HID Subtype). */
-#define BLE_APPEARANCE_HID_CARD_READER 966 /**< Card Reader (HID Subtype). */
-#define BLE_APPEARANCE_HID_DIGITAL_PEN 967 /**< Digital Pen (HID Subtype). */
-#define BLE_APPEARANCE_HID_BARCODE 968 /**< Barcode Scanner (HID Subtype). */
-#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER 1024 /**< Generic Glucose Meter. */
-#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR 1088 /**< Generic Running Walking Sensor. */
-#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE 1089 /**< Running Walking Sensor: In-Shoe. */
-#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE 1090 /**< Running Walking Sensor: On-Shoe. */
-#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP 1091 /**< Running Walking Sensor: On-Hip. */
-#define BLE_APPEARANCE_GENERIC_CYCLING 1152 /**< Generic Cycling. */
-#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER 1153 /**< Cycling: Cycling Computer. */
-#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR 1154 /**< Cycling: Speed Sensor. */
-#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR 1155 /**< Cycling: Cadence Sensor. */
-#define BLE_APPEARANCE_CYCLING_POWER_SENSOR 1156 /**< Cycling: Power Sensor. */
-#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR 1157 /**< Cycling: Speed and Cadence Sensor. */
-/** @} */
-
-/** @brief Set .type and .uuid fields of ble_uuid_struct to specified uuid value. */
-#define BLE_UUID_BLE_ASSIGN(instance, value) do {\
- instance.type = BLE_UUID_TYPE_BLE; \
- instance.uuid = value;} while(0)
-
-/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */
-#define BLE_UUID_COPY_PTR(dst, src) do {\
- (dst)->type = (src)->type; \
- (dst)->uuid = (src)->uuid;} while(0)
-
-/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */
-#define BLE_UUID_COPY_INST(dst, src) do {\
- (dst).type = (src).type; \
- (dst).uuid = (src).uuid;} while(0)
-
-/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
-#define BLE_UUID_EQ(p_uuid1, p_uuid2) \
- (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid))
-
-/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
-#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \
- (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid))
-
-/** @} */
-
-/** @addtogroup BLE_TYPES_STRUCTURES Structures
- * @{ */
-
-/** @brief 128 bit UUID values. */
-typedef struct
-{
- unsigned char uuid128[16]; /**< Little-Endian UUID bytes. */
-} ble_uuid128_t;
-
-/** @brief Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */
-typedef struct
-{
- uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */
- uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. */
-} ble_uuid_t;
-
-/** @} */
-
-#endif /* BLE_TYPES_H__ */
-
-/**
- @}
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/nrf_error.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
- /**
- @defgroup nrf_error SoftDevice Global Error Codes
- @{
-
- @brief Global Error definitions
-*/
-
-/* Header guard */
-#ifndef NRF_ERROR_H__
-#define NRF_ERROR_H__
-
-/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions
- * @{ */
-#define NRF_ERROR_BASE_NUM (0x0) ///< Global error base
-#define NRF_ERROR_SDM_BASE_NUM (0x1000) ///< SDM error base
-#define NRF_ERROR_SOC_BASE_NUM (0x2000) ///< SoC error base
-#define NRF_ERROR_STK_BASE_NUM (0x3000) ///< STK error base
-/** @} */
-
-#define NRF_SUCCESS (NRF_ERROR_BASE_NUM + 0) ///< Successful command
-#define NRF_ERROR_SVC_HANDLER_MISSING (NRF_ERROR_BASE_NUM + 1) ///< SVC handler is missing
-#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED (NRF_ERROR_BASE_NUM + 2) ///< SoftDevice has not been enabled
-#define NRF_ERROR_INTERNAL (NRF_ERROR_BASE_NUM + 3) ///< Internal Error
-#define NRF_ERROR_NO_MEM (NRF_ERROR_BASE_NUM + 4) ///< No Memory for operation
-#define NRF_ERROR_NOT_FOUND (NRF_ERROR_BASE_NUM + 5) ///< Not found
-#define NRF_ERROR_NOT_SUPPORTED (NRF_ERROR_BASE_NUM + 6) ///< Not supported
-#define NRF_ERROR_INVALID_PARAM (NRF_ERROR_BASE_NUM + 7) ///< Invalid Parameter
-#define NRF_ERROR_INVALID_STATE (NRF_ERROR_BASE_NUM + 8) ///< Invalid state, operation disallowed in this state
-#define NRF_ERROR_INVALID_LENGTH (NRF_ERROR_BASE_NUM + 9) ///< Invalid Length
-#define NRF_ERROR_INVALID_FLAGS (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags
-#define NRF_ERROR_INVALID_DATA (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data
-#define NRF_ERROR_DATA_SIZE (NRF_ERROR_BASE_NUM + 12) ///< Data size exceeds limit
-#define NRF_ERROR_TIMEOUT (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out
-#define NRF_ERROR_NULL (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer
-#define NRF_ERROR_FORBIDDEN (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation
-#define NRF_ERROR_INVALID_ADDR (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address
-#define NRF_ERROR_BUSY (NRF_ERROR_BASE_NUM + 17) ///< Busy
-
-#endif // NRF_ERROR_H__
-
-/**
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/nrf_error_sdm.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
- /**
- @addtogroup nrf_sdm_api
- @{
- @defgroup nrf_sdm_error SoftDevice Manager Error Codes
- @{
-
- @brief Error definitions for the SDM API
-*/
-
-/* Header guard */
-#ifndef NRF_ERROR_SDM_H__
-#define NRF_ERROR_SDM_H__
-
-#include "nrf_error.h"
-
-#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN (NRF_ERROR_SDM_BASE_NUM + 0) ///< Unknown lfclk source
-#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1) ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts)
-#define NRF_ERROR_SDM_INCORRECT_CLENR0 (NRF_ERROR_SDM_BASE_NUM + 2) ///< Incorrect CLENR0 (can be caused by erronous SoftDevice flashing)
-
-#endif // NRF_ERROR_SDM_H__
-
-/**
- @}
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/nrf_error_soc.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
- /**
- @addtogroup nrf_soc_api
- @{
- @defgroup nrf_soc_error SoC Library Error Codes
- @{
-
- @brief Error definitions for the SoC library
-
-*/
-
-/* Header guard */
-#ifndef NRF_ERROR_SOC_H__
-#define NRF_ERROR_SOC_H__
-
-#include "nrf_error.h"
-
-/* Mutex Errors */
-#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN (NRF_ERROR_SOC_BASE_NUM + 0) ///< Mutex already taken
-
-/* NVIC errors */
-#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE (NRF_ERROR_SOC_BASE_NUM + 1) ///< NVIC interrupt not available
-#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2) ///< NVIC interrupt priority not allowed
-#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 3) ///< NVIC should not return
-
-/* Power errors */
-#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 4) ///< Power mode unknown
-#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 5) ///< Power POF threshold unknown
-#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 6) ///< Power off should not return
-
-/* Rand errors */
-#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES (NRF_ERROR_SOC_BASE_NUM + 7) ///< RAND not enough values
-
-/* PPI errors */
-#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL (NRF_ERROR_SOC_BASE_NUM + 8) ///< Invalid PPI Channel
-#define NRF_ERROR_SOC_PPI_INVALID_GROUP (NRF_ERROR_SOC_BASE_NUM + 9) ///< Invalid PPI Group
-
-#endif // NRF_ERROR_SOC_H__
-/**
- @}
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/nrf_sdm.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,162 +0,0 @@
-/*
- * Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-/**
- @defgroup nrf_sdm_api SoftDevice Manager API
- @{
-
- @brief APIs for SoftDevice management.
-
-*/
-
-/* Header guard */
-#ifndef NRF_SDM_H__
-#define NRF_SDM_H__
-
-#include "nrf_svc.h"
-#include "nrf51.h"
-#include "nrf_soc.h"
-#include "nrf_error_sdm.h"
-
-/** @addtogroup NRF_SDM_DEFINES Defines
- * @{ */
-
-/**@brief SoftDevice Manager SVC Base number. */
-#define SDM_SVC_BASE 0x10
-
-/** @} */
-
-/** @addtogroup NRF_SDM_ENUMS Enumerations
- * @{ */
-
-/**@brief nRF SoftDevice Manager API SVC numbers. */
-enum NRF_SD_SVCS
-{
- SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */
- SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */
- SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */
- SD_SOFTDEVICE_FORWARD_TO_APPLICATION,/**< ::sd_softdevice_forward_to_application */
- SVC_SDM_LAST /**< Placeholder for last SDM SVC */
-};
-
-/**@brief Possible lfclk oscillator sources. */
-enum NRF_CLOCK_LFCLKSRCS
-{
- NRF_CLOCK_LFCLKSRC_RC_250_PPM_500MS_CALIBRATION, /**< LFCLK RC oscillator, 500ms calibration interval.*/
- NRF_CLOCK_LFCLKSRC_RC_250_PPM_1000MS_CALIBRATION, /**< LFCLK RC oscillator, 1000ms calibration interval.*/
- NRF_CLOCK_LFCLKSRC_RC_250_PPM_2000MS_CALIBRATION, /**< LFCLK RC oscillator, 2000ms calibration interval.*/
- NRF_CLOCK_LFCLKSRC_RC_250_PPM_4000MS_CALIBRATION, /**< LFCLK RC oscillator, 4000ms calibration interval.*/
- NRF_CLOCK_LFCLKSRC_RC_250_PPM_8000MS_CALIBRATION, /**< LFCLK RC oscillator, 8000ms calibration interval.*/
- NRF_CLOCK_LFCLKSRC_SYNTH_250_PPM, /**< LFCLK Synthesized from HFCLK. */
- NRF_CLOCK_LFCLKSRC_XTAL_500_PPM, /**< LFCLK crystal oscillator 500 PPM accuracy. */
- NRF_CLOCK_LFCLKSRC_XTAL_250_PPM, /**< LFCLK crystal oscillator 250 PPM accuracy. */
- NRF_CLOCK_LFCLKSRC_XTAL_150_PPM, /**< LFCLK crystal oscillator 150 PPM accuracy. */
- NRF_CLOCK_LFCLKSRC_XTAL_100_PPM, /**< LFCLK crystal oscillator 100 PPM accuracy. */
- NRF_CLOCK_LFCLKSRC_XTAL_75_PPM, /**< LFCLK crystal oscillator 75 PPM accuracy. */
- NRF_CLOCK_LFCLKSRC_XTAL_50_PPM, /**< LFCLK crystal oscillator 50 PPM accuracy. */
- NRF_CLOCK_LFCLKSRC_XTAL_30_PPM, /**< LFCLK crystal oscillator 30 PPM accuracy. */
- NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, /**< LFCLK crystal oscillator 20 PPM accuracy. */
-};
-
-/** @} */
-
-/** @addtogroup NRF_SDM_TYPES Types
- * @{ */
-
-/**@brief Type representing lfclk oscillator source. */
-typedef uint32_t nrf_clock_lfclksrc_t;
-
-
-/**@brief SoftDevice Assertion Handler type.
- *
- * When an unexpected error occurs within the SoftDevice it will call the SoftDevice assertion handler callback.
- * The protocol stack will be in an undefined state when this happens and the only way to recover will be to
- * perform a reset, using e.g. CMSIS NVIC_SystemReset().
- *
- * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the SoftDevice assert callback.
- *
- * @param[in] pc The program counter of the failed assert.
- * @param[in] line_number Line number where the assert failed.
- * @param[in] file_name File name where the assert failed.
- */
-typedef void (*softdevice_assertion_handler_t)(uint32_t pc, uint16_t line_number, const uint8_t * p_file_name);
-
-/** @} */
-
-/** @addtogroup NRF_SDM_FUNCTIONS Functions
- * @{ */
-
-/**@brief Enables the SoftDevice and by extension the protocol stack.
- *
- * Idempotent function to enable the SoftDevice.
- *
- * @note Some care must be taken if a low frequency clock source is already running when calling this function:
- * If the LF clock has a different source then the one currently running, it will be stopped. Then, the new
- * clock source will be started.
- *
- * @note This function has no effect when returning with an error.
- *
- * @post If return code is ::NRF_SUCCESS
- * - SoC library and protocol stack APIs are made available
- * - A portion of RAM will be unavailable (see relevant SDS documentation)
- * - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation)
- * - Interrupts will not arrive from protected peripherals or interrupts
- * - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the softdevice.
- * - Interrupt latency may be affected by the SoftDevice (see relevant SDS documentation)
- * - Chosen low frequency clock source will be running
- *
- * @param clock_source Low frequency clock source and accuracy. (Note: In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock).
- * @param assertion_handler Callback for SoftDevice assertions.
- *
- * @retval ::NRF_SUCCESS
- * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDeviceinterrupt is already enabled, or an enabled interrupt has an illegal priority level
- * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected
- */
-SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lfclksrc_t clock_source, softdevice_assertion_handler_t assertion_handler));
-
-/**@brief Disables the SoftDevice and by extension the protocol stack.
- *
- * Idempotent function to disable the SoftDevice.
- *
- * @post SoC library and protocol stack APIs are made unavailable.
- * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest).
- * @post All peripherals used by the SoftDevice will be reset to default values.
- * @post All of RAM become available.
- * @post All interrupts are forwarded to the application.
- * @post LFCLK source chosen in ::sd_softdevice_enable will be left running.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void));
-
-/**@brief Check if the SoftDevice is enabled.
- *
- * @param[out] p_softdevice_enabled If the SoftDevice is enabled: 1 else 0.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled));
-
-/**@brief Start forwarding interrupts to application.
- *
- * This function is only intended to be called when a bootloader is enabled is used.
- * The bootloader should call this right before it starts the application.
- * It is recommended that all interrupt sources are off when this is called,
- * or you could end up having interrupts in the application being executed before main() of the application.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_SOFTDEVICE_FORWARD_TO_APPLICATION, uint32_t, sd_softdevice_forward_to_application(void));
-
-/** @} */
-
-#endif // NRF_SDM_H__
-
-/**
- @}
-*/
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/nrf_soc.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,681 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-
-/**
- @defgroup nrf_soc_api SoC Library API
- @{
-
- @brief APIs for the SoC library.
-
-*/
-
-#ifndef NRF_SOC_H__
-#define NRF_SOC_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "nrf_svc.h"
-#include "nrf51.h"
-#include "nrf51_bitfields.h"
-#include "nrf_error_soc.h"
-
-/** @addtogroup NRF_SOC_DEFINES Defines
- * @{ */
-
-/**@brief The number of the lowest SVC number reserved for the SoC library. */
-#define SOC_SVC_BASE 0x20
-
-/**@brief Guranteed time for application to process radio inactive notification. */
-#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US (62)
-
-#define SOC_ECB_KEY_LENGTH (16) /**< ECB key length. */
-#define SOC_ECB_CLEARTEXT_LENGTH (16) /**< ECB cleartext length. */
-#define SOC_ECB_CIPHERTEXT_LENGTH (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */
-
-#define SD_EVENT_IRQn (SWI2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
-#define SD_EVENT_IRQHandler (SWI2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */
-#define RADIO_NOTIFICATION_IRQn (SWI1_IRQn) /**< The radio notification IRQ number. */
-#define RADIO_NOTIFICATION_IRQHandler (SWI1_IRQHandler) /**< The radio notification IRQ handler. */
-
-/** @} */
-
-/** @addtogroup NRF_SOC_TYPES Types
- * @{ */
-
-/**@brief The SVC numbers used by the SVC functions in the SoC library. */
-enum NRF_SOC_SVCS
-{
- SD_MUTEX_NEW = SOC_SVC_BASE,
- SD_MUTEX_ACQUIRE,
- SD_MUTEX_RELEASE,
- SD_NVIC_ENABLEIRQ,
- SD_NVIC_DISABLEIRQ,
- SD_NVIC_GETPENDINGIRQ,
- SD_NVIC_SETPENDINGIRQ,
- SD_NVIC_CLEARPENDINGIRQ,
- SD_NVIC_SETPRIORITY,
- SD_NVIC_GETPRIORITY,
- SD_NVIC_SYSTEMRESET,
- SD_NVIC_CRITICAL_REGION_ENTER,
- SD_NVIC_CRITICAL_REGION_EXIT,
- SD_RAND_APPLICATION_POOL_CAPACITY,
- SD_RAND_APPLICATION_BYTES_AVAILABLE,
- SD_RAND_APPLICATION_GET_VECTOR,
- SD_POWER_MODE_SET,
- SD_POWER_SYSTEM_OFF,
- SD_POWER_RESET_REASON_GET,
- SD_POWER_RESET_REASON_CLR,
- SD_POWER_POF_ENABLE,
- SD_POWER_POF_THRESHOLD_SET,
- SD_POWER_RAMON_SET,
- SD_POWER_RAMON_CLR,
- SD_POWER_RAMON_GET,
- SD_POWER_GPREGRET_SET,
- SD_POWER_GPREGRET_CLR,
- SD_POWER_GPREGRET_GET,
- SD_POWER_DCDC_MODE_SET,
- SD_APP_EVENT_WAIT,
- SD_CLOCK_HFCLK_REQUEST,
- SD_CLOCK_HFCLK_RELEASE,
- SD_CLOCK_HFCLK_IS_RUNNING,
- SD_PPI_CHANNEL_ENABLE_GET,
- SD_PPI_CHANNEL_ENABLE_SET,
- SD_PPI_CHANNEL_ENABLE_CLR,
- SD_PPI_CHANNEL_ASSIGN,
- SD_PPI_GROUP_TASK_ENABLE,
- SD_PPI_GROUP_TASK_DISABLE,
- SD_PPI_GROUP_ASSIGN,
- SD_PPI_GROUP_GET,
- SD_RADIO_NOTIFICATION_CFG_SET,
- SD_ECB_BLOCK_ENCRYPT,
- SD_EVENT_GET,
-
- SVC_SOC_LAST
-};
-
-/**@brief Possible values of a ::nrf_mutex_t. */
-enum NRF_MUTEX_VALUES
-{
- NRF_MUTEX_FREE,
- NRF_MUTEX_TAKEN
-};
-
-/**@brief Possible values of ::nrf_app_irq_priority_t. */
-enum NRF_APP_PRIORITIES
-{
- NRF_APP_PRIORITY_HIGH = 1,
- NRF_APP_PRIORITY_LOW = 3
-};
-
-/**@brief Possible values of ::nrf_power_mode_t. */
-enum NRF_POWER_MODES
-{
- NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */
- NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */
-};
-
-
-/**@brief Possible values of ::nrf_power_failure_threshold_t */
-enum NRF_POWER_THRESHOLDS
-{
- NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */
- NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */
- NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */
- NRF_POWER_THRESHOLD_V27 /**< 2.7 Volts power failure threshold. */
-};
-
-
-/**@brief Possible values of ::nrf_power_dcdc_mode_t. */
-enum NRF_POWER_DCDC_MODES
-{
- NRF_POWER_DCDC_MODE_OFF, /**< The DCDC is always off. */
- NRF_POWER_DCDC_MODE_ON, /**< The DCDC is always on. */
- NRF_POWER_DCDC_MODE_AUTOMATIC /**< The DCDC is automatically managed. */
-};
-
-/**@brief Possible values of ::nrf_radio_notification_distance_t. */
-enum NRF_RADIO_NOTIFICATION_DISTANCES
-{
- NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */
- NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */
- NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */
- NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */
- NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */
- NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */
- NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */
-};
-
-
-/**@brief Possible values of ::nrf_radio_notification_type_t. */
-enum NRF_RADIO_NOTIFICATION_TYPES
-{
- NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */
- NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */
- NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */
- NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */
-};
-
-/**@brief SoC Events. */
-enum NRF_SOC_EVENTS
-{
- NRF_EVENT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */
- NRF_EVENT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */
- NRF_EVENT_NUMBER_OF_EVENTS
-};
-
-/** @} */
-
-/** @addtogroup NRF_SOC_TYPES Types
- * @{ */
-
-/**@brief Represents a mutex for use with the nrf_mutex functions.
- * @note Accessing the value directly is not safe, use the mutex functions!
- */
-typedef volatile uint8_t nrf_mutex_t;
-
-/**@brief The interrupt priorities available to the application while the softdevice is active. */
-typedef uint8_t nrf_app_irq_priority_t;
-
-/**@brief Represents a power mode, used in power mode functions */
-typedef uint8_t nrf_power_mode_t;
-
-/**@brief Represents a power failure threshold value. */
-typedef uint8_t nrf_power_failure_threshold_t;
-
-/**@brief Represents a DCDC mode value. */
-typedef uint32_t nrf_power_dcdc_mode_t;
-
-/**@brief Radio notification distances. */
-typedef uint8_t nrf_radio_notification_distance_t;
-
-/**@brief Radio notification types. */
-typedef uint8_t nrf_radio_notification_type_t;
-
-
-/**@brief AES ECB data structure */
-typedef struct
-{
- uint8_t key[SOC_ECB_KEY_LENGTH]; /**< Encryption key. */
- uint8_t cleartext[SOC_ECB_CLEARTEXT_LENGTH]; /**< Clear Text data. */
- uint8_t ciphertext[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Cipher Text data. */
-} nrf_ecb_hal_data_t;
-
-/** @} */
-
-/** @addtogroup NRF_SOC_FUNCTIONS Functions
- * @{ */
-
-/**@brief Initialize a mutex.
- *
- * @param[in] p_mutex Pointer to the mutex to initialize.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex));
-
-/**@brief Attempt to acquire a mutex.
- *
- * @param[in] p_mutex Pointer to the mutex to acquire.
- *
- * @retval ::NRF_SUCCESS The mutex was successfully acquired.
- * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired.
- */
-SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex));
-
-/**@brief Release a mutex.
- *
- * @param[in] p_mutex Pointer to the mutex to release.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex));
-
-/**@brief Enable External Interrupt.
- * @note Corresponds to NVIC_EnableIRQ in CMSIS.
- *
- * @pre{IRQn is valid and not reserved by the stack}
- *
- * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS.
- *
- * @retval ::NRF_SUCCESS The interrupt was enabled.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application.
- */
-SVCALL(SD_NVIC_ENABLEIRQ, uint32_t, sd_nvic_EnableIRQ(IRQn_Type IRQn));
-
-/**@brief Disable External Interrupt.
- * @note Corresponds to NVIC_DisableIRQ in CMSIS.
- *
- * @pre{IRQn is valid and not reserved by the stack}
- *
- * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS
- *
- * @retval ::NRF_SUCCESS The interrupt was disabled.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
- */
-SVCALL(SD_NVIC_DISABLEIRQ, uint32_t, sd_nvic_DisableIRQ(IRQn_Type IRQn));
-
-/**@brief Get Pending Interrupt.
- * @note Corresponds to NVIC_GetPendingIRQ in CMSIS.
- *
- * @pre{IRQn is valid and not reserved by the stack}
- *
- * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS.
- * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ.
- *
- * @retval ::NRF_SUCCESS The interrupt is available for the application.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
- */
-SVCALL(SD_NVIC_GETPENDINGIRQ, uint32_t, sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq));
-
-/**@brief Set Pending Interrupt.
- * @note Corresponds to NVIC_SetPendingIRQ in CMSIS.
- *
- * @pre{IRQn is valid and not reserved by the stack}
- *
- * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS.
- *
- * @retval ::NRF_SUCCESS The interrupt is set pending.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
- */
-SVCALL(SD_NVIC_SETPENDINGIRQ, uint32_t, sd_nvic_SetPendingIRQ(IRQn_Type IRQn));
-
-/**@brief Clear Pending Interrupt.
- * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS.
- *
- * @pre{IRQn is valid and not reserved by the stack}
- *
- * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS.
- *
- * @retval ::NRF_SUCCESS The interrupt pending flag is cleared.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
- */
-SVCALL(SD_NVIC_CLEARPENDINGIRQ, uint32_t, sd_nvic_ClearPendingIRQ(IRQn_Type IRQn));
-
-/**@brief Set Interrupt Priority.
- * @note Corresponds to NVIC_SetPriority in CMSIS.
- *
- * @pre{IRQn is valid and not reserved by the stack}
- * @pre{priority is valid and not reserved by the stack}
- *
- * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS.
- * @param[in] priority A valid IRQ priority for use by the application.
- *
- * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application.
- */
-SVCALL(SD_NVIC_SETPRIORITY, uint32_t, sd_nvic_SetPriority(IRQn_Type IRQn, nrf_app_irq_priority_t priority));
-
-/**@brief Get Interrupt Priority.
- * @note Corresponds to NVIC_GetPriority in CMSIS.
- *
- * @pre{IRQn is valid and not reserved by the stack}
- *
- * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS.
- * @param[out] p_priority Return value from NVIC_GetPriority.
- *
- * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application.
- */
-SVCALL(SD_NVIC_GETPRIORITY, uint32_t, sd_nvic_GetPriority(IRQn_Type IRQn, nrf_app_irq_priority_t * p_priority));
-
-/**@brief System Reset.
- * @note Corresponds to NVIC_SystemReset in CMSIS.
- *
- * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN
- */
-SVCALL(SD_NVIC_SYSTEMRESET, uint32_t, sd_nvic_SystemReset(void));
-
-/**@brief Enters critical region.
- *
- * @post Application interrupts will be disabled.
- * @sa sd_nvic_critical_region_exit
- *
- * @param[out] p_is_nested_critical_region 1: If in a nested critical region.
- * 0: Otherwise.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_NVIC_CRITICAL_REGION_ENTER, uint32_t, sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region));
-
-/**@brief Exit critical region.
- *
- * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter.
- * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called.
- *
- * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_NVIC_CRITICAL_REGION_EXIT, uint32_t, sd_nvic_critical_region_exit(uint8_t is_nested_critical_region));
-
-/**@brief Query the capacity of the application random pool.
- *
- * @param[out] p_pool_capacity The capacity of the pool.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity));
-
-/**@brief Get number of random bytes available to the application.
- *
- * @param[out] p_bytes_available The number of bytes currently available in the pool.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available));
-
-/**@brief Get random bytes from the application pool.
-
- @param[out] p_buff Pointer to unit8_t buffer for storing the bytes.
- @param[in] length Number of bytes to take from pool and place in p_buff.
-
- @retval ::NRF_SUCCESS The requested bytes were written to p_buff.
- @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available.
-*/
-SVCALL(SD_RAND_APPLICATION_GET_VECTOR, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length));
-
-/**@brief Gets the reset reason register.
- *
- * @param[out] p_reset_reason Contents of the NRF_POWER->RESETREAS register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason));
-
-/**@brief Clears the bits of the reset reason register.
- *
- * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk));
-
-/**@brief Sets the power mode when in CPU sleep.
- *
- * @param[in] power_mode The power mode to use when in CPU sleep. @sa sd_app_event_wait
- *
- * @retval ::NRF_SUCCESS The power mode was set.
- * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown.
- */
-SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(nrf_power_mode_t power_mode));
-
-/**@brief Puts the chip in System OFF mode.
- *
- * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN
- */
-SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void));
-
-/**@brief Enables or disables the power-fail comparator.
- *
- * Enabling this will give a softdevice event (NRF_EVENT_POWER_FAILURE_WARNING) when the power failure warning occurs.
- * The event can be retrived with sd_event_get();
- *
- * @param[in] pof_enable True if the power-fail comparator should be enabled, false if it should be disabled.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable));
-
-/**@brief Sets the power-fail threshold value.
- *
- * @param[in] threshold The power-fail threshold value to use.
- *
- * @retval ::NRF_SUCCESS The power failure threshold was set.
- * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown.
- */
-SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(nrf_power_failure_threshold_t threshold));
-
-/**@brief Sets bits in the NRF_POWER->RAMON register.
- *
- * @param[in] ramon Contains the bits needed to be set in the NRF_POWER->RAMON register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RAMON_SET, uint32_t, sd_power_ramon_set(uint32_t ramon));
-
-/** @brief Clears bits in the NRF_POWER->RAMON register.
- *
- * @param ramon Contains the bits needed to be cleared in the NRF_POWER->RAMON register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RAMON_CLR, uint32_t, sd_power_ramon_clr(uint32_t ramon));
-
-/**@brief Get contents of NRF_POWER->RAMON register, indicates power status of ram blocks.
- *
- * @param[out] p_ramon Content of NRF_POWER->RAMON register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RAMON_GET, uint32_t, sd_power_ramon_get(uint32_t * p_ramon));
-
-/**@brief Set bits in the NRF_POWER->GPREGRET register.
- *
- * @param[in] gpregret_msk Bits to be set in the GPREGRET register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_msk));
-
-/**@brief Clear bits in the NRF_POWER->GPREGRET register.
- *
- * @param[in] gpregret_msk Bits to be clear in the GPREGRET register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_msk));
-
-/**@brief Get contents of the NRF_POWER->GPREGRET register.
- *
- * @param[out] p_gpregret Contents of the GPREGRET register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t *p_gpregret));
-
-/**@brief Sets the DCDC mode.
- *
- * Depending on the internal state of the SoftDevice, the mode change may not happen immediately.
- * The DCDC mode switch will be blocked when occuring in close proximity to radio transmissions. When
- * the radio transmission is done, the last mode will be used.
- *
- * @param[in] dcdc_mode The mode of the DCDC.
- *
- * @retval ::NRF_SUCCESS
- * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid.
- */
-SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(nrf_power_dcdc_mode_t dcdc_mode));
-
-/**@brief Request the high frequency crystal oscillator.
- *
- * Will start the high frequency crystal oscillator, the startup time of the crystal varies
- * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started.
- *
- * @see sd_clock_hfclk_is_running
- * @see sd_clock_hfclk_release
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void));
-
-/**@brief Releases the high frequency crystal oscillator.
- *
- * Will stop the high frequency crystal oscillator, this happens immediately.
- *
- * @see sd_clock_hfclk_is_running
- * @see sd_clock_hfclk_request
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void));
-
-/**@brief Checks if the high frequency crystal oscillator is running.
- *
- * @see sd_clock_hfclk_request
- * @see sd_clock_hfclk_release
- *
- * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running));
-
-/**@brief Waits for an application event.
- *
- * An application event is either an application interrupt or a pended interrupt when the
- * interrupt is disabled. When the interrupt is enabled it will be taken immediately since
- * this function will wait in thread mode, then the execution will return in the application's
- * main thread. When an interrupt is disabled and gets pended it will return to the application's
- * thread main. The application must ensure that the pended flag is cleared using
- * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for
- * disabled interrupts, as the interrupt handler will clear the pending flag automatically for
- * enabled interrupts.
- *
- * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0
- * System Control Register (SCR). @sa CMSIS_SCB
- *
- * @note If an application interrupt has happened since the last time sd_app_event_wait was
- * called this function will return immediately and not go to sleep. This is to avoid race
- * conditions that can occur when a flag is updated in the interrupt handler and processed
- * in the main loop.
- *
- * @post An application interrupt has happened or a interrupt pending flag is set.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_APP_EVENT_WAIT, uint32_t, sd_app_event_wait(void));
-
-/**@brief Get PPI channel enable register contents.
- *
- * @param[out] p_channel_enable The contents of the PPI CHEN register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable));
-
-/**@brief Set PPI channel enable register.
- *
- * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk));
-
-/**@brief Clear PPI channel enable register.
- *
- * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk));
-
-/**@brief Assign endpoints to a PPI channel.
- *
- * @param[in] channel_num Number of the PPI channel to assign.
- * @param[in] event_endpoint Event endpoint of the PPI channel.
- * @param[in] task_endpoint Task endpoint of the PPI channel.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * event_endpoint, const volatile void * task_endpoint));
-
-/**@brief Task to enable a channel group.
- *
- * @param[in] group_num Number of the channel group.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num));
-
-/**@brief Task to disable a channel group.
- *
- * @param[in] group_num Number of the PPI group.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num));
-
-/**@brief Assign PPI channels to a channel group.
- *
- * @param[in] group_num Number of the channel group.
- * @param[in] channel_msk Mask of the channels to assign to the group.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk));
-
-/**@brief Gets the PPI channels of a channel group.
- *
- * @param[in] group_num Number of the channel group.
- * @param[out] p_channel_msk Mask of the channels assigned to the group.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk));
-
-/**@brief Configures the Radio Notification signal.
- *
- * @note
- * - The notification signal latency depends on the interrupt priority settings of SWI used
- * for notification signal.
- * - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice
- * will interrupt the application to do Radio Event preparation.
- * - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have
- * to shorten the connection events to have time for the Radio Notification signals.
- *
- * @param[in] type Type of notification signal.
- * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio
- * notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is
- * recommended (but not required) to be used with
- * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE.
- *
- * @param[in] distance Distance between the notification signal and start of radio activity.
- * This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or
- * @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used.
- *
- * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(nrf_radio_notification_type_t type, nrf_radio_notification_distance_t distance));
-
-/**@brief Encrypts a block according to the specified parameters.
- *
- * 128-bit AES encryption.
- *
- * @param[in, out] p_ecb_data Pointer to the ECB paramters' struct (two input
- * parameters and one output parameter).
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data));
-
-/**@brief Gets any pending events generated by the SoC API.
- *
- * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned.
- *
- * @param[out] p_event Set to the event number, if any events are pending.
- *
- * @retval ::NRF_SUCCESS An event was pending. The event number is written in the p_event paramer.
- * @retval ::NRF_ERROR_NOT_FOUND No pending events.
- */
-SVCALL(SD_EVENT_GET, uint32_t, sd_event_get(uint32_t *p_event));
-
-/** @} */
-
-#endif // NRF_SOC_H__
-
-/**
- @}
- */
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/nrf_svc.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-#ifndef NRF_SVC__
-#define NRF_SVC__
-
-#ifdef SVCALL_AS_NORMAL_FUNCTION
-#define SVCALL(number, return_type, signature) return_type signature
-#else
-
-#ifndef SVCALL
-#if defined (__CC_ARM)
-#define SVCALL(number, return_type, signature) return_type __svc(number) signature
-#elif defined (__GNUC__)
-#define SVCALL(number, return_type, signature) \
- _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \
- _Pragma("GCC diagnostic ignored \"-Wunused-function\"") \
- __attribute__((naked)) static return_type signature \
- { \
- __asm( \
- "svc %0\n" \
- "bx r14" : : "I" (number) : "r0" \
- ); \
- }
-#elif defined (__ICCARM__)
-#define PRAGMA(x) _Pragma(#x)
-#define SVCALL(number, return_type, signature) \
-PRAGMA(swi_number = number) \
- __swi return_type signature;
-#else
-#define SVCALL(number, return_type, signature) return_type signature
-#endif
-#endif // SVCALL
-
-#endif // SVCALL_AS_NORMAL_FUNCTION
-#endif // NRF_SVC__
--- a/hw/nRF51822n/nordic/nrf-sdk/s120/softdevice_assert.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic Semiconductor. The use,
- * copying, transfer or disclosure of such information is prohibited except by express written
- * agreement with Nordic Semiconductor.
- *
- */
-
-/** @brief Utilities for verifying program logic
- */
-
-#ifndef SOFTDEVICE_ASSERT_H_
-#define SOFTDEVICE_ASSERT_H_
-
-#include <stdint.h>
-
-/** @brief This function handles assertions.
- *
- *
- * @note
- * This function is called when an assertion has triggered.
- *
- *
- * @param line_num The line number where the assertion is called
- * @param file_name Pointer to the file name
- */
-void assert_softdevice_callback(uint16_t line_num, const uint8_t *file_name);
-
-
-/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */
-/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \
-/** @brief Check intended for production code
- *
- * Check passes if "expr" evaluates to true. */
-#define ASSERT(expr) \
-if (expr) \
-{ \
-} \
-else \
-{ \
- assert_softdevice_callback((uint16_t)__LINE__, (uint8_t *)__FILE__); \
- /*lint -unreachable */ \
-}
-
-#endif /* SOFTDEVICE_ASSERT_H_ */
--- a/hw/nRF51822n/nordic/nrf-sdk/simple_uart.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,73 +0,0 @@
- /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef SIMPLE_UART_H
-#define SIMPLE_UART_H
-
-/*lint ++flb "Enter library region" */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "nordic_global.h"
-
-/** @file
-* @brief Simple UART driver
-*
-*
-* @defgroup nrf_drivers_simple_uart Simple UART driver
-* @{
-* @ingroup nrf_drivers
-* @brief Simple UART driver
-*/
-
-/** @brief Function for reading a character from UART.
-Execution is blocked until UART peripheral detects character has been received.
-\return cr Received character.
-*/
-uint8_t simple_uart_get(void);
-
-/** @brief Function for reading a character from UART with timeout on how long to wait for the byte to be received.
-Execution is blocked until UART peripheral detects character has been received or until the timeout expires, which even occurs first
-\return bool True, if byte is received before timeout, else returns False.
-@param timeout_ms maximum time to wait for the data.
-@param rx_data pointer to the memory where the received data is stored.
-*/
-bool simple_uart_get_with_timeout(int32_t timeout_ms, uint8_t *rx_data);
-
-/** @brief Function for sending a character to UART.
-Execution is blocked until UART peripheral reports character to have been send.
-@param cr Character to send.
-*/
-void simple_uart_put(uint8_t cr);
-
-/** @brief Function for sending a string to UART.
-Execution is blocked until UART peripheral reports all characters to have been send.
-Maximum string length is 254 characters including null character in the end.
-@param str Null terminated string to send.
-*/
-void simple_uart_putstring(const uint8_t *str);
-
-/** @brief Function for configuring UART to use 38400 baud rate.
-@param rts_pin_number Chip pin number to be used for UART RTS
-@param txd_pin_number Chip pin number to be used for UART TXD
-@param cts_pin_number Chip pin number to be used for UART CTS
-@param rxd_pin_number Chip pin number to be used for UART RXD
-@param hwfc Enable hardware flow control
-*/
-void simple_uart_config(uint8_t rts_pin_number, uint8_t txd_pin_number, uint8_t cts_pin_number, uint8_t rxd_pin_number, bool hwfc);
-
-/**
- *@}
- **/
-
-/*lint --flb "Leave library region" */
-#endif
--- a/hw/nRF51822n/nordic/nrf-sdk/spi_master.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
- /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef SPI_MASTER_H
-#define SPI_MASTER_H
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "nordic_global.h"
-
-/** @file
-* @brief Software controlled SPI Master driver.
-*
-*
-* @defgroup lib_driver_spi_master Software controlled SPI Master driver
-* @{
-* @ingroup nrf_drivers
-* @brief Software controlled SPI Master driver.
-*
-* Supported features:
-* - Operate two SPI masters independently or in parallel.
-* - Transmit and Receive given size of data through SPI.
-* - configure each SPI module separately through @ref spi_master_init.
-*/
-
-/**
- * SPI master operating frequency
- */
-typedef enum
-{
- Freq_125Kbps = 0, /*!< drive SClk with frequency 125Kbps */
- Freq_250Kbps, /*!< drive SClk with frequency 250Kbps */
- Freq_500Kbps, /*!< drive SClk with frequency 500Kbps */
- Freq_1Mbps, /*!< drive SClk with frequency 1Mbps */
- Freq_2Mbps, /*!< drive SClk with frequency 2Mbps */
- Freq_4Mbps, /*!< drive SClk with frequency 4Mbps */
- Freq_8Mbps /*!< drive SClk with frequency 8Mbps */
-} SPIFrequency_t;
-
-/**
- * SPI master module number
- */
-typedef enum
-{
- SPI0 = 0, /*!< SPI module 0 */
- SPI1 /*!< SPI module 1 */
-} SPIModuleNumber;
-
-/**
- * SPI mode
- */
-typedef enum
-{
- //------------------------Clock polarity 0, Clock starts with level 0-------------------------------------------
- SPI_MODE0 = 0, /*!< Sample data at rising edge of clock and shift serial data at falling edge */
- SPI_MODE1, /*!< sample data at falling edge of clock and shift serial data at rising edge */
- //------------------------Clock polarity 1, Clock starts with level 1-------------------------------------------
- SPI_MODE2, /*!< sample data at falling edge of clock and shift serial data at rising edge */
- SPI_MODE3 /*!< Sample data at rising edge of clock and shift serial data at falling edge */
-} SPIMode;
-
-
-/**
- * @brief Function for initializing given SPI master with given configuration.
- *
- * After initializing the given SPI master with given configuration, this function also test if the
- * SPI slave is responding with the configurations by transmitting few test bytes. If the slave did not
- * respond then error is returned and contents of the rx_data are invalid.
- *
- * @param module_number SPI master number (SPIModuleNumber) to initialize.
- * @param mode SPI master mode (mode 0, 1, 2 or 3 from SPIMode)
- * @param lsb_first true if lsb is first bit to shift in/out as serial data on MISO/MOSI pins.
- * @return
- * @retval pointer to direct physical address of the requested SPI module if init was successful
- * @retval 0, if either init failed or slave did not respond to the test transfer
- */
-uint32_t* spi_master_init(SPIModuleNumber module_number, SPIMode mode, bool lsb_first);
-
-/**
- * @brief Function for transferring/receiving data over SPI bus.
- *
- * If TWI master detects even one NACK from the slave or timeout occurs, STOP condition is issued
- * and the function returns false.
- *
- * @note Make sure at least transfer_size number of bytes is allocated in tx_data/rx_data.
- *
- * @param spi_base_address register base address of the selected SPI master module
- * @param transfer_size number of bytes to transmit/receive over SPI master
- * @param tx_data pointer to the data that needs to be transmitted
- * @param rx_data pointer to the data that needs to be received
- * @return
- * @retval true if transmit/reveive of transfer_size were completed.
- * @retval false if transmit/reveive of transfer_size were not complete and tx_data/rx_data points to invalid data.
- */
-bool spi_master_tx_rx(uint32_t *spi_base_address, uint16_t transfer_size, const uint8_t *tx_data, uint8_t *rx_data);
-
-/**
- *@}
- **/
-
-#endif /* SPI_MASTER_H */
--- a/hw/nRF51822n/nordic/nrf-sdk/spi_slave.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,137 +0,0 @@
-/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/**@file
- *
- * @defgroup lib_driver_spi_slave Software controlled SPI Slave driver.
- * @{
- * @ingroup nrf_drivers
- *
- * @brief Software controlled SPI Slave driver.
- */
-
-#ifndef SPI_SLAVE_H__
-#define SPI_SLAVE_H__
-
-#include <stdint.h>
-#include "nordic_global.h"
-#include "nrf_error.h"
-
-/**@brief SPI transaction bit order definitions. */
-typedef enum
-{
- SPIM_LSB_FIRST, /**< Least significant bit shifted out first. */
- SPIM_MSB_FIRST /**< Most significant bit shifted out first. */
-} spi_slave_endian_t;
-
-/**@brief SPI mode definitions for clock polarity and phase. */
-typedef enum
-{
- SPI_MODE_0, /**< (CPOL = 0, CPHA = 0). */
- SPI_MODE_1, /**< (CPOL = 0, CPHA = 1). */
- SPI_MODE_2, /**< (CPOL = 1, CPHA = 0). */
- SPI_MODE_3 /**< (CPOL = 1, CPHA = 1). */
-} spi_slave_mode_t;
-
-/**@brief SPI peripheral device configuration data. */
-typedef struct
-{
- uint32_t pin_miso; /**< SPI MISO pin. */
- uint32_t pin_mosi; /**< SPI MOSI pin. */
- uint32_t pin_sck; /**< SPI SCK pin. */
- uint32_t pin_csn; /**< SPI CSN pin. */
- spi_slave_mode_t mode; /**< SPI mode. */
- spi_slave_endian_t bit_order; /**< SPI transaction bit order. */
- uint8_t def_tx_character; /**< Device configuration mode default character (DEF). Character clocked out in case of an ignored transaction. */
- uint8_t orc_tx_character; /**< Device configuration mode over-read character. Character clocked out after an over-read of the transmit buffer. */
-} spi_slave_config_t;
-
-/**@brief Event callback function event definitions. */
-typedef enum
-{
- SPI_SLAVE_BUFFERS_SET_DONE, /**< Memory buffer set event. Memory buffers have been set successfully to the SPI slave device and SPI transactions can be done. */
- SPI_SLAVE_XFER_DONE, /**< SPI transaction event. SPI transaction has been completed. */
- SPI_SLAVE_EVT_TYPE_MAX /**< Enumeration upper bound. */
-} spi_slave_evt_type_t;
-
-/**@brief Struct containing event context from the SPI slave driver. */
-typedef struct
-{
- spi_slave_evt_type_t evt_type; /**< Type of event. */
- uint32_t rx_amount; /**< Number of bytes received in last transaction (parameter is only valid upon @ref SPI_SLAVE_XFER_DONE event). */
- uint32_t tx_amount; /**< Number of bytes transmitted in last transaction (parameter is only valid upon @ref SPI_SLAVE_XFER_DONE event). */
-} spi_slave_evt_t;
-
-/**@brief SPI slave event callback function type.
- *
- * @param[in] event SPI slave driver event.
- */
-typedef void (*spi_slave_event_handler_t)(spi_slave_evt_t event);
-
-/**@brief Function for registering a handler for SPI slave driver event.
- *
- * @note Multiple registration requests will overwrite any possible existing registration.
- *
- * @param[in] event_handler The function to be called by the SPI slave driver upon event.
- *
- * @retval NRF_SUCCESS Operation success.
- * @retval NRF_ERROR_NULL Operation success. NULL handler registered.
- */
-uint32_t spi_slave_evt_handler_register(spi_slave_event_handler_t event_handler);
-
-/**@brief Function for initializing the SPI slave device.
- *
- * @param[in] p_spi_slave_config SPI peripheral device configuration data.
- *
- * @retval NRF_SUCCESS Operation success.
- * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
- * @retval NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter supplied.
- */
-uint32_t spi_slave_init(const spi_slave_config_t * p_spi_slave_config);
-
-/**@brief Function for preparing the SPI slave device ready for a single SPI transaction.
- *
- * Function prepares the SPI slave device to be ready for a single SPI transaction. It configures
- * the SPI slave device to use the memory, supplied with the function call, in SPI transactions.
- *
- * The @ref spi_slave_event_handler_t will be called with appropriate event @ref
- * spi_slave_evt_type_t when either the memory buffer configuration or SPI transaction has been
- * completed.
- *
- * @note The callback function @ref spi_slave_event_handler_t can be called before returning from
- * this function, since it is called from the SPI slave interrupt context.
- *
- * @note This function can be called from the callback function @ref spi_slave_event_handler_t
- * context.
- *
- * @note Client application must call this function after every @ref SPI_SLAVE_XFER_DONE event if it
- * wants the SPI slave driver to be ready for possible new SPI transaction.
- *
- * @param[in] p_tx_buf Pointer to the TX buffer.
- * @param[in] p_rx_buf Pointer to the RX buffer.
- * @param[in] tx_buf_length Length of the TX buffer in bytes.
- * @param[in] rx_buf_length Length of the RX buffer in bytes.
- *
- * @retval NRF_SUCCESS Operation success.
- * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
- * @retval NRF_ERROR_INVALID_STATE Operation failure. SPI slave device in incorrect state.
- * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
- */
-uint32_t spi_slave_buffers_set(uint8_t * p_tx_buf,
- uint8_t * p_rx_buf,
- uint8_t tx_buf_length,
- uint8_t rx_buf_length);
-
-
-#endif // SPI_SLAVE_H__
-
-/** @} */
--- a/hw/nRF51822n/nordic/nrf-sdk/twi_master.h Thu Feb 13 11:27:58 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,100 +0,0 @@
- /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef TWI_MASTER_H
-#define TWI_MASTER_H
-
-/*lint ++flb "Enter library region" */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "nordic_global.h"
-
-/** @file
-* @brief Software controlled TWI Master driver.
-*
-*
-* @defgroup lib_driver_twi_master Software controlled TWI Master driver
-* @{
-* @ingroup nrf_drivers
-* @brief Software controlled TWI Master driver.
-*
-* Supported features:
-* - Repeated start
-* - No multi-master
-* - Only 7-bit addressing
-* - Supports clock stretching (with optional SMBus style slave timeout)
-* - Tries to handle slaves stuck in the middle of transfer
-*/
-
-#define TWI_READ_BIT (0x01) //!< If this bit is set in the address field, transfer direction is from slave to master.
-
-#define TWI_ISSUE_STOP ((bool)true) //!< Parameter for @ref twi_master_transfer
-#define TWI_DONT_ISSUE_STOP ((bool)false) //!< Parameter for @ref twi_master_transfer
-
-/* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */
-/*lint -e717 -save "Suppress do {} while (0) for these macros" */
-/*lint ++flb "Enter library region" */
-#define TWI_SCL_HIGH() do { NRF_GPIO->OUTSET = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Pulls SCL line high */
-#define TWI_SCL_LOW() do { NRF_GPIO->OUTCLR = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Pulls SCL line low */
-#define TWI_SDA_HIGH() do { NRF_GPIO->OUTSET = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Pulls SDA line high */
-#define TWI_SDA_LOW() do { NRF_GPIO->OUTCLR = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Pulls SDA line low */
-#define TWI_SDA_INPUT() do { NRF_GPIO->DIRCLR = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Configures SDA pin as input */
-#define TWI_SDA_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Configures SDA pin as output */
-#define TWI_SCL_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Configures SCL pin as output */
-/*lint -restore */
-
-#define TWI_SDA_READ() ((NRF_GPIO->IN >> TWI_MASTER_CONFIG_DATA_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SDA */
-#define TWI_SCL_READ() ((NRF_GPIO->IN >> TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SCL */
-
-#define TWI_DELAY() nrf_delay_us(4) /*!< Time to wait when pin states are changed. For fast-mode the delay can be zero and for standard-mode 4 us delay is sufficient. */
-
-
-/**
- * @brief Function for initializing TWI bus IO pins and checks if the bus is operational.
- *
- * Both pins are configured as Standard-0, No-drive-1 (open drain).
- *
- * @return
- * @retval true TWI bus is clear for transfers.
- * @retval false TWI bus is stuck.
- */
-bool twi_master_init(void);
-
-/**
- * @brief Function for transferring data over TWI bus.
- *
- * If TWI master detects even one NACK from the slave or timeout occurs, STOP condition is issued
- * and the function returns false.
- * Bit 0 (@ref TWI_READ_BIT) in the address parameter controls transfer direction;
- * - If 1, master reads data_length number of bytes from the slave
- * - If 0, master writes data_length number of bytes to the slave.
- *
- * @note Make sure at least data_length number of bytes is allocated in data if TWI_READ_BIT is set.
- * @note @ref TWI_ISSUE_STOP
- *
- * @param address Data transfer direction (LSB) / Slave address (7 MSBs).
- * @param data Pointer to data.
- * @param data_length Number of bytes to transfer.
- * @param issue_stop_condition If @ref TWI_ISSUE_STOP, STOP condition is issued before exiting function. If @ref TWI_DONT_ISSUE_STOP, STOP condition is not issued before exiting function. If transfer failed for any reason, STOP condition will be issued in any case.
- * @return
- * @retval true Data transfer succeeded without errors.
- * @retval false Data transfer failed.
- */
-bool twi_master_transfer(uint8_t address, uint8_t *data, uint8_t data_length, bool issue_stop_condition);
-
-/**
- *@}
- **/
-
-/*lint --flb "Leave library region" */
-#endif //TWI_MASTER_H