mbed library sources
Dependents: STM32F103C8T6-RangoTec STM32-103C8_Plantilla_USB
Revision 401:7fa56b1b9d45, committed 2014-11-13
- Comitter:
- mbed_official
- Date:
- Thu Nov 13 08:30:07 2014 +0000
- Parent:
- 400:7c3047f858e1
- Child:
- 402:6d559ae9fd59
- Commit message:
- Synchronized with git revision 08c85ef1361a8a0c66ab4c27be8f4fd9f032a14c
Full URL: https://github.com/mbedmicro/mbed/commit/08c85ef1361a8a0c66ab4c27be8f4fd9f032a14c/
Platform: Add support for MultiTech mDot module
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_MICRO/startup_stm32f405xx.s Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,413 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f405xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F405xx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_MICRO/stm32f405xx.sct Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F405RG: 1024KB FLASH + 128KB SRAM +LR_IROM1 0x08000000 0x100000 { ; load region size_region + + ER_IROM1 0x08000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x20000000+0x188) (0x20000-0x188) { ; RW data + .ANY (+RW +ZI) + } + +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_MICRO/sys.cpp Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rt_misc.h> +#include <stdint.h> + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_STD/startup_stm32f405xx.s Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,387 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f405xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F405xx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_STD/stm32f405xx.sct Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F405RG: 1024KB FLASH + 128KB SRAM +LR_IROM1 0x08000000 0x100000 { ; load region size_region + + ER_IROM1 0x08000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x20000000+0x188) (0x20000-0x188) { ; RW data + .ANY (+RW +ZI) + } + +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rt_misc.h> +#include <stdint.h> + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_GCC_ARM/STM32F405.ld Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,151 @@ +/* Linker script for STM32F405 */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 128K - 0x188 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_GCC_ARM/startup_STM32F40x.s Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,316 @@ +/* File: startup_STM32F40x.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 09 July 2012 + * + * Copyright (c) 2011, 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WWDG_IRQHandler /* Window WatchDog */ + .long PVD_IRQHandler /* PVD through EXTI Line detection */ + .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .long FLASH_IRQHandler /* FLASH */ + .long RCC_IRQHandler /* RCC */ + .long EXTI0_IRQHandler /* EXTI Line0 */ + .long EXTI1_IRQHandler /* EXTI Line1 */ + .long EXTI2_IRQHandler /* EXTI Line2 */ + .long EXTI3_IRQHandler /* EXTI Line3 */ + .long EXTI4_IRQHandler /* EXTI Line4 */ + .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .long CAN1_TX_IRQHandler /* CAN1 TX */ + .long CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .long CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .long CAN1_SCE_IRQHandler /* CAN1 SCE */ + .long EXTI9_5_IRQHandler /* External Line[9:5]s */ + .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .long TIM2_IRQHandler /* TIM2 */ + .long TIM3_IRQHandler /* TIM3 */ + .long TIM4_IRQHandler /* TIM4 */ + .long I2C1_EV_IRQHandler /* I2C1 Event */ + .long I2C1_ER_IRQHandler /* I2C1 Error */ + .long I2C2_EV_IRQHandler /* I2C2 Event */ + .long I2C2_ER_IRQHandler /* I2C2 Error */ + .long SPI1_IRQHandler /* SPI1 */ + .long SPI2_IRQHandler /* SPI2 */ + .long USART1_IRQHandler /* USART1 */ + .long USART2_IRQHandler /* USART2 */ + .long USART3_IRQHandler /* USART3 */ + .long EXTI15_10_IRQHandler /* External Line[15:10]s */ + .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .long FSMC_IRQHandler /* FSMC */ + .long SDIO_IRQHandler /* SDIO */ + .long TIM5_IRQHandler /* TIM5 */ + .long SPI3_IRQHandler /* SPI3 */ + .long UART4_IRQHandler /* UART4 */ + .long UART5_IRQHandler /* UART5 */ + .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .long TIM7_IRQHandler /* TIM7 */ + .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long CAN2_TX_IRQHandler /* CAN2 TX */ + .long CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .long CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .long CAN2_SCE_IRQHandler /* CAN2 SCE */ + .long OTG_FS_IRQHandler /* USB OTG FS */ + .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .long USART6_IRQHandler /* USART6 */ + .long I2C3_EV_IRQHandler /* I2C3 event */ + .long I2C3_ER_IRQHandler /* I2C3 error */ + .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .long OTG_HS_IRQHandler /* USB OTG HS */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long HASH_RNG_IRQHandler /* Hash and Rng */ + .long FPU_IRQHandler /* FPU */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler WWDG_IRQHandler + def_irq_default_handler PVD_IRQHandler + def_irq_default_handler TAMP_STAMP_IRQHandler + def_irq_default_handler RTC_WKUP_IRQHandler + def_irq_default_handler FLASH_IRQHandler + def_irq_default_handler RCC_IRQHandler + def_irq_default_handler EXTI0_IRQHandler + def_irq_default_handler EXTI1_IRQHandler + def_irq_default_handler EXTI2_IRQHandler + def_irq_default_handler EXTI3_IRQHandler + def_irq_default_handler EXTI4_IRQHandler + def_irq_default_handler DMA1_Stream0_IRQHandler + def_irq_default_handler DMA1_Stream1_IRQHandler + def_irq_default_handler DMA1_Stream2_IRQHandler + def_irq_default_handler DMA1_Stream3_IRQHandler + def_irq_default_handler DMA1_Stream4_IRQHandler + def_irq_default_handler DMA1_Stream5_IRQHandler + def_irq_default_handler DMA1_Stream6_IRQHandler + def_irq_default_handler ADC_IRQHandler + def_irq_default_handler CAN1_TX_IRQHandler + def_irq_default_handler CAN1_RX0_IRQHandler + def_irq_default_handler CAN1_RX1_IRQHandler + def_irq_default_handler CAN1_SCE_IRQHandler + def_irq_default_handler EXTI9_5_IRQHandler + def_irq_default_handler TIM1_BRK_TIM9_IRQHandler + def_irq_default_handler TIM1_UP_TIM10_IRQHandler + def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler + def_irq_default_handler TIM1_CC_IRQHandler + def_irq_default_handler TIM2_IRQHandler + def_irq_default_handler TIM3_IRQHandler + def_irq_default_handler TIM4_IRQHandler + def_irq_default_handler I2C1_EV_IRQHandler + def_irq_default_handler I2C1_ER_IRQHandler + def_irq_default_handler I2C2_EV_IRQHandler + def_irq_default_handler I2C2_ER_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler SPI2_IRQHandler + def_irq_default_handler USART1_IRQHandler + def_irq_default_handler USART2_IRQHandler + def_irq_default_handler USART3_IRQHandler + def_irq_default_handler EXTI15_10_IRQHandler + def_irq_default_handler RTC_Alarm_IRQHandler + def_irq_default_handler OTG_FS_WKUP_IRQHandler + def_irq_default_handler TIM8_BRK_TIM12_IRQHandler + def_irq_default_handler TIM8_UP_TIM13_IRQHandler + def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler + def_irq_default_handler TIM8_CC_IRQHandler + def_irq_default_handler DMA1_Stream7_IRQHandler + def_irq_default_handler FSMC_IRQHandler + def_irq_default_handler SDIO_IRQHandler + def_irq_default_handler TIM5_IRQHandler + def_irq_default_handler SPI3_IRQHandler + def_irq_default_handler UART4_IRQHandler + def_irq_default_handler UART5_IRQHandler + def_irq_default_handler TIM6_DAC_IRQHandler + def_irq_default_handler TIM7_IRQHandler + def_irq_default_handler DMA2_Stream0_IRQHandler + def_irq_default_handler DMA2_Stream1_IRQHandler + def_irq_default_handler DMA2_Stream2_IRQHandler + def_irq_default_handler DMA2_Stream3_IRQHandler + def_irq_default_handler DMA2_Stream4_IRQHandler + def_irq_default_handler CAN2_TX_IRQHandler + def_irq_default_handler CAN2_RX0_IRQHandler + def_irq_default_handler CAN2_RX1_IRQHandler + def_irq_default_handler CAN2_SCE_IRQHandler + def_irq_default_handler OTG_FS_IRQHandler + def_irq_default_handler DMA2_Stream5_IRQHandler + def_irq_default_handler DMA2_Stream6_IRQHandler + def_irq_default_handler DMA2_Stream7_IRQHandler + def_irq_default_handler USART6_IRQHandler + def_irq_default_handler I2C3_EV_IRQHandler + def_irq_default_handler I2C3_ER_IRQHandler + def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler + def_irq_default_handler OTG_HS_EP1_IN_IRQHandler + def_irq_default_handler OTG_HS_WKUP_IRQHandler + def_irq_default_handler OTG_HS_IRQHandler + def_irq_default_handler HASH_RNG_IRQHandler + def_irq_default_handler FPU_IRQHandler + def_irq_default_handler DEF_IRQHandler + + .end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_IAR/startup_stm32f405xx.s Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,623 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f405xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F405xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and RNG + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_IAR/stm32f405xx.icf Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,37 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +/* [RAM] Vector table dynamic copy: 98 vectors * 4 bytes = 392 bytes (0x188) */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000187; /* to be aligned on 8 bytes */ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000188; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/cmsis.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/cmsis_nvic.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; i<NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/cmsis_nvic.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F405RG +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to ... +// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM +#define NVIC_NUM_VECTORS 98 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/hal_tick.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/hal_tick.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,7349 @@ +/** + ****************************************************************************** + * @file stm32f405xx.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f405xx + * @{ + */ + +#ifndef __STM32F405xx_H +#define __STM32F405xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include <stdint.h> + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ + uint32_t RESERVED1; /*!< Reserved, 0x78 */ + uint32_t RESERVED2; /*!< Reserved, 0x7C */ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED3; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank2_3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + + + +/** + * @brief __USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */ + uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */ + __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */ + uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} +USB_OTG_GlobalTypeDef; + + + +/** + * @brief __device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ + __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */ + uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */ + __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */ + uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */ + uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */ + __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ + uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ + uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ +} +USB_OTG_DeviceTypeDef; + + +/** + * @brief __IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} +USB_OTG_INEndpointTypeDef; + + +/** + * @brief __OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} +USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief __Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} +USB_OTG_HostTypeDef; + + +/** + * @brief __Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} +USB_OTG_HostChannelTypeDef; + + +/** + * @brief Peripheral_memory_map + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */ +#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + +/*!< AHB2 peripherals */ +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) +#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) + +#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) +#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) +#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) +#define USB_OTG_HOST_BASE ((uint32_t )0x400) +#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) +#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) +#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) +#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */ +#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */ +#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */ +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */ +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */ +#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */ + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */ +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */ +#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */ +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */ +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */ +#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */ +#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */ +#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */ +#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */ +#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */ +#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */ +#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */ +#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ +#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */ +#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */ +#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */ +#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */ +#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */ +#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */ +#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */ +#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */ +#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */ +#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */ +#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */ +#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */ +#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */ +#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */ +#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */ +#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */ +#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */ +#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */ +#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */ +#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */ +#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */ +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */ +#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */ +#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */ +#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */ +#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */ +#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */ +#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */ +#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */ +#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */ +#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */ +#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */ +#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */ +#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */ +#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ +#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ +#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ +#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ +#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ +#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ +#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ +#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ +#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ +#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ +#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ +#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ +#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ +#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ +#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ +#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */ +#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */ +#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */ +#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */ +#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */ +#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */ +#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */ +#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */ + +/******************* Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */ +#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */ +#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */ +#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */ +#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */ +#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */ +#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */ +#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */ +#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */ +#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */ +#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */ +#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */ +#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */ +#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */ +#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */ +#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */ + +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ +#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ +#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */ +#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ +#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */ +#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */ + +/******************* Bit definition for ADC_CDR register ********************/ +#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */ +#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ +/*!<CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */ +#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */ +#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */ +#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */ +#define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */ +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */ +#define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */ +#define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */ +#define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */ +#define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */ +#define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */ +#define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ + +#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ +#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ +#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */ + + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ +#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ +#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ + +#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ + +#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ +#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ +#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ +#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ + + +/*!<Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ +#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ +#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ +#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ +#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ +#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ +#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ +#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ +#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ +#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ +#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ +#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ +#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ +#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ +#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ +#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ +#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ +#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ +#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ +#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ + +/*!<CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */ +#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */ +#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */ +#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */ +#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */ +#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */ +#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */ +#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */ +#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */ +#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */ +#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */ +#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */ +#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */ +#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */ +#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */ +#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */ +#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMA_SxCR register *****************/ +#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000) +#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) +#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) +#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) +#define DMA_SxCR_MBURST ((uint32_t)0x01800000) +#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) +#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) +#define DMA_SxCR_PBURST ((uint32_t)0x00600000) +#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) +#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) +#define DMA_SxCR_ACK ((uint32_t)0x00100000) +#define DMA_SxCR_CT ((uint32_t)0x00080000) +#define DMA_SxCR_DBM ((uint32_t)0x00040000) +#define DMA_SxCR_PL ((uint32_t)0x00030000) +#define DMA_SxCR_PL_0 ((uint32_t)0x00010000) +#define DMA_SxCR_PL_1 ((uint32_t)0x00020000) +#define DMA_SxCR_PINCOS ((uint32_t)0x00008000) +#define DMA_SxCR_MSIZE ((uint32_t)0x00006000) +#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) +#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) +#define DMA_SxCR_PSIZE ((uint32_t)0x00001800) +#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) +#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) +#define DMA_SxCR_MINC ((uint32_t)0x00000400) +#define DMA_SxCR_PINC ((uint32_t)0x00000200) +#define DMA_SxCR_CIRC ((uint32_t)0x00000100) +#define DMA_SxCR_DIR ((uint32_t)0x000000C0) +#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040) +#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080) +#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020) +#define DMA_SxCR_TCIE ((uint32_t)0x00000010) +#define DMA_SxCR_HTIE ((uint32_t)0x00000008) +#define DMA_SxCR_TEIE ((uint32_t)0x00000004) +#define DMA_SxCR_DMEIE ((uint32_t)0x00000002) +#define DMA_SxCR_EN ((uint32_t)0x00000001) + +/******************** Bits definition for DMA_SxCNDTR register **************/ +#define DMA_SxNDT ((uint32_t)0x0000FFFF) +#define DMA_SxNDT_0 ((uint32_t)0x00000001) +#define DMA_SxNDT_1 ((uint32_t)0x00000002) +#define DMA_SxNDT_2 ((uint32_t)0x00000004) +#define DMA_SxNDT_3 ((uint32_t)0x00000008) +#define DMA_SxNDT_4 ((uint32_t)0x00000010) +#define DMA_SxNDT_5 ((uint32_t)0x00000020) +#define DMA_SxNDT_6 ((uint32_t)0x00000040) +#define DMA_SxNDT_7 ((uint32_t)0x00000080) +#define DMA_SxNDT_8 ((uint32_t)0x00000100) +#define DMA_SxNDT_9 ((uint32_t)0x00000200) +#define DMA_SxNDT_10 ((uint32_t)0x00000400) +#define DMA_SxNDT_11 ((uint32_t)0x00000800) +#define DMA_SxNDT_12 ((uint32_t)0x00001000) +#define DMA_SxNDT_13 ((uint32_t)0x00002000) +#define DMA_SxNDT_14 ((uint32_t)0x00004000) +#define DMA_SxNDT_15 ((uint32_t)0x00008000) + +/******************** Bits definition for DMA_SxFCR register ****************/ +#define DMA_SxFCR_FEIE ((uint32_t)0x00000080) +#define DMA_SxFCR_FS ((uint32_t)0x00000038) +#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008) +#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010) +#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020) +#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004) +#define DMA_SxFCR_FTH ((uint32_t)0x00000003) +#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) +#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) + +/******************** Bits definition for DMA_LISR register *****************/ +#define DMA_LISR_TCIF3 ((uint32_t)0x08000000) +#define DMA_LISR_HTIF3 ((uint32_t)0x04000000) +#define DMA_LISR_TEIF3 ((uint32_t)0x02000000) +#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000) +#define DMA_LISR_FEIF3 ((uint32_t)0x00400000) +#define DMA_LISR_TCIF2 ((uint32_t)0x00200000) +#define DMA_LISR_HTIF2 ((uint32_t)0x00100000) +#define DMA_LISR_TEIF2 ((uint32_t)0x00080000) +#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000) +#define DMA_LISR_FEIF2 ((uint32_t)0x00010000) +#define DMA_LISR_TCIF1 ((uint32_t)0x00000800) +#define DMA_LISR_HTIF1 ((uint32_t)0x00000400) +#define DMA_LISR_TEIF1 ((uint32_t)0x00000200) +#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100) +#define DMA_LISR_FEIF1 ((uint32_t)0x00000040) +#define DMA_LISR_TCIF0 ((uint32_t)0x00000020) +#define DMA_LISR_HTIF0 ((uint32_t)0x00000010) +#define DMA_LISR_TEIF0 ((uint32_t)0x00000008) +#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004) +#define DMA_LISR_FEIF0 ((uint32_t)0x00000001) + +/******************** Bits definition for DMA_HISR register *****************/ +#define DMA_HISR_TCIF7 ((uint32_t)0x08000000) +#define DMA_HISR_HTIF7 ((uint32_t)0x04000000) +#define DMA_HISR_TEIF7 ((uint32_t)0x02000000) +#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000) +#define DMA_HISR_FEIF7 ((uint32_t)0x00400000) +#define DMA_HISR_TCIF6 ((uint32_t)0x00200000) +#define DMA_HISR_HTIF6 ((uint32_t)0x00100000) +#define DMA_HISR_TEIF6 ((uint32_t)0x00080000) +#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000) +#define DMA_HISR_FEIF6 ((uint32_t)0x00010000) +#define DMA_HISR_TCIF5 ((uint32_t)0x00000800) +#define DMA_HISR_HTIF5 ((uint32_t)0x00000400) +#define DMA_HISR_TEIF5 ((uint32_t)0x00000200) +#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100) +#define DMA_HISR_FEIF5 ((uint32_t)0x00000040) +#define DMA_HISR_TCIF4 ((uint32_t)0x00000020) +#define DMA_HISR_HTIF4 ((uint32_t)0x00000010) +#define DMA_HISR_TEIF4 ((uint32_t)0x00000008) +#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004) +#define DMA_HISR_FEIF4 ((uint32_t)0x00000001) + +/******************** Bits definition for DMA_LIFCR register ****************/ +#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) +#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) +#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) +#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) +#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) +#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) +#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) +#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) +#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) +#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) +#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) +#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) +#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) +#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) +#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) +#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) +#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) +#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) +#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) +#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) + +/******************** Bits definition for DMA_HIFCR register ****************/ +#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) +#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) +#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) +#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) +#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) +#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) +#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) +#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) +#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) +#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) +#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) +#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) +#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) +#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) +#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) +#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) +#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) +#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) +#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) +#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F) +#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) +#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) +#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) +#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) +#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) +#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) +#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) +#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) + +#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100) +#define FLASH_ACR_ICEN ((uint32_t)0x00000200) +#define FLASH_ACR_DCEN ((uint32_t)0x00000400) +#define FLASH_ACR_ICRST ((uint32_t)0x00000800) +#define FLASH_ACR_DCRST ((uint32_t)0x00001000) +#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) +#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP ((uint32_t)0x00000001) +#define FLASH_SR_SOP ((uint32_t)0x00000002) +#define FLASH_SR_WRPERR ((uint32_t)0x00000010) +#define FLASH_SR_PGAERR ((uint32_t)0x00000020) +#define FLASH_SR_PGPERR ((uint32_t)0x00000040) +#define FLASH_SR_PGSERR ((uint32_t)0x00000080) +#define FLASH_SR_BSY ((uint32_t)0x00010000) + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG ((uint32_t)0x00000001) +#define FLASH_CR_SER ((uint32_t)0x00000002) +#define FLASH_CR_MER ((uint32_t)0x00000004) +#define FLASH_CR_SNB ((uint32_t)0x000000F8) +#define FLASH_CR_SNB_0 ((uint32_t)0x00000008) +#define FLASH_CR_SNB_1 ((uint32_t)0x00000010) +#define FLASH_CR_SNB_2 ((uint32_t)0x00000020) +#define FLASH_CR_SNB_3 ((uint32_t)0x00000040) +#define FLASH_CR_SNB_4 ((uint32_t)0x00000080) +#define FLASH_CR_PSIZE ((uint32_t)0x00000300) +#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) +#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) +#define FLASH_CR_STRT ((uint32_t)0x00010000) +#define FLASH_CR_EOPIE ((uint32_t)0x01000000) +#define FLASH_CR_LOCK ((uint32_t)0x80000000) + +/******************* Bits definition for FLASH_OPTCR register ***************/ +#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) +#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) +#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) +#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) +#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) + +#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) +#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) +#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) +#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00) +#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) +#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) +#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) +#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) +#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) +#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) +#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) +#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) +#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000) +#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) +#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) +#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) +#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) +#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) +#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) +#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) +#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) +#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) +#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) +#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) +#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) + +/****************** Bits definition for FLASH_OPTCR1 register ***************/ +#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000) +#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000) +#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000) +#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000) +#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000) +#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000) +#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000) +#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000) +#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000) +#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000) +#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000) +#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000) +#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000) + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ + +#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ + +#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ +#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ +#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ +#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ +#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ +#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ + +#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ + +#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ +#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ +#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ +#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ +#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ +#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ + +#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ + +#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ +#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ +#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ +#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ +#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ +#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ +#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ + +#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ + +#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ +#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ +#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ +#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ +#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ +#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ + +#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ + +#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */ + +#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ + +#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ + +#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ + +#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ +#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ +#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ +#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ + +#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */ + +#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ + +#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ + +#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ + +#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ +#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ +#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ +#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ + +#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */ + +#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ + +#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ + +#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ + +#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ +#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ +#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ +#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ + +#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ +#define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ +#define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ +#define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODER0 ((uint32_t)0x00000003) +#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) +#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) + +#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) +#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) +#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) + +#define GPIO_MODER_MODER2 ((uint32_t)0x00000030) +#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) +#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) + +#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) +#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) +#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) + +#define GPIO_MODER_MODER4 ((uint32_t)0x00000300) +#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) +#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) + +#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) +#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) +#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) + +#define GPIO_MODER_MODER6 ((uint32_t)0x00003000) +#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) +#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) + +#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) +#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) +#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) + +#define GPIO_MODER_MODER8 ((uint32_t)0x00030000) +#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) +#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) + +#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) +#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) +#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) + +#define GPIO_MODER_MODER10 ((uint32_t)0x00300000) +#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) +#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) + +#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) +#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) +#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) + +#define GPIO_MODER_MODER12 ((uint32_t)0x03000000) +#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) +#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) + +#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) +#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) +#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) + +#define GPIO_MODER_MODER14 ((uint32_t)0x30000000) +#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) +#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) + +#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) +#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) +#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) +#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) +#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) +#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) +#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) +#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) +#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) +#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) +#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) +#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) +#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) +#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) +#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) +#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) +#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) +#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) +#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) +#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) + +#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) +#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) +#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) + +#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) +#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) +#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) + +#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) +#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) +#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) + +#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) +#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) +#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) + +#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) +#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) +#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) + +#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) +#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) +#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) + +#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) +#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) +#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) + +#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) +#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) +#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) + +#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) +#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) +#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) + +#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) +#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) +#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) + +#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) +#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) +#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) + +#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) +#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) +#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) + +#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) +#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) +#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) + +#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) +#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) +#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) + +#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) +#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) +#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) +#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) +#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) + +#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) +#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) +#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) + +#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) +#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) +#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) + +#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) +#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) +#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) + +#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) +#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) +#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) + +#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) +#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) +#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) + +#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) +#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) +#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) + +#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) +#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) +#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) + +#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) +#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) +#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) + +#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) +#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) +#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) + +#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) +#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) +#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) + +#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) +#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) +#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) + +#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) +#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) +#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) + +#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) +#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) +#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) + +#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) +#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) +#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) + +#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) +#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) +#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001) +#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002) +#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004) +#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008) +#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010) +#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020) +#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040) +#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080) +#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100) +#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200) +#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400) +#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800) +#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000) +#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000) +#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000) +#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000) +/* Old GPIO_IDR register bits definition, maintained for legacy purpose */ +#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 +#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 +#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 +#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 +#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 +#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 +#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 +#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 +#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 +#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 +#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 +#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 +#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 +#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 +#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 +#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001) +#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002) +#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004) +#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008) +#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010) +#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020) +#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040) +#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080) +#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100) +#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200) +#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400) +#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800) +#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000) +#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000) +#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000) +#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000) +/* Old GPIO_ODR register bits definition, maintained for legacy purpose */ +#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 +#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 +#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 +#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 +#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 +#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 +#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 +#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 +#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 +#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 +#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 +#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 +#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 +#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 +#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 +#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) +#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) +#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) +#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) +#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) +#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) +#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) +#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) +#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) +#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) +#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) +#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) +#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) +#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) +#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) +#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) +#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) +#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) +#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) +#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) +#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) +#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) +#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) +#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) +#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) +#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) +#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) +#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) +#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) +#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) +#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) +#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */ +#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */ +#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */ +#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */ +#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */ +#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */ +#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */ +#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */ +#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */ +#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */ +#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */ +#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */ + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */ + +#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */ +#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */ + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */ +#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */ + +#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */ +#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */ +#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */ +#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */ + +#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */ + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */ + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */ +#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */ +#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */ +#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */ + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */ +#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */ +#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */ + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/****************** Bit definition for I2C_FLTR register *******************/ +#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */ +#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */ +#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */ +#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */ + +#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ +#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */ +#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ +#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +/* Legacy define */ +#define PWR_CR_PMODE PWR_CR_VOS + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */ +#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */ +#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */ +#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */ +#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */ + +/* Legacy define */ +#define PWR_CSR_REGRDY PWR_CSR_VOSRDY + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) + +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) +#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ +#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ +#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */ +#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ +#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ + +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) +#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ +#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */ +#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ +#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */ +#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */ +#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ +#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ +#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */ + +#define RCC_CR_HSEON ((uint32_t)0x00010000) +#define RCC_CR_HSERDY ((uint32_t)0x00020000) +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) +#define RCC_CR_CSSON ((uint32_t)0x00080000) +#define RCC_CR_PLLON ((uint32_t)0x01000000) +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) +#define RCC_CR_PLLI2SON ((uint32_t)0x04000000) +#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) +#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) +#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) +#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) +#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) +#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) +#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) + +#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) +#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) +#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) +#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) +#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) +#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) +#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) +#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) +#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) +#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) + +#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) +#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) +#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) + +#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) +#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) +#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) + +#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) +#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) +#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) +#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) +#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */ + +/*!< RTCPRE configuration */ +#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) +#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) +#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) +#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) +#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) +#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) + +/*!< MCO1 configuration */ +#define RCC_CFGR_MCO1 ((uint32_t)0x00600000) +#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) +#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) + +#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) + +#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) +#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) +#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) +#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) + +#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) +#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) +#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) +#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) + +#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000) +#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) +#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) + +/******************** Bit definition for RCC_CIR register *******************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) +#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) + +#define RCC_CIR_CSSF ((uint32_t)0x00000080) +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) +#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) + +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) +#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) + +#define RCC_CIR_CSSC ((uint32_t)0x00800000) + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) +#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) +#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) +#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) +#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) +#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) +#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) +#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) +#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) +#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) +#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) +#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) +#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) +#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) + +/******************** Bit definition for RCC_AHB3RSTR register **************/ + +#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001) + +/******************** Bit definition for RCC_APB1RSTR register **************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) +#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) +#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) +#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) +#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) +#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) +#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) +#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) +#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) +#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) +#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) +#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) +#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) +#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) +#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) +#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) +#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) +#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) +#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) +#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) +#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) +#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) +#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) +#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) +#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) + +/* Old SPI1RST bit definition, maintained for legacy purpose */ +#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST + +/******************** Bit definition for RCC_AHB1ENR register ***************/ +#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) +#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) +#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) +#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) +#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) +#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) +#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) +#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) +#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) +#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) +#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) +#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) +#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) +#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) + +#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) +#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) +#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) + +/******************** Bit definition for RCC_AHB3ENR register ***************/ + +#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001) + +/******************** Bit definition for RCC_APB1ENR register ***************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) +#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) +#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) +#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) +#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) +#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) +#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) +#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) +#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) +#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) +#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) +#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) +#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) +#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) +#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) +#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) +#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) + +/******************** Bit definition for RCC_APB2ENR register ***************/ +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) +#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) +#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) +#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) +#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) +#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) +#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) +#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) +#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) +#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000) +#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000) + +/******************** Bit definition for RCC_AHB1LPENR register *************/ +#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) +#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) +#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) +#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) +#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) +#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) +#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) +#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) +#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) +#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) +#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) +#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) +#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) +#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) +#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000) +#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) +#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) +#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) +#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) + +/******************** Bit definition for RCC_AHB2LPENR register *************/ +#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) +#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) + +/******************** Bit definition for RCC_AHB3LPENR register *************/ + +#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001) + +/******************** Bit definition for RCC_APB1LPENR register *************/ +#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) +#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) +#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) +#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) +#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) +#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) +#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) +#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) +#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) +#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) +#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) +#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) +#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) +#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) +#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) +#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) +#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) +#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) +#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) +#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) +#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) +#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) +#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) + +/******************** Bit definition for RCC_APB2LPENR register *************/ +#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) +#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) +#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) +#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) +#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) +#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200) +#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) +#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) +#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) +#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) +#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) +#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) +#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) +#define RCC_CSR_RMVF ((uint32_t)0x01000000) +#define RCC_CSR_BORRSTF ((uint32_t)0x02000000) +#define RCC_CSR_PADRSTF ((uint32_t)0x04000000) +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) +#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) + +/******************** Bit definition for RCC_SSCGR register *****************/ +#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) +#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) +#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) +#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) + +/******************** Bit definition for RCC_PLLI2SCFGR register ************/ +#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) +#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040) +#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080) +#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100) +#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200) +#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400) +#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800) +#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000) +#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000) +#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000) + +#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) +#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000) +#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000) +#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000) + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN ((uint32_t)0x00000004) +#define RNG_CR_IE ((uint32_t)0x00000008) + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY ((uint32_t)0x00000001) +#define RNG_SR_CECS ((uint32_t)0x00000002) +#define RNG_SR_SECS ((uint32_t)0x00000004) +#define RNG_SR_CEIS ((uint32_t)0x00000020) +#define RNG_SR_SEIS ((uint32_t)0x00000040) + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_PM ((uint32_t)0x00400000) +#define RTC_TR_HT ((uint32_t)0x00300000) +#define RTC_TR_HT_0 ((uint32_t)0x00100000) +#define RTC_TR_HT_1 ((uint32_t)0x00200000) +#define RTC_TR_HU ((uint32_t)0x000F0000) +#define RTC_TR_HU_0 ((uint32_t)0x00010000) +#define RTC_TR_HU_1 ((uint32_t)0x00020000) +#define RTC_TR_HU_2 ((uint32_t)0x00040000) +#define RTC_TR_HU_3 ((uint32_t)0x00080000) +#define RTC_TR_MNT ((uint32_t)0x00007000) +#define RTC_TR_MNT_0 ((uint32_t)0x00001000) +#define RTC_TR_MNT_1 ((uint32_t)0x00002000) +#define RTC_TR_MNT_2 ((uint32_t)0x00004000) +#define RTC_TR_MNU ((uint32_t)0x00000F00) +#define RTC_TR_MNU_0 ((uint32_t)0x00000100) +#define RTC_TR_MNU_1 ((uint32_t)0x00000200) +#define RTC_TR_MNU_2 ((uint32_t)0x00000400) +#define RTC_TR_MNU_3 ((uint32_t)0x00000800) +#define RTC_TR_ST ((uint32_t)0x00000070) +#define RTC_TR_ST_0 ((uint32_t)0x00000010) +#define RTC_TR_ST_1 ((uint32_t)0x00000020) +#define RTC_TR_ST_2 ((uint32_t)0x00000040) +#define RTC_TR_SU ((uint32_t)0x0000000F) +#define RTC_TR_SU_0 ((uint32_t)0x00000001) +#define RTC_TR_SU_1 ((uint32_t)0x00000002) +#define RTC_TR_SU_2 ((uint32_t)0x00000004) +#define RTC_TR_SU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_YT ((uint32_t)0x00F00000) +#define RTC_DR_YT_0 ((uint32_t)0x00100000) +#define RTC_DR_YT_1 ((uint32_t)0x00200000) +#define RTC_DR_YT_2 ((uint32_t)0x00400000) +#define RTC_DR_YT_3 ((uint32_t)0x00800000) +#define RTC_DR_YU ((uint32_t)0x000F0000) +#define RTC_DR_YU_0 ((uint32_t)0x00010000) +#define RTC_DR_YU_1 ((uint32_t)0x00020000) +#define RTC_DR_YU_2 ((uint32_t)0x00040000) +#define RTC_DR_YU_3 ((uint32_t)0x00080000) +#define RTC_DR_WDU ((uint32_t)0x0000E000) +#define RTC_DR_WDU_0 ((uint32_t)0x00002000) +#define RTC_DR_WDU_1 ((uint32_t)0x00004000) +#define RTC_DR_WDU_2 ((uint32_t)0x00008000) +#define RTC_DR_MT ((uint32_t)0x00001000) +#define RTC_DR_MU ((uint32_t)0x00000F00) +#define RTC_DR_MU_0 ((uint32_t)0x00000100) +#define RTC_DR_MU_1 ((uint32_t)0x00000200) +#define RTC_DR_MU_2 ((uint32_t)0x00000400) +#define RTC_DR_MU_3 ((uint32_t)0x00000800) +#define RTC_DR_DT ((uint32_t)0x00000030) +#define RTC_DR_DT_0 ((uint32_t)0x00000010) +#define RTC_DR_DT_1 ((uint32_t)0x00000020) +#define RTC_DR_DU ((uint32_t)0x0000000F) +#define RTC_DR_DU_0 ((uint32_t)0x00000001) +#define RTC_DR_DU_1 ((uint32_t)0x00000002) +#define RTC_DR_DU_2 ((uint32_t)0x00000004) +#define RTC_DR_DU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_COE ((uint32_t)0x00800000) +#define RTC_CR_OSEL ((uint32_t)0x00600000) +#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) +#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) +#define RTC_CR_POL ((uint32_t)0x00100000) +#define RTC_CR_COSEL ((uint32_t)0x00080000) +#define RTC_CR_BCK ((uint32_t)0x00040000) +#define RTC_CR_SUB1H ((uint32_t)0x00020000) +#define RTC_CR_ADD1H ((uint32_t)0x00010000) +#define RTC_CR_TSIE ((uint32_t)0x00008000) +#define RTC_CR_WUTIE ((uint32_t)0x00004000) +#define RTC_CR_ALRBIE ((uint32_t)0x00002000) +#define RTC_CR_ALRAIE ((uint32_t)0x00001000) +#define RTC_CR_TSE ((uint32_t)0x00000800) +#define RTC_CR_WUTE ((uint32_t)0x00000400) +#define RTC_CR_ALRBE ((uint32_t)0x00000200) +#define RTC_CR_ALRAE ((uint32_t)0x00000100) +#define RTC_CR_DCE ((uint32_t)0x00000080) +#define RTC_CR_FMT ((uint32_t)0x00000040) +#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) +#define RTC_CR_REFCKON ((uint32_t)0x00000010) +#define RTC_CR_TSEDGE ((uint32_t)0x00000008) +#define RTC_CR_WUCKSEL ((uint32_t)0x00000007) +#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) +#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) +#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) + +/******************** Bits definition for RTC_ISR register ******************/ +#define RTC_ISR_RECALPF ((uint32_t)0x00010000) +#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) +#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) +#define RTC_ISR_TSOVF ((uint32_t)0x00001000) +#define RTC_ISR_TSF ((uint32_t)0x00000800) +#define RTC_ISR_WUTF ((uint32_t)0x00000400) +#define RTC_ISR_ALRBF ((uint32_t)0x00000200) +#define RTC_ISR_ALRAF ((uint32_t)0x00000100) +#define RTC_ISR_INIT ((uint32_t)0x00000080) +#define RTC_ISR_INITF ((uint32_t)0x00000040) +#define RTC_ISR_RSF ((uint32_t)0x00000020) +#define RTC_ISR_INITS ((uint32_t)0x00000010) +#define RTC_ISR_SHPF ((uint32_t)0x00000008) +#define RTC_ISR_WUTWF ((uint32_t)0x00000004) +#define RTC_ISR_ALRBWF ((uint32_t)0x00000002) +#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) +#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_CALIBR register ***************/ +#define RTC_CALIBR_DCS ((uint32_t)0x00000080) +#define RTC_CALIBR_DC ((uint32_t)0x0000001F) + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) +#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) +#define RTC_ALRMAR_DT ((uint32_t)0x30000000) +#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) +#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) +#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) +#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) +#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) +#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) +#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) +#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) +#define RTC_ALRMAR_PM ((uint32_t)0x00400000) +#define RTC_ALRMAR_HT ((uint32_t)0x00300000) +#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) +#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) +#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) +#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) +#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) +#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) +#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) +#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) +#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) +#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) +#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) +#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) +#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) +#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) +#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) +#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) +#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) +#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) +#define RTC_ALRMAR_ST ((uint32_t)0x00000070) +#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) +#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) +#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) +#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) +#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) +#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) +#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) +#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) +#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) +#define RTC_ALRMBR_DT ((uint32_t)0x30000000) +#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) +#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) +#define RTC_ALRMBR_DU ((uint32_t)0x0F000000) +#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) +#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) +#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) +#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) +#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) +#define RTC_ALRMBR_PM ((uint32_t)0x00400000) +#define RTC_ALRMBR_HT ((uint32_t)0x00300000) +#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) +#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) +#define RTC_ALRMBR_HU ((uint32_t)0x000F0000) +#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) +#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) +#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) +#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) +#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) +#define RTC_ALRMBR_MNT ((uint32_t)0x00007000) +#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) +#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) +#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) +#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) +#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) +#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) +#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) +#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) +#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) +#define RTC_ALRMBR_ST ((uint32_t)0x00000070) +#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) +#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) +#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) +#define RTC_ALRMBR_SU ((uint32_t)0x0000000F) +#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) +#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) +#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) +#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY ((uint32_t)0x000000FF) + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) +#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM ((uint32_t)0x00400000) +#define RTC_TSTR_HT ((uint32_t)0x00300000) +#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) +#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) +#define RTC_TSTR_HU ((uint32_t)0x000F0000) +#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) +#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) +#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) +#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) +#define RTC_TSTR_MNT ((uint32_t)0x00007000) +#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) +#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) +#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) +#define RTC_TSTR_MNU ((uint32_t)0x00000F00) +#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) +#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) +#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) +#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) +#define RTC_TSTR_ST ((uint32_t)0x00000070) +#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) +#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) +#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) +#define RTC_TSTR_SU ((uint32_t)0x0000000F) +#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) +#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) +#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) +#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU ((uint32_t)0x0000E000) +#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) +#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) +#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) +#define RTC_TSDR_MT ((uint32_t)0x00001000) +#define RTC_TSDR_MU ((uint32_t)0x00000F00) +#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) +#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) +#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) +#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) +#define RTC_TSDR_DT ((uint32_t)0x00000030) +#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) +#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) +#define RTC_TSDR_DU ((uint32_t)0x0000000F) +#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) +#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) +#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) +#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) + +/******************** Bits definition for RTC_CAL register *****************/ +#define RTC_CALR_CALP ((uint32_t)0x00008000) +#define RTC_CALR_CALW8 ((uint32_t)0x00004000) +#define RTC_CALR_CALW16 ((uint32_t)0x00002000) +#define RTC_CALR_CALM ((uint32_t)0x000001FF) +#define RTC_CALR_CALM_0 ((uint32_t)0x00000001) +#define RTC_CALR_CALM_1 ((uint32_t)0x00000002) +#define RTC_CALR_CALM_2 ((uint32_t)0x00000004) +#define RTC_CALR_CALM_3 ((uint32_t)0x00000008) +#define RTC_CALR_CALM_4 ((uint32_t)0x00000010) +#define RTC_CALR_CALM_5 ((uint32_t)0x00000020) +#define RTC_CALR_CALM_6 ((uint32_t)0x00000040) +#define RTC_CALR_CALM_7 ((uint32_t)0x00000080) +#define RTC_CALR_CALM_8 ((uint32_t)0x00000100) + +/******************** Bits definition for RTC_TAFCR register ****************/ +#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) +#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) +#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) +#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) +#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) +#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) +#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) +#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) +#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) +#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) +#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) +#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) +#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) +#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) +#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) +#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) +#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) +#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) +#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) +#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) +#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) +#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) +#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) +#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) +#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) +#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) +#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) +#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) +#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) +#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) + +/******************** Bits definition for RTC_BKP0R register ****************/ +#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP1R register ****************/ +#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP2R register ****************/ +#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP3R register ****************/ +#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP4R register ****************/ +#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP5R register ****************/ +#define RTC_BKP5R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP6R register ****************/ +#define RTC_BKP6R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP7R register ****************/ +#define RTC_BKP7R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP8R register ****************/ +#define RTC_BKP8R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP9R register ****************/ +#define RTC_BKP9R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP10R register ***************/ +#define RTC_BKP10R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP11R register ***************/ +#define RTC_BKP11R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP12R register ***************/ +#define RTC_BKP12R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP13R register ***************/ +#define RTC_BKP13R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP14R register ***************/ +#define RTC_BKP14R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP15R register ***************/ +#define RTC_BKP15R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP16R register ***************/ +#define RTC_BKP16R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP17R register ***************/ +#define RTC_BKP17R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP18R register ***************/ +#define RTC_BKP18R ((uint32_t)0xFFFFFFFF) + +/******************** Bits definition for RTC_BKP19R register ***************/ +#define RTC_BKP19R ((uint32_t)0xFFFFFFFF) + + + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */ + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */ + +#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */ + +#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */ +#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */ + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */ + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */ + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */ + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */ +#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */ +#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */ + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */ + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */ +#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */ +#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */ +#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */ +#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */ +#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */ + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */ + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */ + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */ + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */ +#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */ +#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */ + +#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */ +#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */ +#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */ + +#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */ +#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */ +#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */ +#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */ +#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */ +#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */ +#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */ +#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */ +#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */ +#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */ +#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */ +#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */ +#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */ +#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* SYSCFG */ +/* */ +/******************************************************************************/ +/****************** Bit definition for SYSCFG_MEMRMP register ***************/ +#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */ +#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) +#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) +#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) + +/****************** Bit definition for SYSCFG_PMC register ******************/ +#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */ +/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */ +#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL + +/***************** Bit definition for SYSCFG_EXTICR1 register ***************/ +#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */ +/** + * @brief EXTI0 configuration + */ +#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */ + +/** + * @brief EXTI1 configuration + */ +#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */ + +/** + * @brief EXTI2 configuration + */ +#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */ + +/** + * @brief EXTI3 configuration + */ +#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */ + +/***************** Bit definition for SYSCFG_EXTICR2 register ***************/ +#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */ +#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */ +#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */ +#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */ +/** + * @brief EXTI4 configuration + */ +#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */ + +/** + * @brief EXTI5 configuration + */ +#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */ + +/** + * @brief EXTI6 configuration + */ +#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */ + +/** + * @brief EXTI7 configuration + */ +#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */ + + +/***************** Bit definition for SYSCFG_EXTICR3 register ***************/ +#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */ + +/** + * @brief EXTI8 configuration + */ +#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */ + +/** + * @brief EXTI9 configuration + */ +#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */ + +/** + * @brief EXTI10 configuration + */ +#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */ + +/** + * @brief EXTI11 configuration + */ +#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */ + +/***************** Bit definition for SYSCFG_EXTICR4 register ***************/ +#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */ +/** + * @brief EXTI12 configuration + */ +#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */ + +/** + * @brief EXTI13 configuration + */ +#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */ + +/** + * @brief EXTI14 configuration + */ +#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */ + +/** + * @brief EXTI15 configuration + */ +#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */ + +/****************** Bit definition for SYSCFG_CMPCR register ****************/ +#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */ +#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */ +#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */ +#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */ +#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */ +#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */ + +#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */ +#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */ + +#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */ + +#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */ +#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */ +#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */ +#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */ + +#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */ +#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */ +#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */ +#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */ + +#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */ +#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */ +#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */ + +#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */ + +#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */ +#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */ +#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */ +#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */ + +#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */ +#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */ + +#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */ +#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */ +#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */ +#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */ +#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */ +#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */ +#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */ +#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */ +#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */ +#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */ +#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */ +#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */ +#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */ +#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */ + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */ + +#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */ + +#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */ + +#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */ + +#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */ + +#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */ + +#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */ + +#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */ + +#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */ + +#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */ + +#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */ + +#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */ + +#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */ +#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */ +#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */ +#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */ +#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */ +#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */ +#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */ +#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */ + +#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */ +#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */ + +#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */ +#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */ +#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */ +#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */ +#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */ +#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */ +#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */ +#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */ + +#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */ +#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */ +#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */ +#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */ +#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */ + +/******************* Bit definition for TIM_OR register *********************/ +#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */ +#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */ +#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */ +#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */ +#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */ +#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */ + + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */ +#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */ +#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */ +#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */ +#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */ +#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */ +#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */ +#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */ +#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */ +#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */ + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */ +#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */ +#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */ +#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */ +#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */ +#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */ +#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */ +#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */ +#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */ +#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */ +#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */ +#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */ +#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */ +#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */ +#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */ +#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */ +#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */ + +#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */ +#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */ + +#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */ +#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */ +#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */ +#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */ +#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */ +#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */ +#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */ +#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */ +#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */ +#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */ +#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */ +#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */ +#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */ +#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */ +#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */ +#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */ +#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */ +#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */ +#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */ + +#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */ +#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */ +#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */ +#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */ +#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */ +#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */ +#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */ + +#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */ +#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */ +#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */ +#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */ +#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */ +#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */ +#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */ + +#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */ + + +/******************************************************************************/ +/* */ +/* DBG */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register *************/ +#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) +#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) + +/******************** Bit definition for DBGMCU_CR register *****************/ +#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) +#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) + +#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) +#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */ + +/******************** Bit definition for DBGMCU_APB1_FZ register ************/ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) +#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) +#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) +#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) +#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) +#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) +#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) +#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) +#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) +#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) +/* Old IWDGSTOP bit definition, maintained for legacy purpose */ +#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP + +/******************** Bit definition for DBGMCU_APB2_FZ register ************/ +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) +#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) +#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) +#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) +#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) + +/******************************************************************************/ +/* */ +/* USB_OTG */ +/* */ +/******************************************************************************/ +/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/ +#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */ +#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */ +#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */ + +/******************** Bit definition forUSB_OTG_HCFG register ********************/ + +#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */ + +/******************** Bit definition forUSB_OTG_DCFG register ********************/ + +#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ +#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */ +#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */ +#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */ + +#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */ +#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */ + +#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ + +/******************** Bit definition forUSB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */ + +/******************** Bit definition forUSB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */ + +/******************** Bit definition forUSB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */ +#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */ +#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */ +#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */ + +/******************** Bit definition forUSB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */ + +/******************** Bit definition forUSB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */ + +/******************** Bit definition forUSB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */ +#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */ +#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */ + +/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */ + +#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */ +#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/ + +#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */ + +#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */ +#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */ +#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */ +#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */ +#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */ + +/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */ + +#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */ +#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */ + +/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ + +/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */ + +#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */ + +/******************** Bit definition forUSB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */ + +/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ + +/******************** Bit definition forUSB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition forUSB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition forUSB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */ + +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for OTG register ********************/ + +#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */ +#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */ + +#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */ +#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */ +#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */ + +#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */ +#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ +#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ +#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ +#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */ + +#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */ +#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */ +#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */ +#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */ +#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */ + +/******************** Bit definition for OTG register ********************/ + +#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */ +#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */ + +#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */ +#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */ +#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */ + +#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */ +#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ +#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ +#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ +#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */ + +#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ + +#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */ +#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */ +#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */ +#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */ +#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */ + +/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */ + +/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */ + +/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/ +#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */ + +/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */ + +/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */ +#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */ +#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */ + +/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition forUSB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition forUSB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */ +#define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */ +#define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */ +#define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */ + +/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition forUSB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */ + +/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */ + +/******************** Bit definition forUSB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */ +#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */ +#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */ +#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */ +#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */ +#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */ +#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */ + +#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */ +#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */ + +/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */ + +/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ +#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ +#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */ +#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */ + +/******************** Bit definition forUSB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */ +#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */ +#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */ +#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */ +#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ +#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ + +#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */ +#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */ + +#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */ +#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */ +#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */ +#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */ +#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */ +#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */ +#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */ +#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */ + +/******************** Bit definition forUSB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */ +#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */ +#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */ +#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */ +#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */ +#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */ +#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */ + +#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */ +#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */ +#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */ +#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */ +#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */ +#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */ +#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */ + +#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */ +#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */ +#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */ + +/******************** Bit definition forUSB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */ +#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */ + +/******************** Bit definition forUSB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */ + +/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */ + +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ + +#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */ +/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */ +#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */ + +/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */ + +/******************** Bit definition forUSB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */ + +/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */ + +/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/ + +#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */ +#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */ +#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */ +#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ +#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ +#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ +#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */ +#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */ +#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */ +#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */ +#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */ +#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */ + +/******************** Bit definition forUSB_OTG_DOEPINT register ********************/ +#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */ +#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */ +#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */ + +/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/ + +#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ +#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ + +#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */ +#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */ + +/******************** Bit definition for PCGCCTL register ********************/ +#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */ +#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */ +#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ + ((INSTANCE) == ADC2) || \ + ((INSTANCE) == ADC3)) + +/******************************* CAN Instances ********************************/ +#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \ + ((INSTANCE) == CAN2)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \ + ((INSTANCE) == DMA1_Stream1) || \ + ((INSTANCE) == DMA1_Stream2) || \ + ((INSTANCE) == DMA1_Stream3) || \ + ((INSTANCE) == DMA1_Stream4) || \ + ((INSTANCE) == DMA1_Stream5) || \ + ((INSTANCE) == DMA1_Stream6) || \ + ((INSTANCE) == DMA1_Stream7) || \ + ((INSTANCE) == DMA2_Stream0) || \ + ((INSTANCE) == DMA2_Stream1) || \ + ((INSTANCE) == DMA2_Stream2) || \ + ((INSTANCE) == DMA2_Stream3) || \ + ((INSTANCE) == DMA2_Stream4) || \ + ((INSTANCE) == DMA2_Stream5) || \ + ((INSTANCE) == DMA2_Stream6) || \ + ((INSTANCE) == DMA2_Stream7)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOE) || \ + ((INSTANCE) == GPIOF) || \ + ((INSTANCE) == GPIOG) || \ + ((INSTANCE) == GPIOH) || \ + ((INSTANCE) == GPIOI)) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ + ((INSTANCE) == I2C2) || \ + ((INSTANCE) == I2C3)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/*************************** I2S Extended Instances ***************************/ +#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3) || \ + ((INSTANCE) == I2S2ext) || \ + ((INSTANCE) == I2S3ext)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/*************************** SPI Extended Instances ***************************/ +#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3) || \ + ((INSTANCE) == I2S2ext) || \ + ((INSTANCE) == I2S3ext)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM9) || \ + ((INSTANCE) == TIM10) || \ + ((INSTANCE) == TIM11) || \ + ((INSTANCE) == TIM12) || \ + ((INSTANCE) == TIM13) || \ + ((INSTANCE) == TIM14)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM9) || \ + ((INSTANCE) == TIM10) || \ + ((INSTANCE) == TIM11) || \ + ((INSTANCE) == TIM12) || \ + ((INSTANCE) == TIM13) || \ + ((INSTANCE) == TIM14)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM9) || \ + ((INSTANCE) == TIM12)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8)) + +/******************** TIM Instances : Advanced-control timers *****************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8)) + +/****************** TIM Instances : DMA requests generation (UDE) *************/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ + ((INSTANCE) == TIM8)) + +/************ TIM Instances : DMA requests generation (CCxDE) *****************/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8)) + +/************ TIM Instances : DMA requests generation (COMDE) *****************/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8)) + +/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM9) || \ + ((INSTANCE) == TIM12)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM9) || \ + ((INSTANCE) == TIM12)) + +/********************** TIM Instances : 32 bit Counter ************************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM5)) + +/***************** TIM Instances : external trigger input availabe ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM11)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM5) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM8) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM9) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + (((INSTANCE) == TIM10) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM11) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM12) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + (((INSTANCE) == TIM13) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM14) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/************ TIM Instances : complementary output(s) available ***************/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3))) \ + || \ + (((INSTANCE) == TIM8) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3)))) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == USART6)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5) || \ + ((INSTANCE) == USART6)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == USART6)) + +/********************* UART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == USART6)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5) || \ + ((INSTANCE) == USART6)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) + +/******************************************************************************/ +/* For a painless codes migration between the STM32F4xx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32F4 Family */ +/******************************************************************************/ + +/* Aliases for __IRQn */ +#define FMC_IRQn FSMC_IRQn + +/* Aliases for __IRQHandler */ +#define FMC_IRQHandler FSMC_IRQHandler + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F405xx_H */ + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * @file stm32f4xx.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32F4xx device used in the target application + * - To use or not the peripherals drivers in application code(i.e. + * code will be based on direct access to peripherals registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) +#define STM32F405xx /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ + /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.1.0 + */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,572 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" +#include "hal_tick.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) + #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 48000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 48000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + SystemCoreClockUpdate(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E0; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + __PWR_CLK_ENABLE(); + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 26; + RCC_OscInitStruct.PLL.PLLN = 192; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + RCC_OscInitStruct.PLL.PLLQ = 4; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/PeripheralNames.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_0 = 0, + DAC_1 +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE, +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/PinNames.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,157 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + PH_0 = 0x70, + PH_1 = 0x71, + + // Generic signals namings + LED1 = PA_10, + LED2 = PA_10, + LED3 = PA_10, + LED4 = PA_10, + SERIAL_TX = PA_10, + SERIAL_RX = PA_9, + I2C_SCL = PA_8, + I2C_SDA = PC_9, + SPI_MOSI = PC_12, + SPI_MISO = PC_11, + SPI_SCK = PC_10, + SPI_CS = PC_13, + PWM0 = PA_8, + PWM1 = PC_9, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/PortNames.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortH = 7 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/analogin_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,184 @@ +/* mbed Microcontroller Library + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "wait_api.h" +#include "cmsis.h" +#include "pinmap.h" + +static const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {NC, NC, 0} +}; + +ADC_HandleTypeDef AdcHandle; + +int adc_inited = 0; + +void analogin_init(analogin_t *obj, PinName pin) { + // Get the peripheral name from the pin and assign it to the object + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + // Configure GPIO + pinmap_pinout(pin, PinMap_ADC); + + // Save pin number for the read function + obj->pin = pin; + + // The ADC initialization is done once + if (adc_inited == 0) { + adc_inited = 1; + + // Enable ADC clock + __ADC1_CLK_ENABLE(); + + // Configure ADC + AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); + AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2; + AdcHandle.Init.Resolution = ADC_RESOLUTION12b; + AdcHandle.Init.ScanConvMode = DISABLE; + AdcHandle.Init.ContinuousConvMode = DISABLE; + AdcHandle.Init.DiscontinuousConvMode = DISABLE; + AdcHandle.Init.NbrOfDiscConversion = 0; + AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; + AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + AdcHandle.Init.NbrOfConversion = 1; + AdcHandle.Init.DMAContinuousRequests = DISABLE; + AdcHandle.Init.EOCSelection = DISABLE; + HAL_ADC_Init(&AdcHandle); + } +} + +static inline uint16_t adc_read(analogin_t *obj) { + ADC_ChannelConfTypeDef sConfig; + + AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); + + // Configure ADC channel + sConfig.Rank = 1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + sConfig.Offset = 0; + + switch (obj->pin) { + case PA_0: + sConfig.Channel = ADC_CHANNEL_0; + break; + case PA_1: + sConfig.Channel = ADC_CHANNEL_1; + break; + case PA_2: + sConfig.Channel = ADC_CHANNEL_2; + break; + case PA_3: + sConfig.Channel = ADC_CHANNEL_3; + break; + case PA_4: + sConfig.Channel = ADC_CHANNEL_4; + break; + case PA_5: + sConfig.Channel = ADC_CHANNEL_5; + break; + case PA_6: + sConfig.Channel = ADC_CHANNEL_6; + break; + case PA_7: + sConfig.Channel = ADC_CHANNEL_7; + break; + case PB_0: + sConfig.Channel = ADC_CHANNEL_8; + break; + case PB_1: + sConfig.Channel = ADC_CHANNEL_9; + break; + case PC_0: + sConfig.Channel = ADC_CHANNEL_10; + break; + case PC_1: + sConfig.Channel = ADC_CHANNEL_11; + break; + case PC_2: + sConfig.Channel = ADC_CHANNEL_12; + break; + case PC_3: + sConfig.Channel = ADC_CHANNEL_13; + break; + case PC_4: + sConfig.Channel = ADC_CHANNEL_14; + break; + case PC_5: + sConfig.Channel = ADC_CHANNEL_15; + break; + default: + return 0; + } + + HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); + + HAL_ADC_Start(&AdcHandle); // Start conversion + + // Wait end of conversion and get value + if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) { + return (HAL_ADC_GetValue(&AdcHandle)); + } else { + return 0; + } +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint16_t value = adc_read(obj); + // 12-bit to 16-bit conversion + value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); + return value; +} + +float analogin_read(analogin_t *obj) { + uint16_t value = adc_read(obj); + return (float)value * (1.0f / (float)0xFFF); // 12 bits range +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/analogout_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,161 @@ +/* mbed Microcontroller Library + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "stm32f4xx_hal.h" + +#define RANGE_12BIT (0xFFF) + +DAC_HandleTypeDef DacHandle; +static DAC_ChannelConfTypeDef sConfig; + +static const PinMap PinMap_DAC[] = { + {PA_4, DAC_0, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT2 + {NC, NC, 0} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + uint32_t channel ; + HAL_StatusTypeDef status; + + // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + + if (obj->dac == (DACName)NC) { + error("DAC pin mapping failed"); + } + + // Configure GPIO + pinmap_pinout(pin, PinMap_DAC); + + // Save the channel for the write and read functions + obj->channel = pin; + + __GPIOA_CLK_ENABLE(); + + __DAC_CLK_ENABLE(); + + DacHandle.Instance = DAC; + + status = HAL_DAC_Init(&DacHandle); + if ( status != HAL_OK ) { + error("HAL_DAC_Init failed"); + } + + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + + if (obj->channel == PA_4) { + channel = DAC_CHANNEL_1; + } else { + channel = DAC_CHANNEL_2; + } + + if (HAL_DAC_ConfigChannel(&DacHandle, &sConfig, channel) != HAL_OK) { + error("HAL_DAC_ConfigChannel failed"); + } + + if (HAL_DAC_Start(&DacHandle, channel) != HAL_OK) { + error("HAL_DAC_Start failed"); + } + + if (HAL_DAC_SetValue(&DacHandle, channel, DAC_ALIGN_12B_R, 0x000) != HAL_OK) { + error("HAL_DAC_SetValue failed"); + } + +} + +void analogout_free(dac_t *obj) +{ +} + +static inline void dac_write(dac_t *obj, uint16_t value) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (obj->channel == PA_4) { + status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + } else if (obj->channel == PA_5) { + status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + } + + if ( status != HAL_OK ) { + error("ADC pin mapping failed"); + } +} + +static inline int dac_read(dac_t *obj) +{ + if (obj->channel == PA_4) { + return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); + } else if (obj->channel == PA_5) { + return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); + } + return 0; /* Just silented warning */ +} + +void analogout_write(dac_t *obj, float value) +{ + if (value < 0.0f) { + dac_write(obj, 0); // Min value + } else if (value > 1.0f) { + dac_write(obj, (uint16_t)RANGE_12BIT); // Max value + } else { + dac_write(obj, (uint16_t)(value * (float)RANGE_12BIT)); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + if (value > (uint16_t)RANGE_12BIT) { + value = (uint16_t)RANGE_12BIT; // Max value + } + + dac_write(obj, value); +} + +float analogout_read(dac_t *obj) +{ + + uint32_t value = dac_read(obj); + return (float)value * (1.0f / (float)RANGE_12BIT); +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + return (uint16_t)dac_read(obj); +} + +#endif // DEVICE_ANALOGOUT
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/device.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/gpio_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,73 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +extern uint32_t Set_GPIO_Clock(uint32_t port_idx); + +uint32_t gpio_set(PinName pin) { + MBED_ASSERT(pin != (PinName)NC); + + pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask +} + +void gpio_init(gpio_t *obj, PinName pin) { + obj->pin = pin; + if (pin == (PinName)NC) + return; + + uint32_t port_index = STM_PORT(pin); + + // Enable GPIO clock + uint32_t gpio_add = Set_GPIO_Clock(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + // Fill GPIO object structure for future use + obj->mask = gpio_set(pin); + obj->reg_in = &gpio->IDR; + obj->reg_set = &gpio->BSRRL; + obj->reg_clr = &gpio->BSRRH; +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + MBED_ASSERT(obj->pin != (PinName)NC); + if (direction == PIN_OUTPUT) { + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); + } else { // PIN_INPUT + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/gpio_irq_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,260 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include <stddef.h> +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +#define EDGE_NONE (0) +#define EDGE_RISE (1) +#define EDGE_FALL (2) +#define EDGE_BOTH (3) + +#define CHANNEL_NUM (16) + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uint32_t channel_gpio[CHANNEL_NUM] = {0}; + +static gpio_irq_handler irq_handler[CHANNEL_NUM] = {NULL}; + +static void handle_interrupt_in(uint32_t pin_index) { + uint32_t pin = (uint32_t)(1 << pin_index); + + // Clear interrupt flag + if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { + GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[pin_index]); + + __HAL_GPIO_EXTI_CLEAR_FLAG(pin); + + if (channel_ids[pin_index] == 0) return; + + // Check which edge has generated the irq + if ((gpio->IDR & pin) == 0) { + irq_handler[pin_index](channel_ids[pin_index], IRQ_FALL); + } else { + irq_handler[pin_index](channel_ids[pin_index], IRQ_RISE); + } + } +} + +// The irq_index is passed to the function +// EXTI line 0 +static void gpio_irq0(void) { + handle_interrupt_in(0); +} +// EXTI line 1 +static void gpio_irq1(void) { + handle_interrupt_in(1); +} +// EXTI line 2 +static void gpio_irq2(void) { + handle_interrupt_in(2); +} +// EXTI line 3 +static void gpio_irq3(void) { + handle_interrupt_in(3); +} +// EXTI line 4 +static void gpio_irq4(void) { + handle_interrupt_in(4); +} +// EXTI lines 5 to 9 +static void gpio_irq5(void) { + uint8_t i; + + for (i = 5; i <= 9; i++) + { + handle_interrupt_in(i); + } +} +// EXTI lines 10 to 15 +static void gpio_irq6(void) { + uint8_t i; + + for (i = 10; i <= 15; i++) + { + handle_interrupt_in(i); + } +} + +extern uint32_t Set_GPIO_Clock(uint32_t port_idx); + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + + if (pin == NC) return -1; + + uint32_t port_index = STM_PORT(pin); + uint32_t pin_index = STM_PIN(pin); + + // Select irq number and interrupt routine + switch (pin_index) { + case 0: + irq_n = EXTI0_IRQn; + vector = (uint32_t)&gpio_irq0; + break; + case 1: + irq_n = EXTI1_IRQn; + vector = (uint32_t)&gpio_irq1; + break; + case 2: + irq_n = EXTI2_IRQn; + vector = (uint32_t)&gpio_irq2; + break; + case 3: + irq_n = EXTI3_IRQn; + vector = (uint32_t)&gpio_irq3; + break; + case 4: + irq_n = EXTI4_IRQn; + vector = (uint32_t)&gpio_irq4; + break; + case 5: + case 6: + case 7: + case 8: + case 9: + irq_n = EXTI9_5_IRQn; + vector = (uint32_t)&gpio_irq5; + break; + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + irq_n = EXTI15_10_IRQn; + vector = (uint32_t)&gpio_irq6; + break; + default: + error("InterruptIn error: pin not supported.\n"); + return -1; + } + + // Enable GPIO clock + uint32_t gpio_add = Set_GPIO_Clock(port_index); + + // Configure GPIO + pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); + + // Save informations for future use + obj->irq_n = irq_n; + obj->event = EDGE_NONE; + obj->pin = pin; + channel_ids[pin_index] = id; + channel_gpio[pin_index] = gpio_add; + + irq_handler[pin_index] = handler; + + // Enable EXTI interrupt + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + uint32_t pin_index = STM_PIN(obj->pin); + + channel_ids[pin_index] = 0; + channel_gpio[pin_index] = 0; + // Disable EXTI line + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + obj->event = EDGE_NONE; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + uint32_t mode = STM_MODE_INPUT; + uint32_t pull = GPIO_NOPULL; + + if (enable) { + + pull = GPIO_NOPULL; + + if (event == IRQ_RISE) { + if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { + mode = STM_MODE_IT_RISING_FALLING; + obj->event = EDGE_BOTH; + } else { // NONE or RISE + mode = STM_MODE_IT_RISING; + obj->event = EDGE_RISE; + } + } + + if (event == IRQ_FALL) { + if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { + mode = STM_MODE_IT_RISING_FALLING; + obj->event = EDGE_BOTH; + } else { // NONE or FALL + mode = STM_MODE_IT_FALLING; + obj->event = EDGE_FALL; + } + } + } else { + mode = STM_MODE_INPUT; + pull = GPIO_NOPULL; + if (event == IRQ_RISE) { + if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { + mode = STM_MODE_IT_FALLING; + obj->event = EDGE_FALL; + } else if (obj->event == EDGE_RISE) { + mode = STM_MODE_IT_EVT_RESET; + obj->event = EDGE_NONE; + } + } + else if (event == IRQ_FALL) { + if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { + mode = STM_MODE_IT_RISING; + obj->event = EDGE_RISE; + } else if (obj->event == IRQ_FALL) { + mode = STM_MODE_IT_EVT_RESET; + obj->event = EDGE_NONE; + } + } + else { + mode = STM_MODE_IT_EVT_RESET; + obj->event = EDGE_NONE; + } + + } + + pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); +} + +void gpio_irq_enable(gpio_irq_t *obj) { + NVIC_EnableIRQ(obj->irq_n); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + NVIC_DisableIRQ(obj->irq_n); + obj->event = EDGE_NONE; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/gpio_object.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,69 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + __IO uint32_t *reg_in; + __IO uint16_t *reg_set; + __IO uint16_t *reg_clr; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + MBED_ASSERT(obj->pin != (PinName)NC); + if (value) { + *obj->reg_set = obj->mask; + } else { + *obj->reg_clr = obj->mask; + } +} + +static inline int gpio_read(gpio_t *obj) { + MBED_ASSERT(obj->pin != (PinName)NC); + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/i2c_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,496 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" + +/* Timeout values for flags and events waiting loops. These timeouts are + not based on accurate values, they just guarantee that the application will + not remain stuck if the I2C communication is corrupted. */ +#define FLAG_TIMEOUT ((int)0x1000) +#define LONG_TIMEOUT ((int)0x8000) + +static const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +I2C_HandleTypeDef I2cHandle; + +int i2c1_inited = 0; +int i2c2_inited = 0; +int i2c3_inited = 0; + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + // Determine the I2C to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + + obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT(obj->i2c != (I2CName)NC); + + // Enable I2C1 clock and pinout if not done + if ((obj->i2c == I2C_1)&& !i2c1_inited) { + i2c1_inited = 1; + __I2C1_CLK_ENABLE(); + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); + } + // Enable I2C2 clock and pinout if not done + if ((obj->i2c == I2C_2)&& !i2c2_inited) { + i2c2_inited = 1; + __I2C2_CLK_ENABLE(); + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); + } + // Enable I2C3 clock and pinout if not done + if ((obj->i2c == I2C_3)&& !i2c3_inited) { + i2c3_inited = 1; + __I2C3_CLK_ENABLE(); + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); + } + + // Reset to clear pending flags if any + i2c_reset(obj); + + // I2C configuration + i2c_frequency(obj, 100000); // 100 kHz per default + + // I2C master by default + obj->slave = 0; +} + +void i2c_frequency(i2c_t *obj, int hz) { + MBED_ASSERT((hz != 0) && (hz <= 400000)); + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + int timeout; + + // wait before init + timeout = LONG_TIMEOUT; + while((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); + + // I2C configuration + I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + I2cHandle.Init.ClockSpeed = hz; + I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; + I2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2; + I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; + I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; + I2cHandle.Init.OwnAddress1 = 0; + I2cHandle.Init.OwnAddress2 = 0; + HAL_I2C_Init(&I2cHandle); + if (obj->slave) { + /* Enable Address Acknowledge */ + I2cHandle.Instance->CR1 |= I2C_CR1_ACK; + } + +} + +inline int i2c_start(i2c_t *obj) { + I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + int timeout; + + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + + // Clear Acknowledge failure flag + __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); + + // Generate the START condition + i2c->CR1 |= I2C_CR1_START; + + // Wait the START condition has been correctly sent + timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) { + if ((timeout--) == 0) { + return 1; + } + } + + return 0; +} + +inline int i2c_stop(i2c_t *obj) { + I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + + // Generate the STOP condition + i2c->CR1 |= I2C_CR1_STOP; + + return 0; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + int timeout; + int count; + int value; + + i2c_start(obj); + + // Wait until SB flag is set + timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) { + timeout--; + if (timeout == 0) { + return -1; + } + } + + i2c->DR = __HAL_I2C_7BIT_ADD_READ(address); + + + // Wait address is acknowledged + timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) { + timeout--; + if (timeout == 0) { + return -1; + } + } + __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle); + + // Read all bytes except last one + for (count = 0; count < (length - 1); count++) { + value = i2c_byte_read(obj, 0); + data[count] = (char)value; + } + + // If not repeated start, send stop. + // Warning: must be done BEFORE the data is read. + if (stop) { + i2c_stop(obj); + } + + // Read the last byte + value = i2c_byte_read(obj, 1); + data[count] = (char)value; + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + int timeout; + int count; + + i2c_start(obj); + + // Wait until SB flag is set + timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) { + timeout--; + if (timeout == 0) { + return -1; + } + } + + i2c->DR = __HAL_I2C_7BIT_ADD_WRITE(address); + + + // Wait address is acknowledged + timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) { + timeout--; + if (timeout == 0) { + return -1; + } + } + __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle); + + for (count = 0; count < length; count++) { + if (i2c_byte_write(obj, data[count]) != 1) { + i2c_stop(obj); + return -1; + } + } + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } + + return count; +} + +int i2c_byte_read(i2c_t *obj, int last) { + I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + int timeout; + + if (last) { + // Don't acknowledge the last byte + i2c->CR1 &= ~I2C_CR1_ACK; + } else { + // Acknowledge the byte + i2c->CR1 |= I2C_CR1_ACK; + } + + // Wait until the byte is received + timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { + if ((timeout--) == 0) { + return -1; + } + } + + return (int)i2c->DR; +} + +int i2c_byte_write(i2c_t *obj, int data) { + I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + int timeout; + + i2c->DR = (uint8_t)data; + + // Wait until the byte is transmitted + timeout = FLAG_TIMEOUT; + while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) && + (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == RESET)) { + if ((timeout--) == 0) { + return 0; + } + } + + return 1; +} + +void i2c_reset(i2c_t *obj) { + int timeout; + + // wait before reset + timeout = LONG_TIMEOUT; + while((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); + + if (obj->i2c == I2C_1) { + __I2C1_FORCE_RESET(); + __I2C1_RELEASE_RESET(); + } + if (obj->i2c == I2C_2) { + __I2C2_FORCE_RESET(); + __I2C2_RELEASE_RESET(); + } + if (obj->i2c == I2C_3) { + __I2C3_FORCE_RESET(); + __I2C3_RELEASE_RESET(); + } +} + +#if DEVICE_I2CSLAVE + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + uint16_t tmpreg = 0; + + // Get the old register value + tmpreg = i2c->OAR1; + // Reset address bits + tmpreg &= 0xFC00; + // Set new address + tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits + // Store the new register value + i2c->OAR1 = tmpreg; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) { + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + if (enable_slave) { + obj->slave = 1; + /* Enable Address Acknowledge */ + I2cHandle.Instance->CR1 |= I2C_CR1_ACK; + } +} + +// See I2CSlave.h +#define NoData 0 // the slave has not been addressed +#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) +#define WriteGeneral 2 // the master is writing to all slave +#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) + +int i2c_slave_receive(i2c_t *obj) { + int retValue = NoData; + + if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { + if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { + if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TRA) == 1) + retValue = ReadAddressed; + else + retValue = WriteAddressed; + + __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); + } + } + + return (retValue); +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) { + uint32_t Timeout; + int size = 0; + + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + + while (length > 0) { + /* Wait until RXNE flag is set */ + // Wait until the byte is received + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + /* Read data from DR */ + (*data++) = I2cHandle.Instance->DR; + length--; + size++; + + if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) { + /* Read data from DR */ + (*data++) = I2cHandle.Instance->DR; + length--; + size++; + } + } + + /* Wait until STOP flag is set */ + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(&I2cHandle); + + /* Wait until BUSY flag is reset */ + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + return size; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + uint32_t Timeout; + int size = 0; + + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + + while (length > 0) { + /* Wait until TXE flag is set */ + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + + /* Write data to DR */ + I2cHandle.Instance->DR = (*data++); + length--; + size++; + + if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) { + /* Write data to DR */ + I2cHandle.Instance->DR = (*data++); + length--; + size++; + } + } + + /* Wait until AF flag is set */ + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_AF) == RESET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); + + + /* Wait until BUSY flag is reset */ + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + I2cHandle.State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(&I2cHandle); + + return size; +} + + +#endif // DEVICE_I2CSLAVE + +#endif // DEVICE_I2C
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/mbed_overrides.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,36 @@ +/* mbed Microcontroller Library + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "cmsis.h" + +// This function is called after RAM initialization and before main. +void mbed_sdk_init() { + // Update the SystemCoreClock variable. + SystemCoreClockUpdate(); + // Need to restart HAL driver after the RAM is initialized + HAL_Init(); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/objects.h Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,109 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct dac_s { + DACName dac; + PinName channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/pinmap.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,138 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "PortNames.h" +#include "mbed_error.h" + +// GPIO mode look-up table +static const uint32_t gpio_mode[13] = { + 0x00000000, // 0 = GPIO_MODE_INPUT + 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP + 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD + 0x00000002, // 3 = GPIO_MODE_AF_PP + 0x00000012, // 4 = GPIO_MODE_AF_OD + 0x00000003, // 5 = GPIO_MODE_ANALOG + 0x10110000, // 6 = GPIO_MODE_IT_RISING + 0x10210000, // 7 = GPIO_MODE_IT_FALLING + 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING + 0x10120000, // 9 = GPIO_MODE_EVT_RISING + 0x10220000, // 10 = GPIO_MODE_EVT_FALLING + 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING + 0x10000000 // 12 = Reset GPIO_MODE_IT_EVT +}; + +// Enable GPIO clock and return GPIO base address +uint32_t Set_GPIO_Clock(uint32_t port_idx) { + uint32_t gpio_add = 0; + switch (port_idx) { + case PortA: + gpio_add = GPIOA_BASE; + __GPIOA_CLK_ENABLE(); + break; + case PortB: + gpio_add = GPIOB_BASE; + __GPIOB_CLK_ENABLE(); + break; + case PortC: + gpio_add = GPIOC_BASE; + __GPIOC_CLK_ENABLE(); + break; + case PortD: + gpio_add = GPIOD_BASE; + __GPIOD_CLK_ENABLE(); + break; + case PortH: + gpio_add = GPIOH_BASE; + __GPIOH_CLK_ENABLE(); + break; + default: + error("Pinmap error: wrong port number."); + break; + } + return gpio_add; +} + +/** + * Configure pin (mode, speed, output type and pull-up/pull-down) + */ +void pin_function(PinName pin, int data) { + MBED_ASSERT(pin != (PinName)NC); + // Get the pin informations + uint32_t mode = STM_PIN_MODE(data); + uint32_t pupd = STM_PIN_PUPD(data); + uint32_t afnum = STM_PIN_AFNUM(data); + + uint32_t port_index = STM_PORT(pin); + uint32_t pin_index = STM_PIN(pin); + + // Enable GPIO clock + uint32_t gpio_add = Set_GPIO_Clock(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + // Configure GPIO + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); + GPIO_InitStructure.Mode = gpio_mode[mode]; + GPIO_InitStructure.Pull = pupd; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_InitStructure.Alternate = afnum; + HAL_GPIO_Init(gpio, &GPIO_InitStructure); + + // [TODO] Disconnect JTAG-DP + SW-DP signals. + // Warning: Need to reconnect under reset + //if ((pin == PA_13) || (pin == PA_14)) { + // + //} + //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) { + // + //} +} + +/** + * Configure pin pull-up/pull-down + */ +void pin_mode(PinName pin, PinMode mode) { + MBED_ASSERT(pin != (PinName)NC); + uint32_t port_index = STM_PORT(pin); + uint32_t pin_index = STM_PIN(pin); + + // Enable GPIO clock + uint32_t gpio_add = Set_GPIO_Clock(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + // Configure pull-up/pull-down resistors + uint32_t pupd = (uint32_t)mode; + if (pupd > 2) + pupd = 0; // Open-drain = No pull-up/No pull-down + gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); + gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); + +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/port_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,97 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "mbed_error.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT + +extern uint32_t Set_GPIO_Clock(uint32_t port_idx); + +// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) +// low nibble = pin number +PinName port_pin(PortName port, int pin_n) { + return (PinName)(pin_n + (port << 4)); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + uint32_t port_index = (uint32_t)port; + + // Enable GPIO clock + uint32_t gpio_add = Set_GPIO_Clock(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + // Fill PORT object structure for future use + obj->port = port; + obj->mask = mask; + obj->direction = dir; + obj->reg_in = &gpio->IDR; + obj->reg_out = &gpio->ODR; + + port_dir(obj, dir); +} + +void port_dir(port_t *obj, PinDirection dir) { + uint32_t i; + obj->direction = dir; + for (i = 0; i < 16; i++) { // Process all pins + if (obj->mask & (1 << i)) { // If the pin is used + if (dir == PIN_OUTPUT) { + pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); + } else { // PIN_INPUT + pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + } + } + } +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + for (i = 0; i < 16; i++) { // Process all pins + if (obj->mask & (1 << i)) { // If the pin is used + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) { + if (obj->direction == PIN_OUTPUT) { + return (*obj->reg_out & obj->mask); + } else { // PIN_INPUT + return (*obj->reg_in & obj->mask); + } +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/pwmout_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,284 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "pwmout_api.h" + +#if DEVICE_PWMOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +// TIM5 cannot be used because already used by the us_ticker +static const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 +// {PA_5, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM8)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N +// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 +// {PA_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH1N + {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 +// {PB_0, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 +// {PB_1, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N +// {PB_14, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2N + {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N +// {PB_15, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM1_CH3N + + {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 +// {PC_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 +// {PC_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 +// {PC_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 +// {PC_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH4 + + {NC, NC, 0} +}; + +static TIM_HandleTypeDef TimHandle; + +void pwmout_init(pwmout_t* obj, PinName pin) { + // Get the peripheral name from the pin and assign it to the object + obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + + if (obj->pwm == (PWMName)NC) { + error("PWM error: pinout mapping failed."); + } + + // Enable TIM clock + if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE(); + if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); + if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); + if (obj->pwm == PWM_4) __TIM4_CLK_ENABLE(); + if (obj->pwm == PWM_9) __TIM9_CLK_ENABLE(); + if (obj->pwm == PWM_10) __TIM10_CLK_ENABLE(); + if (obj->pwm == PWM_11) __TIM11_CLK_ENABLE(); + + // Configure GPIO + pinmap_pinout(pin, PinMap_PWM); + + obj->pin = pin; + obj->period = 0; + obj->pulse = 0; + + pwmout_period_us(obj, 20000); // 20 ms per default +} + +void pwmout_free(pwmout_t* obj) { + // Configure GPIO + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); +} + +void pwmout_write(pwmout_t* obj, float value) { + TIM_OC_InitTypeDef sConfig; + int channel = 0; + int complementary_channel = 0; + + TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); + + if (value < (float)0.0) { + value = 0.0; + } else if (value > (float)1.0) { + value = 1.0; + } + + obj->pulse = (uint32_t)((float)obj->period * value); + + // Configure channels + sConfig.OCMode = TIM_OCMODE_PWM1; + sConfig.Pulse = obj->pulse; + sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH; + sConfig.OCFastMode = TIM_OCFAST_DISABLE; + sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; + + switch (obj->pin) { + + // Channels 1 + case PA_0: + case PA_5: + case PA_6: + case PA_8: + case PA_15: + case PB_4: + case PB_6: + case PC_6: + channel = TIM_CHANNEL_1; + break; + + // Channels 1N + case PA_7: + case PB_13: + channel = TIM_CHANNEL_1; + complementary_channel = 1; + break; + + // Channels 2 + case PA_1: + case PA_9: + case PB_3: + case PB_5: + case PB_7: + case PC_7: + channel = TIM_CHANNEL_2; + break; + + // Channels 2N + case PB_0: + case PB_14: + channel = TIM_CHANNEL_2; + complementary_channel = 1; + break; + + // Channels 3 + case PA_2: + case PA_10: + case PB_8: + case PB_10: + case PC_8: + channel = TIM_CHANNEL_3; + break; + + // Channels 3N + case PB_1: + case PB_15: + channel = TIM_CHANNEL_3; + complementary_channel = 1; + break; + + // Channels 4 + case PA_3: + case PA_11: + case PB_9: + case PB_11: + case PC_9: + channel = TIM_CHANNEL_4; + break; + + default: + return; + } + + HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel); + if (complementary_channel) { + HAL_TIMEx_PWMN_Start(&TimHandle, channel); + } else { + HAL_TIM_PWM_Start(&TimHandle, channel); + } +} + +float pwmout_read(pwmout_t* obj) { + float value = 0; + if (obj->period > 0) { + value = (float)(obj->pulse) / (float)(obj->period); + } + return ((value > (float)1.0) ? (float)(1.0) : (value)); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +void pwmout_period_us(pwmout_t* obj, int us) { + TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); + + float dc = pwmout_read(obj); + + __HAL_TIM_DISABLE(&TimHandle); + + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); + + TimHandle.Init.Period = us - 1; + TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick + TimHandle.Init.ClockDivision = 0; + TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + HAL_TIM_PWM_Init(&TimHandle); + + // Set duty cycle again + pwmout_write(obj, dc); + + // Save for future use + obj->period = us; + + __HAL_TIM_ENABLE(&TimHandle); +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + float value = (float)us / (float)obj->period; + pwmout_write(obj, value); +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/rtc_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,198 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "mbed_error.h" + +static int rtc_inited = 0; + +static RTC_HandleTypeDef RtcHandle; + +void rtc_init(void) { + RCC_OscInitTypeDef RCC_OscInitStruct; + uint32_t rtc_freq = 0; + + if (rtc_inited) return; + rtc_inited = 1; + + RtcHandle.Instance = RTC; + + // Enable Power clock + __PWR_CLK_ENABLE(); + + // Enable access to Backup domain + HAL_PWR_EnableBkUpAccess(); + + // Reset Backup domain + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + // Enable LSE Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */ + RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + // Connect LSE to RTC + __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE); + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); + rtc_freq = LSE_VALUE; + } else { + // Enable LSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("RTC error: LSI clock initialization failed."); + } + // Connect LSI to RTC + __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI); + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); + // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture + rtc_freq = 32000; + } + + // Enable RTC + __HAL_RCC_RTC_ENABLE(); + + RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; + RtcHandle.Init.AsynchPrediv = 127; + RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; + RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; + RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + + if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { + error("RTC error: RTC initialization failed."); + } +} + +void rtc_free(void) { + // Enable Power clock + __PWR_CLK_ENABLE(); + + // Enable access to Backup domain + HAL_PWR_EnableBkUpAccess(); + + // Reset Backup domain + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + // Disable access to Backup domain + HAL_PWR_DisableBkUpAccess(); + + // Disable LSI and LSE clocks + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI_OFF; + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + rtc_inited = 0; +} + +int rtc_isenabled(void) { + return rtc_inited; +} + +/* + RTC Registers + RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday + RTC_Month 1=january, 2=february, ..., 12=december + RTC_Date day of the month 1-31 + RTC_Year year 0-99 + struct tm + tm_sec seconds after the minute 0-61 + tm_min minutes after the hour 0-59 + tm_hour hours since midnight 0-23 + tm_mday day of the month 1-31 + tm_mon months since January 0-11 + tm_year years since 1900 + tm_wday days since Sunday 0-6 + tm_yday days since January 1 0-365 + tm_isdst Daylight Saving Time flag +*/ +time_t rtc_read(void) { + RTC_DateTypeDef dateStruct; + RTC_TimeTypeDef timeStruct; + struct tm timeinfo; + + RtcHandle.Instance = RTC; + + // Read actual date and time + // Warning: the time must be read first! + HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); + HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); + + // Setup a tm structure based on the RTC + timeinfo.tm_wday = dateStruct.WeekDay; + timeinfo.tm_mon = dateStruct.Month - 1; + timeinfo.tm_mday = dateStruct.Date; + timeinfo.tm_year = dateStruct.Year + 100; + timeinfo.tm_hour = timeStruct.Hours; + timeinfo.tm_min = timeStruct.Minutes; + timeinfo.tm_sec = timeStruct.Seconds; + + // Convert to timestamp + time_t t = mktime(&timeinfo); + + return t; +} + +void rtc_write(time_t t) { + RTC_DateTypeDef dateStruct; + RTC_TimeTypeDef timeStruct; + + RtcHandle.Instance = RTC; + + // Convert the time into a tm + struct tm *timeinfo = localtime(&t); + + // Fill RTC structures + dateStruct.WeekDay = timeinfo->tm_wday; + dateStruct.Month = timeinfo->tm_mon + 1; + dateStruct.Date = timeinfo->tm_mday; + dateStruct.Year = timeinfo->tm_year - 100; + timeStruct.Hours = timeinfo->tm_hour; + timeStruct.Minutes = timeinfo->tm_min; + timeStruct.Seconds = timeinfo->tm_sec; + timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; + timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; + + // Change the RTC current date/time + HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); + HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/serial_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,397 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "mbed_assert.h" +#include "serial_api.h" + +#if DEVICE_SERIAL + +#include "cmsis.h" +#include "pinmap.h" +#include <string.h> + +static const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NC, 0} +}; + +#define UART_NUM (6) + +static uint32_t serial_irq_ids[UART_NUM] = {0}; + +static uart_irq_handler irq_handler; + +UART_HandleTypeDef UartHandle; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +static void init_uart(serial_t *obj) { + UartHandle.Instance = (USART_TypeDef *)(obj->uart); + + UartHandle.Init.BaudRate = obj->baudrate; + UartHandle.Init.WordLength = obj->databits; + UartHandle.Init.StopBits = obj->stopbits; + UartHandle.Init.Parity = obj->parity; + UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + + if (obj->pin_rx == NC) { + UartHandle.Init.Mode = UART_MODE_TX; + } else if (obj->pin_tx == NC) { + UartHandle.Init.Mode = UART_MODE_RX; + } else { + UartHandle.Init.Mode = UART_MODE_TX_RX; + } + + HAL_UART_Init(&UartHandle); +} + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + // Determine the UART to use (UART_1, UART_2, ...) + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + + // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object + obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT(obj->uart != (UARTName)NC); + + // Enable USART clock + switch (obj->uart) { + case UART_1: + __USART1_CLK_ENABLE(); + obj->index = 0; + break; + case UART_2: + __USART2_CLK_ENABLE(); + obj->index = 1; + break; + case UART_3: + __USART3_CLK_ENABLE(); + obj->index = 2; + break; + case UART_4: + __UART4_CLK_ENABLE(); + obj->index = 3; + break; + case UART_5: + __UART5_CLK_ENABLE(); + obj->index = 4; + break; + case UART_6: + __USART6_CLK_ENABLE(); + obj->index = 5; + break; + } + + // Configure the UART pins + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + // Configure UART + obj->baudrate = 9600; + obj->databits = UART_WORDLENGTH_8B; + obj->stopbits = UART_STOPBITS_1; + obj->parity = UART_PARITY_NONE; + + obj->pin_tx = tx; + obj->pin_rx = rx; + + init_uart(obj); + + // For stdio management + if (obj->uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } + +} + +void serial_free(serial_t *obj) { + // Reset UART and disable clock + switch (obj->uart) { + case UART_1: + __USART1_FORCE_RESET(); + __USART1_RELEASE_RESET(); + __USART1_CLK_DISABLE(); + break; + case UART_2: + __USART2_FORCE_RESET(); + __USART2_RELEASE_RESET(); + __USART2_CLK_DISABLE(); + break; + case UART_3: + __USART3_FORCE_RESET(); + __USART3_RELEASE_RESET(); + __USART3_CLK_DISABLE(); + break; + case UART_4: + __UART4_FORCE_RESET(); + __UART4_RELEASE_RESET(); + __UART4_CLK_DISABLE(); + break; + case UART_5: + __UART5_FORCE_RESET(); + __UART5_RELEASE_RESET(); + __UART5_CLK_DISABLE(); + break; + case UART_6: + __USART6_FORCE_RESET(); + __USART6_RELEASE_RESET(); + __USART6_CLK_DISABLE(); + break; + } + + // Configure GPIOs + pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + + serial_irq_ids[obj->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) { + obj->baudrate = baudrate; + init_uart(obj); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + if (data_bits == 9) { + obj->databits = UART_WORDLENGTH_9B; + } else { + obj->databits = UART_WORDLENGTH_8B; + } + + switch (parity) { + case ParityOdd: + case ParityForced0: + obj->parity = UART_PARITY_ODD; + break; + case ParityEven: + case ParityForced1: + obj->parity = UART_PARITY_EVEN; + break; + default: // ParityNone + obj->parity = UART_PARITY_NONE; + break; + } + + if (stop_bits == 2) { + obj->stopbits = UART_STOPBITS_2; + } else { + obj->stopbits = UART_STOPBITS_1; + } + + init_uart(obj); +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ + +static void uart_irq(UARTName name, int id) { + UartHandle.Instance = (USART_TypeDef *)name; + if (serial_irq_ids[id] != 0) { + if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { + irq_handler(serial_irq_ids[id], TxIrq); + __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC); + } + if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { + irq_handler(serial_irq_ids[id], RxIrq); + __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE); + } + } +} + +static void uart1_irq(void) { + uart_irq(UART_1, 0); +} +static void uart2_irq(void) { + uart_irq(UART_2, 1); +} +static void uart3_irq(void) { + uart_irq(UART_3, 2); +} +static void uart4_irq(void) { + uart_irq(UART_4, 3); +} +static void uart5_irq(void) { + uart_irq(UART_5, 4); +} +static void uart6_irq(void) { + uart_irq(UART_6, 5); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + + UartHandle.Instance = (USART_TypeDef *)(obj->uart); + + switch (obj->uart) { + case UART_1: + irq_n = USART1_IRQn; + vector = (uint32_t)&uart1_irq; + break; + + case UART_2: + irq_n = USART2_IRQn; + vector = (uint32_t)&uart2_irq; + break; + + case UART_3: + irq_n = USART3_IRQn; + vector = (uint32_t)&uart3_irq; + break; + + case UART_4: + irq_n = UART4_IRQn; + vector = (uint32_t)&uart4_irq; + break; + + case UART_5: + irq_n = UART5_IRQn; + vector = (uint32_t)&uart5_irq; + break; + + case UART_6: + irq_n = USART6_IRQn; + vector = (uint32_t)&uart6_irq; + break; + } + + if (enable) { + + if (irq == RxIrq) { + __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); + } else { // TxIrq + __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); + } + + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + } else { // disable + + int all_disabled = 0; + + if (irq == RxIrq) { + __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); + // Check if TxIrq is disabled too + if ((UartHandle.Instance->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1; + } else { // TxIrq + __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TXE); + // Check if RxIrq is disabled too + if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; + } + + if (all_disabled) NVIC_DisableIRQ(irq_n); + + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ + +int serial_getc(serial_t *obj) { + USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); + while (!serial_readable(obj)); + return (int)(uart->DR & 0x1FF); +} + +void serial_putc(serial_t *obj, int c) { + USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); + while (!serial_writable(obj)); + uart->DR = (uint32_t)(c & 0x1FF); +} + +int serial_readable(serial_t *obj) { + int status; + UartHandle.Instance = (USART_TypeDef *)(obj->uart); + // Check if data is received + status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); + return status; +} + +int serial_writable(serial_t *obj) { + int status; + UartHandle.Instance = (USART_TypeDef *)(obj->uart); + // Check if data is transmitted + status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); + return status; +} + +void serial_clear(serial_t *obj) { + UartHandle.Instance = (USART_TypeDef *)(obj->uart); + __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TXE); + __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE); +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + UartHandle.Instance = (USART_TypeDef *)(obj->uart); + HAL_LIN_SendBreak(&UartHandle); +} + +void serial_break_clear(serial_t *obj) { +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/sleep.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "sleep_api.h" + +#if DEVICE_SLEEP + +#include "cmsis.h" + +static TIM_HandleTypeDef TimMasterHandle; + +void sleep(void) { + TimMasterHandle.Instance = TIM5; + + // Disable HAL tick interrupt + __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); + + // Request to enter SLEEP mode + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + + // Enable HAL tick interrupt + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); +} + +void deepsleep(void) { + // Request to enter STOP mode with regulator in low power mode + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); + + // After wake-up from STOP reconfigure the PLL + SetSysClock(); +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/spi_api.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,324 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "mbed_assert.h" +#include "spi_api.h" + +#if DEVICE_SPI + +#include <math.h> +#include "cmsis.h" +#include "pinmap.h" + +static const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +static SPI_HandleTypeDef SpiHandle; + +static void init_spi(spi_t *obj) { + SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); + + __HAL_SPI_DISABLE(&SpiHandle); + + SpiHandle.Init.Mode = obj->mode; + SpiHandle.Init.BaudRatePrescaler = obj->br_presc; + SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; + SpiHandle.Init.CLKPhase = obj->cpha; + SpiHandle.Init.CLKPolarity = obj->cpol; + SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + SpiHandle.Init.CRCPolynomial = 7; + SpiHandle.Init.DataSize = obj->bits; + SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; + SpiHandle.Init.NSS = obj->nss; + SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; + + HAL_SPI_Init(&SpiHandle); + + __HAL_SPI_ENABLE(&SpiHandle); +} + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // Determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT(obj->spi != (SPIName)NC); + + // Enable SPI clock + if (obj->spi == SPI_1) { + __SPI1_CLK_ENABLE(); + } + if (obj->spi == SPI_2) { + __SPI2_CLK_ENABLE(); + } + if (obj->spi == SPI_3) { + __SPI3_CLK_ENABLE(); + } + + // Configure the SPI pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + + // Save new values + obj->bits = SPI_DATASIZE_8BIT; + obj->cpol = SPI_POLARITY_LOW; + obj->cpha = SPI_PHASE_1EDGE; + obj->br_presc = SPI_BAUDRATEPRESCALER_256; + + obj->pin_miso = miso; + obj->pin_mosi = mosi; + obj->pin_sclk = sclk; + obj->pin_ssel = ssel; + + if (ssel == NC) { // SW NSS Master mode + obj->mode = SPI_MODE_MASTER; + obj->nss = SPI_NSS_SOFT; + } else { // Slave + pinmap_pinout(ssel, PinMap_SPI_SSEL); + obj->mode = SPI_MODE_SLAVE; + obj->nss = SPI_NSS_HARD_INPUT; + } + + init_spi(obj); +} + +void spi_free(spi_t *obj) { + // Reset SPI and disable clock + if (obj->spi == SPI_1) { + __SPI1_FORCE_RESET(); + __SPI1_RELEASE_RESET(); + __SPI1_CLK_DISABLE(); + } + + if (obj->spi == SPI_2) { + __SPI2_FORCE_RESET(); + __SPI2_RELEASE_RESET(); + __SPI2_CLK_DISABLE(); + } + + if (obj->spi == SPI_3) { + __SPI3_FORCE_RESET(); + __SPI3_RELEASE_RESET(); + __SPI3_CLK_DISABLE(); + } + + // Configure GPIOs + pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + // Save new values + if (bits == 16) { + obj->bits = SPI_DATASIZE_16BIT; + } else { + obj->bits = SPI_DATASIZE_8BIT; + } + + switch (mode) { + case 0: + obj->cpol = SPI_POLARITY_LOW; + obj->cpha = SPI_PHASE_1EDGE; + break; + case 1: + obj->cpol = SPI_POLARITY_LOW; + obj->cpha = SPI_PHASE_2EDGE; + break; + case 2: + obj->cpol = SPI_POLARITY_HIGH; + obj->cpha = SPI_PHASE_1EDGE; + break; + default: + obj->cpol = SPI_POLARITY_HIGH; + obj->cpha = SPI_PHASE_2EDGE; + break; + } + + if (slave == 0) { + obj->mode = SPI_MODE_MASTER; + obj->nss = SPI_NSS_SOFT; + } else { + obj->mode = SPI_MODE_SLAVE; + obj->nss = SPI_NSS_HARD_INPUT; + } + + init_spi(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + // Note: The frequencies are obtained with SPI1 clock = 48 MHz (APB2 clock) + if (obj->spi == SPI_1) { + if (hz < 375000) { + obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 187.5 kHz + } else if ((hz >= 375000) && (hz < 750000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 375 kHz + } else if ((hz >= 750000) && (hz < 1500000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 0.75 MHz + } else if ((hz >= 1500000) && (hz < 3000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.5 MHz + } else if ((hz >= 3000000) && (hz < 6000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 3 MHz + } else if ((hz >= 6000000) && (hz < 12000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 6 MHz + } else if ((hz >= 12000000) && (hz < 24000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 12 MHz + } else { // >= 24000000 + obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 24 MHz + } + // Note: The frequencies are obtained with SPI2/3 clock = 48 MHz (APB1 clock) + } else if ((obj->spi == SPI_2) || (obj->spi == SPI_3)) { + if (hz < 375000) { + obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 187.5 kHz + } else if ((hz >= 375000) && (hz < 750000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 375 kHz + } else if ((hz >= 750000) && (hz < 1500000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 0.75 MHz + } else if ((hz >= 1500000) && (hz < 3000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.5 MHz + } else if ((hz >= 3000000) && (hz < 6000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 3 MHz + } else if ((hz >= 6000000) && (hz < 12000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 6 MHz + } else if ((hz >= 12000000) && (hz < 24000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 12 MHz + } else { // >= 24000000 + obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 24 MHz + } + } + + init_spi(obj); +} + +static inline int ssp_readable(spi_t *obj) { + int status; + SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); + // Check if data is received + status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); + return status; +} + +static inline int ssp_writeable(spi_t *obj) { + int status; + SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); + // Check if data is transmitted + status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); + return status; +} + +static inline void ssp_write(spi_t *obj, int value) { + SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); + while (!ssp_writeable(obj)); + spi->DR = (uint16_t)value; +} + +static inline int ssp_read(spi_t *obj) { + SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); + while (!ssp_readable(obj)); + return (int)spi->DR; +} + +static inline int ssp_busy(spi_t *obj) { + int status; + SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); + status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); + return status; +} + +int spi_master_write(spi_t *obj, int value) { + ssp_write(obj, value); + return ssp_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); +}; + +int spi_slave_read(spi_t *obj) { + SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); + while (!ssp_readable(obj)); + return (int)spi->DR; +} + +void spi_slave_write(spi_t *obj, int value) { + SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); + while (!ssp_writeable(obj)); + spi->DR = (uint16_t)value; +} + +int spi_busy(spi_t *obj) { + return ssp_busy(obj); +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_MTS_MDOT_F405RG/us_ticker.c Thu Nov 13 08:30:07 2014 +0000 @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include <stddef.h> +#include "us_ticker_api.h" +#include "PeripheralNames.h" + +#define TIM_MST TIM5 + +static TIM_HandleTypeDef TimMasterHandle; +static int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) return; + us_ticker_inited = 1; + + TimMasterHandle.Instance = TIM_MST; + + HAL_InitTick(0); // The passed value is not used +} + +uint32_t us_ticker_read() { + if (!us_ticker_inited) us_ticker_init(); + return TIM_MST->CNT; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + // Set new output compare value + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); + // Enable IT + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); +} + +void us_ticker_disable_interrupt(void) { + __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); +} + +void us_ticker_clear_interrupt(void) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); +}