Revision 0:66fdbf2cc578, committed 2012-01-01
- Comitter:
- pangsk
- Date:
- Sun Jan 01 21:54:11 2012 +0000
- Child:
- 1:27a1606deace
- Commit message:
- Initial release
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF12B.cpp Sun Jan 01 21:54:11 2012 +0000
@@ -0,0 +1,278 @@
+/* RF12B Library. Based on work done by JeeLabs.org ported to mbed by SK Pang.
+http://jeelabs.net/projects/cafe/wiki/RF12
+
+http://opensource.org/licenses/mit-license.php
+
+Jan 2012 skpang.co.uk
+
+*/
+
+#include "RF12B.h"
+
+#include "RF_defs.h"
+// RF12 command codes
+#define RF_RECEIVER_ON 0x82DD
+#define RF_XMITTER_ON 0x823D
+#define RF_IDLE_MODE 0x820D
+#define RF_SLEEP_MODE 0x8205
+#define RF_WAKEUP_MODE 0x8207
+#define RF_TXREG_WRITE 0xB800
+#define RF_RX_FIFO_READ 0xB000
+#define RF_WAKEUP_TIMER 0xE000
+
+// RF12 status bits
+#define RF_LBD_BIT 0x0400
+#define RF_RSSI_BIT 0x0100
+
+// bits in the node id configuration byte
+#define NODE_BAND 0xC0 // frequency band
+#define NODE_ACKANY 0x20 // ack on broadcast packets if set
+#define NODE_ID 0x1F // id of this node, as A..Z or 1..31
+
+// transceiver states, these determine what to do with each interrupt
+enum {
+ TXCRC1, TXCRC2, TXTAIL, TXDONE, TXIDLE,
+ TXRECV,
+ TXPRE1, TXPRE2, TXPRE3, TXSYN1, TXSYN2,
+};
+
+DigitalOut rfled(LED3);
+DigitalOut t1(p5);
+DigitalOut t2(p6);
+
+RF12B::RF12B(PinName _SDI,
+ PinName _SDO,
+ PinName _SCK,
+ PinName _NCS,
+ PinName _NIRQ):spi(_SDI, _SDO, _SCK),
+ NCS(_NCS), NIRQ(_NIRQ), NIRQ_in(_NIRQ), rfled(LED3),t1(p5),t2(p6) {
+
+ /* SPI frequency, word lenght, polarity and phase */
+ spi.format(8,0);
+ spi.frequency(2000000);
+
+ /* Set ~CS high */
+ NCS = 1;
+
+ /* Setup interrupt to happen on falling edge of NIRQ */
+ NIRQ.fall(this, &RF12B::rxISR);
+}
+
+
+/**********************************************************************
+ * PRIVATE FUNCTIONS
+ *********************************************************************/
+
+/* Initialises the RF12B module */
+void RF12B::init(uint8_t id, uint8_t band, uint8_t g) {
+
+ nodeid = id;
+ group = g;
+ rf12_grp = g;
+
+ writeCmd(0x0000); // intitial SPI transfer added to avoid power-up problem
+ writeCmd(RF_SLEEP_MODE); // DC (disable clk pin), enable lbd
+
+ // wait until RFM12B is out of power-up reset, this takes several *seconds*
+ writeCmd(RF_TXREG_WRITE); // in case we're still in OOK mode
+
+ while (NIRQ == 0) writeCmd(0x0000);
+
+ writeCmd(0x80C7 | (2 << 4)); // EL (ena TX), EF (ena RX FIFO), 12.0pF
+ writeCmd(0xA640); // 868MHz
+ writeCmd(0xC606); // approx 49.2 Kbps, i.e. 10000/29/(1+6) Kbps
+ writeCmd(0x94A2); // VDI,FAST,134kHz,0dBm,-91dBm
+ writeCmd(0xC2AC); // AL,!ml,DIG,DQD4
+
+ writeCmd(0xCA83); // FIFO8,2-SYNC,!ff,DR
+ writeCmd(0xCE00 | 1); // SYNC=2DXX；
+
+ writeCmd(0xC483); // @PWR,NO RSTRIC,!st,!fi,OE,EN
+ writeCmd(0x9850); // !mp,90kHz,MAX OUT
+ writeCmd(0xCC77); // OB1，OB0, LPX,！ddy，DDIT，BW0
+ writeCmd(0xE000); // NOT USE
+ writeCmd(0xC800); // NOT USE
+ writeCmd(0xC049); // 1.66MHz,3.1V
+
+ rxstate = TXIDLE;
+
+ rfled = 0;
+}
+
+/* Write a command to the RF Module */
+unsigned int RF12B::writeCmd(unsigned int cmd) {
+ NCS = 0;
+ unsigned int recv = spi.write(cmd >>8);
+ recv = spi.write(cmd);
+ NCS = 1;
+ return recv;
+}
+
+/* Sends a byte of data across RF */
+void RF12B::send(unsigned char data) {
+ while (NIRQ);
+ writeCmd(0xB800 + data);
+}
+
+
+/* Interrupt routine for data reception and Txing */
+void RF12B::rxISR() {
+
+ // a transfer of 2x 16 bits @ 2 MHz over SPI takes 2x 8 us inside this ISR
+ writeCmd(0x0000);
+
+ if (rxstate == TXRECV) {
+ uint8_t in = rf12_xfer(RF_RX_FIFO_READ);
+
+ if (rxfill == 0 && group != 0)
+ rf12_buf[rxfill++] = group;
+
+ rf12_buf[rxfill++] = in;
+ rf12_crc = _crc16_update(rf12_crc, in);
+
+ if (rxfill >= rf12_len + 5 || rxfill >= RF_MAX)
+ rf12_xfer(RF_IDLE_MODE);
+ } else {
+ uint8_t out;
+
+ if (rxstate < 0) {
+ uint8_t pos = 3 + rf12_len + rxstate++;
+ out = rf12_buf[pos];
+ rf12_crc = _crc16_update(rf12_crc, out);
+ } else
+ switch (rxstate++) {
+ case TXSYN1: out = 0x2D; break;
+ case TXSYN2: out = rf12_grp; rxstate = - (2 + rf12_len); break;
+ case TXCRC1: out = rf12_crc; break;
+ case TXCRC2: out = rf12_crc >> 8; break;
+ case TXDONE: rf12_xfer(RF_IDLE_MODE); // fall through
+ default: out = 0xAA;
+ }
+
+ rf12_xfer(RF_TXREG_WRITE + out);
+ }
+ }
+
+
+void RF12B::rf12_sendStart (uint8_t hdr, const void* ptr, uint8_t len)
+{
+ rf12_len = len;
+ memcpy((void*) rf12_data, ptr, len);
+
+ rf12_sendStart2(hdr);
+
+}
+void RF12B::rf12_sendStart2 (uint8_t hdr) {
+ rf12_hdr = hdr & RF12_HDR_DST ? hdr :
+ (hdr & ~RF12_HDR_MASK) + (nodeid & NODE_ID);
+
+ /* if (crypter != 0)
+ crypter(1);
+ */
+ rf12_crc = ~0;
+
+ rf12_crc = _crc16_update(rf12_crc, rf12_grp);
+ rxstate = TXPRE1;
+
+ rf12_xfer(RF_XMITTER_ON); // bytes will be fed via interrupts
+}
+
+
+ uint16_t RF12B::rf12_xfer (uint16_t cmd) {
+ NCS = 0;
+ uint16_t reply = rf12_byte(cmd >> 8) << 8;
+ reply |= rf12_byte(cmd);
+ NCS = 1;
+ return reply;
+}
+
+ void RF12B::rf12_recvStart (void) {
+ rxfill = rf12_len = 0;
+ rf12_crc = ~0;
+
+ if (group != 0)
+ rf12_crc = _crc16_update(~0, group);
+
+ rxstate = TXRECV;
+ rf12_xfer(RF_RECEIVER_ON);
+}
+uint16_t RF12B::check_crc(void)
+{
+
+ return rf12_crc;
+}
+uint8_t RF12B::length(void)
+{
+
+ return rf12_len;
+}
+ uint8_t* RF12B::get_data(void)
+{
+ return (uint8_t*)rf12_data;
+
+}
+
+
+uint8_t RF12B::rf12_recvDone (void) {
+
+ int i;
+ if (rxstate == TXRECV && (rxfill >= rf12_len + 5 || rxfill >= RF_MAX)) {
+ rxstate = TXIDLE;
+
+ if (rf12_len > RF12_MAXDATA)
+ rf12_crc = 1; // force bad crc if packet length is invalid
+ if (!(rf12_hdr & RF12_HDR_DST) || (nodeid & NODE_ID) == 31 ||
+ (rf12_hdr & RF12_HDR_MASK) == (nodeid & NODE_ID)) {
+ /*
+ for(i=0;i<rf12_len+6;i++)
+ {
+ printf("%X ",rf12_buf[i]);
+ }
+ printf(" crc:%x",rf12_crc);
+ */
+ /*
+ if (rf12_crc == 0 && crypter != 0)
+ crypter(0);
+ else
+ rf12_seq = -1;
+ */
+ return 1; // it's a broadcast packet or it's addressed to this node
+
+ }
+ }
+ if (rxstate == TXIDLE)
+ rf12_recvStart();
+ return 0;
+}
+
+uint8_t RF12B::rf12_byte(uint8_t out)
+{
+ unsigned char recv = spi.write(out);
+
+ return recv;
+}
+
+uint16_t RF12B::_crc16_update(uint16_t crc, uint8_t data) {
+ int i;
+
+ crc ^= data;
+ for (i = 0; i < 8; ++i)
+ {
+ if (crc & 1)
+ crc = (crc >> 1) ^ 0xA001;
+ else
+ crc = (crc >> 1);
+ }
+
+ return crc;
+}
+
+
+
+
+
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF12B.h Sun Jan 01 21:54:11 2012 +0000
@@ -0,0 +1,90 @@
+#ifndef _RF12B_H
+#define _RF12B_H
+
+#include "mbed.h"
+
+
+#define rf12_grp rf12_buf[0]
+#define rf12_hdr rf12_buf[1]
+#define rf12_len rf12_buf[2]
+#define rf12_data (rf12_buf + 3)
+
+#define RF12_HDR_CTL 0x80
+#define RF12_HDR_DST 0x40
+#define RF12_HDR_ACK 0x20
+#define RF12_HDR_MASK 0x1F
+
+#define RF12_MAXDATA 66
+// maximum transmit / receive buffer: 3 header + data + 2 crc bytes
+#define RF_MAX (RF12_MAXDATA + 5)
+#define PACKET_LEN 16
+
+// shorthand to simplify sending out the proper ACK when requested
+#define RF12_WANTS_ACK ((rf12_hdr & RF12_HDR_ACK) && !(rf12_hdr & RF12_HDR_CTL))
+#define RF12_ACK_REPLY (rf12_hdr & RF12_HDR_DST ? RF12_HDR_CTL : \
+ RF12_HDR_CTL | RF12_HDR_DST | (rf12_hdr & RF12_HDR_MASK))
+
+
+//enum rfmode_t{RX, TX};
+
+class RF12B {
+public:
+ /* Constructor */
+ RF12B(PinName SDI,
+ PinName SDO,
+ PinName SCK,
+ PinName NCS,
+ PinName NIRQ);
+
+
+ /* Initialises the RF12B module */
+ void init(uint8_t id, uint8_t band, uint8_t g);
+
+
+ /* Returns the packet length if data is available in the receive buffer, 0 otherwise*/
+ unsigned int available();
+ void rf12_sendStart (uint8_t hdr, const void* ptr, uint8_t len);
+ void rf12_sendStart2 (uint8_t hdr);
+ uint8_t rf12_recvDone (void);
+ void rf12_recvStart (void);
+ uint16_t check_crc(void);
+ uint8_t length(void);
+ uint8_t* get_data(void);
+
+protected:
+
+ /* SPI module */
+ SPI spi;
+
+ /* Other digital pins */
+ DigitalOut NCS;
+ InterruptIn NIRQ;
+ DigitalIn NIRQ_in;
+ DigitalOut rfled;
+ DigitalOut t1;
+ DigitalOut t2;
+ volatile uint16_t rf12_crc; // running crc value
+ volatile unsigned char rf12_buf[RF_MAX]; // recv/xmit buf, including hdr & crc bytes
+ volatile uint8_t nodeid; // address of this node
+ volatile uint8_t group; // network grou
+ volatile uint8_t rxfill; // number of data bytes in rf12_buf
+ volatile int8_t rxstate; // current transceiver state
+
+
+ /* Write a command to the RF Module */
+ unsigned int writeCmd(unsigned int cmd);
+
+ /* Sends a byte of data across RF */
+ void send(unsigned char data);
+
+ /* Interrupt routine for data reception */
+ void rxISR();
+
+
+ uint16_t _crc16_update(uint16_t crc, uint8_t data);
+
+ uint16_t rf12_xfer (uint16_t cmd);
+ uint8_t rf12_byte(uint8_t out);
+};
+
+#endif /* _RF12B_H */
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/RF_defs.h Sun Jan 01 21:54:11 2012 +0000
@@ -0,0 +1,478 @@
+/*
+ * Open HR20
+ *
+ * target: ATmega169 @ 4 MHz in Honnywell Rondostat HR20E
+ *
+ * compiler: WinAVR-20071221
+ * avr-libc 1.6.0
+ * GCC 4.2.2
+ *
+ * copyright: 2008 Dario Carluccio (hr20-at-carluccio-dot-de)
+ * 2008 Jiri Dobry (jdobry-at-centrum-dot-cz)
+ * 2008 Mario Fischer (MarioFischer-at-gmx-dot-net)
+ * 2007 Michael Smola (Michael-dot-Smola-at-gmx-dot-net)
+ *
+ * license: This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http:*www.gnu.org/licenses
+ */
+
+/*
+ * \file rfm.h
+ * \brief functions to control the RFM12 Radio Transceiver Module
+ * \author Mario Fischer <MarioFischer-at-gmx-dot-net>; Michael Smola <Michael-dot-Smola-at-gmx-dot-net>
+ * \date $Date: 2010/04/17 17:57:02 $
+ * $Rev: 260 $
+ */
+
+
+//#pragma once // multi-iclude prevention. gcc knows this pragma
+#ifndef 0 //rfm_H
+#define rfm_H
+
+
+#define RFM_SPI_16(OUTVAL) rfm_spi16(OUTVAL) //<! a function that gets a uint16_t (clocked out value) and returns a uint16_t (clocked in value)
+
+#define RFM_CLK_OUTPUT 0
+
+/*
+#define RFM_TESTPIN_INIT
+#define RFM_TESTPIN_ON
+#define RFM_TESTPIN_OFF
+#define RFM_TESTPIN_TOG
+
+#define RFM_CONFIG_DISABLE 0x00 //<! RFM_CONFIG_*** are combinable flags, what the RFM shold do
+#define RFM_CONFIG_BROADCASTSTATUS 0x01 //<! Flag that enables the HR20's status broadcast every minute
+
+#define RFM_CONFIG_ENABLEALL 0xff
+*/
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// RFM status bits
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// Interrupt bits, latched ////////////////////////////////////////////////////
+
+#define RFM_STATUS_FFIT 0x8000 // RX FIFO reached the progr. number of bits
+ // Cleared by any FIFO read method
+
+#define RFM_STATUS_RGIT 0x8000 // TX register is ready to receive
+ // Cleared by TX write
+
+#define RFM_STATUS_POR 0x4000 // Power On reset
+ // Cleared by read status
+
+#define RFM_STATUS_RGUR 0x2000 // TX register underrun, register over write
+ // Cleared by read status
+
+#define RFM_STATUS_FFOV 0x2000 // RX FIFO overflow
+ // Cleared by read status
+
+#define RFM_STATUS_WKUP 0x1000 // Wake up timer overflow
+ // Cleared by read status
+
+#define RFM_STATUS_EXT 0x0800 // Interupt changed to low
+ // Cleared by read status
+
+#define RFM_STATUS_LBD 0x0400 // Low battery detect
+
+// Status bits ////////////////////////////////////////////////////////////////
+
+#define RFM_STATUS_FFEM 0x0200 // FIFO is empty
+#define RFM_STATUS_ATS 0x0100 // TX mode: Strong enough RF signal
+#define RFM_STATUS_RSSI 0x0100 // RX mode: signal strength above programmed limit
+#define RFM_STATUS_DQD 0x0080 // Data Quality detector output
+#define RFM_STATUS_CRL 0x0040 // Clock recovery lock
+#define RFM_STATUS_ATGL 0x0020 // Toggling in each AFC cycle
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 1. Configuration Setting Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_CONFIG 0x8000
+
+#define RFM_CONFIG_EL 0x8080 // Enable TX Register
+#define RFM_CONFIG_EF 0x8040 // Enable RX FIFO buffer
+#define RFM_CONFIG_BAND_315 0x8000 // Frequency band
+#define RFM_CONFIG_BAND_433 0x8010
+#define RFM_CONFIG_BAND_868 0x8020
+#define RFM_CONFIG_BAND_915 0x8030
+#define RFM_CONFIG_X_8_5pf 0x8000 // Crystal Load Capacitor
+#define RFM_CONFIG_X_9_0pf 0x8001
+#define RFM_CONFIG_X_9_5pf 0x8002
+#define RFM_CONFIG_X_10_0pf 0x8003
+#define RFM_CONFIG_X_10_5pf 0x8004
+#define RFM_CONFIG_X_11_0pf 0x8005
+#define RFM_CONFIG_X_11_5pf 0x8006
+#define RFM_CONFIG_X_12_0pf 0x8007
+#define RFM_CONFIG_X_12_5pf 0x8008
+#define RFM_CONFIG_X_13_0pf 0x8009
+#define RFM_CONFIG_X_13_5pf 0x800A
+#define RFM_CONFIG_X_14_0pf 0x800B
+#define RFM_CONFIG_X_14_5pf 0x800C
+#define RFM_CONFIG_X_15_0pf 0x800D
+#define RFM_CONFIG_X_15_5pf 0x800E
+#define RFM_CONFIG_X_16_0pf 0x800F
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 2. Power Management Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_POWER_MANAGEMENT 0x8200
+
+#define RFM_POWER_MANAGEMENT_ER 0x8280 // Enable receiver
+#define RFM_POWER_MANAGEMENT_EBB 0x8240 // Enable base band block
+#define RFM_POWER_MANAGEMENT_ET 0x8220 // Enable transmitter
+#define RFM_POWER_MANAGEMENT_ES 0x8210 // Enable synthesizer
+#define RFM_POWER_MANAGEMENT_EX 0x8208 // Enable crystal oscillator
+#define RFM_POWER_MANAGEMENT_EB 0x8204 // Enable low battery detector
+#define RFM_POWER_MANAGEMENT_EW 0x8202 // Enable wake-up timer
+#define RFM_POWER_MANAGEMENT_DC 0x8201 // Disable clock output of CLK pin
+
+#ifndef RFM_CLK_OUTPUT
+ #error RFM_CLK_OUTPUT must be defined to 0 or 1
+#endif
+#if RFM_CLK_OUTPUT
+ #define RFM_TX_ON_PRE() RFM_SPI_16( \
+ RFM_POWER_MANAGEMENT_ES | \
+ RFM_POWER_MANAGEMENT_EX )
+ #define RFM_TX_ON() RFM_SPI_16( \
+ RFM_POWER_MANAGEMENT_ET | \
+ RFM_POWER_MANAGEMENT_ES | \
+ RFM_POWER_MANAGEMENT_EX )
+ #define RFM_RX_ON() RFM_SPI_16( \
+ RFM_POWER_MANAGEMENT_ER | \
+ RFM_POWER_MANAGEMENT_EBB | \
+ RFM_POWER_MANAGEMENT_ES | \
+ RFM_POWER_MANAGEMENT_EX )
+ #define RFM_OFF() RFM_SPI_16( \
+ RFM_POWER_MANAGEMENT_EX )
+#else
+ #define RFM_TX_ON_PRE() RFM_SPI_16( \
+ RFM_POWER_MANAGEMENT_DC | \
+ RFM_POWER_MANAGEMENT_ES | \
+ RFM_POWER_MANAGEMENT_EX )
+ #define RFM_TX_ON() RFM_SPI_16( \
+ RFM_POWER_MANAGEMENT_DC | \
+ RFM_POWER_MANAGEMENT_ET | \
+ RFM_POWER_MANAGEMENT_ES | \
+ RFM_POWER_MANAGEMENT_EX )
+ #define RFM_RX_ON() RFM_SPI_16( \
+ RFM_POWER_MANAGEMENT_DC | \
+ RFM_POWER_MANAGEMENT_ER | \
+ RFM_POWER_MANAGEMENT_EBB | \
+ RFM_POWER_MANAGEMENT_ES | \
+ RFM_POWER_MANAGEMENT_EX )
+ #define RFM_OFF() RFM_SPI_16(RFM_POWER_MANAGEMENT_DC)
+#endif
+///////////////////////////////////////////////////////////////////////////////
+//
+// 3. Frequency Setting Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_FREQUENCY 0xA000
+
+#define RFM_FREQ_315Band(v) (uint16_t)((v/10.0-31)*4000)
+#define RFM_FREQ_433Band(v) (uint16_t)((v/10.0-43)*4000)
+#define RFM_FREQ_868Band(v) (uint16_t)((v/20.0-43)*4000)
+#define RFM_FREQ_915Band(v) (uint16_t)((v/30.0-30)*4000)
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 4. Data Rate Command
+//
+/////////////////////////////////////////////////////////////////////////////////
+
+#define RFM_BAUD_RATE 9600
+
+#define RFM_DATA_RATE 0xC600
+
+#define RFM_DATA_RATE_CS 0xC680
+#define RFM_DATA_RATE_4800 0xC647
+#define RFM_DATA_RATE_9600 0xC623
+#define RFM_DATA_RATE_19200 0xC611
+#define RFM_DATA_RATE_38400 0xC608
+#define RFM_DATA_RATE_57600 0xC605
+
+#define RFM_SET_DATARATE(baud) ( ((baud)<5400) ? (RFM_DATA_RATE_CS|((43104/(baud))-1)) : (RFM_DATA_RATE|((344828UL/(baud))-1)) )
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 5. Receiver Control Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_RX_CONTROL 0x9000
+
+#define RFM_RX_CONTROL_P20_INT 0x9000 // Pin20 = ExternalInt
+#define RFM_RX_CONTROL_P20_VDI 0x9400 // Pin20 = VDI out
+
+#define RFM_RX_CONTROL_VDI_FAST 0x9000 // fast VDI Response time
+#define RFM_RX_CONTROL_VDI_MED 0x9100 // medium
+#define RFM_RX_CONTROL_VDI_SLOW 0x9200 // slow
+#define RFM_RX_CONTROL_VDI_ON 0x9300 // Always on
+
+#define RFM_RX_CONTROL_BW_400 0x9020 // bandwidth 400kHz
+#define RFM_RX_CONTROL_BW_340 0x9040 // bandwidth 340kHz
+#define RFM_RX_CONTROL_BW_270 0x9060 // bandwidth 270kHz
+#define RFM_RX_CONTROL_BW_200 0x9080 // bandwidth 200kHz
+#define RFM_RX_CONTROL_BW_134 0x90A0 // bandwidth 134kHz
+#define RFM_RX_CONTROL_BW_67 0x90C0 // bandwidth 67kHz
+
+#define RFM_RX_CONTROL_GAIN_0 0x9000 // LNA gain 0db
+#define RFM_RX_CONTROL_GAIN_6 0x9008 // LNA gain -6db
+#define RFM_RX_CONTROL_GAIN_14 0x9010 // LNA gain -14db
+#define RFM_RX_CONTROL_GAIN_20 0x9018 // LNA gain -20db
+
+#define RFM_RX_CONTROL_RSSI_103 0x9000 // DRSSI threshold -103dbm
+#define RFM_RX_CONTROL_RSSI_97 0x9001 // DRSSI threshold -97dbm
+#define RFM_RX_CONTROL_RSSI_91 0x9002 // DRSSI threshold -91dbm
+#define RFM_RX_CONTROL_RSSI_85 0x9003 // DRSSI threshold -85dbm
+#define RFM_RX_CONTROL_RSSI_79 0x9004 // DRSSI threshold -79dbm
+#define RFM_RX_CONTROL_RSSI_73 0x9005 // DRSSI threshold -73dbm
+//#define RFM_RX_CONTROL_RSSI_67 0x9006 // DRSSI threshold -67dbm // RF12B reserved
+//#define RFM_RX_CONTROL_RSSI_61 0x9007 // DRSSI threshold -61dbm // RF12B reserved
+
+#define RFM_RX_CONTROL_BW(baud) (((baud)<8000) ? \
+ RFM_RX_CONTROL_BW_67 : \
+ ( \
+ ((baud)<30000) ? \
+ RFM_RX_CONTROL_BW_134 : \
+ RFM_RX_CONTROL_BW_200 \
+ ))
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 6. Data Filter Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_DATA_FILTER 0xC228
+
+#define RFM_DATA_FILTER_AL 0xC2A8 // clock recovery auto-lock
+#define RFM_DATA_FILTER_ML 0xC268 // clock recovery fast mode
+#define RFM_DATA_FILTER_DIG 0xC228 // data filter type digital
+#define RFM_DATA_FILTER_ANALOG 0xC238 // data filter type analog
+#define RFM_DATA_FILTER_DQD(level) (RFM_DATA_FILTER | (level & 0x7))
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 7. FIFO and Reset Mode Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_FIFO 0xCA00
+
+#define RFM_FIFO_AL 0xCA04 // FIFO Start condition sync-word/always
+#define RFM_FIFO_FF 0xCA02 // Enable FIFO fill
+#define RFM_FIFO_DR 0xCA01 // Disable hi sens reset mode
+#define RFM_FIFO_IT(level) (RFM_FIFO | (( (level) & 0xF)<<4))
+
+#define RFM_FIFO_OFF() RFM_SPI_16(RFM_FIFO_IT(8) | RFM_FIFO_DR)
+#define RFM_FIFO_ON() RFM_SPI_16(RFM_FIFO_IT(8) | RFM_FIFO_FF | RFM_FIFO_DR)
+
+/////////////////////////////////////////////////////////////////////////////
+//
+// 8. Receiver FIFO Read
+//
+/////////////////////////////////////////////////////////////////////////////
+
+#define RFM_READ_FIFO() (RFM_SPI_16(0xB000) & 0xFF)
+
+/////////////////////////////////////////////////////////////////////////////
+//
+// 9. AFC Command
+//
+/////////////////////////////////////////////////////////////////////////////
+
+#define RFM_AFC 0xC400
+
+#define RFM_AFC_EN 0xC401
+#define RFM_AFC_OE 0xC402
+#define RFM_AFC_FI 0xC404
+#define RFM_AFC_ST 0xC408
+
+// Limits the value of the frequency offset register to the next values:
+
+#define RFM_AFC_RANGE_LIMIT_NO 0xC400 // 0: No restriction
+#define RFM_AFC_RANGE_LIMIT_15_16 0xC410 // 1: +15 fres to -16 fres
+#define RFM_AFC_RANGE_LIMIT_7_8 0xC420 // 2: +7 fres to -8 fres
+#define RFM_AFC_RANGE_LIMIT_3_4 0xC430 // 3: +3 fres to -4 fres
+
+// fres=2.5 kHz in 315MHz and 433MHz Bands
+// fres=5.0 kHz in 868MHz Band
+// fres=7.5 kHz in 915MHz Band
+
+#define RFM_AFC_AUTO_OFF 0xC400 // 0: Auto mode off (Strobe is controlled by microcontroller)
+#define RFM_AFC_AUTO_ONCE 0xC440 // 1: Runs only once after each power-up
+#define RFM_AFC_AUTO_VDI 0xC480 // 2: Keep the foffset only during receiving(VDI=high)
+#define RFM_AFC_AUTO_INDEPENDENT 0xC4C0 // 3: Keep the foffset value independently trom the state of the VDI signal
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 10. TX Configuration Control Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_TX_CONTROL 0x9800
+
+#define RFM_TX_CONTROL_POW_0 0x9800
+#define RFM_TX_CONTROL_POW_3 0x9801
+#define RFM_TX_CONTROL_POW_6 0x9802
+#define RFM_TX_CONTROL_POW_9 0x9803
+#define RFM_TX_CONTROL_POW_12 0x9804
+#define RFM_TX_CONTROL_POW_15 0x9805
+#define RFM_TX_CONTROL_POW_18 0x9806
+#define RFM_TX_CONTROL_POW_21 0x9807
+#define RFM_TX_CONTROL_MOD_15 0x9800
+#define RFM_TX_CONTROL_MOD_30 0x9810
+#define RFM_TX_CONTROL_MOD_45 0x9820
+#define RFM_TX_CONTROL_MOD_60 0x9830
+#define RFM_TX_CONTROL_MOD_75 0x9840
+#define RFM_TX_CONTROL_MOD_90 0x9850
+#define RFM_TX_CONTROL_MOD_105 0x9860
+#define RFM_TX_CONTROL_MOD_120 0x9870
+#define RFM_TX_CONTROL_MOD_135 0x9880
+#define RFM_TX_CONTROL_MOD_150 0x9890
+#define RFM_TX_CONTROL_MOD_165 0x98A0
+#define RFM_TX_CONTROL_MOD_180 0x98B0
+#define RFM_TX_CONTROL_MOD_195 0x98C0
+#define RFM_TX_CONTROL_MOD_210 0x98D0
+#define RFM_TX_CONTROL_MOD_225 0x98E0
+#define RFM_TX_CONTROL_MOD_240 0x98F0
+#define RFM_TX_CONTROL_MP 0x9900
+
+#define RFM_TX_CONTROL_MOD(baud) (((baud)<8000) ? \
+ RFM_TX_CONTROL_MOD_45 : \
+ ( \
+ ((baud)<20000) ? \
+ RFM_TX_CONTROL_MOD_60 : \
+ ( \
+ ((baud)<30000) ? \
+ RFM_TX_CONTROL_MOD_75 : \
+ ( \
+ ((baud)<40000) ? \
+ RFM_TX_CONTROL_MOD_90 : \
+ RFM_TX_CONTROL_MOD_120 \
+ ) \
+ ) \
+ ))
+
+/////////////////////////////////////////////////////////////////////////////
+//
+// 11. Transmitter Register Write Command
+//
+/////////////////////////////////////////////////////////////////////////////
+
+//#define RFM_WRITE(byte) RFM_SPI_16(0xB800 | ((byte) & 0xFF))
+#define RFM_WRITE(byte) RFM_SPI_16(0xB800 | (byte) )
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 12. Wake-up Timer Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_WAKEUP_TIMER 0xE000
+#define RFM_WAKEUP_SET(time) RFM_SPI_16(RFM_WAKEUP_TIMER | (time))
+
+#define RFM_WAKEUP_480s (RFM_WAKEUP_TIMER |(11 << 8)| 234)
+#define RFM_WAKEUP_240s (RFM_WAKEUP_TIMER |(10 << 8)| 234)
+#define RFM_WAKEUP_120s (RFM_WAKEUP_TIMER |(9 << 8)| 234)
+#define RFM_WAKEUP_119s (RFM_WAKEUP_TIMER |(9 << 8)| 232)
+
+#define RFM_WAKEUP_60s (RFM_WAKEUP_TIMER |(8 << 8) | 235)
+#define RFM_WAKEUP_59s (RFM_WAKEUP_TIMER |(8 << 8) | 230)
+
+#define RFM_WAKEUP_30s (RFM_WAKEUP_TIMER |(7 << 8) | 235)
+#define RFM_WAKEUP_29s (RFM_WAKEUP_TIMER |(7 << 8) | 227)
+
+#define RFM_WAKEUP_8s (RFM_WAKEUP_TIMER |(5 << 8) | 250)
+#define RFM_WAKEUP_7s (RFM_WAKEUP_TIMER |(5 << 8) | 219)
+#define RFM_WAKEUP_6s (RFM_WAKEUP_TIMER |(6 << 8) | 94)
+#define RFM_WAKEUP_5s (RFM_WAKEUP_TIMER |(5 << 8) | 156)
+#define RFM_WAKEUP_4s (RFM_WAKEUP_TIMER |(5 << 8) | 125)
+#define RFM_WAKEUP_1s (RFM_WAKEUP_TIMER |(2 << 8) | 250)
+#define RFM_WAKEUP_900ms (RFM_WAKEUP_TIMER |(2 << 8) | 225)
+#define RFM_WAKEUP_800ms (RFM_WAKEUP_TIMER |(2 << 8) | 200)
+#define RFM_WAKEUP_700ms (RFM_WAKEUP_TIMER |(2 << 8) | 175)
+#define RFM_WAKEUP_600ms (RFM_WAKEUP_TIMER |(2 << 8) | 150)
+#define RFM_WAKEUP_500ms (RFM_WAKEUP_TIMER |(2 << 8) | 125)
+#define RFM_WAKEUP_400ms (RFM_WAKEUP_TIMER |(2 << 8) | 100)
+#define RFM_WAKEUP_300ms (RFM_WAKEUP_TIMER |(2 << 8) | 75)
+#define RFM_WAKEUP_200ms (RFM_WAKEUP_TIMER |(2 << 8) | 50)
+#define RFM_WAKEUP_100ms (RFM_WAKEUP_TIMER |(2 << 8) | 25)
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 13. Low Duty-Cycle Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_LOW_DUTY_CYCLE 0xC800
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 14. Low Battery Detector Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_LOW_BATT_DETECT 0xC000
+#define RFM_LOW_BATT_DETECT_D_1MHZ 0xC000
+#define RFM_LOW_BATT_DETECT_D_1_25MHZ 0xC020
+#define RFM_LOW_BATT_DETECT_D_1_66MHZ 0xC040
+#define RFM_LOW_BATT_DETECT_D_2MHZ 0xC060
+#define RFM_LOW_BATT_DETECT_D_2_5MHZ 0xC080
+#define RFM_LOW_BATT_DETECT_D_3_33MHZ 0xC0A0
+#define RFM_LOW_BATT_DETECT_D_5MHZ 0xC0C0
+#define RFM_LOW_BATT_DETECT_D_10MHZ 0xC0E0
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// 15. Status Read Command
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define RFM_READ_STATUS() RFM_SPI_16(0x0000)
+#define RFM_READ_STATUS_FFIT() SPI_1 (0x00)
+#define RFM_READ_STATUS_RGIT RFM_READ_STATUS_FFIT
+
+///////////////////////////////////////////////////////////////////////////////
+
+// RFM air protocol flags:
+
+#define RFMPROTO_FLAGS_BITASK_PACKETTYPE 0b11000000 //!< the uppermost 2 bits of the flags field encode the packettype
+#define RFMPROTO_FLAGS_PACKETTYPE_BROADCAST 0b00000000 //!< broadcast packettype (message from hr20, protocol; step 1)
+#define RFMPROTO_FLAGS_PACKETTYPE_COMMAND 0b01000000 //!< command packettype (message to hr20, protocol; step 2)
+#define RFMPROTO_FLAGS_PACKETTYPE_REPLY 0b10000000 //!< reply packettype (message from hr20, protocol; step 3)
+#define RFMPROTO_FLAGS_PACKETTYPE_SPECIAL 0b11000000 //!< currently unused packettype
+
+#define RFMPROTO_FLAGS_BITASK_DEVICETYPE 0b00011111 //!< the lowermost 5 bytes denote the device type. this way other sensors and actors may coexist
+#define RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 0b00010100 //!< topen HR20 device type. 10100 is for decimal 20
+
+#define RFMPROTO_IS_PACKETTYPE_BROADCAST(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_BROADCAST == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
+#define RFMPROTO_IS_PACKETTYPE_COMMAND(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_COMMAND == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
+#define RFMPROTO_IS_PACKETTYPE_REPLY(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_REPLY == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
+#define RFMPROTO_IS_PACKETTYPE_SPECIAL(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_SPECIAL == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
+#define RFMPROTO_IS_DEVICETYPE_OPENHR20(FLAGS) ( RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 == ((FLAGS) & RFMPROTO_FLAGS_BITASK_DEVICETYPE) )
+
+///////////////////////////////////////////////////////////////////////////////
+
+#endif
\ No newline at end of file
Sukkin Pang