gabriel della-monica
mbed library sources
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mbed official
Revision 423:560d1a9f3083, committed 2014-12-02
- Comitter:
- mbed_official
- Date:
- Tue Dec 02 15:45:09 2014 +0000
- Parent:
- 422:a032ac66f24e
- Child:
- 424:73631a54077f
- Commit message:
- Synchronized with git revision a88eaace6bafba6477cf071369e01c87ccf541b6
Full URL: https://github.com/mbedmicro/mbed/commit/a88eaace6bafba6477cf071369e01c87ccf541b6/
Targets: DISCO_F051R8 - Updated driver files with HAL driver.
Changed in this revision
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/STM32F0xx.ld Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,156 +0,0 @@
-/* Linker script for STM32F */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64k
- RAM (rwx) : ORIGIN = 0x200000C0, LENGTH = 0x2000-0xC0
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
- _sidata = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- _sdata = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- KEEP(*(.jcr*))
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
- _edata = .;
-
- } > RAM
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start__ = .;
- _sbss = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- __bss_end__ = .;
- _ebss = .;
- } > RAM
-
- .heap (COPY):
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- _estack = __StackTop;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
-
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/startup_stm32f0xx.s Tue Dec 02 15:15:06 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,294 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f0xx.s - * @author MCD Application Team - * @version V1.0.0 - * @date 23-March-2012 - * @brief STM32F0xx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 -/* str r3, [r2], #4 */ - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl _start - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/******************************************************************************* -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_1_IRQHandler - .word EXTI2_3_IRQHandler - .word EXTI4_15_IRQHandler - .word TS_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_3_IRQHandler - .word DMA1_Channel4_5_IRQHandler - .word ADC1_COMP_IRQHandler - .word TIM1_BRK_UP_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM6_DAC_IRQHandler - .word 0 - .word TIM14_IRQHandler - .word TIM15_IRQHandler - .word TIM16_IRQHandler - .word TIM17_IRQHandler - .word I2C1_IRQHandler - .word I2C2_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word 0 - .word CEC_IRQHandler - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F0xx devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak TS_IRQHandler - .thumb_set TS_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_COMP_IRQHandler - .thumb_set ADC1_COMP_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM15_IRQHandler - .thumb_set TIM15_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak I2C2_IRQHandler - .thumb_set I2C2_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/cmsis.h Tue Dec 02 15:15:06 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * A generic CMSIS include header - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "stm32f0xx.h" -#include "cmsis_nvic.h" - -#endif
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/cmsis_nvic.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,61 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
-
-static unsigned char vtor_remap = 0; // To keep track that the vectors remap is done
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
- int i;
- // Space for dynamic vectors, initialised to allocate in R/W
- static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
-
- // Copy and switch to dynamic vectors if first time called
- if (vtor_remap == 0) {
- uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
- for (i = 0; i < NVIC_NUM_VECTORS; i++) {
- vectors[i] = old_vectors[i];
- }
- SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
- vtor_remap = 1; // The vectors remap is done
- }
-
- // Set the vector
- vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
- uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
- // Return the vector
- return vectors[IRQn + 16];
-}
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/cmsis_nvic.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// STM32F030R8
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 29 vectors = 116 bytes from 0x40 to 0xB3
-// Total: 45 vectors = 180 bytes (0xB4) to be reserved in RAM (see scatter file)
-#define NVIC_NUM_VECTORS 45
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,5121 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx.h
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F0xx devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripheralâs drivers in application code(i.e.
- * code will be based on direct access to peripheralâs registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheralâs registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx
- * @{
- */
-
-#ifndef __STM32F0XX_H
-#define __STM32F0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32F0 device used in your
- application
- */
-
-#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
- /* #define STM32F030 */
- /* #define STM32F031 */
- #define STM32F051
- /* #define STM32F072 */
- /* #define STM32F042 */
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-/* Old STM32F0XX definition, maintained for legacy purpose */
-#if defined(STM32F0XX) || defined(STM32F0XX_MD)
- #define STM32F051
-#endif /* STM32F0XX */
-
-/* Old STM32F0XX_LD definition, maintained for legacy purpose */
-#ifdef STM32F0XX_LD
- #define STM32F031
-#endif /* STM32F0XX_LD */
-
-/* Old STM32F0XX_HD definition, maintained for legacy purpose */
-#ifdef STM32F0XX_HD
- #define STM32F072
-#endif /* STM32F0XX_HD */
-
-/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
-#if defined (STM32F030X8) || defined (STM32F030X6)
- #define STM32F030
-#endif /* STM32F030X8 or STM32F030X6 */
-
-
-#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
- #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
-#endif
-
-#if !defined USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
-#define USE_STDPERIPH_DRIVER
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
-#endif /* HSE_VALUE */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#if !defined (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- Timeout value
- */
-#if !defined (HSI_STARTUP_TIMEOUT)
-#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
-
-#if !defined (HSI_VALUE)
-#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI14_VALUE)
-#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* HSI14_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* HSI48_VALUE */
-
-#if !defined (LSI_VALUE)
-#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* LSI_VALUE */
-
-#if !defined (LSE_VALUE)
-#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
- * @brief STM32F0xx Standard Peripheral Library version number V1.3.1
- */
-#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
-#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
- |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
- |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
- |(__STM32F0XX_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief STM32F0xx Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-#define __CM0_REV 0 /*!< Core Revision r0p0 */
-#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
-#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-/*!< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
-
-#if defined (STM32F051)
-/****** STM32F051 specific Interrupt Numbers *************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_IRQn = 4, /*!< RCC Interrupt */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- TS_IRQn = 8, /*!< Touch sense controller Interrupt */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
- ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 15, /*!< TIM2 Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM15_IRQn = 20, /*!< TIM15 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- I2C2_IRQn = 24, /*!< I2C2 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- SPI2_IRQn = 26, /*!< SPI2 Interrupt */
- USART1_IRQn = 27, /*!< USART1 Interrupt */
- USART2_IRQn = 28, /*!< USART2 Interrupt */
- CEC_IRQn = 30 /*!< CEC Interrupt */
-#elif defined (STM32F031)
-/****** STM32F031 specific Interrupt Numbers *************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_IRQn = 4, /*!< RCC Interrupt */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
- ADC1_IRQn = 12, /*!< ADC1 Interrupt */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 15, /*!< TIM2 Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- USART1_IRQn = 27 /*!< USART1 Interrupt */
-#elif defined (STM32F030)
-/****** STM32F030 specific Interrupt Numbers *************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_IRQn = 4, /*!< RCC Interrupt */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
- ADC1_IRQn = 12, /*!< ADC1 Interrupt */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM15_IRQn = 20, /*!< TIM15 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- I2C2_IRQn = 24, /*!< I2C2 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- SPI2_IRQn = 26, /*!< SPI2 Interrupt */
- USART1_IRQn = 27, /*!< USART1 Interrupt */
- USART2_IRQn = 28 /*!< USART2 Interrupt */
-#elif defined (STM32F072)
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- TSC_IRQn = 8, /*!< TSC Interrupt */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
- ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 15, /*!< TIM2 Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
- TIM7_IRQn = 18, /*!< TIM7 Interrupts */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM15_IRQn = 20, /*!< TIM15 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- I2C2_IRQn = 24, /*!< I2C2 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- SPI2_IRQn = 26, /*!< SPI2 Interrupt */
- USART1_IRQn = 27, /*!< USART1 Interrupt */
- USART2_IRQn = 28, /*!< USART2 Interrupt */
- USART3_4_IRQn = 29, /*!< USART3 and USART4 Interrupts */
- CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */
- USB_IRQn = 31 /*!< USB Low Priority global Interrupt */
-#elif defined (STM32F042)
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- TSC_IRQn = 8, /*!< TSC Interrupt */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */
- ADC1_IRQn = 12, /*!< ADC1 Interrupts */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 15, /*!< TIM2 Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- SPI2_IRQn = 26, /*!< SPI2 Interrupt */
- USART1_IRQn = 27, /*!< USART1 Interrupt */
- USART2_IRQn = 28, /*!< USART2 Interrupt */
- CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */
- USB_IRQn = 31 /*!< USB Low Priority global Interrupt */
-#endif /* STM32F051 */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm0.h"
-#include "system_stm32f0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Exported_types
- * @{
- */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
- __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
- __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
- __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
- __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
- __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
- uint32_t RESERVED3; /*!< Reserved, 0x24 */
- __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
- uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
- __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-typedef struct
-{
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-typedef struct
-{
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-typedef struct
-{
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-typedef struct
-{
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2; /*!< Reserved, 0x208 */
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3; /*!< Reserved, 0x210 */
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
- uint32_t RESERVED4; /*!< Reserved, 0x218 */
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
-} CAN_TypeDef;
-
-/**
- * @brief HDMI-CEC
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
- * @brief Comparator
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */
-} COMP_TypeDef;
-
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
- * @brief Clock Recovery System
- */
-typedef struct
-{
-__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
-__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
-__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
-__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
-} CRS_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
-} DAC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA channel x configuration register */
- __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
- __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
- __IO uint32_t CMAR; /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
-} DMA_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
- __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-typedef struct
-{
- __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
- __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
- __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
- __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
- __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
- __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
- __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/**
- * @brief Option Bytes Registers
- */
-typedef struct
-{
- __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
- __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
- __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
- __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
- __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
- __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
- __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
- __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
-} OB_TypeDef;
-
-
-/**
- * @brief General Purpose IO
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- uint16_t RESERVED0; /*!< Reserved, 0x06 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- uint16_t RESERVED1; /*!< Reserved, 0x12 */
- __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- uint16_t RESERVED2; /*!< Reserved, 0x16 */
- __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
- __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
- uint16_t RESERVED3; /*!< Reserved, 0x2A */
-}GPIO_TypeDef;
-
-/**
- * @brief SysTem Configuration
- */
-
-typedef struct
-{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
- uint32_t RESERVED; /*!< Reserved, 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/**
- * @brief Independent WATCHDOG
- */
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
- __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-
-/**
- * @brief Reset and Clock Control
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
- __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
- __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
- __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
- __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
- __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register,(only for STM32F072 devices) Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
- uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
- uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
-} RTC_TypeDef;
-
-/* Old register name definition maintained for legacy purpose */
-#define CAL CALR
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} SPI_TypeDef;
-
-
-/**
- * @brief TIM
- */
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
- uint16_t RESERVED10; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED12; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- uint16_t RESERVED17; /*!< Reserved, 0x26 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED18; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
- uint16_t RESERVED19; /*!< Reserved, 0x4E */
- __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
- uint16_t RESERVED20; /*!< Reserved, 0x52 */
-} TIM_TypeDef;
-
-/**
- * @brief Touch Sensing Controller (TSC)
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
- __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
- __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
- __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
- __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
- __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
- __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
- __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
- __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
- __IO uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
- __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
- __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
- __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
- uint16_t RESERVED1; /*!< Reserved, 0x0E */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
- uint16_t RESERVED2; /*!< Reserved, 0x12 */
- __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
- __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
- uint16_t RESERVED3; /*!< Reserved, 0x1A */
- __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
- __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
- __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
- uint16_t RESERVED4; /*!< Reserved, 0x26 */
- __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
- uint16_t RESERVED5; /*!< Reserved, 0x2A */
-} USART_TypeDef;
-
-
-/**
- * @brief Window WATCHDOG
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE PERIPH_BASE
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
-
-#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
-#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
-#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
-#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
-#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
-#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
-#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
-#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
-#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
-#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
-#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
-#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
-#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
-#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
-#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
-#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
-#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
-#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
-#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
-
-#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
-#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
-#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
-#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
-#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
-#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
-#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
-#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
-#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
-#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
-#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
-#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
-
-#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
-#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
-#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
-#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
-
-#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
-#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
-#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
-
-#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
-#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
-#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
-#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
-#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
-#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define USART4 ((USART_TypeDef *) USART4_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define CAN ((CAN_TypeDef *) CAN_BASE)
-#define CRS ((CRS_TypeDef *) CRS_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define TSC ((TSC_TypeDef *) TSC_BASE)
-
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers Bits Definition */
-/******************************************************************************/
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter (ADC) */
-/* */
-/******************************************************************************/
-/******************** Bits definition for ADC_ISR register ******************/
-#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
-#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
-#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
-#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
-#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
-#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS ADC_ISR_EOSEQ
-
-/******************** Bits definition for ADC_IER register ******************/
-#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE ADC_IER_EOSEQIE
-
-/******************** Bits definition for ADC_CR register *******************/
-#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
-#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
-#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
-#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
-
-/******************* Bits definition for ADC_CFGR1 register *****************/
-#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
-#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
-#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
-
-/******************* Bits definition for ADC_CFGR2 register *****************/
-#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
-#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
-#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
-
-/* Old bit definition, maintained for legacy purpose */
-#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
-#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
-
-/****************** Bit definition for ADC_SMPR register ********************/
-#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-/* Old bit definition, maintained for legacy purpose */
-#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
-#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
-#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
-#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
-
-/******************* Bit definition for ADC_TR register ********************/
-#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
-#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
-
-/* Old bit definition, maintained for legacy purpose */
-#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
-#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
-
-/****************** Bit definition for ADC_CHSELR register ******************/
-#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
-
-/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
-#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
-#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
-
-/******************************************************************************/
-/* */
-/* Controller Area Network (CAN ) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for CAN_MCR register ********************/
-#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
-#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
-#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
-#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
-#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
-#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
-#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
-#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
-#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
-
-/******************* Bit definition for CAN_MSR register ********************/
-#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
-#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
-#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
-#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
-#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
-#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
-#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
-#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
-
-/******************* Bit definition for CAN_TSR register ********************/
-#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
-
-#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
-#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
-#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
-
-/******************* Bit definition for CAN_RF0R register *******************/
-#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
-#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
-
-/******************* Bit definition for CAN_RF1R register *******************/
-#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
-#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
-
-/******************** Bit definition for CAN_IER register *******************/
-#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
-#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
-
-/******************** Bit definition for CAN_ESR register *******************/
-#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
-#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
-#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
-
-#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
-
-/******************* Bit definition for CAN_BTR register ********************/
-#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
-#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
-#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
-#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
-#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
-#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
-
-/*!<Mailbox registers */
-/****************** Bit definition for CAN_TI0R register ********************/
-#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/****************** Bit definition for CAN_TDT0R register *******************/
-#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/****************** Bit definition for CAN_TDL0R register *******************/
-#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/****************** Bit definition for CAN_TDH0R register *******************/
-#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_TI1R register *******************/
-#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT1R register ******************/
-#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL1R register ******************/
-#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_TDH1R register ******************/
-#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_TI2R register *******************/
-#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
-#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT2R register ******************/
-#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL2R register ******************/
-#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_TDH2R register ******************/
-#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_RI0R register *******************/
-#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT0R register ******************/
-#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
-#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL0R register ******************/
-#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_RDH0R register ******************/
-#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_RI1R register *******************/
-#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
-#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT1R register ******************/
-#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
-#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL1R register ******************/
-#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_RDH1R register ******************/
-#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/******************* Bit definition for CAN_FMR register ********************/
-#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
-
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
-#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
-
-/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
-
-/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
-
-/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
-
-/******************* Bit definition for CAN_F0R1 register *******************/
-#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R1 register *******************/
-#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R1 register *******************/
-#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R1 register *******************/
-#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R1 register *******************/
-#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R1 register *******************/
-#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R1 register *******************/
-#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R1 register *******************/
-#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R1 register *******************/
-#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R1 register *******************/
-#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R1 register ******************/
-#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R1 register ******************/
-#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R1 register ******************/
-#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R1 register ******************/
-#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F0R2 register *******************/
-#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R2 register *******************/
-#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R2 register *******************/
-#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R2 register *******************/
-#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R2 register *******************/
-#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R2 register *******************/
-#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R2 register *******************/
-#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R2 register *******************/
-#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R2 register *******************/
-#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R2 register *******************/
-#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R2 register ******************/
-#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R2 register ******************/
-#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R2 register ******************/
-#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R2 register ******************/
-#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-
-/******************************************************************************/
-/* */
-/* HDMI-CEC (CEC) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for CEC_CR register *********************/
-#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
-#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
-#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
-
-/******************* Bit definition for CEC_CFGR register *******************/
-#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
-#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
-#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
-#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
-#define CEC_CFGR_LREGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
-#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
-#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
-#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
-#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
-
-/******************* Bit definition for CEC_TXDR register *******************/
-#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
-
-/******************* Bit definition for CEC_RXDR register *******************/
-#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
-
-/******************* Bit definition for CEC_ISR register ********************/
-#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
-#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
-#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
-#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
-#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
-#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
-#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
-#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
-#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
-#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
-#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
-#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
-#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
-
-/******************* Bit definition for CEC_IER register ********************/
-#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
-#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
-#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
-#define CEC_IER_BREIEIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
-#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
-#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
-#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
-#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
-#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
-#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
-#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
-#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
-#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
-
-/******************************************************************************/
-/* */
-/* Analog Comparators (COMP) */
-/* */
-/******************************************************************************/
-/*********************** Bit definition for COMP_CSR register ***************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
-#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
-#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
-#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
-#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
-#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
-#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
-#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
-#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
-#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
-#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
-#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
-#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
-#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
-#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
-#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
-#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
-#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
-#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
-#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
-#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
-#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
-#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
-
-/******************************************************************************/
-/* */
-/* CRC calculation unit (CRC) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits (only for STM32F072 devices)*/
-#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for STM32F072 devices) */
-#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for STM32F072 devices) */
-#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
-#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
-#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
-
-/******************* Bit definition for CRC_INIT register *******************/
-#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
-/******************* Bit definition for CRC_POL register ********************/
-#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for STM32F072 devices) */
-
-/******************************************************************************/
-/* */
-/* CRS Clock Recovery System */
-/* (Available only for STM32F072 devices) */
-/******************************************************************************/
-
-/******************* Bit definition for CRS_CR register *********************/
-#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
-#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
-#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
-#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
-#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
-#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
-#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
-
-/******************* Bit definition for CRS_CFGR register *********************/
-#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
-#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
-#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
-#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
-#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
-#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
-#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
-#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
-#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
-
-/******************* Bit definition for CRS_ISR register *********************/
-#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
-#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
-#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
-#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
-#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
-#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
-#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
-#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
-
-/******************* Bit definition for CRS_ICR register *********************/
-#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
-#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
-#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
-#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
-
-/******************************************************************************/
-/* */
-/* Digital to Analog Converter (DAC) */
-/* */
-/******************************************************************************/
-/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)(only for STM32F072 devices) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) (only for STM32F072 devices) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Underrun Interrupt enable */
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
-
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA Underrun Interrupt enable */
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */
-
-/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
-
-/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */
-
-/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag (only for STM32F072 and STM32F042 devices) */
-
-/******************************************************************************/
-/* */
-/* Debug MCU (DBGMCU) */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
-
-/****************** Bit definition for DBGMCU_APB1_FZ register **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted (only for STM32F072 devices) */
-#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted (only for STM32F072 devices) */
-
-/****************** Bit definition for DBGMCU_APB2_FZ register **************/
-#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
-#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
-
-/******************************************************************************/
-/* */
-/* DMA Controller (DMA) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag (only for STM32F072 devices) */
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag (only for STM32F072 devices) */
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag (only for STM32F072 devices) */
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag (only for STM32F072 devices) */
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag (only for STM32F072 devices) */
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag (only for STM32F072 devices) */
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag (only for STM32F072 devices) */
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag (only for STM32F072 devices) */
-
-/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear (only for STM32F072 devices) */
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear (only for STM32F072 devices) */
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear (only for STM32F072 devices) */
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear (only for STM32F072 devices) */
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear (only for STM32F072 devices) */
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear (only for STM32F072 devices) */
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear (only for STM32F072 devices) */
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear (only for STM32F072 devices) */
-
-/******************* Bit definition for DMA_CCR register ********************/
-#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
-#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
-#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
-#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
-#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-
-#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-
-#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
-
-/****************** Bit definition for DMA_CNDTR register *******************/
-#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CPAR register ********************/
-#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CMAR register ********************/
-#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller (EXTI) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
-#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
-#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
-#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-
-/****************** Bit definition for EXTI_EMR register ********************/
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
-#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
-#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
-#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
-#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
-#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
-#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
-#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
-#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-
-/******************* Bit definition for EXTI_RTSR register ******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-
-/******************* Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-
-/****************** Bit definition for EXTI_PR register *********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
-
-/******************************************************************************/
-/* */
-/* FLASH and Option Bytes Registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
-
-#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
-
-/****************** Bit definition for FLASH_KEYR register ******************/
-#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
-
-/***************** Bit definition for FLASH_OPTKEYR register ****************/
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
-
-/****************** FLASH Keys **********************************************/
-#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
-#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
- to unlock the write access to the FPEC. */
-
-#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
-#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
- unlock the write access to the option byte block */
-
-/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
-#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
-#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
-#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
-#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
-
-/******************* Bit definition for FLASH_CR register *******************/
-#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
-#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
-#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
-#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
-#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
-#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
-#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
-#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
-#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
-#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
-#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
-
-/******************* Bit definition for FLASH_AR register *******************/
-#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
-
-/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
-#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level bit 1 */
-#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level bit 2 */
-
-#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
-#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
-#define FLASH_OBR_nBOOT0 ((uint32_t)0x00000800) /*!< nBOOT0 */
-#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
-#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
-#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM Parity Check */
-#define FLASH_OBR_nBOOT0_SW ((uint32_t)0x00008000) /*!< nBOOT0 SW (available only in the STM32F042 devices)*/
-#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< DATA0 */
-#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< DATA0 */
-
-/* Old BOOT1 bit definition, maintained for legacy purpose */
-#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
-
-/* Old OBR_VDDA bit definition, maintained for legacy purpose */
-#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
-
-/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/****************** Bit definition for OB_RDP register **********************/
-#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
-#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
-
-/****************** Bit definition for OB_USER register *********************/
-#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
-#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
-
-/****************** Bit definition for OB_WRP0 register *********************/
-#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
-#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for OB_WRP1 register *********************/
-#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
-#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for OB_WRP2 register *********************/
-#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
-#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
-
-/****************** Bit definition for OB_WRP3 register *********************/
-#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
-#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
-
-/******************************************************************************/
-/* */
-/* General Purpose IOs (GPIO) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for GPIO_MODER register *****************/
-#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
-#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
-#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
-#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
-#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
-#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
-#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
-#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
-#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
-#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
-#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
-#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
-#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
-#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
-#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
-#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_OTYPER register *****************/
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
-
-/**************** Bit definition for GPIO_OSPEEDR register ******************/
-#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
-#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
-#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
-#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
-#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
-#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
-#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
-#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
-#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
-#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
-#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
-#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
-#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
-#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
-#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
-#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
-#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
-#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
-#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
-#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
-#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
-#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
-#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
-#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
-#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
-#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
-#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
-#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
-#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
-#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
-#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
-#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
-#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
-#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
-#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
-#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
-#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
-#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
-#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
-#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
-
-/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
-#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
-#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
-#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
-#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
-#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
-#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
-#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
-#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
-#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
-#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
-#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
-#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
-#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
-#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
-#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
-#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
-#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
-#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
-#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
-#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
-#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
-#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
-#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
-#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
-#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
-#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
-#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
-#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
-#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
-#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
-#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
-#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
-#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
-#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
-#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
-#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
-#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
-#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
-#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
-#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
-#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
-#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
-#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
-#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
-#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
-#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
-#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
-#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
-
-/******************* Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
-
-/******************* Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_0 ((uint32_t)0x00000001)
-#define GPIO_IDR_1 ((uint32_t)0x00000002)
-#define GPIO_IDR_2 ((uint32_t)0x00000004)
-#define GPIO_IDR_3 ((uint32_t)0x00000008)
-#define GPIO_IDR_4 ((uint32_t)0x00000010)
-#define GPIO_IDR_5 ((uint32_t)0x00000020)
-#define GPIO_IDR_6 ((uint32_t)0x00000040)
-#define GPIO_IDR_7 ((uint32_t)0x00000080)
-#define GPIO_IDR_8 ((uint32_t)0x00000100)
-#define GPIO_IDR_9 ((uint32_t)0x00000200)
-#define GPIO_IDR_10 ((uint32_t)0x00000400)
-#define GPIO_IDR_11 ((uint32_t)0x00000800)
-#define GPIO_IDR_12 ((uint32_t)0x00001000)
-#define GPIO_IDR_13 ((uint32_t)0x00002000)
-#define GPIO_IDR_14 ((uint32_t)0x00004000)
-#define GPIO_IDR_15 ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_ODR register ********************/
-#define GPIO_ODR_0 ((uint32_t)0x00000001)
-#define GPIO_ODR_1 ((uint32_t)0x00000002)
-#define GPIO_ODR_2 ((uint32_t)0x00000004)
-#define GPIO_ODR_3 ((uint32_t)0x00000008)
-#define GPIO_ODR_4 ((uint32_t)0x00000010)
-#define GPIO_ODR_5 ((uint32_t)0x00000020)
-#define GPIO_ODR_6 ((uint32_t)0x00000040)
-#define GPIO_ODR_7 ((uint32_t)0x00000080)
-#define GPIO_ODR_8 ((uint32_t)0x00000100)
-#define GPIO_ODR_9 ((uint32_t)0x00000200)
-#define GPIO_ODR_10 ((uint32_t)0x00000400)
-#define GPIO_ODR_11 ((uint32_t)0x00000800)
-#define GPIO_ODR_12 ((uint32_t)0x00001000)
-#define GPIO_ODR_13 ((uint32_t)0x00002000)
-#define GPIO_ODR_14 ((uint32_t)0x00004000)
-#define GPIO_ODR_15 ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_BSRR register ********************/
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register ********************/
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFR0 ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFR1 ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFR2 ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFR3 ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFR4 ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFR5 ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFR6 ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFR7 ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFR8 ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFR9 ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFR10 ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFR11 ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFR12 ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFR13 ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFR14 ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFR15 ((uint32_t)0xF0000000)
-
-/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
-#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFR0
-#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFR1
-#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFR2
-#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFR3
-#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFR4
-#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFR5
-#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFR6
-#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFR7
-
-/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
-#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFR8
-#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFR9
-#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFR10
-#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFR11
-#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFR12
-#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFR13
-#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFR14
-#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFR15
-
-/****************** Bit definition for GPIO_BRR register *********************/
-#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface (I2C) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for I2C_CR1 register *******************/
-#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
-#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
-#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
-#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
-#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
-#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
-#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
-#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
-
-/****************** Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
-#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
-#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
-
-/******************* Bit definition for I2C_OAR1 register ******************/
-#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
-
-/******************* Bit definition for I2C_OAR2 register ******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
-
-/******************* Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
-#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
-
-/****************** Bit definition for I2C_ISR register *********************/
-#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
-#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
-#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
-#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
-#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
-#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
-#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
-#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
-#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
-#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
-
-/****************** Bit definition for I2C_ICR register *********************/
-#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
-#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
-
-/****************** Bit definition for I2C_PECR register *********************/
-#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
-
-/****************** Bit definition for I2C_RXDR register *********************/
-#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
-
-/****************** Bit definition for I2C_TXDR register *********************/
-#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG (IWDG) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */
-
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/* */
-/* Power Control (PWR) */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep */
-#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
-/* PVD level configuration */
-#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
-
-#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
-
-/* Old Bit definition maintained for legacy purpose ****/
-#define PWR_CR_LPSDSR PWR_CR_LPDS /*!< Low-power deepsleep */
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
-#define PWR_CSR_VREFINTRDY ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready */
-
-#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
-#define PWR_CSR_EWUP4 ((uint16_t)0x0800) /*!< Enable WKUP pin 4 */
-#define PWR_CSR_EWUP5 ((uint16_t)0x1000) /*!< Enable WKUP pin 5 */
-#define PWR_CSR_EWUP6 ((uint16_t)0x2000) /*!< Enable WKUP pin 6 */
-#define PWR_CSR_EWUP7 ((uint16_t)0x4000) /*!< Enable WKUP pin 7 */
-#define PWR_CSR_EWUP8 ((uint16_t)0x8000) /*!< Enable WKUP pin 8 */
-
-/* Old Bit definition maintained for legacy purpose ****/
-#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDY /*!< Internal voltage reference (VREFINT) ready flag */
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
-#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
-
-/******************* Bit definition for RCC_CFGR register *******************/
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-/* SW configuration */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
-#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
-
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-/* SWS configuration */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
-#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 used as system clock */
-
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-/* HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
-#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-/* PPRE configuration */
-#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
- done inside the ADC_CFGR2 */
-
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
-#define RCC_CFGR_PLLSRC_0 ((uint32_t)0x00008000) /*!< Bit 0 (available only in the STM32F072 devices) */
-#define RCC_CFGR_PLLSRC_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-
-#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source;
- Old PREDIV1 bit definition, maintained for legacy purpose */
-#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI PREDIV clock selected as PLL entry clock source
- (This bit and configuration is only available for STM32F072 devices)*/
-#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE PREDIV clock selected as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48 PREDIV clock selected as PLL entry clock source */
-
-#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
-#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
-
-/*!< Old bit definition maintained for legacy purposes */
-#define RCC_CFGR_PLLSRC_HSI_Div2 RCC_CFGR_PLLSRC_HSI_DIV2
-
-/* PLLMUL configuration */
-#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
-#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
-#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
-#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
-#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
-#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
-#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
-#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
-#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
-#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
-#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
-#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
-#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
-#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
-#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
-
-/* Old PLLMUL configuration bit definition maintained for legacy purposes */
-#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMUL /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMULL_0 RCC_CFGR_PLLMUL_0 /*!< Bit 0 */
-#define RCC_CFGR_PLLMULL_1 RCC_CFGR_PLLMUL_1 /*!< Bit 1 */
-#define RCC_CFGR_PLLMULL_2 RCC_CFGR_PLLMUL_2 /*!< Bit 2 */
-#define RCC_CFGR_PLLMULL_3 RCC_CFGR_PLLMUL_3 /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMULL2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
-#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
-#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
-#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
-#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
-#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
-#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
-#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
-#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMUL10 /*!< PLL input clock10 */
-#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
-#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
-#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
-#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
-#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
-#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
-
-#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-/* MCO configuration */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
-#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
-#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (these bits are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (this bit are not available in the STM32F051 devices)*/
-
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (this bit are not available in the STM32F051 devices) */
-
-/******************* Bit definition for RCC_CIR register ********************/
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
-#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
-#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
-#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
-
-/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
-#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
-#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
-#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
-#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
-#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
-
-/* Old ADC1 clock reset bit definition maintained for legacy purpose */
-#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
-
-/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
-#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
-#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
-#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
-#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
-#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
-
-/****************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */
-#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
-#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
-#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
-#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
-#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
-#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
-#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
-#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
-#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
-
-/* Old Bit definition maintained for legacy purpose */
-#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
-#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
-
-/***************** Bit definition for RCC_APB2ENR register ******************/
-#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
-#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
-#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
-#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
-#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
-#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
-#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
-
-/* Old Bit definition maintained for legacy purpose */
-#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
-
-/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
-#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
-#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
-#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
-#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
-#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
-
-/******************* Bit definition for RCC_BDCR register *******************/
-#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
-#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
-#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
-
-#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-
-#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-/* RTC configuration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
-
-#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
-#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
-
-/******************* Bit definition for RCC_CSR register ********************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
-#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
-
-/* Old Bit definition maintained for legacy purpose */
-#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
-/******************* Bit definition for RCC_AHBRSTR register ****************/
-#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
-#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
-#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
-#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD clock reset */
-#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00020000) /*!< GPIOE clock reset */
-#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF clock reset */
-#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00100000) /*!< TS clock reset */
-
-/* Old Bit definition maintained for legacy purpose */
-#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
-
-/******************* Bit definition for RCC_CFGR2 register ******************/
-/* PREDIV1 configuration */
-#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
-#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
-#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
-#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
-#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
-#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
-#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
-#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
-#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
-#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
-#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
-#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
-#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
-#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
-#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
-#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
-#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
-
-/******************* Bit definition for RCC_CFGR3 register ******************/
-#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
-#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
-#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
-#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
-#define RCC_CFGR3_ADCSW ((uint32_t)0x00000100) /*!< ADCSW bits */
-#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
-#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-/******************* Bit definition for RCC_CR2 register ********************/
-#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
-#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
-#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
-#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
-#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
-#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
-#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
-#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock (RTC) */
-/* */
-/******************************************************************************/
-/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000)
-#define RTC_TR_HT ((uint32_t)0x00300000)
-#define RTC_TR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TR_HU ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TR_MNT ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TR_MNU ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TR_ST ((uint32_t)0x00000070)
-#define RTC_TR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TR_SU ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0 ((uint32_t)0x00100000)
-#define RTC_DR_YT_1 ((uint32_t)0x00200000)
-#define RTC_DR_YT_2 ((uint32_t)0x00400000)
-#define RTC_DR_YT_3 ((uint32_t)0x00800000)
-#define RTC_DR_YU ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0 ((uint32_t)0x00010000)
-#define RTC_DR_YU_1 ((uint32_t)0x00020000)
-#define RTC_DR_YU_2 ((uint32_t)0x00040000)
-#define RTC_DR_YU_3 ((uint32_t)0x00080000)
-#define RTC_DR_WDU ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_DR_MT ((uint32_t)0x00001000)
-#define RTC_DR_MU ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0 ((uint32_t)0x00000100)
-#define RTC_DR_MU_1 ((uint32_t)0x00000200)
-#define RTC_DR_MU_2 ((uint32_t)0x00000400)
-#define RTC_DR_MU_3 ((uint32_t)0x00000800)
-#define RTC_DR_DT ((uint32_t)0x00000030)
-#define RTC_DR_DT_0 ((uint32_t)0x00000010)
-#define RTC_DR_DT_1 ((uint32_t)0x00000020)
-#define RTC_DR_DU ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0 ((uint32_t)0x00000001)
-#define RTC_DR_DU_1 ((uint32_t)0x00000002)
-#define RTC_DR_DU_2 ((uint32_t)0x00000004)
-#define RTC_DR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000)
-#define RTC_CR_OSEL ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
-#define RTC_CR_POL ((uint32_t)0x00100000)
-#define RTC_CR_COSEL ((uint32_t)0x00080000)
-#define RTC_CR_BKP ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H ((uint32_t)0x00010000)
-#define RTC_CR_TSIE ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE ((uint32_t)0x00004000)
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
-#define RTC_CR_TSE ((uint32_t)0x00000800)
-#define RTC_CR_WUTE ((uint32_t)0x00000400)
-#define RTC_CR_ALRAE ((uint32_t)0x00000100)
-#define RTC_CR_FMT ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
-
-/* Old bit definition maintained for legacy purpose */
-#define RTC_CR_BCK RTC_CR_BKP
-#define RTC_CR_CALSEL RTC_CR_COSEL
-
-/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
-#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
-#define RTC_ISR_TSF ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF ((uint32_t)0x00000400)
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
-#define RTC_ISR_INIT ((uint32_t)0x00000080)
-#define RTC_ISR_INITF ((uint32_t)0x00000040)
-#define RTC_ISR_RSF ((uint32_t)0x00000020)
-#define RTC_ISR_INITS ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
-
-/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
-
-/******************** Bits definition for RTC_WUTR register *****************/
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_WPR register ******************/
-#define RTC_WPR_KEY ((uint32_t)0x000000FF)
-
-/******************** Bits definition for RTC_SSR register ******************/
-#define RTC_SSR_SS ((uint32_t)0x0003FFFF)
-
-/******************** Bits definition for RTC_SHIFTR register ***************/
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
-
-/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000)
-#define RTC_TSTR_HT ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TSTR_HU ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TSTR_ST ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TSTR_SU ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_TSDR_MT ((uint32_t)0x00001000)
-#define RTC_TSDR_MU ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
-#define RTC_TSDR_DT ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
-#define RTC_TSDR_DU ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSSSR register ****************/
-#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
-
-/******************** Bits definition for RTC_CALR register ******************/
-#define RTC_CALR_CALP ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
-#define RTC_CALR_CALM ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
-
-/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
-#define RTC_CAL_CALP RTC_CALR_CALP
-#define RTC_CAL_CALW8 RTC_CALR_CALW8
-#define RTC_CAL_CALW16 RTC_CALR_CALW16
-#define RTC_CAL_CALM RTC_CALR_CALM
-#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
-#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
-#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
-#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
-#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
-#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
-#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
-#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
-#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
-
-/******************** Bits definition for RTC_TAFCR register ****************/
-#define RTC_TAFCR_PC15MODE ((uint32_t)0x00800000)
-#define RTC_TAFCR_PC15VALUE ((uint32_t)0x00400000)
-#define RTC_TAFCR_PC14MODE ((uint32_t)0x00200000)
-#define RTC_TAFCR_PC14VALUE ((uint32_t)0x00100000)
-#define RTC_TAFCR_PC13MODE ((uint32_t)0x00080000)
-#define RTC_TAFCR_PC13VALUE ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040)
-#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
-#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
-
-/* Old bit definition maintained for legacy purpose */
-#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
-
-/******************** Bits definition for RTC_ALRMASSR register *************/
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
-
-/******************** Bits definition for RTC_BKP0R register ****************/
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP1R register ****************/
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP2R register ****************/
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP3R register ****************/
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP4R register ****************/
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface (SPI) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
-#define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */
-#define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */
-#define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */
-#define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */
-#define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */
-#define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */
-#define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */
-#define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */
-#define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint16_t)0x0004) /*!< Channel side */
-#define SPI_SR_UDR ((uint16_t)0x0008) /*!< Underrun flag */
-#define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */
-#define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */
-#define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */
-#define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */
-#define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */
-#define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */
-#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */
-#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */
-#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
-
-/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
-#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
-
-/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/* */
-/* System Configuration (SYSCFG) */
-/* */
-/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register ****************/
-#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages (only for STM32F042 devices)*/
-#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
-#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
-#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
-#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
-#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for STM32F072) */
-#define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for STM32F072) */
-#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F030, STM32F031 and STM32F072 devices) */
-#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for STM32F072) */
-#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) */
-#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) */
-#define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for STM32F072) */
-
-/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/**
- * @brief EXTI0 configuration
- */
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
-
-/**
- * @brief EXTI1 configuration
- */
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
-
-/**
- * @brief EXTI2 configuration
- */
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
-
-/**
- * @brief EXTI3 configuration
- */
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/**
- * @brief EXTI4 configuration
- */
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
-
-/**
- * @brief EXTI5 configuration
- */
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
-
-/**
- * @brief EXTI6 configuration
- */
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
-
-/**
- * @brief EXTI7 configuration
- */
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/**
- * @brief EXTI8 configuration
- */
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
-
-/**
- * @brief EXTI9 configuration
- */
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
-
-/**
- * @brief EXTI10 configuration
- */
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
-
-/**
- * @brief EXTI11 configuration
- */
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/**
- * @brief EXTI12 configuration
- */
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
-
-/**
- * @brief EXTI13 configuration
- */
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
-
-/**
- * @brief EXTI14 configuration
- */
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
-
-/**
- * @brief EXTI15 configuration
- */
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
-
-/***************** Bit definition for SYSCFG_CFGR2 register ****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
-
-/* Old Bit definition maintained for legacy purpose */
-#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF
-/******************************************************************************/
-/* */
-/* Timers (TIM) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
-
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
-
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
-
-#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
-
-/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
-
-/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
-
-/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
-
-/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
-
-/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
-
-/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
-
-/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
-
-/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
-
-/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
-#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
-#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
-#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
-
-/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
-
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
-
-/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
-
-/******************* Bit definition for TIM_OR register *********************/
-#define TIM14_OR_TI1_RMP ((uint16_t)0x0003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
-#define TIM14_OR_TI1_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM14_OR_TI1_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
-/* */
-/******************************************************************************/
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
-#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
-#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
-#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
-#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
-#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
-#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
-#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
-#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
-#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
-#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
-#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
-#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
-#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
-#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
-#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
-#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
-#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
-#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
-#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
-#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
-#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
-#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
-#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
-#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
-#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
-
-
-/******************* Bit definition for USART_RTOR register *****************/
-#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
-
-/******************* Bit definition for USART_RQR register ******************/
-#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
-#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
-
-/******************* Bit definition for USART_ISR register ******************/
-#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
-#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
-#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
-#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
-#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
-#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
-#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
-#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
-#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
-#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
-#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
-#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
-#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
-#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
-#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
-#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
-
-/******************* Bit definition for USART_ICR register ******************/
-#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
-
-/******************* Bit definition for USART_RDR register ******************/
-#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
-
-/******************* Bit definition for USART_TDR register ******************/
-#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG (WWDG) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
-
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
-
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-#ifdef USE_STDPERIPH_DRIVER
- #include "stm32f0xx_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
- * @{
- */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_H */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_adc.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1250 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_adc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC) peripheral:
- * + Initialization and Configuration
- * + Power saving
- * + Analog Watchdog configuration
- * + Temperature Sensor, Vrefint (Internal Reference Voltage) and
- * Vbat (Voltage battery) management
- * + ADC Channels Configuration
- * + ADC Channels DMA Configuration
- * + Interrupts and flags management
- *
- * @verbatim
-================================================================================
- ##### How to use this driver #####
-================================================================================
- [..]
- (#) Enable the ADC interface clock using
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
- (++) Configure these ADC pins in analog mode using GPIO_Init();
- (#) Configure the ADC conversion resolution, data alignment, external
- trigger and edge, scan direction and Enable/Disable the continuous mode
- using the ADC_Init() function.
- (#) Activate the ADC peripheral using ADC_Cmd() function.
-
- *** ADC channels group configuration ***
- ============================================
- [..]
- (+) To configure the ADC channels features, use ADC_Init() and
- ADC_ChannelConfig() functions.
- (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()
- function.
- (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions.
- (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions.
- (+) To activate the calibration mode, use the ADC_GetCalibrationFactor() functions.
- (+) To read the ADC converted values, use the ADC_GetConversionValue()
- function.
-
- *** DMA for ADC channels features configuration ***
- =============================================================
- [..]
- (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function.
- (+) To configure the DMA transfer request, use ADC_DMARequestModeConfig() function.
-
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_adc.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ADC CFGR mask */
-#define CFGR1_CLEAR_MASK ((uint32_t)0xFFFFD203)
-
-/* Calibration time out */
-#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/** @defgroup ADC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC Prescaler
- (+) ADC Conversion Resolution (12bit..6bit)
- (+) ADC Continuous Conversion Mode (Continuous or Single conversion)
- (+) External trigger Edge and source
- (+) Converted data alignment (left or right)
- (+) The direction in which the channels will be scanned in the sequence
- (+) Enable or disable the ADC peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes ADC1 peripheral registers to their default reset values.
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @retval None
- */
-void ADC_DeInit(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- if(ADCx == ADC1)
- {
- /* Enable ADC1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
-
- /* Release ADC1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @note This function is used to configure the global features of the ADC (
- * Resolution, Data Alignment, continuous mode activation, External
- * trigger source and edge, Sequence Scan Direction).
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
- assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection));
-
- /* Get the ADCx CFGR value */
- tmpreg = ADCx->CFGR1;
-
- /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */
- tmpreg &= CFGR1_CLEAR_MASK;
-
- /*---------------------------- ADCx CFGR Configuration ---------------------*/
-
- /* Set RES[1:0] bits according to ADC_Resolution value */
- /* Set CONT bit according to ADC_ContinuousConvMode value */
- /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */
- /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
- /* Set ALIGN bit according to ADC_DataAlign value */
- /* Set SCANDIR bit according to ADC_ScanDirection value */
-
- tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
- ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
- ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);
-
- /* Write to ADCx CFGR */
- ADCx->CFGR1 = tmpreg;
-}
-
-/**
- * @brief Fills each ADC_InitStruct member with its default value.
- * @note This function is used to initialize the global features of the ADC (
- * Resolution, Data Alignment, continuous mode activation, External
- * trigger source and edge, Sequence Scan Direction).
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Reset ADC init structure parameters values */
- /* Initialize the ADC_Resolution member */
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
-
- /* Initialize the ADC_ContinuousConvMode member */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
-
- /* Initialize the ADC_ExternalTrigConvEdge member */
- ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
-
- /* Initialize the ADC_ExternalTrigConv member */
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;
-
- /* Initialize the ADC_DataAlign member */
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
-
- /* Initialize the ADC_ScanDirection member */
- ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward;
-}
-
-/**
- * @brief Enables or disables the specified ADC peripheral.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the ADCx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ADEN bit to Enable the ADC peripheral */
- ADCx->CR |= (uint32_t)ADC_CR_ADEN;
- }
- else
- {
- /* Set the ADDIS to Disable the ADC peripheral */
- ADCx->CR |= (uint32_t)ADC_CR_ADDIS;
- }
-}
-
-/**
- * @brief Configure the ADC to either be clocked by the asynchronous clock(which is
- * independent, the dedicated 14MHz clock) or the synchronous clock derived from
- * the APB clock of the ADC bus interface divided by 2 or 4
- * @note This function can be called only when ADC is disabled.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_ClockMode: This parameter can be :
- * @arg ADC_ClockMode_AsynClk: ADC clocked by the dedicated 14MHz clock
- * @arg ADC_ClockMode_SynClkDiv2: ADC clocked by PCLK/2
- * @arg ADC_ClockMode_SynClkDiv4: ADC clocked by PCLK/4
- * @retval None
- */
-void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLOCKMODE(ADC_ClockMode));
-
- /* Configure the ADC Clock mode according to ADC_ClockMode */
- ADCx->CFGR2 = (uint32_t)ADC_ClockMode;
-
-}
-
-/**
- * @brief Enables or disables the jitter when the ADC is clocked by PCLK div2
- * or div4
- * @note This function is obsolete and maintained for legacy purpose only. ADC_ClockModeConfig()
- * function should be used instead.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_JitterOff: This parameter can be :
- * @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2
- * @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4
- * @param NewState: new state of the ADCx jitter.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_JITTEROFF(ADC_JitterOff));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Disable Jitter */
- ADCx->CFGR2 |= (uint32_t)ADC_JitterOff;
- }
- else
- {
- /* Enable Jitter */
- ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group2 Power saving functions
- * @brief Power saving functions
- *
-@verbatim
- ===============================================================================
- ##### Power saving functions #####
- ===============================================================================
- [..] This section provides functions allowing to reduce power consumption.
- [..] The two function must be combined to get the maximal benefits:
- When the ADC frequency is higher than the CPU one, it is recommended to
- (#) Enable the Auto Delayed Conversion mode :
- ==> using ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
- (#) Enable the power off in Delay phases :
- ==> using ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the ADC Power Off.
- * @note ADC power-on and power-off can be managed by hardware to cut the
- * consumption when the ADC is not converting.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @note The ADC can be powered down:
- * - During the Auto delay phase: The ADC is powered on again at the end
- * of the delay (until the previous data is read from the ADC data register).
- * - During the ADC is waiting for a trigger event: The ADC is powered up
- * at the next trigger event (when the conversion is started).
- * @param NewState: new state of the ADCx power Off.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the ADC Automatic Power-Off */
- ADCx->CFGR1 |= ADC_CFGR1_AUTOFF;
- }
- else
- {
- /* Disable the ADC Automatic Power-Off */
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF;
- }
-}
-
-/**
- * @brief Enables or disables the Wait conversion mode.
- * @note When the CPU clock is not fast enough to manage the data rate, a
- * Hardware delay can be introduced between ADC conversions to reduce
- * this data rate.
- * @note The Hardware delay is inserted after each conversions and until the
- * previous data is read from the ADC data register
- * @note This is a way to automatically adapt the speed of the ADC to the speed
- * of the system which will read the data.
- * @note Any hardware triggers wich occur while a conversion is on going or
- * while the automatic Delay is applied are ignored
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the ADCx Auto-Delay.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the ADC Automatic Delayed conversion */
- ADCx->CFGR1 |= ADC_CFGR1_WAIT;
- }
- else
- {
- /* Disable the ADC Automatic Delayed conversion */
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group3 Analog Watchdog configuration functions
- * @brief Analog Watchdog configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Analog Watchdog configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the Analog Watchdog
- (AWD) feature in the ADC.
- [..] A typical configuration Analog Watchdog is done following these steps :
- (#) the ADC guarded channel(s) is (are) selected using the
- ADC_AnalogWatchdogSingleChannelConfig() function.
- (#) The Analog watchdog lower and higher threshold are configured using the
- ADC_AnalogWatchdogThresholdsConfig() function.
- (#) The Analog watchdog is enabled and configured to enable the check, on one
- or more channels, using the ADC_AnalogWatchdogCmd() function.
- (#) Enable the analog watchdog on the selected channel using
- ADC_AnalogWatchdogSingleChannelCmd() function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the analog watchdog
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the ADCx Analog Watchdog.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the ADC Analog Watchdog */
- ADCx->CFGR1 |= ADC_CFGR1_AWDEN;
- }
- else
- {
- /* Disable the ADC Analog Watchdog */
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN;
- }
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
-
- /* Set the ADCx high and low threshold */
- ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16);
-
-}
-
-/**
- * @brief Configures the analog watchdog guarded single channel
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected
- * @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected
- * @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected
- * @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected
- * @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected
- * @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected
- * @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected
- * @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected
- * @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected
- * @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected
- * @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected
- * @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected
- * @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected, not available for STM32F030 devices
- * @note The channel selected on the AWDCH must be also set into the CHSELR
- * register
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel));
-
- /* Get the old register value */
- tmpreg = ADCx->CFGR1;
-
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= ~ADC_CFGR1_AWDCH;
-
- /* Set the Analog watchdog channel */
- tmpreg |= ADC_AnalogWatchdog_Channel;
-
- /* Store the new register value */
- ADCx->CFGR1 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the ADC Analog Watchdog Single Channel.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the ADCx ADC Analog Watchdog Single Channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the ADC Analog Watchdog Single Channel */
- ADCx->CFGR1 |= ADC_CFGR1_AWDSGL;
- }
- else
- {
- /* Disable the ADC Analog Watchdog Single Channel */
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group4 Temperature Sensor, Vrefint and Vbat management functions
- * @brief Temperature Sensor, Vrefint and Vbat management functions
- *
-@verbatim
- ===============================================================================
- ##### Temperature Sensor, Vrefint and Vbat management function #####
- ===============================================================================
- [..] This section provides a function allowing to enable/disable the internal
- connections between the ADC and the Temperature Sensor, the Vrefint and
- Vbat source.
-
- [..] A typical configuration to get the Temperature sensor, Vrefint and Vbat channels
- voltages is done following these steps :
- (#) Enable the internal connection of Temperature sensor, Vrefint or Vbat sources
- with the ADC channels using ADC_TempSensorCmd(), ADC_VrefintCmd() or ADC_VbatCmd()
- functions.
- (#) select the ADC_Channel_16(Temperature sensor), ADC_Channel_17(Vrefint)
- or ADC_Channel_18(Voltage battery) using ADC_ChannelConfig() function
- (#) Get the voltage values, using ADC_GetConversionValue() function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the temperature sensor channel.
- * @param NewState: new state of the temperature sensor input channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_TSEN;
- }
- else
- {
- /* Disable the temperature sensor channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN);
- }
-}
-
-/**
- * @brief Enables or disables the Vrefint channel.
- * @param NewState: new state of the Vref input channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VrefintCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Vrefint channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_VREFEN;
- }
- else
- {
- /* Disable the Vrefint channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN);
- }
-}
-
-/**
- * @brief Enables or disables the Vbat channel.
- * @note This feature is not applicable for STM32F030 devices.
- * @param NewState: new state of the Vbat input channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VbatCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Vbat channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_VBATEN;
- }
- else
- {
- /* Disable the Vbat channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group5 Channels Configuration functions
- * @brief Channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Channels Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to manage the ADC channels,
- it is composed of 3 sub sections :
- (#) Configuration and management functions for ADC channels: This subsection
- provides functions allowing to configure the ADC channels :
- (++) Select the ADC channels
- (++) Activate ADC Calibration
- (++) Activate the Overrun Mode.
- (++) Activate the Discontinuous Mode
- (++) Activate the Continuous Mode.
- (++) Configure the sampling time for each channel
- (++) Select the conversion Trigger and Edge for ADC channels
- (++) Select the scan direction.
- -@@- Please Note that the following features for ADC channels are configurated
- using the ADC_Init() function :
- (+@@) Activate the Continuous Mode (can be also activated by ADC_OverrunModeCmd().
- (+@@) Select the conversion Trigger and Edge for ADC channels
- (+@@) Select the scan direction.
- (#) Control the ADC peripheral : This subsection permits to command the ADC:
- (++) Stop or discard an on-going conversion (ADSTP command)
- (++) Start the ADC conversion .
- (#) Get the conversion data: This subsection provides an important function in
- the ADC peripheral since it returns the converted data of the current
- ADC channel. When the Conversion value is read, the EOC Flag is
- automatically cleared.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures for the selected ADC and its sampling time.
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be any combination of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected, not available for STM32F031 devices
- * @arg ADC_Channel_11: ADC Channel11 selected, not available for STM32F031 devices
- * @arg ADC_Channel_12: ADC Channel12 selected, not available for STM32F031 devices
- * @arg ADC_Channel_13: ADC Channel13 selected, not available for STM32F031 devices
- * @arg ADC_Channel_14: ADC Channel14 selected, not available for STM32F031 devices
- * @arg ADC_Channel_15: ADC Channel15 selected, not available for STM32F031 devices
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected, not available for STM32F030 devices
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles
- * @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles
- * @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles
- * @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles
- * @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles
- * @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles
- * @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles
- * @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles
- * @retval None
- */
-void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* Configure the ADC Channel */
- ADCx->CHSELR |= (uint32_t)ADC_Channel;
-
- /* Clear the Sampling time Selection bits */
- tmpreg &= ~ADC_SMPR1_SMPR;
-
- /* Set the ADC Sampling Time register */
- tmpreg |= (uint32_t)ADC_SampleTime;
-
- /* Configure the ADC Sample time register */
- ADCx->SMPR = tmpreg ;
-}
-
-/**
- * @brief Enable the Continuous mode for the selected ADCx channels.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the Continuous mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note It is not possible to have both discontinuous mode and continuous mode
- * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves
- * as if continuous mode was disabled
- * @retval None
- */
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Continuous mode*/
- ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT;
- }
- else
- {
- /* Disable the Continuous mode */
- ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT);
- }
-}
-
-/**
- * @brief Enable the discontinuous mode for the selected ADC channels.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the discontinuous mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note It is not possible to have both discontinuous mode and continuous mode
- * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves
- * as if continuous mode was disabled
- * @retval None
- */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Discontinuous mode */
- ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN;
- }
- else
- {
- /* Disable the Discontinuous mode */
- ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN);
- }
-}
-
-/**
- * @brief Enable the Overrun mode for the selected ADC channels.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the Overrun mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Overrun mode */
- ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD;
- }
- else
- {
- /* Disable the Overrun mode */
- ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD);
- }
-}
-
-/**
- * @brief Active the Calibration operation for the selected ADC.
- * @note The Calibration can be initiated only when ADC is still in the
- * reset configuration (ADEN must be equal to 0).
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @retval ADC Calibration factor
- */
-uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx)
-{
- uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADC calibartion */
- ADCx->CR |= (uint32_t)ADC_CR_ADCAL;
-
- /* Wait until no ADC calibration is completed */
- do
- {
- calibrationstatus = ADCx->CR & ADC_CR_ADCAL;
- calibrationcounter++;
- } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00));
-
- if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET)
- {
- /*Get the calibration factor from the ADC data register */
- tmpreg = ADCx->DR;
- }
- else
- {
- /* Error factor */
- tmpreg = 0x00000000;
- }
- return tmpreg;
-}
-
-/**
- * @brief Stop the on going conversions for the selected ADC.
- * @note When ADSTP is set, any on going conversion is aborted, and the ADC
- * data register is not updated with current conversion.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @retval None
- */
-void ADC_StopOfConversion(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- ADCx->CR |= (uint32_t)ADC_CR_ADSTP;
-}
-
-/**
- * @brief Start Conversion for the selected ADC channels.
- * @note In continuous mode, ADSTART is not cleared by hardware with the
- * assertion of EOSEQ because the sequence is automatic relaunched
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @retval None
- */
-void ADC_StartOfConversion(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- ADCx->CR |= (uint32_t)ADC_CR_ADSTART;
-}
-
-/**
- * @brief Returns the last ADCx conversion result data for ADC channel.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Return the selected ADC conversion value */
- return (uint16_t) ADCx->DR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group6 DMA Configuration functions
- * @brief Regular Channels DMA Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### DMA Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the DMA for ADC hannels.
- Since converted channel values are stored into a unique data register,
- it is useful to use DMA for conversion of more than one channel. This
- avoids the loss of the data already stored in the ADC Data register.
- When the DMA mode is enabled (using the ADC_DMACmd() function), after each
- conversion of a channel, a DMA request is generated.
-
- [..] Depending on the "DMA disable selection" configuration (using the
- ADC_DMARequestModeConfig() function), at the end of the last DMA
- transfer, two possibilities are allowed:
- (+) No new DMA request is issued to the DMA controller (One Shot Mode)
- (+) Requests can continue to be generated (Circular Mode).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified ADC DMA request.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the selected ADC DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_DMARequestMode: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_DMAMode_OneShot: DMA One Shot Mode
- * @arg ADC_DMAMode_Circular: DMA Circular Mode
- * @retval None
- */
-void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG;
- ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions.
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the ADC Interrupts
- and get the status and clear flags and Interrupts pending bits.
-
- [..] The ADC provide 6 Interrupts sources and 11 Flags which can be divided into
- 3 groups:
-
- *** Flags for ADC status ***
- ======================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_ADRDY : This flag is set after the ADC has been enabled (bit ADEN=1)
- and when the ADC reaches a state where it is ready to accept conversion requests
- (##) ADC_FLAG_ADEN : This flag is set by software to enable the ADC.
- The ADC will be effectively ready to operate once the ADRDY flag has been set.
- (##) ADC_FLAG_ADDIS : This flag is cleared once the ADC is effectively
- disabled.
- (##) ADC_FLAG_ADSTART : This flag is cleared after the execution of
- ADC_StopOfConversion() function, at the same time as the ADSTP bit is
- cleared by hardware
- (##) ADC_FLAG_ADSTP : This flag is cleared by hardware when the conversion
- is effectively discarded and the ADC is ready to accept a new start conversion
- (##) ADC_FLAG_ADCAL : This flag is set once the calibration is complete.
-
- (+)Interrupts
- (##) ADC_IT_ADRDY : specifies the interrupt source for ADC ready event.
-
- *** Flags and Interrupts for ADC channel conversion ***
- =====================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_EOC : This flag is set by hardware at the end of each conversion
- of a channel when a new data result is available in the data register
- (##) ADC_FLAG_EOSEQ : This bit is set by hardware at the end of the conversion
- of a sequence of channels selected by ADC_ChannelConfig() function.
- (##) ADC_FLAG_EOSMP : This bit is set by hardware at the end of the sampling phase.
- (##) ADC_FLAG_OVR : This flag is set by hardware when an overrun occurs,
- meaning that a new conversion has complete while the EOC flag was already set.
-
- (+)Interrupts :
- (##) ADC_IT_EOC : specifies the interrupt source for end of conversion event.
- (##) ADC_IT_EOSEQ : specifies the interrupt source for end of sequence event.
- (##) ADC_IT_EOSMP : specifies the interrupt source for end of sampling event.
- (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection
- event.
-
- *** Flags and Interrupts for the Analog Watchdog ***
- ================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_AWD: This flag is set by hardware when the converted
- voltage crosses the values programmed thrsholds
-
- (+)Interrupts :
- (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog
- event.
-
- [..] The user should identify which mode will be used in his application to
- manage the ADC controller events: Polling mode or Interrupt mode.
-
- [..] In the Polling Mode it is advised to use the following functions:
- (+) ADC_GetFlagStatus() : to check if flags events occur.
- (+) ADC_ClearFlag() : to clear the flags events.
-
- [..] In the Interrupt Mode it is advised to use the following functions:
- (+) ADC_ITConfig() : to enable or disable the interrupt source.
- (+) ADC_GetITStatus() : to check if Interrupt occurs.
- (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified ADC interrupts.
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ADC_IT_ADRDY: ADC ready interrupt
- * @arg ADC_IT_EOSMP: End of sampling interrupt
- * @arg ADC_IT_EOC: End of conversion interrupt
- * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
- * @arg ADC_IT_OVR: overrun interrupt
- * @arg ADC_IT_AWD: Analog watchdog interrupt
- * @param NewState: new state of the specified ADC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_CONFIG_IT(ADC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->IER |= ADC_IT;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->IER &= (~(uint32_t)ADC_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @arg ADC_FLAG_EOSEQ: End of Sequence flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_EOSMP: End of sampling flag
- * @arg ADC_FLAG_ADRDY: ADC Ready flag
- * @arg ADC_FLAG_ADEN: ADC enable flag
- * @arg ADC_FLAG_ADDIS: ADC disable flag
- * @arg ADC_FLAG_ADSTART: ADC start flag
- * @arg ADC_FLAG_ADSTP: ADC stop flag
- * @arg ADC_FLAG_ADCAL: ADC Calibration flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
- if((uint32_t)(ADC_FLAG & 0x01000000))
- {
- tmpreg = ADCx->CR & 0xFEFFFFFF;
- }
- else
- {
- tmpreg = ADCx->ISR;
- }
-
- /* Check the status of the specified ADC flag */
- if ((tmpreg & ADC_FLAG) != (uint32_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_ADRDY: ADC Ready flag
- * @arg ADC_FLAG_EOSMP: End of sampling flag
- * @arg ADC_FLAG_EOSEQ: End of Sequence flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval None
- */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
-
- /* Clear the selected ADC flags */
- ADCx->ISR = (uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified ADC interrupt has occurred or not.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral
- * @param ADC_IT: specifies the ADC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg ADC_IT_ADRDY: ADC ready interrupt
- * @arg ADC_IT_EOSMP: End of sampling interrupt
- * @arg ADC_IT_EOC: End of conversion interrupt
- * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
- * @arg ADC_IT_OVR: overrun interrupt
- * @arg ADC_IT_AWD: Analog watchdog interrupt
- * @retval The new state of ADC_IT (SET or RESET).
- */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_IT(ADC_IT));
-
- /* Get the ADC_IT enable bit status */
- enablestatus = (uint32_t)(ADCx->IER & ADC_IT);
-
- /* Check the status of the specified ADC interrupt */
- if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- /* ADC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's interrupt pending bits.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg ADC_IT_ADRDY: ADC ready interrupt
- * @arg ADC_IT_EOSMP: End of sampling interrupt
- * @arg ADC_IT_EOC: End of conversion interrupt
- * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
- * @arg ADC_IT_OVR: overrun interrupt
- * @arg ADC_IT_AWD: Analog watchdog interrupt
- * @retval None
- */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_IT(ADC_IT));
-
- /* Clear the selected ADC interrupt pending bits */
- ADCx->ISR = (uint32_t)ADC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_adc.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,460 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_adc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the ADC firmware
- * library
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_ADC_H
-#define __STM32F0XX_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief ADC Init structure definition
- */
-
-typedef struct
-{
- uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
- This parameter can be a value of @ref ADC_Resolution */
-
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
- Continuous or Single mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
- trigger of a regular group. This parameter can be a value
- of @ref ADC_external_trigger_edge_conversion */
-
- uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
- to digital conversion of regular channels. This parameter
- can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */
-
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
- This parameter can be a value of @ref ADC_data_align */
-
- uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned
- in the sequence.
- This parameter can be a value of @ref ADC_Scan_Direction */
-}ADC_InitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
- * @{
- */
-#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
-
-/** @defgroup ADC_JitterOff
- * @{
- */
-/* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */
-#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2
-#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4
-
-#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_ClockMode
- * @{
- */
-#define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
-#define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */
-#define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */
-#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\
- ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\
- ((CLOCK) == ADC_ClockMode_SynClkDiv4))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Resolution
- * @{
- */
-#define ADC_Resolution_12b ((uint32_t)0x00000000)
-#define ADC_Resolution_10b ADC_CFGR1_RES_0
-#define ADC_Resolution_8b ADC_CFGR1_RES_1
-#define ADC_Resolution_6b ADC_CFGR1_RES
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
- ((RESOLUTION) == ADC_Resolution_10b) || \
- ((RESOLUTION) == ADC_Resolution_8b) || \
- ((RESOLUTION) == ADC_Resolution_6b))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_edge_conversion
- * @{
- */
-#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0
-#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1
-#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN
-
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_sources_for_channels_conversion
- * @{
- */
-
-/* TIM1 */
-#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0
-
-/* TIM2 */
-#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1
-
-/* TIM3 */
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1))
-
-/* TIM15 */
-#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2
-
-#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \
- ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \
- ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \
- ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \
- ((CONV) == ADC_ExternalTrigConv_T15_TRGO))
-/**
- * @}
- */
-
-/** @defgroup ADC_data_align
- * @{
- */
-
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left ADC_CFGR1_ALIGN
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
- ((ALIGN) == ADC_DataAlign_Left))
-/**
- * @}
- */
-
-/** @defgroup ADC_Scan_Direction
- * @{
- */
-
-#define ADC_ScanDirection_Upward ((uint32_t)0x00000000)
-#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR
-
-#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \
- ((DIRECTION) == ADC_ScanDirection_Backward))
-/**
- * @}
- */
-
-/** @defgroup ADC_DMA_Mode
- * @{
- */
-
-#define ADC_DMAMode_OneShot ((uint32_t)0x00000000)
-#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG
-
-#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \
- ((MODE) == ADC_DMAMode_Circular))
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_selection
- * @{
- */
-
-#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000)
-#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000)
-#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000)
-#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000)
-#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000)
-#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000)
-#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000)
-#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000)
-#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000)
-#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000)
-#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000)
-#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000)
-#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000)
-
-
-#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
-/**
- * @}
- */
-
-/** @defgroup ADC_sampling_times
- * @{
- */
-
-#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000)
-#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001)
-#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002)
-#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003)
-#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004)
-#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005)
-#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006)
-#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007)
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \
- ((TIME) == ADC_SampleTime_7_5Cycles) || \
- ((TIME) == ADC_SampleTime_13_5Cycles) || \
- ((TIME) == ADC_SampleTime_28_5Cycles) || \
- ((TIME) == ADC_SampleTime_41_5Cycles) || \
- ((TIME) == ADC_SampleTime_55_5Cycles) || \
- ((TIME) == ADC_SampleTime_71_5Cycles) || \
- ((TIME) == ADC_SampleTime_239_5Cycles))
-/**
- * @}
- */
-
-/** @defgroup ADC_thresholds
- * @{
- */
-
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_channels
- * @{
- */
-
-#define ADC_Channel_0 ADC_CHSELR_CHSEL0
-#define ADC_Channel_1 ADC_CHSELR_CHSEL1
-#define ADC_Channel_2 ADC_CHSELR_CHSEL2
-#define ADC_Channel_3 ADC_CHSELR_CHSEL3
-#define ADC_Channel_4 ADC_CHSELR_CHSEL4
-#define ADC_Channel_5 ADC_CHSELR_CHSEL5
-#define ADC_Channel_6 ADC_CHSELR_CHSEL6
-#define ADC_Channel_7 ADC_CHSELR_CHSEL7
-#define ADC_Channel_8 ADC_CHSELR_CHSEL8
-#define ADC_Channel_9 ADC_CHSELR_CHSEL9
-#define ADC_Channel_10 ADC_CHSELR_CHSEL10 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_11 ADC_CHSELR_CHSEL11 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_12 ADC_CHSELR_CHSEL12 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_13 ADC_CHSELR_CHSEL13 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_14 ADC_CHSELR_CHSEL14 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_15 ADC_CHSELR_CHSEL15 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_16 ADC_CHSELR_CHSEL16
-#define ADC_Channel_17 ADC_CHSELR_CHSEL17
-#define ADC_Channel_18 ADC_CHSELR_CHSEL18 /*!< Not available for STM32F030 devices */
-
-#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16)
-#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17)
-#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18) /*!< Not available for STM32F030 devices */
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_interrupts_definition
- * @{
- */
-
-#define ADC_IT_ADRDY ADC_IER_ADRDYIE
-#define ADC_IT_EOSMP ADC_IER_EOSMPIE
-#define ADC_IT_EOC ADC_IER_EOCIE
-#define ADC_IT_EOSEQ ADC_IER_EOSEQIE
-#define ADC_IT_OVR ADC_IER_OVRIE
-#define ADC_IT_AWD ADC_IER_AWDIE
-
-#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
-
-#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \
- ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \
- ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD))
-
-#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_flags_definition
- * @{
- */
-
-#define ADC_FLAG_ADRDY ADC_ISR_ADRDY
-#define ADC_FLAG_EOSMP ADC_ISR_EOSMP
-#define ADC_FLAG_EOC ADC_ISR_EOC
-#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ
-#define ADC_FLAG_OVR ADC_ISR_OVR
-#define ADC_FLAG_AWD ADC_ISR_AWD
-
-#define ADC_FLAG_ADEN ((uint32_t)0x01000001)
-#define ADC_FLAG_ADDIS ((uint32_t)0x01000002)
-#define ADC_FLAG_ADSTART ((uint32_t)0x01000004)
-#define ADC_FLAG_ADSTP ((uint32_t)0x01000010)
-#define ADC_FLAG_ADCAL ((uint32_t)0x81000000)
-
-#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET))
-
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
- ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \
- ((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \
- ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \
- ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \
- ((FLAG) == ADC_FLAG_ADCAL))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the ADC configuration to the default reset state *****/
-void ADC_DeInit(ADC_TypeDef* ADCx);
-
-/* Initialization and Configuration functions *********************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-/* This Function is obsolete and maintained for legacy purpose only.
- ADC_ClockModeConfig() function should be used instead */
-void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);
-
-/* Power saving functions *****************************************************/
-void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);
-void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Temperature Sensor , Vrefint and Vbat management function ******************/
-void ADC_TempSensorCmd(FunctionalState NewState);
-void ADC_VrefintCmd(FunctionalState NewState);
-void ADC_VbatCmd(FunctionalState NewState); /*!< Not applicable for STM32F030 devices */
-
-/* Channels Configuration functions *******************************************/
-void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);
-void ADC_StopOfConversion(ADC_TypeDef* ADCx);
-void ADC_StartOfConversion(ADC_TypeDef* ADCx);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_ADC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_can.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1641 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_can.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Controller area network (CAN) peripheral and
- * applicable only for STM32F072 devices :
- * + Initialization and Configuration
- * + CAN Frames Transmission
- * + CAN Frames Reception
- * + Operation modes switch
- * + Error management
- * + Interrupts and flags
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN, ENABLE);
- (#) CAN pins configuration:
- (++) Enable the clock for the CAN GPIOs using the following function:
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
- (++) Connect the involved CAN pins to AF0 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
- (++) Configure these CAN pins in alternate function mode by calling
- the function GPIO_Init();
- (#) Initialise and configure the CAN using CAN_Init() and
- CAN_FilterInit() functions.
- (#) Transmit the desired CAN frame using CAN_Transmit() function.
- (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function.
- (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function.
- (#) Receive a CAN frame using CAN_Recieve() function.
- (#) Release the receive FIFOs using CAN_FIFORelease() function.
- (#) Return the number of pending received frames using CAN_MessagePending() function.
- (#) To control CAN events you can use one of the following two methods:
- (++) Check on CAN flags using the CAN_GetFlagStatus() function.
- (++) Use CAN interrupts through the function CAN_ITConfig() at initialization
- phase and CAN_GetITStatus() function into interrupt routines to check
- if the event has occurred or not.
- After checking on a flag you should clear it using CAN_ClearFlag()
- function. And after checking on an interrupt event you should clear it
- using CAN_ClearITPendingBit() function.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_can.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CAN
- * @brief CAN driver modules
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CAN Master Control Register bits */
-#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
-
-/* Flags in TSR register */
-#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
-/* Flags in RF1R register */
-#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
-/* Flags in RF0R register */
-#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
-/* Flags in MSR register */
-#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
-/* Flags in ESR register */
-#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-
-#define CAN_MODE_MASK ((uint32_t) 0x00000003)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
-
-/** @defgroup CAN_Private_Functions
- * @{
- */
-
-/** @defgroup CAN_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum
- number of time quanta to perform resynchronization, the number of time
- quanta in Bit Segment 1 and 2 and many other modes.
- (+) Configure the CAN reception filter.
- (+) Select the start bank filter for slave CAN.
- (+) Enable or disable the Debug Freeze mode for CAN.
- (+) Enable or disable the CAN Time Trigger Operation communication mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the CAN peripheral registers to their default reset values.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @retval None.
- */
-void CAN_DeInit(CAN_TypeDef* CANx)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Enable CAN reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
- /* Release CAN from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
-}
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
- * the configuration information for the CAN peripheral.
- * @retval Constant indicates initialization succeed which will be
- * CAN_InitStatus_Failed or CAN_InitStatus_Success.
- */
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
-{
- uint8_t InitStatus = CAN_InitStatus_Failed;
- uint32_t wait_ack = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
- /* Exit from sleep mode */
- CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
- /* Request initialisation */
- CANx->MCR |= CAN_MCR_INRQ ;
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* Check acknowledge */
- if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- /* Set the time triggered communication mode */
- if (CAN_InitStruct->CAN_TTCM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TTCM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (CAN_InitStruct->CAN_ABOM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_ABOM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
- }
-
- /* Set the automatic wake-up mode */
- if (CAN_InitStruct->CAN_AWUM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_AWUM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
- }
-
- /* Set the no automatic retransmission */
- if (CAN_InitStruct->CAN_NART == ENABLE)
- {
- CANx->MCR |= CAN_MCR_NART;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (CAN_InitStruct->CAN_RFLM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_RFLM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (CAN_InitStruct->CAN_TXFP == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TXFP;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
- }
-
- /* Set the bit timing register */
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
- ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
- ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
- ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
-
- /* Request leave initialisation */
- CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
- /* Wait the acknowledge */
- wait_ack = 0;
-
- while (((CANx->MSR & CAN_MSR_INAK) == (uint16_t)CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* ...and check acknowledged */
- if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- InitStatus = CAN_InitStatus_Success ;
- }
- }
-
- /* At this step, return the status of initialization */
- return InitStatus;
-}
-
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
- * contains the configuration information.
- * @retval None
- */
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
- uint32_t filter_number_bit_pos = 0;
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
- filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
-
- /* Initialisation mode for the filter */
- CAN->FMR |= FMR_FINIT;
-
- /* Filter Deactivation */
- CAN->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* Filter Scale */
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
- {
- /* 16-bit scale for the filter */
- CAN->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
- }
-
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
- {
- /* 32-bit scale for the filter */
- CAN->FS1R |= filter_number_bit_pos;
- /* 32-bit identifier or First 32-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
- {
- /*Id/Mask mode for the filter*/
- CAN->FM1R &= ~(uint32_t)filter_number_bit_pos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- CAN->FM1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CAN->FFA1R &= ~(uint32_t)filter_number_bit_pos;
- }
-
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
- {
- /* FIFO 1 assignation for the filter */
- CAN->FFA1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter activation */
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
- {
- CAN->FA1R |= filter_number_bit_pos;
- }
-
- /* Leave the initialisation mode for the filter */
- CAN->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Fills each CAN_InitStruct member with its default value.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
- * @retval None
- */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
- /* Reset CAN init structure parameters values */
-
- /* Initialize the time triggered communication mode */
- CAN_InitStruct->CAN_TTCM = DISABLE;
-
- /* Initialize the automatic bus-off management */
- CAN_InitStruct->CAN_ABOM = DISABLE;
-
- /* Initialize the automatic wake-up mode */
- CAN_InitStruct->CAN_AWUM = DISABLE;
-
- /* Initialize the no automatic retransmission */
- CAN_InitStruct->CAN_NART = DISABLE;
-
- /* Initialize the receive FIFO locked mode */
- CAN_InitStruct->CAN_RFLM = DISABLE;
-
- /* Initialize the transmit FIFO priority */
- CAN_InitStruct->CAN_TXFP = DISABLE;
-
- /* Initialize the CAN_Mode member */
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
-
- /* Initialize the CAN_SJW member */
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
-
- /* Initialize the CAN_BS1 member */
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
-
- /* Initialize the CAN_BS2 member */
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
-
- /* Initialize the CAN_Prescaler member */
- CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-/**
- * @brief Select the start bank filter for slave CAN.
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
- * @retval None
- */
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
-
- /* Enter Initialisation mode for the filter */
- CAN->FMR |= FMR_FINIT;
-
- /* Select the start slave bank */
- CAN->FMR &= (uint32_t)0xFFFFC0F1 ;
- CAN->FMR |= (uint32_t)(CAN_BankNumber)<<8;
-
- /* Leave Initialisation mode for the filter */
- CAN->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Enables or disables the DBG Freeze for CAN.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Debug Freeze */
- CANx->MCR |= MCR_DBF;
- }
- else
- {
- /* Disable Debug Freeze */
- CANx->MCR &= ~MCR_DBF;
- }
-}
-
-/**
- * @brief Enables or disables the CAN Time TriggerOperation communication mode.
- * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
- * sent over the CAN bus.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
- * When enabled, Time stamp (TIME[15:0]) value is sent in the last two
- * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8]
- * in data byte 7.
- * @retval None
- */
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TTCM mode */
- CANx->MCR |= CAN_MCR_TTCM;
-
- /* Set TGT bits */
- CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
- }
- else
- {
- /* Disable the TTCM mode */
- CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
-
- /* Reset TGT bits */
- CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group2 CAN Frames Transmission functions
- * @brief CAN Frames Transmission functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Frames Transmission functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
- (+) Check the transmission status of a CAN Frame.
- (+) Cancel a transmit request.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
- * @retval The number of the mailbox that is used for transmission or
- * CAN_TxStatus_NoMailBox if there is no empty mailbox.
- */
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
-{
- uint8_t transmit_mailbox = 0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
- assert_param(IS_CAN_RTR(TxMessage->RTR));
- assert_param(IS_CAN_DLC(TxMessage->DLC));
-
- /* Select one empty transmit mailbox */
- if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmit_mailbox = 0;
- }
- else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmit_mailbox = 1;
- }
- else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmit_mailbox = 2;
- }
- else
- {
- transmit_mailbox = CAN_TxStatus_NoMailBox;
- }
-
- if (transmit_mailbox != CAN_TxStatus_NoMailBox)
- {
- /* Set up the Id */
- CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
- if (TxMessage->IDE == CAN_Id_Standard)
- {
- assert_param(IS_CAN_STDID(TxMessage->StdId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
- TxMessage->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(TxMessage->ExtId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
- TxMessage->IDE | \
- TxMessage->RTR);
- }
-
- /* Set up the DLC */
- TxMessage->DLC &= (uint8_t)0x0000000F;
- CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
-
- /* Set up the data field */
- CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
- ((uint32_t)TxMessage->Data[2] << 16) |
- ((uint32_t)TxMessage->Data[1] << 8) |
- ((uint32_t)TxMessage->Data[0]));
- CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
- ((uint32_t)TxMessage->Data[6] << 16) |
- ((uint32_t)TxMessage->Data[5] << 8) |
- ((uint32_t)TxMessage->Data[4]));
- /* Request transmission */
- CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
- }
- return transmit_mailbox;
-}
-
-/**
- * @brief Checks the transmission status of a CAN Frame.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.
- * @retval CAN_TxStatus_Ok if the CAN driver transmits the message,
- * CAN_TxStatus_Failed in an other case.
- */
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
-{
- uint32_t state = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
-
- switch (TransmitMailbox)
- {
- case (CAN_TXMAILBOX_0):
- state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
- break;
- case (CAN_TXMAILBOX_1):
- state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
- break;
- case (CAN_TXMAILBOX_2):
- state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
- break;
- default:
- state = CAN_TxStatus_Failed;
- break;
- }
- switch (state)
- {
- /* transmit pending */
- case (0x0): state = CAN_TxStatus_Pending;
- break;
- /* transmit failed */
- case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
- break;
- /* transmit succeeded */
- case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
- break;
- default: state = CAN_TxStatus_Failed;
- break;
- }
- return (uint8_t) state;
-}
-
-/**
- * @brief Cancels a transmit request.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param Mailbox: Mailbox number.
- * @retval None
- */
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
- /* abort transmission */
- switch (Mailbox)
- {
- case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
- break;
- case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
- break;
- case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
- break;
- default:
- break;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group3 CAN Frames Reception functions
- * @brief CAN Frames Reception functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Frames Reception functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Receive a correct CAN frame.
- (+) Release a specified receive FIFO (2 FIFOs are available).
- (+) Return the number of the pending received CAN frames.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Receives a correct CAN frame.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @param RxMessage: pointer to a structure receive frame which contains CAN Id,
- * CAN DLC, CAN data and FMI number.
- * @retval None
- */
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Get the Id */
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
- if (RxMessage->IDE == CAN_Id_Standard)
- {
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
- }
- else
- {
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
- /* Get the data field */
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Releases the specified receive FIFO.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
- * @retval None
- */
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Returns the number of pending received messages.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval NbMessage : which is the number of pending message.
- */
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- uint8_t message_pending=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- if (FIFONumber == CAN_FIFO0)
- {
- message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
- }
- else if (FIFONumber == CAN_FIFO1)
- {
- message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
- }
- else
- {
- message_pending = 0;
- }
- return message_pending;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group4 CAN Operation modes functions
- * @brief CAN Operation modes functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Operation modes functions #####
- ===============================================================================
- [..] This section provides functions allowing to select the CAN Operation modes:
- (+) sleep mode.
- (+) normal mode.
- (+) initialization mode.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Selects the CAN Operation mode.
- * @param CAN_OperatingMode: CAN Operating Mode.
- * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
- * @retval status of the requested mode which can be:
- * - CAN_ModeStatus_Failed: CAN failed entering the specific mode
- * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode
- */
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
-{
- uint8_t status = CAN_ModeStatus_Failed;
-
- /* Timeout for INAK or also for SLAK bits*/
- uint32_t timeout = INAK_TIMEOUT;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
-
- if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
- {
- /* Request initialisation */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
- {
- /* Request leave initialisation and sleep mode and enter Normal mode */
- CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != 0)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
- {
- /* Request Sleep mode */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else
- {
- status = CAN_ModeStatus_Failed;
- }
-
- return (uint8_t) status;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
- */
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)
-{
- uint8_t sleepstatus = CAN_Sleep_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Request Sleep mode */
- CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Sleep mode status */
- if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
- {
- /* Sleep mode not entered */
- sleepstatus = CAN_Sleep_Ok;
- }
- /* return sleep mode status */
- return (uint8_t)sleepstatus;
-}
-
-/**
- * @brief Wakes up the CAN peripheral from sleep mode .
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
- */
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
-{
- uint32_t wait_slak = SLAK_TIMEOUT;
- uint8_t wakeupstatus = CAN_WakeUp_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Wake up request */
- CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Sleep mode status */
- while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
- {
- wait_slak--;
- }
- if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
- {
- /* wake up done : Sleep mode exited */
- wakeupstatus = CAN_WakeUp_Ok;
- }
- /* return wakeup status */
- return (uint8_t)wakeupstatus;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group5 CAN Bus Error management functions
- * @brief CAN Bus Error management functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Bus Error management functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Return the CANx's last error code (LEC).
- (+) Return the CANx Receive Error Counter (REC).
- (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- [..]
- (@) If TEC is greater than 255, The CAN is in bus-off state.
- (@) If REC or TEC are greater than 96, an Error warning flag occurs.
- (@) If REC or TEC are greater than 127, an Error Passive Flag occurs.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the CANx's last error code (LEC).
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @retval Error code:
- * - CAN_ERRORCODE_NoErr: No Error
- * - CAN_ERRORCODE_StuffErr: Stuff Error
- * - CAN_ERRORCODE_FormErr: Form Error
- * - CAN_ERRORCODE_ACKErr : Acknowledgment Error
- * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
- * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
- * - CAN_ERRORCODE_CRCErr: CRC Error
- * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
- */
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
-{
- uint8_t errorcode=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the error code*/
- errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
-
- /* Return the error code*/
- return errorcode;
-}
-
-/**
- * @brief Returns the CANx Receive Error Counter (REC).
- * @note In case of an error during reception, this counter is incremented
- * by 1 or by 8 depending on the error condition as defined by the CAN
- * standard. After every successful reception, the counter is
- * decremented by 1 or reset to 120 if its value was higher than 128.
- * When the counter value exceeds 127, the CAN controller enters the
- * error passive state.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval CAN Receive Error Counter.
- */
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the Receive Error Counter*/
- counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
-
- /* Return the Receive Error Counter*/
- return counter;
-}
-
-
-/**
- * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval LSB of the 9-bit CAN Transmit Error Counter.
- */
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
-
- /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- return counter;
-}
-/**
- * @}
- */
-
-/** @defgroup CAN_Group6 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the CAN Interrupts
- and to get the status and clear flags and Interrupts pending bits.
- [..] The CAN provides 14 Interrupts sources and 15 Flags:
-
- *** Flags ***
- =============
- [..] The 15 flags can be divided on 4 groups:
- (+) Transmit Flags:
- (++) CAN_FLAG_RQCP0.
- (++) CAN_FLAG_RQCP1.
- (++) CAN_FLAG_RQCP2: Request completed MailBoxes 0, 1 and 2 Flags
- Set when when the last request (transmit or abort) has
- been performed.
- (+) Receive Flags:
- (++) CAN_FLAG_FMP0.
- (++) CAN_FLAG_FMP1: FIFO 0 and 1 Message Pending Flags;
- Set to signal that messages are pending in the receive FIFO.
- These Flags are cleared only by hardware.
- (++) CAN_FLAG_FF0.
- (++) CAN_FLAG_FF1: FIFO 0 and 1 Full Flags;
- Set when three messages are stored in the selected FIFO.
- (++) CAN_FLAG_FOV0.
- (++) CAN_FLAG_FOV1: FIFO 0 and 1 Overrun Flags;
- Set when a new message has been received and passed the filter
- while the FIFO was full.
- (+) Operating Mode Flags:
- (++) CAN_FLAG_WKU: Wake up Flag;
- Set to signal that a SOF bit has been detected while the CAN
- hardware was in Sleep mode.
- (++) CAN_FLAG_SLAK: Sleep acknowledge Flag;
- Set to signal that the CAN has entered Sleep Mode.
- (+) Error Flags:
- (++) CAN_FLAG_EWG: Error Warning Flag;
- Set when the warning limit has been reached (Receive Error Counter
- or Transmit Error Counter greater than 96).
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_EPV: Error Passive Flag;
- Set when the Error Passive limit has been reached (Receive Error
- Counter or Transmit Error Counter greater than 127).
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_BOF: Bus-Off Flag;
- Set when CAN enters the bus-off state. The bus-off state is
- entered on TEC overflow, greater than 255.
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_LEC: Last error code Flag;
- Set If a message has been transferred (reception or transmission)
- with error, and the error code is hold.
-
- *** Interrupts ***
- ==================
- [..] The 14 interrupts can be divided on 4 groups:
- (+) Transmit interrupt:
- (++) CAN_IT_TME: Transmit mailbox empty Interrupt;
- If enabled, this interrupt source is pending when no transmit
- request are pending for Tx mailboxes.
- (+) Receive Interrupts:
- (++) CAN_IT_FMP0.
- (++) CAN_IT_FMP1: FIFO 0 and FIFO1 message pending Interrupts;
- If enabled, these interrupt sources are pending when messages
- are pending in the receive FIFO.
- The corresponding interrupt pending bits are cleared only by hardware.
- (++) CAN_IT_FF0.
- (++) CAN_IT_FF1: FIFO 0 and FIFO1 full Interrupts;
- If enabled, these interrupt sources are pending when three messages
- are stored in the selected FIFO.
- (++) CAN_IT_FOV0.
- (++) CAN_IT_FOV1: FIFO 0 and FIFO1 overrun Interrupts;
- If enabled, these interrupt sources are pending when a new message
- has been received and passed the filter while the FIFO was full.
- (+) Operating Mode Interrupts:
- (++) CAN_IT_WKU: Wake-up Interrupt;
- If enabled, this interrupt source is pending when a SOF bit has
- been detected while the CAN hardware was in Sleep mode.
- (++) CAN_IT_SLK: Sleep acknowledge Interrupt:
- If enabled, this interrupt source is pending when the CAN has
- entered Sleep Mode.
- (+) Error Interrupts:
- (++) CAN_IT_EWG: Error warning Interrupt;
- If enabled, this interrupt source is pending when the warning limit
- has been reached (Receive Error Counter or Transmit Error Counter=96).
- (++) CAN_IT_EPV: Error passive Interrupt;
- If enabled, this interrupt source is pending when the Error Passive
- limit has been reached (Receive Error Counter or Transmit Error Counter>127).
- (++) CAN_IT_BOF: Bus-off Interrupt;
- If enabled, this interrupt source is pending when CAN enters
- the bus-off state. The bus-off state is entered on TEC overflow,
- greater than 255.
- This Flag is cleared only by hardware.
- (++) CAN_IT_LEC: Last error code Interrupt;
- If enabled, this interrupt source is pending when a message has
- been transferred (reception or transmission) with error and the
- error code is hold.
- (++) CAN_IT_ERR: Error Interrupt;
- If enabled, this interrupt source is pending when an error condition
- is pending.
- [..] Managing the CAN controller events:
- The user should identify which mode will be used in his application to manage
- the CAN controller events: Polling mode or Interrupt mode.
- (+) In the Polling Mode it is advised to use the following functions:
- (++) CAN_GetFlagStatus() : to check if flags events occur.
- (++) CAN_ClearFlag() : to clear the flags events.
- (+) In the Interrupt Mode it is advised to use the following functions:
- (++) CAN_ITConfig() : to enable or disable the interrupt source.
- (++) CAN_GetITStatus() : to check if Interrupt occurs.
- (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts
- pending bits since there are cleared only by hardware.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified CANx interrupts.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @param NewState: new state of the CAN interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CANx interrupt */
- CANx->IER |= CAN_IT;
- }
- else
- {
- /* Disable the selected CANx interrupt */
- CANx->IER &= ~CAN_IT;
- }
-}
-/**
- * @brief Checks whether the specified CAN flag is set or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @retval The new state of CAN_FLAG (SET or RESET).
- */
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
-
-
- if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
- {
- /* Check the status of the specified CAN flag */
- if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- /* Return the CAN_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CAN's pending flags.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @retval None
- */
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- uint32_t flagtmp=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
-
- if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
- {
- /* Clear the selected CAN flags */
- CANx->ESR = (uint32_t)RESET;
- }
- else /* MSR or TSR or RF0R or RF1R */
- {
- flagtmp = CAN_FLAG & 0x000FFFFF;
-
- if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF0R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF1R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
- {
- /* Transmit Flags */
- CANx->TSR = (uint32_t)(flagtmp);
- }
- else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
- {
- /* Operating mode Flags */
- CANx->MSR = (uint32_t)(flagtmp);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @retval The current state of CAN_IT (SET or RESET).
- */
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- ITStatus itstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
-
- /* check the interrupt enable bit */
- if((CANx->IER & CAN_IT) != RESET)
- {
- /* in case the Interrupt is enabled, .... */
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Check CAN_TSR_RQCPx bits */
- itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
- break;
- case CAN_IT_FMP0:
- /* Check CAN_RF0R_FMP0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
- break;
- case CAN_IT_FF0:
- /* Check CAN_RF0R_FULL0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
- break;
- case CAN_IT_FOV0:
- /* Check CAN_RF0R_FOVR0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
- break;
- case CAN_IT_FMP1:
- /* Check CAN_RF1R_FMP1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
- break;
- case CAN_IT_FF1:
- /* Check CAN_RF1R_FULL1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
- break;
- case CAN_IT_FOV1:
- /* Check CAN_RF1R_FOVR1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
- break;
- case CAN_IT_WKU:
- /* Check CAN_MSR_WKUI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
- break;
- case CAN_IT_SLK:
- /* Check CAN_MSR_SLAKI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
- break;
- case CAN_IT_EWG:
- /* Check CAN_ESR_EWGF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
- break;
- case CAN_IT_EPV:
- /* Check CAN_ESR_EPVF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
- break;
- case CAN_IT_BOF:
- /* Check CAN_ESR_BOFF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
- break;
- case CAN_IT_LEC:
- /* Check CAN_ESR_LEC bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
- break;
- case CAN_IT_ERR:
- /* Check CAN_MSR_ERRI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
- break;
- default:
- /* in case of error, return RESET */
- itstatus = RESET;
- break;
- }
- }
- else
- {
- /* in case the Interrupt is not enabled, return RESET */
- itstatus = RESET;
- }
-
- /* Return the CAN_IT status */
- return itstatus;
-}
-
-/**
- * @brief Clears the CANx's interrupt pending bits.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @retval None
- */
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_IT(CAN_IT));
-
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Clear CAN_TSR_RQCPx (rc_w1)*/
- CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
- break;
- case CAN_IT_FF0:
- /* Clear CAN_RF0R_FULL0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FULL0;
- break;
- case CAN_IT_FOV0:
- /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FOVR0;
- break;
- case CAN_IT_FF1:
- /* Clear CAN_RF1R_FULL1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FULL1;
- break;
- case CAN_IT_FOV1:
- /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FOVR1;
- break;
- case CAN_IT_WKU:
- /* Clear CAN_MSR_WKUI (rc_w1)*/
- CANx->MSR = CAN_MSR_WKUI;
- break;
- case CAN_IT_SLK:
- /* Clear CAN_MSR_SLAKI (rc_w1)*/
- CANx->MSR = CAN_MSR_SLAKI;
- break;
- case CAN_IT_EWG:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_EPV:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_BOF:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_LEC:
- /* Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- break;
- case CAN_IT_ERR:
- /*Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
- break;
- default:
- break;
- }
-}
- /**
- * @}
- */
-
-/**
- * @brief Checks whether the CAN interrupt has occurred or not.
- * @param CAN_Reg: specifies the CAN interrupt register to check.
- * @param It_Bit: specifies the interrupt source bit to check.
- * @retval The new state of the CAN Interrupt (SET or RESET).
- */
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
-{
- ITStatus pendingbitstatus = RESET;
-
- if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
- {
- /* CAN_IT is set */
- pendingbitstatus = SET;
- }
- else
- {
- /* CAN_IT is reset */
- pendingbitstatus = RESET;
- }
- return pendingbitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_can.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,653 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_can.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the CAN firmware
- * library, applicable only for STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_CAN_H
-#define __STM32F0xx_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN))
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
- It ranges from 1 to 1024. */
-
- uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
- Segment 1. This parameter can be a value of
- @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_InitTypeDef;
-
-/**
- * @brief CAN filter init structure definition
- */
-typedef struct
-{
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
-
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_FilterInitTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be transmitted. This parameter can be a value
- of @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the message that will
- be transmitted. This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be
- transmitted. This parameter can be a value between
- 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
- to 0xFF. */
-} CanTxMsg;
-
-/**
- * @brief CAN Rx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be received. This parameter can be a value of
- @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter can be a value between 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
- 0xFF. */
-
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in
- the mailbox passes through. This parameter can be a
- value between 0 to 0xFF */
-} CanRxMsg;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants
- * @{
- */
-
-/** @defgroup CAN_InitStatus
- * @{
- */
-
-#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
-
-
-/* Legacy defines */
-#define CANINITFAILED CAN_InitStatus_Failed
-#define CANINITOK CAN_InitStatus_Success
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode
- * @{
- */
-
-#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
-#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
-#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
-#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
- ((MODE) == CAN_Mode_LoopBack)|| \
- ((MODE) == CAN_Mode_Silent) || \
- ((MODE) == CAN_Mode_Silent_LoopBack))
-/**
- * @}
- */
-
-
- /**
- * @defgroup CAN_operating_mode
- * @{
- */
-#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
-#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
-#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
-
-
-#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
- ((MODE) == CAN_OperatingMode_Normal)|| \
- ((MODE) == CAN_OperatingMode_Sleep))
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_operating_mode_status
- * @{
- */
-
-#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
-#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
-/**
- * @}
- */
-
-/** @defgroup CAN_synchronisation_jump_width
- * @{
- */
-#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
- ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1
- * @{
- */
-#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
-#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
-#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
-#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
-#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
-#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
-#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
-#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2
- * @{
- */
-#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_clock_prescaler
- * @{
- */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number
- * @{
- */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode
- * @{
- */
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
-#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
- ((MODE) == CAN_FilterMode_IdList))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale
- * @{
- */
-#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
- ((SCALE) == CAN_FilterScale_32bit))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO
- * @{
- */
-#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
- ((FIFO) == CAN_FilterFIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0 CAN_Filter_FIFO0
-#define CAN_FilterFIFO1 CAN_Filter_FIFO1
-/**
- * @}
- */
-
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN
- * @{
- */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
-/**
- * @}
- */
-
-/** @defgroup CAN_Tx
- * @{
- */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type
- * @{
- */
-#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
- ((IDTYPE) == CAN_Id_Extended))
-
-/* Legacy defines */
-#define CAN_ID_STD CAN_Id_Standard
-#define CAN_ID_EXT CAN_Id_Extended
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request
- * @{
- */
-#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
-
-/* Legacy defines */
-#define CAN_RTR_DATA CAN_RTR_Data
-#define CAN_RTR_REMOTE CAN_RTR_Remote
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants
- * @{
- */
-#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
-#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
- an empty mailbox */
-/* Legacy defines */
-#define CANTXFAILED CAN_TxStatus_Failed
-#define CANTXOK CAN_TxStatus_Ok
-#define CANTXPENDING CAN_TxStatus_Pending
-#define CAN_NO_MB CAN_TxStatus_NoMailBox
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-/**
- * @}
- */
-
-/** @defgroup CAN_sleep_constants
- * @{
- */
-#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
-
-/* Legacy defines */
-#define CANSLEEPFAILED CAN_Sleep_Failed
-#define CANSLEEPOK CAN_Sleep_Ok
-/**
- * @}
- */
-
-/** @defgroup CAN_wake_up_constants
- * @{
- */
-#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
-
-/* Legacy defines */
-#define CANWAKEUPFAILED CAN_WakeUp_Failed
-#define CANWAKEUPOK CAN_WakeUp_Ok
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_Error_Code_constants
- * @{
- */
-#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
-#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
-#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
-#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
-#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
-#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
-#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
-#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
-#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
-#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
-#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
-#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
-#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
-#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
-#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
-#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
- ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_SLAK ))
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
-/**
- * @}
- */
-
-
-/** @defgroup CAN_interrupts
- * @{
- */
-#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
-#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
-#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
-
-/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
-#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
-#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
-#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
-#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the CAN configuration to the default reset state *****/
-void CAN_DeInit(CAN_TypeDef* CANx);
-
-/* Initialization and Configuration functions *********************************/
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
-
-/* CAN Frames Transmission functions ******************************************/
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
-
-/* CAN Frames Reception functions *********************************************/
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-
-/* Operation modes functions **************************************************/
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
-
-/* CAN Bus Error management functions *****************************************/
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
-
-/* Interrupts and flags management functions **********************************/
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0xx_CAN_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_cec.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,617 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_cec.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Consumer Electronics Control (CEC) peripheral
- * applicable only on STM32F051, STM32F042 and STM32F072 devices:
- * + Initialization and Configuration
- * + Data transfers functions
- * + Interrupts and flags management
- *
- * @verbatim
- ==============================================================================
- ##### CEC features #####
- ==============================================================================
- [..] This device provides some features:
- (#) Supports HDMI-CEC specification 1.4.
- (#) Supports two source clocks(HSI/244 or LSE).
- (#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
- It can genarate an interrupt in the CEC clock domain that the CPU
- wakes up from the low power mode.
- (#) Configurable Signal Free Time before of transmission start. The
- number of nominal data bit periods waited before transmission can be
- ruled by Hardware or Software.
- (#) Configurable Peripheral Address (multi-addressing configuration).
- (#) Supports listen mode.The CEC Messages addressed to different destination
- can be received without interfering with CEC bus when Listen mode option is enabled.
- (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
- (#) Error detection with configurable error bit generation.
- (#) Arbitration lost error in the case of two CEC devices starting at the same time.
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the CEC device,
- follow steps below:
- (#) The source clock can be configured using:
- (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default)
- (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
- (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
- (#) Peripherals alternate function.
- (++) Connect the pin to the desired peripherals' Alternate Function (AF) using
- GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type open-drain and output speed via GPIO_OType
- and GPIO_Speed members.
- (++) Call GPIO_Init() function.
- (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation
- and Bit error generation using the CEC_Init() function.
- The function CEC_Init() must be called when the CEC peripheral is disabled.
- (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
- (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
- (#) Enable the NVIC and the corresponding interrupt using the function
- CEC_ITConfig() if you need to use interrupt mode.
- CEC_ITConfig() must be called before enabling the CEC peripheral.
- (#) Enable the CEC using the CEC_Cmd() function.
- (#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
- (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage()
- (#) Transmit single data through the CEC peripheral using CEC_SendDataByte()
- and Receive the last transmitted byte using CEC_ReceiveDataByte().
- (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
- [..]
- (@) If the listen mode is enabled, Stop reception generation and Bit error generation
- must be in reset state.
- (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
- must be called before CEC_StartOfMessage().
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_cec.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CEC
- * @brief CEC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BROADCAST_ADDRESS ((uint32_t)0x0000F)
-#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CEC_Private_Functions
- * @{
- */
-
-/** @defgroup CEC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to initialize:
- (+) CEC own addresses
- (+) CEC Signal Free Time
- (+) CEC Rx Tolerance
- (+) CEC Stop Reception
- (+) CEC Bit Rising Error
- (+) CEC Long Bit Period Error
- [..] This section provides also a function to configure the CEC peripheral in Listen Mode.
- Messages addressed to different destination can be received when Listen mode is
- enabled without interfering with CEC bus.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the CEC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void CEC_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
-}
-
-/**
- * @brief Initializes the CEC peripheral according to the specified parameters
- * in the CEC_InitStruct.
- * @note The CEC parameters must be configured before enabling the CEC peripheral.
- * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains
- * the configuration information for the specified CEC peripheral.
- * @retval None
- */
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
- assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
- assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
- assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
- assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
- assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
- assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
-
- /* Get the CEC CFGR value */
- tmpreg = CEC->CFGR;
-
- /* Clear CFGR bits */
- tmpreg &= CFGR_CLEAR_MASK;
-
- /* Configure the CEC peripheral */
- tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
- CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError |
- CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |
- CEC_InitStruct->CEC_SFTOption);
-
- /* Write to CEC CFGR register */
- CEC->CFGR = tmpreg;
-}
-
-/**
- * @brief Fills each CEC_InitStruct member with its default value.
- * @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
-{
- CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
- CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
- CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
- CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
- CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
- CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
- CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
-}
-
-/**
- * @brief Enables or disables the CEC peripheral.
- * @param NewState: new state of the CEC peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_Cmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the CEC peripheral */
- CEC->CR |= CEC_CR_CECEN;
- }
- else
- {
- /* Disable the CEC peripheral */
- CEC->CR &= ~CEC_CR_CECEN;
- }
-}
-
-/**
- * @brief Enables or disables the CEC Listen Mode.
- * @param NewState: new state of the Listen Mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_ListenModeCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Listen Mode */
- CEC->CFGR |= CEC_CFGR_LSTN;
- }
- else
- {
- /* Disable the Listen Mode */
- CEC->CFGR &= ~CEC_CFGR_LSTN;
- }
-}
-
-/**
- * @brief Defines the Own Address of the CEC device.
- * @param CEC_OwnAddress: The CEC own address.
- * @retval None
- */
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
-{
- uint32_t tmp =0x00;
- /* Check the parameters */
- assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
- tmp = 1 <<(CEC_OwnAddress + 16);
- /* Set the CEC own address */
- CEC->CFGR |= tmp;
-}
-
-/**
- * @brief Clears the Own Address of the CEC device.
- * @param CEC_OwnAddress: The CEC own address.
- * @retval None
- */
-void CEC_OwnAddressClear(void)
-{
- /* Set the CEC own address */
- CEC->CFGR = 0x0;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This section provides functions allowing the CEC data transfers.The read
- access of the CEC_RXDR register can be done using the CEC_ReceiveData()function
- and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be
- done using CEC_SendData() function.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the CEC peripheral.
- * @param Data: the data to transmit.
- * @retval None
- */
-void CEC_SendData(uint8_t Data)
-{
- /* Transmit Data */
- CEC->TXDR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the CEC peripheral.
- * @param None
- * @retval The received data.
- */
-uint8_t CEC_ReceiveData(void)
-{
- /* Receive Data */
- return (uint8_t)(CEC->RXDR);
-}
-
-/**
- * @brief Starts a new message.
- * @param None
- * @retval None
- */
-void CEC_StartOfMessage(void)
-{
- /* Starts of new message */
- CEC->CR |= CEC_CR_TXSOM;
-}
-
-/**
- * @brief Transmits message with an EOM bit.
- * @param None
- * @retval None
- */
-void CEC_EndOfMessage(void)
-{
- /* The data byte will be transmitted with an EOM bit */
- CEC->CR |= CEC_CR_TXEOM;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
-*
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the CEC Interrupts
- sources and check or clear the flags or pending bits status.
- [..] The user should identify which mode will be used in his application to manage
- the communication: Polling mode or Interrupt mode.
-
- [..] In polling mode, the CEC can be managed by the following flags:
- (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
- (+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode.
- The initiator detects low impedance in the CEC line.
- (+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode.
- The transmission is enabled while the software has not yet
- loaded any value into the TXDR register.
- (+) CEC_FLAG_TXEND : to indicate the end of successful transmission.
- (+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR.
- (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
- starting at the same time.
- (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
- (+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode.
- (+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode.
- (+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode.
- (+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
- A byte is not yet received while a new byte is stored in the RXDR register.
- (+) CEC_FLAG_RXEND : to indicate the end Of reception
- (+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and
- stored into the RXDR buffer.
- [..]
- (@)In this Mode, it is advised to use the following functions:
- FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
- void CEC_ClearFlag(uint16_t CEC_FLAG);
-
- [..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
- (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge
- (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
- (+) CEC_IT_TXERR : to indicate an error occurs during transmission mode.
- The initiator detects low impedance in the CEC line.
- (+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode.
- The transmission is enabled while the software has not yet
- loaded any value into the TXDR register.
- (+) CEC_IT_TXEND : to indicate the end of successful transmission.
- (+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register.
- (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
- starting at the same time.
- (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
- (+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode.
- (+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode.
- (+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode.
- (+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
- A byte is not yet received while a new byte is stored in the RXDR register.
- (+) CEC_IT_RXEND : to indicate the end Of reception
- (+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and
- stored into the RXDR buffer.
- [..]
- (@)In this Mode it is advised to use the following functions:
- void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
- ITStatus CEC_GetITStatus(uint16_t CEC_IT);
- void CEC_ClearITPendingBit(uint16_t CEC_IT);
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the selected CEC interrupts.
- * @param CEC_IT: specifies the CEC interrupt source to be enabled.
- * This parameter can be any combination of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error.
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
- * @arg CEC_IT_TXBR: Tx-Byte Request.
- * @arg CEC_IT_ARBLST: Arbitration Lost
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_IT_LBPE: Rx Long period Error
- * @arg CEC_IT_SBPE: Rx Short period Error
- * @arg CEC_IT_BRE: Rx Bit Rising Error
- * @arg CEC_IT_RXOVR: Rx Overrun.
- * @arg CEC_IT_RXEND: End Of Reception
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @param NewState: new state of the selected CEC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_CEC_IT(CEC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CEC interrupt */
- CEC->IER |= CEC_IT;
- }
- else
- {
- CEC_IT =~CEC_IT;
- /* Disable the selected CEC interrupt */
- CEC->IER &= CEC_IT;
- }
-}
-
-/**
- * @brief Gets the CEC flag status.
- * @param CEC_FLAG: specifies the CEC flag to check.
- * This parameter can be one of the following values:
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error.
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request.
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun.
- * @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval The new state of CEC_FLAG (SET or RESET)
- */
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
-
- /* Check the status of the specified CEC flag */
- if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
- {
- /* CEC flag is set */
- bitstatus = SET;
- }
- else
- {
- /* CEC flag is reset */
- bitstatus = RESET;
- }
-
- /* Return the CEC flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CEC's pending flags.
- * @param CEC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rising Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun
- * @arg CEC_FLAG_RXEND: End Of Reception
- * @arg CEC_FLAG_RXBR: Rx-Byte Received
- * @retval None
- */
-void CEC_ClearFlag(uint32_t CEC_FLAG)
-{
- assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
-
- /* Clear the selected CEC flag */
- CEC->ISR = CEC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified CEC interrupt has occurred or not.
- * @param CEC_IT: specifies the CEC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error.
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_IT_TXBR: Tx-Byte Request.
- * @arg CEC_IT_ARBLST: Arbitration Lost.
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
- * @arg CEC_IT_LBPE: Rx Long period Error.
- * @arg CEC_IT_SBPE: Rx Short period Error.
- * @arg CEC_IT_BRE: Rx Bit Rising Error.
- * @arg CEC_IT_RXOVR: Rx Overrun.
- * @arg CEC_IT_RXEND: End Of Reception.
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @retval The new state of CEC_IT (SET or RESET).
- */
-ITStatus CEC_GetITStatus(uint16_t CEC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_GET_IT(CEC_IT));
-
- /* Get the CEC IT enable bit status */
- enablestatus = (CEC->IER & CEC_IT);
-
- /* Check the status of the specified CEC interrupt */
- if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* CEC interrupt is set */
- bitstatus = SET;
- }
- else
- {
- /* CEC interrupt is reset */
- bitstatus = RESET;
- }
-
- /* Return the CEC interrupt status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CEC's interrupt pending bits.
- * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun
- * @arg CEC_IT_TXEND: End of Transmission
- * @arg CEC_IT_TXBR: Tx-Byte Request
- * @arg CEC_IT_ARBLST: Arbitration Lost
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_IT_LBPE: Rx Long period Error
- * @arg CEC_IT_SBPE: Rx Short period Error
- * @arg CEC_IT_BRE: Rx Bit Rising Error
- * @arg CEC_IT_RXOVR: Rx Overrun
- * @arg CEC_IT_RXEND: End Of Reception
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @retval None
- */
-void CEC_ClearITPendingBit(uint16_t CEC_IT)
-{
- assert_param(IS_CEC_IT(CEC_IT));
-
- /* Clear the selected CEC interrupt pending bits */
- CEC->ISR = CEC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_cec.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,310 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_cec.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the CEC firmware
- * library, applicable only for STM32F051, STM32F042 and STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CEC_H
-#define __STM32F0XX_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CEC
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief CEC Init structure definition
- */
-typedef struct
-{
- uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration.
- This parameter can be a value of @ref CEC_Signal_Free_Time */
- uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance.
- This parameter can be a value of @ref CEC_RxTolerance */
- uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception.
- This parameter can be a value of @ref CEC_Stop_Reception */
- uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation.
- This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
- uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
- This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
- uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation.
- This parameter can be a value of @ref CEC_BDR_No_Gen */
- uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option.
- This parameter can be a value of @ref CEC_SFT_Option */
-
-}CEC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CEC_Exported_Constants
- * @{
- */
-
-/** @defgroup CEC_Signal_Free_Time
- * @{
- */
-#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */
-#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */
-#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */
-#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */
-#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */
-#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */
-#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */
-#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */
-
-#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
- ((TIME) == CEC_SignalFreeTime_1T)|| \
- ((TIME) == CEC_SignalFreeTime_2T)|| \
- ((TIME) == CEC_SignalFreeTime_3T)|| \
- ((TIME) == CEC_SignalFreeTime_4T)|| \
- ((TIME) == CEC_SignalFreeTime_5T)|| \
- ((TIME) == CEC_SignalFreeTime_6T)|| \
- ((TIME) == CEC_SignalFreeTime_7T))
-/**
- * @}
- */
-
-/** @defgroup CEC_RxTolerance
- * @{
- */
-#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */
-#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */
-
-#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
- ((TOLERANCE) == CEC_RxTolerance_Extended))
-/**
- * @}
- */
-
-/** @defgroup CEC_Stop_Reception
- * @{
- */
-#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
-#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */
-
-#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
- ((RECEPTION) == CEC_StopReception_Off))
-/**
- * @}
- */
-
-/** @defgroup CEC_Bit_Rising_Error_Generation
- * @{
- */
-#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
-#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */
-
-#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
- ((ERROR) == CEC_BitRisingError_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_Long_Bit_Error_Generation
- * @{
- */
-#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */
-#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */
-
-#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
- ((ERROR) == CEC_LongBitPeriodError_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_BDR_No_Gen
- * @{
- */
-
-#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */
-#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */
-
-#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
- ((ERROR) == CEC_BRDNoGen_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_SFT_Option
- * @{
- */
-#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */
-#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */
-
-#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
- ((OPTION) == CEC_SFTOption_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_Own_Address
- * @{
- */
-#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Interrupt_Configuration_definition
- * @{
- */
-#define CEC_IT_TXACKE CEC_IER_TXACKEIE
-#define CEC_IT_TXERR CEC_IER_TXERRIE
-#define CEC_IT_TXUDR CEC_IER_TXUDRIE
-#define CEC_IT_TXEND CEC_IER_TXENDIE
-#define CEC_IT_TXBR CEC_IER_TXBRIE
-#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
-#define CEC_IT_RXACKE CEC_IER_RXACKEIE
-#define CEC_IT_LBPE CEC_IER_LBPEIE
-#define CEC_IT_SBPE CEC_IER_SBPEIE
-#define CEC_IT_BRE CEC_IER_BREIEIE
-#define CEC_IT_RXOVR CEC_IER_RXOVRIE
-#define CEC_IT_RXEND CEC_IER_RXENDIE
-#define CEC_IT_RXBR CEC_IER_RXBRIE
-
-#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
-
-#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
- ((IT) == CEC_IT_TXERR)|| \
- ((IT) == CEC_IT_TXUDR)|| \
- ((IT) == CEC_IT_TXEND)|| \
- ((IT) == CEC_IT_TXBR)|| \
- ((IT) == CEC_IT_ARBLST)|| \
- ((IT) == CEC_IT_RXACKE)|| \
- ((IT) == CEC_IT_LBPE)|| \
- ((IT) == CEC_IT_SBPE)|| \
- ((IT) == CEC_IT_BRE)|| \
- ((IT) == CEC_IT_RXOVR)|| \
- ((IT) == CEC_IT_RXEND)|| \
- ((IT) == CEC_IT_RXBR))
-/**
- * @}
- */
-
-/** @defgroup CEC_ISR_register_flags_definition
- * @{
- */
-#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
-#define CEC_FLAG_TXERR CEC_ISR_TXERR
-#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
-#define CEC_FLAG_TXEND CEC_ISR_TXEND
-#define CEC_FLAG_TXBR CEC_ISR_TXBR
-#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
-#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
-#define CEC_FLAG_LBPE CEC_ISR_LBPE
-#define CEC_FLAG_SBPE CEC_ISR_SBPE
-#define CEC_FLAG_BRE CEC_ISR_BRE
-#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
-#define CEC_FLAG_RXEND CEC_ISR_RXEND
-#define CEC_FLAG_RXBR CEC_ISR_RXBR
-
-#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
- ((FLAG) == CEC_FLAG_TXERR)|| \
- ((FLAG) == CEC_FLAG_TXUDR)|| \
- ((FLAG) == CEC_FLAG_TXEND)|| \
- ((FLAG) == CEC_FLAG_TXBR)|| \
- ((FLAG) == CEC_FLAG_ARBLST)|| \
- ((FLAG) == CEC_FLAG_RXACKE)|| \
- ((FLAG) == CEC_FLAG_LBPE)|| \
- ((FLAG) == CEC_FLAG_SBPE)|| \
- ((FLAG) == CEC_FLAG_BRE)|| \
- ((FLAG) == CEC_FLAG_RXOVR)|| \
- ((FLAG) == CEC_FLAG_RXEND)|| \
- ((FLAG) == CEC_FLAG_RXBR))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the CEC configuration to the default reset state *****/
-void CEC_DeInit(void);
-
-/* CEC_Initialization and Configuration functions *****************************/
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_Cmd(FunctionalState NewState);
-void CEC_ListenModeCmd(FunctionalState NewState);
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
-void CEC_OwnAddressClear(void);
-
-/* CEC_Data transfers functions ***********************************************/
-void CEC_SendData(uint8_t Data);
-uint8_t CEC_ReceiveData(void);
-void CEC_StartOfMessage(void);
-void CEC_EndOfMessage(void);
-
-/* CEC_Interrupts and flags management functions ******************************/
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
-void CEC_ClearFlag(uint32_t CEC_FLAG);
-ITStatus CEC_GetITStatus(uint16_t CEC_IT);
-void CEC_ClearITPendingBit(uint16_t CEC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_CEC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_comp.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,418 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_comp.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the comparators (COMP1 and COMP2) peripheral
- * applicable only on STM32F051 and STM32F072 devices:
- * + Comparators configuration
- * + Window mode control
- *
- * @verbatim
- *
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
-
- The device integrates two analog comparators COMP1 and COMP2:
- (+) The non inverting input is set to PA1 for COMP1 and to PA3
- for COMP2.
-
- (+) The inverting input can be selected among: DAC1_OUT, DAC2_OUT
- 1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,
- I/O (PA0 for COMP1 and PA2 for COMP2)
-
- (+) The COMP output is internally is available using COMP_GetOutputLevel()
- and can be set on GPIO pins: PA0, PA6, PA11 for COMP1
- and PA2, PA7, PA12 for COMP2
-
- (+) The COMP output can be redirected to embedded timers (TIM1, TIM2
- and TIM3)
-
- (+) The two comparators COMP1 and COMP2 can be combined in window
- mode and only COMP1 non inverting (PA1) can be used as non-
- inverting input.
-
- (+) The two comparators COMP1 and COMP2 have interrupt capability
- with wake-up from Sleep and Stop modes (through the EXTI controller).
- COMP1 and COMP2 outputs are internally connected to EXTI Line 21
- and EXTI Line 22 respectively.
-
-
- ##### How to configure the comparator #####
- ===============================================================================
- [..]
- This driver provides functions to configure and program the Comparators
- of all STM32F0xx devices.
-
- [..] To use the comparator, perform the following steps:
-
- (#) Enable the SYSCFG APB clock to get write access to comparator
- register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- (#) Configure the comparator input in analog mode using GPIO_Init()
-
- (#) Configure the comparator output in alternate function mode
- using GPIO_Init() and use GPIO_PinAFConfig() function to map the
- comparator output to the GPIO pin
-
- (#) Configure the comparator using COMP_Init() function:
- (++) Select the inverting input
- (++) Select the output polarity
- (++) Select the output redirection
- (++) Select the hysteresis level
- (++) Select the power mode
-
- (#) Enable the comparator using COMP_Cmd() function
-
- (#) If required enable the COMP interrupt by configuring and enabling
- EXTI line in Interrupt mode and selecting the desired sensitivity
- level using EXTI_Init() function. After that enable the comparator
- interrupt vector using NVIC_Init() function.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_comp.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup COMP
- * @brief COMP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CSR register Mask */
-#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00003FFE)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup COMP_Private_Functions
- * @{
- */
-
-/** @defgroup COMP_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes COMP peripheral registers to their default reset values.
- * @note Deinitialization can't be performed if the COMP configuration is locked.
- * To unlock the configuration, perform a system reset.
- * @param None
- * @retval None
- */
-void COMP_DeInit(void)
-{
- COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */
-}
-
-/**
- * @brief Initializes the COMP peripheral according to the specified parameters
- * in COMP_InitStruct
- * @note If the selected comparator is locked, initialization can't be performed.
- * To unlock the configuration, perform a system reset.
- * @note By default, PA1 is selected as COMP1 non inverting input.
- * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
- * @param COMP_Selection: the selected comparator.
- * This parameter can be one of the following values:
- * @arg COMP_Selection_COMP1: COMP1 selected
- * @arg COMP_Selection_COMP2: COMP2 selected
- * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
- * the configuration information for the specified COMP peripheral.
- * @retval None
- */
-void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
- assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
- assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
- assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
- assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
- assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
-
- /*!< Get the COMP_CSR register value */
- tmpreg = COMP->CSR;
-
- /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */
- tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<<COMP_Selection);
-
- /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
- /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
- /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
- /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
- /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
- /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
- tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output |
- COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis |
- COMP_InitStruct->COMP_Mode)<<COMP_Selection);
-
- /*!< Write to COMP_CSR register */
- COMP->CSR = tmpreg;
-}
-
-/**
- * @brief Fills each COMP_InitStruct member with its default value.
- * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
-{
- COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
- COMP_InitStruct->COMP_Output = COMP_Output_None;
- COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
- COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
- COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
-}
-
-/**
- * @brief Enable or disable the COMP peripheral.
- * @note If the selected comparator is locked, enable/disable can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param COMP_Selection: the selected comparator.
- * This parameter can be one of the following values:
- * @arg COMP_Selection_COMP1: COMP1 selected
- * @arg COMP_Selection_COMP2: COMP2 selected
- * @param NewState: new state of the COMP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @note When enabled, the comparator compares the non inverting input with
- * the inverting input and the comparison result is available on comparator output.
- * @note When disabled, the comparator doesn't perform comparison and the
- * output level is low.
- * @retval None
- */
-void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected COMP peripheral */
- COMP->CSR |= (uint32_t) (1<<COMP_Selection);
- }
- else
- {
- /* Disable the selected COMP peripheral */
- COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
- }
-}
-
-/**
- * @brief Close or Open the SW1 switch.
- * @note This switch is solely intended to redirect signals onto high
- * impedance input, such as COMP1 non-inverting input (highly resistive switch)
- * @param NewState: New state of the analog switch.
- * This parameter can be: ENABLE or DISABLE.
- * @note When enabled, the SW1 is closed; PA1 is connected to PA4
- * @note When disabled, the SW1 switch is open; PA1 is disconnected from PA4
- * @retval None
- */
-void COMP_SwitchCmd(FunctionalState NewState)
-{
- /* Check the parameter */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Close SW1 switch */
- COMP->CSR |= (uint32_t) (COMP_CSR_COMP1SW1);
- }
- else
- {
- /* Open SW1 switch */
- COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1);
- }
-}
-
-/**
- * @brief Return the output level (high or low) of the selected comparator.
- * @note The output level depends on the selected polarity.
- * @note If the polarity is not inverted:
- * - Comparator output is low when the non-inverting input is at a lower
- * voltage than the inverting input
- * - Comparator output is high when the non-inverting input is at a higher
- * voltage than the inverting input
- * @note If the polarity is inverted:
- * - Comparator output is high when the non-inverting input is at a lower
- * voltage than the inverting input
- * - Comparator output is low when the non-inverting input is at a higher
- * voltage than the inverting input
- * @param COMP_Selection: the selected comparator.
- * This parameter can be one of the following values:
- * @arg COMP_Selection_COMP1: COMP1 selected
- * @arg COMP_Selection_COMP2: COMP2 selected
- * @retval Returns the selected comparator output level: low or high.
- *
- */
-uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
-{
- uint32_t compout = 0x0;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-
- /* Check if selected comparator output is high */
- if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0)
- {
- compout = COMP_OutputLevel_High;
- }
- else
- {
- compout = COMP_OutputLevel_Low;
- }
-
- /* Return the comparator output level */
- return (uint32_t)(compout);
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Group2 Window mode control function
- * @brief Window mode control function
- *
-@verbatim
- ===============================================================================
- ##### Window mode control function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the window mode.
- * @note In window mode, COMP1 and COMP2 non inverting inputs are connected
- * together and only COMP1 non inverting input (PA1) can be used.
- * @param NewState: new state of the window mode.
- * This parameter can be :
- * @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
- * @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
- * @retval None
- */
-void COMP_WindowCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the window mode */
- COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN;
- }
- else
- {
- /* Disable the window mode */
- COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Group3 COMP configuration locking function
- * @brief COMP1 and COMP2 configuration locking function
- * COMP1 and COMP2 configuration can be locked each separately.
- * Unlocking is performed by system reset.
- *
-@verbatim
- ===============================================================================
- ##### Configuration Lock function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Lock the selected comparator (COMP1/COMP2) configuration.
- * @note Locking the configuration means that all control bits are read-only.
- * To unlock the comparator configuration, perform a system reset.
- * @param COMP_Selection: selects the comparator to be locked
- * This parameter can be a value of the following values:
- * @arg COMP_Selection_COMP1: COMP1 configuration is locked.
- * @arg COMP_Selection_COMP2: COMP2 configuration is locked.
- * @retval None
- */
-void COMP_LockConfig(uint32_t COMP_Selection)
-{
- /* Check the parameter */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-
- /* Set the lock bit corresponding to selected comparator */
- COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<<COMP_Selection);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_comp.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,255 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_comp.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the COMP firmware
- * library, applicable only for STM32F051 and STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_COMP_H
-#define __STM32F0XX_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup COMP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief COMP Init structure definition
- */
-
-typedef struct
-{
-
- uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
- This parameter can be a value of @ref COMP_InvertingInput */
-
- uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
- This parameter can be a value of @ref COMP_Output */
-
- uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
- This parameter can be a value of @ref COMP_OutputPolarity */
-
- uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
- This parameter can be a value of @ref COMP_Hysteresis */
-
- uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
- and allows to adjust the speed/consumption.
- This parameter can be a value of @ref COMP_Mode */
-
-}COMP_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Constants
- * @{
- */
-
-/** @defgroup COMP_Selection
- * @{
- */
-
-#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
-#define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */
-
-#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
- ((PERIPH) == COMP_Selection_COMP2))
-
-/**
- * @}
- */
-
-/** @defgroup COMP_InvertingInput
- * @{
- */
-
-#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT (PA4) connected to comparator inverting input */
-#define COMP_InvertingInput_DAC2 ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input, applicable only for STM32F072 devices */
-#define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
-
-#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
- ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
- ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
- ((INPUT) == COMP_InvertingInput_VREFINT) || \
- ((INPUT) == COMP_InvertingInput_DAC1) || \
- ((INPUT) == COMP_InvertingInput_DAC2) || \
- ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
- ((INPUT) == COMP_InvertingInput_IO))
-/**
- * @}
- */
-
-/** @defgroup COMP_Output
- * @{
- */
-
-#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
-#define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
-#define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */
-#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */
-#define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */
-#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */
-#define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */
-#define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */
-
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
- ((OUTPUT) == COMP_Output_TIM1BKIN) || \
- ((OUTPUT) == COMP_Output_TIM1IC1) || \
- ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM2IC4) || \
- ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM3IC1) || \
- ((OUTPUT) == COMP_Output_TIM3OCREFCLR))
-/**
- * @}
- */
-
-/** @defgroup COMP_OutputPolarity
- * @{
- */
-#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
-#define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */
-
-#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
- ((POL) == COMP_OutputPol_Inverted))
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Hysteresis
- * @{
- */
-/* Please refer to the electrical characteristics in the device datasheet for
- the hysteresis level */
-#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
-#define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
-#define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
-#define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
- ((HYSTERESIS) == COMP_Hysteresis_Low) || \
- ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
- ((HYSTERESIS) == COMP_Hysteresis_High))
-/**
- * @}
- */
-
-/** @defgroup COMP_Mode
- * @{
- */
-/* Please refer to the electrical characteristics in the device datasheet for
- the power consumption values */
-#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
-#define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */
-#define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */
-#define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */
-
-#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
- ((MODE) == COMP_Mode_LowPower) || \
- ((MODE) == COMP_Mode_MediumSpeed) || \
- ((MODE) == COMP_Mode_HighSpeed))
-/**
- * @}
- */
-
-/** @defgroup COMP_OutputLevel
- * @{
- */
-/* When output polarity is not inverted, comparator output is high when
- the non-inverting input is at a higher voltage than the inverting input */
-#define COMP_OutputLevel_High COMP_CSR_COMP1OUT
-/* When output polarity is not inverted, comparator output is low when
- the non-inverting input is at a lower voltage than the inverting input*/
-#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the COMP configuration to the default reset state ****/
-void COMP_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
-void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
-void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
-void COMP_SwitchCmd(FunctionalState NewState);
-uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
-
-/* Window mode control function ***********************************************/
-void COMP_WindowCmd(FunctionalState NewState);
-
-/* COMP configuration locking function ****************************************/
-void COMP_LockConfig(uint32_t COMP_Selection);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_COMP_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_conf.h Tue Dec 02 15:15:06 2014 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,93 +0,0 @@ -/** - ****************************************************************************** - * @file Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_conf.h - * @author MCD Application Team - * @version V1.3.1 - * @date 17-January-2014 - * @brief Library configuration file. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_CONF_H -#define __STM32F0XX_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Comment the line below to disable peripheral header file inclusion */ -#include "stm32f0xx_adc.h" -#include "stm32f0xx_can.h" -#include "stm32f0xx_cec.h" -#include "stm32f0xx_crc.h" -#include "stm32f0xx_crs.h" -#include "stm32f0xx_comp.h" -#include "stm32f0xx_dac.h" -#include "stm32f0xx_dbgmcu.h" -#include "stm32f0xx_dma.h" -#include "stm32f0xx_exti.h" -#include "stm32f0xx_flash.h" -#include "stm32f0xx_gpio.h" -#include "stm32f0xx_syscfg.h" -#include "stm32f0xx_i2c.h" -#include "stm32f0xx_iwdg.h" -#include "stm32f0xx_pwr.h" -#include "stm32f0xx_rcc.h" -#include "stm32f0xx_rtc.h" -#include "stm32f0xx_spi.h" -#include "stm32f0xx_tim.h" -#include "stm32f0xx_usart.h" -#include "stm32f0xx_wwdg.h" -#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function which reports - * the name of the source file and the source line number of the call - * that failed. If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F0XX_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_crc.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,371 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_crc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of CRC computation unit peripheral:
- * + Configuration of the CRC computation unit
- * + CRC computation of one/many 32-bit data
- * + CRC Independent register (IDR) access
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
-
- (+) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
- function
- (+) If required, select the reverse operation on input data
- using CRC_ReverseInputDataSelect()
- (+) If required, enable the reverse operation on output data
- using CRC_ReverseOutputDataCmd(Enable)
- (+) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
- or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
- data buffer
- (@) To compute the CRC of a new data use CRC_ResetDR() to reset
- the CRC computation unit before starting the computation
- otherwise you can get wrong CRC values.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_crc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
- * @brief Configuration of the CRC computation unit functions
- *
-@verbatim
- ===============================================================================
- ##### CRC configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes CRC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void CRC_DeInit(void)
-{
- /* Set DR register to reset value */
- CRC->DR = 0xFFFFFFFF;
-
- /* Set the POL register to the reset value: 0x04C11DB7 */
- CRC->POL = 0x04C11DB7;
-
- /* Reset IDR register */
- CRC->IDR = 0x00;
-
- /* Set INIT register to reset value */
- CRC->INIT = 0xFFFFFFFF;
-
- /* Reset the CRC calculation unit */
- CRC->CR = CRC_CR_RESET;
-}
-
-/**
- * @brief Resets the CRC calculation unit and sets INIT register content in DR register.
- * @param None
- * @retval None
- */
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR |= CRC_CR_RESET;
-}
-
-/**
- * @brief Selects the polynomial size. This function is only applicable for
- * STM32F072 devices.
- * @param CRC_PolSize: Specifies the polynomial size.
- * This parameter can be:
- * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
- * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
- * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
- * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
- * @retval None
- */
-void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
-{
- uint32_t tmpcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
-
- /* Get CR register value */
- tmpcr = CRC->CR;
-
- /* Reset POL_SIZE bits */
- tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
- /* Set the polynomial size */
- tmpcr |= (uint32_t)CRC_PolSize;
-
- /* Write to CR register */
- CRC->CR = (uint32_t)tmpcr;
-}
-
-/**
- * @brief Selects the reverse operation to be performed on input data.
- * @param CRC_ReverseInputData: Specifies the reverse operation on input data.
- * This parameter can be:
- * @arg CRC_ReverseInputData_No: No reverse operation is performed
- * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
- * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
- * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
- * @retval None
- */
-void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
-{
- uint32_t tmpcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
-
- /* Get CR register value */
- tmpcr = CRC->CR;
-
- /* Reset REV_IN bits */
- tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
- /* Set the reverse operation */
- tmpcr |= (uint32_t)CRC_ReverseInputData;
-
- /* Write to CR register */
- CRC->CR = (uint32_t)tmpcr;
-}
-
-/**
- * @brief Enables or disable the reverse operation on output data.
- * The reverse operation on output data is performed on 32-bit.
- * @param NewState: new state of the reverse operation on output data.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRC_ReverseOutputDataCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable reverse operation on output data */
- CRC->CR |= CRC_CR_REV_OUT;
- }
- else
- {
- /* Disable reverse operation on output data */
- CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
- }
-}
-
-/**
- * @brief Initializes the INIT register.
- * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
- * @param CRC_InitValue: Programmable initial CRC value
- * @retval None
- */
-void CRC_SetInitRegister(uint32_t CRC_InitValue)
-{
- CRC->INIT = CRC_InitValue;
-}
-
-/**
- * @brief Initializes the polynomail coefficients. This function is only
- * applicable for STM32F072 devices.
- * @param CRC_Pol: Polynomial to be used for CRC calculation.
- * @retval None
- */
-void CRC_SetPolynomial(uint32_t CRC_Pol)
-{
- CRC->POL = CRC_Pol;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
- * @brief CRC computation of one/many 32-bit data functions
- *
-@verbatim
- ===============================================================================
- ##### CRC computation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Computes the 32-bit CRC of a given data word(32-bit).
- * @param CRC_Data: data word(32-bit) to compute its CRC
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcCRC(uint32_t CRC_Data)
-{
- CRC->DR = CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 16-bit CRC of a given 16-bit data. This function is only
- * applicable for STM32F072 devices.
- * @param CRC_Data: data half-word(16-bit) to compute its CRC
- * @retval 16-bit CRC
- */
-uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
-{
- *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 8-bit CRC of a given 8-bit data. This function is only
- * applicable for STM32F072 devices.
- * @param CRC_Data: 8-bit data to compute its CRC
- * @retval 8-bit CRC
- */
-uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
-{
- *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
- return (CRC->DR);
-}
-
-/**
- * @brief Returns the current CRC value.
- * @param None
- * @retval 32-bit CRC
- */
-uint32_t CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
- * @brief CRC Independent Register (IDR) access (write/read) functions
- *
-@verbatim
- ===============================================================================
- ##### CRC Independent Register (IDR) access functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Stores an 8-bit data in the Independent Data(ID) register.
- * @param CRC_IDValue: 8-bit value to be stored in the ID register
- * @retval None
- */
-void CRC_SetIDRegister(uint8_t CRC_IDValue)
-{
- CRC->IDR = CRC_IDValue;
-}
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register
- * @param None
- * @retval 8-bit value of the ID register
- */
-uint8_t CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_crc.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,132 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_crc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the CRC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CRC_H
-#define __STM32F0XX_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ----------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRC_ReverseInputData
- * @{
- */
-#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
-#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
-#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
-#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
-
-#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
- ((DATA) == CRC_ReverseInputData_8bits) || \
- ((DATA) == CRC_ReverseInputData_16bits) || \
- ((DATA) == CRC_ReverseInputData_32bits))
-
-/**
- * @}
- */
-
-/** @defgroup CRC_PolynomialSize
- * @brief Only applicable for STM32F042 and STM32F072 devices
- * @{
- */
-#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
-#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
-#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
-#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
-
-#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
- ((SIZE) == CRC_PolSize_8) || \
- ((SIZE) == CRC_PolSize_16) || \
- ((SIZE) == CRC_PolSize_32))
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Configuration of the CRC computation unit **********************************/
-void CRC_DeInit(void);
-void CRC_ResetDR(void);
-void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for STM32F042 and STM32F072 devices */
-void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
-void CRC_ReverseOutputDataCmd(FunctionalState NewState);
-void CRC_SetInitRegister(uint32_t CRC_InitValue);
-void CRC_SetPolynomial(uint32_t CRC_Pol); /*!< Only applicable for STM32F042 and STM32F072 devices */
-
-/* CRC computation ************************************************************/
-uint32_t CRC_CalcCRC(uint32_t CRC_Data);
-uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */
-uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-
-/* Independent register (IDR) access (write/read) *****************************/
-void CRC_SetIDRegister(uint8_t CRC_IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_CRC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_crs.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,476 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_crs.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of CRS peripheral applicable only on STM32F042 and
- * STM32F072 devices:
- * + Configuration of the CRS peripheral
- * + Interrupts and flags management
- *
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
-
- (+) Enable CRS AHB clock using RCC_APB1eriphClockCmd(RCC_APB1Periph_CRS, ENABLE)
- function
-
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_crs.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRS
- * @brief CRS driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CRS Flag Mask */
-#define FLAG_MASK ((uint32_t)0x700)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRS_Private_Functions
- * @{
- */
-
-/** @defgroup CRS_Group1 Configuration of the CRS functions
- * @brief Configuration of the CRS functions
- *
-@verbatim
- ===============================================================================
- ##### CRS configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes CRS peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void CRS_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, DISABLE);
-}
-
-/**
- * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI48 RC.
- * @note This function can be called only when the AUTOTRIMEN bit is reset.
- * @param CRS_HSI48CalibrationValue:
- * @retval None
- */
-void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue)
-{
- /* Clear TRIM[5:0] bits */
- CRS->CR &= ~CRS_CR_TRIM;
-
- /* Set the TRIM[5:0] bits according to CRS_HSI48CalibrationValue value */
- CRS->CR |= (uint32_t)((uint32_t)CRS_HSI48CalibrationValue << 8);
-
-}
-
-/**
- * @brief Enables or disables the oscillator clock for frequency error counter.
- * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
- * @param NewState: new state of the frequency error counter.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRS_FrequencyErrorCounterCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- CRS->CR |= CRS_CR_CEN;
- }
- else
- {
- CRS->CR &= ~CRS_CR_CEN;
- }
-}
-
-/**
- * @brief Enables or disables the automatic hardware adjustement of TRIM bits.
- * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
- * @param NewState: new state of the automatic trimming.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRS_AutomaticCalibrationCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- CRS->CR |= CRS_CR_AUTOTRIMEN;
- }
-else
- {
- CRS->CR &= ~CRS_CR_AUTOTRIMEN;
- }
-}
-
-/**
- * @brief Generate the software synchronization event
- * @param None
- * @retval None
- */
-void CRS_SoftwareSynchronizationGenerate(void)
-{
- CRS->CR |= CRS_CR_SWSYNC;
-}
-
-/**
- * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI48 RC.
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_ReloadValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and .
- * @retval None
- */
-void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue)
-{
-
- /* Clear RELOAD[15:0] bits */
- CRS->CFGR &= ~CRS_CFGR_RELOAD;
-
- /* Set the RELOAD[15:0] bits according to CRS_ReloadValue value */
- CRS->CFGR |= (uint32_t)CRS_ReloadValue;
-
-}
-
-/**
- * @brief
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_ErrorLimitValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and .
- * @retval None
- */
-void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue)
-{
- /* Clear FELIM[7:0] bits */
- CRS->CFGR &= ~CRS_CFGR_FELIM;
-
- /* Set the FELIM[7:0] bits according to CRS_ErrorLimitValue value */
- CRS->CFGR |= (uint32_t)CRS_ErrorLimitValue;
-}
-
-/**
- * @brief
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_Prescaler: specifies the HSI calibration trimming value.
- * This parameter can be one of the following values:
- * @arg CRS_SYNC_Div1:
- * @arg CRS_SYNC_Div2:
- * @arg CRS_SYNC_Div4:
- * @arg CRS_SYNC_Div8:
- * @arg CRS_SYNC_Div16:
- * @arg CRS_SYNC_Div32:
- * @arg CRS_SYNC_Div64:
- * @arg CRS_SYNC_Div128:
- * @retval None
- */
-void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_CRS_SYNC_DIV(CRS_Prescaler));
-
- /* Clear SYNCDIV[2:0] bits */
- CRS->CFGR &= ~CRS_CFGR_SYNCDIV;
-
- /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to CRS_Prescaler value */
- CRS->CFGR |= CRS_Prescaler;
-}
-
-/**
- * @brief
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_Source: .
- * This parameter can be one of the following values:
- * @arg CRS_SYNCSource_GPIO:
- * @arg CRS_SYNCSource_LSE:
- * @arg CRS_SYNCSource_USB:
- * @retval None
- */
-void CRS_SynchronizationSourceConfig(uint32_t CRS_Source)
-{
- /* Check the parameters */
- assert_param(IS_CRS_SYNC_SOURCE(CRS_Source));
-
- /* Clear SYNCSRC[1:0] bits */
- CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
-
- /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
- CRS->CFGR |= CRS_Source;
-}
-
-/**
- * @brief
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_Polarity: .
- * This parameter can be one of the following values:
- * @arg CRS_SYNCPolarity_Rising:
- * @arg CRS_SYNCPolarity_Falling:
- * @retval None
- */
-void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity)
-{
- /* Check the parameters */
- assert_param(IS_CRS_SYNC_POLARITY(CRS_Polarity));
-
- /* Clear SYNCSPOL bit */
- CRS->CFGR &= ~CRS_CFGR_SYNCPOL;
-
- /* Set the SYNCSPOL bits according to CRS_Polarity value */
- CRS->CFGR |= CRS_Polarity;
-}
-
-/**
- * @brief Returns the Relaod value.
- * @param None
- * @retval The reload value
- */
-uint32_t CRS_GetReloadValue(void)
-{
- return ((uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD));
-}
-
-/**
- * @brief Returns the HSI48 Calibration value.
- * @param None
- * @retval The reload value
- */
-uint32_t CRS_GetHSI48CalibrationValue(void)
-{
- return (((uint32_t)(CRS->CR & CRS_CR_TRIM)) >> 8);
-}
-
-/**
- * @brief Returns the frequency error capture.
- * @param None
- * @retval The frequency error capture value
- */
-uint32_t CRS_GetFrequencyErrorValue(void)
-{
- return ((uint32_t)(CRS->ISR & CRS_ISR_FECAP));
-}
-
-/**
- * @brief Returns the frequency error direction.
- * @param None
- * @retval The frequency error direction. The returned value can be one
- * of the following values:
- * - 0x00: Up counting
- * - 0x8000: Down counting
- */
-uint32_t CRS_GetFrequencyErrorDirection(void)
-{
- return ((uint32_t)(CRS->ISR & CRS_ISR_FEDIR));
-}
-
-/** @defgroup CRS_Group2 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified CRS interrupts.
- * @param CRS_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRS_IT_SYNCOK:
- * @arg CRS_IT_SYNCWARN:
- * @arg CRS_IT_ERR:
- * @arg CRS_IT_ESYNC:
- * @param NewState: new state of the specified CRS interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRS_IT(CRS_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- CRS->CR |= CRS_IT;
- }
- else
- {
- CRS->CR &= ~CRS_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified CRS flag is set or not.
- * @param CRS_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CRS_FLAG_SYNCOK:
- * @arg CRS_FLAG_SYNCWARN:
- * @arg CRS_FLAG_ERR:
- * @arg CRS_FLAG_ESYNC:
- * @arg CRS_FLAG_TRIMOVF:
- * @arg CRS_FLAG_SYNCERR:
- * @arg CRS_FLAG_SYNCMISS:
- * @retval The new state of CRS_FLAG (SET or RESET).
- */
-FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_CRS_FLAG(CRS_FLAG));
-
- return ((FlagStatus)(CRS->ISR & CRS_FLAG));
-}
-
-/**
- * @brief Clears the CRS specified FLAG.
- * @param CRS_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CRS_FLAG_SYNCOK:
- * @arg CRS_FLAG_SYNCWARN:
- * @arg CRS_FLAG_ERR:
- * @arg CRS_FLAG_ESYNC:
- * @arg CRS_FLAG_TRIMOVF:
- * @arg CRS_FLAG_SYNCERR:
- * @arg CRS_FLAG_SYNCMISS:
- * @retval None
- */
-void CRS_ClearFlag(uint32_t CRS_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_CRS_FLAG(CRS_FLAG));
-
- if ((CRS_FLAG & FLAG_MASK)!= 0)
- {
- CRS->ICR |= CRS_ICR_ERRC;
- }
- else
- {
- CRS->ICR |= CRS_FLAG;
- }
-}
-
-/**
- * @brief Checks whether the specified CRS IT pending bit is set or not.
- * @param CRS_IT: specifies the IT pending bit to check.
- * This parameter can be one of the following values:
- * @arg CRS_IT_SYNCOK:
- * @arg CRS_IT_SYNCWARN:
- * @arg CRS_IT_ERR:
- * @arg CRS_IT_ESYNC:
- * @arg CRS_IT_TRIMOVF:
- * @arg CRS_IT_SYNCERR:
- * @arg CRS_IT_SYNCMISS:
- * @retval The new state of CRS_IT (SET or RESET).
- */
-ITStatus CRS_GetITStatus(uint32_t CRS_IT)
-{
- /* Check the parameters */
- assert_param(IS_CRS_GET_IT(CRS_IT));
-
- return ((ITStatus)(CRS->ISR & CRS_IT));
-}
-
-/**
- * @brief Clears the CRS specified IT pending bi.
- * @param CRS_FLAG: specifies the IT pending bi to clear.
- * This parameter can be one of the following values:
- * @arg CRS_IT_SYNCOK:
- * @arg CRS_IT_SYNCWARN:
- * @arg CRS_IT_ERR:
- * @arg CRS_IT_ESYNC:
- * @arg CRS_IT_TRIMOVF:
- * @arg CRS_IT_SYNCERR:
- * @arg CRS_IT_SYNCMISS:
- * @retval None
- */
-void CRS_ClearITPendingBit(uint32_t CRS_IT)
-{
- /* Check the parameters */
- assert_param(IS_CRS_CLEAR_IT(CRS_IT));
-
- if ((CRS_IT & FLAG_MASK)!= 0)
- {
- CRS->ICR |= CRS_ICR_ERRC;
- }
- else
- {
- CRS->ICR |= CRS_IT;
- }
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_crs.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,193 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_crs.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the CRS firmware
- * library, applicable only for STM32F042 and STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CRS_H
-#define __STM32F0XX_CRS_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ----------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRS
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRS_Interrupt_Sources
- * @{
- */
-#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
-#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
-#define CRS_IT_ERR CRS_ISR_ERRF /*!< error */
-#define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
-#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
-#define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
-#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
-
-#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
- ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC))
-
-#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
- ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \
- ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \
- ((IT) == CRS_IT_SYNCMISS))
-
-#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00)
-
-/**
- * @}
- */
-
-/** @defgroup CRS_Flags
- * @{
- */
-#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
-#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
-#define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */
-#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
-#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
-#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
-#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
-
-#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \
- ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \
- ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \
- ((FLAG) == CRS_FLAG_SYNCMISS))
-
-/**
- * @}
- */
-
-/** @defgroup CRS_Synchro_Source
- * @{
- */
-#define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
-#define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
-#define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */
-
-#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \
- ((SOURCE) == CRS_SYNCSource_LSE) ||\
- ((SOURCE) == CRS_SYNCSource_USB))
-/**
- * @}
- */
-
-/** @defgroup CRS_SynchroDivider
- * @{
- */
-#define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */
-#define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
-#define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
-#define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
-#define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
-#define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
-#define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
-#define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-
-#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\
- ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \
- ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \
- ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128))
-/**
- * @}
- */
-
-/** @defgroup CRS_SynchroPolarity
- * @{
- */
-#define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */
-#define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-
-#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \
- ((POLARITY) == CRS_SYNCPolarity_Falling))
-/**
- * @}
- */
-
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Configuration of the CRS **********************************/
-void CRS_DeInit(void);
-void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue);
-void CRS_FrequencyErrorCounterCmd(FunctionalState NewState);
-void CRS_AutomaticCalibrationCmd(FunctionalState NewState);
-void CRS_SoftwareSynchronizationGenerate(void);
-void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue);
-void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue);
-void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler);
-void CRS_SynchronizationSourceConfig(uint32_t CRS_Source);
-void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity);
-uint32_t CRS_GetReloadValue(void);
-uint32_t CRS_GetHSI48CalibrationValue(void);
-uint32_t CRS_GetFrequencyErrorValue(void);
-uint32_t CRS_GetFrequencyErrorDirection(void);
-
-/* Interrupts and flags management functions **********************************/
-void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState);
-FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG);
-void CRS_ClearFlag(uint32_t CRS_FLAG);
-ITStatus CRS_GetITStatus(uint32_t CRS_IT);
-void CRS_ClearITPendingBit(uint32_t CRS_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_CRS_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_dac.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,702 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dac.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Digital-to-Analog Converter (DAC) peripheral
- * applicable only on STM32F051 and STM32F072 devices:
- * + DAC channel configuration: trigger, output buffer, data format
- * + DMA management
- * + Interrupts and flags management
- *
- * @verbatim
- *
- ===============================================================================
- ##### DAC Peripheral features #####
- ===============================================================================
- [..] The device integrates two 12-bit Digital Analog Converters refered as
- DAC channel1 with DAC_OUT1 (PA4) and DAC_OUT2 (PA5) as outputs.
-
- [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
- and DAC_OUTx is available once writing to DHRx register using
- DAC_SetChannel1Data() or DAC_SetChannel2Data()
-
- [..] Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
- The used pin (GPIOx_Pin9) must be configured in input mode.
-
- (#) Timers TRGO: TIM2, TIM3,TIM7, TIM6 and TIM15
- (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...)
- The timer TRGO event should be selected using TIM_SelectOutputTrigger()
-
- (#) Software using DAC_Trigger_Software
-
- [..] Each DAC integrates an output buffer that can be used to
- reduce the output impedance, and to drive external loads directly
- without having to add an external operational amplifier.
- To enable the output buffer use
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-
- [..] Refer to the device datasheet for more details about output impedance
- value with and without output buffer.
-
- [..] DAC wave generation feature
- Both DAC channels can be used to generate
- 1- Noise wave using DAC_WaveGeneration_Noise
- 2- Triangle wave using DAC_WaveGeneration_Triangle
-
- [..] The DAC data format can be:
- (#) 8-bit right alignment using DAC_Align_8b_R
- (#) 12-bit left alignment using DAC_Align_12b_L
- (#) 12-bit right alignment using DAC_Align_12b_R
-
- [..] The analog output voltage on each DAC channel pin is determined
- by the following equation: DAC_OUTx = VREF+ * DOR / 4095
- with DOR is the Data Output Register
- VEF+ is the input voltage reference (refer to the device datasheet)
- e.g. To set DAC_OUT1 to 0.7V, use
- DAC_SetChannel1Data(DAC_Align_12b_R, 868);
- Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
- [..] A DMA1 request can be generated when an external trigger (but not
- a software trigger) occurs if DMA1 requests are enabled using
- DAC_DMACmd()
- DMA1 requests are mapped as following:
- (+) DAC channel1 is mapped on DMA1 channel3 which must be already
- configured
- (+) DAC channel2 is mapped on DMA1 channel4 which must be already
- configured
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (+) Enable DAC APB1 clock to get write access to DAC registers
- using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
-
- (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode
- using GPIO_Init() function
-
- (+) Configure the DAC channel using DAC_Init()
-
- (+) Enable the DAC channel using DAC_Cmd()
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dac.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DAC
- * @brief DAC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) /* check the value of the mask */
-
-/* DAC Dual Channels SWTRIG masks */
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) /*!< Only applicable for STM32F072 devices */
-#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /*!< Only applicable for STM32F072 devices */
-
-/* DHR registers offsets */
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)
-#define DHR12R2_OFFSET ((uint32_t)0x00000014) /*!< Only applicable for STM32F072 devices */
-#define DHR12RD_OFFSET ((uint32_t)0x00000020) /*!< Only applicable for STM32F072 devices */
-
-/* DOR register offset */
-#define DOR_OFFSET ((uint32_t)0x0000002C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Functions
- * @{
- */
-
-/** @defgroup DAC_Group1 DAC channels configuration
- * @brief DAC channels configuration: trigger, output buffer, data format
- *
-@verbatim
- ===============================================================================
- ##### DAC channels configuration: trigger, output buffer, data format #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DAC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void DAC_DeInit(void)
-{
- /* Enable DAC reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
- /* Release DAC from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
-}
-
-/**
- * @brief Initializes the DAC peripheral according to the specified parameters
- * in the DAC_InitStruct.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
- * the configuration information for the specified DAC channel.
- * @retval None
- */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
-
-/*---------------------------- DAC CR Configuration --------------------------*/
- /* Get the DAC CR value */
- tmpreg1 = DAC->CR;
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
- /* Configure for the selected DAC channel: buffer output, trigger,
- wave generation, mask/amplitude for wave generation */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set WAVEx bits according to DAC_WaveGeneration value */
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
- /* Set BOFFx bit according to DAC_OutputBuffer value */
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
- DAC_InitStruct->DAC_OutputBuffer);
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << DAC_Channel;
- /* Write to DAC CR */
- DAC->CR = tmpreg1;
-}
-
-/**
- * @brief Fills each DAC_InitStruct member with its default value.
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
- /* Initialize the DAC_Trigger member */
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
-
- /* Initialize the DAC_WaveGeneration member */
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
-
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
-
- /* Initialize the DAC_OutputBuffer member */
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-}
-
-/**
- * @brief Enables or disables the specified DAC channel.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param NewState: new state of the DAC channel.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the DAC channel is enabled the trigger source can no more be modified.
- * @retval None
- */
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel */
- DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel */
- DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel software trigger.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param NewState: new state of the selected DAC channel software trigger.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for the selected DAC channel */
- DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
- }
- else
- {
- /* Disable software trigger for the selected DAC channel */
- DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
- }
-}
-
-/**
- * @brief Enables or disables simultaneously the two DAC channels software triggers.
- * This function is applicable only for STM32F072 devices.
- * @param NewState: new state of the DAC channels software triggers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for both DAC channels */
- DAC->SWTRIGR |= DUAL_SWTRIG_SET;
- }
- else
- {
- /* Disable software trigger for both DAC channels */
- DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * This function is applicable only for STM32F072 devices.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_Wave: specifies the wave type to enable or disable.
- * This parameter can be:
- * @arg DAC_Wave_Noise: noise wave generation
- * @arg DAC_Wave_Triangle: triangle wave generation
- * @param NewState: new state of the selected DAC channel wave generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_WAVE(DAC_Wave));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected wave generation for the selected DAC channel */
- DAC->CR |= DAC_Wave << DAC_Channel;
- }
- else
- {
- /* Disable the selected wave generation for the selected DAC channel */
- DAC->CR &= ~(DAC_Wave << DAC_Channel);
- }
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel1.
- * @param DAC_Align: Specifies the data alignment for DAC channel1.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R1_OFFSET + DAC_Align;
-
- /* Set the DAC channel1 selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-}
-
-/**
- * @brief Sets the specified data holding register value for DAC channel2.
- * This function is applicable only for STM32F072 devices.
- * @param DAC_Align: Specifies the data alignment for DAC channel2.
- * This parameter can be:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R2_OFFSET + DAC_Align;
-
- /* Set the DAC channel2 selected data holding register */
- *(__IO uint32_t *)tmp = Data;
-}
-
-/**
- * @brief Sets the specified data holding register value for dual channel DAC.
- * This function is applicable only for STM32F072 devices.
- * @param DAC_Align: Specifies the data alignment for dual channel DAC.
- * This parameter can be:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval None
- */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
-{
- uint32_t data = 0, tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (DAC_Align == DAC_Align_8b_R)
- {
- data = ((uint32_t)Data2 << 8) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16) | Data1;
- }
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12RD_OFFSET + DAC_Align;
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @retval The selected DAC channel data output value.
- */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
-
- tmp = (uint32_t) DAC_BASE ;
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-
- /* Returns the DAC channel data output register value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Group2 DMA management functions
- * @brief DMA management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC channel DMA request.
- * When enabled DMA1 is generated when an external trigger (EXTI Line9,
- * TIM2, TIM3, TIM6 or TIM15 but not a software trigger) occurs
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param NewState: new state of the selected DAC channel DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @note The DAC channel1 is mapped on DMA1 channel3 which must be already configured.
- * @note The DAC channel2 is mapped on DMA1 channel4 which must be already configured.
- * @retval None
- */
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel DMA request */
- DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel DMA request */
- DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC interrupts.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @param NewState: new state of the specified DAC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_DAC_IT(DAC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC interrupts */
- DAC->CR |= (DAC_IT << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC interrupts */
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
- }
-}
-
-/**
- * @brief Checks whether the specified DAC flag is set or not.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_FLAG: specifies the flag to check.
- * This parameter can be only of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_FLAG (SET or RESET).
- */
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Check the status of the specified DAC flag */
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
- {
- /* DAC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's pending flags.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_FLAG: specifies the flag to clear.
- * This parameter can be of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @retval None
- */
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Clear the selected DAC flags */
- DAC->SR = (DAC_FLAG << DAC_Channel);
-}
-
-/**
- * @brief Checks whether the specified DAC interrupt has occurred or not.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_IT: specifies the DAC interrupt source to check.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_IT (SET or RESET).
- */
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Get the DAC_IT enable bit status */
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
-
- /* Check the status of the specified DAC interrupt */
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
- {
- /* DAC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's interrupt pending bits.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @retval None
- */
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Clear the selected DAC interrupt pending bits */
- DAC->SR = (DAC_IT << DAC_Channel);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_dac.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,322 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dac.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the DAC firmware
- * library, applicable only for STM32F051 and STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DAC_H
-#define __STM32F0XX_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DAC Init structure definition
- */
-
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
- are generated, or whether no wave is generated.
- This parameter can be a value of @ref DAC_wave_generation
- This parameter is only applicable for STM32F072 devices */
-
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
- the maximum amplitude triangle generation for the DAC channel.
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude
- This parameter is only applicable for STM32F072 devices */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
- * @{
- */
-
-/** @defgroup DAC_Trigger
- * @{
- */
-
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel1 */
-#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel1 */
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel1,
- applicable only for STM32F072 devices */
-#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel1 */
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel1 */
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channels */
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channels */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T3_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
- ((TRIGGER) == DAC_Trigger_Software))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @brief This parameters are only applicable for STM32F072 devices.
- * @{
- */
-
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
- ((WAVE) == DAC_WaveGeneration_Noise) || \
- ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
- * @brief These parameters are only applicable for STM32F072 devices.
- * @{
- */
-
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
- ((VALUE) == DAC_TriangleAmplitude_1) || \
- ((VALUE) == DAC_TriangleAmplitude_3) || \
- ((VALUE) == DAC_TriangleAmplitude_7) || \
- ((VALUE) == DAC_TriangleAmplitude_15) || \
- ((VALUE) == DAC_TriangleAmplitude_31) || \
- ((VALUE) == DAC_TriangleAmplitude_63) || \
- ((VALUE) == DAC_TriangleAmplitude_127) || \
- ((VALUE) == DAC_TriangleAmplitude_255) || \
- ((VALUE) == DAC_TriangleAmplitude_511) || \
- ((VALUE) == DAC_TriangleAmplitude_1023) || \
- ((VALUE) == DAC_TriangleAmplitude_2047) || \
- ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
- * @}
- */
-
-/** @defgroup DAC_OutputBuffer
- * @{
- */
-
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable DAC_CR_BOFF1
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
- ((STATE) == DAC_OutputBuffer_Disable))
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection
- * @{
- */
-
-#define DAC_Channel_1 ((uint32_t)0x00000000)
-#define DAC_Channel_2 ((uint32_t)0x00000010) /*!< Only applicable for STM32F072 devices */
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
- ((CHANNEL) == DAC_Channel_2))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignment
- * @{
- */
-
-#define DAC_Align_12b_R ((uint32_t)0x00000000)
-#define DAC_Align_12b_L ((uint32_t)0x00000004)
-#define DAC_Align_8b_R ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
- ((ALIGN) == DAC_Align_12b_L) || \
- ((ALIGN) == DAC_Align_8b_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @brief These parameters are only applicable for STM32F072 devices.
- * @{
- */
-
-#define DAC_Wave_Noise ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
- ((WAVE) == DAC_Wave_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_data
- * @{
- */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_interrupts_definition
- * @{
- */
-
-#define DAC_IT_DMAUDR DAC_SR_DMAUDR1
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
-
-/**
- * @}
- */
-
-
-/** @defgroup DAC_flags_definition
- * @{
- */
-
-#define DAC_FLAG_DMAUDR DAC_SR_DMAUDR1
-
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the DAC configuration to the default reset state *****/
-void DAC_DeInit(void);
-
-/* DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); /*!< Only applicable for STM32F072 devices */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); /*!< Only applicable for STM32F072 devices */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_DAC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_dbgmcu.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,228 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dbgmcu.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Debug MCU (DBGMCU) peripheral:
- * + Device and Revision ID management
- * + Peripherals Configuration
- * @verbatim
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dbgmcu.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DBGMCU
- * @brief DBGMCU driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Private_Functions
- * @{
- */
-
-
-/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
- * @brief Device and Revision ID management functions
- *
-@verbatim
- ==============================================================================
- ##### Device and Revision ID management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
- * @brief Peripherals Configuration
- *
-@verbatim
- ==============================================================================
- ##### Peripherals Configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures low power mode behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the low power mode.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
- * @param NewState: new state of the specified low power mode in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-
-/**
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB1 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted,
- * not applicable for STM32F030 devices
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted,
- * applicable only for STM32F072 devices
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
- * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped
- * when Core is halted.
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped
- * when Core is halted
- * @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted,
- * applicable only for STM32F042 and STM32F072 devices
- * @param NewState: new state of the specified APB1 peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB1FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB2 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
- * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
- * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
- * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
- * @param NewState: new state of the specified APB2 peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB2FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_dbgmcu.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,117 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dbgmcu.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the DBGMCU firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DBGMCU_H
-#define __STM32F0XX_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DBGMCU
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup DBGMCU_Exported_Constants
- * @{
- */
-
-#define DBGMCU_STOP DBGMCU_CR_DBG_STOP
-#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< Not applicable for STM32F030 devices */
-#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
-#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
-#define DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< Only applicable for STM32F072 devices */
-#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
-#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
-#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
-#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
-#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
-#define DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< Only applicable for STM32F042 and STM32F072 devices */
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP
-#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP
-#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP
-#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Device and Revision ID management functions ********************************/
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-
-/* Peripherals Configuration functions ****************************************/
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_DBGMCU_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_dma.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,715 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dma.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access controller (DMA):
- * + Initialization and Configuration
- * + Data Counter
- * + Interrupts and flags management
- *
- * @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable The DMA controller clock using
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1.
- (#) Enable and configure the peripheral to be connected to the DMA channel
- (except for internal SRAM / FLASH memories: no initialization is necessary).
- (#) For a given Channel, program the Source and Destination addresses,
- the transfer Direction, the Buffer Size, the Peripheral and Memory
- Incrementation mode and Data Size, the Circular or Normal mode,
- the channel transfer Priority and the Memory-to-Memory transfer
- mode (if needed) using the DMA_Init() function.
- (#) Enable the NVIC and the corresponding interrupt(s) using the function
- DMA_ITConfig() if you need to use DMA interrupts.
- (#) Enable the DMA channel using the DMA_Cmd() function.
- (#) Activate the needed channel Request using PPP_DMACmd() function for
- any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
- The function allowing this operation is provided in each PPP peripheral
- driver (ie. SPI_DMACmd for SPI peripheral).
- (#) Optionally, you can configure the number of data to be transferred
- when the channel is disabled (ie. after each Transfer Complete event
- or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
- And you can get the number of remaining data to be transferred using
- the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
- enabled and running).
- (#) To control DMA events you can use one of the following two methods:
- (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
- (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
- phase and DMA_GetITStatus() function into interrupt routines in
- communication phase.
- After checking on a flag you should clear it using DMA_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using DMA_ClearITPendingBit() function.
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dma.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) /*!< Only applicable for STM32F072 devices */
-#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) /*!< Only applicable for STM32F072 devices */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/** @defgroup DMA_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This subsection provides functions allowing to initialize the DMA channel
- source and destination addresses, incrementation and data sizes, transfer
- direction, buffer size, circular/normal mode selection, memory-to-memory
- mode selection and channel priority value.
- [..] The DMA_Init() function follows the DMA configuration procedures as described
- in reference manual (RM0091).
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DMAy Channelx registers to their default reset
- * values.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and
- * x can be 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @retval None
- */
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
-
- /* Reset DMAy Channelx control register */
- DMAy_Channelx->CCR = 0;
-
- /* Reset DMAy Channelx remaining bytes register */
- DMAy_Channelx->CNDTR = 0;
-
- /* Reset DMAy Channelx peripheral address register */
- DMAy_Channelx->CPAR = 0;
-
- /* Reset DMAy Channelx memory address register */
- DMAy_Channelx->CMAR = 0;
-
- if (DMAy_Channelx == DMA1_Channel1)
- {
- /* Reset interrupt pending bits for DMA1 Channel1 */
- DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel2)
- {
- /* Reset interrupt pending bits for DMA1 Channel2 */
- DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel3)
- {
- /* Reset interrupt pending bits for DMA1 Channel3 */
- DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel4)
- {
- /* Reset interrupt pending bits for DMA1 Channel4 */
- DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel5)
- {
- /* Reset interrupt pending bits for DMA1 Channel5 */
- DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel6)
- {
- /* Reset interrupt pending bits for DMA1 Channel6 */
- DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
- }
- else
- {
- if (DMAy_Channelx == DMA1_Channel7)
- {
- /* Reset interrupt pending bits for DMA1 Channel7 */
- DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
- }
- }
-}
-
-/**
- * @brief Initializes the DMAy Channelx according to the specified parameters
- * in the DMA_InitStruct.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
- * for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
-
-/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
- /* Get the DMAy_Channelx CCR value */
- tmpreg = DMAy_Channelx->CCR;
-
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= CCR_CLEAR_MASK;
-
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
- /* Set DIR bit according to DMA_DIR value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set PL bits according to DMA_Priority value */
- /* Set the MEM2MEM bit according to DMA_M2M value */
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
-
- /* Write to DMAy Channelx CCR */
- DMAy_Channelx->CCR = tmpreg;
-
-/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
-
-/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
- /* Write to DMAy Channelx CPAR */
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
-/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
- /* Write to DMAy Channelx CMAR */
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
-}
-
-/**
- * @brief Fills each DMA_InitStruct member with its default value.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
-/*-------------- Reset DMA init structure parameters values ------------------*/
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
- /* Initialize the DMA_MemoryBaseAddr member */
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
- /* Initialize the DMA_M2M member */
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
-}
-
-/**
- * @brief Enables or disables the specified DMAy Channelx.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and
- * x can be 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @param NewState: new state of the DMAy Channelx.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Channelx */
- DMAy_Channelx->CCR |= DMA_CCR_EN;
- }
- else
- {
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Group2 Data Counter functions
- * @brief Data Counter functions
- *
-@verbatim
- ===============================================================================
- ##### Data Counter functions #####
- ===============================================================================
- [..] This subsection provides function allowing to configure and read the buffer
- size (number of data to be transferred).The DMA data counter can be written
- only when the DMA channel is disabled (ie. after transfer complete event).
- [..] The following function can be used to write the Channel data counter value:
- (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
- DataNumber).
- -@- It is advised to use this function rather than DMA_Init() in situations
- where only the Data buffer needs to be reloaded.
- [..] The DMA data counter can be read to indicate the number of remaining transfers
- for the relative DMA channel. This counter is decremented at the end of each
- data transfer and when the transfer is complete:
- (+) If Normal mode is selected: the counter is set to 0.
- (+) If Circular mode is selected: the counter is reloaded with the initial
- value(configured before enabling the DMA channel).
- [..] The following function can be used to read the Channel data counter value:
- (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the number of data units in the current DMAy Channelx transfer.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be
- * 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @param DataNumber: The number of data units in the current DMAy Channelx
- * transfer.
- * @note This function can only be used when the DMAy_Channelx is disabled.
- * @retval None.
- */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
-/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DataNumber;
-}
-
-/**
- * @brief Returns the number of remaining data units in the current
- * DMAy Channelx transfer.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and
- * x can be 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @retval The number of remaining data units in the current DMAy Channelx
- * transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- /* Return the number of remaining data units for DMAy Channelx */
- return ((uint16_t)(DMAy_Channelx->CNDTR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This subsection provides functions allowing to configure the DMA Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the DMA controller events: Polling mode or Interrupt mode.
- *** Polling Mode ***
- ====================
- [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
- number x : DMA channel number ).
- (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
- (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
- (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
- (#) DMAy_FLAG_GLx : to indicate that at least one of the events described
- above occurred.
- -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
- same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
- [..]In this Mode it is advised to use the following functions:
- (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
- (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] Each DMA channel can be managed through 4 Interrupts:
- (+) Interrupt Source
- (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
- event.
- (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
- event.
- (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
- (##) DMA_IT_GL : to indicate that at least one of the interrupts described
- above occurred.
- -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
- the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
- [..]In this Mode it is advised to use the following functions:
- (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
- FunctionalState NewState);
- (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
- (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DMAy Channelx interrupts.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and
- * x can be 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled
- * or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @param NewState: new state of the specified DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA interrupts */
- DMAy_Channelx->CCR |= DMA_IT;
- }
- else
- {
- /* Disable the selected DMA interrupts */
- DMAy_Channelx->CCR &= ~DMA_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Channelx flag is set or not.
- * @param DMA_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 devices.
- * @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
- * relative to the same channel is set (Transfer Complete, Half-transfer
- * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
- * DMAy_FLAG_TEx).
- *
- * @retval The new state of DMA_FLAG (SET or RESET).
- */
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
- /* Check the status of the specified DMA flag */
- if ((DMA1->ISR & DMA_FLAG) != (uint32_t)RESET)
- {
- /* DMA_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Channelx's pending flags.
- * @param DMA_FLAG: specifies the flag to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 devices.
- *
- * @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
- * relative to the same channel (Transfer Complete, Half-transfer Complete and
- * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
- *
- * @retval None
- */
-void DMA_ClearFlag(uint32_t DMA_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
-
- /* Clear the selected DMA flags */
- DMA1->IFCR = DMA_FLAG;
-}
-
-/**
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
- * @param DMA_IT: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 devices.
- *
- * @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
- * interrupts relative to the same channel is set (Transfer Complete,
- * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
- * DMAy_IT_HTx or DMAy_IT_TEx).
- *
- * @retval The new state of DMA_IT (SET or RESET).
- */
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DMA_GET_IT(DMA_IT));
-
- /* Check the status of the specified DMA interrupt */
- if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET)
- {
- /* DMA_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DMA_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Channelx's interrupt pending bits.
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 devices.
- *
- * @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
- * interrupts relative to the same channel (Transfer Complete, Half-transfer
- * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
- * DMAy_IT_TEx).
- *
- * @retval None
- */
-void DMA_ClearITPendingBit(uint32_t DMA_IT)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
- /* Clear the selected DMA interrupt pending bits */
- DMA1->IFCR = DMA_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_dma.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,387 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dma.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the DMA firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DMA_H
-#define __STM32F0XX_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DMA Init structures definition
- */
-typedef struct
-{
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
-
- uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
-
- uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
- This parameter can be a value of @ref DMA_data_transfer_direction */
-
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
- The data unit is equal to the configuration set in DMA_PeripheralDataSize
- or DMA_MemoryDataSize members depending in the transfer direction */
-
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
- This parameter can be a value of @ref DMA_memory_incremented_mode */
-
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_peripheral_data_size */
-
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_memory_data_size */
-
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_circular_normal_mode
- @note: The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
-
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_priority_level */
-
- uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
- This parameter can be a value of @ref DMA_memory_to_memory */
-}DMA_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants
- * @{
- */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
- ((PERIPH) == DMA1_Channel2) || \
- ((PERIPH) == DMA1_Channel3) || \
- ((PERIPH) == DMA1_Channel4) || \
- ((PERIPH) == DMA1_Channel5) || \
- ((PERIPH) == DMA1_Channel6) || \
- ((PERIPH) == DMA1_Channel7))
-
-/** @defgroup DMA_data_transfer_direction
- * @{
- */
-
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
-#define DMA_DIR_PeripheralDST DMA_CCR_DIR
-
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
- ((DIR) == DMA_DIR_PeripheralDST))
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_incremented_mode
- * @{
- */
-
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
-#define DMA_PeripheralInc_Enable DMA_CCR_PINC
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
- ((STATE) == DMA_PeripheralInc_Enable))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_incremented_mode
- * @{
- */
-
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
-#define DMA_MemoryInc_Enable DMA_CCR_MINC
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
- ((STATE) == DMA_MemoryInc_Enable))
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_data_size
- * @{
- */
-
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
-#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
- ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_data_size
- * @{
- */
-
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
-#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
- ((SIZE) == DMA_MemoryDataSize_Word))
-/**
- * @}
- */
-
-/** @defgroup DMA_circular_normal_mode
- * @{
- */
-
-#define DMA_Mode_Normal ((uint32_t)0x00000000)
-#define DMA_Mode_Circular DMA_CCR_CIRC
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
-/**
- * @}
- */
-
-/** @defgroup DMA_priority_level
- * @{
- */
-
-#define DMA_Priority_VeryHigh DMA_CCR_PL
-#define DMA_Priority_High DMA_CCR_PL_1
-#define DMA_Priority_Medium DMA_CCR_PL_0
-#define DMA_Priority_Low ((uint32_t)0x00000000)
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
- ((PRIORITY) == DMA_Priority_High) || \
- ((PRIORITY) == DMA_Priority_Medium) || \
- ((PRIORITY) == DMA_Priority_Low))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_to_memory
- * @{
- */
-
-#define DMA_M2M_Disable ((uint32_t)0x00000000)
-#define DMA_M2M_Enable DMA_CCR_MEM2MEM
-
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_interrupts_definition
- * @{
- */
-
-#define DMA_IT_TC DMA_CCR_TCIE
-#define DMA_IT_HT DMA_CCR_HTIE
-#define DMA_IT_TE DMA_CCR_TEIE
-
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
-
-#define DMA1_IT_GL1 DMA_ISR_GIF1
-#define DMA1_IT_TC1 DMA_ISR_TCIF1
-#define DMA1_IT_HT1 DMA_ISR_HTIF1
-#define DMA1_IT_TE1 DMA_ISR_TEIF1
-#define DMA1_IT_GL2 DMA_ISR_GIF2
-#define DMA1_IT_TC2 DMA_ISR_TCIF2
-#define DMA1_IT_HT2 DMA_ISR_HTIF2
-#define DMA1_IT_TE2 DMA_ISR_TEIF2
-#define DMA1_IT_GL3 DMA_ISR_GIF3
-#define DMA1_IT_TC3 DMA_ISR_TCIF3
-#define DMA1_IT_HT3 DMA_ISR_HTIF3
-#define DMA1_IT_TE3 DMA_ISR_TEIF3
-#define DMA1_IT_GL4 DMA_ISR_GIF4
-#define DMA1_IT_TC4 DMA_ISR_TCIF4
-#define DMA1_IT_HT4 DMA_ISR_HTIF4
-#define DMA1_IT_TE4 DMA_ISR_TEIF4
-#define DMA1_IT_GL5 DMA_ISR_GIF5
-#define DMA1_IT_TC5 DMA_ISR_TCIF5
-#define DMA1_IT_HT5 DMA_ISR_HTIF5
-#define DMA1_IT_TE5 DMA_ISR_TEIF5
-#define DMA1_IT_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */
-
-#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
- ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
- ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
- ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
- ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
- ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
- ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
- ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
- ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
- ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
- ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
- ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
- ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
- ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_flags_definition
- * @{
- */
-#define DMA1_FLAG_GL1 DMA_ISR_GIF1
-#define DMA1_FLAG_TC1 DMA_ISR_TCIF1
-#define DMA1_FLAG_HT1 DMA_ISR_HTIF1
-#define DMA1_FLAG_TE1 DMA_ISR_TEIF1
-#define DMA1_FLAG_GL2 DMA_ISR_GIF2
-#define DMA1_FLAG_TC2 DMA_ISR_TCIF2
-#define DMA1_FLAG_HT2 DMA_ISR_HTIF2
-#define DMA1_FLAG_TE2 DMA_ISR_TEIF2
-#define DMA1_FLAG_GL3 DMA_ISR_GIF3
-#define DMA1_FLAG_TC3 DMA_ISR_TCIF3
-#define DMA1_FLAG_HT3 DMA_ISR_HTIF3
-#define DMA1_FLAG_TE3 DMA_ISR_TEIF3
-#define DMA1_FLAG_GL4 DMA_ISR_GIF4
-#define DMA1_FLAG_TC4 DMA_ISR_TCIF4
-#define DMA1_FLAG_HT4 DMA_ISR_HTIF4
-#define DMA1_FLAG_TE4 DMA_ISR_TEIF4
-#define DMA1_FLAG_GL5 DMA_ISR_GIF5
-#define DMA1_FLAG_TC5 DMA_ISR_TCIF5
-#define DMA1_FLAG_HT5 DMA_ISR_HTIF5
-#define DMA1_FLAG_TE5 DMA_ISR_TEIF5
-#define DMA1_FLAG_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */
-
-#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
- ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
- ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
- ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
- ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
- ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
- ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
- ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
- ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
- ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
- ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
- ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
- ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
- ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Buffer_Size
- * @{
- */
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the DMA configuration to the default reset state ******/
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
-
-/* Initialization and Configuration functions *********************************/
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
-
-/* Data Counter functions******************************************************/
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
-
-/* Interrupts and flags management functions **********************************/
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
-void DMA_ClearFlag(uint32_t DMA_FLAG);
-ITStatus DMA_GetITStatus(uint32_t DMA_IT);
-void DMA_ClearITPendingBit(uint32_t DMA_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_DMA_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_exti.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,324 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_exti.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the EXTI peripheral:
- * + Initialization and Configuration
- * + Interrupts and flags management
- *
- * @verbatim
- ==============================================================================
- ##### EXTI features #####
- ==============================================================================
- [..] External interrupt/event lines are mapped as following:
- (#) All available GPIO pins are connected to the 16 external
- interrupt/event lines from EXTI0 to EXTI15.
- (#) EXTI line 16 is connected to the PVD output, not applicable for STM32F030 devices.
- (#) EXTI line 17 is connected to the RTC Alarm event.
- (#) EXTI line 18 is connected to the RTC Alarm event, applicable only for STM32F072 devices.
- (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.
- (#) EXTI line 20 is connected to the RTC wakeup event, applicable only for STM32F072 devices.
- (#) EXTI line 21 is connected to the Comparator 1 wakeup event, applicable only for STM32F051 and STM32F072 devices.
- (#) EXTI line 22 is connected to the Comparator 2 wakeup event, applicable only for STM32F051 and STM32F072 devices.
- (#) EXTI line 23 is connected to the I2C1 wakeup event, not applicable for STM32F030 devices.
- (#) EXTI line 25 is connected to the USART1 wakeup event, not applicable for STM32F030 devices.
- (#) EXTI line 26 is connected to the USART2 wakeup event, applicable only for STM32F072 devices.
- (#) EXTI line 27 is connected to the CEC wakeup event, applicable only for STM32F051 and STM32F072 devices.
- (#) EXTI line 31 is connected to the VDD USB monitor event, applicable only for STM32F072 devices.
-
- ##### How to use this driver #####
- ==============================================================================
- [..] In order to use an I/O pin as an external interrupt source, follow
- steps below:
- (#) Configure the I/O in input mode using GPIO_Init()
- (#) Select the input source pin for the EXTI line using
- SYSCFG_EXTILineConfig().
- (#) Select the mode(interrupt, event) and configure the trigger selection
- (Rising, falling or both) using EXTI_Init(). For the internal interrupt,
- the trigger selection is not needed( the active edge is always the rising one).
- (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
- (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt().
- [..]
- (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
- registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_exti.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup EXTI
- * @brief EXTI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup EXTI_Private_Functions
- * @{
- */
-
-/** @defgroup EXTI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the EXTI peripheral registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-void EXTI_DeInit(void)
-{
- EXTI->IMR = 0x0F940000;
- EXTI->EMR = 0x00000000;
- EXTI->RTSR = 0x00000000;
- EXTI->FTSR = 0x00000000;
- EXTI->PR = 0x006BFFFF;
-}
-
-/**
- * @brief Initializes the EXTI peripheral according to the specified
- * parameters in the EXTI_InitStruct.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
- * contains the configuration information for the EXTI peripheral.
- * @retval None
- */
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
- assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
- tmp = (uint32_t)EXTI_BASE;
-
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
- {
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-
- /* Select the trigger for the selected interrupts */
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
- {
- /* Rising Falling edge */
- EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
- }
- else
- {
- tmp = (uint32_t)EXTI_BASE;
- tmp += EXTI_InitStruct->EXTI_Trigger;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
- }
- }
- else
- {
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- /* Disable the selected external lines */
- *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
- }
-}
-
-/**
- * @brief Fills each EXTI_InitStruct member with its reset value.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param EXTI_Line: specifies the EXTI line on which the software interrupt
- * will be generated.
- * This parameter can be any combination of EXTI_Linex where x can be (0..27).
- * @retval None
- */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->SWIER |= EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Group2 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ==============================================================================
- ##### Interrupts and flags management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param EXTI_Line: specifies the EXTI line flag to check.
- * This parameter can be EXTI_Linex where x can be (0..27).
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param EXTI_Line: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..27).
- * @retval None
- */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param EXTI_Line: specifies the EXTI line to check.
- * This parameter can be EXTI_Linex where x can be (0..27).
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param EXTI_Line: specifies the EXTI lines to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..27).
- * @retval None
- */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_exti.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,226 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_exti.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the EXTI
- * firmware library
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_EXTI_H
-#define __STM32F0XX_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief EXTI mode enumeration
- */
-
-typedef enum
-{
- EXTI_Mode_Interrupt = 0x00,
- EXTI_Mode_Event = 0x04
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/**
- * @brief EXTI Trigger enumeration
- */
-
-typedef enum
-{
- EXTI_Trigger_Rising = 0x08,
- EXTI_Trigger_Falling = 0x0C,
- EXTI_Trigger_Rising_Falling = 0x10
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
- ((TRIGGER) == EXTI_Trigger_Falling) || \
- ((TRIGGER) == EXTI_Trigger_Rising_Falling))
-/**
- * @brief EXTI Init Structure definition
- */
-
-typedef struct
-{
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
- This parameter can be any combination of @ref EXTI_Lines */
-
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-}EXTI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Constants
- * @{
- */
-/** @defgroup EXTI_Lines
- * @{
- */
-
-#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
-#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
-#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
-#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
-#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
-#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
-#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
-#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
-#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
-#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
-#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
-#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
-#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
-#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
-#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
-#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
-#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16
- Connected to the PVD Output,
- not applicable for STM32F030 devices */
-#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17
- Connected to the RTC Alarm
- event */
-#define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18
- Connected to the USB
- event, only applicable for
- STM32F072 devices */
-#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19
- Connected to the RTC Tamper
- and Time Stamp events */
-#define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20
- Connected to the RTC wakeup
- event, only applicable for
- STM32F072 devices */
-#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21
- Connected to the Comparator 1
- event, only applicable for STM32F051
- ans STM32F072 devices */
-#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22
- Connected to the Comparator 2
- event, only applicable for STM32F051
- and STM32F072 devices */
-#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23
- Connected to the I2C1 wakeup
- event, not applicable for STM32F030 devices */
-#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25
- Connected to the USART1 wakeup
- event, not applicable for STM32F030 devices */
-#define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26
- Connected to the USART2 wakeup
- event, applicable only for
- STM32F072 devices */
-#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27
- Connected to the CEC wakeup
- event, applicable only for STM32F051
- and STM32F072 devices */
-#define EXTI_Line31 ((uint32_t)0x80000000) /*!< Internal interrupt line 31
- Connected to the VDD USB monitor
- event, applicable only for
- STM32F072 devices */
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00))
-
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
- ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
- ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
- ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
- ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
- ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
- ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
- ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
- ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
- ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
- ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
- ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \
- ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \
- ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the EXTI configuration to the default reset state *****/
-void EXTI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
-void EXTI_ClearFlag(uint32_t EXTI_Line);
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_EXTI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_flash.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1266 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_flash.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FLASH peripheral:
- * - FLASH Interface configuration
- * - FLASH Memory Programming
- * - Option Bytes Programming
- * - Interrupts and flags management
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver provides functions to configure and program the Flash
- memory of all STM32F0xx devices. These functions are split in 4 groups
- (#) FLASH Interface configuration functions: this group includes the
- management of following features:
- (++) Set the latency
- (++) Enable/Disable the prefetch buffer
-
- (#) FLASH Memory Programming functions: this group includes all needed
- functions to erase and program the main memory:
- (++) Lock and Unlock the Flash interface.
- (++) Erase function: Erase Page, erase all pages.
- (++) Program functions: Half Word and Word write.
-
- (#) FLASH Option Bytes Programming functions: this group includes all
- needed functions to:
- (++) Lock and Unlock the Flash Option bytes.
- (++) Launch the Option Bytes loader
- (++) Erase the Option Bytes
- (++)Set/Reset the write protection
- (++) Set the Read protection Level
- (++) Program the user option Bytes
- (++) Set/Reset the BOOT1 bit
- (++) Enable/Disable the VDDA Analog Monitoring
- (++) Get the user option bytes
- (++) Get the Write protection
- (++) Get the read protection status
-
- (#) FLASH Interrupts and flag management functions: this group includes
- all needed functions to:
- (++) Enable/Disable the flash interrupt sources
- (++) Get flags status
- (++) Clear flags
- (++) Get Flash operation status
- (++) Wait for last flash operation
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_flash.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions
- * @brief FLASH Interface configuration functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Interface configuration functions #####
- ===============================================================================
-
- [..] FLASH_Interface configuration_Functions, includes the following functions:
- (+) void FLASH_SetLatency(uint32_t FLASH_Latency):
- [..] To correctly read data from Flash memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock (HCLK)
- [..]
- +--------------------------------------------- +
- | Wait states | HCLK clock frequency (MHz) |
- |---------------|------------------------------|
- |0WS(1CPU cycle)| 0 < HCLK <= 24 |
- |---------------|------------------------------|
- |1WS(2CPU cycle)| 24 < HCLK <= 48 |
- +----------------------------------------------+
- [..]
- (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
- [..]
- All these functions don't need the unlock sequence.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the code latency value.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Read the ACR register */
- tmpreg = FLASH->ACR;
-
- /* Sets the Latency value */
- tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
- tmpreg |= FLASH_Latency;
-
- /* Write the ACR register */
- FLASH->ACR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @param NewState: new state of the FLASH prefetch buffer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_PRFTBE;
- }
- else
- {
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
- }
-}
-
-/**
- * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
- * @param None
- * @retval FLASH Prefetch Buffer Status (SET or RESET).
- */
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions
- * @brief FLASH Memory Programming functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Memory Programming functions #####
- ===============================================================================
-
- [..] The FLASH Memory Programming functions, includes the following functions:
- (+) void FLASH_Unlock(void);
- (+) void FLASH_Lock(void);
- (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
- (+) FLASH_Status FLASH_EraseAllPages(void);
- (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
- (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-
- [..] Any operation of erase or program should follow these steps:
-
- (#) Call the FLASH_Unlock() function to enable the flash control register and
- program memory access
- (#) Call the desired function to erase page or program data
- (#) Call the FLASH_Lock() to disable the flash program memory access
- (recommended to protect the FLASH memory against possible unwanted operation)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH control register and program memory access.
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
- {
- /* Unlocking the program memory access */
- FLASH->KEYR = FLASH_FKEY1;
- FLASH->KEYR = FLASH_FKEY2;
- }
-}
-
-/**
- * @brief Locks the Program memory access.
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH control register and program memory access */
- FLASH->CR |= FLASH_CR_LOCK;
-}
-
-/**
- * @brief Erases a specified page in program memory.
- * @note To correctly run this function, the FLASH_Unlock() function must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access (recommended
- * to protect the FLASH memory against possible unwanted operation)
- * @param Page_Address: The page address in program memory to be erased.
- * @note A Page is erased in the Program memory only if the address to load
- * is the start address of a page (multiple of 1024 bytes).
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to erase the page */
- FLASH->CR |= FLASH_CR_PER;
- FLASH->AR = Page_Address;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PER Bit */
- FLASH->CR &= ~FLASH_CR_PER;
- }
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH pages.
- * @note To correctly run this function, the FLASH_Unlock() function must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access (recommended
- * to protect the FLASH memory against possible unwanted operation)
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllPages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the MER Bit */
- FLASH->CR &= ~FLASH_CR_MER;
- }
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Programs a word at a specified address.
- * @note To correctly run this function, the FLASH_Unlock() function must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access (recommended
- * to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified address.
- * @note To correctly run this function, the FLASH_Unlock() function must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access (recommended
- * to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new data */
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group3 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ===============================================================================
- ##### Option Bytes Programming functions #####
- ===============================================================================
-
- [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
- (+) void FLASH_OB_Unlock(void);
- (+) void FLASH_OB_Lock(void);
- (+) void FLASH_OB_Launch(void);
- (+) FLASH_Status FLASH_OB_Erase(void);
- (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
- (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
- (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
- (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
- (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
- (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
- (+) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
- (+) uint8_t FLASH_OB_GetUser(void);
- (+) uint32_t FLASH_OB_GetWRP(void);
- (+) FlagStatus FLASH_OB_GetRDP(void);
-
- [..] Any operation of erase or program should follow these steps:
-
- (#) Call the FLASH_OB_Unlock() function to enable the Option Bytes registers access
-
- (#) Call one or several functions to program the desired option bytes
- (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level
- (++) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- => to Enable/Disable the desired sector write protection
- (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- => to configure the user option Bytes: IWDG, STOP and the Standby.
- (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
- => to set or reset BOOT1
- (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
- => to enable or disable the VDDA Analog Monitoring
- (++) You can write all User Options bytes at once using a single function
- by calling FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
- (++) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) to program the
- two half word in the option bytes
-
- (#) Once all needed option bytes to be programmed are correctly written, call the
- FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-
- (#) Call the FLASH_OB_Lock() to disable the Option Bytes registers access (recommended
- to protect the option Bytes against possible unwanted operations)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the option bytes block access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
- {
- /* Unlocking the option bytes block access */
- FLASH->OPTKEYR = FLASH_OPTKEY1;
- FLASH->OPTKEYR = FLASH_OPTKEY2;
- }
-}
-
-/**
- * @brief Locks the option bytes block access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Lock(void)
-{
- /* Set the OPTWREN Bit to lock the option bytes block access */
- FLASH->CR &= ~FLASH_CR_OPTWRE;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @param None
- * @retval None
- */
-void FLASH_OB_Launch(void)
-{
- /* Set the OBL_Launch bit to launch the option byte loading */
- FLASH->CR |= FLASH_CR_OBL_LAUNCH;
-}
-
-/**
- * @brief Erases the FLASH option bytes.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @note This functions erases all option bytes except the Read protection (RDP).
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_Erase(void)
-{
- uint16_t rdptmp = OB_RDP_Level_0;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Get the actual read protection Option Byte value */
- if(FLASH_OB_GetRDP() != RESET)
- {
- rdptmp = 0x00;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to erase the option bytes */
- FLASH->CR |= FLASH_CR_OPTER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- /* Restore the last read protection Option Byte value */
- OB->RDP = (uint16_t)rdptmp;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- else
- {
- if (status != FLASH_TIMEOUT)
- {
- /* Disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- }
- /* Return the erase status */
- return status;
-}
-
-/**
- * @brief Write protects the desired pages
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param OB_WRP: specifies the address of the pages to be write protected.
- * This parameter can be:
- * @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63
- * @arg OB_WRP_AllPages
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
-{
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
-
- OB_WRP = (uint32_t)(~OB_WRP);
- WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
- WRP1_Data = (uint16_t)((OB_WRP >> 8) & OB_WRP0_WRP0);
- WRP2_Data = (uint16_t)((OB_WRP >> 16) & OB_WRP0_WRP0) ;
- WRP3_Data = (uint16_t)((OB_WRP >> 24) & OB_WRP0_WRP0) ;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- FLASH->CR |= FLASH_CR_OPTPG;
-
- if(WRP0_Data != 0xFF)
- {
- OB->WRP0 = WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
- {
- OB->WRP1 = WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
- {
- OB->WRP2 = WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF))
- {
- OB->WRP3 = WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the write protection operation Status */
- return status;
-}
-
-/**
- * @brief Enables or disables the read out protection.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param FLASH_ReadProtection_Level: specifies the read protection level.
- * This parameter can be:
- * @arg OB_RDP_Level_0: No protection
- * @arg OB_RDP_Level_1: Read protection of the memory
- * @arg OB_RDP_Level_2: Chip protection
- * @note When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP(OB_RDP));
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- FLASH->CR |= FLASH_CR_OPTER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->RDP = OB_RDP;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- else
- {
- if(status != FLASH_TIMEOUT)
- {
- /* Disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
- }
- }
- }
- /* Return the protection operation Status */
- return status;
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param OB_IWDG: Selects the WDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software WDG selected
- * @arg OB_IWDG_HW: Hardware WDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the BOOT1 option bit.
- * @param OB_BOOT1: Set or Reset the BOOT1 option bit.
- * This parameter can be one of the following values:
- * @arg OB_BOOT1_RESET: BOOT1 option bit reset
- * @arg OB_BOOT1_SET: BOOT1 option bit set
- * @retval None
- */
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT1(OB_BOOT1));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_BOOT1 | 0xEF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the BOOT0 option bit.
- * @note This function is applicable only for the STM32F042 devices.
- * @param OB_BOOT0: Set or Reset the BOOT0 option bit.
- * This parameter can be one of the following values:
- * @arg OB_BOOT0_RESET: BOOT0 option bit reset
- * @arg OB_BOOT0_SET: BOOT0 option bit set
- * @retval None
- */
-FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT0(OB_BOOT0));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_BOOT0 | 0xF7;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the BOOT0SW option bit.
- * @note This function is applicable only for the STM32F042 devices.
- * @param OB_BOOT0SW: Set or Reset the BOOT0_SW option bit.
- * This parameter can be one of the following values:
- * @arg OB_BOOT0_SW: BOOT0_SW option bit reset
- * @arg OB_BOOT0_HW: BOOT0_SW option bit set
- * @retval None
- */
-FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT0SW(OB_BOOT0SW));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_BOOT0SW | 0x7F;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the analogue monitoring on VDDA Power source.
- * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
- * This parameter can be one of the following values:
- * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
- * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
- * @retval None
- */
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_VDDA_ANALOG | 0xDF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the SRAM parity.
- * @param OB_SRAM_Parity: Set or Reset the SRAM parity enable bit.
- * This parameter can be one of the following values:
- * @arg OB_SRAM_PARITY_SET: Set SRAM parity.
- * @arg OB_SRAM_PARITY_RESET: Reset SRAM parity.
- * @retval None
- */
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_SRAM_Parity | 0xBF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY,
- * BOOT1 and VDDA ANALOG monitoring.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param OB_USER: Selects all user option bytes
- * This parameter is a combination of the following values:
- * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
- * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
- * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
- * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
- * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF
- * @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET
- * @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set
- * @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_USER;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-
-}
-
-/**
- * @brief Programs a half word at a specified Option Byte Data address.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * This parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enables the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @param None
- * @retval The FLASH User Option Bytes .
- */
-uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)(FLASH->OBR >> 8);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint32_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (uint32_t)(FLASH->WRPR);
-}
-
-/**
- * @brief Checks whether the FLASH Read out Protection Status is set or not.
- * @param None
- * @retval FLASH ReadOut Protection Status(SET or RESET)
- */
-FlagStatus FLASH_OB_GetRDP(void)
-{
- FlagStatus readstatus = RESET;
-
- if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
- {
- readstatus = SET;
- }
- else
- {
- readstatus = RESET;
- }
- return readstatus;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or
- * disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: FLASH end of programming Interrupt
- * @arg FLASH_IT_ERR: FLASH Error Interrupt
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
- * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
-
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASH's pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @param None
- * @retval FLASH Status: The returned value can be:
- * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status FLASHstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- FLASHstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
- {
- FLASHstatus = FLASH_ERROR_WRP;
- }
- else
- {
- if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
- {
- FLASHstatus = FLASH_ERROR_PROGRAM;
- }
- else
- {
- FLASHstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the FLASH Status */
- return FLASHstatus;
-}
-
-
-/**
- * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.
- * @param Timeout: FLASH programming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_BUSY,
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the FLASH Status */
- status = FLASH_GetStatus();
-
- /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
- while((status == FLASH_BUSY) && (Timeout != 0x00))
- {
- status = FLASH_GetStatus();
- Timeout--;
- }
-
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_flash.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,440 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_flash.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the FLASH
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_FLASH_H
-#define __STM32F0XX_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief FLASH Status
- */
-typedef enum
-{
- FLASH_BUSY = 1,
- FLASH_ERROR_WRP,
- FLASH_ERROR_PROGRAM,
- FLASH_COMPLETE,
- FLASH_TIMEOUT
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants
- * @{
- */
-
-/** @defgroup FLASH_Latency
- * @{
- */
-#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
-#define FLASH_Latency_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
- ((LATENCY) == FLASH_Latency_1))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupts
- * @{
- */
-
-#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
-#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Address
- * @{
- */
-#ifndef STM32F072
- #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
-#else
- #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF))
-#endif /* STM32F072 */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_DATA_ADDRESS
- * @{
- */
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_Write_Protection
- * @{
- */
-
-#ifndef STM32F072
-
-#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
-#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
-#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
-#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
-#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
-#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
-#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
-#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
-#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
-#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
-#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
-#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
-#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
-#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
-#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
-#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
-
-#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-
-#else
-
-#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
-#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
-#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
-#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
-#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
-#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
-#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
-#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
-#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
-#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
-#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
-#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
-#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
-#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
-#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
-#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
-#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
-#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
-#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
-#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
-#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
-#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
-#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
-#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
-#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
-#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
-#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
-#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
-#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
-#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
-#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
-#define OB_WRP_Pages62to63 ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */
-
-#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-
-#endif /* STM32F072 */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_Read_Protection
- * @{
- */
-
-/**
- * @brief FLASH_Read Protection Level
- */
-#define OB_RDP_Level_0 ((uint8_t)0xAA)
-#define OB_RDP_Level_1 ((uint8_t)0xBB)
-/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
-
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
- ((LEVEL) == OB_RDP_Level_1))/*||\
- ((LEVEL) == OB_RDP_Level_2))*/
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_IWatchdog
- * @{
- */
-
-#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_nRST_STOP
- * @{
- */
-
-#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_nRST_STDBY
- * @{
- */
-
-#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_BOOT1
- * @{
- */
-
-#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_BOOT0
- * @{
- */
-
-#define OB_BOOT0_RESET ((uint8_t)0x00) /*!< BOOT0 Reset */
-#define OB_BOOT0_SET ((uint8_t)0x08) /*!< BOOT0 Set */
-#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_BOOT0SW
- * @{
- */
-
-#define OB_BOOT0_SW ((uint8_t)0x00) /*!< BOOT0 pin disabled */
-#define OB_BOOT0_HW ((uint8_t)0x80) /*!< BOOT0 pin bonded with GPIO */
-#define IS_OB_BOOT0SW(BOOT0) (((BOOT0) == OB_BOOT0_SW) || ((BOOT0) == OB_BOOT0_HW))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring
- * @{
- */
-
-#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
-#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
-
-#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
- * @{
- */
-
-#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
-#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
-
-#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flags
- * @{
- */
-
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
-#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
-
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
-
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
- ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Timeout_definition
- * @{
- */
-#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Legacy
- * @{
- */
-#define FLASH_WRProt_Pages0to3 OB_WRP_Pages0to3
-#define FLASH_WRProt_Pages4to7 OB_WRP_Pages4to7
-#define FLASH_WRProt_Pages8to11 OB_WRP_Pages8to11
-#define FLASH_WRProt_Pages12to15 OB_WRP_Pages12to15
-#define FLASH_WRProt_Pages16to19 OB_WRP_Pages16to19
-#define FLASH_WRProt_Pages20to23 OB_WRP_Pages20to23
-#define FLASH_WRProt_Pages24to27 OB_WRP_Pages24to27
-#define FLASH_WRProt_Pages28to31 OB_WRP_Pages28to31
-#define FLASH_WRProt_Pages32to35 OB_WRP_Pages32to35
-#define FLASH_WRProt_Pages36to39 OB_WRP_Pages36to39
-#define FLASH_WRProt_Pages40to43 OB_WRP_Pages40to21
-#define FLASH_WRProt_Pages44to47 OB_WRP_Pages44to23
-#define FLASH_WRProt_Pages48to51 OB_WRP_Pages48to51
-#define FLASH_WRProt_Pages52to55 OB_WRP_Pages52to55
-#define FLASH_WRProt_Pages56to59 OB_WRP_Pages56to59
-#define FLASH_WRProt_Pages60to63 OB_WRP_Pages60to63
-
-
-#define FLASH_WRProt_AllPages OB_WRP_AllPages
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/**
- * @brief FLASH memory functions that can be executed from FLASH.
- */
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-FlagStatus FLASH_GetPrefetchBufferStatus(void);
-
-/* FLASH Memory Programming functions *****************************************/
-void FLASH_Unlock(void);
-void FLASH_Lock(void);
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
-FLASH_Status FLASH_EraseAllPages(void);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-
-/* FLASH Option Bytes Programming functions *****************************************/
-void FLASH_OB_Unlock(void);
-void FLASH_OB_Lock(void);
-void FLASH_OB_Launch(void);
-FLASH_Status FLASH_OB_Erase(void);
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
-FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0);
-FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW);
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
-FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
-uint8_t FLASH_OB_GetUser(void);
-uint32_t FLASH_OB_GetWRP(void);
-FlagStatus FLASH_OB_GetRDP(void);
-
-/* FLASH Interrupts and flags management functions **********************************/
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
-
-/** @defgroup FLASH_Legacy
- * @{
- */
-#define FLASH_EraseOptionBytes FLASH_OB_Erase
-#define FLASH_EnableWriteProtection FLASH_OB_EnableWRP
-#define FLASH_UserOptionByteConfig FLASH_OB_UserConfig
-#define FLASH_ProgramOptionByteData FLASH_OB_ProgramData
-#define FLASH_GetUserOptionByte FLASH_OB_GetUser
-#define FLASH_GetWriteProtectionOptionByte FLASH_OB_GetWRP
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_FLASH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_gpio.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,550 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_gpio.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the GPIO peripheral:
- * + Initialization and Configuration functions
- * + GPIO Read and Write functions
- * + GPIO Alternate functions configuration functions
- *
- * @verbatim
- *
- *
- ===========================================================================
- ##### How to use this driver #####
- ===========================================================================
- [..]
- (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
- (#) Configure the GPIO pin(s) using GPIO_Init()
- Four possible configuration are available for each pin:
- (++) Input: Floating, Pull-up, Pull-down.
- (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
- Open Drain (Pull-up, Pull-down or no Pull).
- In output mode, the speed is configurable: Low, Medium, Fast or High.
- (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
- Open Drain (Pull-up, Pull-down or no Pull).
- (++) Analog: required mode when a pin is to be used as ADC channel,
- DAC output or comparator input.
- (#) Peripherals alternate function:
- (++) For ADC, DAC and comparators, configure the desired pin in analog
- mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
- (++) For other peripherals (TIM, USART...):
- (+++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function. For PortC,
- PortD and PortF, no configuration is needed.
- (+++) Configure the desired pin in alternate function mode using
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (+++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (+++) Call GPIO_Init() function
- (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
- (#) To set/reset the level of a pin configured in output mode use
- GPIO_SetBits()/GPIO_ResetBits()
- (#) During and just after reset, the alternate functions are not active and
- the GPIO pins are configured in input floating mode (except JTAG pins).
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
- general-purpose (PC14 and PC15, respectively) when the LSE oscillator
- is off. The LSE has priority over the GPIO function.
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
- PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has
- priority over the GPIO function.
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_gpio.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the GPIOx peripheral registers to their default reset
- * values.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if(GPIOx == GPIOA)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
- }
- else if(GPIOx == GPIOB)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
- }
- else if(GPIOx == GPIOC)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
- }
- else if(GPIOx == GPIOD)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
- }
- else if(GPIOx == GPIOE)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
- }
- else
- {
- if(GPIOx == GPIOF)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified
- * parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /*-------------------------- Configure the port pins -----------------------*/
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
-
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration */
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
-
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- /* Pull-up Pull down resistor configuration */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next device reset.
- * @param GPIOx: where x can be (A or B) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit */
- tmp = GPIOx->LCKR;
- /* Read LCKK bit */
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### GPIO Read and Write #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: specifies the port bit to read.
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @retval The input port pin value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: Specifies the port bit to read.
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: specifies the port bits to be written.
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRR = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: specifies the port bits to be written.
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BRR = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: specifies the port bit to be written.
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enumeration values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRR = GPIO_Pin;
- }
- else
- {
- GPIOx->BRR = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param PortVal: specifies the value to be written to the port output data register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
- * @brief GPIO Alternate functions configuration functions
- *
-@verbatim
- ===============================================================================
- ##### GPIO Alternate functions configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOC, GPIOD, GPIOE and GPIOF are available only for STM32F072.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD, GPIOE
- * and (0..12) for GPIOC and (0, 2..5, 9..10) for GPIOF.
- * @param GPIO_AF: selects the pin to used as Alternate function.
- * This parameter can be one of the following value:
- * @arg GPIO_AF_0: WKUP, EVENTOUT, TIM15, SPI1, TIM17, MCO, SWDAT, SWCLK,
- * TIM14, BOOT, USART1, CEC, IR_OUT, SPI2, TIM3, USART4,
- * CAN, USART2, CRS, TIM16, TIM1, TS
- * @arg GPIO_AF_1: USART2, CEC, TIM3, USART1, USART2, EVENTOUT, I2C1,
- * I2C2, TIM15, SPI2, USART3, TS, SPI1
- * @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17, USB
- * @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT
- * @arg GPIO_AF_4: TIM14, USART4, USART3, CRS, CAN
- * @arg GPIO_AF_5: TIM16, TIM17, TIM15, SPI2, I2C2
- * @arg GPIO_AF_6: EVENTOUT
- * @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT
- * @note The pin should already been configured in Alternate Function mode(AF)
- * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * @note Refer to the Alternate function mapping table in the device datasheet
- * for the detailed mapping of the system and peripherals'alternate
- * function I/O pins.
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_gpio.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,368 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_gpio.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_GPIO_H
-#define __STM32F0XX_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOF))
-
-#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB))
-
-/** @defgroup Configuration_Mode_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
-}GPIOMode_TypeDef;
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-/**
- * @}
- */
-
-/** @defgroup Output_type_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-/**
- * @}
- */
-
-/** @defgroup Output_Maximum_frequency_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Speed_Level_1 = 0x00, /*!< I/O output speed: Low 2 MHz */
- GPIO_Speed_Level_2 = 0x01, /*!< I/O output speed: Medium 10 MHz */
- GPIO_Speed_Level_3 = 0x03 /*!< I/O output speed: High 50 MHz */
-}GPIOSpeed_TypeDef;
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
- ((SPEED) == GPIO_Speed_Level_3))
-/**
- * @}
- */
-
-/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-/**
- * @}
- */
-
-/** @defgroup Bit_SET_and_Bit_RESET_enumeration
- * @{
- */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-/**
- * @}
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
-
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternate_function_selection_define
- * @{
- */
-
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
- MCO, SWDAT, SWCLK, TIM14, BOOT,
- USART1, CEC, IR_OUT, SPI2, TS, TIM3,
- USART4, CAN, TIM3, USART2, USART3,
- CRS, TIM16, TIM1 */
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR,
- EVENTOUT, I2C1, I2C2, TIM15, SPI2,
- USART3, TS, SPI1 */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17,
- USB */
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN,
- I2C1 */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2,
- MCO, I2C1, USB */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
- ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
- ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
- ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Speed_Legacy
- * @{
- */
-
-#define GPIO_Speed_2MHz GPIO_Speed_Level_1 /*!< I/O output speed: Low 2 MHz */
-#define GPIO_Speed_10MHz GPIO_Speed_Level_2 /*!< I/O output speed: Medium 10 MHz */
-#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< I/O output speed: High 50 MHz */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the GPIO configuration to the default reset state *****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-
-/* GPIO Alternate functions configuration functions ***************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_GPIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_i2c.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1595 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_i2c.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Inter-Integrated circuit (I2C):
- * + Initialization and Configuration
- * + Communications handling
- * + SMBUS management
- * + I2C registers management
- * + Data transfers management
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
- ============================================================================
- ##### How to use this driver #####
- ============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
- function for I2C1 or I2C2.
- (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
- RCC_AHBPeriphClockCmd() function.
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, OpenDrain and speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function.
- (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address
- using the I2C_Init() function.
- (#) Optionally you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again I2C_Init() function):
- (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
- (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
- (++) Enable the general call using the I2C_GeneralCallCmd() function.
- (++) Enable the clock stretching using I2C_StretchClockCmd() function.
- (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
- (++) For SMBus Mode:
- (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
- (#) Enable the NVIC and the corresponding interrupt using the function
- I2C_ITConfig() if you need to use interrupt mode.
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using I2C_DMACmd() function.
- (#) Enable the I2C using the I2C_Cmd() function.
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
- transfers.
- [..]
- (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
- must be enabled by setting the driving capability control bit in SYSCFG.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_i2c.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*<! I2C CR1 clear register Mask */
-#define CR2_CLEAR_MASK ((uint32_t)0x07FF7FFF) /*<! I2C CR2 clear register Mask */
-#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
-#define ERROR_IT_MASK ((uint32_t)0x00003F00) /*<! I2C Error interrupt register Mask */
-#define TC_IT_MASK ((uint32_t)0x000000C0) /*<! I2C TC interrupt register Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions
- * @{
- */
-
-
-/** @defgroup I2C_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to initialize the I2C Mode,
- I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.
-
- [..] The I2C_Init() function follows the I2C configuration procedures (these procedures
- are available in reference manual).
-
- [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal
- states machines are reset and communication control bits, as well as status bits come
- back to their reset value.
-
- [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to
- HSI and Digital filters must be disabled.
-
- [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be
- configured using I2C_OwnAddress2Config() function.
-
- [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of
- each byte in slave mode when NBYTES is set to 0x01.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- if (I2Cx == I2C1)
- {
- /* Enable I2C1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
- /* Release I2C1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
- }
- else
- {
- /* Enable I2C2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- /* Release I2C2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the I2Cx peripheral according to the specified
- * parameters in the I2C_InitStruct.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
- * contains the configuration information for the specified I2C peripheral.
- * @retval None
- */
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
- assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
- /* Disable I2Cx Peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
-
- /*---------------------------- I2Cx FILTERS Configuration ------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear I2Cx CR1 register */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure I2Cx: analog and digital filter */
- /* Set ANFOFF bit according to I2C_AnalogFilter value */
- /* Set DFN bits according to I2C_DigitalFilter value */
- tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
-
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
- /*---------------------------- I2Cx TIMING Configuration -------------------*/
- /* Configure I2Cx: Timing */
- /* Set TIMINGR bits according to I2C_Timing */
- /* Write to I2Cx TIMING */
- I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
-
- /* Enable I2Cx Peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-
- /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Clear tmpreg local variable */
- tmpreg = 0;
- /* Clear OAR1 register */
- I2Cx->OAR1 = (uint32_t)tmpreg;
- /* Clear OAR2 register */
- I2Cx->OAR2 = (uint32_t)tmpreg;
- /* Configure I2Cx: Own Address1 and acknowledged address */
- /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
- /* Set OA1 bits according to I2C_OwnAddress1 value */
- tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
- (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
- /* Write to I2Cx OAR1 */
- I2Cx->OAR1 = tmpreg;
- /* Enable Own Address1 acknowledgement */
- I2Cx->OAR1 |= I2C_OAR1_OA1EN;
-
- /*---------------------------- I2Cx MODE Configuration ---------------------*/
- /* Configure I2Cx: mode */
- /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
- tmpreg = I2C_InitStruct->I2C_Mode;
- /* Write to I2Cx CR1 */
- I2Cx->CR1 |= tmpreg;
-
- /*---------------------------- I2Cx ACK Configuration ----------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear I2Cx CR2 register */
- tmpreg &= CR2_CLEAR_MASK;
- /* Configure I2Cx: acknowledgement */
- /* Set NACK bit according to I2C_Ack value */
- tmpreg |= I2C_InitStruct->I2C_Ack;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
- /*---------------- Reset I2C init structure parameters values --------------*/
- /* Initialize the I2C_Timing member */
- I2C_InitStruct->I2C_Timing = 0;
- /* Initialize the I2C_AnalogFilter member */
- I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
- /* Initialize the I2C_DigitalFilter member */
- I2C_InitStruct->I2C_DigitalFilter = 0;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Disable peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
-
- /* Perform a dummy read to delay the disable of peripheral for minimum
- 3 APB clock cycles to perform the software reset functionality */
- *(__IO uint32_t *)(uint32_t)I2Cx;
-
- /* Enable peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_ERRI: Error interrupt mask
- * @arg I2C_IT_TCI: Transfer Complete interrupt mask
- * @arg I2C_IT_STOPI: Stop Detection interrupt mask
- * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
- * @arg I2C_IT_ADDRI: Address Match interrupt mask
- * @arg I2C_IT_RXI: RX interrupt mask
- * @arg I2C_IT_TXI: TX interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR1 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
- }
-}
-
-/**
- * @brief Enables or disables the I2C Clock stretching.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable clock stretching */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);
- }
- else
- {
- /* Disable clock stretching */
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
- }
-}
-
-/**
- * @brief Enables or disables I2C wakeup from stop mode.
- * This function is not applicable for STM32F030 devices.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx stop mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable wakeup from stop mode */
- I2Cx->CR1 |= I2C_CR1_WUPEN;
- }
- else
- {
- /* Disable wakeup from stop mode */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN);
- }
-}
-
-/**
- * @brief Enables or disables the I2C own address 2.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C own address 2.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable own address 2 */
- I2Cx->OAR2 |= I2C_OAR2_OA2EN;
- }
- else
- {
- /* Disable own address 2 */
- I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
- }
-}
-
-/**
- * @brief Configures the I2C slave own address 2 and mask.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @param Mask: specifies own address 2 mask to be programmed.
- * This parameter can be one of the following values:
- * @arg I2C_OA2_NoMask: no mask.
- * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
- * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
- * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
- * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
- * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
- * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
- * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
- * @retval None
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_OWN_ADDRESS2(Address));
- assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
-
- /* Set I2Cx SADD */
- tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
- (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the I2C general call mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C general call mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable general call mode */
- I2Cx->CR1 |= I2C_CR1_GCEN;
- }
- else
- {
- /* Disable general call mode */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
- }
-}
-
-/**
- * @brief Enables or disables the I2C slave byte control.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C slave byte control.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable slave byte control */
- I2Cx->CR1 |= I2C_CR1_SBC;
- }
- else
- {
- /* Disable slave byte control */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
- }
-}
-
-/**
- * @brief Configures the slave address to be transmitted after start generation.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @note This function should be called before generating start condition.
- * @retval None
- */
-void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SLAVE_ADDRESS(Address));
-
- /* Get the old register value */
- tmpreg = I2Cx->CR2;
-
- /* Reset I2Cx SADD bit [9:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
-
- /* Set I2Cx SADD */
- tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
-
- /* Store the new register value */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the I2C 10-bit addressing mode for the master.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C 10-bit addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function should be called before generating start condition.
- * @retval None
- */
-void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable 10-bit addressing mode */
- I2Cx->CR2 |= I2C_CR2_ADD10;
- }
- else
- {
- /* Disable 10-bit addressing mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group2 Communications handling functions
- * @brief Communications handling functions
- *
-@verbatim
- ===============================================================================
- ##### Communications handling functions #####
- ===============================================================================
- [..] This section provides a set of functions that handles I2C communication.
-
- [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
- mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
-
- [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
- this configuration should be done before generating start condition in master
- mode.
-
- [..] When switching from master write operation to read operation in 10Bit addressing
- mode, master can only sends the 1st 7 bits of the 10 bit address, followed by
- Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
-
- [..] In master mode, when transferring more than 255 bytes Reload mode should be used
- to handle communication. In the first phase of transfer, Nbytes should be set to
- 255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
- function should be called to handle remaining communication.
-
- [..] In master mode, when software end mode is selected when all data is transferred
- TC flag is set I2C_TransferHandling() function should be called to generate STOP
- or generate ReStart.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the I2C automatic end mode (stop condition is
- * automatically sent when nbytes data are transferred).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C automatic end mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has effect if Reload mode is disabled.
- * @retval None
- */
-void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Auto end mode */
- I2Cx->CR2 |= I2C_CR2_AUTOEND;
- }
- else
- {
- /* Disable Auto end mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
- }
-}
-
-/**
- * @brief Enables or disables the I2C nbytes reload mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the nbytes reload mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Auto Reload mode */
- I2Cx->CR2 |= I2C_CR2_RELOAD;
- }
- else
- {
- /* Disable Auto Reload mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
- }
-}
-
-/**
- * @brief Configures the number of bytes to be transmitted/received.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Number_Bytes: specifies the number of bytes to be programmed.
- * @retval None
- */
-void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->CR2;
-
- /* Reset I2Cx Nbytes bit [7:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
-
- /* Set I2Cx Nbytes */
- tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
-
- /* Store the new register value */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the type of transfer request for the master.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_Direction: specifies the transfer request direction to be programmed.
- * This parameter can be one of the following values:
- * @arg I2C_Direction_Transmitter: Master request a write transfer
- * @arg I2C_Direction_Receiver: Master request a read transfer
- * @retval None
- */
-void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
-{
-/* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
-
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction == I2C_Direction_Transmitter)
- {
- /* Request a write Transfer */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
- }
- else
- {
- /* Request a read Transfer */
- I2Cx->CR2 |= I2C_CR2_RD_WRN;
- }
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR2 |= I2C_CR2_START;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR2 |= I2C_CR2_STOP;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
- }
-}
-
-/**
- * @brief Enables or disables the I2C 10-bit header only mode with read direction.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C 10-bit header only mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This mode can be used only when switching from master transmitter mode
- * to master receiver mode.
- * @retval None
- */
-void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable 10-bit header only mode */
- I2Cx->CR2 |= I2C_CR2_HEAD10R;
- }
- else
- {
- /* Disable 10-bit header only mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
- }
-}
-
-/**
- * @brief Generates I2C communication Acknowledge.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the Acknowledge.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable ACK generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);
- }
- else
- {
- /* Enable NACK generation */
- I2Cx->CR2 |= I2C_CR2_NACK;
- }
-}
-
-/**
- * @brief Returns the I2C slave matched address .
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the slave matched address .
- */
-uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
-}
-
-/**
- * @brief Returns the I2C slave received request.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the received request.
- */
-uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
-{
- uint32_t tmpreg = 0;
- uint16_t direction = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
-
- /* If write transfer is requested */
- if (tmpreg == 0)
- {
- /* write transfer is requested */
- direction = I2C_Direction_Transmitter;
- }
- else
- {
- /* Read transfer is requested */
- direction = I2C_Direction_Receiver;
- }
- return direction;
-}
-
-/**
- * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @param Number_Bytes: specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param ReloadEndMode: new state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_Reload_Mode: Enable Reload mode .
- * @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
- * @arg I2C_SoftEnd_Mode: Enable Software end mode.
- * @param StartStopMode: new state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_No_StartStop: Don't Generate stop and start condition.
- * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
- * @arg I2C_Generate_Start_Read: Generate Restart for read request.
- * @arg I2C_Generate_Start_Write: Generate Restart for write request.
- * @retval None
- */
-void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SLAVE_ADDRESS(Address));
- assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
- assert_param(IS_START_STOP_MODE(StartStopMode));
-
- /* Get the CR2 register value */
- tmpreg = I2Cx->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
- (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
-
- /* update CR2 register */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group3 SMBUS management functions
- * @brief SMBUS management functions
- *
-@verbatim
- ===============================================================================
- ##### SMBUS management functions #####
- ===============================================================================
- [..] This section provides a set of functions that handles SMBus communication
- and timeouts detection.
-
- [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
- function and setting I2C_Mode member of I2C_InitTypeDef() structure to
- I2C_Mode_SMBusDevice.
-
- [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
- function and setting I2C_Mode member of I2C_InitTypeDef() structure to
- I2C_Mode_SMBusHost.
-
- [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
- function.
-
- [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be
- configured (in accordance to SMBus specification) using I2C_TimeoutBConfig()
- function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
- the detection.
-
- [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
- function followed by the call of I2C_ClockTimeoutCmd(). When adding to this
- procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition
- (both SCL and SDA high) is detected also.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables I2C SMBus alert.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx SMBus alert.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable SMBus alert */
- I2Cx->CR1 |= I2C_CR1_ALERTEN;
- }
- else
- {
- /* Disable SMBus alert */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Extended clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA
- * high detection).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Idle clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE);
- }
-}
-
-/**
- * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus
- * idle SCL and SDA high when TIDLE = 1).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param Timeout: specifies the TimeoutA to be programmed.
- * @retval None
- */
-void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_I2C_TIMEOUT(Timeout));
-
- /* Get the old register value */
- tmpreg = I2Cx->TIMEOUTR;
-
- /* Reset I2Cx TIMEOUTA bit [11:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
-
- /* Set I2Cx TIMEOUTA */
- tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
-
- /* Store the new register value */
- I2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
- * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param Timeout: specifies the TimeoutB to be programmed.
- * @retval None
- */
-void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_I2C_TIMEOUT(Timeout));
-
- /* Get the old register value */
- tmpreg = I2Cx->TIMEOUTR;
-
- /* Reset I2Cx TIMEOUTB bit [11:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
-
- /* Set I2Cx TIMEOUTB */
- tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
-
- /* Store the new register value */
- I2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
- * @brief Enables or disables I2C PEC calculation.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable PEC calculation */
- I2Cx->CR1 |= I2C_CR1_PECEN;
- }
- else
- {
- /* Disable PEC calculation */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C PEC transmission/reception request.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable PEC transmission/reception request */
- I2Cx->CR1 |= I2C_CR2_PECBYTE;
- }
- else
- {
- /* Disable PEC transmission/reception request */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE);
- }
-}
-
-/**
- * @brief Returns the I2C PEC.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @retval The value of the PEC .
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group4 I2C registers management functions
- * @brief I2C registers management functions
- *
-@verbatim
- ===============================================================================
- ##### I2C registers management functions #####
- ===============================================================================
- [..] This section provides a functions that allow user the management of
- I2C registers.
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_TIMINGR: TIMING register.
- * @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
- * @arg I2C_Register_ISR: ISR register.
- * @arg I2C_Register_ICR: ICR register.
- * @arg I2C_Register_PECR: PECR register.
- * @arg I2C_Register_RXDR: RXDR register.
- * @arg I2C_Register_TXDR: TXDR register.
- * @retval The value of the read register.
- */
-uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t)I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group5 Data transfers management functions
- * @brief Data transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers management functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the I2C data transfers.
-
- [..] The read access of the I2C_RXDR register can be done using
- the I2C_ReceiveData() function and returns the received value.
- Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
- function and stores the written data into TXDR.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Write in the DR register the data to be sent */
- I2Cx->TXDR = (uint8_t)Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->RXDR;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group6 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
- [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel
- requests:
- (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
- [..] In this Mode it is advised to use the following function:
- (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the I2C DMA interface.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_DMAReq_Tx: Tx DMA transfer request
- * @arg I2C_DMAReq_Rx: Rx DMA transfer request
- * @param NewState: new state of the selected I2C DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR1 |= I2C_DMAReq;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the I2C Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6).
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the I2C communication can be managed by 15 flags:
- (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
- (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
- (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
- (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
- (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
- (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
- (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
- (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
- (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
- (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
- (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
- (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
- (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
- (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
- (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
- (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
- [..]
- (@)Do not use the BUSY flag to handle each data transmission or reception.It is
- better to use the TXIS and RXNE flags instead.
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
- and 15 pending bits:
- [..] Interrupt Source:
- (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
- (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
- (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
- (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
- (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
- (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
- (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
-
- [..] Pending Bits:
- (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
- (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
- (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
- (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
- (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
- (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
- (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
- (#) I2C_IT_BERR: to indicate the status of Bus error flag.
- (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
- (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
- (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
- (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
- (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
- (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_TXE: Transmit data register empty
- * @arg I2C_FLAG_TXIS: Transmit interrupt status
- * @arg I2C_FLAG_RXNE: Receive data register not empty
- * @arg I2C_FLAG_ADDR: Address matched (slave mode)
- * @arg I2C_FLAG_NACKF: NACK received flag
- * @arg I2C_FLAG_STOPF: STOP detection flag
- * @arg I2C_FLAG_TC: Transfer complete (master mode)
- * @arg I2C_FLAG_TCR: Transfer complete reload
- * @arg I2C_FLAG_BERR: Bus error
- * @arg I2C_FLAG_ARLO: Arbitration lost
- * @arg I2C_FLAG_OVR: Overrun/Underrun
- * @arg I2C_FLAG_PECERR: PEC error in reception
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_FLAG_ALERT: SMBus Alert
- * @arg I2C_FLAG_BUSY: Bus busy
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t tmpreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the ISR register value */
- tmpreg = I2Cx->ISR;
-
- /* Get flag status */
- tmpreg &= I2C_FLAG;
-
- if(tmpreg != 0)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_ADDR: Address matched (slave mode)
- * @arg I2C_FLAG_NACKF: NACK received flag
- * @arg I2C_FLAG_STOPF: STOP detection flag
- * @arg I2C_FLAG_BERR: Bus error
- * @arg I2C_FLAG_ARLO: Arbitration lost
- * @arg I2C_FLAG_OVR: Overrun/Underrun
- * @arg I2C_FLAG_PECERR: PEC error in reception
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_FLAG_ALERT: SMBus Alert
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
-
- /* Clear the selected flag */
- I2Cx->ICR = I2C_FLAG;
- }
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_TXIS: Transmit interrupt status
- * @arg I2C_IT_RXNE: Receive data register not empty
- * @arg I2C_IT_ADDR: Address matched (slave mode)
- * @arg I2C_IT_NACKF: NACK received flag
- * @arg I2C_IT_STOPF: STOP detection flag
- * @arg I2C_IT_TC: Transfer complete (master mode)
- * @arg I2C_IT_TCR: Transfer complete reload
- * @arg I2C_IT_BERR: Bus error
- * @arg I2C_IT_ARLO: Arbitration lost
- * @arg I2C_IT_OVR: Overrun/Underrun
- * @arg I2C_IT_PECERR: PEC error in reception
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_IT_ALERT: SMBus Alert
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t tmpreg = 0;
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- /* If Error interrupt */
- if ((uint32_t)(I2C_IT & ERROR_IT_MASK))
- {
- enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
- }
- /* If TC interrupt */
- else if ((uint32_t)(I2C_IT & TC_IT_MASK))
- {
- enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
- }
- else
- {
- enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
- }
-
- /* Get the ISR register value */
- tmpreg = I2Cx->ISR;
-
- /* Get flag status */
- tmpreg &= I2C_IT;
-
- /* Check the status of the specified I2C flag */
- if((tmpreg != RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's interrupt pending bits.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_ADDR: Address matched (slave mode)
- * @arg I2C_IT_NACKF: NACK received flag
- * @arg I2C_IT_STOPF: STOP detection flag
- * @arg I2C_IT_BERR: Bus error
- * @arg I2C_IT_ARLO: Arbitration lost
- * @arg I2C_IT_OVR: Overrun/Underrun
- * @arg I2C_IT_PECERR: PEC error in reception
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_IT_ALERT: SMBus Alert
- * @retval The new state of I2C_IT (SET or RESET).
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
- /* Clear the selected flag */
- I2Cx->ICR = I2C_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_i2c.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,488 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_i2c.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the I2C firmware
- * library
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_I2C_H
-#define __STM32F0XX_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter must be set by referring to I2C_Timing_Config_Tool*/
-
- uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
- This parameter can be a value of @ref I2C_Analog_Filter*/
-
- uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
- This parameter can be a number between 0x00 and 0x0F*/
-
- uint32_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode*/
-
- uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
- This parameter can be a 7-bit or 10-bit address*/
-
- uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement*/
-
- uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address*/
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2))
-
-#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1)
-
-/** @defgroup I2C_Analog_Filter
- * @{
- */
-
-#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
-#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
-
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
- ((FILTER) == I2C_AnalogFilter_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_Digital_Filter
- * @{
- */
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-/**
- * @}
- */
-
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint32_t)0x00000000)
-#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
-#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
-
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint32_t)0x00000000)
-#define I2C_Ack_Disable I2C_CR2_NACK
-
-#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
- ((ACK) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
-#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
-
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint16_t)0x0000)
-#define I2C_Direction_Receiver ((uint16_t)0x0400)
-
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_DMA_transfer_requests
- * @{
- */
-
-#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
-#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
-
-#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_slave_address
- * @{
- */
-
-#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
-/**
- * @}
- */
-
-
-/** @defgroup I2C_own_address2
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address2_mask
- * @{
- */
-
-#define I2C_OA2_NoMask ((uint8_t)0x00)
-#define I2C_OA2_Mask01 ((uint8_t)0x01)
-#define I2C_OA2_Mask02 ((uint8_t)0x02)
-#define I2C_OA2_Mask03 ((uint8_t)0x03)
-#define I2C_OA2_Mask04 ((uint8_t)0x04)
-#define I2C_OA2_Mask05 ((uint8_t)0x05)
-#define I2C_OA2_Mask06 ((uint8_t)0x06)
-#define I2C_OA2_Mask07 ((uint8_t)0x07)
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
- ((MASK) == I2C_OA2_Mask01) || \
- ((MASK) == I2C_OA2_Mask02) || \
- ((MASK) == I2C_OA2_Mask03) || \
- ((MASK) == I2C_OA2_Mask04) || \
- ((MASK) == I2C_OA2_Mask05) || \
- ((MASK) == I2C_OA2_Mask06) || \
- ((MASK) == I2C_OA2_Mask07))
-
-/**
- * @}
- */
-
-/** @defgroup I2C_timeout
- * @{
- */
-
-#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_TIMINGR ((uint8_t)0x10)
-#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
-#define I2C_Register_ISR ((uint8_t)0x18)
-#define I2C_Register_ICR ((uint8_t)0x1C)
-#define I2C_Register_PECR ((uint8_t)0x20)
-#define I2C_Register_RXDR ((uint8_t)0x24)
-#define I2C_Register_TXDR ((uint8_t)0x28)
-
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_TIMINGR) || \
- ((REGISTER) == I2C_Register_TIMEOUTR) || \
- ((REGISTER) == I2C_Register_ISR) || \
- ((REGISTER) == I2C_Register_ICR) || \
- ((REGISTER) == I2C_Register_PECR) || \
- ((REGISTER) == I2C_Register_RXDR) || \
- ((REGISTER) == I2C_Register_TXDR))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_ERRI I2C_CR1_ERRIE
-#define I2C_IT_TCI I2C_CR1_TCIE
-#define I2C_IT_STOPI I2C_CR1_STOPIE
-#define I2C_IT_NACKI I2C_CR1_NACKIE
-#define I2C_IT_ADDRI I2C_CR1_ADDRIE
-#define I2C_IT_RXI I2C_CR1_RXIE
-#define I2C_IT_TXI I2C_CR1_TXIE
-
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-#define I2C_FLAG_TXE I2C_ISR_TXE
-#define I2C_FLAG_TXIS I2C_ISR_TXIS
-#define I2C_FLAG_RXNE I2C_ISR_RXNE
-#define I2C_FLAG_ADDR I2C_ISR_ADDR
-#define I2C_FLAG_NACKF I2C_ISR_NACKF
-#define I2C_FLAG_STOPF I2C_ISR_STOPF
-#define I2C_FLAG_TC I2C_ISR_TC
-#define I2C_FLAG_TCR I2C_ISR_TCR
-#define I2C_FLAG_BERR I2C_ISR_BERR
-#define I2C_FLAG_ARLO I2C_ISR_ARLO
-#define I2C_FLAG_OVR I2C_ISR_OVR
-#define I2C_FLAG_PECERR I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT I2C_ISR_ALERT
-#define I2C_FLAG_BUSY I2C_ISR_BUSY
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
- ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
- ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
- ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
- ((FLAG) == I2C_FLAG_BUSY))
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_TXIS I2C_ISR_TXIS
-#define I2C_IT_RXNE I2C_ISR_RXNE
-#define I2C_IT_ADDR I2C_ISR_ADDR
-#define I2C_IT_NACKF I2C_ISR_NACKF
-#define I2C_IT_STOPF I2C_ISR_STOPF
-#define I2C_IT_TC I2C_ISR_TC
-#define I2C_IT_TCR I2C_ISR_TCR
-#define I2C_IT_BERR I2C_ISR_BERR
-#define I2C_IT_ARLO I2C_ISR_ARLO
-#define I2C_IT_OVR I2C_ISR_OVR
-#define I2C_IT_PECERR I2C_ISR_PECERR
-#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_IT_ALERT I2C_ISR_ALERT
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
- ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
- ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
- ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_ALERT))
-
-
-/**
- * @}
- */
-
-/** @defgroup I2C_ReloadEndMode_definition
- * @{
- */
-
-#define I2C_Reload_Mode I2C_CR2_RELOAD
-#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
-#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
-
-
-#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
- ((MODE) == I2C_AutoEnd_Mode) || \
- ((MODE) == I2C_SoftEnd_Mode))
-
-
-/**
- * @}
- */
-
-/** @defgroup I2C_StartStopMode_definition
- * @{
- */
-
-#define I2C_No_StartStop ((uint32_t)0x00000000)
-#define I2C_Generate_Stop I2C_CR2_STOP
-#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define I2C_Generate_Start_Write I2C_CR2_START
-
-
-#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
- ((MODE) == I2C_Generate_Start_Read) || \
- ((MODE) == I2C_Generate_Start_Write) || \
- ((MODE) == I2C_No_StartStop))
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-
-/* Initialization and Configuration functions *********************************/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /*!< not applicable for STM32F030 devices */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
-void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Communications handling functions ******************************************/
-void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
-void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
-uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
-void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
-
-/* SMBUS management functions ************************************************/
-void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
-void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* I2C registers management functions *****************************************/
-uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-
-/* Data transfers management functions ****************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_I2C_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_iwdg.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,303 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_iwdg.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Independent watchdog (IWDG) peripheral:
- * + Prescaler and Counter configuration
- * + IWDG activation
- * + Flag management
- *
- * @verbatim
- *
- ==============================================================================
- ##### IWDG features #####
- ==============================================================================
- [..] The IWDG can be started by either software or hardware (configurable
- through option byte).
-
- [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
- thus stays active even if the main clock fails.
- Once the IWDG is started, the LSI is forced ON and cannot be disabled
- (LSI cannot be disabled too), and the counter starts counting down from
- the reset value of 0xFFF. When it reaches the end of count value (0x000)
- a system reset is generated.
- The IWDG counter should be reloaded at regular intervals to prevent
- an MCU reset.
-
- [..] The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-
- [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
- reset occurs.
-
- [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx
- devices provide the capability to measure the LSI frequency (LSI clock
- should be seleted as RTC clock which is internally connected to TIM10 CH1
- input capture). The measured value can be used to have an IWDG timeout with
- an acceptable accuracy.
- For more information, please refer to the STM32F0xx Reference manual.
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver allows to use IWDG peripheral with either window option enabled
- or disabled. To do so follow one of the two procedures below.
- (#) Window option is enabled:
- (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware).
- (++) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
- (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
- (++) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
- (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
- (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
-
- (#) Window option is disabled:
- (++) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
- (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
- (++) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
- (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
- (++) reload the IWDG counter at regular intervals during normal operation
- to prevent an MCU reset, using IWDG_ReloadCounter() function.
- (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware).
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_iwdg.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup IWDG
- * @brief IWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ---------------------- IWDG registers bit mask ----------------------------*/
-/* KR register bit mask */
-#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
-#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Functions
- * @{
- */
-
-/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
- * @brief Prescaler and Counter configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Prescaler and Counter configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
- * This parameter can be one of the following values:
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
- * @retval None
- */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
- IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
- * @brief Sets IWDG Prescaler value.
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
- * This parameter can be one of the following values:
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
- * @retval None
- */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
- IWDG->PR = IWDG_Prescaler;
-}
-
-/**
- * @brief Sets IWDG Reload value.
- * @param Reload: specifies the IWDG Reload value.
- * This parameter must be a number between 0 and 0x0FFF.
- * @retval None
- */
-void IWDG_SetReload(uint16_t Reload)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_RELOAD(Reload));
- IWDG->RLR = Reload;
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_ReloadCounter(void)
-{
- IWDG->KR = KR_KEY_RELOAD;
-}
-
-
-/**
- * @brief Sets the IWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * @retval None
- */
-void IWDG_SetWindowValue(uint16_t WindowValue)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
- IWDG->WINR = WindowValue;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group2 IWDG activation function
- * @brief IWDG activation function
- *
-@verbatim
- ==============================================================================
- ##### IWDG activation function #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_Enable(void)
-{
- IWDG->KR = KR_KEY_ENABLE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group3 Flag management function
- * @brief Flag management function
- *
-@verbatim
- ===============================================================================
- ##### Flag management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified IWDG flag is set or not.
- * @param IWDG_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
- * @arg IWDG_FLAG_RVU: Reload Value Update on going
- * @arg IWDG_FLAG_WVU: Counter Window Value Update on going
- * @retval The new state of IWDG_FLAG (SET or RESET).
- */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_iwdg.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,150 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_iwdg.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_IWDG_H
-#define __STM32F0XX_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup IWDG_WriteAccess
- * @{
- */
-
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
- ((ACCESS) == IWDG_WriteAccess_Disable))
-/**
- * @}
- */
-
-/** @defgroup IWDG_prescaler
- * @{
- */
-
-#define IWDG_Prescaler_4 ((uint8_t)0x00)
-#define IWDG_Prescaler_8 ((uint8_t)0x01)
-#define IWDG_Prescaler_16 ((uint8_t)0x02)
-#define IWDG_Prescaler_32 ((uint8_t)0x03)
-#define IWDG_Prescaler_64 ((uint8_t)0x04)
-#define IWDG_Prescaler_128 ((uint8_t)0x05)
-#define IWDG_Prescaler_256 ((uint8_t)0x06)
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
- ((PRESCALER) == IWDG_Prescaler_8) || \
- ((PRESCALER) == IWDG_Prescaler_16) || \
- ((PRESCALER) == IWDG_Prescaler_32) || \
- ((PRESCALER) == IWDG_Prescaler_64) || \
- ((PRESCALER) == IWDG_Prescaler_128)|| \
- ((PRESCALER) == IWDG_Prescaler_256))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag
- * @{
- */
-
-#define IWDG_FLAG_PVU IWDG_SR_PVU
-#define IWDG_FLAG_RVU IWDG_SR_RVU
-#define IWDG_FLAG_WVU IWDG_SR_WVU
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
- ((FLAG) == IWDG_FLAG_WVU))
-
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-
-#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Prescaler and Counter configuration functions ******************************/
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
-void IWDG_SetReload(uint16_t Reload);
-void IWDG_ReloadCounter(void);
-void IWDG_SetWindowValue(uint16_t WindowValue);
-
-/* IWDG activation function ***************************************************/
-void IWDG_Enable(void);
-
-/* Flag management function ***************************************************/
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_IWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_misc.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,177 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_misc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides all the miscellaneous firmware functions (add-on
- * to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_misc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-/**
- *
-@verbatim
- *******************************************************************************
- ##### Interrupts configuration functions #####
- *******************************************************************************
- [..] This section provide functions allowing to configure the NVIC interrupts
- (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions.
- (#) Enable and Configure the priority of the selected IRQ Channels.
- The priority can be 0..3.
-
- -@- Lower priority values gives higher priority.
- -@- Priority Order:
- (#@) Lowest priority.
- (#@) Lowest hardware priority (IRQn position).
-
-@endverbatim
-*/
-
-/**
- * @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
- * @retval None
- */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- uint32_t tmppriority = 0x00;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02];
- tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)));
- tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8));
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Selects the condition for the system to enter low power mode.
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
- * This parameter can be one of the following values:
- * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
- * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
- * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
- * @param NewState: new state of LP condition.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param SysTick_CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
-
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_misc.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_misc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_MISC_H
-#define __STM32F0XX_MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup MISC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief NVIC Init Structure definition
- */
-
-typedef struct
-{
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
- This parameter can be a value of @ref IRQn_Type
- (For the complete STM32 Devices IRQ Channels list,
- please refer to stm32f0xx.h file) */
-
- uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified
- in NVIC_IRQChannel. This parameter can be a value
- between 0 and 3. */
-
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
- will be enabled or disabled.
- This parameter can be set either to ENABLE or DISABLE */
-} NVIC_InitTypeDef;
-
-/**
- *
-@verbatim
-
-@endverbatim
-*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
- * @{
- */
-
-/** @defgroup MISC_System_Low_Power
- * @{
- */
-
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
- ((LP) == NVIC_LP_SLEEPDEEP) || \
- ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
- * @}
- */
-
-/** @defgroup MISC_Preemption_Priority_Group
- * @{
- */
-#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04)
-
-/**
- * @}
- */
-
-/** @defgroup MISC_SysTick_clock_source
- * @{
- */
-
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_MISC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_pwr.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,576 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_pwr.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Backup Domain Access
- * + PVD configuration
- * + WakeUp pins configuration
- * + Low Power modes configuration
- * + Flags management
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_pwr.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/** @defgroup PWR_Group1 Backup Domain Access function
- * @brief Backup Domain Access function
- *
-@verbatim
- ==============================================================================
- ##### Backup Domain Access function #####
- ==============================================================================
-
- [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
- and RTC backup registers) are protected against possible stray write accesses.
- [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
- * @brief Enables or disables access to the Backup domain registers.
- * @note If the HSE divided by 32 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @param NewState: new state of the access to the Backup domain registers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Backup Domain Access */
- PWR->CR |= PWR_CR_DBP;
- }
- else
- {
- /* Disable the Backup Domain Access */
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group2 PVD configuration functions
- * @brief PVD configuration functions
- *
-@verbatim
- ==============================================================================
- ##### PVD configuration functions #####
- ==============================================================================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
- selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
- PVD threshold. This event is internally connected to the EXTI line16
- and can generate an interrupt if enabled through the EXTI registers.
- (+) The PVD is stopped in Standby mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @note This function is not applicable for STM32F030 devices.
- * @param PWR_PVDLevel: specifies the PVD detection level
- * This parameter can be one of the following values:
- * @arg PWR_PVDLevel_0
- * @arg PWR_PVDLevel_1
- * @arg PWR_PVDLevel_2
- * @arg PWR_PVDLevel_3
- * @arg PWR_PVDLevel_4
- * @arg PWR_PVDLevel_5
- * @arg PWR_PVDLevel_6
- * @arg PWR_PVDLevel_7
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_MASK;
-
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Power Voltage Detector(PVD).
- * @note This function is not applicable for STM32F030 devices.
- * @param NewState: new state of the PVD.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the PVD */
- PWR->CR |= PWR_CR_PVDE;
- }
- else
- {
- /* Disable the PVD */
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group3 WakeUp pins configuration functions
- * @brief WakeUp pins configuration functions
- *
-@verbatim
- ==============================================================================
- ##### WakeUp pin configuration functions #####
- ==============================================================================
-
- (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
- forced in input pull down configuration and are active on rising edges.
- (+) There are eight WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13.
- The following WakeUp pins are only applicable for STM32F072 dvices:
- WakeUp Pin 3 on PE.06, WakeUp Pin 4 on PA.02, WakeUp Pin 5 on PC.05,
- WakeUp Pin 6 on PB.05, WakeUp Pin 7 on PB.15 and WakeUp Pin 8 on PF.02.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param PWR_WakeUpPin: specifies the WakeUpPin.
- * This parameter can be one of the following values
- * @arg PWR_WakeUpPin_1
- * @arg PWR_WakeUpPin_2
- * @arg PWR_WakeUpPin_3, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_4, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_5, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_6, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_7, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_8, only applicable for STM32F072 devices
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the EWUPx pin */
- PWR->CSR |= PWR_WakeUpPin;
- }
- else
- {
- /* Disable the EWUPx pin */
- PWR->CSR &= ~PWR_WakeUpPin;
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Group4 Low Power modes configuration functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Low Power modes configuration functions #####
- ==============================================================================
-
- [..] The devices feature three low-power modes:
- (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
- (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
- (+) Standby mode: VCORE domain powered off
-
- *** Sleep mode ***
- ==================
- [..]
- (+) Entry:
- (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
- (+) Exit:
- (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
-
- *** Stop mode ***
- =================
- [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
- the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register
- contents are preserved.
- The voltage regulator can be configured either in normal or low-power mode.
-
- (+) Entry:
- (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
- function with regulator in LowPower or with Regulator ON.
- (+) Exit:
- (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
- or any internal IPs (I2C, UASRT or CEC) wakeup event.
-
- *** Standby mode ***
- ====================
- [..] The Standby mode allows to achieve the lowest power consumption. It is based
- on the Cortex-M0 deepsleep mode, with the voltage regulator disabled.
- The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14
- oscillator and the HSE oscillator are also switched off. SRAM and register
- contents are lost except for the Backup domain (RTC registers, RTC backup
- registers and Standby circuitry).
-
- [..] The voltage regulator is OFF.
-
- (+) Entry:
- (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper
- event, a time-stamp event, or a comparator event, without depending on an
- external interrupt (Auto-wakeup mode).
-
- (+) RTC auto-wakeup (AWU) from the Stop mode
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
- (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function.
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
-
- (+) RTC auto-wakeup (AWU) from the Standby mode
- (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function.
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
-
- (+) Comparator auto-wakeup (AWU) from the Stop mode
- (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
- event, it is necessary to:
- (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
- to be sensitive to to the selected edges (falling, rising or falling
- and rising) (Interrupt or Event modes) using the EXTI_Init() function.
- (+++) Configure the comparator to generate the event.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enters Sleep mode.
- * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
- * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
- * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
-
- /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-
- /* Select SLEEP mode entry -------------------------------------------------*/
- if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
-}
-
-/**
- * @brief Enters STOP mode.
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_ON: STOP mode with regulator ON
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- @arg PWR_STOPEntry_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction
- * @retval None
- */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDSR bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDSR bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
- }
- else if (PWR_STOPEntry == PWR_STOPEntry_WFE)
- {
- /* Request Wait For Event */
- __WFE();
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
- }
- else
- {
- /* Set SLEEP on exit bit of Cortex-M0 System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
- }
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available)
- * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
- * time-stamp, RTC Alarm out, or RTC clock calibration out.
- * - WKUP pin 1 (PA0) if enabled.
- * @param None
- * @retval None
- */
-void PWR_EnterSTANDBYMode(void)
-{
- /* Clear Wakeup flag */
- PWR->CR |= PWR_CR_CWUF;
-
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
-
- /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group5 Flags management functions
- * @brief Flags management functions
- *
-@verbatim
- ==============================================================================
- ##### Flags management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified PWR flag is set or not.
- * @param PWR_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup
- * event was received from the WKUP pin or from the RTC alarm
- * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the
- * system was resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD
- * is enabled by the PWR_PVDCmd() function.
- * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag.
- * This flag indicates the state of the internal voltage
- * reference, VREFINT.
- * @retval The new state of PWR_FLAG (SET or RESET).
- */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the PWR's pending flags.
- * @param PWR_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @retval None
- */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
- PWR->CR |= PWR_FLAG << 2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_pwr.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,207 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_pwr.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the PWR firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_PWR_H
-#define __STM32F0XX_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level
- * @brief This parameters are only applicable for STM32F051 and STM32F072 devices
- * @{
- */
-
-#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
-#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
-#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
-#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
-#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
-#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
-#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
- ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
- ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
- ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
-/**
- * @}
- */
-
-/** @defgroup PWR_WakeUp_Pins
- * @{
- */
-
-#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
-#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
-#define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \
- ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \
- ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \
- ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8))
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
- * @{
- */
-
-#define PWR_Regulator_ON ((uint32_t)0x00000000)
-#define PWR_Regulator_LowPower PWR_CR_LPSDSR
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
- ((REGULATOR) == PWR_Regulator_LowPower))
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry
- * @{
- */
-
-#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
-#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry
- * @{
- */
-
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)
-#define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\
- ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
- * @{
- */
-
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */
-#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
-
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the PWR configuration to the default reset state ******/
-void PWR_DeInit(void);
-
-/* Backup Domain Access function **********************************************/
-void PWR_BackupAccessCmd(FunctionalState NewState);
-
-/* PVD configuration functions ************************************************/
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */
-void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */
-
-/* WakeUp pins configuration functions ****************************************/
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
-
-/* Low Power modes configuration functions ************************************/
-void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-
-/* Flags management functions *************************************************/
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_PWR_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_rcc.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1751 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_rcc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Reset and clock control (RCC) peripheral:
- * + Internal/external clocks, PLL, CSS and MCO configuration
- * + System, AHB and APB busses clocks configuration
- * + Peripheral clocks configuration
- * + Interrupts and flags management
- *
- @verbatim
-
- ===============================================================================
- ##### RCC specific features #####
- ===============================================================================
- [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
- all peripherals are off except internal SRAM, Flash and SWD.
- (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- all peripherals mapped on these busses are running at HSI speed.
- (#) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (#) All GPIOs are in input floating state, except the SWD pins which
- are assigned to be used for debug purpose.
- [..] Once the device started from reset, the user application has to:
- (#) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (#) Configure the System clock frequency and Flash settings
- (#) Configure the AHB and APB busses prescalers
- (#) Enable the clock for the peripheral(s) to be used
- (#) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG)
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- RCC registers mask -------------------------------- */
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
-
-/* CFGR register byte 3 (Bits[31:23]) base address */
-#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009)
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the internal/external clocks,
- PLL, CSS and MCO.
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
- or through the PLL as System clock source.
- The HSI clock can be used also to clock the USART, I2C and CEC peripherals.
- (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock
- the ADC peripheral.
- (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
- clock source.
- (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
- LSE can be used also to clock the USART and CEC peripherals.
- (#) PLL (clocked by HSI or HSE), for System clock.
- (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt)
- exception vector.
- (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI,
- HSE, LSE or PLL (divided by 2) clock on PA8 pin.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * @note HSI ON and used as system clock source
- * @note HSI14, HSE and PLL OFF
- * @note AHB, APB prescaler set to 1.
- * @note CSS and MCO OFF
- * @note All interrupts disabled
- * @note However, this function doesn't modify the configuration of the
- * @note Peripheral clocks
- * @note LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
-#if defined (STM32F051)
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80C;
-#else
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
- RCC->CFGR &= (uint32_t)0x08FFB80C;
-#endif /* STM32F051 */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFE;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function resets the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
-
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This function waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t StartUpCounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus HSEStatus = RESET;
-
- /* Wait till HSE is ready and if timeout is reached exit */
- do
- {
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- StartUpCounter++;
- } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * Refer to the Application Note AN4067 for more details on how to
- * calibrate the HSI.
- * @param HSICalibrationValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note After enabling the HSI, the application software should wait on
- * HSIRDY flag to be set indicating that HSI clock is stable and can
- * be used to clock the PLL and/or system clock.
- * @note HSI can not be stopped if it is used directly or through the PLL
- * as system clock. In this case, you have to select another source
- * of the system clock then stop the HSI.
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR |= RCC_CR_HSION;
- }
- else
- {
- RCC->CR &= ~RCC_CR_HSION;
- }
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14)
- * calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * Refer to the Application Note AN4067 for more details on how to
- * calibrate the HSI14.
- * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
-
- tmpreg = RCC->CR2;
-
- /* Clear HSI14TRIM[4:0] bits */
- tmpreg &= ~RCC_CR2_HSI14TRIM;
-
- /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
- tmpreg |= (uint32_t)HSI14CalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14).
- * @note After enabling the HSI14, the application software should wait on
- * HSIRDY flag to be set indicating that HSI clock is stable and can
- * be used to clock the ADC.
- * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the HSI14.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSI14Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR2 |= RCC_CR2_HSI14ON;
- }
- else
- {
- RCC->CR2 &= ~RCC_CR2_HSI14ON;
- }
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator request from ADC.
- * @param NewState: new state of the HSI14 ADC request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR2 &= ~RCC_CR2_HSI14DIS;
- }
- else
- {
- RCC->CR2 |= RCC_CR2_HSI14DIS;
- }
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to this
- * domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint32_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- RCC->BDCR &= ~(RCC_BDCR_LSEON);
-
- /* Reset LSEBYP bit */
- RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
-
- /* Configure LSE */
- RCC->BDCR |= RCC_LSE;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE) drive capability.
- * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
- * This parameter can be one of the following values:
- * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
- * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
- * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
- * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
- * @retval None
- */
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
-
- /* Clear LSEDRV[1:0] bits */
- RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
-
- /* Set the LSE Drive */
- RCC->BDCR |= RCC_LSEDrive;
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CSR |= RCC_CSR_LSION;
- }
- else
- {
- RCC->CSR &= ~RCC_CSR_LSION;
- }
-}
-
-/**
- * @brief Configures the PLL clock source and multiplication factor.
- * @note This function must be used only when the PLL is disabled.
- *
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
- * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
- * @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
- * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
- * PLL source).
- *
- * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
- * This parameter can be RCC_PLLMul_x where x:[2,16]
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
-
- /* Clear PLL Source [16] and Multiplier [21:18] bits */
- RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
-
- /* Set the PLL Source and Multiplier */
- RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
-}
-
-/**
- * @brief Enables or disables the PLL.
- * @note After enabling the PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The PLL can not be disabled if it is used as system clock source
- * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLL.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR |= RCC_CR_PLLON;
- }
- else
- {
- RCC->CR &= ~RCC_CR_PLLON;
- }
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator for USB (HSI48).
- * This function is only applicable for STM32F072 devices.
- * @note After enabling the HSI48, the application software should wait on
- * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
- * be used to clock the USB.
- * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the HSI48.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSI48Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR2 |= RCC_CR2_HSI48ON;
- }
- else
- {
- RCC->CR2 &= ~RCC_CR2_HSI48ON;
- }
-}
-
-/**
- * @brief Configures the PREDIV1 division factor.
- * @note This function must be used only when the PLL is disabled.
- * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
- * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
- * @retval None
- */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
-
- tmpreg = RCC->CFGR2;
- /* Clear PREDIV1[3:0] bits */
- tmpreg &= ~(RCC_CFGR2_PREDIV1);
- /* Set the PREDIV1 division factor */
- tmpreg |= RCC_PREDIV1_Div;
- /* Store the new value */
- RCC->CFGR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR |= RCC_CR_CSSON;
- }
- else
- {
- RCC->CR &= ~RCC_CR_CSSON;
- }
-}
-
-#ifdef STM32F051
-/**
- * @brief Selects the clock source to output on MCO pin (PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected.
- * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
- * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
- * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
- * @arg RCC_MCOSource_SYSCLK: System clock selected.
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
- * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
-
- /* Select MCO clock source and prescaler */
- *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = RCC_MCOSource;
-}
-#else
-
-/**
- * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
- * prescsaler.
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected.
- * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
- * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
- * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
- * @arg RCC_MCOSource_SYSCLK: System clock selected.
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
- * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
- * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
- * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
- * This parameter can be one of the following values:
- * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
- * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
- * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
- * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
- * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
- * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
- * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
- * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
- assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
-
- /* Get CFGR value */
- tmpreg = RCC->CFGR;
- /* Clear MCOPRE[2:0] bits */
- tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
- /* Set the RCC_MCOSource and RCC_MCOPrescaler */
- tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24));
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-#endif /* STM32F072 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### System, AHB and APB busses clocks configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the System, AHB and
- APB busses clocks.
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable prescaler
- and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
- and APB (PCLK) clocks are derived from AHB clock through
- configurable prescalers and used to clock the peripherals mapped on these busses.
- You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a
- programmable prescaler: 2 or 4).
- (+@) The CEC clock which is derived from LSE or HSI divided by 244.
- (+@) The I2C clock which is derived from HSI or system clock (SYSCLK).
- (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.
- (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE
- divided by a programmable prescaler).
- The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
- clock frequency.
- (+@) IWDG clock which is always the LSI clock.
-
- (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz.
- Depending on the maximum frequency, the FLASH wait states (WS) should be
- adapted accordingly:
- +--------------------------------------------- +
- | Wait states | HCLK clock frequency (MHz) |
- |---------------|------------------------------|
- |0WS(1CPU cycle)| 0 < HCLK <= 24 |
- |---------------|------------------------------|
- |1WS(2CPU cycle)| 24 < HCLK <= 48 |
- +----------------------------------------------+
-
- (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
- prefetch is disabled.
-
- [..] It is recommended to use the following software sequences to tune the number
- of wait states needed to access the Flash memory with the CPU frequency (HCLK).
- (+) Increasing the CPU frequency
- (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
- function
- (++) Check that Flash Prefetch buffer activation is taken into account by
- reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
- (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
- (++) Check that the new number of WS is taken into account by reading FLASH_ACR
- (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- (++) Check that the new CPU clock source is taken into account by reading
- the clock source status, using "RCC_GetSYSCLKSource()" function
- (+) Decreasing the CPU frequency
- (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- (++) Check that the new CPU clock source is taken into account by reading
- the clock source status, using "RCC_GetSYSCLKSource()" function
- (++) Program the new number of WS, using "FLASH_SetLatency()" function
- (++) Check that the new number of WS is taken into account by reading FLASH_ACR
- (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
- function
- (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
- using the FLASH_GetPrefetchBufferStatus() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- * @arg RCC_SYSCLKSource_HSI48: HSI48 selected as system clock source, applicable only for STM32F072 devices
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following values:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
- * - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the APB clock (PCLK).
- * @param RCC_HCLK: defines the APB clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB clock = HCLK
- * @arg RCC_HCLK_Div2: APB clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB clock = HCLK/16
- * @retval None
- */
-void RCC_PCLKConfig(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE;
-
- /* Set PPRE[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the ADC clock (ADCCLK).
- * @note This function is obsolete.
- * For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver
- * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived
- * from the HSI14 or APB clock (PCLK).
- * This parameter can be one of the following values:
- * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)
- * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
- * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4
- * @retval None
- */
-void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
-
- /* Clear ADCPRE bit */
- RCC->CFGR &= ~RCC_CFGR_ADCPRE;
- /* Set ADCPRE bits according to RCC_PCLK value */
- RCC->CFGR |= RCC_ADCCLK & 0xFFFF;
-
- /* Clear ADCSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_ADCSW;
- /* Set ADCSW bits according to RCC_ADCCLK value */
- RCC->CFGR3 |= RCC_ADCCLK >> 16;
-}
-
-/**
- * @brief Configures the CEC clock (CECCLK).
- * @param RCC_CECCLK: defines the CEC clock source. This clock is derived
- * from the HSI or LSE clock.
- * This parameter can be one of the following values:
- * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
- * @arg RCC_CECCLK_LSE: CEC clock = LSE
- * @retval None
- */
-void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CECCLK(RCC_CECCLK));
-
- /* Clear CECSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_CECSW;
- /* Set CECSW bits according to RCC_CECCLK value */
- RCC->CFGR3 |= RCC_CECCLK;
-}
-
-/**
- * @brief Configures the I2C1 clock (I2C1CLK).
- * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived
- * from the HSI or System clock.
- * This parameter can be one of the following values:
- * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
- * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
- * @retval None
- */
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
-
- /* Clear I2CSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
- /* Set I2CSW bits according to RCC_I2CCLK value */
- RCC->CFGR3 |= RCC_I2CCLK;
-}
-
-/**
- * @brief Configures the USART1 clock (USART1CLK).
- * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
- * from the HSI or System clock.
- * This parameter can be one of the following values:
- * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)
- * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock
- * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock
- * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock
- * @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK), applicable only for STM32F072 devices
- * @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock, applicable only for STM32F072 devices
- * @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock, applicable only for STM32F072 devices
- * @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock, applicable only for STM32F072 devices
- * @retval None
- */
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
-
- /* Get USART index */
- tmp = (RCC_USARTCLK >> 28);
-
- /* Clear USARTSW[1:0] bit */
- if (tmp == (uint32_t)0x00000001)
- {
- /* Clear USART1SW[1:0] bit */
- RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
- }
- else
- {
- /* Clear USART2SW[1:0] bit */
- RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
- }
-
- /* Set USARTxSW bits according to RCC_USARTCLK value */
- RCC->CFGR3 |= RCC_USARTCLK;
-}
-
-/**
- * @brief Configures the USB clock (USBCLK).
- * This function is only applicable for STM32F072 devices.
- * @param RCC_USBCLK: defines the USB clock source. This clock is derived
- * from the HSI48 or system clock.
- * This parameter can be one of the following values:
- * @arg RCC_USBCLK_HSI48: USB clock = HSI48
- * @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock
- * @retval None
- */
-void RCC_USBCLKConfig(uint32_t RCC_USBCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_USBCLK(RCC_USBCLK));
-
- /* Clear USBSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_USBSW;
- /* Set USBSW bits according to RCC_USBCLK value */
- RCC->CFGR3 |= RCC_USBCLK;
-}
-
-/**
- * @brief Returns the frequencies of the System, AHB and APB busses clocks.
- * @note The frequency returned by this function is not the real frequency
- * in the chip. It is calculated based on the predefined constant and
- * the source selected by RCC_SYSCLKConfig():
- *
- * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
- *
- * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
- *
- * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * @note If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***)
- *
- * @note (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
- *
- * @note (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * return wrong result.
- *
- * @note (***) HSI48_VALUE is a constant defined in stm32f0xx.h file (default value
- * 48 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- pllclk = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- pllclk = (HSE_VALUE / prediv1factor) * pllmull;
- }
- RCC_Clocks->SYSCLK_Frequency = pllclk;
- break;
- case 0x0C: /* HSI48 used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE;
- break;
- default: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE;
- tmp = tmp >> 8;
- presc = APBAHBPrescTable[tmp];
- /* PCLK clock frequency */
- RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* ADCCLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
- {
- /* ADC Clock is HSI14 Osc. */
- RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
- }
- else
- {
- if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
- {
- /* ADC Clock is derived from PCLK/2 */
- RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
- }
- else
- {
- /* ADC Clock is derived from PCLK/4 */
- RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
- }
-
- }
-
- /* CECCLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)
- {
- /* CEC Clock is HSI/244 */
- RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;
- }
- else
- {
- /* CECC Clock is LSE Osc. */
- RCC_Clocks->CECCLK_Frequency = LSE_VALUE;
- }
-
- /* I2C1CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
- {
- /* I2C1 Clock is HSI Osc. */
- RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
- }
- else
- {
- /* I2C1 Clock is System Clock */
- RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* USART1CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
- {
- /* USART1 Clock is PCLK */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
- {
- /* USART1 Clock is System Clock */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
- {
- /* USART1 Clock is LSE Osc. */
- RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
- {
- /* USART1 Clock is HSI Osc. */
- RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
- }
-
- /* USART2CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
- }
-
- /* USBCLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW)
- {
- /* USB Clock is HSI48 */
- RCC_Clocks->USBCLK_Frequency = HSI48_VALUE;
- }
- else
- {
- /* USB Clock is PLL clock */
- RCC_Clocks->USBCLK_Frequency = pllclk;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- #####Peripheral clocks configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the Peripheral clocks.
- (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE
- divided by 32).
- (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
- except internal SRAM, Flash and SWD. Before to start using a peripheral you
- have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),
- RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
- (#) To reset the peripherals configuration (to the default state after device reset)
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
- RCC_APB1PeriphResetCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the RTC
- * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- *
- * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
- * RTC clock source).
- *
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- /* Select the RTC clock source */
- RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->BDCR |= RCC_BDCR_RTCEN;
- }
- else
- {
- RCC->BDCR &= ~RCC_BDCR_RTCEN;
- }
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_BDCR register.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->BDCR |= RCC_BDCR_BDRST;
- }
- else
- {
- RCC->BDCR &= ~RCC_BDCR_BDRST;
- }
-}
-
-/**
- * @brief Enables or disables the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
- * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
- * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
- * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
- * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices
- * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
- * @arg RCC_AHBPeriph_TS: TS clock
- * @arg RCC_AHBPeriph_CRC: CRC clock
- * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
- * @arg RCC_AHBPeriph_SRAM: SRAM clock
- * @arg RCC_AHBPeriph_DMA1: DMA1 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBENR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBENR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_TIM15: TIM15 clock
- * @arg RCC_APB2Periph_TIM16: TIM16 clock
- * @arg RCC_APB2Periph_TIM17: TIM17 clock
- * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F042 and STM32F072 devices
- * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F042 and STM32F072 devices
- * @arg RCC_APB1Periph_CRS: CRS clock , applicable only for STM32F042 and STM32F072 devices
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices
- * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB peripheral reset.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
- * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
- * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
- * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
- * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices
- * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
- * @arg RCC_AHBPeriph_TS: TS clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBRSTR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBRSTR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_TIM15: TIM15 clock
- * @arg RCC_APB2Periph_TIM16: TIM16 clock
- * @arg RCC_APB2Periph_TIM17: TIM17 clock
- * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_USART4: USART4 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_CRS: CRS clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices
- * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051 and STM32F072 devices
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
- * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
- * automatically generated. The NMI will be executed indefinitely, and
- * since NMI has higher priority than any other IRQ (and main program)
- * the application will be stacked in the NMI ISR unless the CSS interrupt
- * pending bit is cleared.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: PLL clock ready
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
- * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready, applicable only for STM32F072 devices
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
-
- if (tmp == 0) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 1) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else if (tmp == 2) /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
- else /* The flag to check is in CR2 register */
- {
- statusreg = RCC->CR2;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
-
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF,
- * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
- * RCC_FLAG_LPWRRST.
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_rcc.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,618 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_rcc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the RCC
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_RCC_H
-#define __STM32F0XX_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-typedef struct
-{
- uint32_t SYSCLK_Frequency;
- uint32_t HCLK_Frequency;
- uint32_t PCLK_Frequency;
- uint32_t ADCCLK_Frequency;
- uint32_t CECCLK_Frequency;
- uint32_t I2C1CLK_Frequency;
- uint32_t USART1CLK_Frequency;
- uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 devices */
- uint32_t USBCLK_Frequency; /*!< Only applicable for STM32F072 devices */
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_HSE_configuration
- * @{
- */
-
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source
- * @{
- */
-
-#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
-#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */
-#define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */
-#define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */
-#define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */
-
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
- ((SOURCE) == RCC_PLLSource_HSI48) || \
- ((SOURCE) == RCC_PLLSource_HSI) || \
- ((SOURCE) == RCC_PLLSource_HSE) || \
- ((SOURCE) == RCC_PLLSource_PREDIV1))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Multiplication_Factor
- * @{
- */
-
-#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
-#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
-#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
-#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
-#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
-#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
-#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
-#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
-#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
-#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
-#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
-#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
-#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
-#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
-#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
- ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
- ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
- ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
- ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
- ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
- ((MUL) == RCC_PLLMul_16))
-/**
- * @}
- */
-
-/** @defgroup RCC_PREDIV1_division_factor
- * @{
- */
-#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
-#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
-#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
-#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
-#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
-#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
-#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
-#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
-#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
-#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
-#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
-#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
-#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
-#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
-#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
-#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
-
-#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
- ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
- ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
- ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
- ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
- ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
- ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
- ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
-#define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */
-
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_HSI48) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
- ((HCLK) == RCC_SYSCLK_Div512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB_Clock_Source
- * @{
- */
-
-#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1
-#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2
-#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4
-#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8
-#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
- ((PCLK) == RCC_HCLK_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_ADC_clock_source
- * @{
- */
-/* These defines are obsolete and kept for legacy purpose only.
-Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */
-#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000)
-#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000)
-#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000)
-
-#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
- ((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_CEC_clock_source
- * @{
- */
-
-#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000)
-#define RCC_CECCLK_LSE RCC_CFGR3_CECSW
-
-#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_I2C_clock_source
- * @{
- */
-
-#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
-#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
-
-#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_USB_clock_source
- * @brief Applicable only for STM32F072 devices
- * @{
- */
-
-#define RCC_USBCLK_HSI48 ((uint32_t)0x00000000)
-#define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW
-
-#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_USART_clock_source
- * @{
- */
-
-#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
-#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
-#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
-#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
-
-#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 devices */
-#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 devices */
-#define RCC_USART2CLK_LSE ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 devices */
-#define RCC_USART2CLK_HSI ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 devices */
-
-#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \
- ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART1CLK_LSE) || \
- ((USARTCLK) == RCC_USART1CLK_HSI) || \
- ((USARTCLK) == RCC_USART2CLK_PCLK) || \
- ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART2CLK_LSE) || \
- ((USARTCLK) == RCC_USART2CLK_HSI))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_HSI14RDY ((uint8_t)0x20)
-#define RCC_IT_HSI48RDY ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */
-#define RCC_IT_CSS ((uint8_t)0x80)
-
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
-
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
- ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY))
-
-#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration
- * @{
- */
-
-#define RCC_LSE_OFF ((uint32_t)0x00000000)
-#define RCC_LSE_ON RCC_BDCR_LSEON
-#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source
- * @{
- */
-
-#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
-#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
-#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
-
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Drive_Configuration
- * @{
- */
-
-#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
-#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
-#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
-#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
-#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
- ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Peripherals
- * @{
- */
-
-#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
-#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
-#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
-#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
-#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN /*!< Only applicable for STM32F072 devices */
-#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
-#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
-#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
-#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
-#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
-#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
-
-#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFAA) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFFF) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripherals
- * @{
- */
-
-#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
-#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
-#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
-#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
-#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
-#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
-#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
-#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
-#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripherals
- * @{
- */
-
-#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN /*!< Only applicable for STM32F051 and STM32F072 devices */
-#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
-#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
-#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN /*!< Only applicable for STM32F072 devices */
-#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN
-#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
-#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
-#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
-#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN /*!< Only applicable for STM32F072 devices */
-#define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN /*!< Only applicable for STM32F072 devices */
-#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
-#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
-#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN /*!< Only applicable for STM32F072 and STM32F042 devices */
-#define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN /*!< Only applicable for STM32F072 and STM32F042 devices */
-#define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN /*!< Only applicable for STM32F072 and STM32F042 devices*/
-#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
-#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN /*!< Only applicable for STM32F051 and STM32F072 devices */
-#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN /*!< Only applicable for STM32F051, STM32F042 and STM32F072 devices */
-
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8511B6CC) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO_Clock_Source
- * @{
- */
-
-#define RCC_MCOSource_NoClock ((uint8_t)0x00)
-#define RCC_MCOSource_HSI14 ((uint8_t)0x01)
-#define RCC_MCOSource_LSI ((uint8_t)0x02)
-#define RCC_MCOSource_LSE ((uint8_t)0x03)
-#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
-#define RCC_MCOSource_HSI ((uint8_t)0x05)
-#define RCC_MCOSource_HSE ((uint8_t)0x06)
-#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
-#define RCC_MCOSource_HSI48 ((uint8_t)0x08) /*!< Only applicable for STM32F072 devices */
-#define RCC_MCOSource_PLLCLK ((uint8_t)0x87)
-
-#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \
- ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \
- ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
- ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \
- ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOPrescaler
- * @{
- */
-#if !defined (STM32F051)
-#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
-#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
-#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
-#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
-#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
-#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
-#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
-#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
-
-#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
- ((PRESCALER) == RCC_MCOPrescaler_2) || \
- ((PRESCALER) == RCC_MCOPrescaler_4) || \
- ((PRESCALER) == RCC_MCOPrescaler_8) || \
- ((PRESCALER) == RCC_MCOPrescaler_16) || \
- ((PRESCALER) == RCC_MCOPrescaler_32) || \
- ((PRESCALER) == RCC_MCOPrescaler_64) || \
- ((PRESCALER) == RCC_MCOPrescaler_128))
-#endif /* STM32F051 */
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
-#define RCC_FLAG_HSERDY ((uint8_t)0x11)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
-#define RCC_FLAG_LSERDY ((uint8_t)0x21)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
-#define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57)
-#define RCC_FLAG_OBLRST ((uint8_t)0x59)
-#define RCC_FLAG_PINRST ((uint8_t)0x5A)
-#define RCC_FLAG_PORRST ((uint8_t)0x5B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
-#define RCC_FLAG_HSI14RDY ((uint8_t)0x61)
-#define RCC_FLAG_HSI48RDY ((uint8_t)0x71) /*!< Only applicable for STM32F072 devices */
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \
- ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \
- ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \
- ((FLAG) == RCC_FLAG_V18PWRRSTF))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue);
-void RCC_HSI14Cmd(FunctionalState NewState);
-void RCC_HSI14ADCRequestCmd(FunctionalState NewState);
-void RCC_LSEConfig(uint32_t RCC_LSE);
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
-void RCC_LSICmd(FunctionalState NewState);
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
-void RCC_PLLCmd(FunctionalState NewState);
-void RCC_HSI48Cmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
-uint32_t RCC_GetHSI48CalibrationValue(void); /*!< Only applicable for STM32F072 devices */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-#ifdef STM32F051
-void RCC_MCOConfig(uint8_t RCC_MCOSource);
-#else
-void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
-#endif /* STM32F051 */
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLKConfig(uint32_t RCC_HCLK);
-void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete.
- For proper ADC clock selection, refer to
- ADC_ClockModeConfig() in the ADC driver */
-void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
-void RCC_USBCLKConfig(uint32_t RCC_USBCLK); /*!< Only applicable for STM32F042 and STM32F072 devices */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_RCC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_rtc.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2528 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_rtc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A) configuration
- * + Daylight Saving configuration
- * + Output pin Configuration
- * + Digital Calibration configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + Output Type Config configuration
- * + Shift control synchronisation
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### Backup Domain Operating Condition #####
- ===============================================================================
- [..] The real-time clock (RTC) and the RTC backup registers can be powered
- from the VBAT voltage when the main VDD supply is powered off.
- To retain the content of the RTC backup registers and supply the RTC
- when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC to operate even when the main digital supply (VDD)
- is turned off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) PC13 to PC15 I/Os I/Os (when available)
-
- [..] When the backup domain is supplied by VDD (analog switch connected
- to VDD), the following functions are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected
- to VBAT because VDD is not present), the following functions are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_AF1 pin
-
- ##### Backup Domain Reset #####
- ===============================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR
- register to their reset values.
- A backup domain reset is generated when one of the following events
- occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR). You can use the
- RCC_BackupResetCmd().
- (#) VDD or VBAT power on, if both supplies have previously been
- powered off.
-
- ##### Backup Domain Access #####
- ===============================================================================
- [..] After reset, the backup domain (RTC registers and RTC backup data
- registers) is protected against possible unwanted write accesses.
- [..] To enable access to the Backup Domain and RTC registers, proceed as follows:
- (#) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.
- (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.
- (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.
-
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (+) Enable the backup domain access (see description in the section above)
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
- RTC hour format using the RTC_Init() function.
-
- ***Time and Date configuration ***
- ==================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
- and RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
- functions.
- (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
- (+) Use the RTC_DayLightSavingConfig() function to add or sub one
- hour to the RTC Calendar.
-
- ***Alarm configuration ***
- ==========================
- [..]
- (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
- (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
- (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
- (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
-
- ***RTC Wakeup configuration***
- ==========================
- [..]
- (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
- function.
- (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter()
- function
- (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
- (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
- function.
-
- ***Outputs configuration ***
- ============================
- [..] The RTC has 2 different outputs:
- (+) AFO_ALARM: this output is used to manage the RTC Alarm A.
- To output the selected RTC signal on RTC_AF1 pin, use the
- RTC_OutputConfig() function.
- (+) AFO_CALIB: this output is 512Hz signal or 1Hz .
- To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
- function.
-
- ***Original Digital Calibration configuration ***
- =================================
- [..] Configure the RTC Original Digital Calibration Value and the corresponding
- calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
- function.
-
- ***TimeStamp configuration ***
- ==============================
- [..]
- (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp
- using the RTC_TimeStampCmd() function.
- (+) To read the RTC TimeStamp Time and Date register, use the
- RTC_GetTimeStamp() function.
- (+) To read the RTC TimeStamp SubSecond register, use the
- RTC_GetTimeStampSubSecond() function.
-
- ***Tamper configuration ***
- ===========================
- [..]
- (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
- function.
- (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
- filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function
- (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
- function.
- (+) Configure the Tamper precharge or discharge duration using
- RTC_TamperPinsPrechargeDuration() function.
- (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
- (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
- (+) Enable the Time stamp on Tamper detection event using
- RTC_TSOnTamperDetecCmd() function.
-
- ***Backup Data Registers configuration ***
- ==========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
- function.
- (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
- function.
-
- ##### RTC and low power modes #####
- ===============================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper
- event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop
- and Standby lowpower modes.
- The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC
- clock source is LSE or LSI.
-
- ##### Selection of RTC_AF1 alternate functions #####
- ===============================================================================
- [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
- (+) AFO_ALARM output
- (+) AFO_CALIB output
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
-
- +------------------------------------------------------------------------------------------+
- | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE |
- | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM |
- | and function | | | | | |Configuration |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Alarm out | | | | | Don't | |
- | output OD | 1 | 0 |Don't care | Don't care | care | 0 |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Alarm out | | | | | Don't | |
- | output PP | 1 | 0 |Don't care | Don't care | care | 1 |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Calibration out | | | | | Don't | |
- | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TAMPER input | | | | | Don't | |
- | floating | 0 | 0 | 1 | 0 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TIMESTAMP and | | | | | Don't | |
- | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |
- | floating | | | | | | |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TIMESTAMP input | | | | | Don't | |
- | floating | 0 | 0 | 0 | 1 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care |
- +------------------------------------------------------------------------------------------+
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_rtc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RTC
- * @brief RTC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \
- RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | \
- RTC_FLAG_SHPF))
-
-#define INITMODE_TIMEOUT ((uint32_t) 0x00004000)
-#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)
-#define RECALPF_TIMEOUT ((uint32_t) 0x00001000)
-#define SHPF_TIMEOUT ((uint32_t) 0x00001000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t RTC_ByteToBcd2(uint8_t Value);
-static uint8_t RTC_Bcd2ToByte(uint8_t Value);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTC_Private_Functions
- * @{
- */
-
-/** @defgroup RTC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to initialize and configure the RTC
- Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
- Write protection, enter and exit the RTC initialization mode, RTC registers
- synchronization check and reference clock detection enable.
-
- (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
- It is split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
- (++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize consumption.
- (#) All RTC registers are Write protected. Writing to the RTC registers
- is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To Configure the RTC Calendar, user application should enter
- initialization mode. In this mode, the calendar counter is stopped
- and its value can be updated. When the initialization sequence is
- complete, the calendar restarts counting after 4 RTCCLK cycles.
- (#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
- the software must first clear the RSF flag. The software must then
- wait until it is set again before reading the calendar, which means
- that the calendar registers have been correctly copied into the
- RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function
- implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
- * registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are deinitialized
- * - ERROR: RTC registers are not deinitialized
- */
-ErrorStatus RTC_DeInit(void)
-{
- ErrorStatus status = ERROR;
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Reset TR, DR and CR registers */
- RTC->TR = (uint32_t)0x00000000;
- RTC->WUTR = (uint32_t)0x0000FFFF;
- RTC->DR = (uint32_t)0x00002101;
- RTC->CR &= (uint32_t)0x00000000;
- RTC->PRER = (uint32_t)0x007F00FF;
- RTC->ALRMAR = (uint32_t)0x00000000;
- RTC->SHIFTR = (uint32_t)0x00000000;
- RTC->CALR = (uint32_t)0x00000000;
- RTC->ALRMASSR = (uint32_t)0x00000000;
-
- /* Reset ISR register and exit initialization mode */
- RTC->ISR = (uint32_t)0x00000000;
-
- /* Reset Tamper and alternate functions configuration register */
- RTC->TAFCR = 0x00000000;
-
- /* Wait till the RTC RSF flag is set */
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
-
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Initializes the RTC registers according to the specified parameters
- * in RTC_InitStruct.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
- * the configuration information for the RTC peripheral.
- * @note The RTC Prescaler register is write protected and can be written in
- * initialization mode only.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are initialized
- * - ERROR: RTC registers are not initialized
- */
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
- assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
- assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Clear RTC CR FMT Bit */
- RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
- /* Set RTC_CR register */
- RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
-
- /* Configure the RTC PRER */
- RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
- RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_InitStruct member with its default value.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
-{
- /* Initialize the RTC_HourFormat member */
- RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
-
- /* Initialize the RTC_AsynchPrediv member */
- RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
-
- /* Initialize the RTC_SynchPrediv member */
- RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
-}
-
-/**
- * @brief Enables or disables the RTC registers write protection.
- * @note All the RTC registers are write protected except for RTC_ISR[13:8],
- * RTC_TAFCR and RTC_BKPxR.
- * @note Writing a wrong key reactivates the write protection.
- * @note The protection mechanism is not affected by system reset.
- * @param NewState: new state of the write protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_WriteProtectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
- }
- else
- {
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
- }
-}
-
-/**
- * @brief Enters the RTC Initialization mode.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC is in Init mode
- * - ERROR: RTC is not in Init mode
- */
-ErrorStatus RTC_EnterInitMode(void)
-{
- __IO uint32_t initcounter = 0x00;
- ErrorStatus status = ERROR;
- uint32_t initstatus = 0x00;
-
- /* Check if the Initialization mode is set */
- if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- /* Set the Initialization mode */
- RTC->ISR = (uint32_t)RTC_INIT_MASK;
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- do
- {
- initstatus = RTC->ISR & RTC_ISR_INITF;
- initcounter++;
- } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_INITF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = SUCCESS;
- }
-
- return (status);
-}
-
-/**
- * @brief Exits the RTC Initialization mode.
- * @note When the initialization sequence is complete, the calendar restarts
- * counting after 4 RTCCLK cycles.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval None
- */
-void RTC_ExitInitMode(void)
-{
- /* Exit Initialization mode */
- RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
-}
-
-/**
- * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are synchronised
- * - ERROR: RTC registers are not synchronised
- */
-ErrorStatus RTC_WaitForSynchro(void)
-{
- __IO uint32_t synchrocounter = 0;
- ErrorStatus status = ERROR;
- uint32_t synchrostatus = 0x00;
-
- if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)
- {
- /* Bypass shadow mode */
- status = SUCCESS;
- }
- else
- {
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear RSF flag */
- RTC->ISR &= (uint32_t)RTC_RSF_MASK;
-
- /* Wait the registers to be synchronised */
- do
- {
- synchrostatus = RTC->ISR & RTC_ISR_RSF;
- synchrocounter++;
- } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_RSF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
- }
-
- return (status);
-}
-
-/**
- * @brief Enables or disables the RTC reference clock detection.
- * @param NewState: new state of the RTC reference clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC reference clock detection is enabled
- * - ERROR: RTC reference clock detection is disabled
- */
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Enable the RTC reference clock detection */
- RTC->CR |= RTC_CR_REFCKON;
- }
- else
- {
- /* Disable the RTC reference clock detection */
- RTC->CR &= ~RTC_CR_REFCKON;
- }
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or Disables the Bypass Shadow feature.
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @param NewState: new state of the Bypass Shadow feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
-*/
-void RTC_BypassShadowCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Set the BYPSHAD bit */
- RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
- }
- else
- {
- /* Reset the BYPSHAD bit */
- RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group2 Time and Date configuration functions
- * @brief Time and Date configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Time and Date configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to program and read the RTC
- Calendar (Time and Date).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the RTC current time.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
- * the time configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Time register is configured
- * - ERROR: RTC Time register is not configured
- */
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
- }
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
- ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16));
- }
- else
- {
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
- (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_TR register */
- RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = SUCCESS;
- }
-
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_TimeStruct member with its default value
- * (Time = 00h:00min:00sec).
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
-{
- /* Time = 00h:00min:00sec */
- RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
- RTC_TimeStruct->RTC_Hours = 0;
- RTC_TimeStruct->RTC_Minutes = 0;
- RTC_TimeStruct->RTC_Seconds = 0;
-}
-
-/**
- * @brief Get the RTC current Time.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contain the returned current time configuration.
- * @retval None
- */
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
- }
-}
-
-/**
- * @brief Gets the RTC current Calendar Subseconds value.
- * @note This function freeze the Time and Date registers after reading the
- * SSR register.
- * @param None
- * @retval RTC current Calendar Subseconds value.
- */
-uint32_t RTC_GetSubSecond(void)
-{
- uint32_t tmpreg = 0;
-
- /* Get subseconds values from the correspondent registers*/
- tmpreg = (uint32_t)(RTC->SSR);
-
- /* Read DR register to unfroze calendar registers */
- (void) (RTC->DR);
-
- return (tmpreg);
-}
-
-/**
- * @brief Set the RTC current date.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
- * the date configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Date register is configured
- * - ERROR: RTC Date register is not configured
- */
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
- {
- RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
- }
- if (RTC_Format == RTC_Format_BIN)
- {
- assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
- assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
- assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
- }
- else
- {
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- assert_param(IS_RTC_MONTH(tmpreg));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- assert_param(IS_RTC_DATE(tmpreg));
- }
- assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
- (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_DateStruct->RTC_Date) | \
- (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
- ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_DR register */
- RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = SUCCESS;
- }
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_DateStruct member with its default value
- * (Monday, January 01 xx00).
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
-{
- /* Monday, January 01 xx00 */
- RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
- RTC_DateStruct->RTC_Date = 1;
- RTC_DateStruct->RTC_Month = RTC_Month_January;
- RTC_DateStruct->RTC_Year = 0;
-}
-
-/**
- * @brief Get the RTC current date.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will
- * contain the returned current date configuration.
- * @retval None
- */
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
- RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
- RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
- RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group3 Alarms configuration functions
- * @brief Alarms (Alarm A) configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Alarms (Alarm A and Alarm B) configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to program and read the RTC
- Alarms.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the specified RTC Alarm.
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the RTC_AlarmCmd(DISABLE)).
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
- * contains the alarm configuration parameters.
- * @retval None
- */
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm register */
- RTC->ALRMAR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Fills each RTC_AlarmStruct member with its default value
- * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
- * all fields are masked).
- * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- /* Alarm Time Settings : Time = 00h:00mn:00sec */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
-
- /* Alarm Date Settings : Date = 1st day of the month */
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
-
- /* Alarm Masks Settings : Mask = all fields are not masked */
- RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
- * contains the output alarm configuration values.
- * @retval None
- */
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
-
- /* Get the RTC_ALRMAR register */
- tmpreg = (uint32_t)(RTC->ALRMAR);
-
- /* Fill the structure with the read parameters */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
- RTC_ALRMAR_HU)) >> 16);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
- RTC_ALRMAR_MNU)) >> 8);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
- RTC_ALRMAR_SU));
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
-
- if (RTC_Format == RTC_Format_BIN)
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Hours);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Minutes);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Seconds);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- }
-}
-
-/**
- * @brief Enables or disables the specified RTC Alarm.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be any combination of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param NewState: new state of the specified alarm.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Alarm is enabled/disabled
- * - ERROR: RTC Alarm is not enabled/disabled
- */
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
-{
- __IO uint32_t alarmcounter = 0x00;
- uint32_t alarmstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm state */
- if (NewState != DISABLE)
- {
- RTC->CR |= (uint32_t)RTC_Alarm;
-
- status = SUCCESS;
- }
- else
- {
- /* Disable the Alarm in RTC_CR register */
- RTC->CR &= (uint32_t)~RTC_Alarm;
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- do
- {
- alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
- alarmcounter++;
- } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
-
- if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Configure the RTC AlarmA/B Subseconds value and mask.
- * @note This function is performed only when the Alarm is disabled.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param RTC_AlarmSubSecondValue: specifies the Subseconds value.
- * This parameter can be a value from 0 to 0x00007FFF.
- * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask.
- * This parameter can be any combination of the following values:
- * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.
- * There is no comparison on sub seconds for Alarm.
- * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.
- * Only SS[0] is compared
- * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.
- * Only SS[1:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.
- * Only SS[2:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.
- * Only SS[3:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.
- * Only SS[4:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.
- * Only SS[5:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.
- * Only SS[6:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.
- * Only SS[7:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.
- * Only SS[8:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
- * Only SS[9:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
- * Only SS[10:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
- * Only SS[11:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
- * Only SS[12:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
- * Only SS[13:0] are compared
- * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm
- * @retval None
- */
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm A or Alarm B SubSecond registers */
- tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24));
-
- /* Configure the AlarmA SubSecond register */
- RTC->ALRMASSR = tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
-}
-
-/**
- * @brief Gets the RTC Alarm Subseconds value.
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param None
- * @retval RTC Alarm Subseconds value.
- */
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
-{
- uint32_t tmpreg = 0;
-
- /* Get the RTC_ALRMAR register */
- tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
-
- return (tmpreg);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group4 WakeUp Timer configuration functions
- * @brief WakeUp Timer configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp Timer configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to program and read the RTC WakeUp.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC Wakeup clock source.
- * This function is available for STM32F072 devices.
- * @note The WakeUp Clock source can only be changed when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpClock: Wakeup Clock source.
- * This parameter can be one of the following values:
- * @arg RTC_WakeUpClock_RTCCLK_Div16
- * @arg RTC_WakeUpClock_RTCCLK_Div8
- * @arg RTC_WakeUpClock_RTCCLK_Div4
- * @arg RTC_WakeUpClock_RTCCLK_Div2
- * @arg RTC_WakeUpClock_CK_SPRE_16bits
- * @arg RTC_WakeUpClock_CK_SPRE_17bits
- * @retval None
- */
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- RTC->CR |= (uint32_t)RTC_WakeUpClock;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the RTC Wakeup counter.
- * This function is available for STM32F072 devices.
- * @note The RTC WakeUp counter can only be written when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpCounter: specifies the WakeUp counter.
- * This parameter can be a value from 0x0000 to 0xFFFF.
- * @retval None
- */
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Wakeup Timer counter */
- RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC WakeUp timer counter value.
- * This function is available for STM32F072 devices.
- * @param None
- * @retval The RTC WakeUp Counter value.
- */
-uint32_t RTC_GetWakeUpCounter(void)
-{
- /* Get the counter value */
- return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
-}
-
-/**
- * @brief Enables or Disables the RTC WakeUp timer.
- * This function is available for STM32F072 devices.
- * @param NewState: new state of the WakeUp timer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
-{
- __IO uint32_t wutcounter = 0x00;
- uint32_t wutwfstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the Wakeup Timer */
- RTC->CR |= (uint32_t)RTC_CR_WUTE;
- status = SUCCESS;
- }
- else
- {
- /* Disable the Wakeup Timer */
- RTC->CR &= (uint32_t)~RTC_CR_WUTE;
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- do
- {
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
- wutcounter++;
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group5 Daylight Saving configuration functions
- * @brief Daylight Saving configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp Timer configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to program and read the RTC WakeUp.
-
- This section provide functions allowing to configure the RTC DayLight Saving.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Adds or substract one hour from the current time.
- * @param RTC_DayLightSaveOperation: the value of hour adjustment.
- * This parameter can be one of the following values:
- * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
- * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
- * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit
- * in CR register to store the operation.
- * This parameter can be one of the following values:
- * @arg RTC_StoreOperation_Reset: BCK Bit Reset
- * @arg RTC_StoreOperation_Set: BCK Bit Set
- * @retval None
- */
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
-{
- /* Check the parameters */
- assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
- assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_BCK);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC Day Light Saving stored operation.
- * @param None
- * @retval RTC Day Light Saving stored operation.
- * - RTC_StoreOperation_Reset
- * - RTC_StoreOperation_Set
- */
-uint32_t RTC_GetStoreOperation(void)
-{
- return (RTC->CR & RTC_CR_BCK);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group6 Output pin Configuration function
- * @brief Output pin Configuration function
- *
-@verbatim
- ===============================================================================
- ##### Output pin Configuration function #####
- ===============================================================================
- [..] This section provide functions allowing to configure the RTC Output source.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC output source (AFO_ALARM).
- * @param RTC_Output: Specifies which signal will be routed to the RTC output.
- * This parameter can be one of the following values:
- * @arg RTC_Output_Disable: No output selected
- * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
- * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output, available only for STM32F072 devices
- * @param RTC_OutputPolarity: Specifies the polarity of the output signal.
- * This parameter can be one of the following:
- * @arg RTC_OutputPolarity_High: The output pin is high when the
- * ALRAF is high (depending on OSEL)
- * @arg RTC_OutputPolarity_Low: The output pin is low when the
- * ALRAF is high (depending on OSEL)
- * @retval None
- */
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT(RTC_Output));
- assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
-
- /* Configure the output selection and polarity */
- RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group7 Digital Calibration configuration functions
- * @brief Digital Calibration configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Digital Calibration configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the RTC clock to be output through the relative pin.
- * @param NewState: new state of the digital calibration Output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_CalibOutputCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the RTC clock output */
- RTC->CR |= (uint32_t)RTC_CR_COE;
- }
- else
- {
- /* Disable the RTC clock output */
- RTC->CR &= (uint32_t)~RTC_CR_COE;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param RTC_CalibOutput: Select the Calibration output Selection .
- * This parameter can be one of the following values:
- * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
- * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
- * @retval None
-*/
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /*clear flags before config*/
- RTC->CR &= (uint32_t)~(RTC_CR_CALSEL);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)RTC_CalibOutput;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the Smooth Calibration Settings.
- * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values:
- * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
- * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
- * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
- * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
- * This parameter can be one of the following values:
- * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
- * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
- * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
- * This parameter can be one any value from 0 to 0x000001FF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Calib registers are configured
- * - ERROR: RTC Calib registers are not configured
-*/
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue)
-{
- ErrorStatus status = ERROR;
- uint32_t recalpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
- assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* check if a calibration is pending*/
- if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
- {
- /* wait until the Calibration is completed*/
- while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
- {
- recalpfcount++;
- }
- }
-
- /* check if the calibration pending is completed or if there is no calibration operation at all*/
- if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
- {
- /* Configure the Smooth calibration settings */
- RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
-
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Group8 TimeStamp configuration functions
- * @brief TimeStamp configuration functions
- *
-@verbatim
- ===============================================================================
- ##### TimeStamp configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or Disables the RTC TimeStamp functionality with the
- * specified time stamp pin stimulating edge.
- * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following:
- * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising
- * edge of the related pin.
- * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param NewState: new state of the TimeStamp.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- /* Get the new configuration */
- if (NewState != DISABLE)
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
- }
- else
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge);
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- RTC->CR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Get the RTC TimeStamp value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contains the TimeStamp time values.
- * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will
- * contains the TimeStamp date values.
- * @retval None
- */
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct)
-{
- uint32_t tmptime = 0, tmpdate = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the TimeStamp time and date registers values */
- tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
- tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
-
- /* Fill the Time structure fields with the read parameters */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-
- /* Fill the Date structure fields with the read parameters */
- RTC_StampDateStruct->RTC_Year = 0;
- RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the Time structure parameters to Binary format */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
-
- /* Convert the Date structure parameters to Binary format */
- RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
- RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @brief Get the RTC timestamp Subseconds value.
- * @param None
- * @retval RTC current timestamp Subseconds value.
- */
-uint32_t RTC_GetTimeStampSubSecond(void)
-{
- /* Get timestamp subseconds values from the correspondent registers */
- return (uint32_t)(RTC->TSSSR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group9 Tampers configuration functions
- * @brief Tampers configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Tampers configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the select Tamper pin edge.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be any combination of the following values:
- * @arg RTC_Tamper_1: Select Tamper 1.
- * @arg RTC_Tamper_2: Select Tamper 2.
- * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
- * stimulates tamper event.
- * This parameter can be one of the following values:
- * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
- * @retval None
- */
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
-
- if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));
- }
- else
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);
- }
-}
-
-/**
- * @brief Enables or Disables the Tamper detection.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be any combination of the following values:
- * @arg RTC_Tamper_1: Select Tamper 1.
- * @arg RTC_Tamper_2: Select Tamper 2.
- * @param NewState: new state of the tamper pin.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_Tamper;
- }
- else
- {
- /* Disable the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_Tamper;
- }
-}
-
-/**
- * @brief Configures the Tampers Filter.
- * @param RTC_TamperFilter: Specifies the tampers filter.
- * This parameter can be one of the following values:
- * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
- * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
- * samples at the active level
- * @retval None
- */
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
-
- /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
-}
-
-/**
- * @brief Configures the Tampers Sampling Frequency.
- * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
- * This parameter can be one of the following values:
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 32768
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 16384
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 8192
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 4096
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 2048
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 1024
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 512
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 256
- * @retval None
- */
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
-
- /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
-}
-
-/**
- * @brief Configures the Tampers Pins input Precharge Duration.
- * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
- * Precharge Duration.
- * This parameter can be one of the following values:
- * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
- * @retval None
- */
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
-
- /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
-}
-
-/**
- * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
- * @note The timestamp is valid even the TSE bit in tamper control register
- * is reset.
- * @param NewState: new state of the timestamp on tamper event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Save timestamp on tamper detection event */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
- }
- else
- {
- /* Tamper detection does not cause a timestamp to be saved */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;
- }
-}
-
-/**
- * @brief Enables or Disables the Precharge of Tamper pin.
- * @param NewState: new state of tamper pull up.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperPullUpCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable precharge of the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS;
- }
- else
- {
- /* Disable precharge of the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group10 Backup Data Registers configuration functions
- * @brief Backup Data Registers configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Backup Data Registers configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
- * specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
- * @retval None
- */
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @retval None
- */
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group11 Output Type Config configuration functions
- * @brief Output Type Config configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Output Type Config configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC Output Pin mode.
- * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.
- * This parameter can be one of the following values:
- * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in
- * Open Drain mode.
- * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in
- * Push Pull mode.
- * @retval None
- */
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
- RTC->TAFCR |= (uint32_t)(RTC_OutputType);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group12 Shift control synchronisation functions
- * @brief Shift control synchronisation functions
- *
-@verbatim
- ===============================================================================
- ##### Shift control synchronisation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Synchronization Shift Control Settings.
- * @note When REFCKON is set, firmware must not write to Shift control register
- * @param RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar.
- * This parameter can be one of the following values :
- * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar.
- * @arg RTC_ShiftAdd1S_Reset: No effect.
- * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
- * This parameter can be one any value from 0 to 0x7FFF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Shift registers are configured
- * - ERROR: RTC Shift registers are not configured
-*/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
-{
- ErrorStatus status = ERROR;
- uint32_t shpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
- assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Check if a Shift is pending*/
- if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
- {
- /* Wait until the shift is completed*/
- while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
- {
- shpfcount++;
- }
- }
-
- /* Check if the Shift pending is completed or if there is no Shift operation at all*/
- if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
- {
- /* check if the reference clock detection is disabled */
- if((RTC->CR & RTC_CR_REFCKON) == RESET)
- {
- /* Configure the Shift settings */
- RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group13 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] All RTC interrupts are connected to the EXTI controller.
-
- (+) To enable the RTC Alarm interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 17 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()
- function.
- (++) Configure the RTC to generate RTC alarms (Alarm A) using
- the RTC_SetAlarm() and RTC_AlarmCmd() functions.
-
- (+) To enable the RTC Tamper interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
- function.
- (++) Configure the RTC to detect the RTC tamper event using the
- RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
-
- (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
- function.
- (++) Configure the RTC to detect the RTC time-stamp event using the
- RTC_TimeStampCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RTC interrupts.
- * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt mask
- * @arg RTC_IT_WUT: WakeUp Timer interrupt mask, available only for STM32F072 devices
- * @arg RTC_IT_ALRA: Alarm A interrupt mask
- * @arg RTC_IT_TAMP: Tamper event interrupt mask
- * @param NewState: new state of the specified RTC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CONFIG_IT(RTC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- else
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Checks whether the specified RTC flag is set or not.
- * @param RTC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RTC_FLAG_RECALPF: RECALPF event flag
- * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_INITF: Initialization mode flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @arg RTC_FLAG_INITS: Registers Configured flag
- * @retval The new state of RTC_FLAG (SET or RESET).
- */
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
-
- /* Get all the flags */
- tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
-
- /* Return the status of the flag */
- if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's pending flags.
- * @param RTC_FLAG: specifies the RTC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @retval None
- */
-void RTC_ClearFlag(uint32_t RTC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
-
- /* Clear the Flags in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Checks whether the specified RTC interrupt has occurred or not.
- * @param RTC_IT: specifies the RTC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper1 event interrupt
- * @arg RTC_IT_TAMP2: Tamper2 event interrupt
- * @retval The new state of RTC_IT (SET or RESET).
- */
-ITStatus RTC_GetITStatus(uint32_t RTC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_IT(RTC_IT));
-
- /* Get the TAMPER Interrupt enable bit and pending bit */
- tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
-
- /* Get the Interrupt enable Status */
- enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
-
- /* Get the Interrupt pending bit */
- tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
-
- /* Get the status of the Interrupt */
- if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's interrupt pending bits.
- * @param RTC_IT: specifies the RTC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper1 event interrupt
- * @arg RTC_IT_TAMP2: Tamper2 event interrupt
- * @retval None
- */
-void RTC_ClearITPendingBit(uint32_t RTC_IT)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_IT(RTC_IT));
-
- /* Get the RTC_ISR Interrupt pending bits mask */
- tmpreg = (uint32_t)(RTC_IT >> 4);
-
- /* Clear the interrupt pending bits in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Converts a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted.
- * @retval Converted byte
- */
-static uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
- uint8_t bcdhigh = 0;
-
- while (Value >= 10)
- {
- bcdhigh++;
- Value -= 10;
- }
-
- return ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted.
- * @retval Converted word
- */
-static uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
- uint8_t tmp = 0;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
- return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_rtc.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,817 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_rtc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the RTC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_RTC_H
-#define __STM32F0XX_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be set to a value lower than 0x7F */
-
- uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be set to a value lower than 0x1FFF */
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be set to a value in the 0-12 range
- if the RTC_HourFormat_12 is selected or 0-23 range if
- the RTC_HourFormat_24 is selected. */
-
- uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t RTC_Month; /*!< Specifies the RTC Date Month.
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t RTC_Date; /*!< Specifies the RTC Date.
- This parameter must be set to a value in the 1-31 range. */
-
- uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
- This parameter must be set to a value in the 0-99 range. */
-}RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
- uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- This parameter must be set to a value in the 1-31 range
- if the Alarm Date is selected.
- This parameter can be a value of @ref RTC_WeekDay_Definitions
- if the Alarm WeekDay is selected. */
-}RTC_AlarmTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Constants
- * @{
- */
-
-
-/** @defgroup RTC_Hour_Formats
- * @{
- */
-#define RTC_HourFormat_24 ((uint32_t)0x00000000)
-#define RTC_HourFormat_12 ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
- ((FORMAT) == RTC_HourFormat_24))
-/**
- * @}
- */
-
-/** @defgroup RTC_Asynchronous_Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Synchronous_Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions
- * @{
- */
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions
- * @{
- */
-#define RTC_H12_AM ((uint8_t)0x00)
-#define RTC_H12_PM ((uint8_t)0x40)
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Year_Date_Definitions
- * @{
- */
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions
- * @{
- */
-#define RTC_Month_January ((uint8_t)0x01)
-#define RTC_Month_February ((uint8_t)0x02)
-#define RTC_Month_March ((uint8_t)0x03)
-#define RTC_Month_April ((uint8_t)0x04)
-#define RTC_Month_May ((uint8_t)0x05)
-#define RTC_Month_June ((uint8_t)0x06)
-#define RTC_Month_July ((uint8_t)0x07)
-#define RTC_Month_August ((uint8_t)0x08)
-#define RTC_Month_September ((uint8_t)0x09)
-#define RTC_Month_October ((uint8_t)0x10)
-#define RTC_Month_November ((uint8_t)0x11)
-#define RTC_Month_December ((uint8_t)0x12)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions
- * @{
- */
-
-#define RTC_Weekday_Monday ((uint8_t)0x01)
-#define RTC_Weekday_Tuesday ((uint8_t)0x02)
-#define RTC_Weekday_Wednesday ((uint8_t)0x03)
-#define RTC_Weekday_Thursday ((uint8_t)0x04)
-#define RTC_Weekday_Friday ((uint8_t)0x05)
-#define RTC_Weekday_Saturday ((uint8_t)0x6)
-#define RTC_Weekday_Sunday ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Alarm_Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions
- * @{
- */
-#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
-#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
- ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmMask_Definitions
- * @{
- */
-#define RTC_AlarmMask_None ((uint32_t)0x00000000)
-#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
-#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
-#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
-#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
-#define RTC_AlarmMask_All ((uint32_t)0x80808080)
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions
- * @{
- */
-#define RTC_Alarm_A ((uint32_t)0x00000100)
-#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A)
-#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions.
- * @{
- */
-#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match
- to activate alarm. */
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
- ((MASK) == RTC_AlarmSubSecondMask_None))
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Value
- * @{
- */
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Wakeup_Timer_Definitions
- * @brief These parameters are only available for STM32F072 devices
- * @{
- */
-#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
-#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
-#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
-#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
-#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
-#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Stamp_Edges_definitions
- * @{
- */
-#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
-#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
- ((EDGE) == RTC_TimeStampEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_selection_Definitions
- * @{
- */
-#define RTC_Output_Disable ((uint32_t)0x00000000)
-#define RTC_Output_AlarmA ((uint32_t)0x00200000)
-#define RTC_Output_WakeUp ((uint32_t)0x00600000) /*!< available only for STM32F072 devices */
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
- ((OUTPUT) == RTC_Output_AlarmA) || \
- ((OUTPUT) == RTC_Output_WakeUp))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions
- * @{
- */
-#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
-#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
- ((POL) == RTC_OutputPolarity_Low))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Calib_Output_selection_Definitions
- * @{
- */
-#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
-#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
- ((OUTPUT) == RTC_CalibOutput_1Hz))
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_period_Definitions
- * @{
- */
-#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK seconds */
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
- * @{
- */
-#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0].
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0]. */
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
- ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
- * @{
- */
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions
- * @{
- */
-#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
-#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
-#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \
- ((SAVING) == RTC_DayLightSaving_ADD1H))
-
-#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
-#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
- ((OPERATION) == RTC_StoreOperation_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Trigger_Definitions
- * @{
- */
-#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
-#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
- ((TRIGGER) == RTC_TamperTrigger_HighLevel))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Filter_Definitions
- * @{
- */
-#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
-
-#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
- consecutive samples at the active leve. */
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
- ((FILTER) == RTC_TamperFilter_2Sample) || \
- ((FILTER) == RTC_TamperFilter_4Sample) || \
- ((FILTER) == RTC_TamperFilter_8Sample))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
- * @{
- */
-#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
- * @{
- */
-#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pins_Definitions
- * @{
- */
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
- input tamper 1 */
-#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
- input tamper 2 */
-#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
- input tamper 3, available only
- for STM32F072 devices */
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT
- * @{
- */
-#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
-#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
- ((TYPE) == RTC_OutputType_PushPull))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Add_1_Second_Parameter_Definitions
- * @{
- */
-#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
-#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
- ((SEL) == RTC_ShiftAdd1S_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Substract_Fraction_Of_Second_Value
- * @{
- */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Backup_Registers_Definitions
- * @{
- */
-
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4))
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions
- * @{
- */
-#define RTC_Format_BIN ((uint32_t)0x000000000)
-#define RTC_Format_BCD ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions
- * @{
- */
-#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
-#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Only available for STM32F072 devices */
-#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
-#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
-#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
-#define RTC_FLAG_TSF RTC_ISR_TSF
-#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Only available for STM32F072 devices */
-#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
-#define RTC_FLAG_INITF RTC_ISR_INITF
-#define RTC_FLAG_RSF RTC_ISR_RSF
-#define RTC_FLAG_INITS RTC_ISR_INITS
-#define RTC_FLAG_SHPF RTC_ISR_SHPF
-#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< Only available for STM32F072 devices */
-#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
-
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
- ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
- ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
- ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
- ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
- ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
- ((FLAG) == RTC_FLAG_SHPF))
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF02DF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions
- * @{
- */
-#define RTC_IT_TS ((uint32_t)0x00008000)
-#define RTC_IT_WUT ((uint32_t)0x00004000) /* Available only for STM32F072 devices */
-#define RTC_IT_ALRA ((uint32_t)0x00001000)
-#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
-#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
-#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /* Available only for STM32F072 devices */
-
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF2FFB) == (uint32_t)RESET))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \
- ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_WUT) || \
- ((IT) == RTC_IT_TAMP2) || ((IT) == RTC_IT_TAMP3))
-
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF12FFF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the RTC configuration to the default reset state *****/
-ErrorStatus RTC_DeInit(void);
-
-
-/* Initialization and Configuration functions *********************************/
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_WriteProtectionCmd(FunctionalState NewState);
-ErrorStatus RTC_EnterInitMode(void);
-void RTC_ExitInitMode(void);
-ErrorStatus RTC_WaitForSynchro(void);
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
-void RTC_BypassShadowCmd(FunctionalState NewState);
-
-/* Time and Date configuration functions **************************************/
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-uint32_t RTC_GetSubSecond(void);
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-
-/* Alarms (Alarm A) configuration functions **********************************/
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask);
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
-
-/* WakeUp Timer configuration functions ***************************************/
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); /*!< available only for STM32F072 devices */
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); /*!< available only for STM32F072 devices */
-uint32_t RTC_GetWakeUpCounter(void); /*!< available only for STM32F072 devices */
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /*!< available only for STM32F072 devices */
-
-/* Daylight Saving configuration functions ************************************/
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
-uint32_t RTC_GetStoreOperation(void);
-
-/* Output pin Configuration function ******************************************/
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
-
-/* Digital Calibration configuration functions ********************************/
-void RTC_CalibOutputCmd(FunctionalState NewState);
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue);
-
-/* TimeStamp configuration functions ******************************************/
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct);
-uint32_t RTC_GetTimeStampSubSecond(void);
-
-/* Tampers configuration functions ********************************************/
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
-void RTC_TamperPullUpCmd(FunctionalState NewState);
-
-/* Backup Data Registers configuration functions ******************************/
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
-
-/* Output Type Config configuration functions *********************************/
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
-
-/* RTC_Shift_control_synchonisation_functions *********************************/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
-
-/* Interrupts and flags management functions **********************************/
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
-void RTC_ClearFlag(uint32_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);
-void RTC_ClearITPendingBit(uint32_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_RTC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_spi.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1344 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_spi.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (SPI):
- * + Initialization and Configuration
- * + Data transfers functions
- * + Hardware CRC Calculation
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
- function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
- function for SPI2.
-
- (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using
- RCC_AHBPeriphClockCmd() function.
-
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.
- (++) Call GPIO_Init() function.
-
- (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
- Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.In I2S mode, program the Mode, Standard, Data Format, MCLK
- Output, Audio frequency and Polarity using I2S_Init() function.
-
- (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select
- at which threshold the RXNE event is generated.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- SPI_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
-
- (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
- I2S_Cmd().
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
-
- (#) Optionally, you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again SPI_Init() function):
- (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
- is programmed as Data direction parameter using the SPI_Init()
- function it can be possible to switch between SPI_Direction_Tx
- or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.
- (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
- using the SPI_Init() function it can be possible to manage the
- NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
- (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
- (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.
-
- (#) To use the CRC Hardware calculation feature refer to the Peripheral
- CRC hardware Calculation subsection.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_spi.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB)
-#define CR2_LDMA_MASK ((uint16_t)0x9FFF)
-
-#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to initialize the SPI Direction,
- SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
- Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
-
- [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
- and Slave mode (details for these procedures are available in reference manual).
-
- [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
- use the following function to manage the NSS bit:
- void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-
- [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
- is selected, use the follwoing function to enable the NSS output feature.
- void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
- [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function:
- void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
- And it can be managed by software in the SPI Motorola mode using this function:
- void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
- [..] This section provides also functions to initialize the I2S Mode, Standard,
- Data Format, MCLK Output, Audio frequency and Polarity.
-
- [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
- and Slave mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SPIx peripheral registers to their default
- * reset values.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else
- {
- if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- }
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* Initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* Initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
- /*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/slave mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI bit according to SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
- SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
- SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
- /*-------------------------Data Size Configuration -----------------------*/
- /* Get the SPIx CR2 value */
- tmpreg = SPIx->CR2;
- /* Clear DS[3:0] bits */
- tmpreg &=(uint16_t)~SPI_CR2_DS;
- /* Configure SPIx: Data Size */
- tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
- /* Write to SPIx CR2 */
- SPIx->CR2 = tmpreg;
-
- /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-
- /*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear MSTR bit */
- tmpreg &= CR1_CLEAR_MASK2;
- /* Configure SPIx: master/slave mode */
- /* Set MSTR bit according to SPI_Mode */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @note This mode is not supported for STM32F030 devices.
- * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @note This mode is not supported for STM32F030 devices.
- * @param SPIx: where x can be 1 to select the SPI peripheral (configured in I2S mode).
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- * @note This function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead.
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0;
- RCC_ClocksTypeDef RCC_Clocks;
- uint32_t sourceclock = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_1_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) */
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
-
- /* I2S Clock source is System clock: Get System Clock frequency */
- RCC_GetClocksFreq(&RCC_Clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = RCC_Clocks.SYSCLK_Frequency;
-
- /* Compute the Real divider depending on the MCLK output state with a floating point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the floating point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the TI Mode.
- *
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
- * are not taken into consideration and are configured by hardware
- * respectively to the TI mode requirements.
- *
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the selected SPI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TI mode for the selected SPI peripheral */
- SPIx->CR2 |= SPI_CR2_FRF;
- }
- else
- {
- /* Disable the TI mode for the selected SPI peripheral */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @note This mode is not supported for STM32F030 devices.
- * @param SPIx: where x can be 1 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_1_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
- }
- else
- {
- /* Disable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_DataSize: specifies the SPI data size.
- * For the SPIx peripheral this parameter can be one of the following values:
- * @arg SPI_DataSize_4b: Set data size to 4 bits
- * @arg SPI_DataSize_5b: Set data size to 5 bits
- * @arg SPI_DataSize_6b: Set data size to 6 bits
- * @arg SPI_DataSize_7b: Set data size to 7 bits
- * @arg SPI_DataSize_8b: Set data size to 8 bits
- * @arg SPI_DataSize_9b: Set data size to 9 bits
- * @arg SPI_DataSize_10b: Set data size to 10 bits
- * @arg SPI_DataSize_11b: Set data size to 11 bits
- * @arg SPI_DataSize_12b: Set data size to 12 bits
- * @arg SPI_DataSize_13b: Set data size to 13 bits
- * @arg SPI_DataSize_14b: Set data size to 14 bits
- * @arg SPI_DataSize_15b: Set data size to 15 bits
- * @arg SPI_DataSize_16b: Set data size to 16 bits
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
- /* Read the CR2 register */
- tmpreg = SPIx->CR2;
- /* Clear DS[3:0] bits */
- tmpreg &= (uint16_t)~SPI_CR2_DS;
- /* Set new DS[3:0] bits value */
- tmpreg |= SPI_DataSize;
- SPIx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the FIFO reception threshold for the selected SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
- * This parameter can be one of the following values:
- * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/2.
- * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/4.
- * @retval None
- */
-void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
-
- /* Clear FRXTH bit */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
-
- /* Set new FRXTH bit value */
- SPIx->CR2 |= SPI_RxFIFOThreshold;
-}
-
-/**
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
-
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @note This function can be called only after the SPI_Init() function has
- * been called and the NSS hardware management mode is selected.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Enables or disables the NSS pulse management mode.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits NSSP is not taken into
- * consideration and are configured by hardware respectively to the
- * TI mode requirements.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the NSS pulse management mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the NSS pulse management mode */
- SPIx->CR2 |= SPI_CR2_NSSP;
- }
- else
- {
- /* Disable the NSS pulse management mode */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to manage the SPI or I2S
- data transfers.
-
- [..] In reception, data are received and then stored into an internal Rx buffer while
- In transmission, data are first stored into an internal Tx buffer before being
- transmitted.
-
- [..] The read access of the SPI_DR register can be done using
- SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and.
- SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function
- and returns the Rx buffered value. Whereas a write access to the SPI_DR
- can be done using SPI_SendData8() (when data size is equal or inferior than 8bits)
- and SPI_I2S_SendData16() (when data size is superior than 8bits) function
- and stores the written data into Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
-{
- uint32_t spixbase = 0x00;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- spixbase = (uint32_t)SPIx;
- spixbase += 0x0C;
-
- *(__IO uint8_t *) spixbase = Data;
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- SPIx->DR = (uint16_t)Data;
-}
-
-/**
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval The value of the received data.
- */
-uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
-{
- uint32_t spixbase = 0x00;
-
- spixbase = (uint32_t)SPIx;
- spixbase += 0x0C;
-
- return *(__IO uint8_t *) spixbase;
-}
-
-/**
- * @brief Returns the most recent received data by the SPIx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * @note SPI2 is not available for STM32F031 devices.
- * the SPI peripheral.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
-{
- return SPIx->DR;
-}
-/**
- * @}
- */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- * @brief Hardware CRC Calculation functions
- *
-@verbatim
- ===============================================================================
- ##### Hardware CRC Calculation functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to manage the SPI CRC hardware
- calculation.SPI communication using CRC is possible through the following procedure:
-
- (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#) Enable the SPI using the SPI_Cmd() function
- (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
- SPI_TransmitCRC() function to indicate that after transmission of the last
- data, the CRC should be transmitted.
- (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR
- value.
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
-
- -@-
- (+@) It is advised to don't read the calculate CRC values during the communication.
- (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
- when the clock is stable, that is, when the clock is in the steady state.
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever
- the value of the SPE bit.
- (+@) With high bitrate frequencies, be careful when transmitting the CRC.
- As the number of used CPU cycles has to be as low as possible in the CRC
- transfer phase, it is forbidden to call software functions in the CRC
- transmission sequence to avoid errors in the last data and CRC reception.
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception
- of the last data.
- (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
- degradation of the SPI speed performance due to CPU accesses impacting the
- SPI bandwidth.
- (+@) When the STM32F0xx are configured as slaves and the NSS hardware mode is
- used, the NSS pin needs to be kept low between the data phase and the CRC
- phase.
- (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
- calculation takes place even if a high level is applied on the NSS pin.
- This may happen for example in case of a multislave environment where the
- communication master addresses slaves alternately.
- (+@) Between a slave deselection (high level on NSS) and a new slave selection
- (low level on NSS), the CRC value should be cleared on both master and slave
- sides in order to resynchronize the master and slave for their respective
- CRC calculation.
-
- -@- To clear the CRC, follow the procedure below:
- (#@) Disable SPI using the SPI_Cmd() function
- (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the CRC calculation length for the selected SPI.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_CRCLength: specifies the SPI CRC calculation length.
- * This parameter can be one of the following values:
- * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
- * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
- * @retval None
- */
-void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
-
- /* Clear CRCL bit */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
-
- /* Set new CRCL bit value */
- SPIx->CR1 |= SPI_CRCLength;
-}
-
-/**
- * @brief Enables or disables the CRC value calculation of the transferred bytes.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
-
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @brief Configures the number of data to transfer type(Even/Odd) for the DMA
- * last transfers and for the selected SPI.
- * @note This function have a meaning only if DMA mode is selected and if
- * the packing mode is used (data length <= 8 and DMA transfer size halfword)
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
- * This parameter can be one of the following values:
- * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
- * and number of data for reception Even.
- * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
- * and number of data for reception Even.
- * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
- * and number of data for reception Odd.
- * @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd
- * and number of data for reception Odd.
- * @retval None
- */
-void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
-
- /* Clear LDMA_TX and LDMA_RX bits */
- SPIx->CR2 &= CR2_LDMA_MASK;
-
- /* Set new LDMA_TX and LDMA_RX bits value */
- SPIx->CR2 |= SPI_LastDMATransfer;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
- (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
- (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
- (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
- (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
- (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
- (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
- (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
- (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
- (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
-
- [..]
- (@)Do not use the BSY flag to handle each data transmission or reception. It is better
- to use the TXE and RXNE flags instead.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
- and 5 pending bits:
- [..] Pending Bits:
- (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
- (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
- (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
- (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
- (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
-
- [..] Interrupt Source:
- (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
- interrupt.
- (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
- *** FIFO Status ***
- ===================
- [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
- following function:
- (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction);
-
- *** DMA Mode ***
- ================
- [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel
- requests:
- (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
-
- [..] In this Mode it is advised to use the following function:
- (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Returns the current SPIx Transmission FIFO filled level.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval The Transmission FIFO filling state.
- * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
- * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
- * - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
- */
-uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
-{
- /* Get the SPIx Transmission FIFO level bits */
- return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
-}
-
-/**
- * @brief Returns the current SPIx Reception FIFO filled level.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval The Reception FIFO filling state.
- * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
- * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
- * - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
- */
-uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
-{
- /* Get the SPIx Reception FIFO level bits */
- return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
-}
-
-/**
- * @brief Checks whether the specified SPI flag is set or not.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @param SPI_I2S_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @note OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by
- * a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by
- * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg I2S_IT_UDR: Underrun interrupt.
- * @arg SPI_I2S_IT_FRE: Format Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S_IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI_I2S_IT IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_spi.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,598 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_spi.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the SPI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_SPI_H
-#define __STM32F0XX_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief SPI Init structure definition
- */
-
-typedef struct
-{
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_data_direction */
-
- uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
- This parameter can be a value of @ref SPI_mode */
-
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
-
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-
-/**
- * @brief I2S Init structure definition
- * @note These parameters are not available for STM32F030 devices.
- */
-
-typedef struct
-{
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref SPI_I2S_Mode */
-
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref SPI_I2S_Standard */
-
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref SPI_I2S_Data_Format */
-
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref SPI_I2S_MCLK_Output */
-
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
-
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2))
-
-#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
-
-/** @defgroup SPI_data_direction
- * @{
- */
-
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \
- ((MODE) == SPI_Direction_1Line_Rx) || \
- ((MODE) == SPI_Direction_1Line_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
- ((MODE) == SPI_Mode_Slave))
-/**
- * @}
- */
-
-/** @defgroup SPI_data_size
- * @{
- */
-
-#define SPI_DataSize_4b ((uint16_t)0x0300)
-#define SPI_DataSize_5b ((uint16_t)0x0400)
-#define SPI_DataSize_6b ((uint16_t)0x0500)
-#define SPI_DataSize_7b ((uint16_t)0x0600)
-#define SPI_DataSize_8b ((uint16_t)0x0700)
-#define SPI_DataSize_9b ((uint16_t)0x0800)
-#define SPI_DataSize_10b ((uint16_t)0x0900)
-#define SPI_DataSize_11b ((uint16_t)0x0A00)
-#define SPI_DataSize_12b ((uint16_t)0x0B00)
-#define SPI_DataSize_13b ((uint16_t)0x0C00)
-#define SPI_DataSize_14b ((uint16_t)0x0D00)
-#define SPI_DataSize_15b ((uint16_t)0x0E00)
-#define SPI_DataSize_16b ((uint16_t)0x0F00)
-#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
- ((SIZE) == SPI_DataSize_5b) || \
- ((SIZE) == SPI_DataSize_6b) || \
- ((SIZE) == SPI_DataSize_7b) || \
- ((SIZE) == SPI_DataSize_8b) || \
- ((SIZE) == SPI_DataSize_9b) || \
- ((SIZE) == SPI_DataSize_10b) || \
- ((SIZE) == SPI_DataSize_11b) || \
- ((SIZE) == SPI_DataSize_12b) || \
- ((SIZE) == SPI_DataSize_13b) || \
- ((SIZE) == SPI_DataSize_14b) || \
- ((SIZE) == SPI_DataSize_15b) || \
- ((SIZE) == SPI_DataSize_16b))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_length
- * @{
- */
-
-#define SPI_CRCLength_8b ((uint16_t)0x0000)
-#define SPI_CRCLength_16b SPI_CR1_CRCL
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
- ((LENGTH) == SPI_CRCLength_16b))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High SPI_CR1_CPOL
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
- ((CPOL) == SPI_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge SPI_CR1_CPHA
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
- ((CPHA) == SPI_CPHA_2Edge))
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management
- * @{
- */
-
-#define SPI_NSS_Soft SPI_CR1_SSM
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
- ((BIT) == SPI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Mode
- * @{
- */
-
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
- ((MODE) == I2S_Mode_SlaveRx) || \
- ((MODE) == I2S_Mode_MasterTx)|| \
- ((MODE) == I2S_Mode_MasterRx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Standard
- * @{
- */
-
-#define I2S_Standard_Phillips ((uint16_t)0x0000)
-#define I2S_Standard_MSB ((uint16_t)0x0010)
-#define I2S_Standard_LSB ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
- ((STANDARD) == I2S_Standard_MSB) || \
- ((STANDARD) == I2S_Standard_LSB) || \
- ((STANDARD) == I2S_Standard_PCMShort) || \
- ((STANDARD) == I2S_Standard_PCMLong))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Data_Format
- * @{
- */
-
-#define I2S_DataFormat_16b ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
-#define I2S_DataFormat_24b ((uint16_t)0x0003)
-#define I2S_DataFormat_32b ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
- ((FORMAT) == I2S_DataFormat_16bextended) || \
- ((FORMAT) == I2S_DataFormat_24b) || \
- ((FORMAT) == I2S_DataFormat_32b))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_MCLK_Output
- * @{
- */
-
-#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
- ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Audio_Frequency
- * @{
- */
-
-#define I2S_AudioFreq_192k ((uint32_t)192000)
-#define I2S_AudioFreq_96k ((uint32_t)96000)
-#define I2S_AudioFreq_48k ((uint32_t)48000)
-#define I2S_AudioFreq_44k ((uint32_t)44100)
-#define I2S_AudioFreq_32k ((uint32_t)32000)
-#define I2S_AudioFreq_22k ((uint32_t)22050)
-#define I2S_AudioFreq_16k ((uint32_t)16000)
-#define I2S_AudioFreq_11k ((uint32_t)11025)
-#define I2S_AudioFreq_8k ((uint32_t)8000)
-#define I2S_AudioFreq_Default ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
- ((FREQ) <= I2S_AudioFreq_192k)) || \
- ((FREQ) == I2S_AudioFreq_Default))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Clock_Polarity
- * @{
- */
-
-#define I2S_CPOL_Low ((uint16_t)0x0000)
-#define I2S_CPOL_High SPI_I2SCFGR_CKPOL
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
- ((CPOL) == I2S_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_FIFO_reception_threshold
- * @{
- */
-
-#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
-#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH
-#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
- ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests
- * @{
- */
-
-#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN
-#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN
-#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup SPI_last_DMA_transfers
- * @{
- */
-
-#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
-#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
-#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
-#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
-#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
-/**
- * @}
- */
-/** @defgroup SPI_NSS_internal_software_management
- * @{
- */
-
-#define SPI_NSSInternalSoft_Set SPI_CR1_SSI
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
- ((DIRECTION) == SPI_Direction_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_interrupts_definition
- * @{
- */
-
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)
-
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_RXNE) || \
- ((IT) == SPI_I2S_IT_ERR))
-
-#define I2S_IT_UDR ((uint8_t)0x53)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)
-#define SPI_I2S_IT_FRE ((uint8_t)0x58)
-
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
- ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
-/**
- * @}
- */
-
-
-/** @defgroup SPI_transmission_fifo_status_level
- * @{
- */
-
-#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
-#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
-#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
-#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_reception_fifo_status_level
- * @{
- */
-#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
-#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
-#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
-#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
-
-/**
- * @}
- */
-
-
-/** @defgroup SPI_I2S_flags_definition
- * @{
- */
-
-#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE
-#define SPI_I2S_FLAG_TXE SPI_SR_TXE
-#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
-#define I2S_FLAG_UDR SPI_SR_UDR
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR
-#define SPI_FLAG_MODF SPI_SR_MODF
-#define SPI_I2S_FLAG_OVR SPI_SR_OVR
-#define SPI_I2S_FLAG_BSY SPI_SR_BSY
-#define SPI_I2S_FLAG_FRE SPI_SR_FRE
-
-
-
-#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
- ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
- ((FLAG) == I2S_FLAG_UDR))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_polynomial
- * @{
- */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /*!< Not applicable for STM32F030 devices */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
-void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
-uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
-uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
-
-/* Hardware CRC Calculation functions *****************************************/
-void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-
-/* DMA transfers management functions *****************************************/
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
-
-/* Interrupts and flags management functions **********************************/
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
-uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_SPI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_syscfg.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,330 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_syscfg.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the SYSCFG peripheral:
- * + Remapping the memory mapped at 0x00000000
- * + Remapping the DMA channels
- * + Enabling I2C fast mode plus driving capability for I2C pins
- * + Configuring the EXTI lines connection to the GPIO port
- * + Configuring the CFGR2 features (Connecting some internal signal
- * to the break input of TIM1)
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The SYSCFG registers can be accessed only when the SYSCFG
- interface APB clock is enabled.
- To enable SYSCFG APB clock use:
- RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_syscfg.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SYSCFG
- * @brief SYSCFG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Private_Functions
- * @{
- */
-
-/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
- * @brief SYSCFG Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### SYSCFG Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SYSCFG registers to their default reset values.
- * @param None
- * @retval None
- * @note MEM_MODE bits are not affected by APB reset.
- * @note MEM_MODE bits took the value from the user option bytes.
- * @note CFGR2 register is not affected by APB reset.
- * @note CLABBB configuration bits are locked when set.
- * @note To unlock the configuration, perform a system reset.
- */
-void SYSCFG_DeInit(void)
-{
- /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
- SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
- /* Set EXTICRx registers to reset value */
- SYSCFG->EXTICR[0] = 0;
- SYSCFG->EXTICR[1] = 0;
- SYSCFG->EXTICR[2] = 0;
- SYSCFG->EXTICR[3] = 0;
- /* Set CFGR2 register to reset value: clear SRAM parity error flag */
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE;
-}
-
-/**
- * @brief Configures the memory mapping at address 0x00000000.
- * @param SYSCFG_MemoryRemap: selects the memory remapping.
- * This parameter can be one of the following values:
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
- * @retval None
- */
-void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
-{
- uint32_t tmpctrl = 0;
-
- /* Check the parameter */
- assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
-
- /* Get CFGR1 register value */
- tmpctrl = SYSCFG->CFGR1;
-
- /* Clear MEM_MODE bits */
- tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
-
- /* Set the new MEM_MODE bits value */
- tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
-
- /* Set CFGR1 register with the new memory remap configuration */
- SYSCFG->CFGR1 = tmpctrl;
-}
-
-/**
- * @brief Configure the DMA channels remapping.
- * @param SYSCFG_DMARemap: selects the DMA channels remap.
- * This parameter can be one of the following values:
- * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
- * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
- * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
- * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
- * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
- * @param NewState: new state of the DMA channel remapping.
- * This parameter can be: ENABLE or DISABLE.
- * @note When enabled, DMA channel of the selected peripheral is remapped
- * @note When disabled, Default DMA channel is mapped to the selected peripheral
- * @note By default TIM17 DMA requests is mapped to channel 1,
- * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
- * TIM17 DMA requests to channel 2 and use
- * SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
- * TIM17 DMA requests to channel 1 (default mapping)
- * @retval None
- */
-void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Remap the DMA channel */
- SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
- }
- else
- {
- /* use the default DMA channel mapping */
- SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
- }
-}
-
-/**
- * @brief Configure the I2C fast mode plus driving capability.
- * @param SYSCFG_I2CFastModePlus: selects the pin.
- * This parameter can be one of the following values:
- * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
- * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
- * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
- * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
- * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 (only for STM32F031 and STM32F030 devices)
- * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 (only for STM32F031 and STM32F030 devices)
- * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7(only for STM32F031 and STM32F030 devices)
- * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins, available only for STM32F072 devices
- *
- * @param NewState: new state of the DMA channel remapping.
- * This parameter can be: ENABLE or DISABLE.
- * @note ENABLE: Enable fast mode plus driving capability for selected I2C pin
- * @note DISABLE: Disable fast mode plus driving capability for selected I2C pin
- * @note For I2C1, fast mode plus driving capability can be enabled on all selected
- * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
- * on each one of the following pins PB6, PB7, PB8 and PB9.
- * @note For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
- * @note For all I2C2 pins fast mode plus driving capability can be enabled
- * only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
- * @retval None
- */
-void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable fast mode plus driving capability for selected pin */
- SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
- }
- else
- {
- /* Disable fast mode plus driving capability for selected pin */
- SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
- }
-}
-
-/**
- * @brief Selects the GPIO pin used as EXTI Line.
- * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
- * for EXTI lines where x can be (A, B, C, D, E or F).
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
- * @note This parameter can be EXTI_PinSourcex where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval None
- */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
- * @brief Connect the selected parameter to the break input of TIM1.
- * @note The selected configuration is locked and can be unlocked by system reset
- * @param SYSCFG_Break: selects the configuration to be connected to break
- * input of TIM1
- * This parameter can be any combination of the following values:
- * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1,, not avaailable for STM32F030 devices.
- * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
- * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
- * @retval None
- */
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
-
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
-}
-
-/**
- * @brief Checks whether the specified SYSCFG flag is set or not.
- * @param SYSCFG_Flag: specifies the SYSCFG flag to check.
- * This parameter can be one of the following values:
- * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
- * @retval The new state of SYSCFG_Flag (SET or RESET).
- */
-FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameter */
- assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
-
- /* Check the status of the specified SPI flag */
- if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
- {
- /* SYSCFG_Flag is set */
- bitstatus = SET;
- }
- else
- {
- /* SYSCFG_Flag is reset */
- bitstatus = RESET;
- }
- /* Return the SYSCFG_Flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clear the selected SYSCFG flag.
- * @param SYSCFG_Flag: selects the flag to be cleared.
- * This parameter can be any combination of the following values:
- * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
- * @retval None
- */
-void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
-
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_syscfg.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,272 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_syscfg.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the SYSCFG firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*!< Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_SYSCFG_H
-#define __STM32F0XX_SYSCFG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SYSCFG
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Exported_Constants
- * @{
- */
-
-/** @defgroup SYSCFG_EXTI_Port_Sources
- * @{
- */
-#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
-#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
-#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
-#define EXTI_PortSourceGPIOD ((uint8_t)0x03) /*!< not available for STM32F031 devices */
-#define EXTI_PortSourceGPIOE ((uint8_t)0x04) /*!< only available for STM32F072 devices */
-#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
-
-#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOF))
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_EXTI_Pin_sources
- * @{
- */
-#define EXTI_PinSource0 ((uint8_t)0x00)
-#define EXTI_PinSource1 ((uint8_t)0x01)
-#define EXTI_PinSource2 ((uint8_t)0x02)
-#define EXTI_PinSource3 ((uint8_t)0x03)
-#define EXTI_PinSource4 ((uint8_t)0x04)
-#define EXTI_PinSource5 ((uint8_t)0x05)
-#define EXTI_PinSource6 ((uint8_t)0x06)
-#define EXTI_PinSource7 ((uint8_t)0x07)
-#define EXTI_PinSource8 ((uint8_t)0x08)
-#define EXTI_PinSource9 ((uint8_t)0x09)
-#define EXTI_PinSource10 ((uint8_t)0x0A)
-#define EXTI_PinSource11 ((uint8_t)0x0B)
-#define EXTI_PinSource12 ((uint8_t)0x0C)
-#define EXTI_PinSource13 ((uint8_t)0x0D)
-#define EXTI_PinSource14 ((uint8_t)0x0E)
-#define EXTI_PinSource15 ((uint8_t)0x0F)
-
-#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
- ((PINSOURCE) == EXTI_PinSource1) || \
- ((PINSOURCE) == EXTI_PinSource2) || \
- ((PINSOURCE) == EXTI_PinSource3) || \
- ((PINSOURCE) == EXTI_PinSource4) || \
- ((PINSOURCE) == EXTI_PinSource5) || \
- ((PINSOURCE) == EXTI_PinSource6) || \
- ((PINSOURCE) == EXTI_PinSource7) || \
- ((PINSOURCE) == EXTI_PinSource8) || \
- ((PINSOURCE) == EXTI_PinSource9) || \
- ((PINSOURCE) == EXTI_PinSource10) || \
- ((PINSOURCE) == EXTI_PinSource11) || \
- ((PINSOURCE) == EXTI_PinSource12) || \
- ((PINSOURCE) == EXTI_PinSource13) || \
- ((PINSOURCE) == EXTI_PinSource14) || \
- ((PINSOURCE) == EXTI_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Memory_Remap_Config
- * @{
- */
-#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
-#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
-#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
-
-
-#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_DMA_Remap_Config
- * @{
- */
-#define SYSCFG_DMARemap_TIM3 SYSCFG_CFGR1_TIM3_DMA_RMP /* Remap TIM3 DMA requests from channel4 to channel6,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM2 SYSCFG_CFGR1_TIM2_DMA_RMP /* Remap TIM2 DMA requests from channel3/4 to channel7,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM1 SYSCFG_CFGR1_TIM1_DMA_RMP /* Remap TIM1 DMA requests from channel2/3/4 to channel6,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_I2C1 SYSCFG_CFGR1_I2C1_DMA_RMP /* Remap I2C1 DMA requests from channel3/2 to channel7/6,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_USART3 SYSCFG_CFGR1_USART3_DMA_RMP /* Remap USART3 DMA requests from channel6/7 to channel3/2,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_USART2 SYSCFG_CFGR1_USART2_DMA_RMP /* Remap USART2 DMA requests from channel4/5 to channel6/7,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_SPI2 SYSCFG_CFGR1_SPI2_DMA_RMP /* Remap SPI2 DMA requests from channel4/5 to channel6/7,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM17_2 SYSCFG_CFGR1_TIM17_DMA_RMP2 /* Remap TIM17 DMA requests from channel1/2 to channel7,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM16_2 SYSCFG_CFGR1_TIM16_DMA_RMP2 /* Remap TIM16 DMA requests from channel3/4 to channel6,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */
-#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */
-#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
-#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
-#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */
-
-#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
- ((REMAP) == SYSCFG_DMARemap_TIM16) || \
- ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
- ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
- ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \
- ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \
- ((REMAP) == SYSCFG_DMARemap_ADC1))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_I2C_FastModePlus_Config
- * @{
- */
-#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */
-#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */
-#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */
-#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */
-#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0031 and STM32F030 devices) */
-#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins, available only for STM32F072 devices */
-#define SYSCFG_I2CFastModePlus_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9 (only for STM32F031 and STM32F030 devices) */
-#define SYSCFG_I2CFastModePlus_PA10 SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10(only for STM32F031 and STM32F030 devices) */
-
-#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
- ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
- ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PA9) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PA10))
-
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Lock_Config
- * @{
- */
-#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1, not available for STM32F030 devices */
-#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */
-#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */
-
-#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
- ((CONFIG) == SYSCFG_Break_SRAMParity) || \
- ((CONFIG) == SYSCFG_Break_Lockup))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_flags_definition
- * @{
- */
-
-#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
-
-#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the SYSCFG configuration to the default reset state **/
-void SYSCFG_DeInit(void);
-
-/* SYSCFG configuration functions *********************************************/
-void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
-void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
-void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
-FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
-void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_SYSCFG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_tim.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,3359 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_tim.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the TIM peripheral:
- * + TimeBase management
- * + Output Compare management
- * + Input Capture management
- * + Interrupts, DMA and flags management
- * + Clocks management
- * + Synchronization management
- * + Specific interface management
- * + Specific remapping management
- *
- * @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver provides functions to configure and program the TIM
- of all STM32F0xx devices These functions are split in 8 groups:
- (#) TIM TimeBase management: this group includes all needed functions
- to configure the TM Timebase unit:
- (++) Set/Get Prescaler.
- (++) Set/Get Autoreload.
- (++) Counter modes configuration.
- (++) Set Clock division.
- (++) Select the One Pulse mode.
- (++) Update Request Configuration.
- (++) Update Disable Configuration.
- (++) Auto-Preload Configuration.
- (++) Enable/Disable the counter.
-
- (#) TIM Output Compare management: this group includes all needed
- functions to configure the Capture/Compare unit used in Output
- compare mode:
- (++) Configure each channel, independently, in Output Compare mode.
- (++) Select the output compare modes.
- (++) Select the Polarities of each channel.
- (++) Set/Get the Capture/Compare register values.
- (++) Select the Output Compare Fast mode.
- (++) Select the Output Compare Forced mode.
- (++) Output Compare-Preload Configuration.
- (++) Clear Output Compare Reference.
- (++) Select the OCREF Clear signal.
- (++) Enable/Disable the Capture/Compare Channels.
-
- (#) TIM Input Capture management: this group includes all needed
- functions to configure the Capture/Compare unit used in
- Input Capture mode:
- (++) Configure each channel in input capture mode.
- (++) Configure Channel1/2 in PWM Input mode.
- (++) Set the Input Capture Prescaler.
- (++) Get the Capture/Compare values.
-
- (#) Advanced-control timers (TIM1) specific features
- (++) Configures the Break input, dead time, Lock level, the OSSI,
- the OSSR State and the AOE(automatic output enable)
- (++) Enable/Disable the TIM peripheral Main Outputs
- (++) Select the Commutation event
- (++) Set/Reset the Capture Compare Preload Control bit
-
- (#) TIM interrupts, DMA and flags management.
- (++) Enable/Disable interrupt sources.
- (++) Get flags status.
- (++) Clear flags/ Pending bits.
- (++) Enable/Disable DMA requests.
- (++) Configure DMA burst mode.
- (++) Select CaptureCompare DMA request.
-
- (#) TIM clocks management: this group includes all needed functions
- to configure the clock controller unit:
- (++) Select internal/External clock.
- (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.
-
- (#) TIM synchronization management: this group includes all needed.
- functions to configure the Synchronization unit:
- (++) Select Input Trigger.
- (++) Select Output Trigger.
- (++) Select Master Slave Mode.
- (++) ETR Configuration when used as external trigger.
-
- (#) TIM specific interface management, this group includes all
- needed functions to use the specific TIM interface:
- (++) Encoder Interface Configuration.
- (++) Select Hall Sensor.
-
- (#) TIM specific remapping management includes the Remapping
- configuration of specific timers
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_tim.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK ((uint16_t)0x00FF)
-#define CCMR_OFFSET ((uint16_t)0x0018)
-#define CCER_CCE_SET ((uint16_t)0x0001)
-#define CCER_CCNE_SET ((uint16_t)0x0004)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/** @defgroup TIM_Group1 TimeBase management functions
- * @brief TimeBase management functions
- *
-@verbatim
- ===============================================================================
- ##### TimeBase management functions #####
- ===============================================================================
-
- *** TIM Driver: how to use it in Timing(Time base) Mode ***
- ===============================================================================
- [..] To use the Timer in Timing(Time base) mode, the following steps are
- mandatory:
- (#) Enable TIM clock using
- RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
- (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
- (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
- the Time Base unit with the corresponding configuration.
- (#) Enable the NVIC if you need to generate the update interrupt.
- (#) Enable the corresponding interrupt using the function
- TIM_ITConfig(TIMx, TIM_IT_Update).
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
- [..]
- (@) All other functions can be used seperatly to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval None
- *
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM14)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
- }
- else if (TIMx == TIM15)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
- }
- else if (TIMx == TIM16)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
- }
- else
- {
- if (TIMx == TIM17)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
- }
- }
-
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
- * structure that contains the configuration information for
- * the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if(TIMx != TIM6)
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler and the Repetition counter
- values immediately */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
-
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Counter Register value.
- */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Regular: Source of update is the counter
- * overflow/underflow or the setting of UG bit, or an update
- * generation through the slave mode controller.
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
- }
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
- }
-}
-
-/**
- * @brief Selects the TIMx's One Pulse Mode.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17to select the TIMx
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features
- * @brief Advanced-control timers (TIM1) specific features
- *
-@verbatim
- ===============================================================================
- ##### Advanced-control timers (TIM1) specific features #####
- ===============================================================================
-
- ===================================================================
- *** TIM Driver: how to use the Break feature ***
- ===================================================================
- [..] After configuring the Timer channel(s) in the appropriate Output Compare mode:
-
- (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
- Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
- AOE(automatic output enable).
-
- (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
-
- (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
-
- (#) Once the break even occurs, the Timer's output signals are put in reset
- state or in a known state (according to the configuration made in
- TIM_BDTRConfig() function).
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
- /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group3 Output Compare management functions
- * @brief Output Compare management functions
- *
-@verbatim
- ===============================================================================
- ##### Output Compare management functions #####
- ===============================================================================
- *** TIM Driver: how to use it in Output Compare Mode ***
- ===============================================================================
- [..] To use the Timer in Output Compare mode, the following steps are mandatory:
- (#) Enable TIM clock using
- RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
- (#) Configure the Time base unit as described in the first part of this
- driver, if needed, else the Timer will run with the default
- configuration:
- (++) Autoreload value = 0xFFFF.
- (++) Prescaler value = 0x0000.
- (++) Counter mode = Up counting.
- (++) Clock Division = TIM_CKD_DIV1.
- (#) Fill the TIM_OCInitStruct with the desired parameters including:
- (++) The TIM Output Compare mode: TIM_OCMode.
- (++) TIM Output State: TIM_OutputState.
- (++) TIM Pulse value: TIM_Pulse.
- (++) TIM Output Compare Polarity : TIM_OCPolarity.
- (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
- channel with the corresponding configuration.
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
- [..]
- (@) All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
- (@) In case of PWM mode, this function is mandatory:
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).
- (@) If the corresponding interrupt or DMA request are needed, the user should:
- (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
- (#@) Enable the corresponding interrupt (or DMA request) using the function
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
-
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
-
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
-
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM15))
- {
- /* Check the parameters */
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Ouput Compare State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
-
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
-
- if (TIMx == TIM1)
- {
- /* Check the parameters */
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
-
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
-
- /* Reset the Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
-
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- if(TIMx == TIM1)
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- if(TIMx == TIM1)
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Ouput Compare IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x0000000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Selects the TIM Output Compare Mode.
- * @note This function disables the selected channel before changing the Output
- * Compare Mode.
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This parameter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_OFFSET;
-
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
- }
-}
-
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
- tmpccer |= TIM_OCNPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Selects the OCReference Clear source.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
- * This parameter can be one of the following values:
- * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
- * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
- * @retval None
- */
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
-
- /* Set the TIM_OCReferenceClear source */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
- TIMx->SMCR |= TIM_OCReferenceClear;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_SET << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = CCER_CCNE_SET << TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint16_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group4 Input Capture management functions
- * @brief Input Capture management functions
- *
-@verbatim
- ===============================================================================
- ##### Input Capture management functions #####
- ===============================================================================
-
- *** TIM Driver: how to use it in Input Capture Mode ***
- ===============================================================================
- [..] To use the Timer in Input Capture mode, the following steps are mandatory:
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
- function.
- (#) Configure the TIM pins by configuring the corresponding GPIO pins.
- (#) Configure the Time base unit as described in the first part of this
- driver, if needed, else the Timer will run with the default configuration:
- (++) Autoreload value = 0xFFFF.
- (++) Prescaler value = 0x0000.
- (++) Counter mode = Up counting.
- (++) Clock Division = TIM_CKD_DIV1.
- (#) Fill the TIM_ICInitStruct with the desired parameters including:
- (++) TIM Channel: TIM_Channel.
- (++) TIM Input Capture polarity: TIM_ICPolarity.
- (++) TIM Input Capture selection: TIM_ICSelection.
- (++) TIM Input Capture Prescaler: TIM_ICPrescaler.
- (++) TIM Input CApture filter value: TIM_ICFilter.
- (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired
- channel with the corresponding configuration and to measure only
- frequency or duty cycle of the input signal,or, Call
- TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired
- channels with the corresponding configuration and to measure the
- frequency and the duty cycle of the input signal.
- (#) Enable the NVIC or the DMA to read the measured frequency.
- (#) Enable the corresponding interrupt (or DMA request) to read
- the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
- (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
- (#) Use TIM_GetCapturex(TIMx); to read the captured value.
- [..]
- (@) All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* TI3 Configuration */
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* TI4 Configuration */
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Capture Compare 1 Register value.
- */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Capture Compare 3 Register value.
- */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Capture Compare 4 Register value.
- */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
- * @brief Interrupts, DMA and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, DMA and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIMx peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can only generate an update interrupt.
- * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * @note TIM_IT_Break is used only with TIM1 and TIM15.
- * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
- *
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the
- * TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- *
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1.
- *
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
- * @note TIM_FLAG_Break is used only with TIM1 and TIM15.
- * @note TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17.
- *
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or
- * TIM_FLAG_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
- * @note TIM_FLAG_Break is used only with TIM1 and TIM15.
- * @note TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17.
- *
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * @note TIM_IT_Break is used only with TIM1 and TIM15.
- * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
- *
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * @note TIM_IT_Break is used only with TIM1 and TIM15.
- * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
- *
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configures the TIMx's DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_DCR
- * @arg TIM_DMABase_OR
- * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMx's DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST10_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group6 Clocks management functions
- * @brief Clocks management functions
- *
-@verbatim
- ===============================================================================
- ##### Clocks management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx internal Clock
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ITRSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter: specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- tmpsmcr |= TIM_TS_ETRF;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group7 Synchronization management functions
- * @brief Synchronization management functions
- *
-@verbatim
- ===============================================================================
- ##### Synchronization management functions #####
- ===============================================================================
- *** TIM Driver: how to use it in synchronization Mode ***
- ===============================================================================
- [..] Case of two/several Timers
- (#) Configure the Master Timers using the following functions:
- (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,
- uint16_t TIM_TRGOSource).
- (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,
- uint16_t TIM_MasterSlaveMode);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
- uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
- [..] Case of Timers and external trigger(ETR pin)
- (#) Configure the Etrenal trigger using this function:
- (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
- uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
-@endverbatim
- * @{
- */
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, or 15 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This parameter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs (TRGO).
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST9_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
- * the counter and triggers an update of the registers.
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO).
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_MASK;
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group8 Specific interface management functions
- * @brief Specific interface management functions
- *
-@verbatim
- ===============================================================================
- ##### Specific interface management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- tmpsmcr |= TIM_EncoderMode;
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIMx's Hall sensor interface.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group9 Specific remapping management function
- * @brief Specific remapping management function
- *
-@verbatim
- ===============================================================================
- ##### Specific remapping management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures the TIM14 Remapping input Capabilities.
- * @param TIMx: where x can be 14 to select the TIM peripheral.
- * @param TIM_Remap: specifies the TIM input reampping source.
- * This parameter can be one of the following values:
- * @arg TIM14_GPIO: TIM14 Channel 1 is connected to GPIO.
- * @arg TIM14_RTC_CLK: TIM14 Channel 1 is connected to RTC input clock.
- * RTC input clock can be LSE, LSI or HSE/div128.
- * @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock.
- * @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock.
- * MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2.
- * @retval None
- */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST11_PERIPH(TIMx));
- assert_param(IS_TIM_REMAP(TIM_Remap));
-
- /* Set the Timer remapping configuration */
- TIMx->OR = TIM_Remap;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPolarity: The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPolarity: The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPolarity: The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPolarity: The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_tim.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1196 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_tim.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the TIM
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_TIM_H
-#define __STM32F0XX_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief TIM Time Base Init structure definition
- * @note This sturcture is used with all TIMx.
- */
-
-typedef struct
-{
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between 0x0000 and 0xFFFF. */
-
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
- uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
- @note This parameter is valid only for TIM1. */
-} TIM_TimeBaseInitTypeDef;
-
-/**
- * @brief TIM Output Compare Init structure definition
- */
-
-typedef struct
-{
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_state */
-
- uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_N_state
- @note This parameter is valid only for TIM1. */
-
- uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF
- for TIM2) */
-
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1. */
-
- uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1. */
-
- uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1. */
-} TIM_OCInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.
- This parameter can be a value of @ref TIM_Channel */
-
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint16_t TIM_ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/**
- * @brief TIM_BDTR structure definition
- * @note This sturcture is used only with TIM1.
- */
-
-typedef struct
-{
-
- uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_Lock_level */
-
- uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between 0x00 and 0xFF */
-
- uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-
- uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_Break_Polarity */
-
- uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BDTRInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup TIM_Exported_constants
- * @{
- */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM14)|| \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST1: TIM 1 */
-#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1)
-
-/* LIST2: TIM 1, 15, 16 and 17 */
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST3: TIM 1, 2 and 3 */
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3))
-
-/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM14) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST6: TIM 1, 2, 3 and 15 */
-#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM15))
-
-/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */
-#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM14))
-
-/* LIST8: TIM 1, 2, 3 and 14 */
-#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM14))
-
-/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */
-#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM15))
-
-/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */
-#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST1: TIM 11 */
-#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14)
-
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes
- * @{
- */
-
-#define TIM_OCMode_Timing ((uint16_t)0x0000)
-#define TIM_OCMode_Active ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2))
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2) || \
- ((MODE) == TIM_ForcedAction_Active) || \
- ((MODE) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode
- * @{
- */
-
-#define TIM_OPMode_Single ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
- ((MODE) == TIM_OPMode_Repetitive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel
- * @{
- */
-
-#define TIM_Channel_1 ((uint16_t)0x0000)
-#define TIM_Channel_2 ((uint16_t)0x0004)
-#define TIM_Channel_3 ((uint16_t)0x0008)
-#define TIM_Channel_4 ((uint16_t)0x000C)
-
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3) || \
- ((CHANNEL) == TIM_Channel_4))
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3))
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Division_CKD
- * @{
- */
-
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
- ((DIV) == TIM_CKD_DIV2) || \
- ((DIV) == TIM_CKD_DIV4))
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode
- * @{
- */
-
-#define TIM_CounterMode_Up ((uint16_t)0x0000)
-#define TIM_CounterMode_Down ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
- ((MODE) == TIM_CounterMode_Down) || \
- ((MODE) == TIM_CounterMode_CenterAligned1) || \
- ((MODE) == TIM_CounterMode_CenterAligned2) || \
- ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
- * @{
- */
-
-#define TIM_OCPolarity_High ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
- ((POLARITY) == TIM_OCPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity
- * @{
- */
-
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
- ((POLARITY) == TIM_OCNPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_state
- * @{
- */
-
-#define TIM_OutputState_Disable ((uint16_t)0x0000)
-#define TIM_OutputState_Enable ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
- ((STATE) == TIM_OutputState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_state
- * @{
- */
-
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
- ((STATE) == TIM_OutputNState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_state
- * @{
- */
-
-#define TIM_CCx_Enable ((uint16_t)0x0001)
-#define TIM_CCx_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
- ((CCX) == TIM_CCx_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_N_state
- * @{
- */
-
-#define TIM_CCxN_Enable ((uint16_t)0x0004)
-#define TIM_CCxN_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
- ((CCXN) == TIM_CCxN_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable
- * @{
- */
-
-#define TIM_Break_Enable ((uint16_t)0x1000)
-#define TIM_Break_Disable ((uint16_t)0x0000)
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
- ((STATE) == TIM_Break_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity
- * @{
- */
-
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
- ((POLARITY) == TIM_BreakPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset
- * @{
- */
-
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
- ((STATE) == TIM_AutomaticOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Lock_level
- * @{
- */
-
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
- ((LEVEL) == TIM_LOCKLevel_1) || \
- ((LEVEL) == TIM_LOCKLevel_2) || \
- ((LEVEL) == TIM_LOCKLevel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
- * @{
- */
-
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
- ((STATE) == TIM_OSSIState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
- * @{
- */
-
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
- ((STATE) == TIM_OSSRState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State
- * @{
- */
-
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
- ((STATE) == TIM_OCIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State
- * @{
- */
-
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
- ((STATE) == TIM_OCNIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity
- * @{
- */
-
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
- ((POLARITY) == TIM_ICPolarity_Falling)|| \
- ((POLARITY) == TIM_ICPolarity_BothEdge))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection
- * @{
- */
-
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \
- ((SELECTION) == TIM_ICSelection_TRC))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler
- * @{
- */
-
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_interrupt_sources
- * @{
- */
-
-#define TIM_IT_Update ((uint16_t)0x0001)
-#define TIM_IT_CC1 ((uint16_t)0x0002)
-#define TIM_IT_CC2 ((uint16_t)0x0004)
-#define TIM_IT_CC3 ((uint16_t)0x0008)
-#define TIM_IT_CC4 ((uint16_t)0x0010)
-#define TIM_IT_COM ((uint16_t)0x0020)
-#define TIM_IT_Trigger ((uint16_t)0x0040)
-#define TIM_IT_Break ((uint16_t)0x0080)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_COM) || \
- ((IT) == TIM_IT_Trigger) || \
- ((IT) == TIM_IT_Break))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address
- * @{
- */
-
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)
-#define TIM_DMABase_DIER ((uint16_t)0x0003)
-#define TIM_DMABase_SR ((uint16_t)0x0004)
-#define TIM_DMABase_EGR ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
-#define TIM_DMABase_CCER ((uint16_t)0x0008)
-#define TIM_DMABase_CNT ((uint16_t)0x0009)
-#define TIM_DMABase_PSC ((uint16_t)0x000A)
-#define TIM_DMABase_ARR ((uint16_t)0x000B)
-#define TIM_DMABase_RCR ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)
-#define TIM_DMABase_DCR ((uint16_t)0x0012)
-#define TIM_DMABase_OR ((uint16_t)0x0013)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_DMA_Burst_Length
- * @{
- */
-
-#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
- ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources
- * @{
- */
-
-#define TIM_DMA_Update ((uint16_t)0x0100)
-#define TIM_DMA_CC1 ((uint16_t)0x0200)
-#define TIM_DMA_CC2 ((uint16_t)0x0400)
-#define TIM_DMA_CC3 ((uint16_t)0x0800)
-#define TIM_DMA_CC4 ((uint16_t)0x1000)
-#define TIM_DMA_COM ((uint16_t)0x2000)
-#define TIM_DMA_Trigger ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Prescaler
- * @{
- */
-
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_Internal_Trigger_Selection
- * @{
- */
-
-#define TIM_TS_ITR0 ((uint16_t)0x0000)
-#define TIM_TS_ITR1 ((uint16_t)0x0010)
-#define TIM_TS_ITR2 ((uint16_t)0x0020)
-#define TIM_TS_ITR3 ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIM_TS_ETRF ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-/**
- * @}
- */
-
-/** @defgroup TIM_TIx_External_Clock_Source
- * @{
- */
-
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Polarity
- * @{
- */
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
- * @}
- */
-
-/** @defgroup TIM_Prescaler_Reload_Mode
- * @{
- */
-
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
- ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
- * @}
- */
-
-/** @defgroup TIM_Forced_Action
- * @{
- */
-
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
- ((ACTION) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode
- * @{
- */
-
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
- ((MODE) == TIM_EncoderMode_TI2) || \
- ((MODE) == TIM_EncoderMode_TI12))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Event_Source
- * @{
- */
-
-#define TIM_EventSource_Update ((uint16_t)0x0001)
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)
-#define TIM_EventSource_COM ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)
-#define TIM_EventSource_Break ((uint16_t)0x0080)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Source
- * @{
- */
-
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller. */
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
- ((SOURCE) == TIM_UpdateSource_Regular))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Preload_State
- * @{
- */
-
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
- ((STATE) == TIM_OCPreload_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Fast_State
- * @{
- */
-
-#define TIM_OCFast_Enable ((uint16_t)0x0004)
-#define TIM_OCFast_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
- ((STATE) == TIM_OCFast_Disable))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Clear_State
- * @{
- */
-
-#define TIM_OCClear_Enable ((uint16_t)0x0080)
-#define TIM_OCClear_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
- ((STATE) == TIM_OCClear_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Output_Source
- * @{
- */
-
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
- ((SOURCE) == TIM_TRGOSource_Enable) || \
- ((SOURCE) == TIM_TRGOSource_Update) || \
- ((SOURCE) == TIM_TRGOSource_OC1) || \
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC4Ref))
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode
- * @{
- */
-
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
- ((MODE) == TIM_SlaveMode_Gated) || \
- ((MODE) == TIM_SlaveMode_Trigger) || \
- ((MODE) == TIM_SlaveMode_External1))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode
- * @{
- */
-
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
- ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Flags
- * @{
- */
-
-#define TIM_FLAG_Update ((uint16_t)0x0001)
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)
-#define TIM_FLAG_COM ((uint16_t)0x0020)
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)
-#define TIM_FLAG_Break ((uint16_t)0x0080)
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_Trigger) || \
- ((FLAG) == TIM_FLAG_Break) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
-
-
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Input_Capture_Filer_Value
- * @{
- */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Filter
- * @{
- */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_OCReferenceClear
- * @{
- */
-#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
-#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
-#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
- ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
-
-/**
- * @}
- */
-/** @defgroup TIM_Remap
- * @{
- */
-#define TIM14_GPIO ((uint16_t)0x0000)
-#define TIM14_RTC_CLK ((uint16_t)0x0001)
-#define TIM14_HSEDiv32 ((uint16_t)0x0002)
-#define TIM14_MCO ((uint16_t)0x0003)
-
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \
- ((TIM_REMAP) == TIM14_RTC_CLK) || \
- ((TIM_REMAP) == TIM14_HSEDiv32) || \
- ((TIM_REMAP) == TIM14_MCO))
-/**
- * @}
- */
-
-/** @defgroup TIM_Legacy
- * @{
- */
-
-#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
-#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
-#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
-#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
-#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
-#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
-#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
-#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
-#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
-#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
-#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
-#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
-#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
-#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
-#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
-#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
-#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
-#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* TimeBase management ********************************************************/
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Advanced-control timers (TIM1) specific features*******************/
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Output Compare management **************************************************/
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Input Capture management ***************************************************/
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-
-/* Interrupts, DMA and flags management ***************************************/
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Clocks management **********************************************************/
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-
-
-/* Synchronization management *************************************************/
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-
-/* Specific interface management **********************************************/
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Specific remapping management **********************************************/
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_TIM_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_usart.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2106 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_usart.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Universal synchronous asynchronous receiver
- * transmitter (USART):
- * + Initialization and Configuration
- * + STOP Mode
- * + AutoBaudRate
- * + Data transfers
- * + Multi-Processor Communication
- * + LIN mode
- * + Half-duplex mode
- * + Smartcard mode
- * + IrDA mode
- * + RS485 mode
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
- function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
- function for USART2 and USART3.
- (#) According to the USART mode, enable the GPIO clocks using
- RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,
- or and SCLK).
- (#) Peripheral's alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.
- (++) Call GPIO_Init() function.
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) using the SPI_Init()
- function.
- (#) For synchronous mode, enable the clock and program the polarity,
- phase and last bit using the USART_ClockInit() function.
- (#) Enable the NVIC and the corresponding interrupt using the function
- USART_ITConfig() if you need to use interrupt mode.
- (#) When using the DMA mode:
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using USART_DMACmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
- [..]
- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
- for more details.
-
-@endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_usart.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */
-#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \
- USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
- USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */
-#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK ((uint32_t)0x000000FF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/** @defgroup USART_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate.
- (++) Word Length.
- (++) Stop Bit.
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
-
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
-
- (++) Hardware flow control.
- (++) Receiver/transmitter modes.
- [..] The USART_Init() function follows the USART asynchronous configuration
- procedure(details for the procedure are available in reference manual.
- (+) For the synchronous mode in addition to the asynchronous mode parameters
- these parameters should be also configured:
- (++) USART Clock Enabled.
- (++) USART polarity.
- (++) USART phase.
- (++) USART LastBit.
- [..] These parameters can be configured using the USART_ClockInit() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else
- {
- if (USARTx == USART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
- * the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t divider = 0, apbclock = 0, tmpreg = 0;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-
- /* Disable USART */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
-
- /*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
- /* Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = tmpreg;
-
- /*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
- /* Configure the USART Word Length, Parity and mode ----------------------- */
- /* Set the M bits according to USART_WordLength value */
- /* Set PCE and PS bits according to USART_Parity value */
- /* Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = tmpreg;
-
- /*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
- /* Configure the USART HFC -------------------------------------------------*/
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = tmpreg;
-
- /*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate -------------------------------------------*/
- RCC_GetClocksFreq(&RCC_ClocksStatus);
-
- if (USARTx == USART1)
- {
- apbclock = RCC_ClocksStatus.USART1CLK_Frequency;
- }
- else if (USARTx == USART2)
- {
- apbclock = RCC_ClocksStatus.USART2CLK_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* (divider * 10) computing in case Oversampling mode is 8 Samples */
- divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate));
- tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate));
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- /* (divider * 10) computing in case Oversampling mode is 16 Samples */
- divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate));
- tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate));
- }
-
- /* round the divider : if fractional part i greater than 0.5 increment divider */
- if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2)
- {
- divider++;
- }
-
- /* Implement the divider in case Oversampling mode is 8 Samples */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* get the LSB of divider and shift it to the right by 1 bit */
- tmpreg = (divider & (uint16_t)0x000F) >> 1;
-
- /* update the divider value */
- divider = (divider & (uint16_t)0xFFF0) | tmpreg;
- }
-
- /* Write to USART BRR */
- USARTx->BRR = (uint16_t)divider;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure that contains the configuration information for the specified
- * USART peripheral.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
- /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);
- /* Write to USART CR2 */
- USARTx->CR2 = tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_UE;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
- }
-}
-
-/**
- * @brief Enables or disables the USART's transmitter or receiver.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_Direction: specifies the USART direction.
- * This parameter can be any combination of the following values:
- * @arg USART_Mode_Tx: USART Transmitter
- * @arg USART_Mode_Rx: USART Receiver
- * @param NewState: new state of the USART transfer direction.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_MODE(USART_DirectionMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART's transfer interface by setting the TE and/or RE bits
- in the USART CR1 register */
- USARTx->CR1 |= USART_DirectionMode;
- }
- else
- {
- /* Disable the USART's transfer interface by clearing the TE and/or RE bits
- in the USART CR3 register */
- USARTx->CR1 &= (uint32_t)~USART_DirectionMode;
- }
-}
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART 8x oversampling mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has to be called before calling USART_Init() function
- * in order to have correct baudrate Divider value.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_OVER8;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling method.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_ONEBIT;
- }
- else
- {
- /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);
- }
-}
-
-/**
- * @brief Enables or disables the USART's most significant bit first
- * transmitted/received following the start bit.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART most significant bit first
- * transmitted/received following the start bit.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the most significant bit first transmitted/received following the
- start bit by setting the MSBFIRST bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_MSBFIRST;
- }
- else
- {
- /* Disable the most significant bit first transmitted/received following the
- start bit by clearing the MSBFIRST bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);
- }
-}
-
-/**
- * @brief Enables or disables the binary data inversion.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new defined levels for the USART data.
- * This parameter can be:
- * @arg ENABLE: Logical data from the data register are send/received in negative
- * logic (1=L, 0=H). The parity bit is also inverted.
- * @arg DISABLE: Logical data from the data register are send/received in positive
- * logic (1=H, 0=L)
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the binary data inversion feature by setting the DATAINV bit in
- the CR2 register */
- USARTx->CR2 |= USART_CR2_DATAINV;
- }
- else
- {
- /* Disable the binary data inversion feature by clearing the DATAINV bit in
- the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);
- }
-}
-
-/**
- * @brief Enables or disables the Pin(s) active level inversion.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_InvPin: specifies the USART pin(s) to invert.
- * This parameter can be any combination of the following values:
- * @arg USART_InvPin_Tx: USART Tx pin active level inversion.
- * @arg USART_InvPin_Rx: USART Rx pin active level inversion.
- * @param NewState: new active level status for the USART pin(s).
- * This parameter can be:
- * @arg ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
- * @arg DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_INVERSTION_PIN(USART_InvPin));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the active level inversion for selected pins by setting the TXINV
- and/or RXINV bits in the USART CR2 register */
- USARTx->CR2 |= USART_InvPin;
- }
- else
- {
- /* Disable the active level inversion for selected requests by clearing the
- TXINV and/or RXINV bits in the USART CR2 register */
- USARTx->CR2 &= (uint32_t)~USART_InvPin;
- }
-}
-
-/**
- * @brief Enables or disables the swap Tx/Rx pins.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USARTx TX/RX pins pinout.
- * This parameter can be:
- * @arg ENABLE: The TX and RX pins functions are swapped.
- * @arg DISABLE: TX/RX pins are used as defined in standard pinout
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_SWAP;
- }
- else
- {
- /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);
- }
-}
-
-/**
- * @brief Enables or disables the receiver Time Out feature.
- * @param USARTx: where x can be 1 to select the USART peripheral.
- * @param NewState: new state of the USARTx receiver Time Out.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the receiver time out feature by setting the RTOEN bit in the CR2
- register */
- USARTx->CR2 |= USART_CR2_RTOEN;
- }
- else
- {
- /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2
- register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);
- }
-}
-
-/**
- * @brief Sets the receiver Time Out value.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value.
- * @retval None
- */
-void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));
-
- /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR
- register */
- USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);
- /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR
- register */
- USARTx->RTOR |= USART_ReceiverTimeOut;
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= USART_GTPR_GT;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group2 STOP Mode functions
- * @brief STOP Mode functions
- *
-@verbatim
- ===============================================================================
- ##### STOP Mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- WakeUp from STOP mode.
-
- [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI
- or LSI.
-
- [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()
- function.
-
- [..] After configuring the source of WakeUp and before entering in Stop Mode
- USART_STOPModeCmd() function should be called to allow USART WakeUp.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART peripheral in STOP Mode.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param NewState: new state of the USARTx peripheral state in stop mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has to be called when USART clock is set to HSI or LSE.
- * @retval None
- */
-void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1
- register */
- USARTx->CR1 |= USART_CR1_UESM;
- }
- else
- {
- /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1
- register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);
- }
-}
-
-/**
- * @brief Selects the USART WakeUp method form stop mode.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_WakeUp: specifies the selected USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
- * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
- * @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);
- USARTx->CR3 |= USART_WakeUpSource;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group3 AutoBaudRate functions
- * @brief AutoBaudRate functions
- *
-@verbatim
- ===============================================================================
- ##### AutoBaudRate functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the AutoBaudRate detections.
-
- [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()
- The character patterns used to calculate baudrate must be chosen by calling
- USART_AutoBaudRateConfig() function. These function take as parameter :
- (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.
- (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern.
-
- [..] At any later time, another request for AutoBaudRate detection can be performed
- using USART_RequestCmd() function.
-
- [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
- that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
- indicate that this procedure is completed without success. USART_GetFlagStatus ()
- function should be used to monitor the status of these flags.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Auto Baud Rate.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param NewState: new state of the USARTx auto baud rate.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the auto baud rate feature by setting the ABREN bit in the CR2
- register */
- USARTx->CR2 |= USART_CR2_ABREN;
- }
- else
- {
- /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2
- register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);
- }
-}
-
-/**
- * @brief Selects the USART auto baud rate method.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method.
- * This parameter can be one of the following values:
- * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
- * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);
- USARTx->CR2 |= USART_AutoBaudRate;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group4 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the USART data transfers.
- [..] During an USART reception, data shifts in least significant bit first
- through the RX pin. When a transmission is taking place, a write instruction to
- the USART_TDR register stores the data in the shift register.
- [..] The read access of the USART_RDR register can be done using
- the USART_ReceiveData() function and returns the RDR value.
- Whereas a write access to the USART_TDR can be done using USART_SendData()
- function and stores the written data into TDR.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->TDR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group5 MultiProcessor Communication functions
- * @brief Multi-Processor Communication functions
- *
-@verbatim
- ===============================================================================
- ##### Multi-Processor Communication functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- multiprocessor communication.
- [..] For instance one of the USARTs can be the master, its TX output is
- connected to the RX input of the other USART. The others are slaves,
- their respective TX outputs are logically ANDed together and connected
- to the RX input of the master. USART multiprocessor communication is
- possible through the following procedure:
- (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Configures the wake up methode (USART_WakeUp_IdleLine or
- USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only
- for the slaves.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd()
- function.
- [..] The USART Slave exit from mute mode when receive the wake up condition.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART address */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);
- /* Set the USART address node */
- USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);
-}
-
-/**
- * @brief Enables or disables the USART's mute mode.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the MME bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_MME;
- }
- else
- {
- /* Disable the USART mute mode by clearing the MME bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);
- }
-}
-
-/**
- * @brief Selects the USART WakeUp method from mute mode.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @brief Configure the the USART Address detection length.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_AddressLength: specifies the USART address length detection.
- * This parameter can be one of the following values:
- * @arg USART_AddressLength_4b: 4-bit address length detection
- * @arg USART_AddressLength_7b: 7-bit address length detection
- * @retval None
- */
-void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);
- USARTx->CR2 |= USART_AddressLength;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group6 LIN mode functions
- * @brief LIN mode functions
- *
-@verbatim
- ===============================================================================
- ##### LIN mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- LIN Mode communication.
- [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance
- with the LIN standard.
- [..] Only this LIN Feature is supported by the USART IP:
- (+) LIN Master Synchronous Break send capability and LIN slave break
- detection capability : 13-bit break generation and 10/11 bit break
- detection.
- [..] USART LIN Master transmitter communication is possible through the
- following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Send the break character using USART_SendBreak() function.
- [..] USART LIN Master receiver communication is possible through the
- following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Configures the break detection length
- using the USART_LINBreakDetectLengthConfig() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- -@- In LIN mode, the following bits must be kept cleared:
- (+@) CLKEN in the USART_CR2 register.
- (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
- (#) Enable the USART using the USART_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USART's LIN mode.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_LINEN;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group7 Halfduplex mode function
- * @brief Half-duplex mode function
- *
-@verbatim
- ===============================================================================
- ##### Half-duplex mode function #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- Half-duplex communication.
- [..] The USART can be configured to follow a single-wire half-duplex protocol
- where the TX and RX lines are internally connected.
- [..] USART Half duplex communication is possible through the following procedure:
- (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
- or Mode receiver and hardware flow control values using the USART_Init()
- function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- -@- The RX pin is no longer used.
- -@- In Half-duplex mode the following bits must be kept cleared:
- (+@) LINEN and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's Half Duplex communication.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_HDSEL;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group8 Smartcard mode functions
- * @brief Smartcard mode functions
- *
-@verbatim
- ===============================================================================
- ##### Smartcard mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- Smartcard communication.
- [..] The Smartcard interface is designed to support asynchronous protocol
- Smartcards as defined in the ISO 7816-3 standard. The USART can provide
- a clock to the smartcard through the SCLK output. In smartcard mode,
- SCLK is not associated to the communication but is simply derived from
- the internal peripheral input clock through a 5-bit prescaler.
- [..] Smartcard communication is possible through the following procedure:
- (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler()
- function.
- (#) Configures the Smartcard Guard Time using the USART_SetGuardTime()
- function.
- (#) Program the USART clock using the USART_ClockInit() function as following:
- (++) USART Clock enabled.
- (++) USART CPOL Low.
- (++) USART CPHA on first edge.
- (++) USART Last Bit Clock Enabled.
- (#) Program the Smartcard interface using the USART_Init() function as
- following:
- (++) Word Length = 9 Bits.
- (++) 1.5 Stop Bit.
- (++) Even parity.
- (++) BaudRate = 12096 baud.
- (++) Hardware flow control disabled (RTS and CTS signals).
- (++) Tx and Rx enabled
- (#) Optionally you can enable the parity error interrupt using
- the USART_ITConfig() function.
- (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
- (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- Please refer to the ISO 7816-3 specification for more details.
- [..]
- (@) It is also possible to choose 0.5 stop bit for receiving but it is
- recommended to use 1.5 stop bits for both transmitting and receiving
- to avoid switching between the two configurations.
- (@) In smartcard mode, the following bits must be kept cleared:
- (+@) LINEN bit in the USART_CR2 register.
- (+@) HDSEL and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the specified USART guard time.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param USART_GuardTime: specifies the guard time.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= USART_GTPR_PSC;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Enables or disables the USART's Smart Card mode.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_SCEN;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_NACK;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);
- }
-}
-
-/**
- * @brief Sets the Smart Card number of retries in transmit and receive.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param USART_AutoCount: specifies the Smart Card auto retry count.
- * @retval None
- */
-void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));
- /* Clear the USART auto retry count */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);
- /* Set the USART auto retry count*/
- USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);
-}
-
-/**
- * @brief Sets the Smart Card Block length.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param USART_BlockLength: specifies the Smart Card block length.
- * @retval None
- */
-void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
-
- /* Clear the Smart card block length */
- USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);
- /* Set the Smart Card block length */
- USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group9 IrDA mode functions
- * @brief IrDA mode functions
- *
-@verbatim
- ===============================================================================
- ##### IrDA mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- IrDA communication.
- [..] IrDA is a half duplex communication protocol. If the Transmitter is busy,
- any data on the IrDA receive line will be ignored by the IrDA decoder
- and if the Receiver is busy, data on the TX from the USART to IrDA will
- not be encoded by IrDA. While receiving data, transmission should be
- avoided as the data to be transmitted could be corrupted.
- [..] IrDA communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
- Transmitter/Receiver modes and hardware flow control values using
- the USART_Init() function.
- (#) Configures the IrDA pulse width by configuring the prescaler using
- the USART_SetPrescaler() function.
- (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal
- mode using the USART_IrDAConfig() function.
- (#) Enable the IrDA using the USART_IrDACmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- (@) A pulse of width less than two and greater than one PSC period(s) may or
- may not be rejected.
- (@) The receiver set up time should be managed by software. The IrDA physical
- layer specification specifies a minimum of 10 ms delay between
- transmission and reception (IrDA is a half duplex protocol).
- (@) In IrDA mode, the following bits must be kept cleared:
- (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and HDSEL bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the USART's IrDA interface.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USART's IrDA interface.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_IREN;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup USART_Group10 RS485 mode function
- * @brief RS485 mode function
- *
-@verbatim
- ===============================================================================
- ##### RS485 mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- RS485 flow control.
- [..] RS485 flow control (Driver enable feature) handling is possible through
- the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
- Transmitter/Receiver modes and hardware flow control values using
- the USART_Init() function.
- (#) Enable the Driver Enable using the USART_DECmd() function.
- (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()
- function.
- (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime()
- function and deassertion time using the USART_SetDEDeassertionTime()
- function.
- (#) Enable the USART using the USART_Cmd() function.
- -@-
- (+@) The assertion and dessertion times are expressed in sample time units (1/8 or
- 1/16 bit time, depending on the oversampling rate).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DE functionality.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the driver enable mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the DE functionality by setting the DEM bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_DEM;
- }
- else
- {
- /* Disable the DE functionality by clearing the DEM bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);
- }
-}
-
-/**
- * @brief Configures the USART's DE polarity
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DEPolarity: specifies the DE polarity.
- * This parameter can be one of the following values:
- * @arg USART_DEPolarity_Low
- * @arg USART_DEPolarity_High
- * @retval None
- */
-void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);
- USARTx->CR3 |= USART_DEPolarity;
-}
-
-/**
- * @brief Sets the specified RS485 DE assertion time
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DEAssertionTime: specifies the time between the activation of
- * the DE signal and the beginning of the start bit
- * @retval None
- */
-void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime));
-
- /* Clear the DE assertion time */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);
- /* Set the new value for the DE assertion time */
- USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);
-}
-
-/**
- * @brief Sets the specified RS485 DE deassertion time
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DeassertionTime: specifies the time between the middle of the last
- * stop bit in a transmitted message and the de-activation of the DE signal
- * @retval None
- */
-void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime));
-
- /* Clear the DE deassertion time */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);
- /* Set the new value for the DE deassertion time */
- USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group11 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
- [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel
- requests:
- (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
- [..] In this Mode it is advised to use the following function:
- (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq,
- FunctionalState NewState).
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DMA interface.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint32_t)~USART_DMAReq;
- }
-}
-
-/**
- * @brief Enables or disables the USART's DMA interface when reception error occurs.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DMAOnError: specifies the DMA status in case of reception error.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA
- * reception error is asserted.
- * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA
- * reception error is asserted.
- * @retval None
- */
-void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAONERROR(USART_DMAOnError));
-
- /* Clear the DMA Reception error detection bit */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);
- /* Set the new value for the DMA Reception error detection bit */
- USARTx->CR3 |= USART_DMAOnError;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group12 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to configure the
- USART Interrupts sources, Requests and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to
- manage the communication: Polling mode, Interrupt mode.
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the SPI communication can be managed by these flags:
- (#) USART_FLAG_REACK: to indicate the status of the Receive Enable
- acknowledge flag
- (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable
- acknowledge flag.
- (#) USART_FLAG_WU: to indicate the status of the Wake up flag.
- (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
- (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
- (#) USART_FLAG_CM: to indicate the status of the Character match flag.
- (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
- (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
- (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
- (#) USART_FLAG_EOB: to indicate the status of the End of block flag.
- (#) USART_FLAG_RTO: to indicate the status of the Receive time out flag.
- (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input
- bit status.
- (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
- (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
- (#) USART_FLAG_TC: to indicate the status of the transmit operation.
- (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
- (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
- (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
- (#) USART_FLAG_NE: to indicate if a noise error occur.
- (#) USART_FLAG_FE: to indicate if a frame error occur.
- (#) USART_FLAG_PE: to indicate if a parity error occur.
- (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
- (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt
- sources and 10 pending bits:
- (+) Pending Bits:
- (##) USART_IT_WU: to indicate the status of the Wake up interrupt.
- (##) USART_IT_CM: to indicate the status of Character match interrupt.
- (##) USART_IT_EOB: to indicate the status of End of block interrupt.
- (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.
- (##) USART_IT_CTS: to indicate the status of CTS change interrupt.
- (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.
- (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.
- (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.
- (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.
- (##) USART_IT_NE: to indicate the status of Noise Error interrupt.
- (##) USART_IT_FE: to indicate the status of Framing Error interrupt.
- (##) USART_IT_PE: to indicate the status of Parity Error interrupt.
-
- (+) Interrupt Source:
- (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.
- (##) USART_IT_CM: specifies the interrupt source for Character match
- interrupt.
- (##) USART_IT_EOB: specifies the interrupt source for End of block
- interrupt.
- (##) USART_IT_RTO: specifies the interrupt source for Receive time-out
- interrupt.
- (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.
- (##) USART_IT_LBD: specifies the interrupt source for LIN Break
- detection interrupt.
- (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data
- Register empty interrupt.
- (##) USART_IT_TC: specifies the interrupt source for Transmission
- complete interrupt.
- (##) USART_IT_RXNE: specifies the interrupt source for Receive Data
- register not empty interrupt.
- (##) USART_IT_IDLE: specifies the interrupt source for Idle line
- detection interrupt.
- (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.
- (##) USART_IT_ERR: specifies the interrupt source for Error interrupt
- (Frame error, noise error, overrun error)
- -@@- Some parameters are coded in order to use them as interrupt
- source or as pending bits.
- [..] In this Mode it is advised to use the following functions:
- (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).
- (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
- (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices.
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- * @arg USART_IT_IDLE: Idle line detection interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0, itpos = 0, itmask = 0;
- uint32_t usartxbase = 0;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint16_t)USART_IT) >> 0x08);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_MASK;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x04;
- }
- else if (usartreg == 0x03) /* The IT is in CR3 register */
- {
- usartxbase += 0x08;
- }
- else /* The IT is in CR1 register */
- {
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Enables the specified USART's Request.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_Request: specifies the USART request.
- * This parameter can be any combination of the following values:
- * @arg USART_Request_TXFRQ: Transmit data flush ReQuest
- * @arg USART_Request_RXFRQ: Receive data flush ReQuest
- * @arg USART_Request_MMRQ: Mute Mode ReQuest
- * @arg USART_Request_SBKRQ: Send Break ReQuest
- * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest
- * @param NewState: new state of the DMA interface when reception error occurs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_REQUEST(USART_Request));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART ReQuest by setting the dedicated request bit in the RQR
- register.*/
- USARTx->RQR |= USART_Request;
- }
- else
- {
- /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR
- register.*/
- USARTx->RQR &= (uint32_t)~USART_Request;
- }
-}
-
-/**
- * @brief Enables or disables the USART's Overrun detection.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error.
- * This parameter can be any combination of the following values:
- * @arg USART_OVRDetection_Enable: OVR error detection enabled when
- * the USART OVR error is asserted.
- * @arg USART_OVRDetection_Disable: OVR error detection disabled when
- * the USART OVR error is asserted.
- * @retval None
- */
-void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));
-
- /* Clear the OVR detection bit */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);
- /* Set the new value for the OVR detection bit */
- USARTx->CR3 |= USART_OVRDetection;
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_REACK: Receive Enable acknowledge flag.
- * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag.
- * @arg USART_FLAG_WU: Wake up flag, not available for STM32F030 devices.
- * @arg USART_FLAG_RWU: Receive Wake up flag, not available for STM32F030 devices.
- * @arg USART_FLAG_SBK: Send Break flag.
- * @arg USART_FLAG_CM: Character match flag.
- * @arg USART_FLAG_BUSY: Busy flag.
- * @arg USART_FLAG_ABRF: Auto baud rate flag.
- * @arg USART_FLAG_ABRE: Auto baud rate error flag.
- * @arg USART_FLAG_EOB: End of block flag, not available for STM32F030 devices.
- * @arg USART_FLAG_RTO: Receive time out flag.
- * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status.
- * @arg USART_FLAG_CTS: CTS Change flag.
- * @arg USART_FLAG_LBD: LIN Break detection flag, not available for STM32F030 devices.
- * @arg USART_FLAG_TXE: Transmit data register empty flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- * @arg USART_FLAG_IDLE: Idle Line detection flag.
- * @arg USART_FLAG_ORE: OverRun Error flag.
- * @arg USART_FLAG_NE: Noise Error flag.
- * @arg USART_FLAG_FE: Framing Error flag.
- * @arg USART_FLAG_PE: Parity Error flag.
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
-
- if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_WU: Wake up flag, not available for STM32F030 devices.
- * @arg USART_FLAG_CM: Character match flag.
- * @arg USART_FLAG_EOB: End of block flag, not available for STM32F030 devices.
- * @arg USART_FLAG_RTO: Receive time out flag.
- * @arg USART_FLAG_CTS: CTS Change flag.
- * @arg USART_FLAG_LBD: LIN Break detection flag, not available for STM32F030 devices.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_IDLE: IDLE line detected flag.
- * @arg USART_FLAG_ORE: OverRun Error flag.
- * @arg USART_FLAG_NE: Noise Error flag.
- * @arg USART_FLAG_FE: Framing Error flag.
- * @arg USART_FLAG_PE: Parity Errorflag.
- *
- * @note RXNE pending bit is cleared by a read to the USART_RDR register
- * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register
- * USART_RQR (USART_RequestCmd()).
- * @note TC flag can be also cleared by software sequence: a read operation
- * to USART_SR register (USART_GetFlagStatus()) followed by a write
- * operation to USART_TDR register (USART_SendData()).
- * @note TXE flag is cleared by a write to the USART_TDR register (USART_SendData())
- * or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()).
- * @note SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR
- * (USART_RequestCmd()).
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-
- USARTx->ICR = USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices.
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- * @arg USART_IT_IDLE: Idle line detection interrupt.
- * @arg USART_IT_ORE: OverRun Error interrupt.
- * @arg USART_IT_NE: Noise Error interrupt.
- * @arg USART_IT_FE: Framing Error interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)
-{
- uint32_t bitpos = 0, itmask = 0, usartreg = 0;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
-
- /* Get the USART register index */
- usartreg = (((uint16_t)USART_IT) >> 0x08);
- /* Get the interrupt position */
- itmask = USART_IT & IT_MASK;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x10;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->ISR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's interrupt pending bits.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_IDLE: IDLE line detected interrupt.
- * @arg USART_IT_ORE: OverRun Error interrupt.
- * @arg USART_IT_NE: Noise Error interrupt.
- * @arg USART_IT_FE: Framing Error interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- *
- * @note RXNE pending bit is cleared by a read to the USART_RDR register
- * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register
- * USART_RQR (USART_RequestCmd()).
- * @note TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by
- * a write operation to USART_TDR register (USART_SendData()).
- * @note TXE pending bit is cleared by a write to the USART_TDR register
- * (USART_SendData()) or by writing 1 to the TXFRQ in the register
- * USART_RQR (USART_RequestCmd()).
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)
-{
- uint32_t bitpos = 0, itmask = 0;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
-
- bitpos = USART_IT >> 0x10;
- itmask = ((uint32_t)0x01 << (uint32_t)bitpos);
- USARTx->ICR = (uint32_t)itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_usart.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,609 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_usart.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the USART
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_USART_H
-#define __STM32F0XX_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-
-
-/**
- * @brief USART Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
- uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint32_t USART_Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref USART_Hardware_Flow_Control*/
-} USART_InitTypeDef;
-
-/**
- * @brief USART Clock Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_Clock */
-
- uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Constants
- * @{
- */
-
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == USART4))
-
-#define IS_USART_12_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2))
-
-/** @defgroup USART_Word_Length
- * @{
- */
-
-#define USART_WordLength_8b ((uint32_t)0x00000000)
-#define USART_WordLength_9b USART_CR1_M /* should be ((uint32_t)0x00001000) */
-#define USART_WordLength_7b ((uint32_t)0x10001000) /*!< only available for STM32F072 and STM32F030 devices */
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
- ((LENGTH) == USART_WordLength_9b) || \
- ((LENGTH) == USART_WordLength_7b))
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits
- * @{
- */
-
-#define USART_StopBits_1 ((uint32_t)0x00000000)
-#define USART_StopBits_2 USART_CR2_STOP_1
-#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
- ((STOPBITS) == USART_StopBits_2) || \
- ((STOPBITS) == USART_StopBits_1_5))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity
- * @{
- */
-
-#define USART_Parity_No ((uint32_t)0x00000000)
-#define USART_Parity_Even USART_CR1_PCE
-#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
- ((PARITY) == USART_Parity_Even) || \
- ((PARITY) == USART_Parity_Odd))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode
- * @{
- */
-
-#define USART_Mode_Rx USART_CR1_RE
-#define USART_Mode_Tx USART_CR1_TE
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
- ((MODE) != (uint32_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup USART_Hardware_Flow_Control
- * @{
- */
-
-#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
-#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
-#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
-#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == USART_HardwareFlowControl_None) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock
- * @{
- */
-
-#define USART_Clock_Disable ((uint32_t)0x00000000)
-#define USART_Clock_Enable USART_CR2_CLKEN
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
- ((CLOCK) == USART_Clock_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity
- * @{
- */
-
-#define USART_CPOL_Low ((uint32_t)0x00000000)
-#define USART_CPOL_High USART_CR2_CPOL
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase
- * @{
- */
-
-#define USART_CPHA_1Edge ((uint32_t)0x00000000)
-#define USART_CPHA_2Edge USART_CR2_CPHA
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit
- * @{
- */
-
-#define USART_LastBit_Disable ((uint32_t)0x00000000)
-#define USART_LastBit_Enable USART_CR2_LBCL
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
- ((LASTBIT) == USART_LastBit_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Requests
- * @{
- */
-
-#define USART_DMAReq_Tx USART_CR3_DMAT
-#define USART_DMAReq_Rx USART_CR3_DMAR
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
- ((DMAREQ) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Recception_Error
- * @{
- */
-
-#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
-#define USART_DMAOnError_Disable USART_CR3_DDRE
-#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
- ((DMAERROR) == USART_DMAOnError_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_MuteMode_WakeUp_methods
- * @{
- */
-
-#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
-#define USART_WakeUp_AddressMark USART_CR1_WAKE
-#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
- ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
- * @}
- */
-
-/** @defgroup USART_Address_Detection
- * @{
- */
-
-#define USART_AddressLength_4b ((uint32_t)0x00000000)
-#define USART_AddressLength_7b USART_CR2_ADDM7
-#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
- ((ADDRESS) == USART_AddressLength_7b))
-/**
- * @}
- */
-
-/** @defgroup USART_StopMode_WakeUp_methods
- * @note These parameters are only available for STM32F051 and STM32F072 devices
- * @{
- */
-
-#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
-#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
-#define USART_WakeUpSource_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
-#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
- ((SOURCE) == USART_WakeUpSource_StartBit) || \
- ((SOURCE) == USART_WakeUpSource_RXNE))
-/**
- * @}
- */
-
-/** @defgroup USART_LIN_Break_Detection_Length
- * @{
- */
-
-#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
-#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \
- ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
- * @}
- */
-
-/** @defgroup USART_IrDA_Low_Power
- * @{
- */
-
-#define USART_IrDAMode_LowPower USART_CR3_IRLP
-#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
- ((MODE) == USART_IrDAMode_Normal))
-/**
- * @}
- */
-
-/** @defgroup USART_DE_Polarity
- * @{
- */
-
-#define USART_DEPolarity_High ((uint32_t)0x00000000)
-#define USART_DEPolarity_Low USART_CR3_DEP
-#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
- ((POLARITY) == USART_DEPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup USART_Inversion_Pins
- * @{
- */
-
-#define USART_InvPin_Tx USART_CR2_TXINV
-#define USART_InvPin_Rx USART_CR2_RXINV
-#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
- ((PIN) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_AutoBaudRate_Mode
- * @{
- */
-
-#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
-#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
-#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
- ((MODE) == USART_AutoBaudRate_FallingEdge))
-/**
- * @}
- */
-
-/** @defgroup USART_OVR_DETECTION
- * @{
- */
-
-#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
-#define USART_OVRDetection_Disable USART_CR3_OVRDIS
-#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
- ((OVR) == USART_OVRDetection_Disable))
-/**
- * @}
- */
-/** @defgroup USART_Request
- * @{
- */
-
-#define USART_Request_ABRRQ USART_RQR_ABRRQ
-#define USART_Request_SBKRQ USART_RQR_SBKRQ
-#define USART_Request_MMRQ USART_RQR_MMRQ
-#define USART_Request_RXFRQ USART_RQR_RXFRQ
-#define USART_Request_TXFRQ USART_RQR_TXFRQ
-
-#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
- ((REQUEST) == USART_Request_RXFRQ) || \
- ((REQUEST) == USART_Request_MMRQ) || \
- ((REQUEST) == USART_Request_SBKRQ) || \
- ((REQUEST) == USART_Request_ABRRQ))
-/**
- * @}
- */
-
-/** @defgroup USART_Flags
- * @{
- */
-#define USART_FLAG_REACK USART_ISR_REACK
-#define USART_FLAG_TEACK USART_ISR_TEACK
-#define USART_FLAG_WU USART_ISR_WUF /*!< Not available for STM32F030 devices */
-#define USART_FLAG_RWU USART_ISR_RWU /*!< Not available for STM32F030 devices */
-#define USART_FLAG_SBK USART_ISR_SBKF
-#define USART_FLAG_CM USART_ISR_CMF
-#define USART_FLAG_BUSY USART_ISR_BUSY
-#define USART_FLAG_ABRF USART_ISR_ABRF
-#define USART_FLAG_ABRE USART_ISR_ABRE
-#define USART_FLAG_EOB USART_ISR_EOBF /*!< Not available for STM32F030 devices */
-#define USART_FLAG_RTO USART_ISR_RTOF
-#define USART_FLAG_nCTSS USART_ISR_CTS
-#define USART_FLAG_CTS USART_ISR_CTSIF
-#define USART_FLAG_LBD USART_ISR_LBD /*!< Not available for STM32F030 devices */
-#define USART_FLAG_TXE USART_ISR_TXE
-#define USART_FLAG_TC USART_ISR_TC
-#define USART_FLAG_RXNE USART_ISR_RXNE
-#define USART_FLAG_IDLE USART_ISR_IDLE
-#define USART_FLAG_ORE USART_ISR_ORE
-#define USART_FLAG_NE USART_ISR_NE
-#define USART_FLAG_FE USART_ISR_FE
-#define USART_FLAG_PE USART_ISR_PE
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
- ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
- ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
- ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
- ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
- ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
- ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
-
-#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
- ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
- ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
- ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition
- * @brief USART Interrupt definition
- * USART_IT possible values
- * Elements values convention: 0xZZZZYYXX
- * XX: Position of the corresponding Interrupt
- * YY: Register index
- * ZZZZ: Flag position
- * @{
- */
-
-#define USART_IT_WU ((uint32_t)0x00140316) /*!< Not available for STM32F030 devices */
-#define USART_IT_CM ((uint32_t)0x0011010E)
-#define USART_IT_EOB ((uint32_t)0x000C011B) /*!< Not available for STM32F030 devices */
-#define USART_IT_RTO ((uint32_t)0x000B011A)
-#define USART_IT_PE ((uint32_t)0x00000108)
-#define USART_IT_TXE ((uint32_t)0x00070107)
-#define USART_IT_TC ((uint32_t)0x00060106)
-#define USART_IT_RXNE ((uint32_t)0x00050105)
-#define USART_IT_IDLE ((uint32_t)0x00040104)
-#define USART_IT_LBD ((uint32_t)0x00080206) /*!< Not available for STM32F030 devices */
-#define USART_IT_CTS ((uint32_t)0x0009030A)
-#define USART_IT_ERR ((uint32_t)0x00000300)
-#define USART_IT_ORE ((uint32_t)0x00030300)
-#define USART_IT_NE ((uint32_t)0x00020300)
-#define USART_IT_FE ((uint32_t)0x00010300)
-
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
- ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
- ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-/**
- * @}
- */
-
-/** @defgroup USART_Global_definition
- * @{
- */
-
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
-#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
-#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
-#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void USART_DeInit(USART_TypeDef* USARTx);
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); /* Not available for STM32F030 devices */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
-void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
-
-/* STOP Mode functions ********************************************************/
-void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource); /* Not available for STM32F030 devices */
-
-/* AutoBaudRate functions *****************************************************/
-void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
-
-/* Data transfers functions ***************************************************/
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-
-/* Multi-Processor Communication functions ************************************/
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
-void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
-
-/* LIN mode functions *********************************************************/
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength); /* Not available for STM32F030 devices */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
-
-/* Half-duplex mode function **************************************************/
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Smartcard mode functions ***************************************************/
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* Not available for STM32F030 devices */
-void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount); /* Not available for STM32F030 devices */
-void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength); /* Not available for STM32F030 devices */
-
-/* IrDA mode functions ********************************************************/
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode); /* Not available for STM32F030 devices */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
-
-/* RS485 mode functions *******************************************************/
-void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
-void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
-void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
-
-/* DMA transfers management functions *****************************************/
-void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
-void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
-
-/* Interrupts and flags management functions **********************************/
-void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
-void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
-void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_USART_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_wwdg.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,313 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_wwdg.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Window watchdog (WWDG) peripheral:
- * + Prescaler, Refresh window and Counter configuration
- * + WWDG activation
- * + Interrupts and flags management
- *
- * @verbatim
- *
- ==============================================================================
- ##### WWDG features #####
- ==============================================================================
- [..] Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
- before to reach 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
- [..] An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
-
- [..] Once enabled the WWDG cannot be disabled except by a system reset.
-
- [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- reset occurs.
-
- [..] The WWDG counter input clock is derived from the APB clock divided
- by a programmable prescaler.
-
- [..] WWDG counter clock = PCLK1 / Prescaler.
- [..] WWDG timeout = (WWDG counter clock) * (counter value).
-
- [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
- function.
-
- (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
-
- (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
-
- (#) Set the WWDG counter value and start it using WWDG_Enable() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
-
- (#) Optionally you can enable the Early wakeup interrupt which is
- generated when the counter reach 0x40.
- Once enabled this interrupt cannot be disabled except by a system reset.
-
- (#) Then the application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- WWDG_SetCounter() function. This operation must occur only when
- the counter value is lower than the refresh window value,
- programmed using WWDG_SetWindowValue().
-
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_wwdg.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup WWDG
- * @brief WWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------------------- WWDG registers bit mask ---------------------------- */
-/* CFR register bit mask */
-#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
-#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
-#define BIT_MASK ((uint8_t)0x7F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Functions
- * @{
- */
-
-/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
- * @brief Prescaler, Refresh window and Counter configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Prescaler, Refresh window and Counter configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void WWDG_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
- * @brief Sets the WWDG Prescaler.
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.
- * This parameter can be one of the following values:
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
- * @retval None
- */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
- /* Clear WDGTB[1:0] bits */
- tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
- tmpreg |= WWDG_Prescaler;
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Sets the WWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * This parameter value must be lower than 0x80.
- * @retval None
- */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
- __IO uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
- /* Clear W[6:0] bits */
-
- tmpreg = WWDG->CFR & CFR_W_MASK;
-
- /* Set W[6:0] bits according to WindowValue value */
- tmpreg |= WindowValue & (uint32_t) BIT_MASK;
-
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @param None
- * @retval None
- */
-void WWDG_EnableIT(void)
-{
- WWDG->CFR |= WWDG_CFR_EWI;
-}
-
-/**
- * @brief Sets the WWDG counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent
- * generating an immediate reset).
- * @retval None
- */
-void WWDG_SetCounter(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- /* Write to T[6:0] bits to configure the counter value, no need to do
- a read-modify-write; writing a 0 to WDGA bit does nothing */
- WWDG->CR = Counter & BIT_MASK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group2 WWDG activation functions
- * @brief WWDG activation functions
- *
-@verbatim
- ==============================================================================
- ##### WWDG activation function #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables WWDG and load the counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent
- * generating an immediate reset).
- * @retval None
- */
-void WWDG_Enable(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- WWDG->CR = WWDG_CR_WDGA | Counter;
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ==============================================================================
- ##### Interrupts and flags management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.
- * @param None
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
- */
-FlagStatus WWDG_GetFlagStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((WWDG->SR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears Early Wakeup interrupt flag.
- * @param None
- * @retval None
- */
-void WWDG_ClearFlag(void)
-{
- WWDG->SR = (uint32_t)RESET;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_wwdg.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,119 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_wwdg.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the WWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_WWDG_H
-#define __STM32F0XX_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup WWDG_Prescaler
- * @{
- */
-
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
- ((PRESCALER) == WWDG_Prescaler_2) || \
- ((PRESCALER) == WWDG_Prescaler_4) || \
- ((PRESCALER) == WWDG_Prescaler_8))
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the WWDG configuration to the default reset state ****/
-void WWDG_DeInit(void);
-
-/* Prescaler, Refresh window and Counter configuration functions **************/
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
-void WWDG_SetWindowValue(uint8_t WindowValue);
-void WWDG_EnableIT(void);
-void WWDG_SetCounter(uint8_t Counter);
-
-/* WWDG activation functions **************************************************/
-void WWDG_Enable(uint8_t Counter);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus WWDG_GetFlagStatus(void);
-void WWDG_ClearFlag(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_WWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/system_stm32f0xx.c Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,443 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f0xx.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 12-January-2014
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F0xx devices,
- * and is generated by the clock configuration tool
- * STM32F0xx_Clock_Configuration_V1.0.1.xls
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f0xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
- * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
- * through PLL, and you are using different crystal you have to adapt the HSE
- * value to your own configuration.
- *
- * 5. This file configures the system clock as follows:
- *-----------------------------------------------------------------------------
- * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
- * | (external 8 MHz clock) | (internal 8 MHz)
- * | 2- PLL_HSE_XTAL |
- * | (external 8 MHz xtal) |
- *-----------------------------------------------------------------------------
- * SYSCLK(MHz) | 48 | 48
- *-----------------------------------------------------------------------------
- * AHBCLK (MHz) | 48 | 48
- *-----------------------------------------------------------------------------
- * APBCLK (MHz) | 48 | 48
- *-----------------------------------------------------------------------------
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f0xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
- * @{
- */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
- * @{
- */
-uint32_t SystemCoreClock = 48000000;
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
- * @{
- */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80C;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFE;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings */
- SetSysClock();
-}
-
-/**
- * @brief Update SystemCoreClock according to Clock Register Values
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- * @param None
- * @retval None
- */
-void SetSysClock(void)
-{
- /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
- if (SetSysClock_PLL_HSE(1) == 0)
-#endif
- {
- /* 2- If fail try to start with HSE and external xtal */
- #if USE_PLL_HSE_XTAL != 0
- if (SetSysClock_PLL_HSE(0) == 0)
- #endif
- {
- /* 3- If fail start with HSI clock */
- if (SetSysClock_PLL_HSI() == 0)
- {
- while(1)
- {
- // [TODO] Put something here to tell the user that a problem occured...
- }
- }
- }
- }
-
- // Output clock on MCO pin (PA8) for debugging purpose
- /*
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_0);
- // Output clock on MCO pin
- // Warning: only RCC_MCOPrescaler_1 is available on STM32F030x8 devices
- RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
- */
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
- __IO uint32_t StartUpCounter = 0;
- __IO uint32_t HSEStatus = 0;
-
- /* Bypass HSE: can be done only if HSE is OFF */
- RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
- if (bypass != 0)
- {
- RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
- }
- else
- {
- RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
- }
-
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- /* Check if HSE has started correctly */
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Enable Prefetch Buffer and set Flash Latency */
- FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
-
- /* PLL configuration
- PLLCLK = 48 MHz (xtal 8 MHz * 6) */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6
- | RCC_CFGR_HPRE_DIV1 /* HCLK = 48 MHz */
- | RCC_CFGR_PPRE_DIV1); /* PCLK = 48 MHz */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
- {
- }
-
- return 1; // OK
- }
- else
- {
- return 0; // FAIL
- }
-}
-#endif
-
-/******************************************************************************/
-/* PLL (clocked by HSI) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
- /* Enable Prefetch Buffer and set Flash Latency */
- FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
-
- /* PLL configuration
- PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12
- | RCC_CFGR_HPRE_DIV1 /* HCLK = 48 MHz */
- | RCC_CFGR_PPRE_DIV1); /* PCLK = 48 MHz */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
- {
- }
-
- return 1; // OK
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/system_stm32f0xx.c.x Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,319 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f0xx.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 12-January-2014
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F0xx devices,
- * and is generated by the clock configuration tool
- * STM32F0xx_Clock_Configuration_V1.0.1.xls
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f0xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
- * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
- * through PLL, and you are using different crystal you have to adapt the HSE
- * value to your own configuration.
- *
- * 5. This file configures the system clock as follows:
- *=============================================================================
- *=============================================================================
- * System Clock source | HSI
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB Prescaler | 1
- *-----------------------------------------------------------------------------
- * HSE Frequency(Hz) | NA
- *----------------------------------------------------------------------------
- * PLLMUL | NA
- *-----------------------------------------------------------------------------
- * PREDIV | NA
- *-----------------------------------------------------------------------------
- * Flash Latency(WS) | 0
- *-----------------------------------------------------------------------------
- * Prefetch Buffer | ON
- *-----------------------------------------------------------------------------
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f0xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
- * @{
- */
-uint32_t SystemCoreClock = 8000000;
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80C;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFE;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
- SetSysClock();
-}
-
-/**
- * @brief Update SystemCoreClock according to Clock Register Values
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
- * settings.
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-/******************************************************************************/
-/* HSI used as System clock source */
-/******************************************************************************/
-
- /* At this stage the HSI is already enabled and used as System clock source */
-
- /* Enable Prefetch Buffer and Flash 0 wait state */
- FLASH->ACR = FLASH_ACR_PRFTBE;
-
- /* HCLK = SYSCLK / 1 */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK = HCLK / 1 */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
-
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/system_stm32f0xx.h Tue Dec 02 15:15:06 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,116 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f0xx.h
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F0XX_H
-#define __SYSTEM_STM32F0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F0xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F0xx_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F0XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/STM32F0xx.ld Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,155 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64k
+ RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 8k - 0x0C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.s Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,299 @@ +/** + ****************************************************************************** + * @file startup_stm32f051x8.s + * @author MCD Application Team + * @version V2.1.0 + * @date 03-Oct-2014 + * @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bl exit +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC and CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word TSC_IRQHandler /* TSC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word CEC_CAN_IRQHandler /* CEC and CAN */ + .word 0 /* Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f0xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+static unsigned char vtor_remap = 0; // To keep track that the vectors remap is done
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if (vtor_remap == 0) {
+ uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
+ vtor_remap = 1; // The vectors remap is done
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ // Return the vector
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F030R8
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 29 vectors = 116 bytes from 0x40 to 0xB3
+// Total: 45 vectors = 180 bytes (0xB4) to be reserved in RAM
+#define NVIC_NUM_VECTORS 45
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,3815 @@
+/**
+ ******************************************************************************
+ * @file stm32f051x8.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access
+ * Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f051x8
+ * @{
+ */
+
+#ifndef __STM32F051x8_H
+#define __STM32F051x8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
+ */
+#define __CM0_REV 0 /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F051x4/STM32F051x6/STM32F051x8 device Interrupt Number Definition
+ */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** STM32F051x4/STM32F051x6/STM32F051x8 specific Interrupt Numbers **************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD Interrupt through EXTI Lines 16 */
+ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
+ RCC_IRQn = 4, /*!< RCC global Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 28, /*!< USART2 global Interrupt */
+ CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_stm32f0xx.h" /* STM32F0xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+}ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+}ADC_Common_TypeDef;
+
+/**
+ * @brief HDMI-CEC
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
+}COMP1_2_TypeDef;
+
+typedef struct
+{
+ __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+}COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+}CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+}DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+}DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
+}FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
+ __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
+ __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+}OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+}IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+}PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
+}RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+}RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+}SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+}TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+}USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+}WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
+#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP1_2_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP_BASE)
+#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
+#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
+#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
+#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
+
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
+
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/*********************** Bit definition for COMP_CSR register ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+/* COMPx bits definition */
+#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
+
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
+
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** FLASH Keys **********************************************/
+#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+ to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OB_WRP0 register *********************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP1 register *********************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register ****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register ****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register ********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register ********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *******************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *******************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/*****************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register *******************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register ******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register *******************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
+
+/*****************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for PWR_CR register *******************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register *******************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+
+/*****************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for RCC_CR register *******************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************** Bit definition for RCC_CFGR register *****************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!<****************** Bit definition for RCC_CIR register *****************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register ****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+
+/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+
+/***************** Bit definition for RCC_APB1RSTR register ****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
+
+/****************** Bit definition for RCC_AHBENR register *****************/
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register *****************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
+#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
+
+/******************* Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ***************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
+
+/******************* Bit definition for RCC_CFGR2 register *****************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/******************* Bit definition for RCC_CFGR3 register *****************/
+/*!< USART1 Clock source selection */
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+
+/*!< CEC Clock source selection */
+#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
+
+#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
+#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
+
+/*!< USART2 Clock source selection */
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+/******************* Bit definition for RCC_CR2 register *******************/
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
+
+/*****************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/*****************************************************************************/
+/******************** Bits definition for RTC_TR register ******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register ******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register ******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ISR register *****************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register ****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMAR register **************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register *****************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register *****************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register **************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register ****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register ****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ***************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALR register ****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ***************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register ************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ***************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ***************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ***************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ***************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ***************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
+
+/*****************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for SPI_CR1 register *******************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register *******************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register *******************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register *******************/
+#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register *****************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register *****************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register *****************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register ****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register ******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/*****************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/*****************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register **************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register **************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register **************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register **************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM14_OR register ********************/
+#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
+
+/****************************** COMP Instances *********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
+
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+/****************************** GPIO Lock Instances ****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *********************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM14)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : auto Baud rate detection **************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : LIN mode ********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : wakeup from stop mode ********************/
+#define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : Auto Baud Rate detection ********************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : Driver enable detection ********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define PVD_VDDIO2_IRQn PVD_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_VDDIO2_IRQHandler PVD_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F051x8_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,228 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F0xx device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx)
+ /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
+ #define STM32F051x8 /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.1.0
+ */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F030x6)
+ #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+ #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+ #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+ #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+ #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+ #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+ #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+ #include "stm32f058xx.h"
+#elif defined(STM32F071xB)
+ #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+ #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+ #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+ #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+ #include "stm32f098xx.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,434 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.c
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 48 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f0xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 48000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+ RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+ /* Reset PREDIV[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
+ /* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
+#else
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#endif
+
+ /* Reset HSI14 bit */
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the Cube driver */
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+ SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+ {
+ /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select HSE oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+ }
+ RCC_OscInitStruct.HSI48State = 0; // not used
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ return 1; // OK
+}
+
+/* Used for the different timeouts in the HAL */
+void SysTick_Handler(void)
+{
+ HAL_IncTick();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F0xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.s Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,407 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303xE devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20004000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX + DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FMC_IRQHandler ; FMC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD ADC4_IRQHandler ; ADC4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD TIM20_BRK_IRQHandler ; TIM20 Break + DCD TIM20_UP_IRQHandler ; TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation + DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TSC_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ADC4_IRQHandler [WEAK] + EXPORT COMP1_2_3_IRQHandler [WEAK] + EXPORT COMP4_5_6_IRQHandler [WEAK] + EXPORT COMP7_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT USBWakeUp_RMP_IRQHandler [WEAK] + EXPORT TIM20_BRK_IRQHandler [WEAK] + EXPORT TIM20_UP_IRQHandler [WEAK] + EXPORT TIM20_TRG_COM_IRQHandler [WEAK] + EXPORT TIM20_CC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TSC_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN_TX_IRQHandler +USB_LP_CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ADC4_IRQHandler +COMP1_2_3_IRQHandler +COMP4_5_6_IRQHandler +COMP7_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +USBWakeUp_RMP_IRQHandler +TIM20_BRK_IRQHandler +TIM20_UP_IRQHandler +TIM20_TRG_COM_IRQHandler +TIM20_CC_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F303RE: 512KB FLASH (0x80000) + 64KB SRAM (0x10000)
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 101 vectors = 404 bytes (0x194) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x194) (0x10000-0x194) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/sys.cpp Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_STD/startup_stm32f303xe.s Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,380 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303xE devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20004000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX + DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FMC_IRQHandler ; FMC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD ADC4_IRQHandler ; ADC4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD TIM20_BRK_IRQHandler ; TIM20 Break + DCD TIM20_UP_IRQHandler ; TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation + DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TSC_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ADC4_IRQHandler [WEAK] + EXPORT COMP1_2_3_IRQHandler [WEAK] + EXPORT COMP4_5_6_IRQHandler [WEAK] + EXPORT COMP7_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT USBWakeUp_RMP_IRQHandler [WEAK] + EXPORT TIM20_BRK_IRQHandler [WEAK] + EXPORT TIM20_UP_IRQHandler [WEAK] + EXPORT TIM20_TRG_COM_IRQHandler [WEAK] + EXPORT TIM20_CC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TSC_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN_TX_IRQHandler +USB_LP_CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ADC4_IRQHandler +COMP1_2_3_IRQHandler +COMP4_5_6_IRQHandler +COMP7_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +USBWakeUp_RMP_IRQHandler +TIM20_BRK_IRQHandler +TIM20_UP_IRQHandler +TIM20_TRG_COM_IRQHandler +TIM20_CC_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_STD/stm32f303xe.sct Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F303RE: 512KB FLASH (0x80000) + 64KB SRAM (0x10000)
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 101 vectors = 404 bytes (0x194) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x194) (0x10000-0x194) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_STD/sys.cpp Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_IAR/startup_stm32f303xe.s Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,610 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303RE/STM32F303VE/STM32F303ZE devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; 0: Window WatchDog + DCD PVD_IRQHandler ; 1: PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; 2: Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; 3: RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; 4: FLASH + DCD RCC_IRQHandler ; 5: RCC + DCD EXTI0_IRQHandler ; 6: EXTI Line0 + DCD EXTI1_IRQHandler ; 7: EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; 8: EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; 9: EXTI Line3 + DCD EXTI4_IRQHandler ; 10: EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; 11: DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; 12: DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; 13: DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; 14: DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; 15: DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; 16: DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; 17: DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; 18: ADC1 and ADC2 + DCD USB_HP_CAN_TX_IRQHandler ; 19: USB Device High Priority or CAN TX + DCD USB_LP_CAN_RX0_IRQHandler ; 20: USB Device Low Priority or CAN RX0 + DCD CAN_RX1_IRQHandler ; 21: CAN RX1 + DCD CAN_SCE_IRQHandler ; 22: CAN SCE + DCD EXTI9_5_IRQHandler ; 23: External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; 24: TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; 25: TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; 26: TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; 27: TIM1 Capture Compare + DCD TIM2_IRQHandler ; 28: TIM2 + DCD TIM3_IRQHandler ; 29: TIM3 + DCD TIM4_IRQHandler ; 30: TIM4 + DCD I2C1_EV_IRQHandler ; 31: I2C1 Event + DCD I2C1_ER_IRQHandler ; 32: I2C1 Error + DCD I2C2_EV_IRQHandler ; 33: I2C2 Event + DCD I2C2_ER_IRQHandler ; 34: I2C2 Error + DCD SPI1_IRQHandler ; 35: SPI1 + DCD SPI2_IRQHandler ; 36: SPI2 + DCD USART1_IRQHandler ; 37: USART1 + DCD USART2_IRQHandler ; 38: USART2 + DCD USART3_IRQHandler ; 39: USART3 + DCD EXTI15_10_IRQHandler ; 40: External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; 41: RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; 42: USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; 43: TIM8 Break + DCD TIM8_UP_IRQHandler ; 44: TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; 45: TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; 46: TIM8 Capture Compare + DCD ADC3_IRQHandler ; 47: ADC3 + DCD FMC_IRQHandler ; 48: FMC + DCD 0 ; 49: Reserved + DCD 0 ; 50: Reserved + DCD SPI3_IRQHandler ; 51: SPI3 + DCD UART4_IRQHandler ; 52: UART4 + DCD UART5_IRQHandler ; 53: UART5 + DCD TIM6_DAC_IRQHandler ; 54: TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; 55: TIM7 + DCD DMA2_Channel1_IRQHandler ; 56: DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; 57: DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; 58: DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; 59: DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; 60: DMA2 Channel 5 + DCD ADC4_IRQHandler ; 61: ADC4 + DCD 0 ; 62: Reserved + DCD 0 ; 63: Reserved + DCD COMP1_2_3_IRQHandler ; 64: COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; 65: COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; 66: COMP7 + DCD 0 ; 67: Reserved + DCD 0 ; 68: Reserved + DCD 0 ; 69: Reserved + DCD 0 ; 70: Reserved + DCD 0 ; 71: Reserved + DCD I2C3_EV_IRQHandler ; 72: I2C3 Event + DCD I2C3_ER_IRQHandler ; 73: I2C3 Error + DCD USB_HP_IRQHandler ; 74: USB High Priority remap + DCD USB_LP_IRQHandler ; 75: USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; 76: USB Wakeup remap through EXTI + DCD TIM20_BRK_IRQHandler ; 77: TIM20 Break + DCD TIM20_UP_IRQHandler ; 78: TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; 79: TIM20 Trigger and Commutation + DCD TIM20_CC_IRQHandler ; 80: TIM20 Capture Compare + DCD FPU_IRQHandler ; 81: FPU + DCD 0 ; 82: Reserved + DCD 0 ; 83: Reserved + DCD SPI4_IRQHandler ; 84: SPI4 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_TSC_IRQHandler + B EXTI2_TSC_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_CAN_TX_IRQHandler + B USB_HP_CAN_TX_IRQHandler + + PUBWEAK USB_LP_CAN_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_CAN_RX0_IRQHandler + B USB_LP_CAN_RX0_IRQHandler + + PUBWEAK CAN_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_RX1_IRQHandler + B CAN_RX1_IRQHandler + + PUBWEAK CAN_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_SCE_IRQHandler + B CAN_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + + PUBWEAK ADC4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC4_IRQHandler + B ADC4_IRQHandler + + PUBWEAK COMP1_2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_2_3_IRQHandler + B COMP1_2_3_IRQHandler + + PUBWEAK COMP4_5_6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP4_5_6_IRQHandler + B COMP4_5_6_IRQHandler + + PUBWEAK COMP7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP7_IRQHandler + B COMP7_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK USBWakeUp_RMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_RMP_IRQHandler + B USBWakeUp_RMP_IRQHandler + + PUBWEAK TIM20_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_BRK_IRQHandler + B TIM20_BRK_IRQHandler + + PUBWEAK TIM20_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_UP_IRQHandler + B TIM20_UP_IRQHandler + + PUBWEAK TIM20_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_TRG_COM_IRQHandler + B TIM20_TRG_COM_IRQHandler + + PUBWEAK TIM20_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_CC_IRQHandler + B TIM20_CC_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_IAR/stm32f303xe.icf Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,34 @@
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0807FFFF;
+
+define symbol __region_CCMRAM_start__ = 0x10000000;
+define symbol __region_CCMRAM_end__ = 0x10003FFF;
+
+/* [RAM = 64kb = 0x10000] Vector table dynamic copy: 101 vectors = 404 bytes (0x194) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000197; /* Add 4 more bytes to be aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000198;
+define symbol __region_RAM_end__ = 0x2000FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__ = 0x400;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/cmsis.h Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f3xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/cmsis_nvic.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/cmsis_nvic.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F303RE
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to 0x193
+// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+#define NVIC_NUM_VECTORS 101
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/hal_tick.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,120 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+ us_ticker_irq_handler();
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+#if 0 // For DEBUG only
+ HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimMasterHandle.Init.RepetitionCounter = 0;
+ HAL_TIM_OC_Init(&TimMasterHandle);
+
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Channel 1 for mbed timeout
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+ __GPIOB_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/hal_tick.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f3xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM2
+#define TIM_MST_IRQ TIM2_IRQn
+#define TIM_MST_RCC __TIM2_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/stm32f303xe.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,8212 @@
+/**
+ ******************************************************************************
+ * @file stm32f303xe.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 12-Sept-2014
+ * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f303xe
+ * @{
+ */
+
+#ifndef __STM32F303xE_H
+#define __STM32F303xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F303xE devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F303xE devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
+ USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
+ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
+ TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
+ TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
+ TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
+
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
+ uint16_t RESERVED0; /*!< Reserved, 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
+ __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
+ __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
+} OPAMP_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
+ __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
+ __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
+ __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
+ __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
+ __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
+ __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
+ __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
+ __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
+ __IO uint32_t CFGR4; /*!< SYSCFG configuration register 4, Address offset: 0x48 */
+ __IO uint32_t RESERVED12; /*!< Reserved, 0x4C */
+ __IO uint32_t RESERVED13; /*!< Reserved, 0x50 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED0; /*!< Reserved, 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(512KB) base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(16 KB) base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(64KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
+
+#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(16 KB) base address in the bit-band region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(64KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
+#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
+#define DAC_BASE DAC1_BASE
+#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
+#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
+#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
+#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
+#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
+#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
+#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
+#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
+#define COMP_BASE COMP1_BASE
+#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
+#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
+#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
+#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
+#define OPAMP_BASE OPAMP1_BASE
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
+#define TIM20_BASE (APB2PERIPH_BASE + 0x00005000)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
+#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
+#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
+#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
+#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
+#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
+#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+#define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800)
+#define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00)
+
+/*!< AHB3 peripherals */
+#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
+#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
+#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
+#define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400)
+#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
+#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN ((CAN_TypeDef *) CAN_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
+#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
+#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
+#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
+#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
+#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
+#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
+#define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter SAR (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_ISR register ********************/
+#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
+#define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
+
+/******************** Bit definition for ADC_IER register ********************/
+#define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
+#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
+#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
+#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
+#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
+
+/******************** Bit definition for ADC_CFGR register ********************/
+#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
+#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
+
+#define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
+#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
+
+#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
+
+#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
+#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
+#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
+#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
+
+#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
+#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
+
+#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
+#define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
+#define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
+#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
+#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
+#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
+
+#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
+#define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
+#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
+#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
+#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
+#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
+
+/******************** Bit definition for ADC_SMPR1 register ********************/
+#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
+#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
+#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
+#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
+
+#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
+#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
+#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
+#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
+
+#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
+#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
+#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
+#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
+
+#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
+#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
+#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
+#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
+
+#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
+#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
+#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
+#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
+
+#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
+#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
+#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
+#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
+
+#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
+#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
+#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
+#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
+
+#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
+#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
+#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
+#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
+
+#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
+#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
+#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
+#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
+
+#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
+#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
+#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
+#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
+
+/******************** Bit definition for ADC_SMPR2 register ********************/
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
+
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
+
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
+
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
+
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
+
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
+
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
+
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
+
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
+
+/******************** Bit definition for ADC_TR1 register ********************/
+#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
+#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
+#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
+#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
+#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
+#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
+#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
+#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
+#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
+#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
+#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
+#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
+#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
+
+#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
+#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
+#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
+#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
+#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
+#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
+#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
+#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
+#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
+#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
+#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
+#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
+#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
+
+/******************** Bit definition for ADC_TR2 register ********************/
+#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
+#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
+#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
+#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
+#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
+#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
+#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
+#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
+#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
+
+#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
+#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
+#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
+#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
+#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
+#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
+#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
+#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
+#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
+
+/******************** Bit definition for ADC_TR3 register ********************/
+#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
+#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
+#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
+#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
+#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
+#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
+#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
+#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
+#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
+
+#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
+#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
+#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
+#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
+#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
+#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
+#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
+#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
+#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
+
+/******************** Bit definition for ADC_SQR1 register ********************/
+#define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
+
+#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
+#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
+#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
+#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
+#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
+
+#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
+#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
+#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
+#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
+#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
+
+#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
+#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
+#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
+#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
+#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
+
+#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
+#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
+#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
+#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
+#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
+
+/******************** Bit definition for ADC_SQR2 register ********************/
+#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
+#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
+#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
+#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
+#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
+
+#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
+#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
+#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
+#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
+#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
+
+#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
+
+/******************** Bit definition for ADC_SQR3 register ********************/
+#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
+#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
+#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
+#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
+#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
+
+#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
+#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
+#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
+#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
+#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
+
+#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
+#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
+#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
+#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
+#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
+
+#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
+
+#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
+
+/******************** Bit definition for ADC_SQR4 register ********************/
+#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
+#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
+#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
+#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
+#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
+
+#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
+#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
+#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
+#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
+#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
+#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
+#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
+#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
+#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
+#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
+#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
+#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
+#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
+#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
+#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
+#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
+#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
+#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
+#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
+#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
+#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
+
+/******************** Bit definition for ADC_JSQR register ********************/
+#define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
+
+#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
+#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
+#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
+#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
+
+#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
+#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
+
+#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
+
+/******************** Bit definition for ADC_OFR1 register ********************/
+#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
+#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
+#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
+#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
+#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
+#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
+#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
+#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
+#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
+#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
+#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
+#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
+
+#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
+#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
+#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
+#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
+#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
+
+#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
+
+/******************** Bit definition for ADC_OFR2 register ********************/
+#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
+#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
+#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
+#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
+#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
+#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
+#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
+#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
+#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
+#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
+#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
+#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
+
+#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
+#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
+#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
+#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
+#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
+
+#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
+
+/******************** Bit definition for ADC_OFR3 register ********************/
+#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
+#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
+#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
+#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
+#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
+#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
+#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
+#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
+#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
+#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
+#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
+#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
+
+#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
+#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
+#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
+#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
+#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
+
+#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
+
+/******************** Bit definition for ADC_OFR4 register ********************/
+#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
+#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
+#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
+#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
+#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
+#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
+#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
+#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
+#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
+#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
+#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
+#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
+
+#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
+#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
+#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
+#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
+#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
+
+#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
+
+/******************** Bit definition for ADC_JDR1 register ********************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR2 register ********************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR3 register ********************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR4 register ********************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_AWD2CR register ********************/
+#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
+#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
+#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
+#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
+#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
+#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
+#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
+#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
+#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
+#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
+#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
+#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
+#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
+#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
+#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
+#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
+#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
+#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
+
+/******************** Bit definition for ADC_AWD3CR register ********************/
+#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
+#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
+#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
+#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
+#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
+#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
+#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
+#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
+#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
+#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
+#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
+#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
+#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
+#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
+#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
+#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
+#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
+#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
+
+/******************** Bit definition for ADC_DIFSEL register ********************/
+#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
+#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
+#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
+#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
+#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
+#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
+#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
+#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
+#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
+#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
+#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
+#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
+#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
+#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
+#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
+#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
+#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
+#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
+#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
+#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
+#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
+#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
+#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
+#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
+#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
+#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
+#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
+#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
+#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
+#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
+#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC12_CSR register ********************/
+#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC34_CSR register ********************/
+#define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+
+#define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+
+#define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+
+#define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+
+#define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC34_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC34_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/********************** Bit definition for COMP1_CSR register ***************/
+#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
+#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
+#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
+#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
+#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
+#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
+#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
+#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
+#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
+#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
+#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
+#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
+
+/********************** Bit definition for COMP2_CSR register ***************/
+#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
+#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
+#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
+#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
+#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
+#define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
+#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
+#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
+#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
+#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
+#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
+#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
+#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
+#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
+#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
+#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
+#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/********************** Bit definition for COMP3_CSR register ***************/
+#define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
+#define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
+#define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
+#define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
+#define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
+#define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
+#define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
+#define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
+#define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
+#define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
+#define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
+#define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
+#define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
+#define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
+#define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
+#define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
+#define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
+
+/********************** Bit definition for COMP4_CSR register ***************/
+#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
+#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
+#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
+#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
+#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
+#define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
+#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
+#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
+#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
+#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
+#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
+#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
+#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
+#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
+#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
+#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
+#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
+#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
+
+/********************** Bit definition for COMP5_CSR register ***************/
+#define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
+#define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
+#define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
+#define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
+#define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
+#define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
+#define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
+#define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
+#define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
+#define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
+#define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
+#define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
+#define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
+#define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
+#define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
+#define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
+#define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
+
+/********************** Bit definition for COMP6_CSR register ***************/
+#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
+#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
+#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
+#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
+#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
+#define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
+#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
+#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
+#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
+#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
+#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
+#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
+#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
+#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
+#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
+#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
+#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
+#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
+
+/********************** Bit definition for COMP7_CSR register ***************/
+#define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
+#define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
+#define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
+#define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
+#define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
+#define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
+#define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
+#define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
+#define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
+#define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
+#define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
+#define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
+#define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
+#define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
+#define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
+#define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
+#define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
+
+/********************** Bit definition for COMP_CSR register ****************/
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
+#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
+#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
+#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/********************* Bit definition for OPAMP1_CSR register ***************/
+#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
+#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP2_CSR register ***************/
+#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
+#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP3_CSR register ***************/
+#define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
+#define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP4_CSR register ***************/
+#define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
+#define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMPx_CSR register ***************/
+#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network (CAN ) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x04000000)
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB2_FZ_DBG_TIM20_STOP ((uint32_t)0x00000020)
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+
+/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+
+/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
+#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
+#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
+#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
+#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
+
+/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
+#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
+#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
+#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
+#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
+
+/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
+#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
+#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
+#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
+#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
+
+/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
+#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
+#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
+#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
+#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+#define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
+#define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
+#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
+#define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+#define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register ********************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
+
+#define RCC_CFGR_USBPRE_DIV1_5 ((uint32_t)0x00000000) /*!< USB prescaler is PLL clock divided by 1.5 */
+#define RCC_CFGR_USBPRE_DIV1 ((uint32_t)0x00400000) /*!< USB prescaler is PLL clock divided by 1 */
+
+/*!< I2S configuration */
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
+
+#define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
+#define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+
+/********************* Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/****************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00008000) /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
+#define RCC_APB2RSTR_TIM20RST ((uint32_t)0x00100000) /*!< TIM20 reset */
+
+/****************** Bit definition for RCC_APB1RSTR register ******************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
+#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
+#define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_FMCEN ((uint32_t)0x00000020) /*!< FMC clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00010000) /*!< GPIOH clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00800000) /*!< GPIOG clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
+#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00008000) /*!< SPI4 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_TIM20EN ((uint32_t)0x00100000) /*!< TIM20 clock enable */
+
+/****************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+#define RCC_AHBRSTR_FMCRST ((uint32_t)0x00000020) /*!< FMC reset */
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00010000) /*!< GPIOH reset */
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
+#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00800000) /*!< GPIOG reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
+#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
+#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x20000000) /*!< ADC3 & ADC4 reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/*!< ADCPRE12 configuration */
+#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
+#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
+
+/*!< ADCPRE34 configuration */
+#define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
+#define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
+#define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
+
+/******************* Bit definition for RCC_CFGR3 register ******************/
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+
+#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
+#define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
+#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
+#define RCC_CFGR3_I2C3SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C3 clock source */
+#define RCC_CFGR3_I2C3SW_SYSCLK ((uint32_t)0x00000040) /*!< System clock selected as I2C3 clock source */
+
+#define RCC_CFGR3_TIMSW ((uint32_t)0x0000AF00) /*!< TIMSW bits */
+#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
+#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
+#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
+#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
+#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
+#define RCC_CFGR3_TIM20SW ((uint32_t)0x00008000) /*!< TIM20SW bits */
+#define RCC_CFGR3_TIM2SW ((uint32_t)0x01000000) /*!< TIM2SW bits */
+#define RCC_CFGR3_TIM34SW ((uint32_t)0x02000000) /*!< TIM34SW bits */
+
+#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
+#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
+
+#define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
+#define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
+
+#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
+#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
+
+#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
+#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
+
+#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
+#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
+
+#define RCC_CFGR3_TIM20SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM20 clock source */
+#define RCC_CFGR3_TIM20SW_PLL ((uint32_t)0x00008000) /*!< PLL clock used as TIM20 clock source */
+
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
+#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
+#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
+
+#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
+#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
+#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
+
+#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
+#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
+#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
+
+#define RCC_CFGR3_TIM2SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM2 clock source */
+#define RCC_CFGR3_TIM2SW_PLL ((uint32_t)0x01000000) /*!< PLL clock used as TIM2 clock source */
+
+#define RCC_CFGR3_TIM34SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM3/TIM4 clock source */
+#define RCC_CFGR3_TIM34SW_PLL ((uint32_t)0x02000000) /*!< PLL clock used as TIM3/TIM4 clock source */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration(SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_CFGR1_MEM_MODE_2 ((uint32_t)0x00000004) /*!< Bit 1 */
+#define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
+#define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00007900) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
+#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
+#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
+#define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x01000000) /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
+#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
+#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
+#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
+#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
+#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
+
+/***************** Bit definition for SYSCFG_RCR register *******************/
+#define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
+#define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
+#define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
+#define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
+#define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
+#define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
+#define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
+#define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
+#define SYSCFG_RCR_PAGE8 ((uint32_t)0x00000100) /*!< ICODE SRAM Write protection page 8 */
+#define SYSCFG_RCR_PAGE9 ((uint32_t)0x00000200) /*!< ICODE SRAM Write protection page 9 */
+#define SYSCFG_RCR_PAGE10 ((uint32_t)0x00000400) /*!< ICODE SRAM Write protection page 10 */
+#define SYSCFG_RCR_PAGE11 ((uint32_t)0x00000800) /*!< ICODE SRAM Write protection page 11 */
+#define SYSCFG_RCR_PAGE12 ((uint32_t)0x00001000) /*!< ICODE SRAM Write protection page 12 */
+#define SYSCFG_RCR_PAGE13 ((uint32_t)0x00002000) /*!< ICODE SRAM Write protection page 13 */
+#define SYSCFG_RCR_PAGE14 ((uint32_t)0x00004000) /*!< ICODE SRAM Write protection page 14 */
+#define SYSCFG_RCR_PAGE15 ((uint32_t)0x00008000) /*!< ICODE SRAM Write protection page 15 */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+
+/*!<*
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!< PH[0] pin */
+
+/*!<*
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!< PH[1] pin */
+
+/*!<*
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
+
+/*!<*
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+
+/*!<*
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!< PH[4] pin */
+
+/*!<*
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
+
+/*!<*
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
+
+/*!<*
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+
+/*!<*
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
+
+/*!<*
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
+
+/*!<*
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
+
+/*!<*
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+
+/*!<*
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
+
+/*!<*
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
+
+/*!<*
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
+
+/*!<*
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
+#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/***************** Bit definition for SYSCFG_CFGR4 register *****************/
+#define SYSCFG_CFGR4_ADC12_EXT2_RMP ((uint32_t)0x00000001) /*!< ADC12 regular channel EXT2 remap */
+#define SYSCFG_CFGR4_ADC12_EXT3_RMP ((uint32_t)0x00000002) /*!< ADC12 regular channel EXT3 remap */
+#define SYSCFG_CFGR4_ADC12_EXT5_RMP ((uint32_t)0x00000004) /*!< ADC12 regular channel EXT5 remap */
+#define SYSCFG_CFGR4_ADC12_EXT13_RMP ((uint32_t)0x00000008) /*!< ADC12 regular channel EXT13 remap */
+#define SYSCFG_CFGR4_ADC12_EXT15_RMP ((uint32_t)0x00000010) /*!< ADC12 regular channel EXT15 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT3_RMP ((uint32_t)0x00000020) /*!< ADC12 injected channel JEXT3 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT6_RMP ((uint32_t)0x00000040) /*!< ADC12 injected channel JEXT6 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT13_RMP ((uint32_t)0x00000080) /*!< ADC12 injected channel JEXT13 remap */
+#define SYSCFG_CFGR4_ADC34_EXT5_RMP ((uint32_t)0x00000100) /*!< ADC34 regular channel EXT5 remap */
+#define SYSCFG_CFGR4_ADC34_EXT6_RMP ((uint32_t)0x00000200) /*!< ADC34 regular channel EXT6 remap */
+#define SYSCFG_CFGR4_ADC34_EXT15_RMP ((uint32_t)0x00000400) /*!< ADC34 regular channel EXT15 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT5_RMP ((uint32_t)0x00000800) /*!< ADC34 injected channel JEXT5 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT11_RMP ((uint32_t)0x00001000) /*!< ADC34 injected channel JEXT11 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT14_RMP ((uint32_t)0x00002000) /*!< ADC34 injected channel JEXT14 remap */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+#define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCR5 register *******************/
+#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
+
+/******************* Bit definition for TIM_CCR6 register *******************/
+#define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM16_OR register ********************/
+#define TIM16_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
+#define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************* Bit definition for TIM1_OR register ********************/
+#define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
+#define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/******************* Bit definition for TIM8_OR register ********************/
+#define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
+#define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/******************* Bit definition for TIM20_OR register *******************/
+#define TIM20_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */
+#define TIM20_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM20_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM20_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM20_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR3 register *******************/
+#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
+
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
+
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3) || \
+ ((INSTANCE) == ADC4))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON) || \
+ ((INSTANCE) == ADC3_4_COMMON))
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
+
+/****************************** COMP Instances ********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2) || \
+ ((INSTANCE) == COMP3) || \
+ ((INSTANCE) == COMP4) || \
+ ((INSTANCE) == COMP5) || \
+ ((INSTANCE) == COMP6) || \
+ ((INSTANCE) == COMP7))
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
+ ((INSTANCE) == COMP4) || \
+ ((INSTANCE) == COMP6))
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
+ (((INSTANCE) == DAC1) && \
+ (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2)))
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+ ((INSTANCE) == OPAMP2) || \
+ ((INSTANCE) == OPAMP3) || \
+ ((INSTANCE) == OPAMP4))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/******************* TIM Instances : All supported instances ******************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/******************* TIM Instances : at least 1 capture/compare channel *******/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 2 capture/compare channels *******/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 3 capture/compare channels *******/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 4 capture/compare channels *******/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/************************** TIM Instances : Advanced-control timers ***********/
+
+/****************** TIM Instances : supporting clock selection ****************/
+#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting Hall interface *****************/
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting input XOR function *************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting master mode ********************/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting slave mode *********************/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : supporting DMA burst **********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting input/output channel(s) ********/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM20) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM20) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting DMA generation on Update events*/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting DMA generation on Capture/Compare events */
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting remapping capability ***********/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Driver Enable ****************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************************** USB Instances *********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F3xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F3 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define ADC1_IRQn ADC1_2_IRQn
+#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
+#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define COMP_IRQn COMP1_2_3_IRQn
+#define COMP2_IRQn COMP1_2_3_IRQn
+#define COMP1_2_IRQn COMP1_2_3_IRQn
+#define COMP4_6_IRQn COMP4_5_6_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
+#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define COMP_IRQHandler COMP1_2_3_IRQHandler
+#define COMP2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F303xE_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/stm32f3xx.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,238 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 12-Sept-2014
+ * @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F3xx device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f3xx
+ * @{
+ */
+
+#ifndef __STM32F3xx_H
+#define __STM32F3xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
+ !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \
+ !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
+ !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
+ !defined (STM32F373xC) && !defined (STM32F378xx)
+
+ /* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
+ STM32F301R6 and STM32F301R8 Devices */
+ /* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
+ STM32F302R6 and STM32F302R8 Devices */
+ /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB and STM32F302VC Devices */
+ /* #define STM32F302xE */ /*!< STM32F302CE, STM32F302RE, and STM32F302VE Devices */
+ /* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
+ STM32F303R6 and STM32F303R8 Devices */
+ /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
+#define STM32F303xE /*!< STM32F303RE, STM32F303VE and STM32F303ZE Devices */
+ /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC,
+ STM32F373V8, STM32F373VB and STM32F373VC Devices */
+ /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
+ /* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
+ /* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
+ /* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
+ /* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
+ /* #define STM32F398xx */ /*!< STM32F398CE, STM32F398RE, STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.1.0
+ */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F301x8)
+ #include "stm32f301x8.h"
+#elif defined(STM32F302x8)
+ #include "stm32f302x8.h"
+#elif defined(STM32F302xC)
+ #include "stm32f302xc.h"
+#elif defined(STM32F302xE)
+ #include "stm32f302xe.h"
+#elif defined(STM32F303x8)
+ #include "stm32f303x8.h"
+#elif defined(STM32F303xC)
+ #include "stm32f303xc.h"
+#elif defined(STM32F303xE)
+ #include "stm32f303xe.h"
+#elif defined(STM32F373xC)
+ #include "stm32f373xc.h"
+#elif defined(STM32F334x8)
+ #include "stm32f334x8.h"
+#elif defined(STM32F318xx)
+ #include "stm32f318xx.h"
+#elif defined(STM32F328xx)
+ #include "stm32f328xx.h"
+#elif defined(STM32F358xx)
+ #include "stm32f358xx.h"
+#elif defined(STM32F378xx)
+ #include "stm32f378xx.h"
+#elif defined(STM32F398xx)
+ #include "stm32f398xx.h"
+#else
+ #error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f3xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F3xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,456 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f3xx.c
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 12-Sept-2014
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f3xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 8 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 36 | 32
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | NO | NO
+ *-----------------------------------------------------------------------------
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f3xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f3xx.h"
+#include "hal_tick.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 72000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR &= 0xF87FC00C;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+ RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+ }
+ else
+ {
+ /* HSI oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
+ }
+#else
+ if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0)
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ }
+ else
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,124 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f3xx.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 12-Sept-2014
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f3xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F3XX_H
+#define __SYSTEM_STM32F3XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F3xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F3xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F3XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralPins.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,151 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM1 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_4, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14)}, // TIM14_CH1
+ {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1
+// {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16)}, // TIM16_CH1
+ {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2
+// {PA_7, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14)}, // TIM14_CH1
+// {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17)}, // TIM17_CH1
+ {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH3
+ {PB_1, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14)}, // TIM14_CH1
+// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH4
+ {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2
+ {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16)}, // TIM16_CH1N
+ {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17)}, // TIM17_CH1N
+ {PB_8, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16)}, // TIM16_CH1
+ {PB_9, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17)}, // TIM17_CH1
+ {PB_14, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM15)}, // TIM15_CH1
+ {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM15)}, // TIM15_CH2
+// {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM15)}, // TIM15_CH1N
+ {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2
+ {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLDOWN, GPIO_AF0_SPI2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)},
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralPins.h Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,62 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +//*** ADC *** + +extern const PinMap PinMap_ADC[]; + +//*** I2C *** + +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +//*** PWM *** + +extern const PinMap PinMap_PWM[]; + +//*** SERIAL *** + +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +//*** SPI *** + +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; + +#endif
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PinNames.h Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PinNames.h Tue Dec 02 15:45:09 2014 +0000
@@ -36,15 +36,24 @@
extern "C" {
#endif
-// MODE (see GPIOMode_TypeDef structure)
-// OTYPE (see GPIOOType_TypeDef structure)
-// PUPD (see GPIOPuPd_TypeDef structure)
-// AFNUM (see AF_mapping constant table, 0xFF is not used)
-#define STM_PIN_DATA(MODE, OTYPE, PUPD, AFNUM) (((AFNUM)<<8)|((PUPD)<<4)|((OTYPE)<<2)|((MODE)<<0))
-#define STM_PIN_MODE(X) (((X)>>0) & 0x3)
-#define STM_PIN_OTYPE(X) (((X)>>2) & 0x1)
-#define STM_PIN_PUPD(X) (((X)>>4) & 0x3)
-#define STM_PIN_AFNUM(X) (((X)>>8) & 0xF)
+// See stm32f0xx_hal_gpio.h and stm32f0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
+#define STM_MODE_INPUT (0)
+#define STM_MODE_OUTPUT_PP (1)
+#define STM_MODE_OUTPUT_OD (2)
+#define STM_MODE_AF_PP (3)
+#define STM_MODE_AF_OD (4)
+#define STM_MODE_ANALOG (5)
+#define STM_MODE_IT_RISING (6)
+#define STM_MODE_IT_FALLING (7)
+#define STM_MODE_IT_RISING_FALLING (8)
+#define STM_MODE_EVT_RISING (9)
+#define STM_MODE_EVT_FALLING (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
@@ -201,6 +210,8 @@
LED3 = PC_9,
LED4 = PC_8,
USER_BUTTON = PA_0,
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
USBTX = PA_2,
USBRX = PA_3,
I2C_SCL = PB_8,
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/analogin_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/analogin_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -30,39 +30,18 @@
#if DEVICE_ANALOGIN
+#include "wait_api.h"
#include "cmsis.h"
#include "pinmap.h"
-#include "mbed_error.h"
-#include "wait_api.h"
+#include "PeripheralPins.h"
-static const PinMap PinMap_ADC[] = {
- {PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN0
- {PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN1
- {PA_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN2
- {PA_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN3
- {PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN4
- {PA_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN5
- {PA_6, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN6
- {PA_7, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN7
- {PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN8
- {PB_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN9
- {PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN10
- {PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN11
- {PC_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN12
- {PC_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN13
- {PC_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN14
- {PC_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN15
- {NC, NC, 0}
-};
+ADC_HandleTypeDef AdcHandle;
int adc_inited = 0;
-void analogin_init(analogin_t *obj, PinName pin) {
-
- ADC_TypeDef *adc;
- ADC_InitTypeDef ADC_InitStructure;
-
- // Get the peripheral name (ADC_1, ADC_2...) from the pin and assign it to the object
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ // Get the peripheral name from the pin and assign it to the object
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
@@ -76,103 +55,119 @@
if (adc_inited == 0) {
adc_inited = 1;
- // Get ADC registers structure address
- adc = (ADC_TypeDef *)(obj->adc);
-
// Enable ADC clock
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
+ __ADC1_CLK_ENABLE();
// Configure ADC
- ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;
- ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
- ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
- ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;
- ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
- ADC_InitStructure.ADC_ScanDirection = ADC_ScanDirection_Upward;
- ADC_Init(adc, &ADC_InitStructure);
+ AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+ AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
+ AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
+ AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ AdcHandle.Init.ScanConvMode = DISABLE;
+ AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV;
+ AdcHandle.Init.LowPowerAutoWait = DISABLE;
+ AdcHandle.Init.LowPowerAutoPowerOff = DISABLE;
+ AdcHandle.Init.ContinuousConvMode = DISABLE;
+ AdcHandle.Init.DiscontinuousConvMode = DISABLE;
+ AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ AdcHandle.Init.DMAContinuousRequests = DISABLE;
+ AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN;
+ HAL_ADC_Init(&AdcHandle);
- // Calibrate ADC
- ADC_GetCalibrationFactor(adc);
-
- // Enable ADC
- ADC_Cmd(adc, ENABLE);
+ // Run the ADC calibration
+ HAL_ADCEx_Calibration_Start(&AdcHandle);
}
}
-static inline uint16_t adc_read(analogin_t *obj) {
- // Get ADC registers structure address
- ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
+static inline uint16_t adc_read(analogin_t *obj)
+{
+ ADC_ChannelConfTypeDef sConfig;
- adc->CHSELR = 0; // Clear all channels first
+ AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
// Configure ADC channel
+ sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+ sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
+
switch (obj->pin) {
case PA_0:
- ADC_ChannelConfig(adc, ADC_Channel_0, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_0;
break;
case PA_1:
- ADC_ChannelConfig(adc, ADC_Channel_1, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_1;
break;
case PA_2:
- ADC_ChannelConfig(adc, ADC_Channel_2, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_2;
break;
case PA_3:
- ADC_ChannelConfig(adc, ADC_Channel_3, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_3;
break;
case PA_4:
- ADC_ChannelConfig(adc, ADC_Channel_4, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_4;
break;
case PA_5:
- ADC_ChannelConfig(adc, ADC_Channel_5, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_5;
break;
case PA_6:
- ADC_ChannelConfig(adc, ADC_Channel_6, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_6;
break;
case PA_7:
- ADC_ChannelConfig(adc, ADC_Channel_7, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_7;
break;
case PB_0:
- ADC_ChannelConfig(adc, ADC_Channel_8, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_8;
break;
case PB_1:
- ADC_ChannelConfig(adc, ADC_Channel_9, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_9;
break;
case PC_0:
- ADC_ChannelConfig(adc, ADC_Channel_10, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_10;
break;
case PC_1:
- ADC_ChannelConfig(adc, ADC_Channel_11, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_11;
break;
case PC_2:
- ADC_ChannelConfig(adc, ADC_Channel_12, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_12;
break;
case PC_3:
- ADC_ChannelConfig(adc, ADC_Channel_13, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_13;
break;
case PC_4:
- ADC_ChannelConfig(adc, ADC_Channel_14, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_14;
break;
case PC_5:
- ADC_ChannelConfig(adc, ADC_Channel_15, ADC_SampleTime_7_5Cycles);
+ sConfig.Channel = ADC_CHANNEL_15;
break;
default:
return 0;
}
- while (!ADC_GetFlagStatus(adc, ADC_FLAG_ADRDY)); // Wait ADC ready
+ // Clear all channels as it is not done in HAL_ADC_ConfigChannel()
+ AdcHandle.Instance->CHSELR = 0;
- ADC_StartOfConversion(adc); // Start conversion
+ HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+
+ HAL_ADC_Start(&AdcHandle); // Start conversion
- while (ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
-
- return (ADC_GetConversionValue(adc)); // Get conversion value
+ // Wait end of conversion and get value
+ if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&AdcHandle));
+ } else {
+ return 0;
+ }
}
-uint16_t analogin_read_u16(analogin_t *obj) {
- return (adc_read(obj));
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ uint16_t value = adc_read(obj);
+ // 12-bit to 16-bit conversion
+ value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
+ return value;
}
-float analogin_read(analogin_t *obj) {
+float analogin_read(analogin_t *obj)
+{
uint16_t value = adc_read(obj);
return (float)value * (1.0f / (float)0xFFF); // 12 bits range
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -34,17 +34,21 @@
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-uint32_t gpio_set(PinName pin) {
+uint32_t gpio_set(PinName pin)
+{
MBED_ASSERT(pin != (PinName)NC);
- pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+ pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
}
-void gpio_init(gpio_t *obj, PinName pin) {
+void gpio_init(gpio_t *obj, PinName pin)
+{
obj->pin = pin;
- if (pin == (PinName)NC)
+ if (pin == (PinName)NC) {
return;
+ }
uint32_t port_index = STM_PORT(pin);
@@ -59,15 +63,17 @@
obj->reg_clr = &gpio->BRR;
}
-void gpio_mode(gpio_t *obj, PinMode mode) {
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
pin_mode(obj->pin, mode);
}
-void gpio_dir(gpio_t *obj, PinDirection direction) {
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
MBED_ASSERT(obj->pin != (PinName)NC);
if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
} else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_irq_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_irq_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -39,51 +39,107 @@
#define EDGE_FALL (2)
#define EDGE_BOTH (3)
+// Number of EXTI irq vectors (EXTI0_1, EXTI2_3, EXTI4_15)
#define CHANNEL_NUM (3)
-static uint32_t channel_ids[CHANNEL_NUM] = {0, 0, 0};
-static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0};
-static uint32_t channel_pin[CHANNEL_NUM] = {0, 0, 0};
+// Max pins for one line (max with EXTI4_15)
+#define MAX_PIN_LINE (12)
+
+typedef struct gpio_channel {
+ uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
+ uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
+ uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
+ uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
+} gpio_channel_t;
+
+static gpio_channel_t channels[CHANNEL_NUM] = {
+ {.pin_mask = 0},
+ {.pin_mask = 0},
+ {.pin_mask = 0}
+};
+
+// Used to return the index for channels array.
+static uint32_t pin_base_nr[16] = {
+ // EXTI0_1
+ 0, // pin 0
+ 1, // pin 1
+ // EXTI2_3
+ 0, // pin 2
+ 1, // pin 3
+ // EXTI4_15
+ 0, // pin 4
+ 1, // pin 5
+ 2, // pin 6
+ 3, // pin 7
+ 4, // pin 8
+ 5, // pin 9
+ 6, // pin 10
+ 7, // pin 11
+ 8, // pin 12
+ 9, // pin 13
+ 10, // pin 14
+ 11 // pin 15
+};
static gpio_irq_handler irq_handler;
-static void handle_interrupt_in(uint32_t irq_index) {
+static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
+{
+ gpio_channel_t *gpio_channel = &channels[irq_index];
+ uint32_t gpio_idx;
+
+ for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
+ uint32_t current_mask = (1 << gpio_idx);
+
+ if (gpio_channel->pin_mask & current_mask) {
// Retrieve the gpio and pin that generate the irq
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]);
- uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
+ uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
// Clear interrupt flag
- if (EXTI_GetITStatus(pin) != RESET) {
- EXTI_ClearITPendingBit(pin);
- }
+ if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
+ __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
- if (channel_ids[irq_index] == 0) return;
+ if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
// Check which edge has generated the irq
if ((gpio->IDR & pin) == 0) {
- irq_handler(channel_ids[irq_index], IRQ_FALL);
+ irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
} else {
- irq_handler(channel_ids[irq_index], IRQ_RISE);
+ irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
+ }
+ }
+ }
}
}
-// The irq_index is passed to the function
-static void gpio_irq0(void) {
- handle_interrupt_in(0);
+// EXTI lines 0 to 1
+static void gpio_irq0(void)
+{
+ handle_interrupt_in(0, 2);
}
-static void gpio_irq1(void) {
- handle_interrupt_in(1);
+
+// EXTI lines 2 to 3
+static void gpio_irq1(void)
+{
+ handle_interrupt_in(1, 2);
}
-static void gpio_irq2(void) {
- handle_interrupt_in(2);
+
+// EXTI lines 4 to 15
+static void gpio_irq2(void)
+{
+ handle_interrupt_in(2, 12);
}
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
uint32_t irq_index;
+ gpio_channel_t *gpio_channel;
+ uint32_t gpio_idx;
if (pin == NC) return -1;
@@ -111,27 +167,10 @@
// Enable GPIO clock
uint32_t gpio_add = Set_GPIO_Clock(port_index);
- // Enable SYSCFG clock
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- // Connect EXTI line to pin
- SYSCFG_EXTILineConfig(port_index, pin_index);
-
- // Configure EXTI line
- EXTI_InitTypeDef EXTI_InitStructure;
- EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index);
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
-
- // Enable and set EXTI interrupt to the lowest priority
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel = irq_n;
- NVIC_InitStructure.NVIC_IRQChannelPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
+ // Configure GPIO
+ pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
+ // Enable EXTI interrupt
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
@@ -139,68 +178,91 @@
obj->irq_n = irq_n;
obj->irq_index = irq_index;
obj->event = EDGE_NONE;
- channel_ids[irq_index] = id;
- channel_gpio[irq_index] = gpio_add;
- channel_pin[irq_index] = pin_index;
+ obj->pin = pin;
+
+ gpio_channel = &channels[irq_index];
+ gpio_idx = pin_base_nr[pin_index];
+ gpio_channel->pin_mask |= (1 << gpio_idx);
+ gpio_channel->channel_ids[gpio_idx] = id;
+ gpio_channel->channel_gpio[gpio_idx] = gpio_add;
+ gpio_channel->channel_pin[gpio_idx] = pin_index;
irq_handler = handler;
return 0;
}
-void gpio_irq_free(gpio_irq_t *obj) {
- channel_ids[obj->irq_index] = 0;
- channel_gpio[obj->irq_index] = 0;
- channel_pin[obj->irq_index] = 0;
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ gpio_channel_t *gpio_channel = &channels[obj->irq_index];
+ uint32_t pin_index = STM_PIN(obj->pin);
+ uint32_t gpio_idx = pin_base_nr[pin_index];
+
+ gpio_channel->pin_mask &= ~(1 << gpio_idx);
+ gpio_channel->channel_ids[gpio_idx] = 0;
+ gpio_channel->channel_gpio[gpio_idx] = 0;
+ gpio_channel->channel_pin[gpio_idx] = 0;
+
// Disable EXTI line
- EXTI_InitTypeDef EXTI_InitStructure;
- EXTI_StructInit(&EXTI_InitStructure);
- EXTI_Init(&EXTI_InitStructure);
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
obj->event = EDGE_NONE;
}
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
- EXTI_InitTypeDef EXTI_InitStructure;
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ uint32_t mode = STM_MODE_IT_EVT_RESET;
+ uint32_t pull = GPIO_NOPULL;
- uint32_t pin_index = channel_pin[obj->irq_index];
-
- EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index);
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-
+ if (enable) {
if (event == IRQ_RISE) {
if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+ mode = STM_MODE_IT_RISING_FALLING;
obj->event = EDGE_BOTH;
} else { // NONE or RISE
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+ mode = STM_MODE_IT_RISING;
obj->event = EDGE_RISE;
}
}
-
if (event == IRQ_FALL) {
if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+ mode = STM_MODE_IT_RISING_FALLING;
obj->event = EDGE_BOTH;
} else { // NONE or FALL
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
+ mode = STM_MODE_IT_FALLING;
obj->event = EDGE_FALL;
}
}
+ } else { // Disable
+ if (event == IRQ_RISE) {
+ if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_FALLING;
+ obj->event = EDGE_FALL;
+ } else { // NONE or RISE
+ mode = STM_MODE_IT_EVT_RESET;
+ obj->event = EDGE_NONE;
+ }
+ }
+ if (event == IRQ_FALL) {
+ if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_RISING;
+ obj->event = EDGE_RISE;
+ } else { // NONE or FALL
+ mode = STM_MODE_IT_EVT_RESET;
+ obj->event = EDGE_NONE;
+ }
+ }
+ }
- if (enable) {
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- } else {
- EXTI_InitStructure.EXTI_LineCmd = DISABLE;
- }
-
- EXTI_Init(&EXTI_InitStructure);
+ pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
}
-void gpio_irq_enable(gpio_irq_t *obj) {
+void gpio_irq_enable(gpio_irq_t *obj)
+{
NVIC_EnableIRQ(obj->irq_n);
}
-void gpio_irq_disable(gpio_irq_t *obj) {
+void gpio_irq_disable(gpio_irq_t *obj)
+{
NVIC_DisableIRQ(obj->irq_n);
obj->event = EDGE_NONE;
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h Tue Dec 02 15:45:09 2014 +0000
@@ -43,12 +43,13 @@
typedef struct {
PinName pin;
uint32_t mask;
- __IO uint16_t *reg_in;
+ __IO uint32_t *reg_in;
__IO uint32_t *reg_set;
- __IO uint16_t *reg_clr;
+ __IO uint32_t *reg_clr;
} gpio_t;
-static inline void gpio_write(gpio_t *obj, int value) {
+static inline void gpio_write(gpio_t *obj, int value)
+{
MBED_ASSERT(obj->pin != (PinName)NC);
if (value) {
*obj->reg_set = obj->mask;
@@ -57,7 +58,8 @@
}
}
-static inline int gpio_read(gpio_t *obj) {
+static inline int gpio_read(gpio_t *obj)
+{
MBED_ASSERT(obj->pin != (PinName)NC);
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/i2c_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/i2c_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -34,6 +34,7 @@
#include "cmsis.h"
#include "pinmap.h"
+#include "PeripheralPins.h"
/* Timeout values for flags and events waiting loops. These timeouts are
not based on accurate values, they just guarantee that the application will
@@ -41,21 +42,13 @@
#define FLAG_TIMEOUT ((int)0x1000)
#define LONG_TIMEOUT ((int)0x8000)
-static const PinMap PinMap_I2C_SDA[] = {
- {PB_7, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_1)},
- {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_1)},
- {PB_11, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_1)},
- {NC, NC, 0}
-};
+I2C_HandleTypeDef I2cHandle;
-static const PinMap PinMap_I2C_SCL[] = {
- {PB_6, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_1)},
- {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_1)},
- {PB_10, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_1)},
- {NC, NC, 0}
-};
+int i2c1_inited = 0;
+int i2c2_inited = 0;
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
// Determine the I2C to use
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
@@ -63,20 +56,28 @@
obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT(obj->i2c != (I2CName)NC);
- // Enable I2C clock
- if (obj->i2c == I2C_1) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
- RCC_I2CCLKConfig(RCC_I2C1CLK_SYSCLK);
- }
- if (obj->i2c == I2C_2) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
+ // Enable I2C1 clock and pinout if not done
+ if ((obj->i2c == I2C_1) && !i2c1_inited) {
+ i2c1_inited = 1;
+ __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK);
+ __I2C1_CLK_ENABLE();
+ // Configure I2C pins
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(sda, OpenDrain);
+ pin_mode(scl, OpenDrain);
}
- // Configure I2C pins
- pinmap_pinout(scl, PinMap_I2C_SCL);
- pin_mode(scl, OpenDrain);
+ // Enable I2C2 clock and pinout if not done
+ if ((obj->i2c == I2C_2) && !i2c2_inited) {
+ i2c2_inited = 1;
+ __I2C2_CLK_ENABLE();
+ // Configure I2C pins
pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(sda, OpenDrain);
+ pin_mode(scl, OpenDrain);
+ }
// Reset to clear pending flags if any
i2c_reset(obj);
@@ -85,103 +86,87 @@
i2c_frequency(obj, 100000); // 100 kHz per default
}
-void i2c_frequency(i2c_t *obj, int hz) {
- MBED_ASSERT((hz == 100000) || (hz == 200000) || (hz == 400000) || (hz == 1000000));
- I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
- I2C_InitTypeDef I2C_InitStructure;
- uint32_t tim = 0;
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
- // Disable the Fast Mode Plus capability
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); // Enable SYSCFG clock
- SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C1, DISABLE);
- SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C2, DISABLE);
+ // wait before init
+ timeout = LONG_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
- /*
- Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235)
- * Standard mode (up to 100 kHz)
- * Fast Mode (up to 400 kHz)
- * Fast Mode Plus (up to 1 MHz)
- Below values obtained with:
- - I2C clock source = 48 MHz (System Clock)
- - Analog filter delay = ON
- - Digital filter coefficient = 0
- - Rise time = 100 ns
- - Fall time = 10ns
- */
+ // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0
switch (hz) {
case 100000:
- tim = 0x10805E89; // Standard mode
- break;
- case 200000:
- tim = 0x00905E82; // Fast Mode
+ I2cHandle.Init.Timing = 0x10805E89; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
break;
case 400000:
- tim = 0x00901850; // Fast Mode
+ I2cHandle.Init.Timing = 0x00901850; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
break;
case 1000000:
- tim = 0x00700818; // Fast Mode Plus
- // Enable the Fast Mode Plus capability
- if (obj->i2c == I2C_1) {
- SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C1, ENABLE);
- }
- if (obj->i2c == I2C_2) {
- SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C2, ENABLE);
- }
+ I2cHandle.Init.Timing = 0x00700818; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
break;
default:
break;
}
// I2C configuration
- I2C_DeInit(i2c);
- I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
- I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
- I2C_InitStructure.I2C_DigitalFilter = 0x00;
- I2C_InitStructure.I2C_OwnAddress1 = 0x00;
- I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
- I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
- I2C_InitStructure.I2C_Timing = tim;
- I2C_Init(i2c, &I2C_InitStructure);
-
- I2C_Cmd(i2c, ENABLE);
+ I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;
+ I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;
+ I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED;
+ I2cHandle.Init.OwnAddress1 = 0;
+ I2cHandle.Init.OwnAddress2 = 0;
+ I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ HAL_I2C_Init(&I2cHandle);
}
-inline int i2c_start(i2c_t *obj) {
+inline int i2c_start(i2c_t *obj)
+{
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
- // Test BUSY Flag
- timeout = LONG_TIMEOUT;
- while (I2C_GetFlagStatus(i2c, I2C_ISR_BUSY) != RESET) {
- timeout--;
- if (timeout == 0) {
- return 0;
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+ // Clear Acknowledge failure flag
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
+
+ // Generate the START condition
+ i2c->CR2 |= I2C_CR2_START;
+
+ // Wait the START condition has been correctly sent
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) {
+ if ((timeout--) == 0) {
+ return 1;
}
}
- I2C_GenerateSTART(i2c, ENABLE);
-
return 0;
}
-inline int i2c_stop(i2c_t *obj) {
+inline int i2c_stop(i2c_t *obj)
+{
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
- I2C_GenerateSTOP(i2c, ENABLE);
+ // Generate the STOP condition
+ i2c->CR2 |= I2C_CR2_STOP;
return 0;
}
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
int count;
- int timeout;
int value;
- if (length == 0) return 0;
-
- // Configure slave address, nbytes, reload, end mode and start or stop generation
- I2C_TransferHandling(i2c, address, length, I2C_SoftEnd_Mode, I2C_Generate_Start_Read);
+ // Update CR2 register
+ i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)))
+ | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ);
// Read all bytes
for (count = 0; count < length; count++) {
@@ -189,100 +174,138 @@
data[count] = (char)value;
}
+ // Wait transfer complete
timeout = FLAG_TIMEOUT;
- while (!I2C_GetFlagStatus(i2c, I2C_FLAG_TC)) {
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) {
timeout--;
- if (timeout == 0) return 0;
+ if (timeout == 0) {
+ return -1;
+ }
}
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC);
- if (stop) i2c_stop(obj);
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ // Wait until STOPF flag is set
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+ // Clear STOP Flag
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF);
+ }
return length;
}
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
int timeout;
int count;
- if (length == 0) return 0;
-
- // Configure slave address, nbytes, reload, end mode and start generation
- I2C_TransferHandling(i2c, address, length, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+ // Update CR2 register
+ i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)))
+ | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE);
- // Write all bytes
for (count = 0; count < length; count++) {
i2c_byte_write(obj, data[count]);
}
+ // Wait transfer complete
timeout = FLAG_TIMEOUT;
- while (!I2C_GetFlagStatus(i2c, I2C_FLAG_TC)) {
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) {
timeout--;
- if (timeout == 0) return 0;
+ if (timeout == 0) {
+ return -1;
+ }
}
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC);
- if (stop) i2c_stop(obj);
+ // If not repeated start, send stop
+ if (stop) {
+ i2c_stop(obj);
+ // Wait until STOPF flag is set
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+ // Clear STOP Flag
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF);
+ }
return count;
}
-int i2c_byte_read(i2c_t *obj, int last) {
+int i2c_byte_read(i2c_t *obj, int last)
+{
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
- uint8_t data;
int timeout;
// Wait until the byte is received
timeout = FLAG_TIMEOUT;
- while (I2C_GetFlagStatus(i2c, I2C_ISR_RXNE) == RESET) {
- timeout--;
- if (timeout == 0) {
- return 0;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
+ if ((timeout--) == 0) {
+ return -1;
}
}
- data = I2C_ReceiveData(i2c);
-
- return (int)data;
+ return (int)i2c->RXDR;
}
-int i2c_byte_write(i2c_t *obj, int data) {
+int i2c_byte_write(i2c_t *obj, int data)
+{
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
// Wait until the previous byte is transmitted
timeout = FLAG_TIMEOUT;
- while (I2C_GetFlagStatus(i2c, I2C_ISR_TXIS) == RESET) {
- timeout--;
- if (timeout == 0) {
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) {
+ if ((timeout--) == 0) {
return 0;
}
}
- I2C_SendData(i2c, (uint8_t)data);
+ i2c->TXDR = (uint8_t)data;
return 1;
}
-void i2c_reset(i2c_t *obj) {
+void i2c_reset(i2c_t *obj)
+{
+ int timeout;
+
+ // Wait before reset
+ timeout = LONG_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
+
if (obj->i2c == I2C_1) {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ __I2C1_FORCE_RESET();
+ __I2C1_RELEASE_RESET();
}
if (obj->i2c == I2C_2) {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ __I2C2_FORCE_RESET();
+ __I2C2_RELEASE_RESET();
}
}
#if DEVICE_I2CSLAVE
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
- uint16_t tmpreg;
-
- // reset own address enable
- i2c->OAR1 &= ~ I2C_OAR1_OA1EN;
+ uint16_t tmpreg = 0;
+ // disable
+ i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN);
// Get the old register value
tmpreg = i2c->OAR1;
// Reset address bits
@@ -290,11 +313,28 @@
// Set new address
tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
// Store the new register value
- i2c->OAR1 = tmpreg | I2C_OAR1_OA1EN;
+ i2c->OAR1 = tmpreg;
+ // enable
+ i2c->OAR1 |= I2C_OAR1_OA1EN;
}
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
- // Nothing to do
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint16_t tmpreg;
+
+ // Get the old register value
+ tmpreg = i2c->OAR1;
+
+ // Enable / disable slave
+ if (enable_slave == 1) {
+ tmpreg |= I2C_OAR1_OA1EN;
+ } else {
+ tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN);
+ }
+
+ // Set new mode
+ i2c->OAR1 = tmpreg;
}
// See I2CSlave.h
@@ -303,43 +343,45 @@
#define WriteGeneral 2 // the master is writing to all slave
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
-int i2c_slave_receive(i2c_t *obj) {
- I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
- int event = NoData;
+int i2c_slave_receive(i2c_t *obj)
+{
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int retValue = NoData;
- if (I2C_GetFlagStatus(i2c, I2C_ISR_BUSY) == SET) {
- if (I2C_GetFlagStatus(i2c, I2C_ISR_ADDR) == SET) {
- // Check direction
- if (I2C_GetFlagStatus(i2c, I2C_ISR_DIR) == SET) {
- event = ReadAddressed;
- } else event = WriteAddressed;
- // Clear adress match flag to generate an acknowledge
- i2c->ICR |= I2C_ICR_ADDRCF;
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) {
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) {
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1)
+ retValue = ReadAddressed;
+ else
+ retValue = WriteAddressed;
+
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR);
}
}
- return event;
+
+ return (retValue);
}
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
- int count = 0;
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+ int size = 0;
- // Read all bytes
- for (count = 0; count < length; count++) {
- data[count] = i2c_byte_read(obj, 0);
- }
+ while (size < length) data[size++] = (char)i2c_byte_read(obj, 0);
- return count;
+ return size;
}
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
- int count = 0;
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+ int size = 0;
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
- // Write all bytes
- for (count = 0; count < length; count++) {
- i2c_byte_write(obj, data[count]);
- }
+ do {
+ i2c_byte_write(obj, data[size]);
+ size++;
+ } while (size < length);
- return count;
+ return size;
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/mbed_overrides.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "cmsis.h"
+
+// This function is called after RAM initialization and before main.
+void mbed_sdk_init()
+{
+ // Update the SystemCoreClock variable.
+ SystemCoreClockUpdate();
+}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/objects.h Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/objects.h Tue Dec 02 15:45:09 2014 +0000
@@ -43,14 +43,15 @@
IRQn_Type irq_n;
uint32_t irq_index;
uint32_t event;
+ PinName pin;
};
struct port_s {
PortName port;
uint32_t mask;
PinDirection direction;
- __IO uint16_t *reg_in;
- __IO uint16_t *reg_out;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
};
struct analogin_s {
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pinmap.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pinmap.c Tue Dec 02 15:45:09 2014 +0000
@@ -32,32 +32,50 @@
#include "PortNames.h"
#include "mbed_error.h"
+// GPIO mode look-up table
+static const uint32_t gpio_mode[13] = {
+ 0x00000000, // 0 = GPIO_MODE_INPUT
+ 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP
+ 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD
+ 0x00000002, // 3 = GPIO_MODE_AF_PP
+ 0x00000012, // 4 = GPIO_MODE_AF_OD
+ 0x00000003, // 5 = GPIO_MODE_ANALOG
+ 0x10110000, // 6 = GPIO_MODE_IT_RISING
+ 0x10210000, // 7 = GPIO_MODE_IT_FALLING
+ 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING
+ 0x10120000, // 9 = GPIO_MODE_EVT_RISING
+ 0x10220000, // 10 = GPIO_MODE_EVT_FALLING
+ 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING
+ 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL)
+};
+
// Enable GPIO clock and return GPIO base address
-uint32_t Set_GPIO_Clock(uint32_t port_idx) {
+uint32_t Set_GPIO_Clock(uint32_t port_idx)
+{
uint32_t gpio_add = 0;
switch (port_idx) {
case PortA:
gpio_add = GPIOA_BASE;
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+ __GPIOA_CLK_ENABLE();
break;
case PortB:
gpio_add = GPIOB_BASE;
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+ __GPIOB_CLK_ENABLE();
break;
case PortC:
gpio_add = GPIOC_BASE;
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+ __GPIOC_CLK_ENABLE();
break;
case PortD:
gpio_add = GPIOD_BASE;
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+ __GPIOD_CLK_ENABLE();
break;
case PortF:
gpio_add = GPIOF_BASE;
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+ __GPIOF_CLK_ENABLE();
break;
default:
- error("Port number is not correct.");
+ error("Pinmap error: wrong port number.");
break;
}
return gpio_add;
@@ -66,11 +84,11 @@
/**
* Configure pin (mode, speed, output type and pull-up/pull-down)
*/
-void pin_function(PinName pin, int data) {
+void pin_function(PinName pin, int data)
+{
MBED_ASSERT(pin != (PinName)NC);
// Get the pin informations
uint32_t mode = STM_PIN_MODE(data);
- uint32_t otype = STM_PIN_OTYPE(data);
uint32_t pupd = STM_PIN_PUPD(data);
uint32_t afnum = STM_PIN_AFNUM(data);
@@ -81,36 +99,27 @@
uint32_t gpio_add = Set_GPIO_Clock(port_index);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
- // Configure Alternate Function
- // Warning: Must be done before the GPIO is initialized
- if (afnum != 0xFF) {
- GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum);
- }
-
// Configure GPIO
GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
- GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_Level_3;
- GPIO_InitStructure.GPIO_OType = (GPIOOType_TypeDef)otype;
- GPIO_InitStructure.GPIO_PuPd = (GPIOPuPd_TypeDef)pupd;
- GPIO_Init(gpio, &GPIO_InitStructure);
+ GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index);
+ GPIO_InitStructure.Mode = gpio_mode[mode];
+ GPIO_InitStructure.Pull = pupd;
+ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
+ GPIO_InitStructure.Alternate = afnum;
+ HAL_GPIO_Init(gpio, &GPIO_InitStructure);
- // *** TODO ***
- // Disconnect JTAG-DP + SW-DP signals.
- // Warning: Need to reconnect under reset
+ // [TODO] Disconnect SWDIO and SWCLK signals ?
+ // Warning: For debugging it is necessary to reconnect under reset if this is done.
//if ((pin == PA_13) || (pin == PA_14)) {
//
//}
- //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
- //
- //}
}
/**
* Configure pin pull-up/pull-down
*/
-void pin_mode(PinName pin, PinMode mode) {
+void pin_mode(PinName pin, PinMode mode)
+{
MBED_ASSERT(pin != (PinName)NC);
uint32_t port_index = STM_PORT(pin);
uint32_t pin_index = STM_PIN(pin);
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/port_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/port_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -28,22 +28,23 @@
*******************************************************************************
*/
#include "port_api.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
#include "pinmap.h"
#include "gpio_api.h"
#include "mbed_error.h"
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
// low nibble = pin number
-PinName port_pin(PortName port, int pin_n) {
+PinName port_pin(PortName port, int pin_n)
+{
return (PinName)(pin_n + (port << 4));
}
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
uint32_t port_index = (uint32_t)port;
// Enable GPIO clock
@@ -60,21 +61,23 @@
port_dir(obj, dir);
}
-void port_dir(port_t *obj, PinDirection dir) {
+void port_dir(port_t *obj, PinDirection dir)
+{
uint32_t i;
obj->direction = dir;
for (i = 0; i < 16; i++) { // Process all pins
if (obj->mask & (1 << i)) { // If the pin is used
if (dir == PIN_OUTPUT) {
- pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
} else { // PIN_INPUT
- pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
}
}
}
-void port_mode(port_t *obj, PinMode mode) {
+void port_mode(port_t *obj, PinMode mode)
+{
uint32_t i;
for (i = 0; i < 16; i++) { // Process all pins
if (obj->mask & (1 << i)) { // If the pin is used
@@ -83,11 +86,13 @@
}
}
-void port_write(port_t *obj, int value) {
+void port_write(port_t *obj, int value)
+{
*obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
}
-int port_read(port_t *obj) {
+int port_read(port_t *obj)
+{
if (obj->direction == PIN_OUTPUT) {
return (*obj->reg_out & obj->mask);
} else { // PIN_INPUT
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pwmout_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pwmout_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -27,52 +27,32 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
-#include "mbed_assert.h"
#include "pwmout_api.h"
#if DEVICE_PWMOUT
#include "cmsis.h"
#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
-// TIM1 cannot be used because already used by the us_ticker
-static const PinMap PinMap_PWM[] = {
- {PA_4, TIM_14, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_4)}, // TIM14_CH1
- {PA_6, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_1)}, // TIM3_CH1
-// {PA_6, TIM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_5)}, // TIM16_CH1
- {PA_7, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_1)}, // TIM3_CH2
-// {PA_7, TIM_14, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_4)}, // TIM14_CH1
-// {PA_7, TIM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_5)}, // TIM17_CH1
- {PB_0, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_1)}, // TIM3_CH3
- {PB_1, TIM_14, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)}, // TIM14_CH1
-// {PB_1, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_1)}, // TIM3_CH4
- {PB_4, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_1)}, // TIM3_CH1
- {PB_5, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_1)}, // TIM3_CH2
- {PB_6, TIM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_2)}, // TIM16_CH1N
- {PB_7, TIM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_2)}, // TIM17_CH1N
- {PB_8, TIM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_2)}, // TIM16_CH1
- {PB_9, TIM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_2)}, // TIM17_CH1
- {PB_14, TIM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_1)}, // TIM15_CH1
- {PB_15, TIM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_1)}, // TIM15_CH2
-// {PB_15, TIM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_3)}, // TIM15_CH1N
- {PC_6, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)}, // TIM3_CH1
- {PC_7, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)}, // TIM3_CH2
- {PC_8, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)}, // TIM3_CH3
- {PC_9, TIM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)}, // TIM3_CH4
- {NC, NC, 0}
-};
+static TIM_HandleTypeDef TimHandle;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
// Get the peripheral name from the pin and assign it to the object
obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
- MBED_ASSERT(obj->pwm != (PWMName)NC);
+
+ if (obj->pwm == (PWMName)NC) {
+ error("PWM error: pinout mapping failed.");
+ }
// Enable TIM clock
- if (obj->pwm == TIM_3) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
- if (obj->pwm == TIM_14) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM14, ENABLE);
- if (obj->pwm == TIM_15) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM15, ENABLE);
- if (obj->pwm == TIM_16) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM16, ENABLE);
- if (obj->pwm == TIM_17) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM17, ENABLE);
+ if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
+ if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE();
+ if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE();
+ if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE();
+ if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE();
// Configure GPIO
pinmap_pinout(pin, PinMap_PWM);
@@ -84,30 +64,36 @@
pwmout_period_us(obj, 20000); // 20 ms per default
}
-void pwmout_free(pwmout_t* obj) {
- // Configure GPIOs
- pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+void pwmout_free(pwmout_t* obj)
+{
+ // Configure GPIO
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
-void pwmout_write(pwmout_t* obj, float value) {
- TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm);
- TIM_OCInitTypeDef TIM_OCInitStructure;
+void pwmout_write(pwmout_t* obj, float value)
+{
+ TIM_OC_InitTypeDef sConfig;
+ int channel = 0;
+ int complementary_channel = 0;
+
+ TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
- if (value < 0.0) {
+ if (value < (float)0.0) {
value = 0.0;
- } else if (value > 1.0) {
+ } else if (value > (float)1.0) {
value = 1.0;
}
obj->pulse = (uint32_t)((float)obj->period * value);
// Configure channels
- TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
- TIM_OCInitStructure.TIM_Pulse = obj->pulse;
- TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCPolarity_Low;
- TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+ sConfig.OCMode = TIM_OCMODE_PWM1;
+ sConfig.Pulse = obj->pulse;
+ sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
+ sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ sConfig.OCFastMode = TIM_OCFAST_DISABLE;
+ sConfig.OCIdleState = TIM_OCIDLESTATE_RESET;
+ sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
switch (obj->pin) {
// Channels 1
@@ -119,95 +105,100 @@
case PB_9:
case PB_14:
case PC_6:
- TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
- TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable);
- TIM_OC1Init(tim, &TIM_OCInitStructure);
+ channel = TIM_CHANNEL_1;
break;
// Channels 1N
case PB_6:
case PB_7:
- TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
- TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable);
- TIM_OC1Init(tim, &TIM_OCInitStructure);
+ channel = TIM_CHANNEL_1;
+ complementary_channel = 1;
break;
// Channels 2
case PA_7:
case PB_5:
+ case PB_15:
case PC_7:
- TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
- TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable);
- TIM_OC2Init(tim, &TIM_OCInitStructure);
+ channel = TIM_CHANNEL_2;
break;
// Channels 3
case PB_0:
case PC_8:
- TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
- TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable);
- TIM_OC3Init(tim, &TIM_OCInitStructure);
+ channel = TIM_CHANNEL_3;
break;
// Channels 4
-// case PB_1:
case PC_9:
- TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
- TIM_OC4PreloadConfig(tim, TIM_OCPreload_Enable);
- TIM_OC4Init(tim, &TIM_OCInitStructure);
+ channel = TIM_CHANNEL_4;
break;
default:
return;
}
- TIM_CtrlPWMOutputs(tim, ENABLE);
+ HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel);
+ if (complementary_channel) {
+ HAL_TIMEx_PWMN_Start(&TimHandle, channel);
+ } else {
+ HAL_TIM_PWM_Start(&TimHandle, channel);
+ }
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
float value = 0;
if (obj->period > 0) {
value = (float)(obj->pulse) / (float)(obj->period);
}
- return ((value > 1.0) ? (1.0) : (value));
+ return ((value > (float)1.0) ? (float)(1.0) : (value));
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
-void pwmout_period_us(pwmout_t* obj, int us) {
- TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm);
- TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+ TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
float dc = pwmout_read(obj);
- TIM_Cmd(tim, DISABLE);
+ __HAL_TIM_DISABLE(&TimHandle);
- obj->period = us;
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
- TIM_TimeBaseStructure.TIM_Period = obj->period - 1;
- TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
- TIM_TimeBaseStructure.TIM_ClockDivision = 0;
- TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure);
+ TimHandle.Init.Period = us - 1;
+ TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TimHandle.Init.ClockDivision = 0;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ HAL_TIM_PWM_Init(&TimHandle);
// Set duty cycle again
pwmout_write(obj, dc);
- TIM_ARRPreloadConfig(tim, ENABLE);
+ // Save for future use
+ obj->period = us;
- TIM_Cmd(tim, ENABLE);
+ __HAL_TIM_ENABLE(&TimHandle);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
float value = (float)us / (float)obj->period;
pwmout_write(obj, value);
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/rtc_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/rtc_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -31,79 +31,98 @@
#if DEVICE_RTC
-#include "wait_api.h"
-
-#define LSE_STARTUP_TIMEOUT ((uint16_t)500) // delay in ms
+#include "mbed_error.h"
static int rtc_inited = 0;
-void rtc_init(void) {
- uint32_t StartUpCounter = 0;
- uint32_t LSEStatus = 0;
+static RTC_HandleTypeDef RtcHandle;
+
+void rtc_init(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
uint32_t rtc_freq = 0;
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); // Enable PWR clock
+ if (rtc_inited) return;
+ rtc_inited = 1;
- PWR_BackupAccessCmd(ENABLE); // Enable access to Backup domain
+ RtcHandle.Instance = RTC;
- // Reset back up registers
- RCC_BackupResetCmd(ENABLE);
- RCC_BackupResetCmd(DISABLE);
-
- // Enable LSE clock
- RCC_LSEConfig(RCC_LSE_ON);
+ // Enable Power clock
+ __PWR_CLK_ENABLE();
+
+ // Enable access to Backup domain
+ HAL_PWR_EnableBkUpAccess();
+
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
- // Wait till LSE is ready
- do {
- LSEStatus = RCC_GetFlagStatus(RCC_FLAG_LSERDY);
- wait_ms(1);
- StartUpCounter++;
- } while ((LSEStatus == 0) && (StartUpCounter <= LSE_STARTUP_TIMEOUT));
-
- if (StartUpCounter > LSE_STARTUP_TIMEOUT) {
- // The LSE has not started, use LSI instead.
- // The RTC Clock may vary due to LSI frequency dispersion.
- RCC_LSEConfig(RCC_LSE_OFF);
- RCC_LSICmd(ENABLE); // Enable LSI
- while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} // Wait until ready
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select the RTC Clock Source
- rtc_freq = 40000; // [TODO] To be measured precisely using a timer input capture
+ // Enable LSE Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+ // Connect LSE to RTC
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+ rtc_freq = LSE_VALUE;
} else {
- // The LSE has correctly started
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select the RTC Clock Source
- rtc_freq = LSE_VALUE;
+ // Enable LSI clock
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("RTC error: LSI clock initialization failed.");
+ }
+ // Connect LSI to RTC
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+ // This value is LSI typical value. To be measured precisely using a timer input capture for example.
+ rtc_freq = LSI_VALUE;
}
-
- RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock
-
- RTC_WaitForSynchro(); // Wait for RTC registers synchronization
- RTC_InitTypeDef RTC_InitStructure;
- RTC_InitStructure.RTC_AsynchPrediv = 127;
- RTC_InitStructure.RTC_SynchPrediv = (rtc_freq / 128) - 1;
- RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24;
- RTC_Init(&RTC_InitStructure);
+ // Enable RTC
+ __HAL_RCC_RTC_ENABLE();
- PWR_BackupAccessCmd(DISABLE); // Disable access to Backup domain
+ RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
+ RtcHandle.Init.AsynchPrediv = 127;
+ RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1;
+ RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
- rtc_inited = 1;
+ if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+ error("RTC error: RTC initialization failed.");
+ }
}
-void rtc_free(void) {
- // Reset RTC
- PWR_BackupAccessCmd(ENABLE); // Enable access to Backup Domain
- RTC_DeInit();
- RCC_BackupResetCmd(ENABLE);
- RCC_BackupResetCmd(DISABLE);
- // Disable RTC, LSE and LSI clocks
- RCC_RTCCLKCmd(DISABLE);
- RCC_LSEConfig(RCC_LSE_OFF);
- RCC_LSICmd(DISABLE);
+void rtc_free(void)
+{
+ // Enable Power clock
+ __PWR_CLK_ENABLE();
+
+ // Enable access to Backup domain
+ HAL_PWR_EnableBkUpAccess();
+
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ // Disable access to Backup domain
+ HAL_PWR_DisableBkUpAccess();
+
+ // Disable LSI and LSE clocks
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
rtc_inited = 0;
}
-int rtc_isenabled(void) {
+int rtc_isenabled(void)
+{
return rtc_inited;
}
@@ -124,23 +143,27 @@
tm_yday days since January 1 0-365
tm_isdst Daylight Saving Time flag
*/
-time_t rtc_read(void) {
+time_t rtc_read(void)
+{
RTC_DateTypeDef dateStruct;
RTC_TimeTypeDef timeStruct;
struct tm timeinfo;
+ RtcHandle.Instance = RTC;
+
// Read actual date and time
- RTC_GetTime(RTC_Format_BIN, &timeStruct);
- RTC_GetDate(RTC_Format_BIN, &dateStruct);
+ // Warning: the time must be read first!
+ HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+ HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
// Setup a tm structure based on the RTC
- timeinfo.tm_wday = dateStruct.RTC_WeekDay;
- timeinfo.tm_mon = dateStruct.RTC_Month - 1;
- timeinfo.tm_mday = dateStruct.RTC_Date;
- timeinfo.tm_year = dateStruct.RTC_Year + 100;
- timeinfo.tm_hour = timeStruct.RTC_Hours;
- timeinfo.tm_min = timeStruct.RTC_Minutes;
- timeinfo.tm_sec = timeStruct.RTC_Seconds;
+ timeinfo.tm_wday = dateStruct.WeekDay;
+ timeinfo.tm_mon = dateStruct.Month - 1;
+ timeinfo.tm_mday = dateStruct.Date;
+ timeinfo.tm_year = dateStruct.Year + 100;
+ timeinfo.tm_hour = timeStruct.Hours;
+ timeinfo.tm_min = timeStruct.Minutes;
+ timeinfo.tm_sec = timeStruct.Seconds;
// Convert to timestamp
time_t t = mktime(&timeinfo);
@@ -148,28 +171,31 @@
return t;
}
-void rtc_write(time_t t) {
+void rtc_write(time_t t)
+{
RTC_DateTypeDef dateStruct;
RTC_TimeTypeDef timeStruct;
+ RtcHandle.Instance = RTC;
+
// Convert the time into a tm
struct tm *timeinfo = localtime(&t);
// Fill RTC structures
- dateStruct.RTC_WeekDay = timeinfo->tm_wday;
- dateStruct.RTC_Month = timeinfo->tm_mon + 1;
- dateStruct.RTC_Date = timeinfo->tm_mday;
- dateStruct.RTC_Year = timeinfo->tm_year - 100;
- timeStruct.RTC_Hours = timeinfo->tm_hour;
- timeStruct.RTC_Minutes = timeinfo->tm_min;
- timeStruct.RTC_Seconds = timeinfo->tm_sec;
- timeStruct.RTC_H12 = RTC_HourFormat_24;
+ dateStruct.WeekDay = timeinfo->tm_wday;
+ dateStruct.Month = timeinfo->tm_mon + 1;
+ dateStruct.Date = timeinfo->tm_mday;
+ dateStruct.Year = timeinfo->tm_year - 100;
+ timeStruct.Hours = timeinfo->tm_hour;
+ timeStruct.Minutes = timeinfo->tm_min;
+ timeStruct.Seconds = timeinfo->tm_sec;
+ timeStruct.TimeFormat = RTC_HOURFORMAT12_PM;
+ timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+ timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
// Change the RTC current date/time
- PWR_BackupAccessCmd(ENABLE); // Enable access to RTC
- RTC_SetDate(RTC_Format_BIN, &dateStruct);
- RTC_SetTime(RTC_Format_BIN, &timeStruct);
- PWR_BackupAccessCmd(DISABLE); // Disable access to RTC
+ HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+ HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
}
#endif
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/serial_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/serial_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -35,49 +35,46 @@
#include "cmsis.h"
#include "pinmap.h"
#include <string.h>
-
-static const PinMap PinMap_UART_TX[] = {
- {PA_2, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)},
- {PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)},
- {PB_6, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_0)},
- {NC, NC, 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
- {PA_3, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)},
- {PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)},
- {PA_15, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)},
- {PB_7, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_0)},
- {NC, NC, 0}
-};
+#include "PeripheralPins.h"
#define UART_NUM (2)
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uint32_t serial_irq_ids[UART_NUM] = {0, 0};
static uart_irq_handler irq_handler;
+UART_HandleTypeDef UartHandle;
+
int stdio_uart_inited = 0;
serial_t stdio_uart;
-static void init_usart(serial_t *obj) {
- USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
- USART_InitTypeDef USART_InitStructure;
-
- USART_Cmd(usart, DISABLE);
+static void init_uart(serial_t *obj)
+{
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+ UartHandle.Init.BaudRate = obj->baudrate;
+ UartHandle.Init.WordLength = obj->databits;
+ UartHandle.Init.StopBits = obj->stopbits;
+ UartHandle.Init.Parity = obj->parity;
+ UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- USART_InitStructure.USART_BaudRate = obj->baudrate;
- USART_InitStructure.USART_WordLength = obj->databits;
- USART_InitStructure.USART_StopBits = obj->stopbits;
- USART_InitStructure.USART_Parity = obj->parity;
- USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
- USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_Init(usart, &USART_InitStructure);
+ if (obj->pin_rx == NC) {
+ UartHandle.Init.Mode = UART_MODE_TX;
+ } else if (obj->pin_tx == NC) {
+ UartHandle.Init.Mode = UART_MODE_RX;
+ } else {
+ UartHandle.Init.Mode = UART_MODE_TX_RX;
+ }
+
+ // Disable the reception overrun detection
+ UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT;
+ UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
- USART_Cmd(usart, ENABLE);
+ HAL_UART_Init(&UartHandle);
}
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
// Determine the UART to use (UART_1, UART_2, ...)
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
@@ -88,11 +85,11 @@
// Enable USART clock
if (obj->uart == UART_1) {
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+ __USART1_CLK_ENABLE();
obj->index = 0;
}
if (obj->uart == UART_2) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+ __USART2_CLK_ENABLE();
obj->index = 1;
}
@@ -108,112 +105,121 @@
// Configure UART
obj->baudrate = 9600;
- obj->databits = USART_WordLength_8b;
- obj->stopbits = USART_StopBits_1;
- obj->parity = USART_Parity_No;
+ obj->databits = UART_WORDLENGTH_8B;
+ obj->stopbits = UART_STOPBITS_1;
+ obj->parity = UART_PARITY_NONE;
obj->pin_tx = tx;
obj->pin_rx = rx;
- init_usart(obj);
+ init_uart(obj);
// For stdio management
if (obj->uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
-
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
// Reset UART and disable clock
if (obj->uart == UART_1) {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, DISABLE);
+ __USART1_FORCE_RESET();
+ __USART1_RELEASE_RESET();
+ __USART1_CLK_DISABLE();
}
if (obj->uart == UART_2) {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, DISABLE);
+ __USART2_FORCE_RESET();
+ __USART2_RELEASE_RESET();
+ __USART2_CLK_DISABLE();
}
// Configure GPIOs
- pin_function(obj->pin_tx, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
- pin_function(obj->pin_rx, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+ pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
obj->baudrate = baudrate;
- init_usart(obj);
+ init_uart(obj);
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- if (data_bits == 8) {
- obj->databits = USART_WordLength_8b;
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ if (data_bits == 9) {
+ obj->databits = UART_WORDLENGTH_9B;
} else {
- obj->databits = USART_WordLength_9b;
+ obj->databits = UART_WORDLENGTH_8B;
}
switch (parity) {
case ParityOdd:
case ParityForced0:
- obj->parity = USART_Parity_Odd;
+ obj->parity = UART_PARITY_ODD;
break;
case ParityEven:
case ParityForced1:
- obj->parity = USART_Parity_Even;
+ obj->parity = UART_PARITY_EVEN;
break;
default: // ParityNone
- obj->parity = USART_Parity_No;
+ obj->parity = UART_PARITY_NONE;
break;
}
if (stop_bits == 2) {
- obj->stopbits = USART_StopBits_2;
+ obj->stopbits = UART_STOPBITS_2;
} else {
- obj->stopbits = USART_StopBits_1;
+ obj->stopbits = UART_STOPBITS_1;
}
- init_usart(obj);
+ init_uart(obj);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-// not api
-static void uart_irq(USART_TypeDef* usart, int id) {
+static void uart_irq(UARTName name, int id)
+{
+ UartHandle.Instance = (USART_TypeDef *)name;
if (serial_irq_ids[id] != 0) {
- if (USART_GetITStatus(usart, USART_IT_TC) != RESET) {
+ if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
irq_handler(serial_irq_ids[id], TxIrq);
- USART_ClearITPendingBit(usart, USART_IT_TC);
+ __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC);
}
- if (USART_GetITStatus(usart, USART_IT_RXNE) != RESET) {
+ if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
irq_handler(serial_irq_ids[id], RxIrq);
- USART_ClearITPendingBit(usart, USART_IT_RXNE);
+ volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit
}
}
}
-static void uart1_irq(void) {
- uart_irq((USART_TypeDef*)UART_1, 0);
-}
-static void uart2_irq(void) {
- uart_irq((USART_TypeDef*)UART_2, 1);
+static void uart1_irq(void)
+{
+ uart_irq(UART_1, 0);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+static void uart2_irq(void)
+{
+ uart_irq(UART_2, 1);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
- USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
if (obj->uart == UART_1) {
irq_n = USART1_IRQn;
@@ -228,9 +234,9 @@
if (enable) {
if (irq == RxIrq) {
- USART_ITConfig(usart, USART_IT_RXNE, ENABLE);
+ __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
} else { // TxIrq
- USART_ITConfig(usart, USART_IT_TC, ENABLE);
+ __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
}
NVIC_SetVector(irq_n, vector);
@@ -241,13 +247,13 @@
int all_disabled = 0;
if (irq == RxIrq) {
- USART_ITConfig(usart, USART_IT_RXNE, DISABLE);
+ __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
// Check if TxIrq is disabled too
- if ((usart->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
+ if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1;
} else { // TxIrq
- USART_ITConfig(usart, USART_IT_TXE, DISABLE);
+ __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC);
// Check if RxIrq is disabled too
- if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+ if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
}
if (all_disabled) NVIC_DisableIRQ(irq_n);
@@ -259,48 +265,58 @@
* READ/WRITE
******************************************************************************/
-int serial_getc(serial_t *obj) {
- USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+int serial_getc(serial_t *obj)
+{
+ USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
while (!serial_readable(obj));
- return (int)(USART_ReceiveData(usart));
+ return (int)(uart->RDR & (uint16_t)0xFF);
}
-void serial_putc(serial_t *obj, int c) {
- USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+void serial_putc(serial_t *obj, int c)
+{
+ USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
while (!serial_writable(obj));
- USART_SendData(usart, (uint16_t)c);
+ uart->TDR = (uint32_t)(c & (uint16_t)0xFF);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
int status;
- USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
// Check if data is received
- status = ((USART_GetFlagStatus(usart, USART_FLAG_RXNE) != RESET) ? 1 : 0);
+ status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
return status;
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
int status;
- USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
// Check if data is transmitted
- status = ((USART_GetFlagStatus(usart, USART_FLAG_TXE) != RESET) ? 1 : 0);
+ status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
return status;
}
-void serial_clear(serial_t *obj) {
- USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
- USART_ClearFlag(usart, USART_FLAG_TXE);
- USART_ClearFlag(usart, USART_FLAG_RXNE);
+void serial_clear(serial_t *obj)
+{
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+ __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC);
+ __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST);
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
+ // [TODO]
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
+ // [TODO]
}
#endif
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/sleep.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/sleep.c Tue Dec 02 15:45:09 2014 +0000
@@ -33,28 +33,27 @@
#include "cmsis.h"
-void sleep(void) {
- // Disable us_ticker update interrupt
- TIM_ITConfig(TIM1, TIM_IT_Update, DISABLE);
-
- SCB->SCR = 0; // Normal sleep mode for ARM core
- __WFI();
-
- // Re-enable us_ticker update interrupt
- TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
+void sleep(void)
+{
+ // Stop HAL systick
+ HAL_SuspendTick();
+ // Request to enter SLEEP mode
+ HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+ // Restart HAL systick
+ HAL_ResumeTick();
}
-// MCU STOP mode
-// Wake-up with external interrupt
-void deepsleep(void) {
- // Enable PWR clock
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
-
+void deepsleep(void)
+{
// Request to enter STOP mode with regulator in low power mode
- PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
+ HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+
+ HAL_InitTick(TICK_INT_PRIORITY);
// After wake-up from STOP reconfigure the PLL
SetSysClock();
+
+ HAL_InitTick(TICK_INT_PRIORITY);
}
#endif
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/spi_api.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/spi_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -35,59 +35,35 @@
#include <math.h>
#include "cmsis.h"
#include "pinmap.h"
+#include "PeripheralPins.h"
-static const PinMap PinMap_SPI_MOSI[] = {
- {PA_7, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {PB_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {PB_15, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {NC, NC, 0}
-};
+static SPI_HandleTypeDef SpiHandle;
-static const PinMap PinMap_SPI_MISO[] = {
- {PA_6, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {PB_4, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {PB_14, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {NC, NC, 0}
-};
+static void init_spi(spi_t *obj)
+{
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-static const PinMap PinMap_SPI_SCLK[] = {
- {PA_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {PB_3, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {PB_13, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_0)},
- {NC, NC, 0}
-};
+ __HAL_SPI_DISABLE(&SpiHandle);
-// Only used in Slave mode
-static const PinMap PinMap_SPI_SSEL[] = {
- {PA_4, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0)},
- {PA_15, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0)},
- {PB_12, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0)},
- {NC, NC, 0}
-};
-
-static void init_spi(spi_t *obj) {
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
- SPI_InitTypeDef SPI_InitStructure;
-
- SPI_Cmd(spi, DISABLE);
+ SpiHandle.Init.Mode = obj->mode;
+ SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
+ SpiHandle.Init.Direction = SPI_DIRECTION_2LINES;
+ SpiHandle.Init.CLKPhase = obj->cpha;
+ SpiHandle.Init.CLKPolarity = obj->cpol;
+ SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
+ SpiHandle.Init.CRCPolynomial = 7;
+ SpiHandle.Init.DataSize = obj->bits;
+ SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
+ SpiHandle.Init.NSS = obj->nss;
+ SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
- SPI_InitStructure.SPI_Mode = obj->mode;
- SPI_InitStructure.SPI_NSS = obj->nss;
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- SPI_InitStructure.SPI_DataSize = obj->bits;
- SPI_InitStructure.SPI_CPOL = obj->cpol;
- SPI_InitStructure.SPI_CPHA = obj->cpha;
- SPI_InitStructure.SPI_BaudRatePrescaler = obj->br_presc;
- SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
- SPI_InitStructure.SPI_CRCPolynomial = 7;
- SPI_Init(spi, &SPI_InitStructure);
+ HAL_SPI_Init(&SpiHandle);
- SPI_RxFIFOThresholdConfig(spi, SPI_RxFIFOThreshold_QF);
-
- SPI_Cmd(spi, ENABLE);
+ __HAL_SPI_ENABLE(&SpiHandle);
}
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// Determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -102,10 +78,10 @@
// Enable SPI clock
if (obj->spi == SPI_1) {
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
+ __SPI1_CLK_ENABLE();
}
if (obj->spi == SPI_2) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+ __SPI2_CLK_ENABLE();
}
// Configure the SPI pins
@@ -114,181 +90,207 @@
pinmap_pinout(sclk, PinMap_SPI_SCLK);
// Save new values
- obj->bits = SPI_DataSize_8b;
- obj->cpol = SPI_CPOL_Low;
- obj->cpha = SPI_CPHA_1Edge;
- obj->br_presc = SPI_BaudRatePrescaler_8; // 1 MHz
+ obj->bits = SPI_DATASIZE_8BIT;
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_1EDGE;
+ obj->br_presc = SPI_BAUDRATEPRESCALER_256;
obj->pin_miso = miso;
obj->pin_mosi = mosi;
obj->pin_sclk = sclk;
obj->pin_ssel = ssel;
- if (ssel == NC) { // Master
- obj->mode = SPI_Mode_Master;
- obj->nss = SPI_NSS_Soft;
+ if (ssel == NC) { // SW NSS Master mode
+ obj->mode = SPI_MODE_MASTER;
+ obj->nss = SPI_NSS_SOFT;
} else { // Slave
pinmap_pinout(ssel, PinMap_SPI_SSEL);
- obj->mode = SPI_Mode_Slave;
- obj->nss = SPI_NSS_Hard;
+ obj->mode = SPI_MODE_SLAVE;
+ obj->nss = SPI_NSS_HARD_INPUT;
}
init_spi(obj);
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
// Reset SPI and disable clock
if (obj->spi == SPI_1) {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, DISABLE);
+ __SPI1_FORCE_RESET();
+ __SPI1_RELEASE_RESET();
+ __SPI1_CLK_DISABLE();
}
if (obj->spi == SPI_2) {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, DISABLE);
+ __SPI2_FORCE_RESET();
+ __SPI2_RELEASE_RESET();
+ __SPI2_CLK_DISABLE();
}
// Configure GPIOs
- pin_function(obj->pin_miso, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
- pin_function(obj->pin_mosi, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
- pin_function(obj->pin_sclk, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
- pin_function(obj->pin_ssel, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+ pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
// Save new values
if (bits == 16) {
- obj->bits = SPI_DataSize_16b;
+ obj->bits = SPI_DATASIZE_16BIT;
} else {
- obj->bits = SPI_DataSize_8b;
+ obj->bits = SPI_DATASIZE_8BIT;
}
switch (mode) {
case 0:
- obj->cpol = SPI_CPOL_Low;
- obj->cpha = SPI_CPHA_1Edge;
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_1EDGE;
break;
case 1:
- obj->cpol = SPI_CPOL_Low;
- obj->cpha = SPI_CPHA_2Edge;
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_2EDGE;
break;
case 2:
- obj->cpol = SPI_CPOL_High;
- obj->cpha = SPI_CPHA_1Edge;
+ obj->cpol = SPI_POLARITY_HIGH;
+ obj->cpha = SPI_PHASE_1EDGE;
break;
default:
- obj->cpol = SPI_CPOL_High;
- obj->cpha = SPI_CPHA_2Edge;
+ obj->cpol = SPI_POLARITY_HIGH;
+ obj->cpha = SPI_PHASE_2EDGE;
break;
}
if (slave == 0) {
- obj->mode = SPI_Mode_Master;
- obj->nss = SPI_NSS_Soft;
+ obj->mode = SPI_MODE_MASTER;
+ obj->nss = SPI_NSS_SOFT;
} else {
- obj->mode = SPI_Mode_Slave;
- obj->nss = SPI_NSS_Hard;
+ obj->mode = SPI_MODE_SLAVE;
+ obj->nss = SPI_NSS_HARD_INPUT;
}
init_spi(obj);
}
-void spi_frequency(spi_t *obj, int hz) {
- // Note: The frequencies are obtained with SPI clock = 48 MHz (APB1 & APB2 clocks)
- if (hz < 300000) {
- obj->br_presc = SPI_BaudRatePrescaler_256; // 188 kHz
- } else if ((hz >= 300000) && (hz < 700000)) {
- obj->br_presc = SPI_BaudRatePrescaler_128; // 375 kHz
- } else if ((hz >= 700000) && (hz < 1000000)) {
- obj->br_presc = SPI_BaudRatePrescaler_64; // 750 kHz
+void spi_frequency(spi_t *obj, int hz)
+{
+ // Note: The frequencies are obtained with SPI clock = 48 MHz (APB clock)
+ if (hz < 375000) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 188 kHz
+ } else if ((hz >= 375000) && (hz < 750000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 375 kHz
+ } else if ((hz >= 750000) && (hz < 1000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 750 kHz
} else if ((hz >= 1000000) && (hz < 3000000)) {
- obj->br_presc = SPI_BaudRatePrescaler_32; // 1.5 MHz
+ obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.5 MHz
} else if ((hz >= 3000000) && (hz < 6000000)) {
- obj->br_presc = SPI_BaudRatePrescaler_16; // 3 MHz
+ obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 3 MHz
} else if ((hz >= 6000000) && (hz < 12000000)) {
- obj->br_presc = SPI_BaudRatePrescaler_8; // 6 MHz
+ obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 6 MHz
} else if ((hz >= 12000000) && (hz < 24000000)) {
- obj->br_presc = SPI_BaudRatePrescaler_4; // 12 MHz
+ obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 12 MHz
} else { // >= 24000000
- obj->br_presc = SPI_BaudRatePrescaler_2; // 24 MHz
+ obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 24 MHz
}
init_spi(obj);
}
-static inline int ssp_readable(spi_t *obj) {
+static inline int ssp_readable(spi_t *obj)
+{
int status;
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
// Check if data is received
- status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_RXNE) != RESET) ? 1 : 0);
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
return status;
}
-static inline int ssp_writeable(spi_t *obj) {
+static inline int ssp_writeable(spi_t *obj)
+{
int status;
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
// Check if data is transmitted
- status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_TXE) != RESET) ? 1 : 0);
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
return status;
}
-static inline void ssp_write(spi_t *obj, int value) {
+static inline void ssp_write(spi_t *obj, int value)
+{
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
- if (obj->bits == SPI_DataSize_8b) {
- SPI_SendData8(spi, (uint8_t)value);
- } else { // 16-bit
- SPI_I2S_SendData16(spi, (uint16_t)value);
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ *p_spi_dr = (uint8_t)value;
+ } else { // SPI_DATASIZE_16BIT
+ spi->DR = (uint16_t)value;
}
}
-static inline int ssp_read(spi_t *obj) {
+static inline int ssp_read(spi_t *obj)
+{
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_readable(obj));
- if (obj->bits == SPI_DataSize_8b) {
- return (int)SPI_ReceiveData8(spi);
- } else { // 16-bit
- return (int)SPI_I2S_ReceiveData16(spi);
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ return (int)(*p_spi_dr);
+ } else {
+ return (int)spi->DR;
}
}
-static inline int ssp_busy(spi_t *obj) {
+static inline int ssp_busy(spi_t *obj)
+{
int status;
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
- status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_BSY) != RESET) ? 1 : 0);
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
return status;
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
ssp_write(obj, value);
return ssp_read(obj);
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
};
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
- if (obj->bits == SPI_DataSize_8b) {
- return (int)SPI_ReceiveData8(spi);
- } else { // 16-bit
- return (int)SPI_I2S_ReceiveData16(spi);
+ while (!ssp_readable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ return (int)(*p_spi_dr);
+ } else {
+ return (int)spi->DR;
}
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
- if (obj->bits == SPI_DataSize_8b) {
- SPI_SendData8(spi, (uint8_t)value);
- } else { // 16-bit
- SPI_I2S_SendData16(spi, (uint16_t)value);
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ *p_spi_dr = (uint8_t)value;
+ } else { // SPI_DATASIZE_16BIT
+ spi->DR = (uint16_t)value;
}
}
-int spi_busy(spi_t *obj) {
+int spi_busy(spi_t *obj)
+{
return ssp_busy(obj);
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/us_ticker.c Tue Dec 02 15:15:06 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/us_ticker.c Tue Dec 02 15:45:09 2014 +0000
@@ -33,35 +33,47 @@
#define TIM_MST TIM1
#define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn
#define TIM_MST_OC_IRQ TIM1_CC_IRQn
-#define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE)
+#define TIM_MST_RCC __TIM1_CLK_ENABLE()
+
+static TIM_HandleTypeDef TimMasterHandle;
+
static int us_ticker_inited = 0;
static volatile uint32_t SlaveCounter = 0;
static volatile uint32_t oc_int_part = 0;
static volatile uint16_t oc_rem_part = 0;
-void set_compare(uint16_t count) {
+void set_compare(uint16_t count)
+{
+ TimMasterHandle.Instance = TIM_MST;
+
// Set new output compare value
- TIM_SetCompare1(TIM_MST, count);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count);
// Enable IT
- TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
// Used to increment the slave counter
-static void tim_update_irq_handler(void) {
- if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) {
- TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update);
+static void tim_update_irq_handler(void)
+{
+ TimMasterHandle.Instance = TIM_MST;
+
+ // Clear Update interrupt flag
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE);
SlaveCounter++;
}
}
// Used by interrupt system
-static void tim_oc_irq_handler(void) {
+static void tim_oc_irq_handler(void)
+{
uint16_t cval = TIM_MST->CNT;
+ TimMasterHandle.Instance = TIM_MST;
- // Clear interrupt flag
- if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) {
- TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
+ // Clear CC1 interrupt flag
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
}
if (oc_rem_part > 0) {
@@ -78,25 +90,25 @@
}
}
-void us_ticker_init(void) {
- TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+void us_ticker_init(void)
+{
if (us_ticker_inited) return;
us_ticker_inited = 1;
- // Enable Timer clock
+ // Enable timer clock
TIM_MST_RCC;
// Configure time base
- TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
- TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
- TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 �s tick
- TIM_TimeBaseStructure.TIM_ClockDivision = 0;
- TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure);
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 �s tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ HAL_TIM_Base_Init(&TimMasterHandle);
// Configure interrupts
- TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE);
// Update interrupt used for 32-bit counter
NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler);
@@ -107,10 +119,11 @@
NVIC_EnableIRQ(TIM_MST_OC_IRQ);
// Enable timer
- TIM_Cmd(TIM_MST, ENABLE);
+ HAL_TIM_Base_Start(&TimMasterHandle);
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
uint32_t counter, counter2;
if (!us_ticker_inited) us_ticker_init();
// A situation might appear when Master overflows right after Slave is read and before the
@@ -131,7 +144,8 @@
return counter2;
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)((uint32_t)timestamp - us_ticker_read());
uint16_t cval = TIM_MST->CNT;
@@ -150,12 +164,16 @@
}
}
-void us_ticker_disable_interrupt(void) {
- TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE);
+void us_ticker_disable_interrupt(void)
+{
+ TimMasterHandle.Instance = TIM_MST;
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
-void us_ticker_clear_interrupt(void) {
- if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) {
- TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
+void us_ticker_clear_interrupt(void)
+{
+ TimMasterHandle.Instance = TIM_MST;
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
}
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE,
+ ADC_4 = (int)ADC4_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_3
+#define STDIO_UART UART_2
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_15 = (int)TIM15_BASE,
+ PWM_16 = (int)TIM16_BASE,
+ PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,263 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - ARDUINO A0
+ {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - ARDUINO A1
+ {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3
+ {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4
+ {PA_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN1 - ARDUINO A2
+ {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN2 - Warning: LED1 is connected on this pin
+ {PA_6, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN3
+ {PA_7, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN4
+
+ {PB_0, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN12 - ARDUINO A3
+ {PB_1, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN1
+ {PB_2, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN12
+ {PB_11, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN14
+ {PB_12, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN3
+ {PB_13, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5
+ {PB_14, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN4
+ {PB_15, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN5
+
+ {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN6 - ARDUINO A5
+ {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN7 - ARDUINO A4
+ {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN8
+ {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN9
+ {PC_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN5
+ {PC_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN11
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT2 - Warning: LED1 is connected on this pin
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PA_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_5, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)},
+ {PA_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM2 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+// {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1
+// {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2
+ {PA_1, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1N
+ {PA_2, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1
+ {PA_3, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH2
+ {PA_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2
+// {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - Warning: LED1 is connected on this pin
+ {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1
+// {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1
+ {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 - ARDUINO
+// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2
+// {PA_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1N
+// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N - ARDUINO
+ {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2
+// {PA_9, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2)}, // TIM2_CH3
+ {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3
+// {PA_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2)}, // TIM2_CH4
+ {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1)}, // TIM1_CH4
+// {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N
+// {PA_11, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4)}, // TIM4_CH1
+ {PA_12, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1
+// {PA_12, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N
+// {PA_12, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4)}, // TIM4_CH2
+ {PA_13, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N
+// {PA_13, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4)}, // TIM4_CH3
+ {PA_14, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8)}, // TIM8_CH2
+// {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1
+ {PA_15, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8)}, // TIM8_CH1
+
+// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3
+// {PB_0, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2N
+ {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N
+// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4
+// {PB_1, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3N
+ {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N
+// {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO --> USED BY TIMER
+ {PB_3, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1N - ARDUINO
+ {PB_4, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 - ARDUINO
+// {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1
+// {PB_4, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2N
+// {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2
+// {PB_5, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3N
+ {PB_5, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17)},// TIM17_CH1
+ {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N - ARDUINO
+// {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1
+// {PB_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8)}, // TIM8_CH1
+ {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1N
+// {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2
+// {PB_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3)}, // TIM3_CH4
+ {PB_8, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1
+// {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3
+// {PB_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8)}, // TIM8_CH2
+ {PB_9, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1
+// {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4
+// {PB_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8)}, // TIM8_CH3
+// {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO --> USED BY TIMER
+// {PB_11, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N
+ {PB_14, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH1
+// {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N
+ {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH2
+// {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15)}, // TIM15_CH1N
+// {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1)}, // TIM1_CH3N
+
+ {PC_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1
+ {PC_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2
+ {PC_2, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3
+ {PC_3, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH4
+ {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1
+// {PC_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2
+// {PC_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3
+// {PC_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4
+// {PC_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH4
+ {PC_10, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1N
+ {PC_11, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2N
+ {PC_12, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3N
+ {PC_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1)}, // TIM1_CH1N
+
+ {PF_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_5, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Warning: LED1 is connected on this pin
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PF_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PF_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.h Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,66 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +//*** ADC *** + +extern const PinMap PinMap_ADC[]; + +//*** DAC *** + +extern const PinMap PinMap_DAC[]; + +//*** I2C *** + +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +//*** PWM *** + +extern const PinMap PinMap_PWM[]; + +//*** SERIAL *** + +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +//*** SPI *** + +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PinNames.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,183 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// See stm32f3xx_hal_gpio.h and stm32f3xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
+#define STM_MODE_INPUT (0)
+#define STM_MODE_OUTPUT_PP (1)
+#define STM_MODE_OUTPUT_OD (2)
+#define STM_MODE_AF_PP (3)
+#define STM_MODE_AF_OD (4)
+#define STM_MODE_ANALOG (5)
+#define STM_MODE_IT_RISING (6)
+#define STM_MODE_IT_FALLING (7)
+#define STM_MODE_IT_RISING_FALLING (8)
+#define STM_MODE_EVT_RISING (9)
+#define STM_MODE_EVT_FALLING (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET (12)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ USER_BUTTON = PC_13,
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
+ USBTX = PA_2,
+ USBRX = PA_3,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_4,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3,
+ PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PortNames.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortF = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,205 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+ADC_HandleTypeDef AdcHandle;
+
+int adc1_inited = 0;
+int adc2_inited = 0;
+int adc3_inited = 0;
+int adc4_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ // Get the peripheral name from the pin and assign it to the object
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_ADC);
+
+ // Save pin number for the read function
+ obj->pin = pin;
+
+ // The ADC initialization is done only once for each ADC
+ if ((adc1_inited == 0) || (adc2_inited == 0) || (adc3_inited == 0) || (adc4_inited == 0)) {
+ if (obj->adc == ADC_1) {
+ __ADC12_CLK_ENABLE();
+ adc1_inited = 1;
+ }
+ if (obj->adc == ADC_2) {
+ __ADC12_CLK_ENABLE();
+ adc2_inited = 1;
+ }
+ if (obj->adc == ADC_3) {
+ __ADC34_CLK_ENABLE();
+ adc3_inited = 1;
+ }
+ if (obj->adc == ADC_4) {
+ __ADC34_CLK_ENABLE();
+ adc4_inited = 1;
+ }
+ // Configure ADC
+ AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+ AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2;
+ AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
+ AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ AdcHandle.Init.ScanConvMode = DISABLE;
+ AdcHandle.Init.EOCSelection = DISABLE;
+ AdcHandle.Init.LowPowerAutoWait = DISABLE;
+ AdcHandle.Init.ContinuousConvMode = DISABLE;
+ AdcHandle.Init.NbrOfConversion = 1;
+ AdcHandle.Init.DiscontinuousConvMode = DISABLE;
+ AdcHandle.Init.NbrOfDiscConversion = 0;
+ AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
+ AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ AdcHandle.Init.DMAContinuousRequests = DISABLE;
+ AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN;
+ HAL_ADC_Init(&AdcHandle);
+ }
+}
+
+static inline uint16_t adc_read(analogin_t *obj)
+{
+ ADC_ChannelConfTypeDef sConfig;
+
+ AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+
+ // Configure ADC channel
+ sConfig.Rank = ADC_REGULAR_RANK_1;
+ sConfig.SamplingTime = ADC_SAMPLETIME_19CYCLES_5;
+ sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ sConfig.Offset = 0;
+
+ switch (obj->pin) {
+ case PA_0:
+ sConfig.Channel = ADC_CHANNEL_1;
+ break;
+ case PA_1:
+ sConfig.Channel = ADC_CHANNEL_2;
+ break;
+ case PA_2:
+ sConfig.Channel = ADC_CHANNEL_3;
+ break;
+ case PA_3:
+ sConfig.Channel = ADC_CHANNEL_4;
+ break;
+ case PA_4:
+ sConfig.Channel = ADC_CHANNEL_1;
+ break;
+ case PA_5:
+ sConfig.Channel = ADC_CHANNEL_2;
+ break;
+ case PA_6:
+ sConfig.Channel = ADC_CHANNEL_3;
+ break;
+ case PA_7:
+ sConfig.Channel = ADC_CHANNEL_4;
+ break;
+ case PB_0:
+ sConfig.Channel = ADC_CHANNEL_12;
+ break;
+ case PB_1:
+ sConfig.Channel = ADC_CHANNEL_1;
+ break;
+ case PB_2:
+ sConfig.Channel = ADC_CHANNEL_12;
+ break;
+ case PB_11:
+ sConfig.Channel = ADC_CHANNEL_14;
+ break;
+ case PB_12:
+ sConfig.Channel = ADC_CHANNEL_3;
+ break;
+ case PB_13:
+ sConfig.Channel = ADC_CHANNEL_5;
+ break;
+ case PB_14:
+ sConfig.Channel = ADC_CHANNEL_4;
+ break;
+ case PB_15:
+ sConfig.Channel = ADC_CHANNEL_5;
+ break;
+ case PC_0:
+ sConfig.Channel = ADC_CHANNEL_6;
+ break;
+ case PC_1:
+ sConfig.Channel = ADC_CHANNEL_7;
+ break;
+ case PC_2:
+ sConfig.Channel = ADC_CHANNEL_8;
+ break;
+ case PC_3:
+ sConfig.Channel = ADC_CHANNEL_9;
+ break;
+ case PC_4:
+ sConfig.Channel = ADC_CHANNEL_5;
+ break;
+ case PC_5:
+ sConfig.Channel = ADC_CHANNEL_11;
+ break;
+ default:
+ return 0;
+ }
+
+ HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+
+ HAL_ADC_Start(&AdcHandle); // Start conversion
+
+ // Wait end of conversion and get value
+ if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&AdcHandle));
+ } else {
+ return 0;
+ }
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ uint16_t value = adc_read(obj);
+ // 12-bit to 16-bit conversion
+ value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
+ return value;
+}
+
+float analogin_read(analogin_t *obj)
+{
+ uint16_t value = adc_read(obj);
+ return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogout_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,153 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogout_api.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+#define DAC_RANGE (0xFFF) // 12 bits
+
+static DAC_HandleTypeDef DacHandle;
+
+// These variables are used for the "free" function
+static int pa4_used = 0;
+static int pa5_used = 0;
+
+void analogout_init(dac_t *obj, PinName pin)
+{
+ DAC_ChannelConfTypeDef sConfig;
+
+ // Get the peripheral name from the pin and assign it to the object
+ obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+ MBED_ASSERT(obj->dac != (DACName)NC);
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_DAC);
+
+ // Save the pin for future use
+ obj->pin = pin;
+
+ // Enable DAC clock
+ __DAC1_CLK_ENABLE();
+
+ // Configure DAC
+ DacHandle.Instance = (DAC_TypeDef *)(obj->dac);
+
+ sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
+
+ if (pin == PA_4) {
+ HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1);
+ pa4_used = 1;
+ }
+
+ if (pin == PA_5) {
+ HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2);
+ pa5_used = 1;
+ }
+
+ analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj)
+{
+ // Reset DAC and disable clock
+ if (obj->pin == PA_4) pa4_used = 0;
+ if (obj->pin == PA_5) pa5_used = 0;
+
+ if ((pa4_used == 0) && (pa5_used == 0)) {
+ __DAC1_FORCE_RESET();
+ __DAC1_RELEASE_RESET();
+ __DAC1_CLK_DISABLE();
+ }
+
+ // Configure GPIO
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+static inline void dac_write(dac_t *obj, uint16_t value)
+{
+ if (obj->pin == PA_4) {
+ HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value);
+ HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1);
+ }
+
+ if (obj->pin == PA_5) {
+ HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value);
+ HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2);
+ }
+}
+
+static inline int dac_read(dac_t *obj)
+{
+ if (obj->pin == PA_4) {
+ return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1);
+ } else if (obj->pin == PA_5) {
+ return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2);
+ } else {
+ return 0;
+ }
+}
+
+void analogout_write(dac_t *obj, float value)
+{
+ if (value < 0.0f) {
+ dac_write(obj, 0); // Min value
+ } else if (value > 1.0f) {
+ dac_write(obj, (uint16_t)DAC_RANGE); // Max value
+ } else {
+ dac_write(obj, (uint16_t)(value * (float)DAC_RANGE));
+ }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value)
+{
+ if (value > (uint16_t)DAC_RANGE) {
+ dac_write(obj, (uint16_t)DAC_RANGE); // Max value
+ } else {
+ dac_write(obj, value);
+ }
+}
+
+float analogout_read(dac_t *obj)
+{
+ uint32_t value = dac_read(obj);
+ return (float)((float)value * (1.0f / (float)DAC_RANGE));
+}
+
+uint16_t analogout_read_u16(dac_t *obj)
+{
+ return (uint16_t)dac_read(obj);
+}
+
+#endif // DEVICE_ANALOGOUT
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/device.h Tue Dec 02 15:45:09 2014 +0000 @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+uint32_t gpio_set(PinName pin)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+
+ pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+ return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ obj->pin = pin;
+ if (pin == (PinName)NC) {
+ return;
+ }
+
+ uint32_t port_index = STM_PORT(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Fill GPIO object structure for future use
+ obj->mask = gpio_set(pin);
+ obj->reg_in = &gpio->IDR;
+ obj->reg_set = &gpio->BSRRL;
+ obj->reg_clr = &gpio->BSRRH;
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (direction == PIN_OUTPUT) {
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+ } else { // PIN_INPUT
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_irq_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,332 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define EDGE_NONE (0)
+#define EDGE_RISE (1)
+#define EDGE_FALL (2)
+#define EDGE_BOTH (3)
+
+// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15)
+#define CHANNEL_NUM (7)
+
+// Max pins for one line (max with EXTI10_15)
+#define MAX_PIN_LINE (6)
+
+typedef struct gpio_channel {
+ uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
+ uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
+ uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
+ uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
+} gpio_channel_t;
+
+static gpio_channel_t channels[CHANNEL_NUM] = {
+ {.pin_mask = 0},
+ {.pin_mask = 0},
+ {.pin_mask = 0},
+ {.pin_mask = 0},
+ {.pin_mask = 0},
+ {.pin_mask = 0},
+ {.pin_mask = 0}
+};
+
+// Used to return the index for channels array.
+static uint32_t pin_base_nr[16] = {
+ // EXTI0
+ 0, // pin 0
+ // EXTI1
+ 0, // pin 1
+ // EXTI2
+ 0, // pin 2
+ // EXTI3
+ 0, // pin 3
+ // EXTI4
+ 0, // pin 4
+ // EXTI5_9
+ 0, // pin 5
+ 1, // pin 6
+ 2, // pin 7
+ 3, // pin 8
+ 4, // pin 9
+ // EXTI10_15
+ 0, // pin 10
+ 1, // pin 11
+ 2, // pin 12
+ 3, // pin 13
+ 4, // pin 14
+ 5 // pin 15
+};
+
+static gpio_irq_handler irq_handler;
+
+static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
+{
+ gpio_channel_t *gpio_channel = &channels[irq_index];
+ uint32_t gpio_idx;
+
+ for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
+ uint32_t current_mask = (1 << gpio_idx);
+
+ if (gpio_channel->pin_mask & current_mask) {
+ // Retrieve the gpio and pin that generate the irq
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
+ uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
+
+ // Clear interrupt flag
+ if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
+ __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
+
+ if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
+
+ // Check which edge has generated the irq
+ if ((gpio->IDR & pin) == 0) {
+ irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
+ } else {
+ irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
+ }
+ }
+ }
+ }
+}
+
+// EXTI line 0
+static void gpio_irq0(void)
+{
+ handle_interrupt_in(0, 1);
+}
+
+// EXTI line 1
+static void gpio_irq1(void)
+{
+ handle_interrupt_in(1, 1);
+}
+
+// EXTI line 2
+static void gpio_irq2(void)
+{
+ handle_interrupt_in(2, 1);
+}
+
+// EXTI line 3
+static void gpio_irq3(void)
+{
+ handle_interrupt_in(3, 1);
+}
+
+// EXTI line 4
+static void gpio_irq4(void)
+{
+ handle_interrupt_in(4, 1);
+}
+
+// EXTI lines 5 to 9
+static void gpio_irq5(void)
+{
+ handle_interrupt_in(5, 5);
+}
+
+// EXTI lines 10 to 15
+static void gpio_irq6(void)
+{
+ handle_interrupt_in(6, 6);
+}
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ uint32_t irq_index;
+ gpio_channel_t *gpio_channel;
+ uint32_t gpio_idx;
+
+ if (pin == NC) return -1;
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Select irq number and interrupt routine
+ switch (pin_index) {
+ case 0:
+ irq_n = EXTI0_IRQn;
+ vector = (uint32_t)&gpio_irq0;
+ irq_index = 0;
+ break;
+ case 1:
+ irq_n = EXTI1_IRQn;
+ vector = (uint32_t)&gpio_irq1;
+ irq_index = 1;
+ break;
+ case 2:
+ irq_n = EXTI2_TSC_IRQn;
+ vector = (uint32_t)&gpio_irq2;
+ irq_index = 2;
+ break;
+ case 3:
+ irq_n = EXTI3_IRQn;
+ vector = (uint32_t)&gpio_irq3;
+ irq_index = 3;
+ break;
+ case 4:
+ irq_n = EXTI4_IRQn;
+ vector = (uint32_t)&gpio_irq4;
+ irq_index = 4;
+ break;
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ irq_n = EXTI9_5_IRQn;
+ vector = (uint32_t)&gpio_irq5;
+ irq_index = 5;
+ break;
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ irq_n = EXTI15_10_IRQn;
+ vector = (uint32_t)&gpio_irq6;
+ irq_index = 6;
+ break;
+ default:
+ error("InterruptIn error: pin not supported.\n");
+ return -1;
+ }
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+
+ // Configure GPIO
+ pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
+
+ // Enable EXTI interrupt
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ // Save informations for future use
+ obj->irq_n = irq_n;
+ obj->irq_index = irq_index;
+ obj->event = EDGE_NONE;
+ obj->pin = pin;
+
+ gpio_channel = &channels[irq_index];
+ gpio_idx = pin_base_nr[pin_index];
+ gpio_channel->pin_mask |= (1 << gpio_idx);
+ gpio_channel->channel_ids[gpio_idx] = id;
+ gpio_channel->channel_gpio[gpio_idx] = gpio_add;
+ gpio_channel->channel_pin[gpio_idx] = pin_index;
+
+ irq_handler = handler;
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ gpio_channel_t *gpio_channel = &channels[obj->irq_index];
+ uint32_t pin_index = STM_PIN(obj->pin);
+ uint32_t gpio_idx = pin_base_nr[pin_index];
+
+ gpio_channel->pin_mask &= ~(1 << gpio_idx);
+ gpio_channel->channel_ids[gpio_idx] = 0;
+ gpio_channel->channel_gpio[gpio_idx] = 0;
+ gpio_channel->channel_pin[gpio_idx] = 0;
+
+ // Disable EXTI line
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ obj->event = EDGE_NONE;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ uint32_t mode = STM_MODE_IT_EVT_RESET;
+ uint32_t pull = GPIO_NOPULL;
+
+ if (enable) {
+ if (event == IRQ_RISE) {
+ if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_RISING_FALLING;
+ obj->event = EDGE_BOTH;
+ } else { // NONE or RISE
+ mode = STM_MODE_IT_RISING;
+ obj->event = EDGE_RISE;
+ }
+ }
+ if (event == IRQ_FALL) {
+ if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_RISING_FALLING;
+ obj->event = EDGE_BOTH;
+ } else { // NONE or FALL
+ mode = STM_MODE_IT_FALLING;
+ obj->event = EDGE_FALL;
+ }
+ }
+ } else { // Disable
+ if (event == IRQ_RISE) {
+ if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_FALLING;
+ obj->event = EDGE_FALL;
+ } else { // NONE or RISE
+ mode = STM_MODE_IT_EVT_RESET;
+ obj->event = EDGE_NONE;
+ }
+ }
+ if (event == IRQ_FALL) {
+ if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_RISING;
+ obj->event = EDGE_RISE;
+ } else { // NONE or FALL
+ mode = STM_MODE_IT_EVT_RESET;
+ obj->event = EDGE_NONE;
+ }
+ }
+ }
+
+ pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ NVIC_EnableIRQ(obj->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ NVIC_DisableIRQ(obj->irq_n);
+ obj->event = EDGE_NONE;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ __IO uint32_t *reg_in;
+ __IO uint16_t *reg_set;
+ __IO uint16_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value) {
+ *obj->reg_set = obj->mask;
+ } else {
+ *obj->reg_clr = obj->mask;
+ }
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/i2c_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,442 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+/* Timeout values for flags and events waiting loops. These timeouts are
+ not based on accurate values, they just guarantee that the application will
+ not remain stuck if the I2C communication is corrupted. */
+#define FLAG_TIMEOUT ((int)0x4000)
+#define LONG_TIMEOUT ((int)0x8000)
+
+I2C_HandleTypeDef I2cHandle;
+
+int i2c1_inited = 0;
+int i2c2_inited = 0;
+int i2c3_inited = 0;
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+ // Determine the I2C to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+
+ obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT(obj->i2c != (I2CName)NC);
+
+ // Enable I2C clock and pinout if not done
+ if ((obj->i2c == I2C_1) && !i2c1_inited) {
+ i2c1_inited = 1;
+ __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK);
+ __I2C1_CLK_ENABLE();
+ // Configure I2C1 pins
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(sda, OpenDrain);
+ pin_mode(scl, OpenDrain);
+ }
+
+ if ((obj->i2c == I2C_2) && !i2c2_inited) {
+ i2c2_inited = 1;
+ __I2C2_CLK_ENABLE();
+ // Configure I2C2 pins
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(sda, OpenDrain);
+ pin_mode(scl, OpenDrain);
+ }
+
+ if ((obj->i2c == I2C_3) && !i2c3_inited) {
+ i2c3_inited = 1;
+ __I2C3_CLK_ENABLE();
+ // Configure I2C3 pins
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(sda, OpenDrain);
+ pin_mode(scl, OpenDrain);
+ }
+
+ // Reset to clear pending flags if any
+ i2c_reset(obj);
+
+ // I2C configuration
+ i2c_frequency(obj, 100000); // 100 kHz per default
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ uint32_t tim = 0;
+
+ MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
+
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ // wait before init
+ timeout = LONG_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
+
+ // Update the SystemCoreClock variable.
+ SystemCoreClockUpdate();
+
+ /*
+ Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235)
+ * Standard mode (up to 100 kHz)
+ * Fast Mode (up to 400 kHz)
+ * Fast Mode Plus (up to 1 MHz)
+ Below values obtained with:
+ - I2C clock source = 64 MHz (System Clock w/ HSI) or 72 (System Clock w/ HSE)
+ - Analog filter delay = ON
+ - Digital filter coefficient = 0
+ */
+ if (SystemCoreClock == 64000000) {
+ switch (hz) {
+ case 100000:
+ tim = 0x10B17DB4; // Standard mode with Rise time = 120ns, Fall time = 120ns
+ break;
+ case 400000:
+ tim = 0x00E22163; // Fast Mode with Rise time = 120ns, Fall time = 120ns
+ break;
+ case 1000000:
+ tim = 0x00A00D1E; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns
+ break;
+ default:
+ break;
+ }
+ } else if (SystemCoreClock == 72000000) {
+ switch (hz) {
+ case 100000:
+ tim = 0x10D28DCB; // Standard mode with Rise time = 120ns, Fall time = 120ns
+ break;
+ case 400000:
+ tim = 0x00F32571; // Fast Mode with Rise time = 120ns, Fall time = 120ns
+ break;
+ case 1000000:
+ tim = 0x00C00D24; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns
+ break;
+ default:
+ break;
+ }
+ }
+
+ // Enable the Fast Mode Plus capability
+ if (hz == 1000000) {
+ if (obj->i2c == I2C_1) {
+ __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1);
+ }
+ if (obj->i2c == I2C_2) {
+ __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C2);
+ }
+ if (obj->i2c == I2C_3) {
+ __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C3);
+ }
+ }
+
+ // I2C configuration
+ I2cHandle.Init.Timing = tim;
+ I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;
+ I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;
+ I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED;
+ I2cHandle.Init.OwnAddress1 = 0;
+ I2cHandle.Init.OwnAddress2 = 0;
+ I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ HAL_I2C_Init(&I2cHandle);
+}
+
+inline int i2c_start(i2c_t *obj)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+ // Clear Acknowledge failure flag
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
+
+ // Generate the START condition
+ i2c->CR2 |= I2C_CR2_START;
+
+ // Wait the START condition has been correctly sent
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) {
+ if ((timeout--) == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+inline int i2c_stop(i2c_t *obj)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+
+ // Generate the STOP condition
+ i2c->CR2 |= I2C_CR2_STOP;
+
+ return 0;
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+ int count;
+ int value;
+
+ /* update CR2 register */
+ i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)))
+ | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ);
+
+ // Read all bytes
+ for (count = 0; count < length; count++) {
+ value = i2c_byte_read(obj, 0);
+ data[count] = (char)value;
+ }
+
+ // Wait transfer complete
+ timeout = LONG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ /* Wait until STOPF flag is set */
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+ int count;
+
+ /* update CR2 register */
+ i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)))
+ | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE);
+
+ for (count = 0; count < length; count++) {
+ i2c_byte_write(obj, data[count]);
+ }
+
+ // Wait transfer complete
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ /* Wait until STOPF flag is set */
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF);
+ }
+
+ return count;
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ // Wait until the byte is received
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
+ if ((timeout--) == 0) {
+ return -1;
+ }
+ }
+
+ return (int)i2c->RXDR;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ // Wait until the previous byte is transmitted
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) {
+ if ((timeout--) == 0) {
+ return 0;
+ }
+ }
+
+ i2c->TXDR = (uint8_t)data;
+
+ return 1;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+ int timeout;
+
+ // wait before reset
+ timeout = LONG_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
+
+ __I2C1_FORCE_RESET();
+ __I2C1_RELEASE_RESET();
+}
+
+#if DEVICE_I2CSLAVE
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint16_t tmpreg;
+
+ // disable
+ i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN);
+ // Get the old register value
+ tmpreg = i2c->OAR1;
+ // Reset address bits
+ tmpreg &= 0xFC00;
+ // Set new address
+ tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
+ // Store the new register value
+ i2c->OAR1 = tmpreg;
+ // enable
+ i2c->OAR1 |= I2C_OAR1_OA1EN;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint16_t tmpreg;
+
+ // Get the old register value
+ tmpreg = i2c->OAR1;
+
+ // Enable / disable slave
+ if (enable_slave == 1) {
+ tmpreg |= I2C_OAR1_OA1EN;
+ } else {
+ tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN);
+ }
+
+ // Set new mode
+ i2c->OAR1 = tmpreg;
+
+}
+
+// See I2CSlave.h
+#define NoData 0 // the slave has not been addressed
+#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral 2 // the master is writing to all slave
+#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
+
+int i2c_slave_receive(i2c_t *obj)
+{
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int retValue = NoData;
+
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) {
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) {
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1)
+ retValue = ReadAddressed;
+ else
+ retValue = WriteAddressed;
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR);
+ }
+ }
+
+ return (retValue);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+ char size = 0;
+
+ while (size < length) data[size++] = (char)i2c_byte_read(obj, 0);
+
+ return size;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+ char size = 0;
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+ do {
+ i2c_byte_write(obj, data[size]);
+ size++;
+ } while (size < length);
+
+ return size;
+}
+
+
+#endif // DEVICE_I2CSLAVE
+
+#endif // DEVICE_I2C
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/mbed_overrides.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "cmsis.h"
+
+// This function is called after RAM initialization and before main.
+void mbed_sdk_init()
+{
+ // Update the SystemCoreClock variable.
+ SystemCoreClockUpdate();
+ // Need to restart HAL driver after the RAM is initialized
+ HAL_Init();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/objects.h Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct dac_s {
+ DACName dac;
+ PinName pin;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+ PinName pin_tx;
+ PinName pin_rx;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
+};
+
+struct i2c_s {
+ I2CName i2c;
+ uint32_t slave;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/pinmap.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+
+// GPIO mode look-up table
+// Warning: the elements order must be the same as the one defined in PinNames.h
+static const uint32_t gpio_mode[13] = {
+ GPIO_MODE_INPUT, // 0 = STM_MODE_INPUT
+ GPIO_MODE_OUTPUT_PP, // 1 = STM_MODE_OUTPUT_PP
+ GPIO_MODE_OUTPUT_OD, // 2 = STM_MODE_OUTPUT_OD
+ GPIO_MODE_AF_PP, // 3 = STM_MODE_AF_PP
+ GPIO_MODE_AF_OD, // 4 = STM_MODE_AF_OD
+ GPIO_MODE_ANALOG, // 5 = STM_MODE_ANALOG
+ GPIO_MODE_IT_RISING, // 6 = STM_MODE_IT_RISING
+ GPIO_MODE_IT_FALLING, // 7 = STM_MODE_IT_FALLING
+ GPIO_MODE_IT_RISING_FALLING, // 8 = STM_MODE_IT_RISING_FALLING
+ GPIO_MODE_EVT_RISING, // 9 = STM_MODE_EVT_RISING
+ GPIO_MODE_EVT_FALLING, // 10 = STM_MODE_EVT_FALLING
+ GPIO_MODE_EVT_RISING_FALLING, // 11 = STM_MODE_EVT_RISING_FALLING
+ 0x10000000 // 12 = STM_MODE_IT_EVT_RESET (not in STM32Cube HAL)
+};
+
+// Enable GPIO clock and return GPIO base address
+uint32_t Set_GPIO_Clock(uint32_t port_idx)
+{
+ uint32_t gpio_add = 0;
+ switch (port_idx) {
+ case PortA:
+ gpio_add = GPIOA_BASE;
+ __GPIOA_CLK_ENABLE();
+ break;
+ case PortB:
+ gpio_add = GPIOB_BASE;
+ __GPIOB_CLK_ENABLE();
+ break;
+ case PortC:
+ gpio_add = GPIOC_BASE;
+ __GPIOC_CLK_ENABLE();
+ break;
+ case PortD:
+ gpio_add = GPIOD_BASE;
+ __GPIOD_CLK_ENABLE();
+ break;
+ case PortF:
+ gpio_add = GPIOF_BASE;
+ __GPIOF_CLK_ENABLE();
+ break;
+ default:
+ error("Pinmap error: wrong port number.");
+ break;
+ }
+ return gpio_add;
+}
+
+/**
+ * Configure pin (mode, speed, output type and pull-up/pull-down)
+ */
+void pin_function(PinName pin, int data)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ // Get the pin informations
+ uint32_t mode = STM_PIN_MODE(data);
+ uint32_t pupd = STM_PIN_PUPD(data);
+ uint32_t afnum = STM_PIN_AFNUM(data);
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Configure GPIO
+ GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index);
+ GPIO_InitStructure.Mode = gpio_mode[mode];
+ GPIO_InitStructure.Pull = pupd;
+ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
+ GPIO_InitStructure.Alternate = afnum;
+ HAL_GPIO_Init(gpio, &GPIO_InitStructure);
+
+ // [TODO] Disconnect JTAG-DP + SW-DP signals.
+ // Warning: Need to reconnect under reset
+ //if ((pin == PA_13) || (pin == PA_14)) {
+ //
+ //}
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Configure pull-up/pull-down resistors
+ uint32_t pupd = (uint32_t)mode;
+ if (pupd > 2) {
+ pupd = 0; // Open-drain = No pull-up/No pull-down
+ }
+ gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2)));
+ gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2));
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/port_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
+// low nibble = pin number
+PinName port_pin(PortName port, int pin_n)
+{
+ return (PinName)(pin_n + (port << 4));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+ uint32_t port_index = (uint32_t)port;
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Fill PORT object structure for future use
+ obj->port = port;
+ obj->mask = mask;
+ obj->direction = dir;
+ obj->reg_in = &gpio->IDR;
+ obj->reg_out = &gpio->ODR;
+
+ port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+ uint32_t i;
+ obj->direction = dir;
+ for (i = 0; i < 16; i++) { // Process all pins
+ if (obj->mask & (1 << i)) { // If the pin is used
+ if (dir == PIN_OUTPUT) {
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+ } else { // PIN_INPUT
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ }
+ }
+ }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+ uint32_t i;
+ for (i = 0; i < 16; i++) { // Process all pins
+ if (obj->mask & (1 << i)) { // If the pin is used
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_write(port_t *obj, int value)
+{
+ *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj)
+{
+ if (obj->direction == PIN_OUTPUT) {
+ return (*obj->reg_out & obj->mask);
+ } else { // PIN_INPUT
+ return (*obj->reg_in & obj->mask);
+ }
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/pwmout_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,246 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+static TIM_HandleTypeDef TimHandle;
+
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+ // Get the peripheral name from the pin and assign it to the object
+ obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+
+ if (obj->pwm == (PWMName)NC) {
+ error("PWM error: pinout mapping failed.");
+ }
+
+ // Enable TIM clock
+ if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE();
+ if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE();
+ if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
+ if (obj->pwm == PWM_8) __TIM8_CLK_ENABLE();
+ if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE();
+ if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE();
+ if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE();
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_PWM);
+
+ obj->pin = pin;
+ obj->period = 0;
+ obj->pulse = 0;
+
+ pwmout_period_us(obj, 20000); // 20 ms per default
+}
+
+void pwmout_free(pwmout_t* obj)
+{
+ // Configure GPIO
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void pwmout_write(pwmout_t* obj, float value)
+{
+ TIM_OC_InitTypeDef sConfig;
+ int channel = 0;
+ int complementary_channel = 0;
+
+ TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
+ if (value < (float)0.0) {
+ value = 0.0;
+ } else if (value > (float)1.0) {
+ value = 1.0;
+ }
+
+ obj->pulse = (uint32_t)((float)obj->period * value);
+
+ // Configure channels
+ sConfig.OCMode = TIM_OCMODE_PWM1;
+ sConfig.Pulse = obj->pulse;
+ sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
+ sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ sConfig.OCFastMode = TIM_OCFAST_DISABLE;
+ sConfig.OCIdleState = TIM_OCIDLESTATE_RESET;
+ sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+
+ switch (obj->pin) {
+
+ // Channels 1
+ case PA_2:
+ case PA_6:
+ case PA_7:
+ case PA_8:
+ case PA_12:
+ case PA_15:
+ case PB_4:
+ case PB_5:
+ case PB_8:
+ case PB_9:
+ case PB_14:
+ case PC_0:
+ case PC_6:
+ channel = TIM_CHANNEL_1;
+ break;
+
+ // Channels 1N
+ case PA_1:
+ case PA_13:
+ case PB_3:
+ case PB_6:
+ case PB_7:
+ case PB_13:
+ case PC_10:
+ case PC_13:
+ channel = TIM_CHANNEL_1;
+ complementary_channel = 1;
+ break;
+
+ // Channels 2
+ case PA_3:
+ case PA_4:
+ case PA_9:
+ case PA_14:
+ case PB_15:
+ case PC_1:
+ case PC_7:
+ channel = TIM_CHANNEL_2;
+ break;
+
+ // Channels 2N
+ case PB_0:
+ case PC_11:
+ channel = TIM_CHANNEL_2;
+ complementary_channel = 1;
+ break;
+
+ // Channels 3
+ case PA_10:
+ case PC_2:
+ case PC_8:
+ channel = TIM_CHANNEL_3;
+ break;
+
+ // Channels 3N
+ case PB_1:
+ case PC_12:
+ case PF_0:
+ channel = TIM_CHANNEL_3;
+ complementary_channel = 1;
+ break;
+
+ // Channels 4
+ case PA_11:
+ case PC_3:
+ case PC_9:
+ channel = TIM_CHANNEL_4;
+ break;
+
+ default:
+ return;
+ }
+
+ HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel);
+
+ if (complementary_channel) {
+ HAL_TIMEx_PWMN_Start(&TimHandle, channel);
+ } else {
+ HAL_TIM_PWM_Start(&TimHandle, channel);
+ }
+}
+
+float pwmout_read(pwmout_t* obj)
+{
+ float value = 0;
+ if (obj->period > 0) {
+ value = (float)(obj->pulse) / (float)(obj->period);
+ }
+ return ((value > (float)1.0) ? (float)(1.0) : (value));
+}
+
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+ pwmout_period_us(obj, ms * 1000);
+}
+
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+ TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
+ float dc = pwmout_read(obj);
+
+ __HAL_TIM_DISABLE(&TimHandle);
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ TimHandle.Init.Period = us - 1;
+ TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TimHandle.Init.ClockDivision = 0;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ HAL_TIM_PWM_Init(&TimHandle);
+
+ // Set duty cycle again
+ pwmout_write(obj, dc);
+
+ // Save for future use
+ obj->period = us;
+
+ __HAL_TIM_ENABLE(&TimHandle);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+ float value = (float)us / (float)obj->period;
+ pwmout_write(obj, value);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/rtc_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,201 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "mbed_error.h"
+
+static int rtc_inited = 0;
+
+static RTC_HandleTypeDef RtcHandle;
+
+void rtc_init(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ uint32_t rtc_freq = 0;
+
+ if (rtc_inited) return;
+ rtc_inited = 1;
+
+ RtcHandle.Instance = RTC;
+
+ // Enable Power clock
+ __PWR_CLK_ENABLE();
+
+ // Enable access to Backup domain
+ HAL_PWR_EnableBkUpAccess();
+
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ // Enable LSE Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+ // Connect LSE to RTC
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+ rtc_freq = LSE_VALUE;
+ } else {
+ // Enable LSI clock
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("RTC error: LSI clock initialization failed.");
+ }
+ // Connect LSI to RTC
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+ // Note: The LSI clock can be measured precisely using a timer input capture.
+ rtc_freq = LSI_VALUE;
+ }
+
+ // Enable RTC
+ __HAL_RCC_RTC_ENABLE();
+
+ RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
+ RtcHandle.Init.AsynchPrediv = 127;
+ RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1;
+ RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+
+ if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+ error("RTC error: RTC initialization failed.");
+ }
+}
+
+void rtc_free(void)
+{
+ // Enable Power clock
+ __PWR_CLK_ENABLE();
+
+ // Enable access to Backup domain
+ HAL_PWR_EnableBkUpAccess();
+
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ // Disable access to Backup domain
+ HAL_PWR_DisableBkUpAccess();
+
+ // Disable LSI and LSE clocks
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ rtc_inited = 0;
+}
+
+int rtc_isenabled(void)
+{
+ return rtc_inited;
+}
+
+/*
+ RTC Registers
+ RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
+ RTC_Month 1=january, 2=february, ..., 12=december
+ RTC_Date day of the month 1-31
+ RTC_Year year 0-99
+ struct tm
+ tm_sec seconds after the minute 0-61
+ tm_min minutes after the hour 0-59
+ tm_hour hours since midnight 0-23
+ tm_mday day of the month 1-31
+ tm_mon months since January 0-11
+ tm_year years since 1900
+ tm_wday days since Sunday 0-6
+ tm_yday days since January 1 0-365
+ tm_isdst Daylight Saving Time flag
+*/
+time_t rtc_read(void)
+{
+ RTC_DateTypeDef dateStruct;
+ RTC_TimeTypeDef timeStruct;
+ struct tm timeinfo;
+
+ RtcHandle.Instance = RTC;
+
+ // Read actual date and time
+ // Warning: the time must be read first!
+ HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+ HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+
+ // Setup a tm structure based on the RTC
+ timeinfo.tm_wday = dateStruct.WeekDay;
+ timeinfo.tm_mon = dateStruct.Month - 1;
+ timeinfo.tm_mday = dateStruct.Date;
+ timeinfo.tm_year = dateStruct.Year + 100;
+ timeinfo.tm_hour = timeStruct.Hours;
+ timeinfo.tm_min = timeStruct.Minutes;
+ timeinfo.tm_sec = timeStruct.Seconds;
+
+ // Convert to timestamp
+ time_t t = mktime(&timeinfo);
+
+ return t;
+}
+
+void rtc_write(time_t t)
+{
+ RTC_DateTypeDef dateStruct;
+ RTC_TimeTypeDef timeStruct;
+
+ RtcHandle.Instance = RTC;
+
+ // Convert the time into a tm
+ struct tm *timeinfo = localtime(&t);
+
+ // Fill RTC structures
+ dateStruct.WeekDay = timeinfo->tm_wday;
+ dateStruct.Month = timeinfo->tm_mon + 1;
+ dateStruct.Date = timeinfo->tm_mday;
+ dateStruct.Year = timeinfo->tm_year - 100;
+ timeStruct.Hours = timeinfo->tm_hour;
+ timeStruct.Minutes = timeinfo->tm_min;
+ timeStruct.Seconds = timeinfo->tm_sec;
+ timeStruct.TimeFormat = RTC_HOURFORMAT12_PM;
+ timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+ timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
+
+ // Change the RTC current date/time
+ HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+ HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/serial_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,392 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include <string.h>
+#include "PeripheralPins.h"
+
+#define UART_NUM (3)
+
+static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0};
+
+static uart_irq_handler irq_handler;
+
+UART_HandleTypeDef UartHandle;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+static void init_uart(serial_t *obj)
+{
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+ UartHandle.Init.BaudRate = obj->baudrate;
+ UartHandle.Init.WordLength = obj->databits;
+ UartHandle.Init.StopBits = obj->stopbits;
+ UartHandle.Init.Parity = obj->parity;
+ UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+
+ if (obj->pin_rx == NC) {
+ UartHandle.Init.Mode = UART_MODE_TX;
+ } else if (obj->pin_tx == NC) {
+ UartHandle.Init.Mode = UART_MODE_RX;
+ } else {
+ UartHandle.Init.Mode = UART_MODE_TX_RX;
+ }
+
+ // Disable the reception overrun detection
+ UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT;
+ UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+
+ HAL_UART_Init(&UartHandle);
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+ // Determine the UART to use (UART_1, UART_2, ...)
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+
+ // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+ obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ MBED_ASSERT(obj->uart != (UARTName)NC);
+
+ // Enable USART clock + switch to SystemClock
+ if (obj->uart == UART_1) {
+ __USART1_CLK_ENABLE();
+ __HAL_RCC_USART1_CONFIG(RCC_USART1CLKSOURCE_SYSCLK);
+ obj->index = 0;
+ }
+ if (obj->uart == UART_2) {
+ __USART2_CLK_ENABLE();
+ __HAL_RCC_USART2_CONFIG(RCC_USART2CLKSOURCE_SYSCLK);
+ obj->index = 1;
+ }
+ if (obj->uart == UART_3) {
+ __USART3_CLK_ENABLE();
+ __HAL_RCC_USART3_CONFIG(RCC_USART3CLKSOURCE_SYSCLK);
+ obj->index = 2;
+ }
+ if (obj->uart == UART_4) {
+ __UART4_CLK_ENABLE();
+ __HAL_RCC_UART4_CONFIG(RCC_UART4CLKSOURCE_SYSCLK);
+ obj->index = 3;
+ }
+ if (obj->uart == UART_5) {
+ __UART5_CLK_ENABLE();
+ __HAL_RCC_UART5_CONFIG(RCC_UART5CLKSOURCE_SYSCLK);
+ obj->index = 4;
+ }
+
+ // Configure the UART pins
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+ if (tx != NC) {
+ pin_mode(tx, PullUp);
+ }
+ if (rx != NC) {
+ pin_mode(rx, PullUp);
+ }
+
+ // Configure UART
+ obj->baudrate = 9600;
+ obj->databits = UART_WORDLENGTH_8B;
+ obj->stopbits = UART_STOPBITS_1;
+ obj->parity = UART_PARITY_NONE;
+
+ obj->pin_tx = tx;
+ obj->pin_rx = rx;
+
+ init_uart(obj);
+
+ // For stdio management
+ if (obj->uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj)
+{
+ // Reset UART and disable clock
+ if (obj->uart == UART_1) {
+ __USART1_FORCE_RESET();
+ __USART1_RELEASE_RESET();
+ __USART1_CLK_DISABLE();
+ }
+ if (obj->uart == UART_2) {
+ __USART2_FORCE_RESET();
+ __USART2_RELEASE_RESET();
+ __USART2_CLK_DISABLE();
+ }
+ if (obj->uart == UART_3) {
+ __USART3_FORCE_RESET();
+ __USART3_RELEASE_RESET();
+ __USART3_CLK_DISABLE();
+ }
+ if (obj->uart == UART_4) {
+ __UART4_FORCE_RESET();
+ __UART4_RELEASE_RESET();
+ __UART4_CLK_DISABLE();
+ }
+ if (obj->uart == UART_5) {
+ __UART5_FORCE_RESET();
+ __UART5_RELEASE_RESET();
+ __UART5_CLK_DISABLE();
+ }
+
+ // Configure GPIOs
+ pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+ serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+ obj->baudrate = baudrate;
+ init_uart(obj);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ if (data_bits == 9) {
+ obj->databits = UART_WORDLENGTH_9B;
+ } else {
+ obj->databits = UART_WORDLENGTH_8B;
+ }
+
+ switch (parity) {
+ case ParityOdd:
+ case ParityForced0:
+ obj->parity = UART_PARITY_ODD;
+ break;
+ case ParityEven:
+ case ParityForced1:
+ obj->parity = UART_PARITY_EVEN;
+ break;
+ default: // ParityNone
+ obj->parity = UART_PARITY_NONE;
+ break;
+ }
+
+ if (stop_bits == 2) {
+ obj->stopbits = UART_STOPBITS_2;
+ } else {
+ obj->stopbits = UART_STOPBITS_1;
+ }
+
+ init_uart(obj);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_irq(UARTName name, int id)
+{
+ UartHandle.Instance = (USART_TypeDef *)name;
+ if (serial_irq_ids[id] != 0) {
+ if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
+ irq_handler(serial_irq_ids[id], TxIrq);
+ __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC);
+ }
+ if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
+ irq_handler(serial_irq_ids[id], RxIrq);
+ volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit
+ }
+ }
+}
+
+static void uart1_irq(void)
+{
+ uart_irq(UART_1, 0);
+}
+
+static void uart2_irq(void)
+{
+ uart_irq(UART_2, 1);
+}
+
+static void uart3_irq(void)
+{
+ uart_irq(UART_3, 2);
+}
+
+static void uart4_irq(void)
+{
+ uart_irq(UART_4, 3);
+}
+
+static void uart5_irq(void)
+{
+ uart_irq(UART_5, 4);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+ if (obj->uart == UART_1) {
+ irq_n = USART1_IRQn;
+ vector = (uint32_t)&uart1_irq;
+ }
+
+ if (obj->uart == UART_2) {
+ irq_n = USART2_IRQn;
+ vector = (uint32_t)&uart2_irq;
+ }
+
+ if (obj->uart == UART_3) {
+ irq_n = USART3_IRQn;
+ vector = (uint32_t)&uart3_irq;
+ }
+
+ if (obj->uart == UART_4) {
+ irq_n = UART4_IRQn;
+ vector = (uint32_t)&uart4_irq;
+ }
+
+ if (obj->uart == UART_5) {
+ irq_n = UART5_IRQn;
+ vector = (uint32_t)&uart5_irq;
+ }
+
+ if (enable) {
+
+ if (irq == RxIrq) {
+ __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
+ } else { // TxIrq
+ __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
+ }
+
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ } else { // disable
+
+ int all_disabled = 0;
+
+ if (irq == RxIrq) {
+ __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
+ // Check if TxIrq is disabled too
+ if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1;
+ } else { // TxIrq
+ __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC);
+ // Check if RxIrq is disabled too
+ if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+ }
+
+ if (all_disabled) NVIC_DisableIRQ(irq_n);
+
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_getc(serial_t *obj)
+{
+ USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+ while (!serial_readable(obj));
+ if (obj->databits == UART_WORDLENGTH_8B) {
+ return (int)(uart->RDR & (uint8_t)0xFF);
+ } else {
+ return (int)(uart->RDR & (uint16_t)0x1FF);
+ }
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+ USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+ while (!serial_writable(obj));
+ if (obj->databits == UART_WORDLENGTH_8B) {
+ uart->TDR = (uint8_t)(c & (uint8_t)0xFF);
+ } else {
+ uart->TDR = (uint16_t)(c & (uint16_t)0x1FF);
+ }
+}
+
+int serial_readable(serial_t *obj)
+{
+ int status;
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+ // Check if data is received
+ status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
+ return status;
+}
+
+int serial_writable(serial_t *obj)
+{
+ int status;
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+ // Check if data is transmitted
+ status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
+ return status;
+}
+
+void serial_clear(serial_t *obj)
+{
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+ __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC);
+ __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST);
+}
+
+void serial_pinout_tx(PinName tx)
+{
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+ HAL_LIN_SendBreak(&UartHandle);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/sleep.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "sleep_api.h"
+
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
+
+static TIM_HandleTypeDef TimMasterHandle;
+
+void sleep(void)
+{
+ TimMasterHandle.Instance = TIM2;
+
+ // Disable HAL tick interrupt
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+ // Request to enter SLEEP mode
+ HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+
+ // Enable HAL tick interrupt
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+}
+
+void deepsleep(void)
+{
+ // Request to enter STOP mode with regulator in low power mode
+ HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+
+ // After wake-up from STOP reconfigure the PLL
+ SetSysClock();
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/spi_api.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,329 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include <math.h>
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+static SPI_HandleTypeDef SpiHandle;
+
+static void init_spi(spi_t *obj)
+{
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+
+ __HAL_SPI_DISABLE(&SpiHandle);
+
+ SpiHandle.Init.Mode = obj->mode;
+ SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
+ SpiHandle.Init.Direction = SPI_DIRECTION_2LINES;
+ SpiHandle.Init.CLKPhase = obj->cpha;
+ SpiHandle.Init.CLKPolarity = obj->cpol;
+ SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
+ SpiHandle.Init.CRCPolynomial = 7;
+ SpiHandle.Init.DataSize = obj->bits;
+ SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
+ SpiHandle.Init.NSS = obj->nss;
+ SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
+
+ HAL_SPI_Init(&SpiHandle);
+
+ __HAL_SPI_ENABLE(&SpiHandle);
+}
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+ // Determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+ obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+ MBED_ASSERT(obj->spi != (SPIName)NC);
+
+ // Enable SPI clock
+ if (obj->spi == SPI_1) {
+ __SPI1_CLK_ENABLE();
+ }
+
+ if (obj->spi == SPI_2) {
+ __SPI2_CLK_ENABLE();
+ }
+
+ if (obj->spi == SPI_3) {
+ __SPI3_CLK_ENABLE();
+ }
+
+ // Configure the SPI pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+
+ // Save new values
+ obj->bits = SPI_DATASIZE_8BIT;
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_1EDGE;
+ obj->br_presc = SPI_BAUDRATEPRESCALER_32;
+
+ obj->pin_miso = miso;
+ obj->pin_mosi = mosi;
+ obj->pin_sclk = sclk;
+ obj->pin_ssel = ssel;
+
+ if (ssel == NC) { // SW NSS Master mode
+ obj->mode = SPI_MODE_MASTER;
+ obj->nss = SPI_NSS_SOFT;
+ } else { // Slave
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ obj->mode = SPI_MODE_SLAVE;
+ obj->nss = SPI_NSS_HARD_INPUT;
+ }
+
+ init_spi(obj);
+}
+
+void spi_free(spi_t *obj)
+{
+ // Reset SPI and disable clock
+ if (obj->spi == SPI_1) {
+ __SPI1_FORCE_RESET();
+ __SPI1_RELEASE_RESET();
+ __SPI1_CLK_DISABLE();
+ }
+
+ if (obj->spi == SPI_2) {
+ __SPI2_FORCE_RESET();
+ __SPI2_RELEASE_RESET();
+ __SPI2_CLK_DISABLE();
+ }
+
+ if (obj->spi == SPI_3) {
+ __SPI3_FORCE_RESET();
+ __SPI3_RELEASE_RESET();
+ __SPI3_CLK_DISABLE();
+ }
+
+ // Configure GPIOs
+ pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ // Save new values
+ if (bits == 16) {
+ obj->bits = SPI_DATASIZE_16BIT;
+ } else {
+ obj->bits = SPI_DATASIZE_8BIT;
+ }
+
+ switch (mode) {
+ case 0:
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_1EDGE;
+ break;
+ case 1:
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_2EDGE;
+ break;
+ case 2:
+ obj->cpol = SPI_POLARITY_HIGH;
+ obj->cpha = SPI_PHASE_1EDGE;
+ break;
+ default:
+ obj->cpol = SPI_POLARITY_HIGH;
+ obj->cpha = SPI_PHASE_2EDGE;
+ break;
+ }
+
+ if (slave == 0) {
+ obj->mode = SPI_MODE_MASTER;
+ obj->nss = SPI_NSS_SOFT;
+ } else {
+ obj->mode = SPI_MODE_SLAVE;
+ obj->nss = SPI_NSS_HARD_INPUT;
+ }
+
+ init_spi(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+ // Values depend of APB1CLK and APB2CLK : 32 MHz if HSI is used, 36 MHz if HSE is used
+ if (obj->spi == SPI_1) {
+ if (hz < 500000) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 250 kHz - 280 kHz
+ } else if ((hz >= 500000) && (hz < 1000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 500 kHz - 560 kHz
+ } else if ((hz >= 1000000) && (hz < 2000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1 MHz - 1.13 MHz
+ } else if ((hz >= 2000000) && (hz < 4000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2 MHz - 2.25 MHz
+ } else if ((hz >= 4000000) && (hz < 8000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 4 MHz - 4.5 MHz
+ } else if ((hz >= 8000000) && (hz < 16000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 8 MHz - 9 MHz
+ } else if ((hz >= 16000000) && (hz < 32000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 16 MHz - 18 MHz
+ } else { // >= 32000000
+ obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 32 MHz - 36 MHz
+ }
+ } else {
+ if (hz < 250000) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz - 141 kHz
+ } else if ((hz >= 250000) && (hz < 500000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz - 280 kHz
+ } else if ((hz >= 500000) && (hz < 1000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz - 560 kHz
+ } else if ((hz >= 1000000) && (hz < 2000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz - 1.13 MHz
+ } else if ((hz >= 2000000) && (hz < 4000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz - 2.25 MHz
+ } else if ((hz >= 4000000) && (hz < 8000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz - 4.5 MHz
+ } else if ((hz >= 8000000) && (hz < 16000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz - 9 MHz
+ } else { // >= 16000000
+ obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz - 18 MHz
+ }
+ }
+
+ init_spi(obj);
+}
+
+static inline int ssp_readable(spi_t *obj)
+{
+ int status;
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+ // Check if data is received
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
+ return status;
+}
+
+static inline int ssp_writeable(spi_t *obj)
+{
+ int status;
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+ // Check if data is transmitted
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
+ return status;
+}
+
+static inline void ssp_write(spi_t *obj, int value)
+{
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_writeable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ *p_spi_dr = (uint8_t)value;
+ } else { // SPI_DATASIZE_16BIT
+ spi->DR = (uint16_t)value;
+ }
+}
+
+static inline int ssp_read(spi_t *obj)
+{
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_readable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ return (int)(*p_spi_dr);
+ } else {
+ return (int)spi->DR;
+ }
+}
+
+static inline int ssp_busy(spi_t *obj)
+{
+ int status;
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
+ return status;
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+ return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_readable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ return (int)(*p_spi_dr);
+ } else {
+ return (int)spi->DR;
+ }
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_writeable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ *p_spi_dr = (uint8_t)value;
+ } else { // SPI_DATASIZE_16BIT
+ spi->DR = (uint16_t)value;
+ }
+}
+
+int spi_busy(spi_t *obj)
+{
+ return ssp_busy(obj);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/us_ticker.c Tue Dec 02 15:45:09 2014 +0000
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+// 32-bit timer selection
+#define TIM_MST TIM2
+
+static TIM_HandleTypeDef TimMasterHandle;
+static int us_ticker_inited = 0;
+
+void us_ticker_init(void)
+{
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ TimMasterHandle.Instance = TIM_MST;
+
+ HAL_InitTick(0); // The passed value is not used
+}
+
+uint32_t us_ticker_read()
+{
+ if (!us_ticker_inited) us_ticker_init();
+ return TIM_MST->CNT;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ // Set new output compare value
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp);
+ // Enable IT
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+}